WO2022105890A1 - 一种输出可调的电压偏置电路、芯片及通信终端 - Google Patents

一种输出可调的电压偏置电路、芯片及通信终端 Download PDF

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Publication number
WO2022105890A1
WO2022105890A1 PCT/CN2021/131898 CN2021131898W WO2022105890A1 WO 2022105890 A1 WO2022105890 A1 WO 2022105890A1 CN 2021131898 W CN2021131898 W CN 2021131898W WO 2022105890 A1 WO2022105890 A1 WO 2022105890A1
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Prior art keywords
voltage
transmission gate
pmos transistor
gate switch
output
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PCT/CN2021/131898
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English (en)
French (fr)
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高晨阳
林升
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唯捷创芯(天津)电子技术股份有限公司
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Priority to EP21894037.7A priority Critical patent/EP4250054A1/en
Publication of WO2022105890A1 publication Critical patent/WO2022105890A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown

Definitions

  • the invention relates to a voltage bias circuit with adjustable output, and also relates to an integrated circuit chip including the voltage bias circuit and a corresponding communication terminal, belonging to the technical field of integrated circuits.
  • the bias circuit responsible for providing the DC operating point for the RF front-end module bears the brunt, especially the Heterojunction Bipolar Transistor (HBT) RF bias circuit.
  • HBT Heterojunction Bipolar Transistor
  • Bandgap voltage reference circuit bandgap voltage reference circuit, referred to as bandgap
  • low dropout linear regulator low dropout regulator
  • the flexibility of their output voltage determines the RF front-end Flexibility of modules (mainly power amplifiers). It can be said that the more flexible the output voltage of the bandgap voltage reference circuit and the low dropout linear regulator is, the easier it is for the RF front-end module to achieve better performance, and the more the communication terminal can adapt to the complex application environment.
  • the output voltage of the existing bandgap voltage reference circuit and the low dropout linear regulator is single, and it is impossible to achieve an output voltage of any temperature coefficient and any value on the same circuit module. Their low flexibility leads to the development and debugging of the RF front-end module and the communication terminal. Apps face limitations.
  • the primary technical problem to be solved by the present invention is to provide a voltage bias circuit with adjustable output.
  • Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the above-mentioned voltage bias circuit and a corresponding communication terminal.
  • the present invention adopts the following technical scheme:
  • an output adjustable voltage bias circuit including a bandgap voltage reference unit, a low dropout linear voltage regulator unit, a first transmission gate switch unit, a logic coding control unit and a second a transmission gate switch unit; the bandgap voltage reference unit is connected to the low dropout linear voltage regulator unit through the first transmission gate switch unit, and the low dropout linear voltage regulator unit is connected to the second transmission gate switch unit, so the logic coding control unit is connected to the first transmission gate switch unit and the second transmission gate switch unit;
  • the logic coding control unit is used to control the first transmission gate switch unit to select a voltage with a required value and temperature coefficient from a plurality of voltages with different temperature coefficients and different values generated by the bandgap voltage reference unit, and output the voltage to the
  • the low dropout linear voltage regulator unit is used as its input reference voltage; at the same time, the logic coding control unit controls the second transmission gate switch unit to select the corresponding The required gain coefficient is obtained, and a negative feedback closed-loop system is formed by the low dropout linear voltage regulator unit, so that the voltage of the gain coefficient feedback node is approximately equal to the input reference voltage, thereby outputting the voltage with the required value and temperature coefficient.
  • the bandgap voltage reference unit includes an operational amplifier, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first resistor, a first bipolar transistor, a second bipolar transistor, a Three bipolar transistors and a resistor divider network; the non-inverting input end of the operational amplifier is connected to the drain of the first PMOS transistor and one end of the first resistor, and the other end of the first resistor is connected to the first resistor
  • the emitter of a bipolar transistor, the inverting input terminal of the operational amplifier is connected to the drain of the second PMOS transistor and the emitter of the second bipolar transistor, and the output terminal of the operational amplifier is connected to the The gates of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor, the drain of the third PMOS transistor is connected to one end of the resistor divider network, and the other end of the resistor divider network One end is connected to the emitter of the third bipolar transistor, the output end of the resistor divider network is
  • the resistor divider network is composed of a plurality of second resistors connected in series; different resistor nodes of the resistor divider network output voltages with different temperature coefficients and different values correspondingly.
  • the low-dropout linear voltage regulator unit includes an error amplifier, a power tube and a feedback resistor network; the non-inverting input end of the error amplifier is connected to the first transmission gate switch unit, and the inverting phase of the error amplifier is connected to the first transmission gate switch unit.
  • the input end is connected to the feedback resistor network through the second transmission gate switch unit, the output end of the error amplifier is connected to the gate of the power transistor, the drain of the power transistor is connected to one end of the feedback resistor network, The other end of the feedback resistor network is grounded, and the source of the power transistor is connected to the power supply voltage.
  • the feedback resistor network is composed of a plurality of third resistors connected in series; each of the resistor feedback nodes outputs different gain coefficients correspondingly.
  • the logic coding control unit is a binary coding circuit composed of a NOT gate circuit and an AND gate circuit.
  • the first transmission gate switch unit includes a plurality of first transmission gate switches, the first transmission gate switches include a tenth PMOS transistor, a seventh NMOS transistor and a first inverter, and the first transmission gate switch includes a tenth PMOS transistor, a seventh NMOS transistor and a first inverter.
  • the source of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor as the input end of the first transmission gate switch, which is used to connect the resistance node corresponding to the resistor divider network; the drain of the tenth PMOS transistor is connected to The source of the seventh NMOS transistor is used as the output end of the first transmission gate switch to connect to the non-inverting input end of the error amplifier; the gate of the seventh NMOS transistor is connected to the logic coding control unit The corresponding output end and the input end of the first inverter, and the output end of the first inverter is connected to the gate of the tenth PMOS transistor.
  • the second transmission gate switch unit includes a plurality of second transmission gate switches, and the second transmission gate switches include an eleventh PMOS transistor, an eighth NMOS transistor and a second inverter.
  • the source of the eleventh PMOS transistor is connected to the drain of the eighth NMOS transistor as the input end of the second transmission gate switch, which is used to connect the resistance feedback node corresponding to the feedback resistor network;
  • the eleventh PMOS transistor The drain is connected to the source of the eighth NMOS transistor as the output end of the second transmission gate switch for connecting to the inverting input end of the error amplifier;
  • the gate of the eighth NMOS transistor is connected to the logic The corresponding output end of the coding control unit and the input end of the second inverter, and the output end of the second inverter is connected to the gate of the eleventh PMOS transistor.
  • an integrated circuit chip is provided, and the integrated circuit chip includes the above-mentioned voltage bias circuit.
  • a communication terminal including the above-mentioned voltage bias circuit.
  • the output-adjustable voltage bias circuit provided by the present invention generates a plurality of different temperature coefficients, different value voltage and different gain coefficients; use the logic coding control unit to control the corresponding transmission gate switch unit to select the input reference voltage and the required gain coefficient of the required value and temperature coefficient to output the voltage of the required value and temperature coefficient, Provide a suitable bias state for the RF front-end module, so that the RF front-end module can achieve better performance and make the communication terminal have better flexibility and adaptability in complex environments.
  • Figure 1 is a schematic diagram of a typical voltage bias circuit
  • FIG. 2 is a schematic diagram of a voltage bias circuit with adjustable output provided by an embodiment of the present invention
  • FIG. 3 is a circuit schematic diagram of a bandgap voltage reference unit in an output-adjustable voltage bias circuit provided by an embodiment of the present invention
  • FIG. 4 is a circuit schematic diagram of an error amplifier in an output-adjustable voltage bias circuit provided by an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a 3-8 coding circuit in a logic coding control unit in an output-adjustable voltage bias circuit provided by an embodiment of the present invention
  • FIG. 6 is a circuit schematic diagram of a first transmission gate switch unit in an output-adjustable voltage bias circuit provided by an embodiment of the present invention
  • FIG. 7 is a circuit schematic diagram of a second transmission gate switch unit in an output-adjustable voltage bias circuit provided by an embodiment of the present invention.
  • a typical voltage bias circuit is composed of a bandgap voltage reference unit 101 and a low dropout linear voltage regulator unit 102 .
  • the function of the bandgap voltage reference unit is to generate a reference voltage Vref with zero temperature coefficient and not affected by the power supply voltage, and then provide it to the low dropout linear voltage regulator unit 102 as an input reference voltage.
  • the low dropout linear voltage regulator unit 102 is composed of an error amplifier 201 , a power transistor 202 and a feedback resistor network 203 .
  • the feedback resistor network 203 consists of a resistor Rf1 and a resistor Rf2.
  • the output voltage Vout is expressed as in the formula It can be called the gain coefficient, and its size is determined by the proportional relationship between the resistance Rf1 and the resistance Rf2.
  • the output voltage Vout is jointly determined by the reference voltage Vref of the bandgap voltage reference unit 101 and the gain coefficient of the low dropout linear voltage regulator unit 102 .
  • the RF front-end module can achieve better performance, communication terminal
  • the embodiment of the present invention provides a voltage bias circuit with adjustable output, which is used to provide voltages with different temperature coefficients and different values for the radio frequency front-end module. As shown in FIG.
  • the voltage bias circuit includes a bandgap voltage reference unit 301, a low dropout linear voltage regulator unit 302, a first transmission gate switch unit 303, a logic code control unit 304 and a second transmission gate switch unit 306;
  • the gap voltage reference unit 301 and the low dropout linear voltage regulator unit 302 are connected to the power supply voltage VDD, the bandgap voltage reference unit 301 is connected to the low dropout linear voltage regulator unit 302 through the first transmission gate switch unit 303, and the low dropout linear voltage regulator unit 302 is connected to the first transmission gate switch unit 303.
  • Two transmission gate switch units 306 , and the logic coding control unit 304 is connected to the first transmission gate switch unit 303 and the second transmission gate switch unit 306 .
  • the logic coding control unit 304 is used to control the first transmission gate switch unit 303 to select a voltage with a desired value and temperature coefficient from a plurality of voltages with different temperature coefficients and different values generated by the bandgap voltage reference unit 301, and output the voltage to the low dropout linear
  • the voltage regulator unit 302 is used as its input reference voltage; at the same time, the logic code control unit 304 controls the second transmission gate switch unit 306 to select the corresponding required gain coefficient from the multiple gain coefficients of the low dropout linear voltage regulator unit 302, and pass
  • the low dropout linear voltage regulator unit 302 constitutes a negative feedback closed-loop system, and realizes that the voltage of the gain coefficient feedback node is approximately equal to the input reference voltage, thereby outputting the voltage of the required value and temperature coefficient, and providing a suitable bias state for the RF front-end module, so that the RF The front-end module achieves better performance, and the communication terminal is better used in complex environments.
  • the bandgap voltage reference unit 301 is used to generate a plurality of voltages with different temperature coefficients and different values. The number of voltages with different temperature coefficients and different values generated by the bandgap voltage reference unit 301 is adjusted according to the number actually required by the radio frequency front-end module. As shown in FIG. 3 , the bandgap voltage reference unit 301 includes an operational amplifier A1, a first PMOS transistor 701, a second PMOS transistor 702, a third PMOS transistor 703, a first resistor R1, a first bipolar transistor 706, a second Bipolar transistor 707 , third bipolar transistor 708 and resistor divider network 709 .
  • the non-inverting input end of the operational amplifier A1 is connected to the drain of the first PMOS transistor 701 and one end of the first resistor R1, the other end of the first resistor R1 is connected to the emitter of the first bipolar transistor 706, and the inverting input of the operational amplifier A1
  • the terminal is connected to the drain of the second PMOS transistor 702 and the emitter of the second bipolar transistor 707, and the output terminal of the operational amplifier A1 is connected to the gates of the first PMOS transistor 701, the second PMOS transistor 702 and the third PMOS transistor 703,
  • the drain of the third PMOS transistor 703 is connected to one end of the resistor divider network 709, the other end of the resistor divider network 709 is connected to the emitter of the third bipolar transistor 708, and the output end of the resistor divider network 709 is connected to the first transmission gate Switch unit 303, the sources of the first PMOS transistor 701, the second PMOS transistor 702 and the third PMOS transistor 703 are connected to the power supply voltage VDD,
  • the resistor divider network 709 is composed of a plurality of second resistors (resistors R2_A, R2_B, R2_C... R2_N) in series; the resistor divider is used to generate multiple voltages (Vref1 , Vref2...Vrefn), that is, different resistance nodes of the resistance voltage divider network 709 correspondingly output voltages with different temperature coefficients and different values.
  • the logic coding control unit 304 to control the on-off state of the first transmission gate switch unit 303, it is possible to select a voltage with a desired value and a temperature coefficient from a plurality of voltages with different temperature coefficients and different values generated by the resistor divider network 709, These different voltages are provided to the low dropout linear voltage regulator unit 302 as input reference voltages, so as to realize the diversity of input reference voltages.
  • the size of the second resistance ratio in the resistor divider network 709 determines the adjustable accuracy of the output voltage of this output-adjustable voltage bias circuit, and a resistor with an appropriate ratio can be designed according to the voltage value accuracy and voltage temperature coefficient accuracy required by the application Voltage divider network 709.
  • the first PMOS transistor 701 , the second PMOS transistor 702 and the third PMOS transistor 703 form a current mirror, and the width to length ratio of the first PMOS transistor 701 and the second PMOS transistor 702 are the same, so the flow through the first PMOS transistor 701 and the second PMOS transistor 702
  • the low dropout linear voltage regulator unit 302 includes an error amplifier 401, a power tube 402 and a feedback resistor network 403; the non-inverting input terminal of the error amplifier 401 is connected to the first transmission gate switch unit 303, and the inverting The input terminal is connected to the feedback resistor network 403 through the second transmission gate switch unit 306, the output terminal of the error amplifier 401 is connected to the gate of the power tube 402, the drain of the power tube 402 is connected to one end of the feedback resistor network 403, and the other end of the feedback resistor network 403 is connected. One end is grounded, and the source of the power transistor 402 is connected to the power supply voltage VDD.
  • the feedback resistor network 403 is composed of a plurality of third resistors (Rf2_A, Rf2_B, Rf2_C...Rf2_H) in series; different resistance feedback nodes (Vfb_A, Vfb_B, Vfb_C...Vfb_H) in the feedback resistor network 403 correspond different gain factors.
  • the error amplifier 401, the power tube 402 and the feedback resistor network 403 constitute a negative feedback closed-loop system, so that the voltages of the non-inverting input terminal and the inverting input terminal of the error amplifier 401 are approximately equal, thereby realizing the input reference voltage node of the error amplifier 401 and the resistance feedback node ( That is, the gain factor feedback node) is clamped, that is, the voltage of the resistor feedback node is approximately equal to the input reference voltage.
  • a resistor feedback node is set between adjacent third resistors in the feedback resistor network 403 ; each resistor feedback node corresponds to different voltages, and each resistor feedback node outputs different gain coefficients to achieve diversity of gain coefficients.
  • the size of the third resistance ratio in the feedback resistor network 403 determines the adjustable precision of the output voltage gain coefficient of the output adjustable voltage bias circuit, and the feedback resistor network 403 with an appropriate ratio can be designed according to the gain coefficient of the voltage required by the application.
  • the error amplifier 401 includes a fourth PMOS transistor 601, a fifth PMOS transistor 602, a first NMOS transistor 603, a second NMOS transistor 604, a sixth PMOS transistor 605, a seventh PMOS transistor 606, and a third NMOS transistor 607, the fourth NMOS transistor 608, the fifth NMOS transistor 609, the sixth NMOS transistor 610, the eighth PMOS transistor 611 and the ninth PMOS transistor 612; the gate of the fourth PMOS transistor 601 is used as the non-inverting input terminal of the error amplifier 401, It is used to connect the first transmission gate switch unit 303, the gate of the fifth PMOS transistor 602 is used as the inverting input terminal of the error amplifier 401 to connect to the second transmission gate switch unit 306, and the drain of the fourth PMOS transistor 601 is connected to the first transmission gate switch unit 306.
  • the gate and drain of an NMOS transistor 603, the gate of the second NMOS transistor 604, the drain of the second NMOS transistor 604 is connected to the gate and drain of the sixth PMOS transistor 605, and the gate of the seventh PMOS transistor 606,
  • the drain of the seventh PMOS transistor 606 is used as the output terminal Vop of the error amplifier 401 to connect the gate of the power transistor 402 and the drain of the fourth NMOS transistor 608 , and the gate of the fourth NMOS transistor 608 is connected to the third NMOS transistor 607
  • the gate and drain of the fifth PMOS transistor 602, the source of the fifth PMOS transistor 602 is connected to the source of the fourth PMOS transistor 601, the drain of the ninth PMOS transistor 612, and the gate of the ninth PMOS transistor 612
  • the electrode is connected to the gate and drain of the eighth PMOS transistor 611 and the drain of the sixth NMOS transistor 610.
  • the gate of the sixth NMOS transistor 610 is connected to the gate and drain of the fifth NMOS transistor 609.
  • the drain is connected to the external bias voltage Ibias
  • the sources of the sixth PMOS transistor 605, the seventh PMOS transistor 606, the eighth PMOS transistor 611 and the ninth PMOS transistor 612 are all connected to the power supply voltage VDD
  • the sources of the NMOS transistor 604 , the third NMOS transistor 607 , the fourth NMOS transistor 608 , the fifth NMOS transistor 609 and the sixth NMOS transistor 610 are all grounded.
  • the fourth PMOS transistor 601 and the fifth PMOS transistor 602 are input amplification pair transistors, the first NMOS transistor 603 and the second NMOS transistor 604, the sixth PMOS transistor 605 and the seventh PMOS transistor 606 , the third NMOS transistor 607 and the fourth NMOS transistor 608 , the fifth NMOS transistor 609 and the sixth NMOS transistor 610 , and the eighth PMOS transistor 611 and the ninth PMOS transistor 612 respectively constitute mirror current mirrors.
  • the bias current Ibias is mirrored by the fifth NMOS transistor 609 and the sixth NMOS transistor 610 and the eighth PMOS transistor 611 and the ninth PMOS transistor 612 to provide current bias for the fourth PMOS transistor 601 and the fifth PMOS transistor 602 .
  • the fourth PMOS transistor 601 receives the voltage with the required value and temperature coefficient provided by the bandgap voltage reference unit 301 as the reference input voltage of the low dropout linear voltage regulator unit, and the fifth PMOS transistor 602 receives the feedback resistor network 403 to provide the required gain
  • the resistance feedback node corresponding to the coefficient is mirrored by the first NMOS transistor 603 and the second NMOS transistor 604 , the sixth PMOS transistor 605 and the seventh PMOS transistor 606 , the third NMOS transistor 607 and the fourth NMOS transistor 608 .
  • error amplifier 401 is an operational amplifier with a current mirror load.
  • the error amplifier, power tube and feedback resistor network of the low-dropout linear voltage regulator unit form a negative feedback closed-loop system, which makes the voltages of the non-inverting input terminal and the inverting input terminal of the error amplifier approximately equal, thereby realizing the clamping of the input reference voltage node and the resistance feedback node. bit, that is, the voltage at the resistive feedback node is approximately equal to the input reference voltage.
  • the logic code control unit 304 uses a few less logic control bits to generate various logic combinations to control the first transmission gate switch unit 303 and the second transmission gate switch unit 306 to select different input reference voltages and different gain coefficients, And then realize a variety of different voltage combinations.
  • the logic coding control unit 304 may be a binary coding circuit composed of a NOT gate circuit and an AND gate circuit; for example, the logic coding control unit 304 may be a binary coding circuit such as a 2-4 coding circuit, a 3-8 coding circuit, a 4-16 coding circuit, etc. circuit.
  • the number of logic control bits of the logic code control unit 304 is determined by the type of voltage required to be output and the method of logic code.
  • the number of control levels generated by the logic coding control unit 304 is determined by the number of voltages of temperature coefficient and numerical value required by the RF front-end module.
  • the logic control bits Reg0 ⁇ 2>, Reg0 ⁇ 1>, and Reg0 ⁇ 0> first pass through the NOT gate circuits in turn to obtain the level Reg0 ⁇ 2>_Bar and Reg0 ⁇ 2>_Buf, Reg0 ⁇ 1>_Bar and Reg0 ⁇ 1>_Buf, Reg0 ⁇ 0>_Bar and Reg0 ⁇ 0>_Buf. Then, these levels are logically combined to obtain a control level through a three-input AND gate circuit.
  • Reg0 ⁇ 2:0> corresponds to a control level
  • Reg0 ⁇ 2:0> 000; 001; ...; 111 sequentially corresponds to the output control levels VC_0; VC_1; ...; VC_7.
  • the first transmission gate switch unit 303 includes a plurality of first transmission gate switches, and the number of the first transmission gate switches is the same as the number of voltages with different values and different temperature coefficients generated by the resistor divider network 709 , and corresponds one-to-one. Different resistance nodes of the resistor divider network 709 are correspondingly connected to a plurality of first transmission gate switches, so that each fixed value and fixed temperature coefficient voltage output by the resistor divider network 709 corresponds to one first transmission gate switch.
  • each first transmission gate switch includes a tenth PMOS transistor, a seventh NMOS transistor and a first inverter, and the source of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor as a first transmission gate
  • the input end of the switch is used to connect the resistance node corresponding to the resistor divider network 709; the drain of the tenth PMOS transistor is connected to the source of the seventh NMOS transistor as the output end of the first transmission gate switch, which is used to connect the positive pole of the error amplifier 401.
  • Phase input terminal; the gate of the seventh NMOS transistor is connected to the corresponding output terminal of the logic coding control unit 304 and the input terminal of the first inverter, and the output terminal of the first inverter is connected to the gate of the tenth PMOS transistor.
  • PMOS transistor M30, NMOS transistor M29 and first inverter J15 correspondingly constitutes a plurality of first transmission gate switches.
  • the on and off of the MOS tube corresponds to the on and off of the control branch, so as to realize the one-to-one correspondence between the logic combination and the voltage obtained by the resistance division of the bandgap voltage reference unit 301, and then realize the one-to-one correspondence between the logic combination and the output voltage , to ensure that a logic corresponds to a voltage that determines the value and determines the temperature coefficient.
  • the voltages Vref1, Vref2...Vrefn are controlled by the first transmission gate switch unit 303 to output a voltage Vref with a determined value and a determined temperature coefficient to the low dropout linear voltage regulator unit 302 as its input reference voltage.
  • the control levels VC_0; VC_1; . . . ; VC_7 output by the logic coding control unit 304 are used as enable signals to sequentially control the turn-on and turn-off of the corresponding first transmission gate switches.
  • the control level VC_0 as an example, when the control level VC_0 is high, the PMOS transistor M1 and the NMOS transistor M2 are turned on, so that the first transmission gate switch is turned on, and the voltage Vref_1 is transmitted to the output end of the first transmission gate switch, It outputs a voltage Vref with a fixed value and a fixed temperature coefficient to the low dropout linear voltage regulator unit 302 as its input reference voltage.
  • each logic combination corresponds to a control level
  • each control level corresponds to a voltage that controls a certain value and a temperature coefficient.
  • the second transmission gate switch unit 306 includes a plurality of second transmission gate switches, and the number of the second transmission gate switches is the same as the number of voltages with different values and different temperature coefficients generated by the resistor divider network 709 .
  • Different resistance feedback nodes in the feedback resistance network 403 are correspondingly connected to a plurality of second transmission gate switches, so that the voltage of each gain coefficient output by the feedback resistance network 403 corresponds to one second transmission gate switch.
  • each second transmission gate switch includes an eleventh PMOS transistor, an eighth NMOS transistor and a second inverter, and the source of the eleventh PMOS transistor is connected to the drain of the eighth NMOS transistor as the second
  • the input terminal of the transmission gate switch is used to connect the resistance feedback node corresponding to the feedback resistor network 403; the drain of the eleventh PMOS transistor is connected to the source of the eighth NMOS transistor as the output terminal of the second transmission gate switch, which is used to connect to the error amplifier
  • the inverting input terminal of 401; the gate of the eighth NMOS transistor is connected to the output terminal corresponding to the logic coding control unit 304 and the input terminal of the second inverter, and the output terminal of the second inverter is connected to the gate of the eleventh PMOS transistor.
  • PMOS transistor M31, NMOS transistor M32 and second inverter J30 correspondingly constitutes a plurality of second transmission gate switches.
  • the turn-on and turn-off of the MOS tube corresponds to the turn-on and turn-off of the control branch, so as to achieve a one-to-one correspondence between the logic combination and the gain coefficient obtained by the resistance of the feedback resistor network 403, and then achieve a one-to-one correspondence between the logic combination and the output voltage, ensuring that Each logic corresponds to a fixed gain factor.
  • the control levels VC_0; VC_1; . . . ; VC_7 output by the logic coding control unit 304 are used as enable signals to sequentially control the turn-on and turn-off of the corresponding second transmission gate switches.
  • the control level VC_0 as an example, when the control level VC_0 is high, the PMOS transistor M3 and the NMOS transistor M4 are turned on, so that the second transmission gate switch is turned on, and the voltage transmission of a certain gain coefficient output by the resistance feedback node Vfb_A To the output end of the second transmission gate switch, it outputs a voltage Vfb with a fixed gain factor to the low dropout linear voltage regulator unit 302 .
  • each logic combination corresponds to a control level
  • each control level corresponds to a voltage that controls a fixed value and a fixed temperature coefficient.
  • the control levels VC_0; VC_1; . . . ; VC_7 output by the logic coding control unit 304 are correspondingly selected and controlled to control the corresponding resistance node and resistance feedback node to control the first transmission gate
  • the switch unit 303 selects the required input reference voltage, and at the same time, the control level also controls the second transmission gate switch unit 306 to select the required corresponding gain coefficient, the two are combined together and output through the low dropout linear voltage regulator unit 102
  • the value and temperature coefficient of the voltage required by the RF front-end module Different logic combinations correspond to voltages with different values and temperature coefficients.
  • the output adjustable voltage bias circuit provided in the embodiment of the present invention can be used in an integrated circuit chip.
  • the specific structure of the output-adjustable voltage bias circuit in the integrated circuit chip will not be described in detail here.
  • the above-mentioned output-adjustable voltage bias circuit can also be used in a communication terminal as an important part of a radio frequency integrated circuit.
  • the communication terminal mentioned here refers to the computer equipment that can be used in the mobile environment and supports various communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, etc., including mobile phones, notebook computers, tablet computers, car computers, etc.
  • the technical solutions provided by the present invention are also applicable to other radio frequency integrated circuit applications, such as communication base stations and the like.
  • the output-adjustable voltage bias circuit provided by the present invention generates a plurality of different temperature coefficients and different numerical values by correspondingly setting a resistor divider network and a feedback resistor network in the bandgap voltage reference unit and the low dropout linear voltage regulator unit. voltage and different gain coefficients; use the logic coding control unit to control the corresponding transmission gate switch unit to select the input reference voltage with the required value and temperature coefficient and the required gain coefficient to output the voltage with the required value and temperature coefficient, which is
  • the RF front-end module provides a suitable bias state, so that the RF front-end module can achieve better performance and make the communication terminal have better flexibility and adaptability in complex environments.

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Abstract

本发明提供了一种输出可调的电压偏置电路、芯片及通信终端。该偏置电路包括带隙电压基准单元、低压差线性稳压单元、第一传输门开关单元、逻辑编码控制单元和第二传输门开关单元。该偏置电路通过在带隙电压基准单元和低压差线性稳压单元中相应的设置电阻分压网络和反馈电阻网络，以生成多个不同温度系数、不同数值的电压和不同的增益系数；利用逻辑编码控制单元控制相应的传输门开关单元选择所需数值和温度系数的输入参考电压和所需的增益系数，以输出所需数值和温度系数的电压，为射频前端模块提供合适的偏置状态，以使射频前端模块实现更好的性能，并使通信终端在复杂环境下具有更好的灵活性和适应性。

Description

一种输出可调的电压偏置电路、芯片及通信终端 技术领域
本发明涉及一种输出可调的电压偏置电路，同时也涉及包括该电压偏置电路的集成电路芯片及相应的通信终端，属于集成电路技术领域。
背景技术
随着通信技术日新月异的发展，对通信终端的性能提出了更高的要求。对集成电路芯片而言，需要具有更高的灵活性，更强的适应性。负责为射频前端模块提供直流工作点的偏置电路首当其冲，尤其是异质结双极晶体管(Heterojunction Bipolar Transistor，简称为HBT)射频偏置电路。因为射频前端模块的性能与偏置电路的工作状态息息相关，又考虑到射频前端模块在研发和应用中需要反复调试，加上如今便携式通信终端(以手机、平板电脑为主)规模数量巨大，应用环境复杂，因此为射频前端模块提供一个高灵活性的直流工作点至关重要，否则新一代通信技术的发展会受到很大的限制。
带隙电压基准电路(bandgap voltage reference circuit，简称为bandgap)和低压差线性稳压器(low dropout regulator，简称为LDO)是常用的典型电压偏置电路，其输出电压的灵活性决定了射频前端模块(以功率放大器为主)的灵活性。可以说，带隙电压基准电路和低压差线性稳压器的输出电压越灵活，射频前端模块越容易实现更好的性能，通信终端越能适应复杂的应用环境。但是，现有带隙电压基准电路和低压差线性稳压器输出电压单一，无法在同一电路模块上实现任意温度系数、任意数值的输出电压，其低灵活性导致射频前端模块研发调试和通信终端应用面临限制。
发明内容
本发明所要解决的首要技术问题在于提供一种输出可调的电压偏置电路。
本发明所要解决的另一技术问题在于提供一种包括上述电压偏置电路的集成电路芯片及相应的通信终端。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种输出可调的电压偏置电路，包括带隙电压基准单元、低压差线性稳压单元、第一传输门开关单元、逻辑编码控制单元和第二传输门开关单元；所述带隙电压基准单元通过所述第一传输门开关单元连接所述低压差线性稳压单元，所述低压差线性稳压单元连接所述第二传输门开关单元，所述逻辑编码控制单元连接所述第一传输门开关单元和所述第二传输门开关单元；
利用所述逻辑编码控制单元控制所述第一传输门开关单元从所述带隙电压基准单元生成的多个不同温度系数、不同数值的电压中选取出所需数值和温度系数的电压，输出到所述低压差线性稳压单元作为其输入参考电压；同时，所述逻辑编码控制单元控制所述第二传输门开关单元从所述低压差线性稳压单元的多个增益系数中选取出对应所需的增益系数，并通过所述低压差线性稳压单元构成负反馈闭环系统，实现增益系数反馈节点的电压近似等于输入参考电压，从而输出所需数值和温度系数的电压。
其中较优地，所述带隙电压基准单元包括运算放大器、第一PMOS管、第二PMOS管、第三PMOS管、第一电阻、第一双极型晶体管、第二双极型晶体管、第三双极型晶体管和电阻分压网络；所述运算放大器的同相输入端连接所述第一PMOS管的漏极和所述第一电阻的一端，所述第一电阻的另一端连接所述第一双极型晶体管的发射极，所述运算放大器的反相输入端连接所述第二PMOS管的漏极和所述第二双极型晶体管的发射极，所述运算放大器的输出端连接所述第一PMOS管、所述第二PMOS管和所述第三PMOS管的栅极，所述第三PMOS管的漏极连接所述电阻分压网络的一端，所述电阻分压网络的另一端连接所述第三双极型晶体管的发射极，所述电阻分压网络的输出端连接所述第一传输门开关单元，所述第一PMOS管、所述第二PMOS管和所述第三PMOS管的源极连接电源电压,所述第一双极型晶体管、所述第二双极型晶体管、所述第三双极型晶体管的集电极接地。
其中较优地，所述电阻分压网络由多个第二电阻串联组成；所述电阻分压网络不同的电阻节点对应输出不同温度系数、不同数值的电压。
其中较优地，所述低压差线性稳压单元包括误差放大器、功率管和反馈电阻网络；所述误差放大器的正相输入端连接所述第一传输门开关单元，所述误差放大器的反相输入端通过所述第二传输门开关单元连接所述反馈电阻网络，所述误差放大器的输出端连接所述功率管的栅极，所述功率管的漏极连接所述反馈电阻网络的一端，所述反馈电阻网络的另一端接地，所述功率管的源极连接电源电压。
其中较优地，所述反馈电阻网络由多个第三电阻串联组成；每个所述电阻反馈节点对应输出不同的增益系数。
其中较优地，所述逻辑编码控制单元是由非门电路和与门电路构成的二进制编码电路。
其中较优地，所述第一传输门开关单元包括多个第一传输门开关，所述第一传输门开关包括一个第十PMOS管、第七NMOS管和第一反相器,所述第十PMOS管源极连接所述第七NMOS管的漏极作为所述第一传输门开关的输入端，用于连接所述电阻分压网络对应的电阻节点；所述第十PMOS管漏极连接所述第七NMOS管的源极作为所述第一传输门开关的输出端，用于连接所述误差放大器的正相输入端；所述第七NMOS管的栅极连接所述逻辑编码控制单元对应的输出端和所述第一反相器的输入端，所述第一反相器的输出端连接所述第十PMOS管的栅极。
其中较优地，所述第二传输门开关单元包括多个第二传输门开关，所述第二传输门开关包括一个第十一PMOS管、第八NMOS管和第二反相器,所述第十一PMOS管源极连接所述第八NMOS管的漏极作为所述第二传输门开关的输入端，用于连接所述反馈电阻网络对应的电阻反馈节点；所述第十一PMOS管漏极连接所述第八NMOS管的源极作为所述第二传输门开关的输出端，用于连接所述误差放大器的反相输入端；所述第八NMOS管的栅极连接所述逻辑编码控制单元对应的输出端和所述第二反相器的输入端，所述第二反相器的输出端连接所述第十一PMOS管的栅极。
根据本发明实施例的第二方面，提供一种集成电路芯片，所述集成电路芯片包括上述的电压偏置电路。
根据本发明实施例的第三方面，提供一种通信终端，所述通信终 端中包括上述的电压偏置电路。
本发明所提供的输出可调的电压偏置电路，通过在带隙电压基准单元和低压差线性稳压单元中相应的设置电阻分压网络和反馈电阻网络，以生成多个不同温度系数、不同数值的电压和不同的增益系数；利用逻辑编码控制单元控制相应的传输门开关单元选择所需数值和温度系数的输入参考电压和所需的增益系数，以输出所需数值和温度系数的电压，为射频前端模块提供合适的偏置状态，以使射频前端模块实现更好的性能，并使通信终端在复杂环境下具有更好的灵活性和适应性。
附图说明
图1为典型的电压偏置电路原理图；
图2为本发明实施例提供的输出可调的电压偏置电路原理图；
图3为本发明实施例提供的输出可调的电压偏置电路中，带隙电压基准单元的电路原理图；
图4为本发明实施例提供的输出可调的电压偏置电路中，误差放大器的电路原理图；
图5为本发明实施例提供的输出可调的电压偏置电路中，逻辑编码控制单元中3-8编码电路的示意图；
图6为本发明实施例提供的输出可调的电压偏置电路中，第一传输门开关单元的电路原理图；
图7为本发明实施例提供的输出可调的电压偏置电路中，第二传输门开关单元的电路原理图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
如图1所示，典型的电压偏置电路由带隙电压基准单元101和低压差线性稳压单元102组成。带隙电压基准单元的作用是生成零温度系数、并不受电源电压影响的基准电压Vref，然后提供给低压差线性稳压单元102作为输入参考电压。
低压差线性稳压单元102由误差放大器201、功率管202和反馈电阻网络203组成。反馈电阻网络203由电阻Rf1和电阻Rf2组成。 输出电压Vout表达式为
Figure PCTCN2021131898-appb-000001
式中
Figure PCTCN2021131898-appb-000002
可称为增益系数，其大小由电阻Rf1和电阻Rf2两者的比例关系决定。输出电压Vout由带隙电压基准单元101的基准电压Vref和低压差线性稳压单元102的增益系数共同决定。
为了解决上述带隙电压基准电路和低压差线性稳压器输出电压单一，无法在同一电路模块上实现任意温度系数、任意数值的输出电压的问题，达到射频前端模块实现更好的性能，通信终端更好的应用在复杂环境的目的，本发明实施例提供了一种输出可调的电压偏置电路，用于为射频前端模块提供不同温度系数、不同数值的电压。如图2所示，该电压偏置电路包括带隙电压基准单元301、低压差线性稳压单元302、第一传输门开关单元303、逻辑编码控制单元304和第二传输门开关单元306；带隙电压基准单元301和低压差线性稳压单元302连接电源电压VDD，带隙电压基准单元301通过第一传输门开关单元303连接低压差线性稳压单元302，低压差线性稳压单元302连接第二传输门开关单元306，逻辑编码控制单元304连接第一传输门开关单元303和第二传输门开关单元306。
利用逻辑编码控制单元304控制第一传输门开关单元303从带隙电压基准单元301生成的多个不同温度系数、不同数值的电压中选取出所需数值和温度系数的电压，输出到低压差线性稳压单元302作为其输入参考电压；同时，逻辑编码控制单元304控制第二传输门开关单元306从低压差线性稳压单元302的多个增益系数中选取出对应所需的增益系数，并通过低压差线性稳压单元302构成负反馈闭环系统，实现增益系数反馈节点的电压近似等于输入参考电压，从而输出所需数值和温度系数的电压，为射频前端模块提供合适的偏置状态，以便射频前端模块实现更好的性能，通信终端更好的应用在复杂环境。
带隙电压基准单元301，用于生成多个不同温度系数、不同数值的电压。其中，带隙电压基准单元301生成的不同温度系数、不同数值的电压的数量根据射频前端模块实际所需的数量进行调整。如图3所示，带隙电压基准单元301包括运算放大器A1、第一PMOS管701、第二PMOS管702、第三PMOS管703、第一电阻R1、第一双极型晶体管706、第二双极型晶体管707、第三双极型晶体管708和电阻分压网 络709。运算放大器A1的同相输入端连接第一PMOS管701的漏极和第一电阻R1的一端，第一电阻R1的另一端连接第一双极型晶体管706的发射极，运算放大器A1的反相输入端连接第二PMOS管702的漏极和第二双极型晶体管707的发射极，运算放大器A1的输出端连接第一PMOS管701、第二PMOS管702和第三PMOS管703的栅极，第三PMOS管703的漏极连接电阻分压网络709的一端，电阻分压网络709的另一端连接第三双极型晶体管708的发射极，电阻分压网络709的输出端连接第一传输门开关单元303，第一PMOS管701、第二PMOS管702和第三PMOS管703的源极连接电源电压VDD,第一双极型晶体管706、第二双极型晶体管707、第三双极型晶体管708的集电极接地。
其中，如图3所示，电阻分压网络709由多个第二电阻(电阻R2_A、R2_B、R2_C……R2_N)串联组成；利用电阻分压生成多个不同温度系数、不同数值的电压(Vref1、Vref2……Vrefn)，即电阻分压网络709不同的电阻节点对应输出不同温度系数、不同数值的电压。利用逻辑编码控制单元304控制第一传输门开关单元303的通断状态，实现从电阻分压网络709生成的多个不同温度系数、不同数值的电压中选取出所需数值和温度系数的电压，这些不同的电压提供给低压差线性稳压单元302作为输入参考电压，以实现输入参考电压的多样性。其中，电阻分压网络709中第二电阻比例的大小决定本输出可调的电压偏置电路的输出电压的可调精度，可根据应用需要的电压值精度和电压温度系数精度设计合适比例的电阻分压网络709。
如图3所示，第一PMOS管701、第二PMOS管702和第三PMOS管703构成电流镜，且第一PMOS管701和第二PMOS管702的宽长比一样，所以流过第一双极型晶体管706和第二双极型晶体管707的电流相等，进而第一双极型晶体管706和第二双极型晶体管707的基极-发射极电压的差值ΔV BE＝inn*V T，其中n为双极型晶体管706和双极型晶体管707并联个数的比值，V T为双极型晶体管的热电压，
Figure PCTCN2021131898-appb-000003
k为玻尔兹曼常数，q为电子电荷，即
Figure PCTCN2021131898-appb-000004
所以第一双极型晶体管706和第二双极型晶体管707的基极-发射极电压的差值ΔV BE与绝对温度T成正比，即PTAT电流。另外，由于运算放大器A1的存在， 其同相输入端和反相输入端有相同的电压，因此第一电阻R1上的压降为第一双极型晶体管706和第二双极型晶体管707的基极-发射极电压的差值ΔV BE，流过第一PMOS管701和第二PMOS管702的电流
Figure PCTCN2021131898-appb-000005
假设第三PMOS管703与第一PMOS管701、第二PMOS管702的电流镜比例为M，则流过第三PMOS管703的电流
Figure PCTCN2021131898-appb-000006
那么，利用电阻分压网络709生成多个不同温度系数、不同数值的电压(Vref1、Vref2……、Vrefn)由电流I 3流过电阻分压网络709中对应电阻产生的电压加上第三双极型晶体管708的基极-发射极电压V BE决定，如Vref1＝I 3*(R2_A+R2_B+R2_C+……R2_N)+V BE，Vref2＝I 3*(R2_B+R2_C+……R2_N)+V BE，这样电阻分压网络709的不同电阻节点可以输出不同数值、不同温度系数的电压。
如图2所示，低压差线性稳压单元302包括误差放大器401、功率管402和反馈电阻网络403；误差放大器401的正相输入端连接第一传输门开关单元303，误差放大器401的反相输入端通过第二传输门开关单元306连接反馈电阻网络403，误差放大器401的输出端连接功率管402的栅极，功率管402的漏极连接反馈电阻网络403的一端，反馈电阻网络403的另一端接地，功率管402的源极连接电源电压VDD。
如图2所示，反馈电阻网络403由多个第三电阻(Rf2_A、Rf2_B、Rf2_C……Rf2_H)串联组成；反馈电阻网络403中不同的电阻反馈节点(Vfb_A、Vfb_B、Vfb_C……Vfb_H)对应不同的增益系数。误差放大器401、功率管402和反馈电阻网络403构成一个负反馈闭环系统，使误差放大器401同相输入端和反相输入端的电压近似相等，进而实现误差放大器401的输入参考电压节点和电阻反馈节点(即增益系数反馈节点)的钳位，即电阻反馈节点的电压近似等于输入参考电压。其中，反馈电阻网络403中相邻第三电阻之间设置一个电阻反馈节点；各个电阻反馈节点对应不同的电压，每个电阻反馈节点对应输出不同的增益系数，以实现增益系数的多样性。反馈电阻网络403中第三电阻比例的大小决定本输出可调的电压偏置电路的输出电压增益系数的 可调精度，可根据应用需要的电压的增益系数设计合适比例的反馈电阻网络403。
如图4所示，误差放大器401包括第四PMOS管601、第五PMOS管602、第一NMOS管603、第二NMOS管604、第六PMOS管605、第七PMOS管606、第三NMOS管607、第四NMOS管608、第五NMOS管609、第六NMOS管610、第八PMOS管611和第九PMOS管612；第四PMOS管601的栅极作为误差放大器401的正相输入端，用于连接第一传输门开关单元303，第五PMOS管602的栅极作为误差放大器401的反相输入端，用于连接第二传输门开关单元306，第四PMOS管601的漏极连接第一NMOS管603的栅极和漏极、第二NMOS管604的栅极，第二NMOS管604的漏极连接第六PMOS管605的栅极和漏极、第七PMOS管606的栅极，第七PMOS管606的漏极作为误差放大器401的输出端Vop，用于连接功率管402的栅极、第四NMOS管608的漏极，第四NMOS管608的栅极连接第三NMOS管607的栅极和漏极、第五PMOS管602的漏极，第五PMOS管602的源极连接第四PMOS管601的源极、第九PMOS管612的漏极，第九PMOS管612的栅极连接第八PMOS管611的栅极和漏极、第六NMOS管610的漏极，第六NMOS管610的栅极连接第五NMOS管609的栅极和漏极，第五NMOS管609的漏极连接外部的偏置电压Ibias，第六PMOS管605、第七PMOS管606、第八PMOS管611和第九PMOS管612的源极均连接电源电压VDD，第一NMOS管603、第二NMOS管604、第三NMOS管607、第四NMOS管608、第五NMOS管609和第六NMOS管610的源极均接地。
本发明实施例提供的误差放大器401中，第四PMOS管601和第五PMOS管602是输入放大对管，第一NMOS管603和第二NMOS管604、第六PMOS管605和第七PMOS管606、第三NMOS管607和第四NMOS管608、第五NMOS管609和第六NMOS管610以及第八PMOS管611和第九PMOS管612分别构成镜像电流镜。偏置电流Ibias经过第五NMOS管609和第六NMOS管610以及第八PMOS管611和第九PMOS管612镜像为第四PMOS管601和第五PMOS管602提供电流偏置。第四PMOS管601接收带隙电压基准单元301提供所需数值和温度系数的电压，作为所述低压差线性稳压单元的参考输入电压，第五PMOS管602接收反 馈电阻网络403提供所需增益系数对应的电阻反馈节点，通过第一NMOS管603和第二NMOS管604、第六PMOS管605和第七PMOS管606、第三NMOS管607和第四NMOS管608镜像。本质上，误差放大器401是一个带电流镜负载的运算放大器。低压差线性稳压单元的误差放大器，功率管和反馈电阻网络构成一个负反馈闭环系统，使误差放大器同相输入端和反相输入端的电压近似相等，进而实现输入参考电压节点和电阻反馈节点的钳位，即电阻反馈节点的电压近似等于输入参考电压。
逻辑编码控制单元304是利用若干个较少的逻辑控制位生成多种逻辑组合，以控制传第一传输门开关单元303和第二传输门开关单元306选择不同输入参考电压和不同的增益系数，进而实现多种不同电压组合。逻辑编码控制单元304可以是由非门电路和与门电路构成的二进制编码电路；例如，逻辑编码控制单元304可以是2-4编码电路、3-8编码电路、4-16编码电路等二进制编码电路。其中，逻辑编码控制单元304的逻辑控制位的多少由要求输出的电压种类和逻辑编码的方式决定，一般遵循使用尽可能少的逻辑控制位来实现尽可能多的电压种类，以适应更多的应用需求。即逻辑编码控制单元304产生的控制电平的数量由射频前端模块所需温度系数、数值的电压的数量决定。
如图5所示，以逻辑编码控制单元304是3-8编码电路为例，逻辑控制位Reg0<2>，Reg0<1>，Reg0<0>首先分别依次经过非门电路得到电平Reg0<2>_Bar和Reg0<2>_Buf，Reg0<1>_Bar和Reg0<1>_Buf，Reg0<0>_Bar和Reg0<0>_Buf。然后将这些电平进行逻辑组合经过三输入与门电路得到控制电平，一种Reg0<2:0>的逻辑组合对应一个控制电平，Reg0<2:0>＝000；001；……；111依次对应输出控制电平VC_0；VC_1；…；VC_7。
第一传输门开关单元303包括多个第一传输门开关，第一传输门开关的数量与电阻分压网络709产生的不同数值、不同温度系数的电压的数量相同，并且一一对应。电阻分压网络709不同的电阻节点与多个第一传输门开关对应连接，使得电阻分压网络709输出的每一个固定数值、固定温度系数的电压对应一个第一传输门开关。
如图6所示，每个第一传输门开关包括一个第十PMOS管、第七 NMOS管和第一反相器,第十PMOS管源极连接第七NMOS管的漏极作为第一传输门开关的输入端，用于连接电阻分压网络709对应的电阻节点；第十PMOS管漏极连接第七NMOS管的源极作为第一传输门开关的输出端，用于连接误差放大器401的正相输入端；第七NMOS管的栅极连接逻辑编码控制单元304对应的输出端和第一反相器的输入端，第一反相器的输出端连接第十PMOS管的栅极。如图6示出的PMOS管M1、NMOS管M2和第一反相器J1、PMOS管M5、NMOS管M6和第一反相器J2……PMOS管M30、NMOS管M29和第一反相器J15相应组成多个第一传输门开关。利用MOS管的导通和截止对应控制支路的导通和截止，以实现逻辑组合与带隙电压基准单元301的电阻分压得到的电压一一对应，进而实现逻辑组合和输出电压一一对应，保证一种逻辑对应一种确定数值、确定温度系数的电压。电压Vref1、Vref2……Vrefn通过第一传输门开关单元303控制输出一个确定数值、确定温度系数的电压Vref给低压差线性稳压单元302作为其输入参考电压。
如图6所示，逻辑编码控制单元304输出的控制电平VC_0；VC_1；…；VC_7作为使能信号依次控制相应的第一传输门开关的导通和截止。以控制电平VC_0为例，当控制电平VC_0为高电平时，PMOS管M1和NMOS管M2导通，使得第一传输门开关导通，电压Vref_1传输到第一传输门开关的输出端，使其输出一个固定数值、固定温度系数的电压Vref给低压差线性稳压单元302作为其输入参考电压。当控制电平VC_0为低电平时，PMOS管M1和NMOS管M2截止，使得第一传输门开关截止，即停止向低压差线性稳压单元302输出一个固定数值、固定温度系数的电压Vref。因此，每一种逻辑组合对应一个控制电平，每一个控制电平对应控制一个确定数值、确定温度系数的电压。
第二传输门开关单元306包括多个第二传输门开关，第二传输门开关的数量与电阻分压网络709产生的不同数值、不同温度系数的电压的数量相同。反馈电阻网络403中不同的电阻反馈节点与多个第二传输门开关对应连接，使得反馈电阻网络403输出的每一个增益系数的电压对应一个第二传输门开关。
如图7所示，每个第二传输门开关包括一个第十一PMOS管、第八NMOS管和第二反相器,第十一PMOS管源极连接第八NMOS管的漏极作 为第二传输门开关的输入端，用于连接反馈电阻网络403对应的电阻反馈节点；第十一PMOS管漏极连接第八NMOS管的源极作为第二传输门开关的输出端，用于连接误差放大器401的反相输入端；第八NMOS管的栅极连接逻辑编码控制单元304对应的输出端和第二反相器的输入端，第二反相器的输出端连接第十一PMOS管的栅极。如图7示出的PMOS管M3、NMOS管M4和第二反相器J16、PMOS管M7、NMOS管M8和第二反相器J17……PMOS管M31、NMOS管M32和第二反相器J30相应组成多个第二传输门开关。利用MOS管的导通和截止对应控制支路的导通和截止，以实现逻辑组合与反馈电阻网络403的电阻得到的增益系数一一对应，进而实现逻辑组合和输出电压一一对应，保证每一种逻辑对应一个固定增益系数。
如图7所示，逻辑编码控制单元304输出的控制电平VC_0；VC_1；…；VC_7作为使能信号依次控制相应的第二传输门开关的导通和截止。以控制电平VC_0为例，当控制电平VC_0为高电平时，PMOS管M3和NMOS管M4导通，使得第二传输门开关导通，电阻反馈节点Vfb_A输出的某一增益系数的电压传输到第二传输门开关的输出端，使其输出一个固定增益系数的电压Vfb给低压差线性稳压单元302。当控制电平VC_0为低电平时，PMOS管M3和NMOS管M4截止，使得第二传输门开关截止，即停止向低压差线性稳压单元302输出一个固定增益系数的电压Vfb。因此，每一种逻辑组合对应一个控制电平，每一个控制电平对应控制一个固定数值、固定温度系数的电压。
因此，根据射频前端模块所需数值和温度系数的电压，逻辑编码控制单元304输出的控制电平VC_0；VC_1；…；VC_7对应选择控制相应的电阻节点和电阻反馈节点，以控制第一传输门开关单元303选择出所需的输入参考电压，同时该控制电平还控制第二传输门开关单元306选择出所需的对应增益系数，两者组合到一起，通过低压差线性稳压单元102输出射频前端模块所需的数值和温度系数的电压。不同的逻辑组合对应不同数值和温度系数的电压。
另外，本发明实施例中提供的输出可调的电压偏置电路可以被用在集成电路芯片中。对于该集成电路芯片中输出可调的电压偏置电路的具体结构，在此不再一一详述。
上述输出可调的电压偏置电路还可以被用在通信终端中，作为射频集成电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明所提供的技术方案也适用于其他射频集成电路应用的场合，例如通信基站等。
本发明所提供的输出可调的电压偏置电路通过在带隙电压基准单元和低压差线性稳压单元中相应的设置电阻分压网络和反馈电阻网络，以生成多个不同温度系数、不同数值的电压和不同的增益系数；利用逻辑编码控制单元控制相应的传输门开关单元选择所需数值和温度系数的输入参考电压和所需的增益系数，以输出所需数值和温度系数的电压，为射频前端模块提供合适的偏置状态，以使射频前端模块实现更好的性能，并使通信终端在复杂环境下具有更好的灵活性和适应性。
以上对本发明所提供的输出可调的电压偏置电路、芯片及通信终端进行了详细的说明。对本领域的技术人员在本发明的基础上所做的任何非实质性的变化及替换，均属于本发明所要求保护的范围。

Claims (10)

  1. 一种输出可调的电压偏置电路，其特征在于包括带隙电压基准单元、低压差线性稳压单元、第一传输门开关单元、逻辑编码控制单元和第二传输门开关单元；所述带隙电压基准单元通过所述第一传输门开关单元连接所述低压差线性稳压单元，所述低压差线性稳压单元连接所述第二传输门开关单元，所述逻辑编码控制单元连接所述第一传输门开关单元和所述第二传输门开关单元；
    利用所述逻辑编码控制单元控制所述第一传输门开关单元从所述带隙电压基准单元生成的多个不同温度系数、不同数值的电压中选取出所需数值和温度系数的电压，输出到所述低压差线性稳压单元作为其输入参考电压；同时，所述逻辑编码控制单元控制所述第二传输门开关单元从所述低压差线性稳压单元的多个增益系数中选取出对应所需的增益系数，并通过所述低压差线性稳压单元构成负反馈闭环系统，实现增益系数反馈节点的电压近似等于输入参考电压，从而输出所需数值和温度系数的电压。
  2. 如权利要求1所述的输出可调的电压偏置电路，其特征在于：
    所述带隙电压基准单元包括运算放大器、第一PMOS管、第二PMOS管、第三PMOS管、第一电阻、第一双极型晶体管、第二双极型晶体管、第三双极型晶体管和电阻分压网络；所述运算放大器的同相输入端连接所述第一PMOS管的漏极和所述第一电阻的一端，所述第一电阻的另一端连接所述第一双极型晶体管的发射极，所述运算放大器的反相输入端连接所述第二PMOS管的漏极和所述第二双极型晶体管的发射极，所述运算放大器的输出端连接所述第一PMOS管、所述第二PMOS管和所述第三PMOS管的栅极，所述第三PMOS管的漏极连接所述电阻分压网络的一端，所述电阻分压网络的另一端连接所述第三双极型晶体管的发射极，所述电阻分压网络的输出端连接所述第一传输门开关单元，所述第一PMOS管、所述第二PMOS管和所述第三PMOS管的源极连接电源电压,所述第一双极型晶体管、所述第二双极型晶体管、所述第三双极型晶体管的集电极接地。
  3. 如权利要求2所述的输出可调的电压偏置电路，其特征在于：
    所述电阻分压网络由多个第二电阻串联组成；所述电阻分压网络不同的电阻节点对应输出不同温度系数、不同数值的电压。
  4. 如权利要求2所述的输出可调的电压偏置电路，其特征在于：
    所述低压差线性稳压单元包括误差放大器、功率管和反馈电阻网络；所述误差放大器的正相输入端连接所述第一传输门开关单元，所述误差放大器的反相输入端通过所述第二传输门开关单元连接所述反馈电阻网络，所述误差放大器的输出端连接所述功率管的栅极，所述功率管的漏极连接所述反馈电阻网络的一端，所述反馈电阻网络的另一端接地，所述功率管的源极连接电源电压。
  5. 如权利要求4所述的输出可调的电压偏置电路，其特征在于：
    所述反馈电阻网络由多个第三电阻串联组成；每个所述电阻反馈节点对应输出不同的增益系数。
  6. 如权利要求1所述的输出可调的电压偏置电路，其特征在于：
    所述逻辑编码控制单元是由非门电路和与门电路构成的二进制编码电路。
  7. 如权利要求4所述的输出可调的电压偏置电路，其特征在于：
    所述第一传输门开关单元包括多个第一传输门开关，所述第一传输门开关包括一个第十PMOS管、第七NMOS管和第一反相器,所述第十PMOS管源极连接所述第七NMOS管的漏极作为所述第一传输门开关的输入端，用于连接所述电阻分压网络对应的电阻节点；所述第十PMOS管漏极连接所述第七NMOS管的源极作为所述第一传输门开关的输出端，用于连接所述误差放大器的正相输入端；所述第七NMOS管的栅极连接所述逻辑编码控制单元对应的输出端和所述第一反相器的输入端，所述第一反相器的输出端连接所述第十PMOS管的栅极。
  8. 如权利要求4所述的输出可调的电压偏置电路，其特征在于：
    所述第二传输门开关单元包括多个第二传输门开关，所述第二传输门开关包括一个第十一PMOS管、第八NMOS管和第二反相器,所述第十一PMOS管源极连接所述第八NMOS管的漏极作为所述第二传输门开关的输入端，用于连接所述反馈电阻网络对应的电阻反馈节点；所述第十一PMOS管漏极连接所述第八NMOS管的源极作为所述第二传输门开关的输出端，用于连接所述误差放大器的反相输入端；所述第八NMOS 管的栅极连接所述逻辑编码控制单元对应的输出端和所述第二反相器的输入端，所述第二反相器的输出端连接所述第十一PMOS管的栅极。
  9. 一种集成电路芯片，其特征在于包括权利要求1～8中任意一项所述的输出可调的电压偏置电路。
  10. 一种通信终端，其特征在于包括权利要求1～8中任意一项所述的输出可调的电压偏置电路。
PCT/CN2021/131898 2020-11-20 2021-11-19 一种输出可调的电压偏置电路、芯片及通信终端 WO2022105890A1 (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220228929A1 (en) * 2021-01-20 2022-07-21 Kioxia Corporation Semiconductor integrated circuit
CN116523012A (zh) * 2023-07-03 2023-08-01 湖南师范大学 一种基于生成对抗神经网络的忆阻器自学习电路
CN117082682A (zh) * 2023-08-31 2023-11-17 魅杰光电科技(上海)有限公司 电压调节电路、电压调节方法、光源控制器
WO2024040758A1 (zh) * 2022-08-26 2024-02-29 长鑫存储技术有限公司 电压生成电路及存储器

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112327992A (zh) * 2020-11-20 2021-02-05 唯捷创芯(天津)电子技术股份有限公司 一种输出可调的电压偏置电路、芯片及通信终端
CN113311898B (zh) * 2021-07-30 2021-12-17 唯捷创芯(天津)电子技术股份有限公司 一种具有电源抑制的ldo电路、芯片及通信终端
CN113311899B (zh) * 2021-08-02 2021-11-16 四川蕊源集成电路科技有限公司 一种电压调节器
CN114035643A (zh) * 2022-01-10 2022-02-11 上海奥简微电子科技有限公司 温控保护电路
CN114442717B (zh) * 2022-01-21 2023-04-07 星宸科技股份有限公司 具有双向电流调整的低压差稳压器
CN115202423A (zh) * 2022-07-07 2022-10-18 芯海科技（深圳）股份有限公司 一种低压差线性稳压电路
CN115951752B (zh) * 2023-03-13 2023-06-06 唯捷创芯(天津)电子技术股份有限公司 具有过流保护的低压差线性稳压器、芯片及电子设备
CN116088631B (zh) * 2023-04-11 2023-06-30 长鑫存储技术有限公司 一种电源电路和存储器
CN117353673B (zh) * 2023-12-04 2024-03-15 上海安其威微电子科技有限公司 射频放大电路、控制方法、控制模块和电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177785B1 (en) * 1998-09-29 2001-01-23 Samsung Electronics Co., Ltd. Programmable voltage regulator circuit with low power consumption feature
CN102289238A (zh) * 2010-04-13 2011-12-21 半导体元件工业有限责任公司 可编程低压降调节器及其方法
CN106227282A (zh) * 2016-07-27 2016-12-14 中国航天科技集团公司第九研究院第七七研究所 具有多模式控制功能的高可靠性低压差线性稳压器电路
CN112327992A (zh) * 2020-11-20 2021-02-05 唯捷创芯(天津)电子技术股份有限公司 一种输出可调的电压偏置电路、芯片及通信终端

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009003886A (ja) * 2007-06-25 2009-01-08 Samsung Electronics Co Ltd 電圧レギュレータ回路
TWI694320B (zh) * 2015-09-22 2020-05-21 南韓商三星電子股份有限公司 使用多電源和增益提升技術之電壓調節器以及包含該電壓調節器的行動裝置
CN105259969B (zh) * 2015-11-16 2017-04-19 西安紫光国芯半导体有限公司 一种温度系数小的带隙基准电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177785B1 (en) * 1998-09-29 2001-01-23 Samsung Electronics Co., Ltd. Programmable voltage regulator circuit with low power consumption feature
CN102289238A (zh) * 2010-04-13 2011-12-21 半导体元件工业有限责任公司 可编程低压降调节器及其方法
CN106227282A (zh) * 2016-07-27 2016-12-14 中国航天科技集团公司第九研究院第七七研究所 具有多模式控制功能的高可靠性低压差线性稳压器电路
CN112327992A (zh) * 2020-11-20 2021-02-05 唯捷创芯(天津)电子技术股份有限公司 一种输出可调的电压偏置电路、芯片及通信终端

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220228929A1 (en) * 2021-01-20 2022-07-21 Kioxia Corporation Semiconductor integrated circuit
US11835399B2 (en) * 2021-01-20 2023-12-05 Kioxia Corporation Semiconductor integrated circuit with configurable setting based on temperature information
WO2024040758A1 (zh) * 2022-08-26 2024-02-29 长鑫存储技术有限公司 电压生成电路及存储器
CN116523012A (zh) * 2023-07-03 2023-08-01 湖南师范大学 一种基于生成对抗神经网络的忆阻器自学习电路
CN116523012B (zh) * 2023-07-03 2023-09-08 湖南师范大学 一种基于生成对抗神经网络的忆阻器自学习电路
CN117082682A (zh) * 2023-08-31 2023-11-17 魅杰光电科技(上海)有限公司 电压调节电路、电压调节方法、光源控制器
CN117082682B (zh) * 2023-08-31 2024-05-28 魅杰光电科技(上海)有限公司 电压调节电路、电压调节方法、光源控制器

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