WO2022104613A1 - 电压监测电路和芯片 - Google Patents

电压监测电路和芯片 Download PDF

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WO2022104613A1
WO2022104613A1 PCT/CN2020/129895 CN2020129895W WO2022104613A1 WO 2022104613 A1 WO2022104613 A1 WO 2022104613A1 CN 2020129895 W CN2020129895 W CN 2020129895W WO 2022104613 A1 WO2022104613 A1 WO 2022104613A1
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delay
flip
circuit
signal
flop
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PCT/CN2020/129895
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English (en)
French (fr)
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肖长焕
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华为技术有限公司
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Priority to PCT/CN2020/129895 priority Critical patent/WO2022104613A1/zh
Priority to CN202080107236.9A priority patent/CN116635724A/zh
Publication of WO2022104613A1 publication Critical patent/WO2022104613A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof

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  • the present application relates to the field of chips, and in particular, to a voltage monitoring circuit and method.
  • the chip can detect whether the power supply voltage is safe through a voltage monitoring circuit. At present, the voltage monitoring circuit in the chip can only judge that the voltage of the monitored power supply is higher or lower than the threshold, but cannot provide a higher-precision voltage value.
  • Embodiments of the present application provide a voltage monitoring circuit and a chip, which are used to measure the voltage of a monitored power supply with higher precision.
  • a voltage monitoring circuit comprising: a first delay sub-circuit, a second delay sub-circuit and an encoding sub-circuit; the first delay sub-circuit is used for delaying a reference signal whose cycle is inverted. At least one cycle of the reference signal is used to obtain the first signal; the second delay sub-circuit includes multiple groups of delay devices connected in series, and the multiple groups of delay devices are powered by the monitored power supply, and the first group of delay devices is used for inputting cycle inversion.
  • the reference signal, each group of delay devices is used to delay the input signal to output a second signal; the encoding sub-circuit is used to differentiate the first signal from the multiple second signals output by the multiple groups of delay devices respectively. Or, to output the coded value corresponding to the voltage of the monitored power supply.
  • the voltage monitoring circuit includes: a first delay sub-circuit, a second delay sub-circuit, and an encoding sub-circuit; the first delay sub-circuit is used to delay the input cycle-reversed reference signal by at least one The cycle of the reference signal is used to obtain the first signal; the second delay sub-circuit includes multiple groups of delay devices connected in series, the multiple groups of delay devices are powered by the monitored power supply, and the first group of delay devices is used to input the reference signal whose cycle is reversed , each group of delay devices is used to delay the input signal to output a second signal; the encoding sub-circuit is used to XOR the first signal with multiple second signals output by multiple groups of delay devices respectively, To output the coded value corresponding to the voltage of the monitored power supply.
  • the voltage of the monitored power supply can be encoded by using the different distances transmitted by the cycle-flipped reference signal in the delay chain under the condition of different monitored power supplies, which can measure the voltage of the monitored power supply with higher accuracy.
  • the first delay sub-circuit includes 2N first flip-flops connected in series, the data input terminal of the first first flip-flop is used to input a reference signal for cycle inversion, and the previous first flip-flop
  • the data output terminal of the device is coupled to the data input terminal of the last first flip-flop, the data output terminal of the last first flip-flop is used to output the first signal, and N is a positive integer.
  • the second delay sub-circuit further includes a plurality of second flip-flops corresponding to the multiple groups of delay devices respectively, and the data input terminals of the second flip-flops are coupled to the outputs of the corresponding delay devices terminal, the data output terminal of the second flip-flop is used to output a second signal.
  • the second flip-flop can sample the signal input from the data input terminal D, thereby outputting a stable signal through the data output terminal Q, preventing the output signal from being metastable, that is, preventing the output of a signal with an uncertain result.
  • the encoding sub-circuit includes multiple sets of coupled XOR gates and third flip-flops, for a set of XOR gates and third flip-flops: one input end of the XOR gate is used to input the first signal, the other input terminal of the XOR gate is used to input the second signal, the output terminal of the XOR gate is coupled to the data input terminal of the third flip-flop, and the data output terminal of the third flip-flop is used to output one bit of the encoded value .
  • This embodiment provides one possible form of encoding subcircuit.
  • the voltage monitoring circuit further includes a frequency dividing circuit, and the frequency dividing circuit is used for dividing the frequency of the clock signal to obtain a reference signal whose period is inverted.
  • This embodiment provides how to simply obtain a reference signal whose period is reversed without adding additional circuits.
  • the frequency dividing circuit includes a fourth flip-flop and a NOT gate, a clock signal terminal of the fourth flip-flop is used to input a clock signal, and a data output terminal of the fourth flip-flop is coupled to an input terminal of the NOT gate , the output end of the NOT gate is coupled to the data input end of the fourth flip-flop, and the output end of the NOT gate is used for outputting a reference signal whose cycle is inverted.
  • This embodiment provides one possible form of frequency dividing circuit.
  • a chip including the voltage monitoring circuit and the working circuit as described in the first aspect and any of the implementations thereof, where the voltage monitoring circuit is used to monitor the working voltage of the working circuit.
  • FIG. 1 is a schematic structural diagram of a voltage monitoring circuit based on a bandgap (BandGap) circuit provided by an embodiment of the present application;
  • FIG. 2 is a schematic structural diagram of a voltage monitoring circuit based on a ring oscillator provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a voltage monitoring circuit based on a delay chain provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of another voltage monitoring circuit based on a delay chain provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a TT Corner simulation result of a delay device according to an embodiment of the present application.
  • another voltage monitoring circuit includes a band gap (BandGap) circuit 11 and an analog-to-digital converter (analog to digital converter, ADC) 12 .
  • the band gap (BandGap) circuit 11 generates a reference voltage, and converts the voltage of the monitored power supply into a digital code through the ADC 12, and the voltage of the monitored power supply can be judged through the coding.
  • the input voltage is too low, so that the BandGap circuit can hardly be used in the scene of poor power quality.
  • another voltage monitoring circuit includes a process voltage temperature (Process, voltage, temperature, PVT) sensor 21, a reference counter 22, an OR gate 23, and an advanced peripheral bus , APB) 24.
  • the PVT sensor 21 includes a ring oscillator (Ring Oscillator) 211 , a multiplexer (MUX) 212 , a counter 213 , and a synchronizer 214 .
  • the reference counter 22 receives the control and feedback of other devices in the chip through the APB 24 .
  • the reference counter 22 outputs a reference clock with a fixed frequency to the counter 213, controls the MUX 212 to select one of the self-check clock or the ring oscillator 211 through the selection signal, and controls whether the ring oscillator 211 works through the enable signal.
  • the synchronizer 214 is used to synchronize the output of the counter 213 . Among them, when testing whether the entire circuit is working normally, the MUX 212 selects the self-check clock to test whether the working state of the counter 213 is normal, and when working normally (monitoring the voltage of the monitored power supply), the MUX 212 selects The output of ring oscillator 211 .
  • the ring oscillator 211 is a closed-loop self-oscillating circuit, which can output different oscillation frequencies according to the voltage level of the monitored power supply. If the voltage of the monitored power supply becomes high, the output frequency of the ring oscillator 211 will become faster, and if the voltage of the monitored power supply becomes low, the output frequency of the ring oscillator 211 will become slower.
  • the counter 213 counts the reference signal of the fixed frequency output by the reference counter 22, and also counts the oscillation frequency output by the ring oscillator 211. By comparing the two count values, it is judged that the voltage of the monitored power supply is higher or lower than the The reference voltage corresponding to the reference clock. This kind of circuit cannot accurately measure the voltage of the monitored power supply, and can only compare the magnitude with the reference voltage, with low precision.
  • an embodiment of the present application provides another voltage monitoring circuit, including a first delay sub-circuit 31 , a second delay sub-circuit 32 and an encoding sub-circuit 33 .
  • the first delay sub-circuit 31 is used for delaying the input reference signal whose period is inverted by at least one period of the reference signal to obtain the first signal.
  • the reason is that the reference signal is delayed through the delay chain, and the delay chain supports the shortest delay period of one reference signal period, and the reference signal transition (for example, from high level to low level) can occur in at least one reference signal period. level, or, from low to high).
  • the first delay sub-circuit 31 includes 2N first flip-flops 311 connected in series, and N is a positive integer.
  • the data input terminal D of the first first flip-flop 311 is used to input a reference signal for cycle inversion, the data output terminal Q of the previous first flip-flop 311 is coupled to the data input terminal D of the next flip-flop 311, and the last first flip-flop 311
  • the data output terminal Q of a flip-flop 311 is coupled to the encoding sub-circuit 33 for outputting the first signal.
  • 2N first flip-flops 311 are used because each flip-flop will invert the reference signal, and the reference signal will be flipped back after a pair of flip-flops, so as to be compared with the output of the second delay sub-circuit.
  • the flip-flop can output a stable signal through the data output terminal Q by sampling the signal input by the data input terminal D, so as to prevent the output signal from being metastable, that is, to prevent the output of a signal with an uncertain result.
  • the second delay sub-circuit 32 includes multiple groups of delay devices 321 connected in series.
  • the multiple groups of delay devices 321 are powered by the monitored power supply.
  • Exemplary delay devices can be buffers (BUFs), inverters, etc.
  • the delays of the delay devices 321 may be the same or different.
  • the first group of delay devices 321 is used for inputting the reference signal of cycle inversion, and each group of delay devices is used for delaying the input signal to output a second signal through the tap, that is, the latter group of delay devices 321 is used for delaying the input signal.
  • the second signal output by the previous group of delay devices 321 is delayed, and another second signal is output.
  • the second delay sub-circuit 32 further includes a plurality of second flip-flops 322 corresponding to the multiple groups of delay devices 321 respectively.
  • the output terminal, the data output terminal Q of the second flip-flop 322 is used to output a second signal.
  • the voltage monitoring circuit further includes a frequency dividing circuit 41 , and the frequency dividing circuit 41 is used to divide the frequency of the clock signal to obtain the reference signal whose period is inverted.
  • the frequency dividing circuit 41 includes a fourth flip-flop 411 and a NOT gate 412 , the clock signal terminal CLK of the fourth flip-flop 411 is used for inputting the clock signal, and the data output terminal Q of the fourth flip-flop 411 It is coupled to the input terminal of the NOT gate 412 , the output terminal of the NOT gate 412 is coupled to the data input terminal D of the fourth flip-flop 411 , and the output terminal of the NOT gate 412 is used to output a reference signal whose cycle is inverted.
  • the encoding sub-circuit 33 is used to XOR the first signal with the second signal output by the multiple groups of delay devices 321 respectively, so as to output the encoded value corresponding to the voltage of the monitored power supply.
  • the encoding sub-circuit 33 includes multiple groups of coupled XOR gates 331 and third flip-flops 332 , for a group of XOR gates 331 and third flip-flops 332 : one input of the XOR gate 331 terminal is used to input the first signal, the other input terminal of the XOR gate 331 is used to input the second signal, the output terminal of the XOR gate 331 is coupled to the data input terminal D of the third flip-flop 332, The data output Q is used to output one bit of the encoded value.
  • the first delay sub-circuit 31 and the second delay sub-circuit 32 delay the reference signal with the same cycle inversion, and the delay time of the first delay sub-circuit 31 is fixed, the first delay The first signal output by the sub-circuit 31 is used as a reference.
  • the cycle-reversed reference signals are sequentially transmitted in multiple groups of delay devices 321, when the second signal output by a certain group of delay devices 321 is the same as the first signal, it indicates that the cycle-reversed reference signal is transmitted to the group of delay devices 321, the result of the XOR of the first signal and the second signal is 0, that is, the code value corresponds to the one-bit value of this group of delay devices 321 is 0; when the second signal output by a certain group of delay devices 321 is When one signal is different, it indicates that the reference signal whose period is reversed has not been transmitted to the group of delay devices 321 , and the result of the XOR of the first signal and the second signal is 1, that is, the encoded value corresponds to one bit of the delay device 321 of the group. The value is 1.
  • the magnitude of the voltage of the monitored power supply (or the frequency of the reference signal) connected to the second delay sub-circuit can be judged by the magnitude of the encoded value.
  • the delay of each group of delay devices will be relatively smaller.
  • the reference signal whose cycle is inverted will travel more in the delay device. long, the later the number of digits where the coded value begins to appear 1. Taking the front position of the encoded value as the low bit and the rear position as the high bit as an example, the smaller the encoded value is. In the same way, when the voltage of the monitored power supply is smaller (or the frequency of the reference signal is slower), the delay of each group of delay devices will become relatively larger.
  • the reference signal whose cycle is inverted is in the delay device.
  • the shorter the distance passed the earlier the number of digits in which the coded value begins to appear. Taking the front position of the encoded value as the low bit and the rear position as the high bit as an example, the larger the encoded value is.
  • a coding value is shown in Table 1.
  • the delay inflection point is the nth tap position n ’b10**** The delay inflection point is the n-1th tap position n-1 ’b110** The delay inflection point is the n-2th tap position n-2 ’b1110*** The delay inflection point is the n-3th tap position n-3 ’b11110*** The delay inflection point is the n-4th tap position n-4 ’b111110*** The delay inflection point is the n-5th tap position n-5 ’b1111110*** The delay inflection point is the n-6th tap position n-6 ’b11111110*** The delay inflection point is the n-7th tap position n-7 ’b111111110*** The delay inflection point is the n-8th tap position n-8 ’b1111111110*** The delay inflection point is the n-9th tap position n-7 ... ... ⁇
  • the delay inflection point represents the tap position where the result of the XOR of the first signal and the second signal starts to be 1.
  • Tables 3-5 show the coding values at different frequencies of the reference signals, wherein Table 3 is 160Mhz, Table 4 is 240Mhz, and Table 5 is 300MHz. It can be seen from this that the faster the frequency of the reference signal, the smaller the coding value.
  • the voltage monitoring circuit includes: a first delay sub-circuit, a second delay sub-circuit, and an encoding sub-circuit; the first delay sub-circuit is used to delay the input cycle-reversed reference signal by at least one The cycle of the reference signal is used to obtain the first signal; the second delay sub-circuit includes multiple groups of delay devices connected in series, the multiple groups of delay devices are powered by the monitored power supply, and the first group of delay devices is used to input the reference signal whose cycle is reversed , each group of delay devices is used to delay the input signal to output a second signal; the encoding sub-circuit is used to XOR the first signal with multiple second signals output by multiple groups of delay devices respectively, To output the coded value corresponding to the voltage of the monitored power supply.
  • the voltage of the monitored power supply can be encoded by using the different distances transmitted by the cycle-flipped reference signal in the delay chain under the condition of different monitored power supplies, which can measure the voltage of the monitored power supply with higher accuracy.
  • the range of functional indicators that cannot be achieved by traditional analog circuits can be solved.
  • the area of the chip occupied by the power detection circuit can be effectively reduced, and it is estimated that the area can be reduced by at least 50% compared to the area of the analog circuit.
  • the traditional analog circuit must be placed in a reasonable position, and the solution of the present application has basically no constraints in the layout and wiring process, and can be more flexible.
  • Analog circuits have obvious boundaries, and it is relatively easy to find, detect or perform attacks such as focused ion beam (FIB) in the field of security chips.
  • FIB focused ion beam
  • the above-mentioned voltage monitoring circuit can be used for power supply voltage detection and clock frequency detection in the field of security chips (that is, to realize the function of a digital voltage sensor, and compare the output code value with the threshold value. If the code value is greater than the high alarm threshold, it means that the power supply voltage is too high. High. If the code value is less than the low alarm threshold, it means that the power supply voltage is too low. On this basis, an interrupt or reset signal can be output to remind or reset safely.
  • the above-mentioned voltage monitoring circuit can also be used for power supply voltage detection, time-frequency frequency detection, etc. inside the chip in non-safety fields.
  • the above-mentioned voltage monitoring circuit can also be used to detect the process speed of the device in the chip production process, and can also realize the speed of the working clock inside the chip, manage the power supply voltage, and realize power consumption control.
  • An embodiment of the present application also provides a chip, including the above-mentioned voltage monitoring circuit and a working circuit, where the voltage monitoring circuit is used to monitor the working voltage of the working circuit. Its technical effect refers to the description of the voltage monitoring circuit.
  • the disclosed systems, devices and methods may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

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Abstract

一种电压监测电路和芯片，涉及芯片领域，用于实现对被监测电源的电压进行更高精度的测量。电压监测电路包括：第一延时子电路（31）、第二延时子电路（32）和编码子电路（33）；第一延时子电路（31）用于将输入的周期翻转的参考信号延时至少一个参考信号的周期以得到第一信号；第二延时子电路（32）包括串联的多组延时器件（321），多组延时器件（321）由被监测电源供电，第一组延时器件用于输入周期翻转的参考信号，每组延时器件（321）用于对输入的信号进行延时，以输出一个第二信号；编码子电路（33）用于将第一信号分别与多组延时器件（321）输出的多个第二信号进行异或，以输出被监测电源的电压对应的编码值。

Description

电压监测电路和芯片 技术领域
本申请涉及芯片领域，尤其涉及一种电压监测电路和方法。
背景技术
芯片中可以通过电压监测电路来检测电源电压是否安全。目前芯片中的电压监测电路只能判断被监测电源的电压高于或低于门限，而不能提供更高精度的电压值。
发明内容
本申请实施例提供一种电压监测电路和芯片，用于实现对被监测电源的电压进行更高精度的测量。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种电压监测电路，包括：第一延时子电路、第二延时子电路和编码子电路；第一延时子电路用于将输入的周期翻转的参考信号延时至少一个参考信号的周期以得到第一信号；第二延时子电路包括串联的多组延时器件，多组延时器件由被监测电源供电，第一组延时器件用于输入周期翻转的参考信号，每组延时器件用于对输入的信号进行延时，以输出一个第二信号；编码子电路用于将第一信号分别与多组延时器件输出的多个第二信号进行异或，以输出被监测电源的电压对应的编码值。
本申请实施例提供的电压监测电路，包括：第一延时子电路、第二延时子电路和编码子电路；第一延时子电路用于将输入的周期翻转的参考信号延时至少一个参考信号的周期以得到第一信号；第二延时子电路包括串联的多组延时器件，多组延时器件由被监测电源供电，第一组延时器件用于输入周期翻转的参考信号，每组延时器件用于对输入的信号进行延时，以输出一个第二信号；编码子电路用于将第一信号分别与多组延时器件输出的多个第二信号进行异或，以输出被监测电源的电压对应的编码值。利用不同被监测电源供电的情况下，周期翻转的参考信号在延时链中传递的距离不同来对被监测电源的电压进行编码，可以实现对被监测电源的电压进行更高精度的测量。
在一种可能的实施方式中，第一延时子电路包括串联的2N个第一触发器，第一个第一触发器的数据输入端用于输入周期翻转的参考信号，前一个第一触发器的数据输出端耦合至后一个第一触发器的数据输入端，最后一个第一触发器的数据输出端用于输出第一信号，N为正整数。该实施方式提供了第一延时子电路的一种可能形式。
在一种可能的实施方式中，第二延时子电路还包括与多组延时器件分别对应的多个第二触发器，第二触发器的数据输入端耦合至对应的延时器件的输出端，第二触发器的数据输出端用于输出一个第二信号。第二触发器可以通过对数据输入端D输入的信号进行采样，从而通过数据输出端Q输出稳定信号，防止输出信号为亚稳态，即防止输出不确定结果的信号。
在一种可能的实施方式中，编码子电路包括多组耦合的异或门和第三触发器，对于一组异或门和第三触发器：异或门的一个输入端用于输入第一信号，异或门的另一 个输入端用于输入第二信号，异或门的输出端耦合至第三触发器的数据输入端，第三触发器的数据输出端用于输出编码值的一位。该实施方式提供了编码子电路的一种可能形式。
在一种可能的实施方式中，电压监测电路还包括分频电路，分频电路用于对时钟信号进行分频以得到周期翻转的参考信号。该实施方式提供了如何不增加额外电路，简单得到周期翻转的参考信号。
在一种可能的实施方式中，分频电路包括第四触发器和非门，第四触发器的时钟信号端用于输入时钟信号，第四触发器的数据输出端耦合至非门的输入端，非门的输出端耦合至第四触发器的数据输入端，非门的输出端用于输出周期翻转的参考信号。该实施方式提供了分频电路的一种可能形式。
第二方面，提供了一种芯片，包括如第一方面及其任一实施方式所述的电压监测电路和工作电路，电压监测电路用于对工作电路的工作电压进行监测。
附图说明
图1为本申请实施例提供的一种基于带隙(BandGap)电路的电压监测电路的结构示意图；
图2为本申请实施例提供的一种基于环形振荡器的电压监测电路的结构示意图；
图3为本申请实施例提供的一种基于延时链的电压监测电路的结构示意图；
图4为本申请实施例提供的另一种基于延时链的电压监测电路的结构示意图；
图5为本申请实施例提供的一种延时器件的TT Corner仿真结果的示意图。
具体实施方式
如图1所示，为本申请实施例提供的另一种电压监测电路，包括带隙(BandGap)电路11、模数转换器(analog to digital converter，ADC)12。带隙(BandGap)电路11产生参考电压，通过ADC 12将被监测电源的电压转化成数字编码，通过编码即可以判断被监测电源的电压的高低。
但是在5nm及以下的先进芯片制造工艺中，输入电压过低，使得带隙(BandGap)电路在电源质量较差场景下几乎不能使用。
如图2所示，为本申请实施例提供的另一种电压监测电路，包括过程电压温度(Process,voltage,temperature，PVT)传感器21、参考计数器22、或门23和外围总线(advanced peripheral bus，APB)24。其中，PVT传感器21包括环形振荡器(Ring Oscillator)211、多路选择器(multiplexer，MUX)212、计数器213、同步器214。
参考计数器22通过APB 24接受芯片中其他器件的控制以及进行反馈。参考计数器22通过向计数器213输出固定频率的参考时钟，通过选择信号控制MUX 212选择自检时钟或者环形振荡器211中的一个输出，通过使能信号控制环形振荡器211是否工作。同步器214用于对计数器213的输出进行同步。其中，在对整个电路是否正常工作进行测试时，MUX 212选择自检时钟，用于对计数器213的工作状态是否正常进行测试，而在正常工作(监测被监测电源的电压)时，MUX 212选择环形振荡器211的输出。
环形振荡器211是闭环的自振荡电路，可以根据被监测电源的电压高低输出不同振荡频率。如果被监测电源的电压变高，则会导致环形振荡器211的输出频率变快， 如果被监测电源的电压变低，则会导致环形振荡器211的输出频率变慢。计数器213对参考计数器22输出固定频率的参考信号进行计数，还对环形振荡器211输出的振荡频率进行计数，通过对这两个计数值比较大小来判断被监测电源的电压高于或低于与参考时钟对应的基准电压。这种电路无法精确对被监测的电源的电压进行精确测量，仅能与基准电压比较大小，精度较低。
如图3所示，本申请实施例提供了另一种电压监测电路，包括第一延时子电路31、第二延时子电路32和编码子电路33。
第一延时子电路31用于将输入的周期翻转的参考信号延时至少一个参考信号的周期以得到第一信号。原因在于，通过延时链对参考信号进行延时，延时链最短支持延时一个参考信号的周期，在至少一个参考信号的周期内可以出现参考信号的转变(例如从高电平变为低电平，或者，从低电平变为高电平)。
在一种可能的实施方式中，第一延时子电路31包括串联的2N个第一触发器311，N为正整数。第一个第一触发器311的数据输入端D用于输入周期翻转的参考信号，前一个第一触发器311的数据输出端Q耦合至后一个触发器311的数据输入端D，最后一个第一触发器311的数据输出端Q耦合至编码子电路33，用于输出第一信号。
采用2N个第一触发器311是由于每个触发器会对参考信号进行一翻转，经过成对的触发器才会将参考信号翻转回来，以便与第二延时子电路的输出进行比较。
本申请实施例中，触发器可以通过对数据输入端D输入的信号进行采样，从而通过数据输出端Q输出稳定信号，防止输出信号为亚稳态，即防止输出不确定结果的信号。
第二延时子电路32包括串联的多组延时器件321，多组延时器件321由被监测电源供电，示例性的延时器件可以是缓存器(BUF)、反相器等，各组延时器件321的延时可以相同或不同。第一组延时器件321用于输入周期翻转的参考信号，每组延时器件用于对输入的信号进行延时，以通过抽头输出一个第二信号，即后一组延时器件321用于对前一组延时器件321的输出的第二信号进行延时，并输出另一个第二信号。
可选的，第二延时子电路32还包括与多组延时器件321分别对应的多个第二触发器322，第二触发器322的数据输入端D耦合至一组延时器件321的输出端，第二触发器322的数据输出端Q用于输出一个第二信号。
可选的，如图4所示，该电压监测电路还包括分频电路41，分频电路41用于对时钟信号进行分频以得到上述周期翻转的参考信号。
在一种可能的实施方式中，分频电路41包括第四触发器411和非门412，第四触发器411的时钟信号端CLK用于输入时钟信号，第四触发器411的数据输出端Q耦合至非门412的输入端，非门412的输出端耦合至第四触发器411的数据输入端D，并且非门412的输出端用于输出周期翻转的参考信号。
编码子电路33用于将第一信号分别与多组延时器件321输出的第二信号进行异或，以输出被监测电源的电压对应的编码值。
在一种可能的实施方式中，编码子电路33包括多组耦合的异或门331和第三触发器332，对于一组异或门331和第三触发器332：异或门331的一个输入端用于输入第一信号，异或门331的另一个输入端用于输入第二信号，异或门331的输出端耦合至 第三触发器332的数据输入端D，第三触发器332的数据输出端Q用于输出编码值的一位。
由于第一延时子电路31和第二延时子电路32对相同的周期翻转的参考信号进行延时，而第一延时子电路31的延时时间是固定的，因此将第一延时子电路31输出的第一信号作为基准。周期翻转的参考信号依次在多组延时器件321中传递时，当某一组延时器件321输出的第二信号与第一信号相同时，表明周期翻转的参考信号传递至该组延时器件321，则第一信号与第二信号异或的结果为0，即编码值与该组延时器件321对应的一位值为0；当某一组延时器件321输出的第二信号与第一信号不同时，表明周期翻转的参考信号尚未传递至该组延时器件321，则第一信号与第二信号异或的结果为1，即编码值与该组延时器件321对应的一位值为1。
通过编码值的大小即可以判断第二延时子电路接入的被监测电源的电压的大小(或者参考信号的频率快慢)。当被监测电源的电压越大(或者参考信号的频率越快)时，每组延时器件的延时相对会变小，相同时间内，周期翻转的参考信号在延时器件中传递的距离越长，编码值开始出现1的位数越靠后。以编码值靠前位置为低位，靠后位置为高位为例，则编码值越小。同理地，当被监测电源的电压越小(或者参考信号的频率越慢)时，每组延时器件的延时相对会变大，相同时间内，周期翻转的参考信号在延时器件中传递的距离越短，编码值开始出现1的位数越靠前。以编码值靠前位置为低位，靠后位置为高位为例，则编码值越大。
示例性的，一种编码值如表1所示。
表1
OUT[n-1:0]抽头位置的值 说明 编码值
’b0***** 延时拐点为第n个抽头位置 n
’b10**** 延时拐点为第n-1个抽头位置 n-1
’b110** 延时拐点为第n-2个抽头位置 n-2
’b1110*** 延时拐点为第n-3个抽头位置 n-3
’b11110*** 延时拐点为第n-4个抽头位置 n-4
’b111110*** 延时拐点为第n-5个抽头位置 n-5
’b1111110*** 延时拐点为第n-6个抽头位置 n-6
’b11111110*** 延时拐点为第n-7个抽头位置 n-7
’b111111110*** 延时拐点为第n-8个抽头位置 n-8
’b1111111110*** 延时拐点为第n-9个抽头位置 n-7
……   ……
{n-1{1},1’b0} 延时拐点为第1个抽头位置 1
{n{1}} 延时拐点为第0个抽头位置 0
表1中*表示不关注该值，默认为0。延时拐点表示第一信号与第二信号异或的结果开始为1的抽头位置。
举例如下：使用一个5nm工艺固定长度的延时链，在不同温度下，延时器件的TT Corner仿真如表2和图5所示，从中可以看出延时器件的延时与温度相关性较小，而与输入的被监测电源的电压相关性较大。
表2
Figure PCTCN2020129895-appb-000001
下面表3-表5示出了在不同参考信号的频率下的编码值，其中，表3为160Mhz，表4为240Mhz，表5为300MHz。从中可以看出，参考信号的频率越快则编码值越小。
表3
Figure PCTCN2020129895-appb-000002
表4
Figure PCTCN2020129895-appb-000003
表5
Figure PCTCN2020129895-appb-000004
本申请实施例提供的电压监测电路，包括：第一延时子电路、第二延时子电路和编码子电路；第一延时子电路用于将输入的周期翻转的参考信号延时至少一个参考信号的周期以得到第一信号；第二延时子电路包括串联的多组延时器件，多组延时器件由被监测电源供电，第一组延时器件用于输入周期翻转的参考信号，每组延时器件用于对输入的信号进行延时，以输出一个第二信号；编码子电路用于将第一信号分别与多组延时器件输出的多个第二信号进行异或，以输出被监测电源的电压对应的编码值。利用不同被监测电源供电的情况下，周期翻转的参考信号在延时链中传递的距离不同来对被监测电源的电压进行编码，可以实现对被监测电源的电压进行更高精度的测量。
通过将芯片内部的电源电压检测与生产工艺解耦，可以解决传统模拟电路无法实现的功能指标范围。在先进生产工艺下，可以有效减小电源检测电路所占芯片的面积，相对模拟电路的面积估计至少可以减少50％的面积。另外，传统模拟电路，必须放置在合理位置，本申请的方案在布局布线环节基本没有约束，可以更加灵活。而且相对模拟电路在版图识别级别更加隐蔽，没有任何明显边界，电源网络分散。模拟电路具有明显的边界，在安全芯片领域比较容易发现，探测或做聚焦离子束(focused ion beam，FIB)等攻击。
另外，上述电压监测电路可以用作安全芯片领域的电源电压检测、时钟频率检测(即实现数字电压传感器的功能，将输出的编码值和阈值比较，如果编码值大于高报警阈值，说明电源电压过高。如果编码值小于低报警门限，说明电源电压过低。在此基础上可以输出中断或者复位信号，用于提醒或者安全复位。
上述电压监测电路也可以用在非安全领域的芯片内部的电源电压检测、时频频率检测等。
上述电压监测电路还可以用于在芯片生产过程中对器件工艺速度的检测，也可以实现对芯片内部的工作时钟快慢、对电源电压进行管理，实现功耗控制等。
本申请实施例还提供了一种芯片，包括上述电压监测电路和工作电路，电压监测电路用于对工作电路的工作电压进行监测。其技术效果参照电压监测电路的描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专 业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (7)

  1. 一种电压监测电路，其特征在于，包括：第一延时子电路、第二延时子电路和编码子电路；
    所述第一延时子电路用于将输入的周期翻转的参考信号延时至少一个参考信号的周期以得到第一信号；
    所述第二延时子电路包括串联的多组延时器件，所述多组延时器件由被监测电源供电，第一组延时器件用于输入所述周期翻转的参考信号，每组延时器件用于对输入的信号进行延时，以输出一个第二信号；
    所述编码子电路用于将所述第一信号分别与所述多组延时器件输出的多个第二信号进行异或，以输出所述被监测电源的电压对应的编码值。
  2. 根据权利要求1所述的电压监测电路，其特征在于，所述第一延时子电路包括串联的2N个第一触发器，第一个第一触发器的数据输入端用于输入所述周期翻转的参考信号，前一个第一触发器的数据输出端耦合至后一个第一触发器的数据输入端，最后一个第一触发器的数据输出端用于输出所述第一信号，N为正整数。
  3. 根据权利要求1-2任一项所述的电压监测电路，其特征在于，所述第二延时子电路还包括与所述多组延时器件分别对应的多个第二触发器，所述第二触发器的数据输入端耦合至对应的延时器件的输出端，所述第二触发器的数据输出端用于输出一个所述第二信号。
  4. 根据权利要求1-3任一项所述的电压监测电路，其特征在于，所述编码子电路包括多组耦合的异或门和第三触发器，对于一组异或门和第三触发器：所述异或门的一个输入端用于输入所述第一信号，所述异或门的另一个输入端用于输入所述第二信号，所述异或门的输出端耦合至所述第三触发器的数据输入端，所述第三触发器的数据输出端用于输出所述编码值的一位。
  5. 根据权利要求1-4任一项所述的电压监测电路，其特征在于，所述电压监测电路还包括分频电路，所述分频电路用于对时钟信号进行分频以得到所述周期翻转的参考信号。
  6. 根据权利要求5所述的电压监测电路，其特征在于，所述分频电路包括第四触发器和非门，所述第四触发器的时钟信号端用于输入所述时钟信号，所述第四触发器的数据输出端耦合至所述非门的输入端，所述非门的输出端耦合至所述第四触发器的数据输入端，所述非门的输出端用于输出所述周期翻转的参考信号。
  7. 一种芯片，其特征在于，包括如权利要求1-6任一项所述的电压监测电路和工作电路，所述电压监测电路用于对所述工作电路的工作电压进行监测。
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CN106093531A (zh) * 2016-07-25 2016-11-09 华为技术有限公司 一种芯片动态电压降检测电路及检测方法
CN111416619A (zh) * 2020-03-26 2020-07-14 中国科学院微电子研究所 一种延时测量电路、延时测量方法、电子设备及芯片

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