WO2022100754A1 - 一种片内rc振荡器、芯片及通信终端 - Google Patents

一种片内rc振荡器、芯片及通信终端 Download PDF

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Publication number
WO2022100754A1
WO2022100754A1 PCT/CN2021/130943 CN2021130943W WO2022100754A1 WO 2022100754 A1 WO2022100754 A1 WO 2022100754A1 CN 2021130943 W CN2021130943 W CN 2021130943W WO 2022100754 A1 WO2022100754 A1 WO 2022100754A1
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Prior art keywords
module
oscillator
circuit
voltage
frequency
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PCT/CN2021/130943
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English (en)
French (fr)
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王永寿
高晨阳
林升
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唯捷创芯(天津)电子技术股份有限公司
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Priority to EP21891274.9A priority Critical patent/EP4246803A1/en
Priority to KR1020237020470A priority patent/KR20230118863A/ko
Priority to JP2023529031A priority patent/JP2023550361A/ja
Publication of WO2022100754A1 publication Critical patent/WO2022100754A1/zh
Priority to US18/318,031 priority patent/US20230283265A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
    • H03B5/26—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator frequency-determining element being part of bridge circuit in closed ring around which signal is transmitted; frequency-determining element being connected via a bridge circuit to such a closed ring, e.g. Wien-Bridge oscillator, parallel-T oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
    • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits

Definitions

  • the invention relates to an on-chip RC oscillator, as well as an integrated circuit chip including the on-chip RC oscillator and a corresponding communication terminal, belonging to the technical field of analog integrated circuits.
  • On-chip RC oscillators are widely used in integrated circuit chips, especially in mixed-signal chips and high-end analog chips. Integrating a high-precision on-chip RC oscillator inside the integrated circuit chip can not only improve the system precision and reliability, but also reduce the system cost. In high-precision mixed-signal integrated circuit chips, the quality of the output clock signal from the on-chip RC oscillator will affect the conversion accuracy of the analog-to-digital conversion circuit. At the same time, in other integrated circuit chips with communication interfaces, high-precision on-chip The RC oscillator can greatly reduce the bit error rate of the communication interface, thereby greatly improving the stability and reliability of the data transmission of the communication interface.
  • a high frequency and low temperature drift RC oscillator is disclosed.
  • the oscillator has made temperature adjustment and accuracy calibration to its frequency to a certain extent, because the calibration current used has a certain temperature coefficient, the temperature characteristics of the output frequency of the oscillator will be larger with the change of temperature.
  • the temperature calibration is realized by active devices (such as NMOSFET) and resistors, the resistance value of this resistor has obvious process dispersion and electrical parameter dependence, so that the accuracy of the oscillator output frequency is greatly limited.
  • a Chinese patent application with application number 201811430806.9 discloses a tunable high-precision RC oscillator.
  • the principle of the oscillator to achieve low temperature drift is to adjust the output impedance of the amplifier, introduce a part of the input offset voltage, and adjust the absolute value of the comparator delay to change its temperature coefficient to compensate the temperature characteristics of the delay time of the digital logic of the later stage.
  • the accuracy of the output frequency of this oscillator is limited due to the certain temperature characteristics of the digital delay unit itself. At the same time, the higher the output frequency, the more difficult it is to implement.
  • the primary technical problem to be solved by the present invention is to provide an on-chip RC oscillator.
  • Another technical problem to be solved by the present invention is to provide a chip including the on-chip RC oscillator and a corresponding communication terminal.
  • the present invention adopts the following technical scheme:
  • an on-chip RC oscillator including a voltage regulator source module, an RC core oscillator module, a frequency sampling and conversion module, and a frequency trimming module; the voltage regulator source modules are respectively connected to The RC core oscillator module, the frequency sampling and conversion module and the frequency trimming module, the output end of the RC core oscillator module is connected to the input end of the frequency sampling and conversion module, the frequency sampling and The output end of the conversion module is connected to the input end of the frequency trimming module, and the output end of the frequency trimming module is connected to the RC core oscillator module; wherein,
  • the voltage-stabilizing source module is used to generate a power supply voltage that does not change with the power supply voltage
  • the frequency sampling and conversion module is used to convert the frequency of the clock signal output by the RC core oscillator module sampled in real time into a voltage signal, and perform analog-to-digital conversion to obtain a corresponding digital code;
  • the frequency trimming module is used for receiving the digital code, and according to the preset voltage and zero temperature coefficient current of the on-chip RC oscillator, generating a control signal through the digital code to control the direction to the desired frequency.
  • the RC core oscillator module outputs a voltage with a suitable temperature coefficient and a zero temperature coefficient current, so as to implement temperature compensation and precision calibration for the frequency of the clock signal output by the RC core oscillator module.
  • the RC core oscillator module includes a first switch tube, a second switch tube, a first capacitor, a first comparator, a second comparator, an RS flip-flop and a buffer circuit;
  • the first switch The gates of the transistor and the second switch are respectively connected to the output end of the RS flip-flop, and the drains of the first switch and the second switch are respectively connected to the first bias current and the second bias One end of the current, the other ends of the first bias current and the second bias current are connected to one end of the first capacitor, the inverting input end of the first comparator and the second comparator Non-inverting input terminal, the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are connected to the corresponding voltage output terminals of the frequency trimming module, the first comparator and the The output terminal of the second comparator is connected to the corresponding input terminal of the RS flip-flop, the signal output terminal of the RS flip-flop is connected to the input terminal of the buffer circuit, the first comparator
  • the frequency sampling and conversion module includes a frequency sampling module and an analog-to-digital conversion module, the input end of the frequency sampling module is connected to the output end of the RC core oscillator module, and the output end of the frequency sampling module The input end of the analog-to-digital conversion module is connected, and the output end of the analog-to-digital conversion module is connected to the input end of the frequency trimming module.
  • the frequency sampling module includes a two-phase non-overlapping clock generating circuit, the switched capacitor resistor and the voltage-in-phase proportional amplifier; the input end of the two-phase non-overlapping clock generating circuit is connected to the RC The output end of the core oscillator module, the output end of the two-phase non-overlapping clock generating circuit is connected to the switched capacitor resistor, and the switched capacitor resistor is respectively connected to the zero temperature current source and the input end of the proportional amplifier with the same voltage, The output terminal of the same-phase proportional amplifier is connected to the analog-to-digital conversion module.
  • the switched capacitor resistor includes a first NMOS transistor, a second NMOS transistor and a second capacitor; the gates of the first NMOS transistor and the second NMOS transistor are respectively connected to the two-phase non-overlapping The output terminal of the clock generation circuit, the source of the first NMOS transistor is connected to a zero temperature current source, the drain of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to one end of the second capacitor , the other end of the second capacitor is grounded, and the drain of the second NMOS transistor is connected to the input end of the proportional amplifier with the same voltage.
  • the voltage in-phase proportional amplifier includes a first operational amplifier, a first resistor and a second resistor; the non-inverting input end of the first operational amplifier is connected to the drain of the second NMOS transistor, and the first operational amplifier is connected to the drain of the second NMOS transistor.
  • the inverting input end of the operational amplifier is connected to one end of the first resistor and the second resistor, the other end of the first resistor is grounded, and the other end of the second resistor is respectively connected to the output end of the first operational amplifier and the analog-to-digital conversion module.
  • the frequency trimming module includes a decoding and logic control circuit, a clock temperature drift trimming circuit, and a clock absolute precision trimming circuit; the input end of the decoding and logic control circuit is connected to the analog-to-digital converter The output end of the module, the output end of the decoding and logic control circuit is respectively connected to the input end of the clock temperature drift trimming circuit and the clock absolute accuracy trimming circuit, and the clock temperature drift trimming circuit is connected to the The non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator, and the output terminal of the clock absolute accuracy trimming circuit is connected to the first bias current and the second bias current.
  • the clock temperature drift trimming circuit includes a second bandgap reference circuit, a first transmission gate switch group and a second low-dropout linear regulator;
  • the second bandgap reference circuit is connected to the first a transmission gate switch group, the first transmission gate switch group is respectively connected to the output end of the decoding and logic control circuit and the input end of the second low dropout linear regulator, the second low dropout linear regulator
  • the output terminal of the comparator is correspondingly connected to the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator.
  • the second bandgap reference circuit generates voltages with different values and different temperature coefficients through a first resistor divider network composed of a plurality of fourth resistors in series, and each voltage is correspondingly connected to the first transmission gate switch A transmission gate switch in a group.
  • the second low-dropout linear regulator includes an error amplifier, a power tube, a second resistor divider network and a third resistor divider network; the non-inverting input end of the error amplifier is connected to the first a transmission gate switch group, the inverting input end of the error amplifier is connected to one end of the second resistor divider network and the third resistor divider network, and the other end of the second resistor divider network is connected to the power The drain of the tube, and the output end of the error amplifier is connected to the gate of the power tube.
  • the clock absolute accuracy trimming circuit includes a first programmable current source, a second programmable current source, a second transmission gate switch group and a third transmission gate switch group; the first programmable current source
  • the output terminal of the voltage regulator source module is connected to the second programmable current source through the first current mirror circuit and the second current mirror circuit correspondingly, and the first programmable current source is connected to the second transmission gate switch.
  • the second programmable current source is connected to the third transmission gate switch group, and the second transmission gate switch group and the third transmission gate switch group are respectively connected to the output ends of the decoding and logic control circuits .
  • the first programmable current source is composed of a plurality of third PMOS transistors, and the gate of each of the third PMOS transistors is respectively connected to the output end of the voltage-to-current circuit through the first current mirror circuit , the drain of each of the third PMOS transistors is respectively connected to a second transmission gate switch in the second transmission gate switch group;
  • the second programmable current source is composed of a plurality of third NMOS transistors, and the gate of each third NMOS transistor is respectively connected to the output end of the voltage-to-current circuit through the second current mirror circuit.
  • the drains of the third NMOS transistors are respectively connected to a third transmission gate switch in the third transmission gate switch group.
  • an integrated circuit chip is provided, and the integrated circuit chip includes the above-mentioned on-chip RC oscillator.
  • a communication terminal including the above-mentioned on-chip RC oscillator.
  • the on-chip RC oscillator, chip, and communication terminal provided by the embodiments of the present invention perform real-time sampling detection on the clock frequency of the oscillator through a frequency sampling and conversion module, convert the sampled clock frequency into a voltage signal, and then perform analog-to-digital conversion. A corresponding digital code is formed, so that when the clock frequency changes, the frequency trimming module circuit converts the digital code into a control signal. Temperature compensation; on the other hand, the RC core oscillator module outputs a zero temperature coefficient current of a suitable size for accurate calibration of the clock frequency.
  • FIG. 1 is a circuit schematic block diagram of an on-chip RC oscillator provided by an embodiment of the present invention
  • FIG. 2 is a circuit schematic diagram of a voltage regulator source module in an on-chip RC oscillator provided by an embodiment of the present invention
  • FIG. 3 is a circuit schematic diagram of an RC core oscillator module in an on-chip RC oscillator provided by an embodiment of the present invention
  • FIG. 4 is a circuit schematic diagram of a frequency sampling and conversion module in an on-chip RC oscillator provided by an embodiment of the present invention
  • FIG. 5 is a circuit schematic diagram of a frequency trimming module in an on-chip RC oscillator provided by an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a clock temperature drift trimming circuit in an on-chip RC oscillator provided by an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a clock absolute precision trimming circuit in an on-chip RC oscillator provided by an embodiment of the present invention.
  • an embodiment of the present invention provides an on-chip RC oscillator, including a voltage regulator source module 101, an RC core oscillator module 102, a frequency sampling and conversion module 103, and a frequency trimming module 104;
  • the source module 101 is respectively connected to the RC core oscillator module 102, the frequency sampling and conversion module 103 and the frequency trimming module 104.
  • the output end of the RC core oscillator module 102 is connected to the input end of the frequency sampling and conversion module 103.
  • the frequency sampling and conversion module The output end of 103 is connected to the input end of the frequency trimming module 104 , and the output end of the frequency trimming module 104 is connected to the RC core oscillator module 102 .
  • the voltage stabilization source module 101 is used to generate one or more supply voltages that do not change with the power supply voltage to supply power to other modules of the on-chip RC oscillator.
  • the frequency sampling and conversion module 103 is used to convert the frequency of the clock signal output by the RC core oscillator module 102 sampled in real time into a voltage signal, and perform analog-to-digital conversion to obtain a corresponding digital code.
  • the frequency trimming module 104 is used for receiving the digital code output by the frequency sampling and converting module 103, and according to the preset voltage of the standard temperature coefficient of the on-chip RC oscillator and the zero temperature coefficient current, through the digital code to generate a control signal to control the direction of the frequency.
  • the RC core oscillator module outputs a voltage with a suitable temperature coefficient and a zero temperature coefficient current, so as to realize temperature compensation and precision calibration of the clock frequency output by the RC core oscillator module.
  • the regulated power supply module 101 is used to isolate the external power supply voltage to generate an internal power supply voltage that does not change with the power supply voltage. Using the voltage output by the voltage stabilized source module 101 to supply power to the RC core oscillator module 102 can eliminate non-ideal factors such as disturbance of the external power supply and noise interference, thereby effectively isolating the clock output from the on-chip RC oscillator from fluctuations in the external power supply The effect of signal frequency.
  • the regulated power supply module 101 can be implemented by any voltage regulated circuit, which can be either a linear regulated power supply or a switching power supply circuit.
  • the linear regulated power supply used by the regulated power supply module 101 may include a first bandgap reference circuit 201 , a voltage-to-current circuit 205 , and a first low-dropout linear regulator 200.
  • the first low dropout linear regulator 200 includes an error amplifier 202 , a power transistor 203 and a feedback resistor network 204 .
  • the output end of the first bandgap reference circuit 201 is connected to the non-inverting input end of the error amplifier 202 and the input end of the voltage-to-current circuit 205, the inverting input end of the error amplifier 202 is connected to the feedback resistor network 204, and the output end of the error amplifier 202 is connected to the power
  • the gate of the tube 203, the drain of the power tube 203 and the feedback resistor network 203 are connected together to form the output end of the first low dropout linear regulator 200, which is used to connect the output load.
  • the power supply voltage VDD is respectively connected to the first bandgap reference circuit 201 , the error amplifier 202 and the power transistor 203 .
  • the feedback resistor network 204 is grounded.
  • the feedback resistor network 204 consists of a resistor Rf1 and a resistor Rf2 in series.
  • the voltage-to-current circuit 205 is composed of an operational amplifier, a power tube and a resistor, and the output current provides DC current bias for other modules.
  • the voltage-to-current circuit 205 is an existing mature circuit, and its specific structure and working principle will not be described here.
  • the function of the first bandgap reference circuit 201 is to generate a reference voltage Vref and a bias current, and the reference voltage Vref is used to provide the error amplifier 202 as an input reference voltage.
  • the error amplifier 202, the power transistor 203 and the feedback resistor network 204 form a negative feedback loop to achieve voltage clamping, so that the first low dropout linear regulator 200 generates an internal supply voltage that does not change with the supply voltage.
  • the voltage-to-current circuit 205 is used to provide a zero temperature coefficient current for the frequency sampling and conversion module 103 and the frequency trimming module 104 respectively, so as to reduce the influence of temperature on the clock frequency output by the RC core oscillator module 102 .
  • the RC core oscillator module 102 is used to generate a voltage-controlled or current-controlled clock frequency.
  • the implementation of the RC core oscillator module 102 is various.
  • the RC core oscillator module 102 may be a voltage controlled oscillator structure or a current controlled oscillator structure.
  • the RC core oscillator module 102 may also be a feedback self-excited oscillation circuit composed of resistors, capacitors and amplifiers, and the RC core oscillator module 102 may also be a ring oscillator composed of inverters.
  • the RC core oscillator module 102 includes a first switch tube 301 , a second switch tube 304 , a first capacitor C1 , a first comparator 306 , a second comparator 307 , an RS flip-flop 308 and a buffer circuit 309; the gates of the first switch tube 301 and the second switch tube 304 are respectively connected to the output end of the RS flip-flop 308
  • the drains of the first switch transistor 301 and the second switch transistor 304 are respectively connected to one end of the first bias current I1_302 and the second bias current I2_303 .
  • the other ends of the first bias current I1_302 and the second bias current I2_303 are connected to one end of the first capacitor C1 , the inverting input terminal of the first comparator 306 and the non-inverting input terminal of the second comparator 307 .
  • the non-inverting input terminal of the first comparator 306 and the inverting input terminal of the second comparator 307 are connected to the corresponding voltage output terminals of the frequency adjustment module 104 (as shown in FIG. voltage output terminals VH and VL) of the voltage regulator 605).
  • the output terminals of the first comparator 306 and the second comparator 307 are connected to the corresponding input terminals R and S of the RS flip-flop 308 , and the signal output terminal Q of the RS flip-flop 308 is connected to the input terminal of the buffer circuit 309 .
  • the first comparator 306, the second comparator 307 and the RS flip-flop 308 respectively receive the reset signal.
  • the source of the first switch tube 301 is connected to the power supply voltage, and the source of the second switch tube 304 and the other end of the first capacitor C1 are grounded respectively.
  • the first switch transistor 301 may be implemented by a PMOS transistor, and the second switch transistor 304 may be implemented by an NMOS transistor.
  • the process of generating a current-controlled clock frequency by the RC core oscillator module 102 is as follows: firstly, receiving the initial first bias current I1 and the second bias current I2 provided by the first bandgap reference circuit 201 of the voltage regulator source module 101 , The first switch tube 301 and the second switch tube 304 respectively control the first bias current I1_302 and the second bias current I2_303 to charge and discharge the first capacitor C1, and the voltage VC1 generated on the first capacitor C1 passes through the first
  • the comparator 306 and the second comparator 307 compare with the corresponding first reference voltage VH and the second reference voltage VL, and continuously output high and low levels to the RS flip-flop 308 in an alternate manner, so that the RS flip-flop 308 outputs 0 or to a logic high and low level of 1 to control the first switch tube 301 and the second switch tube 304 to be alternately on and off, thereby controlling the first bias current I1_302 and the second bias current I2_303 to continuously charge the first capacitor C
  • the buffer circuit 309 drives and shapes the clock signal, so that the RC core oscillator module 102 can output a clock signal with a certain frequency.
  • the reset signal controls the enabling of the first comparator 306, the second comparator 307 and the RS flip-flop.
  • the first capacitor C1 is charged by the first bias current I1_302 at this time, and the voltage VC1 at the capacitor end is respectively output to the first capacitor C1.
  • a comparator 306 and a second comparator 307 if the voltage VC1 is greater than or less than the first reference voltage VH, the voltage output by the first comparator 306 will jump correspondingly; similarly, when the second switch tube 304 is in the In the on state, the first switch tube 302 is in the off state, at this time the first capacitor C1 is discharged, and the voltage VC1 of the capacitor terminal is output to the first comparator 306 and the second comparator 307 respectively. If the reference voltage VL is two, the voltage output by the second comparator 307 will jump correspondingly, so that the voltage output by the first comparator 306 and the second comparator 307 will alternate between high and low levels, thereby generating a clock signal .
  • the charging and discharging time of the first capacitor C1 is determined by the impedance of the first switch tube 301 and the second switch tube 304, the first bias The set current I1_302, the second bias current I2_303 and the first capacitance value of the first capacitor C1 are determined, while the impedances of the first switch tube 301 and the second switch tube 304 and the first capacitance value of the first capacitor C1 are fixed values, Therefore, by adjusting the first bias current I1_302 and the second bias current I2_303, the precision calibration of the frequency of the clock signal output by the RC core oscillator module can be achieved.
  • the temperature coefficients corresponding to the first reference voltage VH and the second reference voltage VL determine the temperature characteristics of the frequency of the clock signal output by the RC core oscillator module, by adjusting the temperature coefficients corresponding to the first reference voltage VH and the second reference voltage VL , which can realize temperature compensation for the frequency of the clock signal output by the RC core oscillator module 102
  • the voltage stabilization circuit adopted by the voltage stabilization source module 101 cannot provide the first bias current I1_302 and the second bias current I2_303 to the RC core oscillator module 102 , it can be used in the voltage stabilization source module 101 at this time.
  • a self-bias current generating circuit is added to provide the RC core oscillator module 102 with the first bias current I1 and the second bias current I2.
  • the frequency sampling and conversion module 103 includes a frequency sampling module 105 and an analog-to-digital conversion module 106.
  • the input end of the frequency sampling module 105 is connected to the output end of the RC core oscillator module 102, and the output end of the frequency sampling module 105 is connected to The input end of the analog-to-digital conversion module 106 and the output end of the analog-to-digital conversion module 106 are connected to the input end of the frequency trimming module 104 .
  • the frequency sampling module 105 is used to sample the frequency of the clock signal output by the RC core oscillator module 102 in real time, and convert the sampled frequency into a voltage signal.
  • the frequency sampling module 105 includes a two-phase non-overlapping clock generating circuit 402, a switched capacitor resistor 403 and a proportional amplifier 404 with the same voltage; the input end of the two-phase non-overlapping clock generating circuit 402 is connected to the RC core oscillator
  • the output terminal of the module 102, the output terminal of the two-phase non-overlapping clock generation circuit 402 is connected to the switched capacitor resistor 403, and the switched capacitor resistor 403 is respectively connected to the zero temperature current source IZTC and the input terminal of the same-phase proportional amplifier 404, and the voltage is the same as the phase proportional amplifier 404
  • the output end of the A/D converter is connected to the analog-to-digital conversion module 405 .
  • the switched capacitor resistor 403 includes a first NMOS transistor 406 , a second NMOS transistor 407 and a second capacitor CR; wherein the gates of the first NMOS transistor 406 and the second NMOS transistor 407 are respectively connected
  • the output terminal of the two-phase non-overlapping clock generation circuit 402, the source of the first NMOS transistor 406 is connected to the zero temperature current source IZTC, the zero temperature coefficient current IZTC makes the clock signal frequency of the sampling RC core oscillator module 102 affected by temperature small to ensure the accuracy of frequency sampling.
  • the drain of the first NMOS transistor 406 and the source of the second NMOS transistor 407 are respectively connected to one end of the second capacitor CR, the other end of the second capacitor CR is grounded, and the drain of the second NMOS transistor 407 is connected to the same voltage as that of the proportional amplifier 404 . input.
  • the voltage in-phase proportional amplifier 404 includes a first operational amplifier 408 , a first resistor Rf and a second resistor R1 ; the non-inverting input terminal of the first operational amplifier 408 is connected to the drain of the second NMOS transistor 407 of the switched capacitor resistor 403
  • the inverting input terminals of the first operational amplifier 408 are respectively connected to one end of the first resistor Rf and the second resistor R1, the other end of the first resistor Rf is grounded, and the other end of the second resistor R1 is respectively connected to the output of the first operational amplifier 408 terminal and analog-to-digital conversion module 405.
  • the process in which the frequency sampling module 105 converts the frequency of the clock signal output by the real-time sampling RC core oscillator module 102 into a voltage signal is as follows: the clock signal Vosc output by the RC core oscillator module 102 is generated by the two-phase non-overlapping clock generation circuit 402 The continuous high and low levels are used to control the on-off of the first NMOS transistor 406 and the second NMOS transistor 407, so as to realize the charging and discharging of the second capacitor CR to generate the equivalent resistance value R of the sampled clock signal, assuming RC
  • the oscillation period of the clock signal Vosc output by the core oscillator module 102 is T, then the equivalent resistance value of the clock signal corresponding voltage
  • CR is the capacitance value of the second capacitor CR
  • IZTC is zero temperature coefficient current.
  • the purpose of converting the frequency of the clock signal output by the RC core oscillator module 102 into the magnitude of the voltage VR is achieved.
  • the voltage is converted into VR to zoom in, magnification
  • the analog-to-digital conversion module can be implemented by using an existing analog-to-digital conversion chip.
  • the analog-to-digital conversion chip is used to convert the amplified voltage VR output by the frequency sampling module 105 into digital codes D0, . . . , Dn (composed of high and low levels of 0 and 1).
  • the conversion number and conversion accuracy of the analog-to-digital conversion chip determine the temperature compensation and calibration accuracy of the frequency of the clock signal output by the frequency trimming module 104 to the RC core oscillator module. Choose the appropriate analog-to-digital conversion chip for accuracy.
  • the frequency trimming module 104 includes a decoding and logic control circuit 502 , a clock temperature drift trimming circuit 503 , and a clock absolute precision trimming circuit 504 ; the input end of the decoding and logic control circuit 502 is connected to an analog-to-digital converter
  • the output terminal of the module 405, the output terminal of the decoding and logic control circuit 502 is connected to the input terminal of the clock temperature drift trimming circuit 503 and the clock absolute accuracy trimming circuit 504, and the clock temperature drift trimming circuit 503 is connected to the RC core oscillator module 102.
  • the output end of the clock absolute accuracy trimming circuit 504 is connected to the first bias current I1_302 and the second bias current I2_303 of the RC core oscillator module 102 .
  • the digital code output by the analog-to-digital conversion module 405 is converted into high and low level digital control signals Bit ⁇ n:0> and Bit ⁇ m:0> by the decoding and logic control circuit 502 , where m and n represent the number of bits.
  • the control signal Bit ⁇ n:0> is used to control the clock temperature drift trimming circuit 503 to provide the RC core oscillator module 102 with the corresponding temperature coefficient corresponding to the required temperature coefficient according to the preset voltage of the standard temperature coefficient of the on-chip RC oscillator.
  • the first reference voltage VH and the second reference voltage VL are used to adjust the temperature characteristics of the frequency of the clock signal output by the RC core oscillator module 102 .
  • the control signal Bit ⁇ m:0> is used to control the clock absolute accuracy trimming circuit 504 to provide the first zero temperature coefficient current I3 and
  • the second zero temperature coefficient current I4 is used to adjust the absolute accuracy of the frequency of the clock signal output by the RC core oscillator module 102 .
  • the clock temperature drift trimming circuit 503 includes a second bandgap reference circuit 601, a first transmission gate switch group 604 and a second low-dropout linear regulator 605; the second bandgap reference circuit 601 is connected to the first The transmission gate switch group 604, the first transmission gate switch group 604 is respectively connected to the output terminal of the decoding and logic control circuit 502 and the input terminal of the second low dropout linear regulator 605, and the output of the second low dropout linear regulator 605
  • the terminals are correspondingly connected to the non-inverting input terminal of the first comparator 306 and the inverting input terminal of the second comparator 307 of the RC core oscillator module 102 .
  • the second bandgap reference circuit 601 includes a first PMOS transistor 607 , a second PMOS transistor 608 , a first transistor 609 , a second transistor 610 , a second operational amplifier 611 and a first resistor divider voltage network 606; the drain of the first PMOS transistor 607 and the emitter of the first transistor 609 are respectively connected to the inverting input of the second operational amplifier 611, and the non-inverting input of the second operational amplifier 611 is connected to the first One end of a resistor divider network 606 is connected to the emitter of the second transistor 610 through a third resistor R3 on the other hand, and the other end of the first resistor divider network 606 is connected to the drain of the second PMOS transistor 608 .
  • the output end of the operational amplifier 611 is connected to the gates of the first PMOS transistor 607 and the second PMOS transistor 608 , the first resistor divider network 606 is connected to the first transmission gate switch group 604 ;
  • the sources are respectively connected to the power supply voltage, and the bases and collectors of the first triode 609 and the second triode 610 are grounded respectively.
  • the first PMOS transistor 607 , the second PMOS transistor 608 , the first transistor 609 , the second transistor 610 , and the second operational amplifier 611 constitute a typical basic structure of the first bandgap reference circuit 201 . Therefore, the second bandgap reference circuit 601 may be formed by connecting the first bandgap reference circuit 201 and the first resistor divider network 606 .
  • the first resistor divider network 606 is composed of a plurality of fourth resistors connected in series, and is used to generate voltages Vbg1 , . . . , Vbgn with different values and different temperature coefficients.
  • the first transfer gate switch group 604 includes a plurality of first transfer gate switches. The number of the first transmission gate switches is the same as the number of the voltages Vbg with different values and different temperature coefficients generated by the first resistive voltage divider network 606 , and they correspond one-to-one.
  • each fourth resistor Two ends of each fourth resistor are respectively connected to a first transmission gate switch, that is, each voltage with a fixed value and a fixed temperature coefficient output by the first resistance voltage divider network 606 corresponds to a first transmission gate switch.
  • a first transmission gate switch that is, each voltage with a fixed value and a fixed temperature coefficient output by the first resistance voltage divider network 606 corresponds to a first transmission gate switch.
  • the voltage regulator 605 outputs a voltage Vref_TCF with a suitable temperature coefficient, and the voltage Vref_TCF is used as a reference voltage for the second low dropout linear regulator 605 to make the second low dropout linear regulator 605 output the first reference voltage VH with a suitable temperature coefficient and the second reference voltage VL to the RC core oscillator module 102, so as to adjust the temperature characteristics of the clock signal output by the RC core oscillator module 102 by adjusting the first reference voltage VH and the second reference voltage VL.
  • the second low dropout linear regulator 605 includes an error amplifier 612 , a power transistor 613 , a second resistor divider network 614 and a third resistor divider network 615 .
  • the non-inverting input terminal of the error amplifier 612 is connected to the first transmission gate switch group 604, the inverting input terminal of the error amplifier 612 is connected to the second resistor divider network 614 and one end of the third resistor divider network 615, and the second resistor divider network 615.
  • the other end of 614 is connected to the drain of the power transistor 613, the other end of the third resistor divider network 615 is grounded, the output end of the error amplifier 612 is connected to the gate of the power transistor 613, and the source of the power transistor 613 is connected to the power supply voltage.
  • the power transistor 613 forms a negative feedback loop with the second resistor divider network 614 and the third resistor divider network 615, respectively, to realize voltage clamping, so that the second low dropout linear regulator 605 outputs a suitable temperature
  • the first reference voltage VH and the second reference voltage VL of the coefficient are sent to the RC core oscillator module 102 to adjust the temperature characteristics of the clock signal output by the RC core oscillator module 102, thereby realizing the output of the clock signal to the RC core oscillator module 102.
  • the temperature change of the frequency is compensated in real time by closed-loop, so that the frequency of the clock signal output by the RC oscillator is almost unchanged with the temperature.
  • the second resistor divider network 614 and the third resistor divider network 615 are respectively composed of resistors connected in series.
  • the number of resistors in the second resistor divider network 614 and the third resistor divider network 615 is determined according to the actual required temperature coefficients of the first reference voltage VH and the second reference voltage VL.
  • the clock absolute accuracy trimming circuit 504 includes a first programmable current source 702 , a second programmable current source 703 , a second transmission gate switch group 704 and a third transmission gate switch group 705 ;
  • the current source 702 and the second programmable current source 703 are respectively connected to the output terminals of the voltage-to-current circuit 205 through the first current mirror circuit 706 and the second current mirror circuit 707 to receive the zero temperature output by the voltage-to-current circuit 205 respectively.
  • the first programmable current source 702 is connected to the second transmission gate switch group 704, the second programmable current source 703 is connected to the third transmission gate switch group 705, the second transmission gate switch group 704 and the third transmission gate switch group 705 is connected to the output terminals of the decoding and logic control circuit 502, respectively.
  • the first programmable current source 702 is composed of a plurality of third PMOS transistors for generating different first zero temperature coefficient currents I3.
  • the second transfer gate switch group 704 includes a plurality of second transfer gate switches.
  • the gate of each third PMOS transistor is connected to the output terminal of the voltage-to-current circuit 205 through the first current mirror circuit 706 respectively, and the drain of each third PMOS transistor is respectively connected to a second transmission gate switch, that is, the first programmable
  • Each first zero temperature coefficient current I3 output by the current source 702 corresponds to a second transmission gate switch.
  • the second programmable current source 703 is composed of a plurality of third NMOS transistors for generating different second zero temperature coefficient currents I4 .
  • the third transfer gate switch group 705 includes a plurality of third transfer gate switches. The gate of each third NMOS transistor is connected to the output terminal of the voltage-to-current circuit 205 through the second current mirror circuit 707, and the drain of each third NMOS transistor is respectively connected to a third transmission gate switch, that is, the second programmable Each second zero temperature coefficient current I4 output by the current source 703 corresponds to a third transmission gate switch.
  • the number of second transmission gate switches, the number of third transmission gate switches, the number of the first zero temperature coefficient current I3 generated by the first programmable current source 702 and the second zero temperature generated by the second programmable current source 703 The number of coefficient currents I4 is the same, one-to-one correspondence.
  • the digital code corresponding to the frequency of the clock signal changes accordingly.
  • the transmission gate switch provides the first zero temperature coefficient current I3 and the second zero temperature coefficient current I4 with appropriate magnitudes to the RC core oscillator module 102 as the charging and discharging currents in the RC core oscillator module, so as to realize the adjustment of the first zero temperature coefficient current by adjusting the first zero temperature coefficient current I4.
  • the absolute values of the temperature coefficient current I3 and the second zero temperature coefficient current I4 are used to adjust the absolute accuracy of the frequency of the clock signal output by the RC core oscillator module 102, thereby realizing the calibration of the absolute accuracy of the frequency of the RC oscillator output clock signal .
  • the on-chip RC oscillator provided in the embodiments of the present invention may be used in an integrated circuit chip.
  • the specific structure of the on-chip RC oscillator in the integrated circuit chip will not be described in detail here.
  • the above-mentioned on-chip RC oscillator can also be used in a communication terminal as an important part of an analog integrated circuit.
  • the communication terminal mentioned here refers to the computer equipment that can be used in the mobile environment and supports various communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, etc., including mobile phones, notebook computers, tablet computers, car computers, etc.
  • GSM Global System for Mobile communications
  • EDGE TD_SCDMA
  • TDD_LTE Time Division Duplex
  • FDD_LTE Frequency Division Duplex
  • the technical solutions provided by the present invention are also applicable to other analog integrated circuit applications, such as communication base stations and the like.
  • the on-chip RC oscillator, chip, and communication terminal provided in the embodiment of the present invention perform real-time sampling detection on the clock frequency of the oscillator through a frequency sampling and conversion module, and convert the sampled clock frequency into voltage for analog-to-digital conversion into phase.
  • the corresponding digital code so that when the clock frequency changes, the frequency trimming module circuit converts the digital code into a control signal. Compensation; on the other hand, output a suitable size of zero temperature coefficient current for the RC core oscillator module to achieve the calibration of the clock frequency accuracy. Therefore, by performing closed-loop real-time calibration compensation for the temperature change of the oscillator clock frequency, it can be achieved that the frequency of the oscillator output clock signal is almost constant with temperature.
  • the precision trimming technology is adopted to realize the calibration of the clock frequency precision, which can realize a high-precision on-chip RC oscillator.

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Abstract

本发明公开了一种片内RC振荡器、芯片及通信终端。该片内RC振荡器包括稳压源模块、RC核心振荡器模块、频率采样与转换模块和频率修调模块。通过频率采样和转换模块对振荡器的时钟频率进行实时采样检测，并将采样的时钟频率转换为电压信号，再进行模数转换成相对应的数字码，以便在时钟频率发生变化时，频率修调模块电路将该数字码转换成控制信号，一方面为RC核心振荡器模块输出合适温度系数的电压，以实现对时钟频率进行温度补偿，进而达到振荡器输出时钟频率随温度几乎不变的目的；另一方面为RC核心振荡器模块输出合适大小的零温度系数电流，以便对时钟频率进行精度校准。

Description

一种片内RC振荡器、芯片及通信终端 技术领域
本发明涉及一种片内RC振荡器，同时也涉及包括该片内RC振荡器的集成电路芯片及相应的通信终端，属于模拟集成电路技术领域。
背景技术
随着集成电路工艺的不断发展，以及集成电路系统性能的不断提升，对高精度集成电路提出了新的挑战和机遇。片内RC振荡器在集成电路芯片中被广泛的应用，尤其在混合信号芯片和高端模拟芯片中应用较多。在集成电路芯片内部集成高精度的片内RC振荡器，不仅可以提高系统精度和可靠性，而且可以降低系统成本。在高精度混合信号集成电路芯片中，片内RC振荡器输出时钟信号的质量会影响到模数转换电路的转换精度，同时在其他带有通信接口的集成电路芯片中，集成高精度的片内RC振荡器，可以大幅降低通信接口的误码率，从而大大提高通信接口数据传输的稳定性和可靠性。
在申请号为201710598686.2的中国专利申请中，公开了一种高频低温漂RC振荡器。该振荡器虽然在一定程度上对其频率做了温度修调和精度校准，但是由于其所用的校准电流存在一定的温度系数，因此随着温度变化，该振荡器输出频率的温度特性会产生较大的偏差，另外由于其温度校准采用有源器件(例如NMOSFET)、电阻实现，该电阻阻值具有明显工艺离散度和电气参数依赖，使得振荡器输出频率的精度受到较大的限制。
另外，申请号为201811430806.9的中国专利申请公开了一种可修调高精度RC振荡器。该振荡器实现低温漂的原理是通过调节放大器输出阻抗，引入一部分输入失调电压，通过调节比较器延迟的绝对值，改变其温度系数，补偿后级数字逻辑延迟时间的温度特性。但是，该振荡器由于数字延迟单元本身具有的一定温度特性，导致其输出频率的精度受限，同时输出频率越高，实现难度越大。
发明内容
本发明所要解决的首要技术问题在于提供一种片内RC振荡器。
本发明所要解决的另一技术问题在于提供一种包括该片内RC振荡器的芯片及相应的通信终端。
为了实现上述目的，本发明采用如下的技术方案：
根据本发明实施例的第一方面，提供一种片内RC振荡器，包括稳压源模块、RC核心振荡器模块、频率采样与转换模块和频率修调模块；所述稳压源模块分别连接所述RC核心振荡器模块、所述频率采样与转换模块和所述频率修调模块，所述RC核心振荡器模块的输出端连接所述频率采样与转换模块的输入端，所述频率采样与转换模块的输出端连接所述频率修调模块的输入端，所述频率修调模块的输出端连接所述RC核心振荡器模块；其中，
所述稳压源模块，用于产生不随电源电压变化的供电电压；
所述频率采样与转换模块，用于将实时采样的所述RC核心振荡器模块输出的时钟信号的频率转换为电压信号后，并进行模数转换得到相对应的数字码；
所述频率修调模块，用于接收所述数字码，并根据预先设置的所述片内RC振荡器的标准温度系数的电压和零温度系数电流，通过所述数字码产生控制信号控制向所述RC核心振荡器模块输出合适温度系数的电压和零温度系数电流，以实现对所述RC核心振荡器模块输出的时钟信号频率进行温度补偿和精度校准。
其中较优地，当所述RC核心振荡器模块包括第一开关管、第二开关管、第一电容、第一比较器、第二比较器、RS触发器和缓冲电路；所述第一开关管与所述第二开关管的栅极分别连接所述RS触发器的输出端，所述第一开关管与所述第二开关管的漏极分别连接第一偏置电流和第二偏置电流的一端，所述第一偏置电流和所述第二偏置电流的另一端连接所述第一电容的一端、所述第一比较器的反相输入端与所述第二比较器的正相输入端，所述第一比较器的正相输入端、所述第二比较器的反相输入端连接所述频率修调模块的相应电压输出端，所述第一比较器与所述第二比较器的输出端连接所述RS触发器的相应输入端，所述RS触发器的信号输出端连接所述缓冲电路的输入端，所述第一比较器、所述第二比较器以及所述RS触发器分别接收复位信号，所述第一开关管的源极连接电源电压，所述第二开关管的源极与 所述第一电容的另一端分别接地。
其中较优地，所述频率采样与转换模块包括频率采样模块和模数转换模块，所述频率采样模块的输入端连接所述RC核心振荡器模块的输出端，所述频率采样模块的输出端连接所述模数转换模块的输入端，所述模数转换模块的输出端连接所述频率修调模块的输入端。
其中较优地，所述频率采样模块包括两相非交叠时钟产生电路、所述开关电容电阻和所述电压同相比例放大器；所述两相非交叠时钟产生电路的输入端连接所述RC核心振荡器模块的输出端，所述两相非交叠时钟产生电路的输出端连接所述开关电容电阻，所述开关电容电阻分别连接零温度电流源和所述电压同相比例放大器的输入端，所述电压同相比例放大器的输出端连接所述模数转换模块。
其中较优地，所述开关电容电阻包括第一NMOS管、第二NMOS管和第二电容；所述第一NMOS管与所述第二NMOS管的栅极分别连接所述两相非交叠时钟产生电路的输出端，所述第一NMOS管的源极连接零温度电流源，所述第一NMOS管的漏极与所述第二NMOS管的源极分别连接所述第二电容的一端，所述第二电容的另一端接地，所述第二NMOS管的漏极连接所述电压同相比例放大器的输入端。
其中较优地，所述电压同相比例放大器包括第一运算放大器、第一电阻和第二电阻；所述第一运算放大器的同相输入端连接所述第二NMOS管的漏极，所述第一运算放大器的反相输入端连接所述第一电阻和所述第二电阻的一端，所述第一电阻另一端接地，所述第二电阻的另一端分别连接所述第一运算放大器的输出端和所述模数转换模块。
其中较优地，所述频率修调模块包括译码和逻辑控制电路、时钟温漂修调电路和时钟绝对精度修调电路；所述译码和逻辑控制电路的输入端连接所述模数转换模块的输出端，所述译码和逻辑控制电路的输出端分别连接到所述时钟温漂修调电路和所述时钟绝对精度修调电路的输入端，所述时钟温漂修调电路连接所述第一比较器的正相输入端和所述第二比较器的反相输入端，所述时钟绝对精度修调电路的输出端连接至所述第一偏置电流和第二偏置电流。
其中较优地，所述时钟温漂修调电路包括第二带隙基准电路、第一传输门开关组和第二低压差线性稳压器；所述第二带隙基准电路连 接所述第一传输门开关组，所述第一传输门开关组分别连接所述译码和逻辑控制电路的输出端和所述第二低压差线性稳压器的输入端，所述第二低压差线性稳压器的输出端对应连接所述第一比较器的正相输入端和第二比较器的反相输入端。
其中较优地，所述第二带隙基准电路通过由多个第四电阻串联组成的第一电阻分压网络产生不同值不同温度系数的电压，每个电压对应连接所述第一传输门开关组中的一个传输门开关。
其中较优地，所述第二低压差线性稳压器包括误差放大器、功率管、第二电阻分压网络和第三电阻分压网络；所述误差放大器的正相输入端连接所述第一传输门开关组，所述误差放大器的反相输入端连接所述第二电阻分压网络和所述第三电阻分压网络的一端，所述第二电阻分压网络的另一端连接所述功率管的漏极，所述误差放大器的输出端连接所述功率管的栅极。
其中较优地，所述时钟绝对精度修调电路包括第一可编程电流源、第二可编程电流源、第二传输门开关组和第三传输门开关组；所述第一可编程电流源与所述第二可编程电流源通过第一电流镜电路、第二电流镜电路相应的连接所述稳压源模块的输出端，所述第一可编程电流源连接所述第二传输门开关组，所述第二可编程电流源连接所述第三传输门开关组，所述第二传输门开关组和所述第三传输门开关组分别连接所述译码和逻辑控制电路的输出端。
其中较优地，所述第一可编程电流源由多个第三PMOS管组成，每个所述第三PMOS管的栅极分别通过所述第一电流镜电路连接电压转电流电路的输出端，每个所述第三PMOS管的漏极分别连接所述第二传输门开关组中的一个第二传输门开关；
所述第二可编程电流源由多个第三NMOS管组成，每个所述第三NMOS管的栅极分别通过所述第二电流镜电路连接电压转电流电路的输出端，每个所述第三NMOS管的漏极分别连接所述第三传输门开关组中的一个第三传输门开关。
根据本发明实施例的第二方面，提供一种集成电路芯片，所述集成电路芯片包括上述的片内RC振荡器。
根据本发明实施例的第三方面，提供一种通信终端，所述通信终 端包括上述的片内RC振荡器。
本发明实施例提供的片内RC振荡器、芯片及通信终端，通过频率采样和转换模块对振荡器的时钟频率进行实时采样检测，并将采样的时钟频率转换为电压信号，再进行模数转换成相对应的数字码，以便在时钟频率发生变化时，频率修调模块电路将该数字码转换成控制信号，一方面为RC核心振荡器模块输出合适温度系数的电压，以实现对时钟频率进行温度补偿；另一方面为RC核心振荡器模块输出合适大小的零温度系数电流，以便对时钟频率进行精度校准。
附图说明
图1为本发明实施例提供的片内RC振荡器的电路原理框图；
图2为本发明实施例提供的片内RC振荡器中，稳压源模块的电路原理图；
图3为本发明实施例提供的片内RC振荡器中，RC核心振荡器模块的电路原理图；
图4为本发明实施例提供的片内RC振荡器中，频率采样和转换模块的电路原理图；
图5为本发明实施例提供的片内RC振荡器中，频率修调模块的电路原理图；
图6为本发明实施例提供的片内RC振荡器中，时钟温漂修调电路的原理图；
图7为本发明实施例提供的片内RC振荡器中，时钟绝对精度修调电路的原理图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
片内RC振荡器作为一个在高性能集成电路芯片中广泛应用的模块，需要保证其输出的时钟信号频率不但能够克服工艺和电源电压的影响，而且在严苛的温度变化范围内，也依然能够输出精准的频率，为整个系统提供高质量且可靠的时钟信号。为此如图1所示，本发明实施例提供一种片内RC振荡器，包括稳压源模块101、RC核心振荡器模块102、频率采样与转换模块103和频率修调模块104；稳压源模块 101分别连接RC核心振荡器模块102、频率采样与转换模块103和频率修调模块104，RC核心振荡器模块102的输出端连接频率采样与转换模块103的输入端，频率采样与转换模块103的输出端连接频率修调模块104的输入端，频率修调模块104的输出端连接RC核心振荡器模块102。
其中，稳压源模块101，用于产生一个或多个不随电源电压变化的供电电压，对本片内RC振荡器的其它模块供电。
频率采样与转换模块103，用于将实时采样的RC核心振荡器模块102输出的时钟信号的频率转换为电压信号后，并进行模数转换得到相对应的数字码。
频率修调模块104，用于接收频率采样与转换模块103输出的数字码，并根据预先设置的片内RC振荡器的标准温度系数的电压和零温度系数电流，通过数字码产生控制信号控制向RC核心振荡器模块输出合适温度系数的电压和零温度系数电流，以实现对RC核心振荡器模块输出的时钟频率进行温度补偿和精度校准。
稳压源模块101，用于将外部电源电压进行隔离，产生一个不随电源电压变化的内部供电电压。利用稳压源模块101输出的电压给RC核心振荡器模块102进行供电，可以消除外部电源的扰动和噪声干扰等非理想因素，从而实现有效地隔离外部电源波动对片内RC振荡器输出的时钟信号频率的影响。该稳压源模块101可以由任意稳压电路实现，既可以是线性稳压电源，也可以是开关电源电路。
在本发明的一个实施例中，如图2所示，稳压源模块101采用的线性稳压电源可以包括第一带隙基准电路201、电压转电流电路205、第一低压差线性稳压器200。第一低压差线性稳压器200包括误差放大器202，功率管203和反馈电阻网络204。第一带隙基准电路201的输出端连接误差放大器202的同相输入端和电压转电流电路205的输入端，误差放大器202的反相输入端连接反馈电阻网络204，误差放大器202的输出端连接功率管203的栅极，功率管203的漏极与反馈电阻网络203连接在一起后，构成第一低压差线性稳压器200的输出端，用于连接输出负载。电源电压VDD分别连接第一带隙基准电路201、误差放大器202、功率管203。反馈电阻网络204接地。反馈电阻网络 204由电阻Rf1和电阻Rf2串联组成。电压转电流电路205由运算放大器、功率管和电阻组成，其输出的电流为其他模块提供直流电流偏置。该电压转电流电路205为现有成熟电路，在此不再描述其具体结构及工作原理。
其中，第一带隙基准电路201的作用是产生基准电压Vref和偏置电流，基准电压Vref用于提供给误差放大器202做输入参考电压。误差放大器202，功率管203和反馈电阻网络204构成一个负反馈环路，实现电压钳位，从而使得第一低压差线性稳压器200产生一个不随电源电压变化的内部供电电压。电压转电流电路205，用于分别为频率采样与转换模块103和频率修调模块104提供零温度系数电流，以减小温度对RC核心振荡器模块102输出的时钟频率的影响。
RC核心振荡器模块102，用于产生一个受电压控制或者电流控制的时钟频率。该RC核心振荡器模块102的实现方式是多样的。RC核心振荡器模块102可以是电压控制振荡器结构，也可以是电流控制振荡器结构。RC核心振荡器模块102还可以是利用电阻、电容以及放大器构成的反馈自激振荡电路，RC核心振荡器模块102还可以是由反相器组成的环形振荡器。
下面以RC核心振荡器模块102产生一个受电流控制的时钟频率为例进行说明。如图3所示，该RC核心振荡器模块102包括第一开关管301、第二开关管304、第一电容C1、第一比较器306、第二比较器307、RS触发器308和缓冲电路309；第一开关管301与第二开关管304的栅极分别连接RS触发器308的输出端
Figure PCTCN2021130943-appb-000001
第一开关管301与第二开关管304的漏极分别连接第一偏置电流I1_302和第二偏置电流I2_303的一端。第一偏置电流I1_302和第二偏置电流I2_303的另一端连接第一电容C1的一端、第一比较器306的反相输入端与第二比较器307的正相输入端。第一比较器306的正相输入端、第二比较器307的反相输入端连接频率修调模块104的相应电压输出端(如图6示出的频率修调模块104的第二低压差线性稳压器605的电压输出端VH和VL)。第一比较器306与第二比较器307的输出端连接RS触发器308的相应输入端R和S，RS触发器308的信号输出端Q连接缓冲电路309的输入端。第一比较器306、第二比较器307以及RS触发器308分别接收 复位信号。第一开关管301的源极连接电源电压，第二开关管304的源极与第一电容C1的另一端分别接地。其中，第一开关管301可以采用PMOS管实现，第二开关管304可以采用NMOS管实现。
RC核心振荡器模块102产生一个受电流控制的时钟频率的过程为：首先接收稳压源模块101的第一带隙基准电路201提供的初始第一偏置电流I1和第二偏置电流I2，通过第一开关管301与第二开关管304分别控制第一偏置电流I1_302和第二偏置电流I2_303对第一电容C1进行充放电，在第一电容C1上产生的电压VC1分别经过第一比较器306、第二比较器307，并与相应的第一参考电压VH和第二参考电压VL进行比较，以交替方式持续输出高低电平到RS触发器308，使得RS触发器308输出至0或至1的逻辑高低电平以控制第一开关管301与第二开关管304交替处于通断状态，从而控制第一偏置电流I1_302和第二偏置电流I2_303对第一电容C1持续进行充放电，产生的电压VC1分别经过第一比较器306、第二比较器307与相应的参考电压进行比较，如此往复，得到时钟信号。缓冲电路309对该时钟信号进行驱动整形，使得RC核心振荡器模块102能够输出具有一定频率的时钟信号。复位信号控制第一比较器306、第二比较器307和RS触发器的使能。
具体地说，当第一开关管301处于导通状态时，第二开关管304处于截止状态，此时通过第一偏置电流I1_302对第一电容C1进行充电，电容端的电压VC1分别输出到第一比较器306与第二比较器307，如果该电压VC1大于或小于第一参考电压VH，则第一比较器306输出的电压会发生对应的跳变；同理，当第二开关管304处于导通状态时，第一开关管302处于截止状态，此时第一电容C1进行放电，电容端的电压VC1分别输出到第一比较器306与第二比较器307，如果该电压VC1大于或小于第二参考电压VL，则第二比较器307输出的电压会发生对应的跳变，从而使得第一比较器306与第二比较器307输出的电压在高低电平之间交替变化，从而产生时钟信号。
由于RC核心振荡器模块102产生的时钟信号的周期为第一电容C1的充放电时间，该第一电容C1的充放电时间由第一开关管301与第二开关管304的阻抗、第一偏置电流I1_302、第二偏置电流I2_303 以及第一电容C1的第一电容值决定，而第一开关管301与第二开关管304的阻抗、第一电容C1的第一电容值为固定值，因此，通过调整第一偏置电流I1_302和第二偏置电流I2_303，可以实现对RC核心振荡器模块输出的时钟信号的频率的精度校准。
由于第一参考电压VH和第二参考电压VL对应的温度系数决定RC核心振荡器模块输出的时钟信号的频率的温度特性，因此通过调整第一参考电压VH和第二参考电压VL对应的温度系数，可以实现对RC核心振荡器模块102输出的时钟信号的频率的温度补偿
需要说明的是，如果稳压源模块101采用的稳压电路无法向RC核心振荡器模块102提供第一偏置电流I1_302、第二偏置电流I2_303，此时可以采用在稳压源模块101中添加自偏置电流产生电路，从而实现为RC核心振荡器模块102提供第一偏置电流I1、第二偏置电流I2。
如图1所示，频率采样与转换模块103包括频率采样模块105和模数转换模块106，频率采样模块105的输入端连接RC核心振荡器模块102的输出端，频率采样模块105的输出端连接模数转换模块106的输入端，模数转换模块106的输出端连接频率修调模块104的输入端。
频率采样模块105，用于实时采样RC核心振荡器模块102输出的时钟信号的频率，并将采样后的频率转换为电压信号。如图4所示，该频率采样模块105包括两相非交叠时钟产生电路402、开关电容电阻403和电压同相比例放大器404；两相非交叠时钟产生电路402的输入端连接RC核心振荡器模块102的输出端，两相非交叠时钟产生电路402的输出端连接开关电容电阻403，开关电容电阻403分别连接零温度电流源IZTC、电压同相比例放大器404的输入端，电压同相比例放大器404的输出端连接模数转换模块405。
具体地说，如图4所示，开关电容电阻403包括第一NMOS管406、第二NMOS管407和第二电容CR；其中，第一NMOS管406与第二NMOS管407的栅极分别连接两相非交叠时钟产生电路402的输出端，第一NMOS管406的源极连接零温度电流源IZTC，该零温度系数电流IZTC使得采样RC核心振荡器模块102的时钟信号频率受温度的影响小，以保证频率采样的准确性。第一NMOS管406的漏极与第二NMOS管407 的源极分别连接第二电容CR的一端，第二电容CR的另一端接地，第二NMOS管407的漏极连接电压同相比例放大器404的输入端。
如图4所示，电压同相比例放大器404包括第一运算放大器408，第一电阻Rf和第二电阻R1；第一运算放大器408的同相输入端连接开关电容电阻403的第二NMOS管407的漏极，第一运算放大器408的反相输入端分别连接第一电阻Rf和第二电阻R1的一端，第一电阻Rf另一端接地，第二电阻R1的另一端分别连接第一运算放大器408的输出端和模数转换模块405。
频率采样模块105将实时采样的RC核心振荡器模块102输出的时钟信号的频率转换为电压信号的过程为：RC核心振荡器模块102输出的时钟信号Vosc经过两相非交叠时钟产生电路402生成连续的高低电平，用于控制第一NMOS管406、第二NMOS管407的通断，从而实现对第二电容CR的充放电，以产生采样的时钟信号的等效电阻值R，假设RC核心振荡器模块102输出的时钟信号Vosc的振荡周期为T，则该时钟信号的等效电阻值
Figure PCTCN2021130943-appb-000002
对应的电压
Figure PCTCN2021130943-appb-000003
其中，CR为第二电容CR的电容值，IZTC为零温度系数电流。这样就实现了将RC核心振荡器模块102输出的时钟信号的频率转换为电压VR大小的目的，考虑到电压VR的变化幅度和模数转换模块405的精度，因此通过电压同相比例放大器404将电压VR进行放大，放大倍数
Figure PCTCN2021130943-appb-000004
模数转换模块可以采用现有的模数转换芯片实现。该模数转换芯片用于将频率采样模块105输出的经过放大的电压VR转换为数字码D0，……，Dn(由0、1的高低电平组成)。其中，模数转换芯片的转换位数和转换精度决定频率修调模块104对RC核心振荡器模块输出的时钟信号的频率的温度补偿和校准的精度，因此可根据需要的时钟信号温度特性和频率精度选择合适的模数转换芯片。
如图5所示，频率修调模块104包括译码和逻辑控制电路502，时钟温漂修调电路503、时钟绝对精度修调电路504；译码和逻辑控制电路502的输入端连接模数转换模块405的输出端，译码和逻辑控制电路502的输出端连接时钟温漂修调电路503和时钟绝对精度修调电路504的输入端，时钟温漂修调电路503连接RC核心振荡器模块102 的第一比较器306的正相输入端和第二比较器307的反相输入端，
时钟绝对精度修调电路504的输出端连接RC核心振荡器模块102的第一偏置电流I1_302和第二偏置电流I2_303。
模数转换模块405输出的数字码经过译码和逻辑控制电路502转换成高低电平的数字控制信号Bit<n:0>和Bit<m:0>，m、n表示位数。其中，控制信号Bit<n:0>用于根据预先设置的片内RC振荡器的标准温度系数的电压，控制时钟温漂修调电路503向RC核心振荡器模块102提供所需温度系数对应的第一参考电压VH和第二参考电压VL，从而实现对RC核心振荡器模块102输出的时钟信号的频率的温度特性进行修调。
控制信号Bit<m:0>用于根据预先设置的片内RC振荡器的标准零温度系数电流，控制时钟绝对精度修调电路504向RC核心振荡器模块102提供第一零温度系数电流I3和第二零温度系数电流I4，从而实现对RC核心振荡器模块102输出的时钟信号的频率的绝对精度进行修调。
如图6所示，时钟温漂修调电路503包括第二带隙基准电路601、第一传输门开关组604和第二低压差线性稳压器605；第二带隙基准电路601连接第一传输门开关组604，第一传输门开关组604分别连接译码和逻辑控制电路502的输出端和第二低压差线性稳压器605的输入端，第二低压差线性稳压器605的输出端对应连接RC核心振荡器模块102的第一比较器306的正相输入端和第二比较器307的反相输入端。
如图6所示，第二带隙基准电路601包括第一PMOS管607、第二PMOS管608、第一三极管609、第二三极管610、第二运算放大器611和第一电阻分压网络606；第一PMOS管607的漏极和第一三极管609的发射极分别连接第二运算放大器611的反相输入端，第二运算放大器611的正相输入端连接一方面连接第一电阻分压网络606的一端，另一方面通过第三电阻R3连接第二三极管610的发射极，第一电阻分压网络606的另一端连接第二PMOS管608的漏极，第二运算放大器611的输出端连接第一PMOS管607和第二PMOS管608的栅极，第一电阻分压网络606连接第一传输门开关组604；第一PMOS管607和第 二PMOS管608的源极分别连接电源电压，第一三极管609、第二三极管610的基极和集电极分别接地。
需要说明的是，第一PMOS管607、第二PMOS管608、第一三极管609、第二三极管610、第二运算放大器611组成典型的第一带隙基准电路201的基本结构。因此，第二带隙基准电路601可以由第一带隙基准电路201和第一电阻分压网络606连接组成。
其中，如图6所示，第一电阻分压网络606由多个第四电阻串联组成，用于产生不同值不同温度系数的电压Vbg1，……，Vbgn。第一传输门开关组604包括多个第一传输门开关。第一传输门开关的数量与第一电阻分压网络606产生的不同值不同温度系数的电压Vbg的数量相同，一一对应。
每个第四电阻的两端分别对应连接一个第一传输门开关，即第一电阻分压网络606输出的每一个固定值固定温度系数的电压对应一个第一传输门开关。当采样的RC核心振荡器模块102输出的时钟信号的频率因温度、环境等因素发生变化时，使得该时钟信号的频率对应的数字码发生随之变化，根据预先设置的片内RC振荡器的标准温度系数的电压，并通过由数字码经过译码和逻辑控制电路502转换成的高低电平的数字控制信号Bit<n:0>控制相应的第一传输门开关向第二低压差线性稳压器605输出合适温度系数的电压Vref_TCF，该电压Vref_TCF作为第二低压差线性稳压器605的参考电压，用于使得第二低压差线性稳压器605输出合适温度系数的第一参考电压VH和第二参考电压VL到RC核心振荡器模块102，进而实现通过修调第一参考电压VH和第二参考电压VL，以修调RC核心振荡器模块102输出的时钟信号的温度特性。
如图6所示，第二低压差线性稳压器605包括误差放大器612、功率管613、第二电阻分压网络614和第三电阻分压网络615。误差放大器612的正相输入端连接第一传输门开关组604，误差放大器612的反相输入端连接第二电阻分压网络614和第三电阻分压网络615的一端，第二电阻分压网络614的另一端连接功率管613的漏极，第三电阻分压网络615的另一端接地，误差放大器612的输出端连接功率管613的栅极，功率管613的源极连接电源电压。通过误差放大器612， 功率管613分别和第二电阻分压网络614和第三电阻分压网络615构成负反馈环路，实现电压钳位，从而使得第二低压差线性稳压器605输出合适温度系数的第一参考电压VH和第二参考电压VL到RC核心振荡器模块102，以修调RC核心振荡器模块102输出的时钟信号的温度特性，进而实现对RC核心振荡器模块102输出时钟信号频率的温度变化进行闭环实时补偿，以实现RC振荡器输出的时钟信号频率随温度几乎是不变。其中，第二电阻分压网络614和第三电阻分压网络615分别由电阻串联组成。第二电阻分压网络614和第三电阻分压网络615中电阻的数量根据实际所需第一参考电压VH和第二参考电压VL的温度系数而定。
如图7所示，时钟绝对精度修调电路504包括第一可编程电流源702、第二可编程电流源703、第二传输门开关组704和第三传输门开关组705；第一可编程电流源702与第二可编程电流源703通过第一电流镜电路706、第二电流镜电路707相应的连接电压转电流电路205的输出端，用于分别接收电压转电流电路205输出的零温度系数电流ITCF，第一可编程电流源702连接第二传输门开关组704，第二可编程电流源703连接第三传输门开关组705，第二传输门开关组704和第三传输门开关组705分别连接译码和逻辑控制电路502的输出端。
如图7所示，第一可编程电流源702由多个第三PMOS管组成，用于产生不同第一零温度系数电流I3。第二传输门开关组704包括多个第二传输门开关。每个第三PMOS管的栅极分别通过第一电流镜电路706连接电压转电流电路205的输出端，每个第三PMOS管的漏极分别连接一个第二传输门开关，即第一可编程电流源702输出的每一个第一零温度系数电流I3对应一个第二传输门开关。
如图7所示，第二可编程电流源703由多个第三NMOS管组成，用于产生不同第二零温度系数电流I4。第三传输门开关组705包括多个第三传输门开关。每个第三NMOS管的栅极分别通过第二电流镜电路707连接电压转电流电路205的输出端，每个第三NMOS管的漏极分别连接一个第三传输门开关，即第二可编程电流源703输出的每一个第二零温度系数电流I4对应一个第三传输门开关。其中，第二传输门开关的数量、第三传输门开关的数量、第一可编程电流源702产生的第 一零温度系数电流I3的数量以及第二可编程电流源703产生的第二零温度系数电流I4的数量相同，一一对应。
当采样的RC核心振荡器模块102输出的时钟信号的频率发生变化时，使得该时钟信号的频率对应的数字码发生随之变化，根据预先设置的片内RC振荡器的第一零温度系数电流I3和第二零温度系数电流I4，并通过由数字码经过译码和逻辑控制电路502转换成的高低电平的数字控制信号Bit<m:0>控制相应的第二传输门开关和第三传输门开关向RC核心振荡器模块102提供合适大小的第一零温度系数电流I3和第二零温度系数电流I4，作为RC核心振荡器模块中的充放电电流，从而实现通过修调第一零温度系数电流I3和第二零温度系数电流I4的绝对值，以修调RC核心振荡器模块102输出的时钟信号的频率的绝对精度，进而实现对RC振荡器输出时钟信号频率的绝对精度的校准。
另外，本发明实施例中提供的片内RC振荡器可以被用在集成电路芯片中。对于该集成电路芯片中片内RC振荡器的具体结构，在此不再一一详述。
上述片内RC振荡器还可以被用在通信终端中，作为模拟集成电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明所提供的技术方案也适用于其他模拟集成电路应用的场合，例如通信基站等。
本发明实施例中提供的片内RC振荡器、芯片及通信终端，通过频率采样和转换模块对振荡器的时钟频率进行实时采样检测，并将采样的时钟频率转换为电压进行模数转换成相对应的数字码，以便于在时钟频率发生变化时，频率修调模块电路将该数字码转换成控制信号，一方面为RC核心振荡器模块输出合适温度系数的电压，以实现对时钟频率的温度补偿；另一方面为RC核心振荡器模块输出合适大小的零温度系数电流，以实现对时钟频率精度的校准。因此，通过对振荡器时钟频率的温度变化进行闭环实时校准补偿，可以实现振荡器输出时钟信号频率随温度几乎是不变的。同时，采用精度修调技术，以实现对时钟频率精度的校准，可以实现一种高精度的片内RC振荡器。
以上对本发明实施例提供的片内RC振荡器、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (14)

  1. 一种片内RC振荡器，其特征在于包括稳压源模块、RC核心振荡器模块、频率采样与转换模块和频率修调模块；所述稳压源模块分别连接所述RC核心振荡器模块、所述频率采样与转换模块和所述频率修调模块，所述RC核心振荡器模块的输出端连接所述频率采样与转换模块的输入端，所述频率采样与转换模块的输出端连接所述频率修调模块的输入端，所述频率修调模块的输出端连接所述RC核心振荡器模块；其中，
    所述稳压源模块，用于产生不随电源电压变化的供电电压；
    所述频率采样与转换模块，用于将实时采样的所述RC核心振荡器模块输出的时钟信号的频率转换为电压信号后，并进行模数转换得到相对应的数字码；
    所述频率修调模块，用于接收所述数字码，并根据预先设置的所述片内RC振荡器的标准温度系数的电压和零温度系数电流，通过所述数字码产生控制信号控制向所述RC核心振荡器模块输出合适温度系数的电压和零温度系数电流，以实现对所述RC核心振荡器模块输出的时钟信号频率进行温度补偿和精度校准。
  2. 如权利要求1所述的片内RC振荡器，其特征在于：
    所述RC核心振荡器模块包括第一开关管、第二开关管、第一电容、第一比较器、第二比较器、RS触发器和缓冲电路；所述第一开关管与所述第二开关管的栅极分别连接所述RS触发器的输出端，所述第一开关管与所述第二开关管的漏极分别连接第一偏置电流和第二偏置电流的一端，所述第一偏置电流和所述第二偏置电流的另一端连接所述第一电容的一端、所述第一比较器的反相输入端与所述第二比较器的正相输入端，所述第一比较器的正相输入端、所述第二比较器的反相输入端连接所述频率修调模块的相应电压输出端，所述第一比较器与所述第二比较器的输出端连接所述RS触发器的相应输入端，所述RS触发器的信号输出端连接所述缓冲电路的输入端，所述第一比较器、所述第二比较器以及所述RS触发器分别接收复位信号，所述第一开关管的源极连接电源电压，所述第二开关管的源极与所述第一电容的另一 端分别接地。
  3. 如权利要求1所述的片内RC振荡器，其特征在于：
    所述频率采样与转换模块包括频率采样模块和模数转换模块，所述频率采样模块的输入端连接所述RC核心振荡器模块的输出端，所述频率采样模块的输出端连接所述模数转换模块的输入端，所述模数转换模块的输出端连接所述频率修调模块的输入端。
  4. 如权利要求3所述的片内RC振荡器，其特征在于：
    所述频率采样模块包括两相非交叠时钟产生电路、所述开关电容电阻和所述电压同相比例放大器；所述两相非交叠时钟产生电路的输入端连接所述RC核心振荡器模块的输出端，所述两相非交叠时钟产生电路的输出端连接所述开关电容电阻，所述开关电容电阻分别连接零温度电流源和所述电压同相比例放大器的输入端，所述电压同相比例放大器的输出端连接所述模数转换模块。
  5. 如权利要求4所述的片内RC振荡器，其特征在于：
    所述开关电容电阻包括第一NMOS管、第二NMOS管和第二电容；所述第一NMOS管与所述第二NMOS管的栅极分别连接所述两相非交叠时钟产生电路的输出端，所述第一NMOS管的源极连接零温度电流源，所述第一NMOS管的漏极与所述第二NMOS管的源极分别连接所述第二电容的一端，所述第二电容的另一端接地，所述第二NMOS管的漏极连接所述电压同相比例放大器的输入端。
  6. 如权利要求5所述的片内RC振荡器，其特征在于：
    所述电压同相比例放大器包括第一运算放大器、第一电阻和第二电阻；所述第一运算放大器的同相输入端连接所述第二NMOS管的漏极，所述第一运算放大器的反相输入端连接所述第一电阻和所述第二电阻的一端，所述第一电阻另一端接地，所述第二电阻的另一端分别连接所述第一运算放大器的输出端和所述模数转换模块。
  7. 如权利要求2所述的片内RC振荡器，其特征在于：
    所述频率修调模块包括译码和逻辑控制电路、时钟温漂修调电路和时钟绝对精度修调电路；所述译码和逻辑控制电路的输入端连接所述模数转换模块的输出端，所述译码和逻辑控制电路的输出端分别连接到所述时钟温漂修调电路和所述时钟绝对精度修调电路的输入端， 所述时钟温漂修调电路连接所述第一比较器的正相输入端和所述第二比较器的反相输入端，所述时钟绝对精度修调电路的输出端连接至所述第一偏置电流和第二偏置电流。
  8. 如权利要求7所述的片内RC振荡器，其特征在于：
    所述时钟温漂修调电路包括第二带隙基准电路、第一传输门开关组和第二低压差线性稳压器；所述第二带隙基准电路连接所述第一传输门开关组，所述第一传输门开关组分别连接所述译码和逻辑控制电路的输出端和所述第二低压差线性稳压器的输入端，所述第二低压差线性稳压器的输出端对应连接所述第一比较器的正相输入端和第二比较器的反相输入端。
  9. 如权利要求8所述的片内RC振荡器，其特征在于：
    所述第二带隙基准电路通过由多个第四电阻串联组成的第一电阻分压网络产生不同值不同温度系数的电压，每个电压对应连接所述第一传输门开关组中的一个传输门开关。
  10. 如权利要求9所述的片内RC振荡器，其特征在于：
    所述第二低压差线性稳压器包括误差放大器、功率管、第二电阻分压网络和第三电阻分压网络；所述误差放大器的正相输入端连接所述第一传输门开关组，所述误差放大器的反相输入端连接所述第二电阻分压网络和所述第三电阻分压网络的一端，所述第二电阻分压网络的另一端连接所述功率管的漏极，所述误差放大器的输出端连接所述功率管的栅极。
  11. 如权利要求7所述的片内RC振荡器，其特征在于：
    所述时钟绝对精度修调电路包括第一可编程电流源、第二可编程电流源、第二传输门开关组和第三传输门开关组；所述第一可编程电流源与所述第二可编程电流源通过第一电流镜电路、第二电流镜电路相应的连接所述稳压源模块的输出端，所述第一可编程电流源连接所述第二传输门开关组，所述第二可编程电流源连接所述第三传输门开关组，所述第二传输门开关组和所述第三传输门开关组分别连接所述译码和逻辑控制电路的输出端。
  12. 如权利要求11所述的片内RC振荡器，其特征在于：
    所述第一可编程电流源由多个第三PMOS管组成，每个所述第三 PMOS管的栅极分别通过所述第一电流镜电路连接所述电压转电流电路的输出端，每个所述第三PMOS管的漏极分别连接所述第二传输门开关组中的一个第二传输门开关；
    所述第二可编程电流源由多个第三NMOS管组成，每个所述第三NMOS管的栅极分别通过所述第二电流镜电路连接所述电压转电流电路的输出端，每个所述第三NMOS管的漏极分别连接所述第三传输门开关组中的一个第三传输门开关。
  13. 一种集成电路芯片，其特征在于包括权利要求1～12中任意一项所述的片内RC振荡器。
  14. 一种通信终端，其特征在于包括权利要求1～12中任意一项所述的片内RC振荡器。
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