WO2022089633A1 - 半导体基板及其制造方法和半导体器件结构及其制造方法 - Google Patents

半导体基板及其制造方法和半导体器件结构及其制造方法 Download PDF

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WO2022089633A1
WO2022089633A1 PCT/CN2021/127866 CN2021127866W WO2022089633A1 WO 2022089633 A1 WO2022089633 A1 WO 2022089633A1 CN 2021127866 W CN2021127866 W CN 2021127866W WO 2022089633 A1 WO2022089633 A1 WO 2022089633A1
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Prior art keywords
layer
semiconductor
electrostatic ring
substrate
electrostatic
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PCT/CN2021/127866
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English (en)
French (fr)
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黄河
汪新学
徐海瑛
王敬平
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中芯集成电路（宁波）有限公司上海分公司
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Publication of WO2022089633A1 publication Critical patent/WO2022089633A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the field of semiconductor device manufacturing, in particular to a semiconductor substrate and a manufacturing method thereof, a semiconductor device structure and a manufacturing method thereof.
  • Semiconductor devices are used in various electronic applications such as personal computers, cell phones, digital cameras and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and layers of semiconductor material over a semiconductor substrate, and then patterning the various layers of material using lithography to form circuit components and elements thereon.
  • silicon-on-insulator (SOI) materials Compared with traditional bulk silicon, silicon-on-insulator (SOI) materials have the following advantages: 1. It can realize dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch-up effect in bulk silicon CMOS circuits. 2. It also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short-channel effect, and is especially suitable for low-voltage and low-power circuits.
  • the invention discloses a semiconductor substrate and its manufacturing method, a semiconductor device structure and its manufacturing method, which can solve the problem that when a substrate with an insulating layer in the middle is used, the static charge generated in the etching process cannot be caused by the existence of the insulating layer. Tip discharge problems caused by export.
  • the present invention provides a semiconductor substrate, the semiconductor substrate includes from bottom to top:
  • Projections of the insulating layer and the semiconductor layer in the direction of the surface of the substrate layer are located within the boundary of the substrate layer;
  • an electrostatic ring surrounding the outer periphery of the insulating layer and the semiconductor layer, the inner sidewall of the electrostatic ring is in contact with the outer sidewall of the semiconductor layer, and the bottom of the electrostatic ring extends to the substrate layer;
  • the semiconductor substrate includes a device region and a non-device region, and the electrostatic ring is disposed in the non-device region.
  • the present invention also provides a semiconductor device structure, using the above-mentioned semiconductor substrate, the semiconductor device structure includes:
  • a dielectric layer located on the semiconductor layer and covering the micro device
  • the conductive interconnection structure is arranged in the dielectric layer and connects the electrostatic ring.
  • the present invention also provides a method for manufacturing a semiconductor substrate, comprising:
  • the first substrate including a substrate layer, an insulating layer and a semiconductor layer stacked in sequence from bottom to top;
  • An electrostatic ring is formed at the recess, and the top surface of the electrostatic ring is higher than the bottom surface of the semiconductor layer and at least partially connected to the semiconductor layer.
  • the present invention also provides a method for manufacturing a semiconductor device structure, comprising:
  • the semiconductor substrate adopts the above-mentioned manufacturing method of a semiconductor substrate
  • a conductive interconnect structure is formed in the dielectric layer to connect the electrostatic ring.
  • the semiconductor substrate of the present invention forms an electrostatic ring connecting the substrate layer and the semiconductor layer on the outer periphery of the insulating layer and the semiconductor layer of the semiconductor substrate, and the electrostatic charge generated in the semiconductor layer in the subsequent etching process can enter the substrate layer through the electrostatic ring, Prevent tip discharge.
  • the material of the electrostatic ring is polysilicon, which can be formed by a deposition process, which is convenient for manufacture.
  • the semiconductor device structure of the present invention, the conductive interconnect structure and the electrostatic ring are connected to derive the electrostatic charge generated in the dielectric layer during the manufacturing process.
  • the manufacturing method of the semiconductor substrate of the present invention forms an electrostatic ring through a deposition process, which is compatible with the CMOS process.
  • FIG. 1 shows a schematic structural diagram of a semiconductor substrate of Embodiment 1. As shown in FIG. 1
  • FIG. 2 shows a schematic diagram of the structure of a semiconductor device in Embodiment 2.
  • FIG. 2 shows a schematic diagram of the structure of a semiconductor device in Embodiment 2.
  • FIG. 3 to FIG. 8 are schematic structural diagrams corresponding to different steps of a method for manufacturing a semiconductor substrate according to Embodiment 3.
  • FIG. 3 to FIG. 8 are schematic structural diagrams corresponding to different steps of a method for manufacturing a semiconductor substrate according to Embodiment 3.
  • 9 to 14 are schematic structural diagrams corresponding to different steps of a method for manufacturing a semiconductor substrate according to a modification of the third embodiment.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • a method herein includes a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the steps may be omitted and/or some other steps not described herein may be added to this method. If the components in a certain drawing are the same as the components in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings clearer, this specification will not refer to all the same components. Numbers are attached to each figure.
  • Embodiment 1 of the present invention provides a semiconductor substrate.
  • FIG. 1 shows a schematic structural diagram of the semiconductor substrate of Embodiment 1. Please refer to FIG. 1 , the semiconductor substrate includes from bottom to top:
  • the projections of the insulating layer 11 and the semiconductor layer 12 in the direction of the surface of the substrate layer 10 are located within the boundary of the substrate layer 10;
  • An electrostatic ring 20 surrounds the outer periphery of the insulating layer 11 and the semiconductor layer 12 , and the inner sidewall of the electrostatic ring 20 is at least partially in contact with the outer sidewall of the semiconductor layer 12 , and the bottom of the electrostatic ring 20 is extending to the substrate layer 10;
  • the semiconductor substrate includes a device region and a non-device region, and the electrostatic ring is disposed in the non-device region.
  • the substrate layer 10 , the insulating layer 11 and the semiconductor layer 12 constitute a silicon-on-insulator (SOI) structure, that is, the material of the substrate layer 10 is a semiconductor material, such as silicon, and the material of the insulating layer is silicon dioxide , the material of the semiconductor layer 12 is silicon.
  • SOI silicon-on-insulator
  • the material of the substrate layer 10 is a semiconductor material, such as silicon
  • the material of the insulating layer is silicon dioxide
  • the material of the semiconductor layer 12 is silicon.
  • the outer boundary of the insulating layer 11 and the semiconductor layer 12 is smaller than the boundary of the substrate layer 10 .
  • the electrostatic ring 20 is disposed above the substrate layer 10 beyond the boundary of the insulating layer 11 and the semiconductor layer 12 , and the outer side of the electrostatic ring 20 The projection of the wall and the outer sidewall of the substrate layer 10 in the direction of the surface of the substrate layer 10 is coincident, that is, the outer boundaries of the two are aligned.
  • the inner sidewalls of the electrostatic ring 20 are in contact with the opposite regions of the outer sidewalls of the semiconductor layer 12 .
  • the inner sidewall of the electrostatic ring 20 and the outer sidewall of the semiconductor layer 12 are partially in contact with each other, that is, some areas of the two opposite areas are in contact, and some areas are not in contact.
  • the area where the inner sidewall of the electrostatic ring 20 and the outer sidewall of the semiconductor layer 12 meet is relatively large, it is more beneficial to introduce more and more electrostatic charges generated in the later process into the substrate layer 10 more quickly.
  • the inner sidewall of the electrostatic ring and the outer sidewall of the semiconductor layer are all in contact with each other.
  • the outer sidewall of the insulating layer 12 is also in contact with the inner sidewall of the electrostatic ring 20 .
  • the electrostatic ring 20 is a closed ring, and the width of the electrostatic ring 20 is 0.1 micrometers to 10 micrometers, such as 0.3 micrometers, 1 micrometer, 2 micrometers, or 5 micrometers.
  • the thickness of the electrostatic ring 20 refers to the distance between the inner side wall and the outer side wall of the electrostatic ring. In this embodiment, the thickness of the electrostatic ring 20 is uniformly set everywhere. In other embodiments, the electrostatic ring 20 may also be an intermittent ring, and certainly may be other structural forms except the ring.
  • the electrostatic ring 20 may be a continuous structure or a discontinuous structure.
  • the material of the electrostatic ring can be metal or polysilicon.
  • the bottom of the electrostatic ring 20 is in contact with the surface of the substrate layer 10 . In another embodiment, the bottom of the electrostatic ring 20 extends to a part of the thickness of the substrate layer 10 or through the substrate layer 10 .
  • the semiconductor substrate of the present invention is used to manufacture a plurality of micro-devices thereon, wherein the area where the micro-devices are planned to be formed is the device area, and the area where the micro-devices are not formed is the non-device area.
  • the electrostatic ring 20 is disposed in the non-device area.
  • Embodiment 2 provides a semiconductor device structure.
  • FIG. 2 shows a schematic diagram of the semiconductor device structure of Embodiment 2. Please refer to FIG. 2.
  • the semiconductor device structure includes: the semiconductor substrate in Embodiment 1, and further includes:
  • the dielectric layer 14 is located on the semiconductor layer 12 and covers the micro device 16;
  • the conductive interconnect structure 15 is disposed in the dielectric layer 14 and is connected to the electrostatic ring 20 .
  • the micro-device 16 may be a transistor, such as a diode, a triode or a MOS transistor.
  • the micro device 16 is a MOS transistor, wherein the source electrode and the drain electrode of the MOS transistor are formed in the semiconductor layer 12 , and the gate electrode of the MOS transistor is formed in the dielectric layer 14 .
  • the dielectric layer 16 is also formed with interconnect lines electrically connected to the micro-devices 16 and conductive interconnect structures 15 connected to the electrostatic ring 20 .
  • the conductive interconnection structure 15 is formed on the upper surface of the electrostatic ring 20 and is in the shape of a column.
  • the upper surface of the electrostatic ring 20 may be provided with the conductive interconnect structure 15 , and the conductive interconnect structure 15 may also be provided only on a part of the surface of the electrostatic ring 20 .
  • the material of the conductive interconnect structure includes metals, such as copper, aluminum, gold, etc., and the material of the conductive interconnect structure 15 can also be polysilicon.
  • Embodiment 3 provides a method for manufacturing a semiconductor substrate, comprising the following steps:
  • S01 Provide a first substrate, where the first substrate includes a substrate layer, an insulating layer and a semiconductor layer stacked in sequence from bottom to top;
  • FIG. 3 to FIG. 7 are schematic structural diagrams corresponding to different steps of a method for manufacturing a semiconductor substrate according to Embodiment 3.
  • a first substrate is provided, and the first substrate includes a substrate layer 10 , an insulating layer 11 and a semiconductor layer 12 sequentially stacked from bottom to top.
  • the first substrate is an SOI structure, that is, the material of the substrate layer 10 is a semiconductor material, such as silicon, the material of the insulating layer is silicon dioxide, and the material of the semiconductor layer 12 is silicon.
  • a sacrificial layer 13 is formed on the upper surface of the semiconductor layer 12.
  • the material of the sacrificial layer 13 includes silicon dioxide, silicon nitride or carbon, and the sacrificial layer 13 can be formed by a deposition process.
  • the sacrificial layer 13 serves as an etch stop layer in the later process to prevent over-etching from damaging the upper surface of the semiconductor layer 12 .
  • the sacrificial layer may not be formed in this step, but may be formed in a later process. For details, please refer to the modification of this embodiment.
  • the sacrificial layer 13 , the semiconductor layer 12 and the insulating layer 11 with a set width are removed inward from the boundary of the first substrate to form an annular recess 22 .
  • the set width is 0.1 micrometer to 1 micrometer, such as 0.5 micrometer and 0.8 micrometer.
  • the integrity of the substrate layer 10 remains intact, the edges are not removed, and the bottom surface of the recess 22 is the top surface of the substrate layer 10 .
  • a part of the thickness of the substrate layer 10 on the side close to the insulating layer 11 may also be removed, and at this time, the bottom surface of the recess 22 is lower than the substrate layer 10 in contact with the insulating layer 11 . top.
  • the formed depression 22 is a continuous ring shape.
  • the depression 22 may also be an intermittent ring shape, or the depression 22 is formed only in a certain part of the region.
  • the method for forming the recess 22 is an edge removal process. The edge removal process is to use a dicing knife to cut off the set width of the edge of the wafer. This process is common knowledge in the field and will not be introduced in detail.
  • an electrostatic material layer 21 is formed on the recess and the surface of the sacrificial layer 13 by a deposition process.
  • the material of the electrostatic material layer 21 includes metal or polysilicon.
  • metal it can be It is formed by a physical vapor deposition process.
  • the material of the electrostatic material layer is polysilicon, it is formed by a physical vapor deposition process or a chemical vapor deposition process.
  • the electrostatic material layer above the sacrificial layer 13 and the periphery of the sacrificial layer 13 is removed to form an electrostatic ring including the electrostatic material layer located above the recessed area.
  • the electrostatic material layer above the sacrificial layer 13 may be removed by a grinding process, and then an edge removal process or an etching process may be used to remove the electrostatic material layer on the periphery of the sacrificial layer.
  • the electrostatic material layer may also be removed only by the etching process, and the electrostatic material layer on the periphery of the sacrificial layer may also be removed by the edge trimming process.
  • the top surface of the electrostatic ring is higher than the bottom surface of the semiconductor layer 12 . In an alternative solution, the top surface of the electrostatic ring 20 is flush with the top surface of the semiconductor layer 12 .
  • the sacrificial layer is removed to form a desired semiconductor substrate.
  • the sacrificial layer is removed by a wet etching process.
  • the first step of this modification is the same as the first step of Embodiment 3, and FIG. 3 and Embodiment 3 may be referred to.
  • the semiconductor layer 12 and the insulating layer 11 of a set width are removed inwardly from the boundary of the first substrate to form an annular recess 22 .
  • the set width is 0.1 micrometers to 10 micrometers, for example, 0.5 micrometers, 1 micrometer, 3 micrometers, or 6 micrometers.
  • the integrity of the substrate layer 10 remains intact, the edges are not removed, and the bottom surface of the recess 22 is the top surface of the substrate layer 10 .
  • a part of the thickness of the substrate layer 10 on the side close to the insulating layer 11 may also be removed, and the bottom surface of the recess 22 is lower than the top surface of the substrate layer 10 in contact with the insulating layer 11 .
  • the formed depression 22 is a continuous ring shape.
  • the depression 22 may also be an intermittent ring shape, or the depression 22 is formed only in a certain part of the region.
  • the method for forming the recess 22 is an edge removal process.
  • a sacrificial layer 13 is formed above the recess and above the semiconductor layer 13 , and the material and formation method of the sacrificial layer 13 refer to Embodiment 3, which will not be repeated here.
  • the sacrificial layer material above the recess is removed by an edge removal process, and the sacrificial layer material 13 above the semiconductor layer 12 is retained.
  • an electrostatic material layer 21 is formed over the recessed region and over the sacrificial layer material, and the material and formation method of the electrostatic material layer 21 refer to Embodiment 3.
  • the electrostatic material layer on the periphery of the sacrificial layer 13 is removed by an etching process, so that the top surface of the electrostatic material layer is flush with the top surface of the semiconductor layer, so as to form an electrostatic ring.
  • the sacrificial layer is removed to form the semiconductor substrate.
  • the sacrificial layer is removed by a wet etching process.
  • Embodiment 4 of the present invention provides a method for manufacturing a semiconductor device structure, comprising the following steps:
  • S04 Form a conductive interconnection structure in the dielectric layer to connect the electrostatic ring.
  • FIG. 2 shows a schematic diagram of the structure of a semiconductor device formed by the method of this embodiment.
  • the semiconductor substrate includes a substrate layer 10, an insulating layer 11, a semiconductor layer 12 and an electrostatic ring 20.
  • the semiconductor substrate For the manufacturing method, refer to Embodiment 3 or a modification of Embodiment 3, which will not be repeated here.
  • the micro-devices in this embodiment include transistors, such as diodes, triodes, and MOS tubes. Taking MOS as an example, the source and drain stages of the MOS are formed in the semiconductor layer 12 , and the gate is formed in the dielectric layer 14 above the semiconductor layer 12 . , the dielectric layer 14 is also formed with interconnect lines connecting the micro-devices 16 and a conductive interconnect structure 15 connecting the electrostatic ring 20 .
  • the method for forming the conductive interconnection structure may be: after forming the dielectric layer, forming a through hole penetrating the dielectric layer in the dielectric layer above the electrostatic ring, and the bottom of the through hole exposes the The upper surface of the electrostatic ring or extends into the electrostatic ring; conductive material is formed in the through hole to form the conductive interconnect structure 15 .
  • the material of the conductive interconnect structure 15 includes metal, such as copper, aluminum, gold, etc., and the material of the conductive interconnect structure 15 can also be polysilicon.
  • the shape and the position of the conductive interconnection structure 15 refer to Embodiment 2, and are not repeated here.
  • the method for forming the conductive interconnect structure may also be: after forming the dielectric layer, removing the edge of the dielectric layer with a set width through an edge removal process to expose the electrostatic ring, and applying a deposition process or an electroplating process to the dielectric layer.
  • the conductive interconnect structure is formed on the electrostatic ring.

Abstract

本发明提供了一种半导体基板及其制造方法和半导体器件结构及其制造方法，其中，半导体基板从下至上包括：叠置的衬底层、绝缘层和半导体层；所述绝缘层和所述半导体层在所述衬底层表面方向上的投影位于所述衬底层的边界内；静电环，环绕于所述绝缘层和所述半导体层的外周，且所述静电环的内侧壁与所述半导体层的外侧壁相接，所述静电环的底部延伸至所述衬底层；所述半导体基板包括器件区和非器件区，所述静电环设置于所述非器件区。本发明通过在半导体基板的绝缘层和半导体层的外周形成连接衬底层和半导体层的静电环，在后续刻蚀工艺中在半导体层中产生的静电荷可以通过静电环进入衬底层，防止尖端放电。

Description

半导体基板及其制造方法和半导体器件结构及其制造方法 技术领域
本发明涉及半导体器件制造领域，尤其涉及一种半导体基板及其制造方法和半导体器件结构及其制造方法。
 背景技术
半导体器件用于各种电子应用中，诸如个人电脑、手机、数码相机和其他电子设备。通常通过以下步骤来制造半导体器件:在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导体材料层，然后使用光刻图案化各种材料层以在其上形成电路组件和元件。
绝缘体上硅（SOI）材料相对于传统的体硅有如下优点：1、可以实现集成电路中元器件的介质隔离，彻底消除了体硅CMOS电路中的寄生闩锁效应。2、还具有寄生电容小、集成密度高、速度快、工艺简单、短沟道效应小及特别适用于低压低功耗电路等优势。
 技术问题
但SOI材料由于中间绝缘层的存在，在刻蚀过程中产生的静电荷无法通过体硅导走，极易产生尖端放电现象（称为arcing），导致器件报废，严重影响产线良率。
 技术解决方案
本发明揭示了一种半导体基板及其制造方法和半导体器件结构及其制造方法，能够解决当采用中间带有绝缘层的基板时,由于绝缘层的存在，导致刻蚀过程中产生的静电荷无法导出而引起的尖端放电问题。
为解决上述技术问题，本发明提供了一种半导体基板，所述半导体基板从下至上包括：
叠置的衬底层、绝缘层和半导体层；
所述绝缘层和所述半导体层在所述衬底层表面方向上的投影位于所述衬底层的边界内；
静电环，环绕于所述绝缘层和所述半导体层的外周，且所述静电环的内侧壁与所述半导体层的外侧壁相接，所述静电环的底部延伸至所述衬底层；
所述半导体基板包括器件区和非器件区，所述静电环设置于所述非器件区。
本发明还提供了一种半导体器件结构，利用上述的半导体基板，所述半导体器件结构包括：
微器件，形成于所述半导体层中；
介质层，位于所述半导体层上、覆盖所述微器件；
导电互连结构，设置于所述介质层中，连接所述静电环。
本发明还提供了一种半导体基板的制造方法，包括：
提供第一基板，所述第一基板包括从下至上依次叠置的衬底层、绝缘层和半导体层；
从所述第一基板的边界向内去除设定宽度和厚度的所述第一基板，以在所述第一基板的边缘形成凹陷，所述凹陷的底面延伸至所述衬底层；
在所述凹陷处形成静电环，所述静电环的顶面高于所述半导体层的底面，并与所述半导体层至少部分相接。
本发明还提供了一种半导体器件结构的制造方法，包括：
形成半导体基板，所述半导体基板采用上述的半导体基板的制造方法；
在所述半导体层上形成微器件；
形成介质层，覆盖所述微器件和所述半导体层；
在所述介质层中形成导电互连结构，连接所述静电环。
 有益效果
本发明的有益效果在于：
本发明的半导体基板通过在半导体基板的绝缘层和半导体层的外周形成连接衬底层和半导体层的静电环，在后续刻蚀工艺中在半导体层中产生的静电荷可以通过静电环进入衬底层，防止尖端放电。
进一步地，静电环的材料为多晶硅，可以通过沉积工艺形成，方便制造。
本发明的半导体器件结构，导电互连结构和静电环连接，以导出在制造工艺中产生在介质层中的静电荷。
本发明的半导体基板的制造方法通过沉积工艺形成静电环，与CMOS工艺兼容。
 附图说明
通过结合附图对本发明示例性实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显，在本发明示例性实施例中，相同的参考标号通常代表相同部件。
图1示出了实施例1的一种半导体基板的结构示意图。
图2示出了实施例2中一种半导体器件结构的示意图。
图3至图8示出了实施例3的一种半导体基板的制造方法的不同步骤对应的结构示意图。
图9至图14示出了实施例3变形例的一种半导体基板的制造方法的不同步骤对应的结构示意图。
附图标记说明：
10-衬底层；11-绝缘层；12-半导体层；13-牺牲层；14-介质层；15-导电互连结构；16-微器件；20-静电环；21-静电环材料层。
 本发明的实施方式
以下结合附图和具体实施例对本发明作进一步详细说明。根据下面的说明和附图，本发明的优点和特征将更清楚，然而，需说明的是，本发明技术方案的构思可按照多种不同的形式实施，并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
如果本文的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同，虽然在所有附图中都可轻易辨认出这些构件，但为了使附图的说明更为清楚，本说明书不会将所有相同构件的标号标于每一图中。
实施例 1
本发明实施例1提供了一种半导体基板，图1示出了实施例1的半导体基板的结构示意图，请参考图1，半导体基板从下至上包括：
叠置的衬底层10、绝缘层11和半导体层12；
所述绝缘层11和所述半导体层12在所述衬底层10表面方向上的投影位于所述衬底层10的边界内；
静电环20，环绕于所述绝缘层11和所述半导体层12的外周，且所述静电环20的内侧壁与所述半导体层12的外侧壁至少部分相接，所述静电环20的底部延伸至所述衬底层10；
所述半导体基板包括器件区和非器件区，所述静电环设置于所述非器件区。
具体地，本实施例中，衬底层10、绝缘层11和半导体层12构成了绝缘体上硅结构（SOI），即衬底层10的材料为半导体材料，如硅，绝缘层的材料为二氧化硅，半导体层12的材料为硅。其中绝缘层11和半导体层12的外边界小于衬底层10的边界，本实施例中，静电环20设置于衬底层10超出绝缘层11和半导体层12的边界的上方，且静电环20的外侧壁与所述衬底层10的外侧壁在所述衬底层10表面方向上的投影重合，即两者的外边界相齐。
本实施例中，静电环20的内侧壁与所述半导体层12的外侧壁相对的区域都相接。在另一个实施例中，静电环20的内侧壁与所述半导体层12的外侧壁相对的区域部分相接，即两者相对的区域有的位置相接触，有的位置不相接触。当静电环20的内侧壁与所述半导体层12的外侧壁相接的区域比较大时，更有利于将后期工艺中产生的静电荷更多更快地导入衬底层10中，较好的方式是，静电环的内侧壁与半导体层的外侧壁全部相接。本实施例中，绝缘层12的外侧壁与所述静电环20的内侧壁也相接触。
本实施例中，静电环20为封闭的环形，静电环20的宽度为0.1微米至10微米，如0.3微米、1微米、2微米或5微米等。静电环20的厚度是指静电环内侧壁与外侧壁之间的距离，本实施例中，静电环20的厚度各处均匀设置。在其它实施例中，静电环20还可以是间断的环形，当然也可以是除环形以外的其它结构形式，原理上只要半导体层12和衬底层10通过静电环20相通即可。静电环20可以是连续的结构或间断的结构。静电环的材料可以为金属或多晶硅。
本实施例中，所述静电环20的底部与所述衬底层10的表面相接。在另一个实施例中，所述静电环20的底部延伸至所述衬底层10中的一部分厚度或者贯穿衬底层10。
本发明的半导体基板用于在其上方制造多个微器件，其中规划形成有微器件的区域为器件区，不形成微器件的区域为非器件区域。所述静电环20设置于所述非器件区。
实施例 2
实施例2提供了一种半导体器件架构，图2示出了实施例2的半导体器件结构的示意图，请参考图2，半导体器件结构包括：实施例1中的半导体基板，还包括：
微器件16，形成于所述半导体层12中；
介质层14，位于所述半导体层12上、覆盖所述微器件16；
导电互连结构15，设置于所述介质层14中，连接所述静电环20。
关于半导体基板的结构及材料参照实施例1，此处不再赘述。微器件16可以为晶体管，如二极管、三极管或MOS管。本实施例中，微器件16为MOS管，其中MOS管的源极和漏极形成在半导体层12中，MOS管的栅极形成在介质层14中。介质层16中还形成有电连接微器件16的互连线以及连接于静电环20的导电互连结构15。本实施例中，导电互连结构15形成在静电环20的上表面，为柱状。静电环20的上表面可以均设置有导电互连结构15，导电互连结构15也可以仅设置于静电环20的部分表面。导电互连结构的材料包括金属，如铜、铝、金等，导电互连结构15的材料也可以是多晶硅。当介质层14中由于刻蚀工艺或者其他工艺产生静电荷时，静电荷通过导电互连结构15导入静电环20中，从而导入衬底层10中，防止互连线的尖端放电。
实施例 3
实施例3提供了一种半导体基板的制造方法，包括以下步骤：
S01：提供第一基板，所述第一基板包括从下至上依次叠置的衬底层、绝缘层和半导体层；
S02：从所述第一基板的边界向内去除设定宽度和厚度的所述第一基板，以在所述第一基板的边缘形成凹陷，所述凹陷的底面延伸至所述衬底层；
S03：在所述凹陷处形成静电环，所述静电环的顶面高于所述半导体层的底面，并与所述半导体层至少部分相接。
需要说明的是，本说明书中的S0N不代表制造工艺的先后顺序。
图3至图7示出了实施例3的一种半导体基板的制造方法的不同步骤对应的结构示意图。请参考图3至图7，详细说明各步骤。
参考图3，提供第一基板，所述第一基板包括从下至上依次叠置的衬底层10、绝缘层11和半导体层12。本实施例中，第一基板为SOI结构，即衬底层10的材料为半导体材料，如硅，绝缘层的材料为二氧化硅，半导体层12的材料为硅。
参考图4，在半导体层12的上表面形成牺牲层13，牺牲层13的材料包括二氧化硅，氮化硅或碳，可以通过沉积工艺形成牺牲层13。牺牲层13作为后期工艺中的刻蚀停止层，防止过刻蚀损伤半导体层12的上表面。在另一个实施例中，也可以不在此步骤形成牺牲层，而是在后期工艺中形成，具体情况请参照本实施例的变形例。
参考图5，本实施例中，从所述第一基板的边界向内去除设定宽度的牺牲层13、半导体层12和绝缘层11，以形成环形的凹陷22。本实施例中，设定宽度为0.1微米至1微米，例如0.5微米、0.8微米。本实施例中，衬底层10保留完整性，边缘没有去除，凹陷22的底面即为衬底层10的顶面。在另一个实施例中，也可以去除靠近所述绝缘层11一侧的一部分厚度的衬底层10，此时所述凹陷22的底面低于与所述绝缘层11接触的所述衬底层10的顶面。本实施例中，形成的凹陷22为连续的环形，在另一实施例中，凹陷22也可以是间断的环形，或者只在某一部分区域形成凹陷22。本实施例中，形成凹陷22的方法为去边工艺。去边工艺为用切割刀切掉晶圆边缘的设定宽度，此工艺为本领域的公知常识，不做详细介绍。
参考图6，通过沉积工艺在所述凹陷处和所述牺牲层13的表面上方形成静电材料层21，静电材料层21的材料包括金属或多晶硅，当静电材料层的材料为金属时，可以通过物理气相沉积工艺形成，当静电材料层的材料为多晶硅时，通过物理气相沉积工艺或化学气相沉积工艺形成。
参考图7，去除所述牺牲层13上方及所述牺牲层13外周的所述静电材料层，以形成静电环，所述静电环包括位于所述凹陷区域上方的所述静电材料层。可以采用研磨工艺去除牺牲层13上方的静电材料层，之后采用去边工艺或刻蚀工艺去除牺牲层外周的静电材料层。也可以只用刻蚀工艺去除静电材料层，还可以用边缘修剪工艺去除牺牲层外周的静电材料层。所述静电环的顶面高于所述半导体层12的底面，可选方案中，所述静电环20的顶面与所述半导体层12的顶面齐平。
参考图8，去除牺牲层，形成需要的半导体基板，本实施例中通过湿法腐蚀工艺去除牺牲层。
实施例 3 的变形例
本变形例的第一步骤和实施例3的第一步骤相同，参考图3和实施例3即可。
之后参照图9，从所述第一基板的边界向内去除设定宽度的半导体层12和绝缘层11，以形成环形的凹陷22。本实施例中，设定宽度为0.1微米至10微米，例如0.5微米、1微米、3微米或6微米等。本实施例中，衬底层10保留完整性，边缘没有去除，凹陷22的底面即为衬底层10的顶面。在其它实施例中，也可以去除靠近所述绝缘层11一侧的一部分厚度的衬底层10，所述凹陷22的底面低于与所述绝缘层11接触的所述衬底层10的顶面。本实施例中，形成的凹陷22为连续的环形，在另一实施例中，凹陷22也可以是间断的环形，或者只在某一部分区域形成凹陷22。本实施例中，形成凹陷22的方法为去边工艺。
参考图10，在凹陷的上方和半导体层13的上方形成牺牲层13，牺牲层13的材料和形成方法参照实施例3，此处不在赘述。
参考图11，采用去边工艺去除凹陷上方的牺牲层材料，并保留半导体层12上方的牺牲层材料13。
参考图12，在凹陷区域的上方以及牺牲层材料的上方形成静电材料层21，静电材料层21的材料和形成方法参照实施例3。
参考图13，通过刻蚀工艺去除牺牲层13外周的静电材料层，使静电材料层的顶面与半导体层的顶面齐平，以形成静电环。
参考图14，去除牺牲层，形成所述的半导体基板。本实施例中，通过湿法腐蚀工艺去除牺牲层。
实施例 4
本发明实施例4提供了一种半导体器件结构的制造方法，包括以下步骤：
S01：形成半导体基板，所述半导体基板采用实施例3的制造方法；
S02：在所述半导体层上形成微器件；
S03：形成介质层，覆盖所述微器件和所述半导体层；
S04：在所述介质层中形成导电互连结构，连接所述静电环。
图2示出了采用本实施例的方法形成的半导体器件结构的示意图，半导体基板包括衬底层10、绝缘层11、半导体层12以及静电环20，其具体结构和材料参照实施例1，半导体基板的制造方法参照实施例3或实施例3的变形例，此处不再赘述。本实施例中的微器件包括晶体管，如二极管、三极管、MOS管，以MOS为例，MOS的源级和漏级形成在半导体层12中，栅极形成在半导体层12上方的介质层14中，介质层14还形成有连接微器件16的互连线以及连接静电环20的导电互连结构15。
形成导电互连结构的方法可以为：形成所述介质层后，在所述静电环的上方的所述介质层中形成贯穿所述介质层的通孔，所述通孔的底部暴露出所述静电环的上表面或延伸至所述静电环中；在所述通孔中形成导电材料，以形成所述导电互连结构15。导电互连结构15的材料包括金属，如铜、铝、金等，导电互连结构15的材料也可以是多晶硅。导电互连结构15的形状以及设置的位置参照实施例2，此处不再赘述。
形成导电互连结构的方法还可以为：形成所述介质层后，通过去边工艺去除设定宽度的所述介质层的边缘，以暴露出所述静电环，通过沉积工艺或电镀工艺在所述静电环上形成所述导电互连结构。
 
需要说明的是，本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于结构实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (27)

  1. 一种半导体基板，其特征在于，所述半导体基板从下至上包括：
    叠置的衬底层、绝缘层和半导体层；
    所述绝缘层和所述半导体层在所述衬底层表面方向上的投影位于所述衬底层的边界内；
    静电环，位于所述绝缘层和所述半导体层的外周，且所述静电环的内侧壁与所述半导体层的外侧壁至少部分相接，所述静电环的底部延伸至所述衬底层；
    所述半导体基板包括器件区和非器件区，所述静电环设置于所述非器件区。
  2. 根据权利要求1所述的半导体基板，其特征在于，所述静电环的外侧壁与所述衬底层的外侧壁在所述衬底层表面方向上的投影重合。
  3. 根据权利要求1所述的半导体基板，其特征在于，所述静电环为连续或间断的结构。
  4. 根据权利要求1所述的半导体基板，其特征在于，所述静电环的厚度为0.1微米至10微米。
  5. 根据权利要求1所述的半导体基板，其特征在于，所述静电环的底部与所述衬底层的表面相接或所述静电环的底部至少延伸至所述衬底层的部分厚度。
  6. 根据权利要求1所述的半导体基板，其特征在于，所述静电环的材料包括金属或多晶硅。
  7. 根据权利要求1所述的半导体基板，其特征在于，所述衬底层的材料包括半导体材料，所述绝缘层的材料包括二氧化硅，所述半导体层的材料包括硅。
  8. 根据权利要求1所述的半导体基板，其特征在于，所述绝缘层的外侧壁与所述静电环的内侧壁相接。
  9. 一种半导体器件结构，利用权利要求1至8任一项所述的半导体基板，其特征在于，所述半导体器件结构包括：
    微器件，形成于所述半导体层中；
    介质层，位于所述半导体层上、覆盖所述微器件；
    导电互连结构，设置于所述介质层中，连接所述静电环。
  10. 根据权利要求9所述的半导体器件结构，其特征在于，所述导电互连结构为柱状，设置于所述静电环的上表面。
  11. 根据权利要求9所述的半导体器件结构，其特征在于，所述导电互连结构的材料包括金属、多晶硅 。
  12. 根据权利要求9所述的半导体器件结构，其特征在于，所述导电互连结构的材料包括金属，所述静电环的材料包括多晶硅。
  13. 根据权利要求9所述的半导体器件结构，其特征在于，所述微器件包括晶体管。
  14. 一种半导体基板的制造方法，其特征在于，包括：
    提供第一基板，所述第一基板包括从下至上依次叠置的衬底层、绝缘层和半导体层；
    从所述第一基板的边界向内去除设定宽度和厚度的所述第一基板，以在所述第一基板的边缘形成凹陷，所述凹陷的底面延伸至所述衬底层；
    在所述凹陷处形成静电环，所述静电环的顶面高于所述半导体层的底面，并与所述半导体层至少部分相接。
  15. 根据权利要求14所述的半导体基板的制造方法，其特征在于，所述静电环的顶面与所述半导体层的顶面齐平。
  16. 根据权利要求14所述的半导体基板的制造方法，其特征在于，形成所述凹陷包括：
    去除设定宽度的所述半导体层和所述绝缘层，所述凹陷的底面与所述衬底层的顶面齐平；或，
    去除设定宽度的所述半导体层和所述绝缘层并去除靠近所述绝缘层的一部分厚度的所述衬底层，所述凹陷的底面低于与所述绝缘层接触的所述衬底层的顶面。
  17. 根据权利要求14所述的半导体基板的制造方法，其特征在于，所述设定宽度为0.1微米至1微米。
  18. 根据权利要求14所述的半导体基板的制造方法，其特征在于，通过离子束修剪工艺形成所述凹陷。
  19. 根据权利要求14所述的半导体基板的制造方法，其特征在于，形成所述凹陷之前还包括：
    在所述半导体层上形成牺牲层；形成所述凹陷时还包括去除所述牺牲层的边缘；形成所述静电环后，还包括去除所述牺牲层。
  20. 根据权利要求14所述的半导体基板的制造方法，其特征在于，所述静电环的材料包括金属或多晶硅。
  21. 根据权利要求20所述的半导体基板的制造方法，其特征在于，形成所述静电环包括：
    形成所述凹陷后，在所述凹陷处和所述牺牲层的表面上方形成静电材料层，去除所述牺牲层上方及所述牺牲层外周的所述静电材料层，所述静电环包括位于所述凹陷区域上方的所述静电材料层。
  22. 根据权利要求21所述的半导体基板的制造方法，其特征在于，去除所述牺牲层外周的所述静电材料层的方法包括边缘修剪工艺或刻蚀工艺。
  23. 根据权利要求21所述的半导体基板的制造方法，其特征在于，所述静电材料层的材料包括金属或多晶硅。
  24. 根据权利要求18所述的半导体基板的制造方法，其特征在于，所述静电环为封闭或间断的环形。
  25. 根据权利要求14所述的半导体基板的制造方法，其特征在于，所述衬底层的材料包括半导体材料，所述绝缘层的材料包括二氧化硅，所述半导体层的材料包括硅。
  26. 一种半导体器件结构的制造方法，其特征在于，包括：
    形成半导体基板，所述半导体基板采用权利要求14至25任一项所述的方法；
    在所述半导体层上形成微器件；
    形成介质层，覆盖所述微器件和所述半导体层；
    在所述介质层中形成导电互连结构，连接所述静电环。
  27. 根据权利要求26所述的半导体器件结构的制造方法，其特征在于，形成导电互连结构包括：
    形成所述介质层后，在所述静电环的上方的所述介质层中形成贯穿所述介质层的通孔，所述通孔的底部暴露出所述静电环的上表面或延伸至所述静电环中；
    在所述通孔中形成导电材料，以形成所述导电互连结构；
    或，形成所述介质层后，通过去边工艺去除设定宽度的所述介质层的边缘，以暴露出所述静电环，在所述静电环上形成所述导电互连结构。
PCT/CN2021/127866 2020-10-30 2021-11-01 半导体基板及其制造方法和半导体器件结构及其制造方法 WO2022089633A1 (zh)

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CN109952532A (zh) * 2017-08-08 2019-06-28 京东方科技集团股份有限公司 阵列基板、显示装置和制造阵列基板的方法

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US20010010964A1 (en) * 1999-07-01 2001-08-02 International Business Machines Corporation Method and structure for SOI wafers to avoid electrostatic discharge
CN101465349A (zh) * 2007-12-18 2009-06-24 世界先进积体电路股份有限公司 半导体装置
US20090256202A1 (en) * 2008-04-14 2009-10-15 Abou-Khalil Michel J Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures
CN109952532A (zh) * 2017-08-08 2019-06-28 京东方科技集团股份有限公司 阵列基板、显示装置和制造阵列基板的方法

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