WO2022077986A1 - 半导体结构的制备工艺及半导体结构 - Google Patents

半导体结构的制备工艺及半导体结构 Download PDF

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WO2022077986A1
WO2022077986A1 PCT/CN2021/107135 CN2021107135W WO2022077986A1 WO 2022077986 A1 WO2022077986 A1 WO 2022077986A1 CN 2021107135 W CN2021107135 W CN 2021107135W WO 2022077986 A1 WO2022077986 A1 WO 2022077986A1
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material layer
semiconductor structure
silicon
nitrogen source
nitride material
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PCT/CN2021/107135
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French (fr)
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许俊杰
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长鑫存储技术有限公司
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Priority to US17/487,779 priority Critical patent/US20220115227A1/en
Publication of WO2022077986A1 publication Critical patent/WO2022077986A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Definitions

  • the present disclosure relates to the technical field of semiconductor structures, and in particular, to a preparation process of a semiconductor structure and a semiconductor structure.
  • the nitrogen source eg ammonia, NH 3
  • the nitrogen source at the bottom of the furnace tube has a relatively high concentration due to the machine characteristics of the furnace tube.
  • the plasma deposition of the nitride layer (eg silicon nitride, SiN) is usually achieved by the plasma deposition process in the prior art, in the above deposition process, the plasma further improves the activity of the ammonia gas, which makes semiconductor products, especially
  • the surface of the conductive layer (eg tungsten, W) of the base of the semiconductor product located at the bottom of the furnace tube is more likely to be nitrided, thereby increasing the resistance of the semiconductor product and resulting in poor uniformity of the film resistance.
  • a main purpose of the present disclosure is to overcome at least one of the above-mentioned defects of the prior art, and to provide a fabrication process for a semiconductor structure capable of avoiding the nitridation of the conductive layer during the manufacturing process.
  • Another main purpose of the present disclosure is to overcome at least one of the above-mentioned defects of the prior art, and to provide a semiconductor structure with excellent thin film resistance uniformity.
  • a process for preparing a semiconductor structure includes the following steps:
  • a second nitrogen source is passed through, and a plasma deposition process is used to deposit a second nitride material layer on the surface of the second silicon-containing material layer.
  • a semiconductor structure including a substrate, a metal material layer is provided on the surface of the substrate, and a first nitride material layer and a second nitride material layer are sequentially provided on the surface of the metal material layer. Dinitride material layer, the first nitride material layer is formed by chemical vapor deposition process, and the second nitride material layer is formed by plasma deposition process.
  • the preparation process of the semiconductor structure proposed in the present disclosure adopts the process design of depositing nitride on the surface of the conductive layer by chemical vapor deposition process, and then depositing the nitride by plasma deposition process.
  • the activity is improved due to the influence of the bulk, so that the nitridation of the exposed conductive layer can be avoided.
  • the present disclosure can utilize the silicon-containing material layer covering the surface of the conductive layer through the process design of covering the surface of the conductive layer of the semiconductor structure substrate with the silicon-containing material layer before depositing the nitride, so that the exposed conductive layer can further Avoid nitriding in subsequent nitride deposition processes. Therefore, the preparation process of the semiconductor structure proposed in the present disclosure can avoid the nitridation of the conductive layer, and the semiconductor structure prepared by the preparation process has excellent uniformity of thin film resistance and high product yield.
  • FIG. 1 is a schematic diagram of a semiconductor structure in a step of a manufacturing process of a semiconductor structure according to an exemplary embodiment
  • FIG. 2 is a schematic diagram of a semiconductor structure in another step of a manufacturing process of a semiconductor structure according to an exemplary embodiment
  • FIG. 3 is a schematic diagram of a semiconductor structure in another step of a manufacturing process of a semiconductor structure according to an exemplary embodiment
  • FIG. 4 is a schematic diagram of a semiconductor structure in another step of a manufacturing process of a semiconductor structure according to an exemplary embodiment.
  • FIG. 1 to FIG. 4 respectively represent schematic diagrams of the semiconductor structure in several steps of the fabrication process of the semiconductor structure proposed by the present disclosure.
  • the fabrication process of the semiconductor structure proposed in the present disclosure is described by using a deposition furnace tube to deposit nitride on the surface of the semiconductor structure as an example. It will be easily understood by those skilled in the art that, in order to apply the related designs of the present disclosure to other types of processes, various modifications, additions, substitutions, deletions or other changes may be made to the following specific embodiments. Still within the scope of the principles of the fabrication process of the semiconductor structure presented in this disclosure.
  • the fabrication process of the semiconductor structure proposed by the present disclosure includes the following steps:
  • the second nitrogen source is passed through, and a plasma deposition process is used to deposit a second nitride material layer 142 on the surface of the second silicon-containing material layer.
  • the fabrication process of the semiconductor structure proposed by the present disclosure is to first deposit nitrides on the surface of the conductive layer 120 by chemical vapor deposition, and then deposit nitrides by plasma deposition. The process is not affected by the plasma to increase the activity, so that the exposed conductive layer 120 can be prevented from being nitrided. Furthermore, in the present disclosure, before depositing the nitride, the first silicon-containing material layer 130 is deposited on the surface of the conductive layer 120 of the semiconductor structure substrate 100 to further prevent the conductive layer 120 from being nitrided in the subsequent nitride deposition process.
  • first nitrogen source 220 and the second nitrogen source both as ammonia (NH 3 ) as an example, it has been verified by experiments that during chemical vapor deposition (such as thermal chemical vapor deposition) , which is characterized by a low resistance state and will not produce poor uniformity of the bottom product with the furnace tube. Accordingly, the present disclosure adopts the chemical vapor deposition process without turning on the plasma when starting to deposit the nitride, and turns on the plasma during the subsequent deposition process of the nitride and adopts the plasma deposition process, so that the exposed conductive layer can be effectively prevented 120 is nitrided.
  • chemical vapor deposition such as thermal chemical vapor deposition
  • the present disclosure first feeds the first silicon source 210 of dichlorosilane before depositing the nitride, and covers the surface of the conductive layer 120 with the first silicon source 210 .
  • the silicon-containing material layer 130 can prevent the nitrogen source in the subsequent nitride deposition process from contacting the conductive layer 120 in advance, thereby preventing the conductive layer 120 from being oxidized.
  • the base 100 of the semiconductor structure in this step includes a substrate 110 (eg, a silicon substrate, Si) and a conductive layer 120 (eg, tungsten, W).
  • the conductive layer 120 is located in the substrate 110 , and the conductive layer 120 Parts are exposed in the holes of the substrate 110 .
  • the introduced first silicon source 210 is attached to the surface of the exposed conductive layer 120 to form a first silicon-containing material layer 130 covering the surface of the conductive layer 120 .
  • the first silicon source 210 may be deposited on the surface of the conductive layer 120 by a process such as chemical vapor deposition.
  • the feeding of the first silicon source 210 may be a plurality of cycles. In other embodiments, the supply of the first silicon source 210 may also be a cycle period, which is not limited to this embodiment.
  • the supply of the first silicon source 210 is a process design of multiple cycles.
  • the first silicon source 210 The number of the access circulation cycles can be 3 to 7, for example, 3, 5, 6, 7 and so on. In other embodiments, when the first silicon source 210 is fed for multiple cycles, the number of cycles of the first silicon source 210 can also be less than 3, or can be greater than 7, for example, 2 , 8, etc., are not limited to this embodiment.
  • the first silicon source 210 may include dichlorosilane (DCS for short, chemical formula SiH 2 Cl 2 ).
  • DCS dichlorosilane
  • other silicon-containing compounds can also be used as the first silicon source 210 , such as trichlorosilane (HCl 3 Si), silane (SiH 4 ), or a combination of at least two of the above silicon-containing compounds. , and is not limited to this embodiment.
  • the first nitrogen source 220 is passed through and the first nitride material layer 141 is formed.
  • the introduced first nitrogen source 220 is deposited on the surface of the exposed conductive layer 120 (covered with the first silicon-containing material layer 130 ) by a chemical vapor deposition process to form a nitride material covering the surface of the conductive layer 120 layer, in order to be different from the nitride material layer deposited by the plasma deposition process described below, the nitride material layer deposited in this step is defined as the first nitride material layer 141 .
  • the exposed conductive layer 120 can be further prevented from nitriding reaction due to the deposition of nitride.
  • the flow rate of the first nitrogen source 220 may be 10slm ⁇ 30slm, for example, 10slm, 15slm, 25slm, 30slm, and the like. In other embodiments, the incoming flow rate of the first nitrogen source 220 may also be less than 10 slm, or may be greater than 30 slm, such as 8 slm, 31 slm, etc., which is not limited to this embodiment.
  • the present disclosure can further prevent the conductive layer 120 from being oxidized by reducing the amount of nitrogen source such as ammonia.
  • the incoming flow rate of the first nitrogen source 220 may be 24 slm.
  • the first nitrogen source 220 may include ammonia gas (NH 3 ).
  • NH 3 ammonia gas
  • other nitrogen-containing compounds, such as nitrogen-containing gas may also be used instead of ammonia gas as the first nitrogen source 220, which is not limited to this embodiment.
  • the deposition thickness of the first nitride material layer 141 may be 3 nm ⁇ 15 nm, such as 3 nm, 11 nm, 14 nm, 15 nm, and the like. In other embodiments, the deposition thickness of the first nitride material layer 141 may also be greater than 15 nm, such as 16 nm, etc., which is not limited to this embodiment.
  • the The deposition thickness may be 3 nm to 10 nm.
  • the second silicon source may be deposited on the surface of the first nitride material layer 141 by a process such as chemical vapor deposition.
  • the second silicon source may include dichlorosilane.
  • other silicon-containing compounds can also be used as the second silicon source, such as trichlorosilane, silane, or a combination of at least two of the above-mentioned silicon-containing compounds, which is not limited to this embodiment.
  • the semiconductor structure in this step includes a substrate 110, a conductive layer 120, a first silicon-containing material layer 130, a first nitride material layer 141 and a second silicon-containing material layer (not shown in the figure).
  • the passed second nitrogen source is deposited on the exposed conductive layer 120 through a plasma deposition process (the first silicon-containing material layer 130, the first nitride material layer 141 and the second silicon-containing material layer are deposited in sequence ), a nitrided material layer covering the surface of the conductive layer 120 is formed.
  • the nitrided material layer deposited in this step is defined as the second nitrided material. layer 142 .
  • the flow rate of the second nitrogen source may be 20slm ⁇ 50slm, such as 20slm, 25slm, 40slm, 50slm, and the like. In other embodiments, the incoming flow rate of the second nitrogen source may also be less than 20 slm, or may be greater than 50 slm, such as 18 slm, 31 slm, etc., which is not limited to this embodiment.
  • the incoming flow rate of the second nitrogen source may be greater than the incoming flow rate of the first nitrogen source 220 .
  • the first nitrogen source 220 and the second nitrogen source may be the same.
  • the second nitrogen source may include ammonia gas (NH 3 ).
  • NH 3 ammonia gas
  • other nitrogen-containing compounds such as nitrogen-containing gas, etc., may also be used instead of ammonia gas as the second nitrogen source, which is not limited to this embodiment.
  • the deposition thickness of the second nitride material layer 142 may be 30 nm ⁇ 40 nm, such as 30 nm, 34 nm, 38 nm, 40 nm, and the like. In other embodiments, the deposition thickness of the second nitride material layer 142 may also be less than 30 nm, or may be greater than 40 nm, such as 28 nm, 42 nm, etc., which is not limited to this embodiment.
  • the semiconductor structure proposed by the present disclosure includes a substrate 100 .
  • a metal material layer is provided on the surface of the substrate 100 , and a first nitride material layer 141 and a second nitride material layer 142 are sequentially provided on the surface of the metal material layer.
  • the first nitride material layer 141 is formed by a chemical vapor deposition process
  • the second nitride material layer 142 is formed by a plasma deposition process.
  • the fabrication process of the semiconductor structure proposed in the present disclosure adopts the process design of depositing nitride on the surface of the conductive layer by chemical vapor deposition, and then depositing nitride by plasma deposition. The process is not affected by the plasma to increase the activity, thus avoiding the nitridation of the exposed conductive layer.
  • the present disclosure can utilize the silicon-containing material layer covering the surface of the conductive layer through the process design of covering the surface of the conductive layer of the semiconductor structure substrate with the silicon-containing material layer before depositing the nitride, so that the exposed conductive layer can further Avoid nitriding in subsequent nitride deposition processes. Therefore, the preparation process of the semiconductor structure proposed in the present disclosure can avoid the nitridation of the conductive layer, and the semiconductor structure prepared by the preparation process has excellent uniformity of thin film resistance and high product yield.

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Abstract

本公开提出一种半导体结构的制备工艺及半导体结构，制备工艺包含以下步骤：通入第一硅源，在半导体结构的基底表面沉积形成第一含硅材料层；通入第一氮源，并采用化学气相沉积工艺，在第一含硅材料层表面沉积形成第一氮化材料层；通入第二硅源，在第一氮化材料层表面沉积形成第二含硅材料层；通入第二氮源，并采用等离子体沉积工艺，在第二含硅材料层表面沉积形成第二氮化材料层。本公开采用化学气相沉积与等离子体沉积交替沉积氮化物，在沉积氮化物之前先在导电层表面覆盖含硅材料层，能够进一步避免导电层在之后的沉积氮化物的制程中被氮化。本公开能够避免导电层被氮化，以此制得的半导体结构的薄膜阻值均匀性优良，具有较高的产品良率。

Description

半导体结构的制备工艺及半导体结构
交叉引用
本申请基于申请号为202011097098.9、申请日为2020年10月14日、申请名称为“半导体结构的制备工艺及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及半导体结构技术领域，尤其涉及一种半导体结构的制备工艺及半导体结构。
背景技术
目前，在采用例如沉积炉管的沉积设备实现半导体结构的氮化层沉积的现有工艺中，由于炉管的机台特性，其底部的氮源(例如氨气，NH 3)浓度较高。并且，由于现有工艺中通常采用等离子体沉积工艺实现氮化层(例如氮化硅，SiN)的沉积，在上述沉积过程中，等离子体使得氨气的活性进一步提高，使得半导体产品，特别是位于炉管底部位置的半导体产品的基底的导电层(例如钨，W)的表面更容易被氮化，从而使得半导体产品的阻值增高，产生薄膜阻值均匀性不良。
发明内容
本公开的一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种能够在制程中避免导电层被氮化的半导体结构的制备工艺。
本公开的另一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种薄膜阻值均匀性优良的半导体结构。
为实现上述目的，本公开采用如下技术方案：
根据本公开的一个方面，提供一种半导体结构的制备工艺，其中，所述半导体结构的制备工艺包含以下步骤：
通入第一硅源，在半导体结构的基底表面沉积形成第一含硅材料 层；
通入第一氮源，并采用化学气相沉积工艺，在所述第一含硅材料层表面沉积形成第一氮化材料层；
通入第二硅源，在所述第一氮化材料层表面沉积形成第二含硅材料层；
通入第二氮源，并采用等离子体沉积工艺，在所述第二含硅材料层表面沉积形成第二氮化材料层。
根据本公开的另一个方面，提供一种半导体结构，其中，所述半导体结构包含基底，所述基底表面设置有金属材料层，所述金属材料层表面依次设置有第一氮化材料层和第二氮化材料层，所述第一氮化材料层通过化学气相沉积工艺沉积形成，所述第二氮化材料层通过等离子体沉积工艺形成。
由上述技术方案可知，本公开提出的半导体结构的制备工艺及半导体结构的优点和积极效果在于：
本公开提出的半导体结构的制备工艺，采用先以化学气相沉积工艺在导电层表面沉积氮化物，再以等离子体沉积工艺沉积氮化物的工艺设计，由于氮源在化学气相沉积过程不会受到等离子体影响而使活性提高，因此能够避免裸露的导电层被氮化。并且，本公开通过在沉积氮化物之前，先在半导体结构的基底的导电层表面覆盖含硅材料层的工艺设计，能够利用覆盖在导电层表面的含硅材料层，使得裸露的导电层能够进一步避免在之后的沉积氮化物的制程中被氮化。因此，本公开提出的半导体结构的制备工艺能够避免导电层被氮化，通过该制备工艺制备的半导体结构的薄膜阻值均匀性优良，具有较高的产品良率。
附图说明
通过结合附图考虑以下对本公开的示例性实施方式的详细说明，本公开的各种目标、特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标 记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的制备工艺的一步骤中的半导体结构示意图；
图2是根据一示例性实施方式示出的一种半导体结构的制备工艺的另一步骤中的半导体结构示意图；
图3是根据一示例性实施方式示出的一种半导体结构的制备工艺的另一步骤中的半导体结构示意图；
图4是根据一示例性实施方式示出的一种半导体结构的制备工艺的另一步骤中的半导体结构示意图。
附图标记说明如下：
100.基底；110.衬底；120.导电层；130.第一含硅材料层；141.第一氮化材料层；142.第二氮化材料层；210.第一硅源；220.第一氮源。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，所述附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构、系统和步骤。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中所述的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
参阅图1至图4，其分别代表性地示出了本公开提出的半导体结 构的制备工艺的几个步骤中的半导体结构示意图。在该示例性实施方式中，本公开提出的半导体结构的制备工艺，是以利用沉积炉管在半导体结构表面沉积氮化物为例进行说明的。本领域技术人员容易理解的是，为将本公开的相关设计应用于其他类型的工艺中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的半导体结构的制备工艺的原理的范围内。
如图1至图4所示，在一些实施例中，本公开提出的半导体结构的制备工艺包含以下步骤：
通入第一硅源210，在半导体结构的基底100表面沉积形成第一含硅材料层130；
通入第一氮源220，并采用化学气相沉积工艺，在第一含硅材料层130表面沉积形成第一氮化材料层141；
通入第二硅源，在第一氮化材料层141表面沉积形成第二含硅材料层；
通入第二氮源，并采用等离子体沉积工艺，在第二含硅材料层表面沉积形成第二氮化材料层142。
承上所述，本公开提出的半导体结构的制备工艺，先以化学气相沉积工艺在导电层120表面沉积氮化物，再以等离子体沉积工艺沉积氮化物的工艺设计，由于氮源在化学气相沉积过程不会受到等离子体影响而使活性提高，因此能够避免裸露的导电层120被氮化。并且，本公开在沉积氮化物之前，先在半导体结构的基底100的导电层120表面沉积形成第一含硅材料层130，进一步避免导电层120在之后的沉积氮化物的制程中被氮化。
需说明的是，以上述第一氮源220和第二氮源均为氨气(NH 3)为例，通过实验验证，这类氮源的在化学气相沉积(例如热化学气相沉积)过程中，其特性表现为低阻态且不会随炉管产生底部产品均匀性不良的现象。据此，本公开在开始沉积氮化物时未开启等离子体而采用化学气相沉积工艺，并在氮化物的后续沉积过程中开启等离子体而采用等离子体沉积工艺，从而能够有效地防止裸露的导电层120被 氮化。并且，由于导电层120在未沉积氮化物之前是部分裸露于衬底110，本公开在沉积氮化物之前，先通入二氯硅烷的第一硅源210，而在导电层120表面覆盖第一含硅材料层130，据此能够预先阻止后续氮化物沉积工艺中的氮源与导电层120接触，进而避免导电层120被氧化。
如图1所示，其代表性地示出了在上述“形成第一含硅材料层130”的步骤中，半导体结构的示例性结构。具体而言，在该步骤下的半导体结构的基底100包含衬底110(例如硅衬底，Si)以及导电层120(例如钨，W)，导电层120位于衬底110中，且导电层120部分裸露于衬底110的孔洞中。在此基础上，通入的第一硅源210附着在裸露的导电层120的表面，形成覆盖于导电层120表面的第一含硅材料层130。
在一些实施例中，对于“形成第一含硅材料层130”的步骤而言，第一硅源210可以通过化学气相沉积法等工艺，沉积在导电层120的表面。
在一些实施例中，对于“形成第一含硅材料层130”的步骤而言，第一硅源210的通入可以为多个循环周期。在其他实施方式中，第一硅源210的通入亦可为一个循环周期，并不以本实施方式为限。
一些实施例中，基于第一硅源210的通入为多个循环周期的工艺设计，对于“形成第一含硅材料层130”的步骤而言，在本实施方式中，第一硅源210的通入循环周期的数量可以为3个～7个，例如3个、5个、6个、7个等。在其他实施方式中，当第一硅源210的通入为多个循环周期时，第一硅源210的通入循环周期的数量亦可少于3个，或可大于7个，例如2个、8个等，并不以本实施方式为限。
在示例性实施例中，对于“形成第一含硅材料层130”的步骤而言，第一硅源210可以包含二氯硅烷(dichlorosilane，简称DCS，化学式SiH 2Cl 2)。在其他实施方式中，亦可采用其他含硅化合物作为第一硅源210，例如三氯硅烷(HCl 3Si)、硅烷(SiH 4)，亦可为上述含硅化合物的至少两种的组合物，并不以本实施方式为限。
如图2和图3所示，其代表性地示出了在上述“形成第一氮化材料层141”的步骤中，通入第一氮源220时和形成第一氮化材料层141时的半导体结构的示例性结构。具体而言，在该步骤下的半导体结构包含衬底110、导电层120、第一含硅材料层130(图中未示出)和第一氮化材料层141。在此基础上，通入的第一氮源220通过化学气相沉积工艺沉积在裸露的导电层120(覆盖有第一含硅材料层130)的表面，形成覆盖于导电层120表面的氮化材料层，为区别于下述的通过等离子体沉积工艺沉积的氮化材料层，定义本步骤中沉积的氮化材料层为第一氮化材料层141。其中，在上述沉积过程中，由于裸露的导电层120表面预先覆盖有第一含硅材料层130，因此能够进一步避免裸露的导电层120由于氮化物的沉积而产生氮化反应。
在示例性实施例中，对于“形成第一氮化材料层141”的步骤而言，第一氮源220的通入流量可以为10slm～30slm，例如10slm、15slm、25slm、30slm等。在其他实施方式中，第一氮源220的通入流量亦可小于10slm，或可大于30slm，例如8slm、31slm等，并不以本实施方式为限。通过上述设计，相比于现有工艺中氮源的流量通常为45slm左右的工艺方案，本公开通过减少例如氨气的氮源的用量，能够进一步防止导电层120被氧化。
一些实施例中，基于第一氮源220的通入流量为10slm～30slm的工艺设计，在本实施方式中，第一氮源220的通入流量可以为24slm。
在示例性实施例中，对于“形成第一氮化材料层141”的步骤而言，第一氮源220可以包含氨气(NH 3)。在其他实施方式中，亦可采用其他含氮元素的化合物，例如含氮气体等，替代氨气作为第一氮源220，并不以本实施方式为限。
在示例性实施例中，对于“形成第一氮化材料层141”的步骤而言，第一氮化材料层141的沉积厚度可以为3nm～15nm，例如3nm、11nm、14nm、15nm等。在其他实施方式中，第一氮化材料层141的沉积厚度亦可大于15nm，例如16nm等，并不以本实施方式为限。
如图3所示，在一些实施例中，对于“形成第一氮化材料层141”的步骤而言，对于第一氮化材料层141的位于基底100的沟槽内的部分而言，其沉积厚度可以为3nm～10nm。
在示例性实施例中，对于“形成第二含硅材料层”的步骤而言，第二硅源可以通过化学气相沉积法等工艺，沉积在第一氮化材料层141的表面。
在示例性实施例中，对于“形成第二含硅材料层”的步骤而言，第二硅源可以包含二氯硅烷。在其他实施方式中，亦可采用其他含硅化合物作为第二硅源，例如三氯硅烷、硅烷，亦可为上述含硅化合物的至少两种的组合物，并不以本实施方式为限。
如图4所示，其代表性地示出了在上述“形成第二氮化材料层142”的步骤中，半导体结构的示例性结构。具体而言，在该步骤下的半导体结构包含衬底110、导电层120、第一含硅材料层130、第一氮化材料层141和第二含硅材料层(图中未示出)。在此基础上，通入的第二氮源通过等离子体沉积工艺沉积在裸露的导电层120(依次沉积有第一含硅材料层130、第一氮化材料层141和第二含硅材料层)的表面，形成覆盖于导电层120表面的氮化材料层，为区别于上述的通过化学气相沉积工艺沉积的氮化材料层，定义本步骤中沉积的氮化材料层为第二氮化材料层142。
在示例性实施例中，对于“形成第二氮化材料层142”的步骤而言，第二氮源的通入流量可以为20slm～50slm，例如20slm、25slm、40slm、50slm等。在其他实施方式中，第二氮源的通入流量亦可小于20slm，或可大于50slm，例如18slm、31slm等，并不以本实施方式为限。
在一些实施例中，第二氮源的通入流量可以大于第一氮源220的通入流量。
在一些实施例中，第一氮源220与第二氮源可以相同。
在一些实施例中，对于“形成第二氮化材料层142”的步骤而言，第二氮源可以包含氨气(NH 3)。在其他实施方式中，亦可采用其他含 氮元素的化合物，例如含氮气体等，替代氨气作为第二氮源，并不以本实施方式为限。
在一些实施例中中，对于“形成第二氮化材料层142”的步骤而言，第二氮化材料层142的沉积厚度可以为30nm～40nm，例如30nm、34nm、38nm、40nm等。在其他实施方式中，第二氮化材料层142的沉积厚度亦可小于30nm，或可大于40nm，例如28nm、42nm等，并不以本实施方式为限。
在此应注意，附图中示出而且在本说明书中描述的半导体结构的制备工艺仅仅是能够采用本公开原理的许多种制备工艺中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的半导体结构的制备工艺的任何细节或任何步骤。
基于上述对本公开提出的半导体结构的制备工艺的一示例性实施方式的详细说明，以下将结合图4，对本公开提出的半导体结构的一示例性实施方式进行说明。
如图4所示，在本实施方式中，本公开提出的半导体结构包含基底100。具体而言，基底100表面设置有金属材料层，金属材料层表面依次设置有第一氮化材料层141和第二氮化材料层142。其中，第一氮化材料层141通过化学气相沉积工艺沉积形成，第二氮化材料层142通过等离子体沉积工艺形成。
在此应注意，附图中示出而且在本说明书中描述的半导体结构仅仅是能够采用本公开原理的许多种半导体结构中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的半导体结构的任何细节。
综上所述，本公开提出的半导体结构的制备工艺，采用先以化学气相沉积工艺在导电层表面沉积氮化物，再以等离子体沉积工艺沉积氮化物的工艺设计，由于氮源在化学气相沉积过程不会受到等离子体影响而使活性提高，因此能够避免裸露的导电层被氮化。并且，本公开通过在沉积氮化物之前，先在半导体结构的基底的导电层表面覆盖含硅材料层的工艺设计，能够利用覆盖在导电层表面的含硅材料层， 使得裸露的导电层能够进一步避免在之后的沉积氮化物的制程中被氮化。因此，本公开提出的半导体结构的制备工艺能够避免导电层被氮化，通过该制备工艺制备的半导体结构的薄膜阻值均匀性优良，具有较高的产品良率。
以上详细地描述和/或图示了本公开提出的半导体结构的制备工艺及半导体结构的示例性实施方式。但本公开的实施方式不限于这里所描述的特定实施方式，相反，每个实施方式的组成部分和/或步骤可与这里所描述的其它组成部分和/或步骤独立和分开使用。一个实施方式的每个组成部分和/或每个步骤也可与其它实施方式的其它组成部分和/或步骤结合使用。在介绍这里所描述和/或图示的要素/组成部分/等时，用语“一个”、“一”和“上述”等用以表示存在一个或多个要素/组成部分/等。术语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。此外，权利要求书及说明书中的术语“第一”和“第二”等仅作为标记使用，不是对其对象的数字限制。
虽然已根据不同的特定实施例对本公开提出的半导体结构的制备工艺及半导体结构进行了描述，但本领域技术人员将会认识到可在权利要求的精神和范围内对本公开的实施进行改动。

Claims (10)

  1. 一种半导体结构的制备工艺，包含以下步骤：
    通入第一硅源，在半导体结构的基底表面沉积形成第一含硅材料层；
    通入第一氮源，并采用化学气相沉积工艺，在所述第一含硅材料层表面沉积形成第一氮化材料层；
    通入第二硅源，在所述第一氮化材料层表面沉积形成第二含硅材料层；
    通入第二氮源，并采用等离子体沉积工艺，在所述第二含硅材料层表面沉积形成第二氮化材料层。
  2. 根据权利要求1所述的半导体结构的制备工艺，其中，在形成所述第一含硅材料层的步骤中，是经由多个循环周期通入所述第一硅源。
  3. 根据权利要求2所述的半导体结构的制备工艺，其中，在形成所述第一含硅材料层的步骤中，通入所述第一硅源的循环周期的数量为3个～7个。
  4. 根据权利要求1所述的半导体结构的制备工艺，其中，所述第一硅源包含二氯硅烷、三氯硅烷、硅烷的其中之一或者其中至少两个的组合物；和/或，所述第二硅源包含二氯硅烷、三氯硅烷、硅烷的其中之一或者其中至少两个的组合物。
  5. 根据权利要求1所述的半导体结构的制备工艺，其中，所述第一氮源与所述第二氮源相同，所述第二氮源的流量大于所述第一氮源的流量。
  6. 根据权利要求5所述的半导体结构的制备工艺，其中，所述第一氮源的通入流量为10slm～30slm；和/或，所述第二氮源的通入流量为20slm～50slm。
  7. 根据权利要求5所述的半导体结构的制备工艺，其中，所述第一氮源包含氨气，所述第二氮源包含氨气。
  8. 根据权利要求1所述的半导体结构的制备工艺，其中，所述第一氮化材料层的厚度为3nm～15nm。
  9. 根据权利要求1所述的半导体结构的制备工艺，其中，所述第二氮化材料层的厚度为30nm～40nm。
  10. 一种半导体结构，其中，所述半导体结构包含基底，所述基底表面设置有金属材料层，所述金属材料层表面依次设置有第一氮化材料层和第二氮化材料层，所述第一氮化材料层通过化学气相沉积工艺沉积形成，所述第二氮化材料层通过等离子体沉积工艺形成。
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