WO2022074297A1 - Procédé de fabrication d'une tranche de manipulation de silicium à haute résistivité permettant la formation d'une structure de substrat hybride - Google Patents

Procédé de fabrication d'une tranche de manipulation de silicium à haute résistivité permettant la formation d'une structure de substrat hybride Download PDF

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Publication number
WO2022074297A1
WO2022074297A1 PCT/FI2021/050664 FI2021050664W WO2022074297A1 WO 2022074297 A1 WO2022074297 A1 WO 2022074297A1 FI 2021050664 W FI2021050664 W FI 2021050664W WO 2022074297 A1 WO2022074297 A1 WO 2022074297A1
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WO
WIPO (PCT)
Prior art keywords
wafer
polishing
grinding
controlled
front surface
Prior art date
Application number
PCT/FI2021/050664
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English (en)
Inventor
Päivi SIEVILÄ
Samuli SIEVÄNEN
Jukka-Pekka LÄHTEENMÄKI
Karri MANNERMAA
Joel SALMI
Atte Haapalinna
Original Assignee
Okmetic Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Okmetic Oy filed Critical Okmetic Oy
Priority to JP2023520210A priority Critical patent/JP2023549029A/ja
Priority to EP21877067.5A priority patent/EP4226411A1/fr
Priority to KR1020237012366A priority patent/KR20230080428A/ko
Priority to CN202180069096.5A priority patent/CN116325084A/zh
Publication of WO2022074297A1 publication Critical patent/WO2022074297A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

Definitions

  • the application relates generally to a manufacture method of a high-resistivity silicon handle wafer for enabling a formation of a hybrid substrate structure, a high- resistivity silicon handle wafer, and a hybrid substrate structure.
  • Devices which are manufactured on hybrid wafers, utilize an active layer that is bonded to a single crystal silicon handle wafer and thinned against it.
  • the handle wafer enables to a reliable handling of hybrid material with advanced tools, which are designed for standard silicon wafer processing, and it provides mechanical stability and compatibly with cleanliness and chemicals, which are used in semiconductor manufacturing.
  • One example of such devices is piezoacoustic thin film surface acoustic wave (TF-SAW) filters, which are designed to utilize a thin active layer made of e.g. piezomaterial.
  • TF-SAW piezoacoustic thin film surface acoustic wave
  • Hybrid wafer structures which are used for devices operating at radio frequencies (RF) of several hundreds of MHz to several tens of GHz, require the use of very high resistivity (over 5000 Q-cm) silicon substrates, featured with an additional parasitic current suppression surface passivation layer, in order to minimize an interaction of the RF signal with the handle wafer.
  • RF radio frequencies
  • the performance of these devices is to a large extend limited by by their geometric accuracy.
  • the final device geometry is defined both by the manufacture process of the device and the thickness control of the active layer in a substrate process.
  • the accuracy of the device manufacture process is defined using lithography, the precision achievable with modern processes is very high. This increases the relative importance of active layer thickness variation, as this dimension cannot be controlled in the same manner.
  • TTV total thickness variation
  • the TTV is especially critical when it appears non-circular symmetrically over a wafer surface, as a further rotational active layer thinning process can be relatively easily adjusted in radial direction, but correcting other shapes is much more complicated.
  • One object of the invention is to withdraw drawbacks of known solutions and to provide a manufacture method for a high-resistive, surface-passivated silicon handle wafer that compensates a geometric influence of a produced crystal orientation identifier and enables higher flatness of a 150-200 mm -diameter silicon handle wafer.
  • Such manufactured silicon handle wafer is used in a formation of a hybrid substrate structure and, then, the formed hybrid substrate structure may be used in device manufacture methods, such as front-end and back-end methods, in order to manufacture a semiconductor device (component).
  • One object of the invention is fulfilled by providing a manufacture method, a high- resistivity silicon handle wafer, and a hybrid substrate structure according to the independent claims.
  • Embodiments of the invention are specified by the manufacture method, a high- resistivity silicon handle wafer, and a hybrid substrate structure according to the independent claims.
  • One manufacture method of a high-resistivity silicon handle wafer for enabling a formation of a hybrid substrate structure comprises a step of producing the wafer having a crystal orientation identifier and a certain thickness.
  • the method further comprises a step of thinning the produced wafer from the certain thickness to a desired thickness of the wafer in order to obtain the thinned wafer.
  • the method further comprises a step of providing a surface passivation layer having a certain layer thickness on a front surface of the thinned wafer.
  • the method further comprises a step of polishing the passivation layer from the certain layer thickness to a desired final layer thickness of the passivation layer so that the polished front surface of the wafer enables active layer bonding (bonding of an active layer) in order to form the hybrid substrate structure.
  • the step of thinning comprises a controlled single-side, fixed abrasive grinding of the produced, crystal orientation identifier-comprised wafer with a chuck arrangement, which eliminates at least majority of an effect of noncircular asymmetry caused by the identifier, in order to manufacture the wafer with a desired submicron total thickness variation for enabling the formation of the hybrid substrate structure.
  • One high-resistivity silicon handle wafer for enabling a formation of a hybrid substrate structure is manufactured in accordance with the steps of previous method.
  • One hybrid substrate structure comprises the high-resistivity silicon in accordance with the previous handle wafer.
  • Fig. 1 a-1 b present a flowchart of manufacture method of a handle wafer
  • Fig. 2a-2b present how the handle wafer is processed during the manufacture method
  • Fig. 3a-3b present how an active layer is bonded to the manufactured handle wafer and thinned to form a hybrid substrate structure in a front-end manufacture method
  • Fig. 1 a and 1 b present how steps of manufacture method 100 of a high-resistivity silicon (HRS) handle wafer 230, which is ready (prepared) to be used in a formation (manufacture) of a hybrid substrate structure 336, proceed and, beside the method steps, fig. 2a and 2b how each method step effects to the wafer 230.
  • HRS high-resistivity silicon
  • the manufacture of the wafer 230 is performed before the formation of the hybrid substrate structure 336 and a device manufacture phase in which the formed hybrid substrate structure 336 is exposed to at least one device manufacture method (process).
  • the device manufacture method(s) which comprises e.g. a front-end method (process) and a back-end method (process), is directed to the hybrid substrate structure 336 in order to obtain (to manufacture, to process) a semiconductor device (component).
  • Fig. 3a and 3b present the hybrid substrate structure 336, which is manufactured in the front-end method by using the processed wafer 230 as a handle wafer and which may be used in manufacturing a piezoacoustic thin film surface acoustic wave (TF- SAW) filter or other, e.g.
  • TF- SAW piezoacoustic thin film surface acoustic wave
  • the hybrid substrate structure 336 utilizes a thin active layer 334, which is made of sapphire or compound semiconductor material, and which is fusion bonded in accordance with fig. 3a and thinned against the wafer 230 in accordance with fig. 3b during the front-end method.
  • a crystal puller which is suitable either for a float zone (FZ) or Magnetic Czochralski (MCz) silicon crystal growth, is used in crystal growing.
  • Special preparations, which are necessary for extremely low impurity cystal growth are carried out, e.g. the verification of very high cleanliness status of crystal growth chamber, the availability of very high purity inert gas, and the extremely tight control of impurities added to a polysilicon charge to be used.
  • a HRS ingot which has a target diameter (d) of 150-210 mm, e.g. 150, 160, 170, 180, 190, or 200 mm, is pulled in the growing chamber as the first stage of production of the wafer 230.
  • the grown HRS ingot is cut and ground for producing a crystal orientation identifier 210, which is e.g. a primary flat when the diameter d of HRS ingot is 150 mm or a notch when the diameter d is 200 mm, along a side of the HRS ingot.
  • the primary flat 210 which is used as an example of an identifier 210 in these figures, is used as a standard identifier in order to identify the surface orientation for a 150 mm silicon wafer 230.
  • the surface orientation of a silicon wafer 230 is required to be exactly ⁇ 111 ⁇ or very close to it, or exactly ⁇ 100 ⁇ or very close to it, typically at most with 0,5 degree tolerance.
  • the primary flat 210 is an irregularity in the round shape of a silicon wafer 230 that invariably causes flatness degradation in mechanical thinning steps typically used in wafer manufacturing, e.g. grinding and polishing steps 116, 122.
  • the method 100 compensates the influence of the identifier 210 and enables higher flatness for the silicon wafer 230, e.g. for the 150 mm-diameter silicon wafer 230, specification of which typically requires the primary flat 210 because of processing tool requirements for this wafer size, and for a 200 mm-diameter silicon wafer 230.
  • HRS wafers 212 are sliced from the produced HRS ingot, e.g. by multiwire slicing in accordance with the current industry standard. The slicing process applies mechanical force to remove material and creates sub-surface crystal lattice damage into and under the front (top) surface 209 of sliced wafers 212.
  • crystal lattice damage is also incorporated into and under the back surface 211 of sliced wafers 212.
  • the incorporated crystal lattice damage creates a disordered lattice damage zone 213 into the front (top) side of sliced wafers 212 and another disordered lattice damage zone (not presented in the figures) into the back side of sliced wafers 212.
  • Each sliced wafer 212 comprises single crystal silicon, the identifier 210 and the first thickness hi , which is a distance between the front and back surfaces 209, 211 .
  • the sliced wafer 212 may be thinned at least from its front side by lapping in order to remove at least partly the slicing-based crystal damage, i.e. the disordered zone 213, and the lapped wafer 212 may be cleaned.
  • the lapped wafer 212 comprises the disordered zone 213.
  • the slicing-based crystal damage is meant to retain at least partly in the lapped wafer 212, it is possible to modify the lapping process so that at least a part of the slicing-based disordered zone 213 remains, whereupon the lapped wafer 212 comprises the slicing and lapping-based crystal damages.
  • the lapped wafer 212 may be acid etched in order to remove at least partly the produced crystal damage(s) and, then, the etched wafer 212 is inspected visually, cleaned, and processed by thermal donor anneal.
  • the processed, identifier 210-comprised wafer 212 is attached to a chuck arrangement of a grinding machine and only its front surface 209 on the front side of the wafer 212 is exposed to a controlled single-side, fixed abrasive grinding, which is carried out by a rotating grinding wheel of the grinding machine.
  • the thickness of the wafer 218 decreases about a distance h2 from the first thickness hi to a third thickness h3 so that its front surface 217 approaches the back surface of wafer 218 said distance h2.
  • the fixed abrasive grinding process incorporates mechanically again some sub-surface crystal lattice damage into and under the front surface 217 of the ground wafer 218, and creates the disordered zone 213 into the front side of the ground wafer 218, if such does not already exist.
  • the effective, short control loop controlled, fixed abrasive grinding process eliminates at least partly, in fact at least majority of (most of, significantly, substantially completely) the effect of asymmetric variation (non-circular asymmetry), which is caused at least partly by the identifier 210 from the front surface 217 of the ground wafer 218 so that it is possible to obtain a desired total thickness variation (TTV) on the wafer 218.
  • the TTV defines the difference between the minimum (min, lowest) thickness and the maximum (max, highest) thickness of the wafer 218, 222, 230 in accordance with fig. 2a.
  • the controlled, fixed abrasive grinding process removes the identifier-caused asymmetric variation, or at least minimizes this asymmetric variation so insignificant that its effect to the TTV is eliminated.
  • step 118 during the fixed abrasive grinding process, it is monitored continuosly by at least one of an optical measurement (equipment, system) and a charge carrier- adjusted capacitive measurement (equipment, system), and at least one grinding parameter is controlled continuously.
  • an optical measurement equipment, system
  • a charge carrier- adjusted capacitive measurement equipment, system
  • the grinding parameter(s) comprises at least one of the cooling water temperature of the chuck arrangement, the grinding chuck inclination of the chuck arrangement, and the grinding feed rate of the grinding wheel.
  • step 120 if it is necessary to adjust the grinding parameter(s) because of a predetermined grinding plan or an emerged need as a result of monitoring, said grinding parameter(s) is adjusted during the the fixed abrasive grinding process in order to achieve the desired TTV.
  • the tolerance of cooling water temperature is in a range of ⁇ 1 °C or better.
  • the inclinations of grinding chuck between the wafer 212 and the grinding wheel are constantly monitored, e.g. 0,5 to 2 per hour in a constant operation and adjusted with short feedback loop.
  • the incoming TTV is in a range of 1 to 5 pm.
  • the grinding feed rate is in a range of 0.15 to 1 pm per second.
  • a diamond size and type of grinding wheel is selected for the best combination of throughput, robustness, and surface quality.
  • the particle cleanliness of the incoming wafer 218 must be sufficient to prevent generation of local excess material removal.
  • the single-side ground wafer 218 is attached to a wafer carrier of a polishing machine and only its ground front surface 217 on the front side of the wafer 218 is exposed to a controlled polishing, which is carried out by a rotating polishing pad of the polishing machine.
  • the polishing process finishes the elimination of the thickness variation from the polished wafer 222 so that the polished wafer 222 meets the desired TTV level.
  • the desired TTV of the wafer 222, 230 is less than 600 nm, e.g. 200, 300, 400, or 500 nm.
  • step 124 during the polishing process, it is monitored continuosly by a Makyoh mirror, an optical measurement (equipment) or a geometry-monitoring suitable carried-adjusted capacitive measurement (equipment, system), and a surface scanning equipment (system) and at least one polishing parameter is controlled continuously.
  • the polishing parameter(s) comprises at least one of the polishing pressure of the wafer 222 and the polishing pad, the rotation speed of the wafer 222 and the polishing pad, and the location of the wafer 222 relative to the polishing pad.
  • step 126 if it is necessary to adjust the polishing parameter(s) because of a predetermined polishing plan or an emerged need as a result of monitoring, said at least one polishing parameter is adjusted during the the polishing process in order to achieve the desired TTV, to complete the thinning steps 116, 122 so that the thinned wafer 222 is ready for a treatment, which produces parasitic current suppression in radio frequencies (RF).
  • RF radio frequencies
  • the thinned wafer 222 is set into a deposition chamber of a deposition machine and at least one polysilicon layer 229 is deposited on its front surface 221 by a chemical vapour deposition (CVD) process.
  • CVD chemical vapour deposition
  • 229 comprises a highly uniform polysilicon film, which has a total layer thickness h6.
  • the thickness of the wafer 222 increases about a sixth distance h6, which is equal with the total layer thickness h6, from the fifth thickness h5 to a seventh thickness h7 so that its front surface 223 goes away from the back surface of the wafer 222 said sixth distance h6.
  • the wafer 222 which comprises the deposited polysilicon layer(s) 229, is attached to a wafer carrier of a polishing machine, which is suitable for chemicalmechanical polishing, and only its deposited front surface 223 on the front side of the wafer 222 is exposed to controlled chemical-mechanical polishing, which is carried out by a rotating polishing pad of the polishing machine.
  • the thickness of deposited polysilicon layer(s) 229 decreases about said eight distance h8 from the sixth thickness h6 to a nineth thickness h9 so that its front surface 232 approaches the back surface of the wafer 230 said eight distance h8.
  • the chemical-mechanical polishing process provides the polysilicon layer(s) 229 with the desired thickness h9 and a mirror-polished front surface 232, which is suitable for fusion bonding the hybrid substrate structure 336 in the front-end method.
  • the chemical-mechanical polishing process is monitored continuosly by measuring polished wafers 230 with an optical measurement (equipment) , e.g. interferometry, reflectometry, or ellipsometry, using an optical wavelenght range from visible (VIS) to near-infrared (NIR), and at least one chemical-mechanical polishing parameter is controlled continuously.
  • an optical measurement e.g. interferometry, reflectometry, or ellipsometry
  • an optical wavelenght range from visible (VIS) to near-infrared (NIR) e.g. interferometry, reflectometry, or ellipsometry
  • the operating principle of the optical measurement is based on reflecting broadband light from the front surface 223 and the polysilicon layer(s) interface, and calculating the layer thickness from the resulting spectrum.
  • the reflected light shows a periodic interference spectrum based on the layer thickness versus the wavelength, and the thickness is calculated from the signal by using a theoretical model for a layer having a matching period.
  • the poly-monocrystalline silicon interface produces only a weak reflection due to a small difference in the refractive indices of poly- and monocrystalline silicon materials. A moderate difference is still seen in the visible part of the spectrum, although light absorbance in silicon is high in the same wavelength area.
  • the optimal spectral range found is from 600 nm to 900 nm.
  • the chemical-mechanical polishing parameter(s) comprises at least one of the removal rate of material from the front surface 223 of the wafer 222 and the polishing time of the front surface 223 of the wafer 222.
  • step 136 if it is necessary to adjust the chemical-mechanical polishing parameters) because of a predetermined polishing plan or an emerged need as a result of monitoring, said chemical-mechanical polishing parameter(s) is adjusted during the the chemical-mechanical polishing process in order to achieve the desired final layer thickness h9 of the polysilicon layer(s) 229 and to complete the polishing step 130 so that the processed wafer 230 is ready for fusion bonding with the active layer 334 in accordance with fig. 3a to form a hybrid substrate structure 336 in the front-end method.
  • other structure may be formed (processed) on the back surface of the wafer 230 in the back-end method (process).
  • This method 100 addresses the critical importance of the geometry of the wafer 230, especially its non-circular symmetric variation, by carrying out the vast majority of material removal of the wafer shape definition with a circular symmetric, fixed abrasive grinding process.
  • a double-sided variant of this type of process is widely used for reaching very tight geometry in manufacturing 300 mm-diameter wafers, but the same is not possible for smaller wafer sizes relevant to substrates bonded to a single crystal silicon wafer 230.
  • One-sided grinding tools are commercially available for these wafer sizes, but the typical processes are not capable of the geometric accuracy needed.
  • the method 100 uses very well controlled, single-side grinding to manufacture very accurately defined geometries, resulting a TTV typically in the level of 500 nm in the wafer 230.
  • this variation mainly appears as a circular symmetric shape with the asymmetric part of the thickness variation being as low as 200 nm.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

L'invention concerne un procédé de fabrication (100) d'une tranche de manipulation de silicium à haute résistivité (230) permettant la formation d'une structure de substrat hybride (336). Le procédé consiste à produire la tranche (212) avec un identificateur d'orientation de cristal (210), à amincir la tranche produite pour obtenir une tranche amincie (222), à disposer une couche de passivation de surface (229) sur une surface avant (221) de la tranche amincie, et à polir la couche de passivation de sorte que la surface avant polie (232) de la tranche permette une liaison de couche active afin de former la structure de substrat hybride. L'étape d'amincissement comprend un meulage abrasif fixe d'un seul côté commandé de la tranche à identificateur d'orientation cristalline produite (218) à l'aide un agencement de mandrin, qui élimine au moins la majorité d'un effet d'asymétrie non circulaire provoqué par l'identificateur, afin de fabriquer la tranche avec une variation d'épaisseur totale de l'ordre du sous-micron souhaitée pour permettre la formation de la structure de substrat hybride.
PCT/FI2021/050664 2020-10-08 2021-10-08 Procédé de fabrication d'une tranche de manipulation de silicium à haute résistivité permettant la formation d'une structure de substrat hybride WO2022074297A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2023520210A JP2023549029A (ja) 2020-10-08 2021-10-08 ハイブリッド基板構造の形成を可能にするための高抵抗シリコンハンドルウェハの製造方法
EP21877067.5A EP4226411A1 (fr) 2020-10-08 2021-10-08 Procédé de fabrication d'une tranche de manipulation de silicium à haute résistivité permettant la formation d'une structure de substrat hybride
KR1020237012366A KR20230080428A (ko) 2020-10-08 2021-10-08 하이브리드 기판 구조체의 형성을 가능하게 하기 위한 고저항 실리콘 핸들 웨이퍼의 제조 방법
CN202180069096.5A CN116325084A (zh) 2020-10-08 2021-10-08 制造能够形成混合衬底结构的高电阻率硅处置晶片的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20205989 2020-10-08
FI20205989A FI129826B (en) 2020-10-08 2020-10-08 Manufacturing method of high-resistive silicon wafer intended for hybrid substrate structure

Publications (1)

Publication Number Publication Date
WO2022074297A1 true WO2022074297A1 (fr) 2022-04-14

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PCT/FI2021/050664 WO2022074297A1 (fr) 2020-10-08 2021-10-08 Procédé de fabrication d'une tranche de manipulation de silicium à haute résistivité permettant la formation d'une structure de substrat hybride

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EP (1) EP4226411A1 (fr)
JP (1) JP2023549029A (fr)
KR (1) KR20230080428A (fr)
CN (1) CN116325084A (fr)
FI (1) FI129826B (fr)
WO (1) WO2022074297A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0460437A2 (fr) * 1990-05-18 1991-12-11 Fujitsu Limited Procédé pour fabriquer un substrat semi-conducteur et procédé pour fabriquer un dispositif semi-conducteur comportant ce substrat
US6465328B1 (en) * 1998-10-01 2002-10-15 Sumitomo Metal Industries, Ltd. Semiconductor wafer manufacturing method
US20150145105A1 (en) * 2013-11-26 2015-05-28 Okmetic Oyj High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0460437A2 (fr) * 1990-05-18 1991-12-11 Fujitsu Limited Procédé pour fabriquer un substrat semi-conducteur et procédé pour fabriquer un dispositif semi-conducteur comportant ce substrat
US6465328B1 (en) * 1998-10-01 2002-10-15 Sumitomo Metal Industries, Ltd. Semiconductor wafer manufacturing method
US20150145105A1 (en) * 2013-11-26 2015-05-28 Okmetic Oyj High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device

Also Published As

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FI20205989A1 (en) 2022-04-09
KR20230080428A (ko) 2023-06-07
JP2023549029A (ja) 2023-11-22
EP4226411A1 (fr) 2023-08-16
CN116325084A (zh) 2023-06-23
FI129826B (en) 2022-09-15

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