WO2022068940A1 - 一种半导体设备 - Google Patents

一种半导体设备 Download PDF

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Publication number
WO2022068940A1
WO2022068940A1 PCT/CN2021/122443 CN2021122443W WO2022068940A1 WO 2022068940 A1 WO2022068940 A1 WO 2022068940A1 CN 2021122443 W CN2021122443 W CN 2021122443W WO 2022068940 A1 WO2022068940 A1 WO 2022068940A1
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Prior art keywords
layer
substrate
semiconductor device
chamber
semiconductor
Prior art date
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PCT/CN2021/122443
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English (en)
French (fr)
Inventor
陈卫军
Original Assignee
深圳市晶相技术有限公司
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Priority claimed from CN202011060031.8A external-priority patent/CN112267106A/zh
Application filed by 深圳市晶相技术有限公司 filed Critical 深圳市晶相技术有限公司
Publication of WO2022068940A1 publication Critical patent/WO2022068940A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
    • H01L21/67781—Batch transfer of wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a semiconductor device.
  • the present application proposes a semiconductor device to improve the process flow, simplify the structure of the semiconductor device, and improve work efficiency.
  • the present application proposes a semiconductor device, which includes a preheating chamber, and the preheating chamber includes: a casing; a heater arranged at the bottom of the casing to place a substrate; an electrode, The utility model is arranged on the top of the casing and located above the base plate; and a lifting and rotating mechanism is connected with the electrode.
  • a suction port is provided at the bottom of the preheating chamber.
  • a radio frequency power supply is provided in the preheating chamber, and the radio frequency power supply is connected to the electrode.
  • the semiconductor device includes a transfer chamber, and a substrate loading and unloading robot arm is arranged on the transfer chamber.
  • the semiconductor device includes a transition cavity, and a lifting base motor is disposed in the transition cavity.
  • the elevating base motor is disposed at the bottom of the transition cavity cavity, and a carrier is disposed on the elevating base motor.
  • a tray is set on the carrier, and a multi-layer open-type transfer box is set on the tray.
  • the carrier is cylindrical or rectangular.
  • the transition chamber is provided with a suction port, and the suction port is connected to a vacuum pump.
  • the semiconductor device includes a cleaning chamber, and a circulating water cooling device is provided on a side wall of the cleaning chamber.
  • the circulating water cooling device is arranged in a wave shape.
  • the semiconductor device includes a growth chamber, a target is disposed in the growth chamber, and the diameter of the bombarded surface of the target is set to be greater than or equal to 400 mm to 600 mm.
  • a guard ring is provided in the growth chamber, and the guard ring surrounds the target.
  • the protection ring is a ceramic ring or a stainless steel ring.
  • the semiconductor device further includes at least one detachable cavity, and the detachable cavity is disposed on one side of the transfer cavity.
  • the semiconductor device further includes an air inlet line, which is connected to the detachable cavity, so as to deliver gas into the detachable cavity.
  • the air inlet pipeline is connected to the detachable cavity through an air inlet, and the air inlet is provided on the top of the detachable cavity.
  • the intake pipeline includes a first intake pipeline and a second intake pipeline, and the first intake pipeline and the second intake pipeline are connected by a conversion joint.
  • the detachable cavity further includes a substrate inlet, the substrate inlet is connected to a locking unit, and the locking unit is used for locking the substrate inlet.
  • the detachable cavity further includes a substrate outlet, the substrate outlet is connected to a locking unit, and the locking unit is used for locking the substrate outlet.
  • the present application proposes a semiconductor device.
  • plasma cleaning is performed while baking and preheating, and the time for frequent gas filling and pumping of the intermediate transfer plate is saved. .
  • the cooling time can be reduced by pretending a cooling device in the transfer cavity to cool during the transfer process.
  • the purpose of simultaneous transmission is achieved by the use of multi-layer open conveyor boxes. It makes the whole process flow more smoothly and saves the overall time.
  • the vacuum sealing property of the entire semiconductor device is also ensured, the quality of film formation is improved, and the uniformity of the coating film is improved, and at the same time, the semiconductor device has a simple structure and high work efficiency.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a transition cavity in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a cleaning chamber in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a preheating chamber in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the structure of a growth chamber in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the structure of the target material and the backing plate according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram showing the structure of another semiconductor device according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a deposition chamber in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of the first deposition chamber.
  • Figure 10 is a schematic diagram of a diffuser plate.
  • FIG. 11 is a schematic structural diagram of the first intake line and the second intake line.
  • Figure 12 is a schematic diagram of the substrate inlet.
  • Figure 13 is a schematic diagram of the second pipeline.
  • FIG. 14 is a schematic structural diagram of a semiconductor device.
  • FIG. 15 is a structural diagram of a semiconductor epitaxy provided with a hole injection layer.
  • FIG. 16 is a schematic diagram of a polar surface and a non-polar surface.
  • FIG. 17 is a structural diagram of a semiconductor epitaxial structure with stable wavelength.
  • FIG. 18 is a structural diagram of a semiconductor epitaxy provided with a resistance layer.
  • FIG. 19 is an equivalent circuit diagram of the semiconductor epitaxial structure shown in FIG. 18 .
  • FIG. 20 is a schematic structural diagram of a miniature light emitting diode.
  • FIG. 21 is a schematic structural diagram of a large-angle miniature light-emitting diode.
  • FIG. 22 is a schematic structural diagram of a small-angle miniature light-emitting diode.
  • FIG. 23 is a schematic diagram of the structure of the shielding layer shown in FIG. 21 .
  • FIG. 24 is a schematic diagram of a shielding layer covering two side surfaces.
  • FIG. 25 is a schematic diagram of a shielding layer covering four sides.
  • FIG. 26 is a schematic structural diagram of a miniature light emitting diode provided with a leveling layer.
  • FIG. 27 is a schematic structural diagram of the leveling layer shown in FIG. 25 .
  • FIG. 28 is a schematic diagram of the force of the micro light-emitting diode shown in FIG. 25 being welded on the substrate.
  • FIG. 29 is a schematic diagram of the light emitting angle of the micro light emitting diode structure without the leveling layer.
  • FIG. 30 is a schematic diagram of the light-emitting angle of the miniature light-emitting diode shown in FIG. 25 .
  • FIG. 31 is a schematic diagram of a micro light-emitting diode with metal stacks disposed on the electrodes.
  • FIG. 32 is a schematic diagram of a miniature light-emitting diode with a special conductive structure.
  • FIG. 33 is a schematic diagram of a miniature light-emitting diode with a waterproof protective layer.
  • FIG. 34 is a schematic structural diagram of the protective film layer shown in FIG. 32 .
  • FIG. 35 is an electron microscope image of the protruding structure shown in FIG. 33 .
  • Figure 36 is a schematic diagram of the angle between the tangent to the edge of the droplet and the reference plane for surfaces with different hydrophobicity.
  • FIG. 37 is a schematic diagram of a micro light-emitting diode with a support layer disposed between electrodes.
  • FIG. 38 is a schematic structural diagram of a miniature light-emitting diode transfer device.
  • FIG. 39 is a top view of the structure of a miniature light emitting diode transfer device.
  • FIG. 40 is a schematic diagram of a cutting groove of a miniature light emitting diode transfer device.
  • FIG. 41 is a schematic diagram of the cutting position of a miniature light emitting diode transfer device.
  • FIG. 42 is a schematic structural diagram of a miniature light emitting diode display panel.
  • FIG. 43 is a top view of a miniature light emitting diode display panel.
  • FIG. 44 is a schematic structural diagram of an electronic device.
  • FIG. 45 is a schematic diagram of the structure of a semiconductor device.
  • FIG. 46 is a schematic structural diagram of a radio frequency module.
  • the present embodiment provides a semiconductor device 100, which may be, for example, chemical vapor deposition equipment, physical vapor deposition equipment, or a combination of physical vapor deposition equipment, chemical vapor deposition equipment, or other semiconductor equipment. .
  • the semiconductor device 100 may include, for example, a transfer chamber 110 , a preheating chamber 140 , and a cleaning chamber 130 , the transition chamber 120 and a plurality of growth chambers 150 .
  • the substrate may be preheated and plasma cleaned first, and the cleaned substrate is transferred to the growth chamber 150 , where film growth is performed in the growth chamber 150 , followed by cooling.
  • the transfer chamber 110 includes a substrate loading and unloading robot arm 111 , and the substrate loading and unloading robot arm 111 can be operated to transfer the substrates between the chambers.
  • the size of the substrate loading and unloading robot arm 111 can also be adjusted according to the spatial size of different cavities. More specifically, the substrate handling robot 111 may have dual substrate handling blades adapted to transfer two substrates from one chamber to the other at the same time. Substrates may be transferred between transfer chamber 110 and other chambers via slit valve 112 .
  • the movement of the substrate handling robot 111 may be controlled by a motor driving system (not shown), and the motor driving system may include a servo motor or a stepper motor.
  • the semiconductor equipment further includes a manufacturing interface 113
  • the manufacturing interface 113 includes a cassette and a substrate loading and unloading robot arm (not shown)
  • the cassette contains the substrates to be processed
  • the robotic arm may include a substrate planning system to load the substrates in the cassettes into the transition chamber 120, in particular, to place the substrates on the trays of the stage.
  • the preheating chamber 140 is connected to the transfer chamber 110, and the preheating chamber 140 is located on the side wall of the transfer chamber 110.
  • the substrate loading and unloading robot arm 111 in the transfer chamber 110 The substrate is then transferred from transition chamber 120 into preheat chamber 140 for preheating and plasma cleaning.
  • a plurality of growth chambers 150 are provided on the sidewall of the transfer chamber 110 .
  • the substrate loading and unloading robot arm 111 in the transfer chamber 110 transfers the substrate to the growth chamber.
  • uniform sputtering ions can be formed on the surface of the substrate, thereby forming a uniform thin film on the substrate.
  • the transition cavity 120 is connected to the transfer cavity 110 , wherein the transition cavity 120 is located between the manufacturing interface 113 and the transfer cavity 110 .
  • the transition chamber 120 provides a vacuum interface between the fabrication interface 113 and the transfer chamber 110 .
  • the transition chamber 120 may implement the processes of transferring, preheating and cleaning the substrate.
  • the transition chamber 120 includes a casing 120a, the casing 120a is, for example, a sealed cylinder, and a suction port and an exhaust port are provided on the side wall of the casing 120a.
  • the transition chamber 120 is provided with a plurality of air passages such as the air inlet 128 . Multiple gas paths such as air inlets 128 and power supplies are installed in the transition chamber 120 to realize the baking preheating and plasma cleaning process, and a separate pump is used for gas filling, which makes the entire process flow more smoothly and saves overall time.
  • the transition cavity 120 is provided with a carrier 122 , and the carrier 122 is fixed on the bottom of the housing 120 a by the lifting base motor 121 .
  • a tray 123 can be set on the carrier table 122, and a multi-layer open-type transfer box 124 can be set on the tray 123 to play the role of simultaneous tray transfer.
  • the carrier 122 can be cylindrical or rectangular or other shapes, for example, and the carrier 122 can be fixed in the housing 120 a by, for example, a lifting base motor 121 .
  • a laser sensor 125 may be provided inside the housing 120a.
  • the transition chamber 120 allows multiple disks to enter at the same time. It only needs to be evacuated once at the beginning and filled with air once at the end, which saves the frequent charging and pumping time of intermediate transfer disks, and reduces the charging and pumping time of the transmission node.
  • the transition chamber 120 further includes an air suction port, and the air suction port is connected to a vacuum pump 127 , and the transition chamber 120 is evacuated through the vacuum pump 127 .
  • Multiple N2 gas paths are newly added in the transition chamber 120 to introduce gas, so that air cooling can be provided instead of the cooling chamber when the chamber is not being transferred.
  • the vacuuming process is realized through multiple steps, for example, a dry pump (Dry Pump) is used first to evacuate the vacuum degree of the transition chamber 120 from atmospheric pressure to, for example, 5.00E-04Pa for no more than 2.5 minutes.
  • a dry pump Dry Pump
  • the gas circuit and power supply in the original preheating chamber 140 are transferred to the transition chamber 120, and a separate pump is used to perform the gas filling and pumping operation. Both the preheating of the substrate and the plasma cleaning can be performed. When the conveying action is not performed, the gas is introduced to take away the heat in it to achieve the effect of cooling the tray.
  • the transition chamber 120 is connected to the transfer chamber 110 , the substrate loading and unloading robot 111 in the transfer chamber 110 transfers the substrate from the transition chamber 120 to the transfer chamber 110 , and then the substrate loading and unloading robot 111 transfers the substrate to the transfer chamber 110 .
  • a thin film can be formed on the surface of the substrate, and the material of the thin film can include aluminum oxide, hafnium oxide, titanium oxide, One or more of Titanium Nitride, Aluminum Nitride, Aluminum Gallium Nitride or Gallium Nitride.
  • an exhaust port is also included on one side of the casing 120a, and the exhaust port is connected to an air source 126. Nitrogen gas or argon gas is introduced into the transition cavity 120 through the gas port, and the transition cavity 120 is subjected to vacuum breaking treatment, so as to avoid cracks on the substrate due to the introduction of nitrogen gas while the substrate is cooling. After the transition chamber 120 completes the vacuum breaking, the substrate can be taken out for preservation and analysis.
  • nitrogen or argon gas is first introduced into the chamber through the exhaust port, so that the chamber reaches the atmosphere.
  • the pressure is balanced, or the pressure in the cavity is greater than the atmospheric pressure, so as to prevent pollutants from entering the cavity due to negative pressure difference.
  • the transition chamber 120 only realizes the transfer function of the substrate, and the cleaning chamber 130 realizes the plasma cleaning and cooling of the substrate.
  • the cleaning chamber 130 is connected to the transfer chamber 110, and the cleaning chamber 130 is located on the side wall of the transfer chamber 110.
  • the substrate loading and unloading robot arm 111 in the transfer chamber 110 then removes the substrate from the transition chamber. 120 is transferred to the cleaning chamber 130 for cleaning, and after growing a thin film on the substrate, the substrate is transferred to the cleaning chamber 130 for cooling.
  • a substrate support assembly 131 is disposed in the cleaning chamber 130 , the substrate support assembly 131 is disposed at the bottom of the cleaning chamber 130 , and the substrate support assembly 131 does not contact the cleaning chamber 130 .
  • the substrate support assembly 131 includes a pedestal electrode 1311 and an electrostatic chuck 1312.
  • the electrostatic chuck 1312 is disposed on the pedestal electrode 1311.
  • the electrostatic chuck 1312 is used for placing a substrate. At least one substrate can be placed on the electrostatic chuck 1312. In some embodiments Among them, a plurality of substrates can be set on the electrostatic chuck 1312, and the cleaning work of the plurality of substrates can be performed at the same time, thereby improving the work efficiency.
  • the substrate support assembly 131 is connected with a lifting and rotating mechanism 134 .
  • the lifting and rotating mechanism 134 is connected to the pedestal electrode 1311 .
  • Lift or rotate to indirectly realize the lifting or rotation of the substrate.
  • the distance between the substrate and the electrode 132 changes to adjust the electric field strength between the pedestal electrode 1311 and the electrode 132, so that the plasma can better clean the substrate.
  • the cleaning chamber 130 further includes an electrode 132, the electrode 132 is relatively disposed above the substrate support assembly 131, the electrode 132 does not contact the top of the cleaning chamber 130, in some embodiments , the distance between the electrode 132 and the substrate support assembly 131 may be 2-25 cm.
  • the electrode 132 is also connected with a lifting and rotating mechanism 133 , and the structure of the lifting and rotating mechanism 133 is the same as that of the lifting and rotating mechanism 134 .
  • the electrode 132 rotates up or down, the distance between the electrode 132 and the substrate changes to adjust the electric field strength between the electrode 132 and the substrate, so that the plasma can uniformly clean the substrate.
  • the rotation speed of the electrode 132 and the substrate support assembly 131 may be the same or have a certain speed difference, so that the plasma uniformly cleans the substrate.
  • the substrate support assembly 131 is further connected to at least one RF bias power supply 138 , specifically, the RF bias power supply 138 is connected to the pedestal electrode 1311 .
  • the RF frequency of the RF bias power supply 138 can be high frequency, medium frequency or low frequency. Among them, high-frequency radio frequency can be used to perform silicon etching, and intermediate frequency or low-frequency radio frequency can be used to perform dielectric etching. Therefore, radio frequency bias power supplies 138 of different frequencies can be connected to the pedestal electrode 1311 at the same time to achieve simultaneous etching of silicon and Dielectric.
  • the electrode 132 is also connected to at least one radio frequency power supply 137 , and the radio frequency of the radio frequency power supply 137 is, for example, 10 ⁇ 15 MHz.
  • the RF power supply 137 and the RF bias power supply 138 are both driven by synchronous pulses, which can be switched on and off at the same time to reduce the temperature of electrons in the cleaning chamber 130, and the synchronous pulses have good control for cleaning (etching depth) in dense areas of the substrate.
  • the cleaning chamber 130 further includes an air inlet, the air inlet is close to the electrode 132 , the air inlet is connected to the gas source 135 , and the gas is supplied into the cleaning chamber 130 through the gas source 135 .
  • the gas is a precursor gas for cleaning applications.
  • the RF power supply 137 and/or the RF bias power supply 138 are activated, a plasma is generated near the substrate surface.
  • the resulting plasma typically contains free radicals and ions formed from the gas mixture.
  • the plasma is used to modify the surface structure of the substrate to ensure better crystal alignment between the substrate and the deposited epitaxial thin film layer (eg, an AlN-containing buffer layer).
  • the cleaning chamber 130 further includes a suction port, which is close to the substrate support assembly 131 .
  • the suction port is connected to a vacuum pump 136 , and the vacuum pump 136 is used to extract the gas in the cleaning chamber 130 .
  • the cleaning chamber 130 not only needs to realize the cleaning function, but also needs to transfer the substrate to the cleaning chamber 130 for cooling after the film is formed in the growth chamber 150 to ensure the cooling effect.
  • a water circulation device can be installed in the side wall of the cleaning chamber 130 to accelerate the cooling of the film on the substrate.
  • the water circulation device in the side wall of the cleaning chamber 130 can be, for example, the circulating water cooling device 1508 arranged in waves as shown in FIG. 6 to increase the cooling effect of the water circulation device.
  • the substrate needs to be placed in the preheating chamber 140 for preheating before the thin film is grown on the substrate.
  • the cleaned substrate is transferred to the cleaning chamber 130 for cleaning, the cleaned substrate is transferred to the growth chamber 150 to grow a thin film, and after the film growth is completed, it is transferred to the cleaning chamber 130 for cooling.
  • heat radiation is easily lost during the process of preheating the substrate in the preheating chamber 140 and cleaning in the cleaning chamber 130.
  • a cleaning structure is installed in the preheating chamber 140, The substrate can be plasma cleaned at the same time as the substrate is preheated.
  • the preheating chamber 140 includes a housing 140a, and a bracket 141 is provided at the bottom of the housing 140a.
  • the bracket 141 can be, for example, a hollow structure, and then the wires are placed In the inner structure of the holder 141, a wire is connected to the heater 142.
  • the bracket 141 can be, for example, a high temperature resistant material.
  • a heater 142 is disposed in the preheating chamber 140 , and the heater 142 is fixed on the bracket 141 .
  • the heater 142 may include a bottom plate and a heating coil disposed at the bottom of the chassis.
  • a plurality of measurement points are also provided on the side of the tray 143 close to the substrate 144 , and then the plurality of measurement points are connected to a temperature measurement device, which can be set in the preheating chamber 140 or in the preheating chamber 140 The temperature on the substrate 144 can be measured in real time through the temperature measuring device, so that the surface temperature of the substrate 144 and its thermal uniformity can be controlled.
  • the preheating chamber 140 can also be provided with at least one air outlet, which is connected to a vacuum pump 145 , and the preheating chamber 140 is evacuated by the vacuum pump 145 to obtain a vacuum state of the preheating chamber. 140.
  • At least one heater 142 is provided in the preheating chamber 140 . It should be noted that, a plurality of heaters 142 may also be provided on the side wall of the preheating chamber 140 , or a plurality of heaters may be provided on the top of the preheating chamber 140 , so as to ensure the uniformity of the overall temperature of the preheating chamber 140 .
  • the electrode 149 is also connected to the lifting and rotating mechanism 146.
  • the lifting and rotating mechanism 146 can be consistent with the structure of the lifting and rotating mechanism 133 in FIG. 3. When the electrode 149 rotates to ascend or descend, the distance between the electrode 149 and the substrate changes. , to adjust the electric field strength between the electrode 149 and the substrate, so that the plasma can uniformly clean the substrate.
  • the bracket 141 and the heater 142 may also be provided with a lifting and rotating mechanism 134 and a radio frequency bias power supply 138 .
  • the rotation speed of the electrode 149 and the rotation speed of the substrate 144 on the heater 142 can be the same or have a preset speed difference, so that the plasma uniformly cleans the substrate.
  • the electrode 149 is also connected to at least one radio frequency power supply 148 , and the radio frequency power supply 148 is configured in the same manner as the radio frequency power supply 148 shown in FIG. 3 .
  • an air inlet is also provided on the side wall of the preheating chamber 140 , the air inlet is close to the electrode 149 , and the air inlet is connected to the gas source 147 , and the gas source 147 conveys the air into the preheating chamber 140 Gas, which is a precursor gas for cleaning applications.
  • the plasma cleaning process needs to be carried out in a high temperature and constant environment.
  • a plasma cleaning device is installed in the preheating chamber 140 to preheat the substrate while simultaneously cleaning the substrate. Perform plasma cleaning. After the substrate is heated in the preheating chamber 140 , there is no need to transfer the substrate to the cleaning chamber 130 for cleaning. After preheating and cleaning in the preheating chamber 140 , the substrate can be directly transferred to the growth chamber 150 to form a thin film.
  • the growth chamber 150 includes a growth chamber housing 151 , a base 152 , a target 153 and a magnet 154 .
  • a circulating water cooling device 1508 is installed inside or on the side wall of the growth chamber 150 , as shown in FIG. 5 .
  • a susceptor 152 may be disposed at the bottom end of the growth chamber housing 151, and one or more substrates 155 may be placed on the susceptor 152, for example, four or six or more or less substrates 155 may be placed.
  • the diameter of the base 152 may range, for example, from 200 mm to 800 mm, for example, from 400 to 600 mm.
  • the size of the base 152 is, for example, 2-12 inches.
  • the pedestal 152 may be formed from a variety of materials, including silicon carbide or silicon carbide-coated graphite.
  • the base 152 has a surface area of 2000 square centimeters or more, such as 5000 square centimeters, 6000 square centimeters or more.
  • the base 152 is also connected to a drive unit 156, the drive unit 156 is connected to a control unit (not shown), the drive unit 156 is used to drive the base 152 to rise or fall, and the drive unit 156 can use a drive device such as a servo motor or a stepping motor.
  • the control unit is used to control the drive unit 156 to drive the base 152 to rise during the magnetron sputtering process, so that the distance between the target 153 and the base 152 is always kept constant at a predetermined value. Therefore, in the process of magnetron sputtering, the drive unit 156 can be controlled to drive the susceptor 152 to rise, so that the target-base spacing can always keep the optimal value unchanged, which can improve the uniformity of the film and the deposition rate, thereby improving the process quality.
  • the susceptor 152 may also be coupled with a rotating unit for rotating the susceptor 152 during film deposition, further improving the thickness uniformity of the coating, and improving the stress uniformity of the coating.
  • the target 153 is disposed on the top of the growth chamber housing 151 , and the target 153 is electrically connected to a sputtering power source (not shown). During the magnetron sputtering process, the sputtering The radio source outputs sputtering power to the target 153 to cause the plasma formed in the growth chamber housing 151 to etch the target 153 .
  • Target 153 has at least one surface portion comprised of material to be sputter deposited on substrate 155 disposed on susceptor 152 .
  • a substantially pure aluminum target when forming an aluminum nitride buffer layer, for example, can be used to form the aluminum nitride-containing buffer layer by sputtering the buffer layer using a plasma including an inert gas and a nitrogen-containing gas Pure aluminum target.
  • the magnet 154 in the process chamber of the machine is as large as the tray. For example, when it is less than or equal to 330 mm, the aluminum nitride deposition thickness at the outer position of the outer ring of the tray is too thin, which will affect the overall thickness uniformity.
  • the target material 153 and the back plate 1509 are enlarged as a whole, and the diameter of the bombarded surface of the target material 153 is set to be greater than or equal to, for example, 400mm to 600mm, and the diameter of the magnet operating coverage is greater than or equal to 400mm to 600mm.
  • a guard ring 1510 is used to surround them, and the guard ring is a ceramic ring or a stainless steel ring.
  • a continuous thin film of aluminum nitride may be deposited on the substrate 155 by using an aluminum-containing target and a nitrogen-containing process gas, which is used during the sputtering process.
  • Process gases may include, but are not limited to, nitrogen-containing gases and inert gases.
  • the magnet 154 is located above the target 153 , the magnet 154 rotates around the central axis of the target 153 , and the magnet 154 can rotate at any angle around the central axis of the target 153 .
  • the magnet 154 is connected to a driving mechanism, and the driving mechanism can drive the magnet 154 to rotate, and can also reciprocate up and down.
  • the driving mechanism includes a first motor 157, a transmission rod 158, a second motor 159 and a lifting assembly.
  • the first motor 157 is connected to the second motor 159 through the transmission rod 158 , the first motor 157 can drive the second motor 159 to reciprocate up and down through the transmission rod 158 , and the first motor 157 drives the transmission rod 158 to rotate forward or reverse.
  • the second motor 159 is reciprocated.
  • the lifting assembly includes an outer shaft 1501 and an inner shaft 1502.
  • the second motor 159 is connected to the inner shaft 1502 through an output shaft 1504.
  • the output shaft 1504 is partially located in the outer shaft 1501, and the second motor 159 can drive the inner shaft 1502 to rotate through the output shaft 1504.
  • the first motor 157 drives the second motor 159 to reciprocate up and down through the transmission rod 158.
  • the inner shaft 1502 can rotate. While performing the up-and-down reciprocating motion, the rotating motion can also be performed, so that the magnet 154 on the inner shaft 1502 can be driven to perform corresponding motion.
  • the inner shaft 1502 can only reciprocate up and down.
  • the staff can choose to turn on and/or turn off the first motor 157 and/or the second motor 159 according to the actual situation.
  • the target 153 when the magnet 154 rotates, the target 153 may remain stationary or rotate around its central axis, but there is a speed difference between the target 153 and the magnet 154 .
  • the relative movement of the target 153 and the magnet 154 can cause the magnetic field generated by the magnet 154 to scan the sputtering surface of the target 153 uniformly, and since the electric field and the magnetic field uniformly distributed on the sputtering surface of the target 153 in this embodiment are at the same time Acting on the secondary electrons, the movement trajectory of the secondary electrons can be adjusted to increase the number of collisions between the secondary electrons and the argon atoms, so that the argon atoms near the sputtering surface of the target 153 are sufficiently ionized to generate more argon ions. And by bombarding the target 153 with more argon ions, the sputtering utilization rate and sputtering uniformity of the target 153 can be effectively improved, and the quality
  • the present application also proposes a method for using the semiconductor device, including:
  • the present application further proposes a method for using the semiconductor device, including:
  • S11 place the multi-layer open transfer box in the transition chamber on the tray, and transfer the substrate to the preheating chamber;
  • S12 in the preheating chamber
  • the semiconductor device 100 is, for example, a chemical vapor deposition device
  • a plurality of deposition chambers are provided on the sidewall of the transfer chamber 110 .
  • Four deposition chambers are shown in this embodiment, namely, a first deposition chamber 161 , a second deposition chamber 162 , a third deposition chamber 163 and a fourth deposition chamber 164 .
  • the robot arm in the transfer chamber 110 can transport the substrate or wafer into the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163 and the fourth deposition chamber 164 in sequence for forming on the substrate or wafer film.
  • the first deposition chamber 161 , the second deposition chamber 162 , the third deposition chamber 163 and the fourth deposition chamber 164 include at least one detachable chamber, and the detachable chamber means that the chamber can be It will not affect the work of the entire semiconductor device 100 if it is disassembled separately.
  • the first deposition chamber 161 is set as a detachable chamber. In other embodiments, a separate detachable cavity may be provided.
  • the first deposition chamber 161 can be, for example, an undoped and/or N-type gallium nitride MOCVD reaction chamber.
  • the second deposition chamber 162 may be, for example, a multiple quantum well MOCVD reaction chamber.
  • the third deposition chamber 163 may be, for example, the P-type gallium nitride MOCVD reaction chamber 106 .
  • FIG. 9 shows a cross-sectional view of the first deposition chamber 161 .
  • the first deposition chamber 161 includes a main cavity 101 , and a base 102 is disposed in the main cavity 101 , and the base 102 may be disposed at the bottom of the main cavity 101 .
  • a radio frequency assembly 103 is disposed on the top of the main cavity 102 , and the radio frequency assembly 103 is disposed opposite to the base 102 .
  • the radio frequency assembly 103 and the base 102 form a plasma generating region.
  • the material of the main cavity 101 is, for example, stainless steel.
  • the radio frequency assembly 103 may also be rotated during the deposition process to allow for more uniform thin film deposition.
  • the base 102 is used to place substrates.
  • multiple substrates are allowed to be placed on the front surface of the base 102 , for example, four or six or more or Fewer substrates.
  • a substrate is disposed on the base 102 to reduce the mass of the first deposition chamber 161 and facilitate the disassembly of the first deposition chamber 161 .
  • the base 102 may also be connected to a rotating unit for rotating the base 102 during film deposition, further improving the thickness uniformity of the coating and improving the stress uniformity of the coating.
  • a heating unit may also be provided on the back of the base 102 , and the substrate may be heated by the heating unit.
  • the heating unit may be a radio frequency heater, an infrared radiation heater, or a resistance heater, etc., which may be selected differently according to the size and material of the main cavity 101 .
  • the radio frequency heating method the graphite base 102 is heated by the radio frequency coil through inductive coupling. This heating form can be applied to a large main cavity 101, but the system is usually too complicated.
  • the infrared radiation heating method is usually adopted, the thermal energy generated by the halogen tungsten lamp is converted into infrared radiation energy, and the graphite base 102 absorbs this radiation energy and converts it heat recovery.
  • the base 102 is heated by the heating of the resistance wire.
  • the heating unit may also be integrated into the base 102 .
  • the radio frequency component 103 is further connected to a radio frequency power supply, and a voltage is supplied to the radio frequency component 103 through the radio frequency power supply, thereby ionizing the reaction source gas into plasma.
  • an air inlet is further included at the top of the main cavity 101 , the air inlet pipe 104 is connected to the air inlet, and one end of the air inlet pipe 104 is connected to the air inlet, and the air inlet is connected to the air inlet.
  • the other end of the gas pipeline 104 is connected to an external gas source 105 . Through the external gas source 105 , the gas inlet pipeline 104 and the gas inlet can deliver the reaction gas into the main cavity 101 .
  • the air inlet is disposed on one side of the radio frequency assembly 103
  • the air intake pipeline 104 includes a first pipeline 1041 and a second pipeline 1042 .
  • One end of the first pipeline 1041 is connected to the external air source 105
  • the other end of the first pipeline 1041 is connected to the second pipeline 1042 .
  • the first pipeline 1041 is connected to the second pipeline 1042 through, for example, a quick connector 107 .
  • a first valve body 106 is provided on the first pipeline 1041.
  • the first valve body 106 When gas is supplied into the main cavity 101, the first valve body 106 is, for example, in an open state. When the cavity needs to be disassembled, the first valve body 106 For example, it is the closed state, which can prevent heavy metal dust from entering the clean room.
  • one end of the second pipeline 1042 extends into the main cavity 101 , and one end of the second pipeline 1042 is provided with a diffusion plate 108 .
  • the diffusion plate 108 has a plurality of diffusion holes 1081 .
  • the reaction gas can be uniformly diffused into the main cavity 101 through the diffusion holes 1081 .
  • the diameters of these diffusion holes 1081 may be the same or different, and the arrangement density of these diffusion holes 1081 may also be changed.
  • a plurality of air inlets may also be provided at the top of the main cavity 101 , that is, a plurality of air intake pipelines 104 , for example, a first air intake pipeline 104 a and a first air intake pipeline 104 a
  • a plurality of air intake pipelines 104 for example, a first air intake pipeline 104 a and a first air intake pipeline 104 a
  • Two air intake lines 104b the first air intake line 104a can be connected to the first air intake device, and the second air intake line 104b can be connected to the second air intake device.
  • the first intake line 104a and the second intake line 104b are located on both sides of the main cavity 101, and the height of the first intake line 104a is greater than the height of the second intake line 104b.
  • the two air intake pipelines 104b have a height difference, and the gases delivered to the main cavity 101 through the first air intake pipeline 104a and the second air intake pipeline 104b will not affect each other.
  • the gas transported into the main cavity 101 by the first gas inlet line 104a is, for example, a first gas, and the first gas includes one or more of a reaction precursor, a carrier gas, and a purge gas.
  • the gas transported by the second inlet line 104b into the main cavity 101 is, for example, the second gas, and the second gas also includes one or more of reaction precursors, carrier gas, and purge gas.
  • the first gas inlet device and the second gas inlet device have different temperatures, so the first gas and the second gas have different temperatures.
  • the first gas inlet device is used to transmit the Group III metal organic source
  • the second gas inlet device is used to transport the Group V hydride source as an example to illustrate. Due to the extremely high requirements of the MOCVD growth process, extremely high temperature control is usually required, and the ratio of reaction gases needs to be precisely controlled, and the decomposition temperature of group III metal-organic sources is quite different from that of group V hydride sources. Therefore, When the temperature of the group III metal organic source and the group V hydride source are controlled to be different, the occurrence of side reactions can be reduced, the quality and deposition rate of the III-V compound semiconductor thin film can be improved, and the Waste of hydride source.
  • the temperature of the first air intake device is lower than the temperature of the second air intake device, but this should not limit the protection scope of the present application. It is worth noting that, while the first gas inlet device transmits the Group III metal organic source and the second gas inlet device transmits the Group V hydride source, the first gas inlet device and the second gas inlet device can also transmit the carrier gas at the same time, such as hydrogen or nitrogen.
  • At least one exhaust port is also provided at the bottom of the main cavity 101 , one end of the exhaust pipe 109 is connected to the exhaust port, and the other end is connected to the air pump 1013 , through which the air pump 1013 performs a pumping operation on the main cavity 101 to pump away excess plasma, thereby reducing the probability of excess ions falling on the thin film and improving the quality of the thin film.
  • a second valve body 1014 is also arranged at the bottom of the main cavity 101, and the second valve body 1014 is located on the exhaust port. When the air extraction operation is performed, the second valve body 1014
  • the second valve body 1014 may be in the closed state to prevent the plasma from diffusing out.
  • the main cavity 101 further includes a substrate inlet, and the robot arm in the transfer cavity 110 places the substrate in the main cavity 101 through the substrate inlet.
  • the base plate entrance includes two retractable doors 1011 . When the two retractable doors 1011 are opened, the substrate entrance is opened. When the two retractable doors 1011 are closed, the substrate outlet is closed.
  • the main cavity 101 is also connected with a locking unit 1012. When the main cavity 101 is disassembled, the locking unit 1012 can keep the substrate entrance in a locked state, that is, when the main cavity 101 is powered off, the locking unit 1012 The substrate access can be kept closed or locked. When the substrate inlet is kept in a locked state, the remaining plasma in the main cavity 101 can be prevented from diffusing into the clean room, thereby preventing heavy metal pollution in the clean room.
  • the substrate inlet can also be used as a substrate outlet, that is to say, the robot arm puts the substrate into the main cavity 101 or takes the substrate out of the main cavity 101 through the substrate inlet.
  • the main cavity 101 may further include a substrate outlet, that is to say, the substrate outlet is disposed opposite to the substrate inlet, so when the robot arm places the substrate in the main cavity 101 through the substrate inlet, and then passes the substrate outlet to the main cavity 101 The substrate is taken out of the main cavity 101 . Since the substrate outlet and the substrate inlet are disposed opposite to each other, when the substrate outlet is opened, the heavy metal dust in the main cavity 101 will not diffuse into the clean room, so that the clean room will not be polluted.
  • the end of the second pipeline 1042 can also be designed in a bent shape, and the bent shape faces between the radio frequency component 103 and the base 102 , so that the gas is between the radio frequency component 103 and the base 102 . Diffusion between bases 102 .
  • the semiconductor device 100 includes a transfer chamber 110 and a detachable chamber, and the robot arm in the transfer chamber 110 transfers the substrate to or from the detachable chamber.
  • the cavity completes the operation (including preheating, cleaning, deposition, growth and cooling)
  • the gas in the gas source cannot enter the detachable cavity, and the The reaction gas cannot be discharged from the exhaust port.
  • the substrate inlet of the detachable chamber is closed by the locking unit, and then the detachable chamber is moved to another clean room, the substrate inlet is opened, and the substrate is taken out, so as to avoid causing damage.
  • the original clean room is polluted by heavy metals, and then the detachable cavity can be maintained, and then the detachable cavity can be arranged outside the transfer cavity 110 .
  • the coating system 180 of the semiconductor device 100 is provided with a plurality of reaction chambers 170 , and the reaction chambers 170 may be a growth chamber in a physical vapor deposition device or a deposition chamber in a chemical deposition device .
  • the reaction chamber 170 includes, for example, a first reaction chamber 171 and a second reaction chamber 172 .
  • the first reaction chamber 171 and the second reaction chamber 172 are both provided with two chamber doors, such as the first chamber door 173 and the second chamber door 174 .
  • Each chamber door corresponds to a substrate loading and unloading robot arm 111, for example, it includes a first robot arm 111a corresponding to the first chamber door 173, and a second robot arm 111b corresponding to the second chamber door 174, and the reaction chamber 170 One side is also provided with an air intake line 183 and a transmission track 181 .
  • the first reaction chamber 171 and the second reaction chamber 172 are connected by opening and closing valves, which can facilitate the transportation of the substrate and improve the processing efficiency.
  • the first chamber door 173 and the second chamber door 174 are provided on the first reaction chamber 171 and the second reaction chamber 172 .
  • the first chamber door 173 and the second chamber door 174 are provided On the same side of the reaction chamber, in other embodiments, the first chamber door 173 and the second chamber door 174 are arranged on opposite sides of the reaction chamber.
  • the specific structures of the first cavity door 173 and the second cavity door 174 may be the telescopic doors shown in FIG. 12 , which will not be described again here.
  • the first chamber door 173 serves as the substrate inlet/substrate outlet
  • the second chamber door 174 serves as the substrate outlet/substrate inlet.
  • the substrate loading and unloading robot arm 111 corresponding to the cavity door includes a first robot arm 111a and a second robot arm 111b.
  • the first robot arm 111a can transfer the substrate into the reaction chamber 170 through the first chamber door 173, for example, and the second robot arm 111b can transfer the substrate from the reaction chamber 170 through the second chamber door 174, for example. out.
  • Setting two robotic arms can facilitate the picking up of substrates, and at the same time transmit and transmit substrates, and distinguish the incoming and outgoing substrate loading and unloading robotic arms 111, which can further reduce the pollution of the substrates, thereby improving the quality of deposited films and uniformity.
  • the base 152 (or the base 102 ) is arranged at the top of the reaction chamber 170 , and the target 153 (or the radio frequency component 103 ) is arranged at the bottom of the reaction chamber 170 .
  • the reactants move from bottom to top.
  • the base 152 has fixing buckles for fixing the substrate.
  • the base 152 is a magnetic base, which allows multiple magnetic bases to be placed on opposite sides of the target 153. At this time, the base 152 can directly adsorb the substrate on the base 152 without the need for other magnetic bases. structure to fix the substrate.
  • the base 152 can be made of sapphire, silicon carbide, silicon, gallium nitride, diamond, lithium aluminate, zinc oxide, tungsten, copper and/or aluminum gallium nitride, etc., and the base 152 can be evaporated with metal layer so that the base 152 has metallicity.
  • a magnet is arranged in the base 152 so that the base 152 has an adsorption function. When the magnet rotates, the base 152 can rotate around its central axis.
  • a power source such as a motor can be used to drive the base 152 to rotate around its central axis, so that the magnetic field generated by the magnet tightly adsorbs the base 152, further improving the quality and uniformity of the deposited film, and the base 152
  • the size is for example 2-12 inches.
  • the transfer track 181 connects the reaction chamber 170 with other semiconductor devices, for example, the chamber door is connected with other semiconductor devices, wherein the other semiconductor devices can be cleaning devices, preheating devices or other semiconductor devices.
  • the gas inlet pipeline 182 is connected to an external gas source, and the external gas source feeds gas into the reaction chamber 170 through the gas inlet pipeline 182 .
  • the intake pipeline 182 may include a first intake pipeline and a second intake pipeline. The first intake pipeline is connected to the first reaction chamber 171, and the second intake pipeline is connected to the second reaction chamber 172.
  • the design of the intake pipeline is convenient for gas input and output.
  • the semiconductor device of the present application can manufacture high-quality pollution-free thin films, such as metal thin films, semiconductor thin films, insulating thin films, compound thin films or thin films of other materials.
  • the semiconductor epitaxial structure 20 when a semiconductor epitaxial structure 20 is fabricated by using the semiconductor device of the present disclosure, the semiconductor epitaxial structure 20 may include a substrate 200 , and a first layer disposed on the substrate 200 in sequence. A semiconductor layer 203 , an active layer 204 and a second semiconductor structure 21 .
  • the substrate 200 may be a sapphire substrate 200 .
  • the substrate 200 may also be made of materials such as silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), lithium aluminate (LiAlO 2 ).
  • the substrate 200 may be made of a crystal axis material without polarization effect, or a special flattening layer may be formed on the substrate 200 so as to align the substrate 200 The orientation of the crystal phase is selected to eliminate the influence of the piezoelectric effect on the substrate 200 .
  • the substrate 200 may be made of materials of N-plane (1100) or A-plane (1120), such as SiCO 3 , GaN, and SiC.
  • a planarization layer may be formed on the substrate 200 to eliminate lattice defects.
  • the material of the leveling layer can be selected from a compound composed of a group IIA element and nitrogen, for example, a non-polar AlN material or a non-polar GaN material. Selecting a special crystal axis material or setting a leveling layer can avoid the generation of lattice torsion in the substrate 200 when a large current is introduced, thereby generating piezoelectric voids and causing thermal cracking of the material.
  • the surface of the substrate 200 may be subjected to crushed grain processing, and the crushed grains on the surface of the substrate 200 may be oxidized to form crushed oxidation Then, oxide etching solution is used to clean the broken crystal oxide, so as to obtain a flat surface of the substrate 200 .
  • the substrate 200 is, for example, a silicon substrate.
  • Preliminary surface processing may be performed through a process such as grinding or planing to form silicon microcrystalline particles on the surface of the substrate 200 .
  • the generation of broken grains leads to the appearance of stress marks on the crystal lattice, which affects the growth of crystals. Therefore, the broken grains need to be treated.
  • a physical or chemical method can be used to eliminate the influence of broken crystal particles.
  • the substrate 200 can be heated in a preheating chamber so that the surface of the substrate 200 reaches, for example, 300-400 degrees, and oxygen or other oxides are introduced into the chamber to make the broken crystal particles oxidize. to form fragmented crystalline oxides.
  • an oxidizing agent such as hydrogen peroxide can be used to react with the broken crystal particles to form broken crystal oxides.
  • the oxidation reaction rate can be increased by raising the temperature, and the temperature is in the range of, for example, 40 to 80 degrees.
  • the fragmented crystal oxide is silicon dioxide.
  • a dense silicon dioxide layer is formed on the surface of the substrate 200, which can be cleaned by an oxide etching solution to obtain a complete crystal form.
  • hydrofluoric acid or ammonia can be used to remove fragmented oxides.
  • the material of the substrate 200 is not limited to the silicon substrate 200, and the SiC substrate 200 and other substrates 200 can also be selected. Due to the different materials of the substrate 200, different methods can be used to oxidize the crushed grains, and different solution to remove fragmented oxides.
  • a buffer layer 201 is disposed between the first semiconductor layer 203 and the substrate 200 to alleviate the lattice mismatch between the first semiconductor layer 203 and the substrate 200 , and further Defects that cause dislocations, stacking faults, or voids.
  • the material of the buffer layer 201 can be, but not limited to, aluminum nitride, gallium nitride and other materials, but the buffer layer 201 is not sufficient to solve the problem of lattice mismatch.
  • the lattice mismatch problem between the first semiconductor layer 203 and the buffer layer 201 can be further alleviated.
  • the material of the transition metal layer can be selected from group IIA elements, for example, aluminum can be selected.
  • the transition metal layer is annealed to form an annealing interface between the surface of the silicon substrate 200 and the transition layer.
  • the metal Al in the transition metal layer and the lining The lattice conversion of Si in the bottom 200 further reduces defects such as dislocations generated by directly growing the buffer layer 201 on the silicon bottom.
  • the range of the annealing temperature may be, for example, 400-600 degrees, and the time range of the annealing treatment may be, for example, 5-30 minutes.
  • the buffer layer 201 includes, for example, a periodic aluminum nitride layer and a shielding layer. Since only the aluminum nitride layer has too many defects as the buffer layer, the aluminum nitride layer can be A blocking layer is inserted periodically to improve lattice defects. Specifically, an aluminum nitride layer with a thickness of, for example, 10 to 25 nm can be grown, and the growth can be stopped.
  • the temperature of the reaction chamber is set to, for example, 500-1000 degrees, and nitrogen oxide or oxygen is used to purge the surface of the aluminum nitride layer, and then an aluminum oxide layer with a thickness of, for example, 3 to 5 nm is formed on the surface of the aluminum nitride layer, as a shielding layer.
  • the blocking layer can block lattice defects to improve the quality of the buffer layer 201 .
  • the nitrogen oxide may be nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ) or oxygen (O 2 ).
  • the aluminum nitride layer is repeatedly grown, and then a blocking layer is formed on the aluminum nitride layer, and finally a buffer layer 201 having a thickness of, for example, 20 to 300 nm is formed.
  • Each of the shielding layers can alleviate lattice defects in the aluminum nitride layer above it, so that the higher the thickness of the buffer layer 201, the fewer defects.
  • the thickness of the aluminum nitride layer grown each time is set according to the required thickness of the buffer layer 201 , which is not limited in the present application.
  • the buffer layer 201 is, for example, a gallium nitride layer.
  • ammonia and trimethyl may be introduced into the reaction chamber under the conditions that the temperature is, for example, 500 to 850° C., or 500 to 550° C., and the pressure of the reaction chamber is, for example, 100 to 650 Torr, or, for example, 200 to 500 Torr.
  • Gallium (TMGa) and then a layer of gallium nitride with a thickness of, for example, 200-400 angstroms or 400-600 angstroms is grown on the substrate 200 to form a buffer layer 201 .
  • an undoped gallium nitride layer 202 can be grown on the buffer layer 201 , and the temperature can be, for example, 1000-1200° C., or 1050° C.-1200° C. °C, the pressure of the reaction chamber is, for example, 100 Torr to 500 Torr, and under the condition of, for example, 200 to 500 Torr, ammonia and trimethyl gallium (TMGa) are introduced into the reaction chamber, and then a layer of thickness is grown on the buffer layer 201, for example, 10,000-30,000 angstroms of gallium nitride form an undoped gallium nitride layer 202 .
  • TMGa trimethyl gallium
  • the buffer layer 201 and the undoped gallium nitride layer 202 can be arranged between the substrate 200 and the first semiconductor layer 203, the problem of lattice mismatch between the substrate 200 and the first semiconductor layer 203 can be alleviated, improving the The quality of the semiconductor epitaxial structure 20 .
  • the first semiconductor layer 203 is, for example, a first-type gallium nitride layer, for example, an N-type gallium nitride layer, and the doping ions of the first semiconductor layer 203 may be silicon.
  • the temperature is, for example, 1000-1200 °C, or 1050-1200 °C
  • the pressure in the reaction chamber is, for example, 100-600 Torr, or, for example, 200-500 Torr Ammonia
  • trimethyl gallium (TMGa) and silane (SiH 4 ) are introduced, and then a layer of N with a thickness of, for example, 10,000-30,000 angstroms, for example, 20,000-40,000 angstroms, is grown on the undoped gallium nitride layer 202 type gallium nitride layer.
  • the ion concentration of silicon ions in the first semiconductor layer 203 is, for example, 1 ⁇ 10 18 to 7 ⁇ 10 18 atoms/cm 3 , or, for example, 8 ⁇ 10 18 to 2 ⁇ 10 19 atoms/cm 3 .
  • the first semiconductor layer 203 may be a superlattice structure of an N-type gallium nitride layer doped with silicon ions and an undoped gallium nitride layer.
  • the first semiconductor layer 203 may include an N-type gallium nitride layer and a superlattice structure disposed on the N-type gallium nitride.
  • the active layer 204 is located on the first semiconductor layer 203.
  • the active layer 204 includes one or more alternately formed periodic quantum barrier layers and quantum well layers, and the quantum barrier layer
  • the quantum barrier layer For example, it includes a GaN/AlGaN superlattice structure
  • the quantum well layer includes, for example, InGaN.
  • the thickness of the active layer 204 is, for example, 200 nm to 300 nm
  • the thickness of the quantum well layer of each period is, for example, 3 nm to 4 nm
  • the thickness of the quantum barrier layer of each period is, for example, 12 nm to 16 nm.
  • the thickness of the medium GaN is, for example, 1.5 nm to 3 nm
  • the thickness of the medium AlGaN constituting the quantum barrier layer is, for example, 1.5 nm to 3 nm.
  • the active layer 204 in this embodiment adopts a modulated doped GaN/AlGaN superlattice structure, which can effectively guide the impulse current, so that the impulse current is conducted in the lateral direction in the two-dimensional electron gas of the GaN/AlGaN structure.
  • the density distribution of the pulse current is made more uniform, and the recombination efficiency of electrons and holes can be effectively improved.
  • a layer of GaN with a thickness of, for example, 1 nm to 3 nm can be grown at a temperature of, for example, 810 to 860° C. and a pressure of, for example, 200 to 500 Torr, and then a layer of, for example, 1 nm to 3nm modulation doped AlGaN.
  • GaN and AlGaN form a superlattice unit structure, and the superlattice unit structure of 2 to 6 periods is alternately and continuously grown, and a quantum barrier layer of the superlattice structure can be formed. After the quantum barrier layer is formed, the growth conditions are changed, for example, under the conditions of a temperature of 710 to 760° C.
  • the indium source is, for example, trimethyl indium (TMIn).
  • the active layer 204 can be formed by alternately growing the quantum barrier layer and the quantum well layer for 2 to 6 or 9 to 12 cycles.
  • the second semiconductor structure 21 may include a second semiconductor layer 205 and a hole injection layer 22, the second semiconductor layer 205 is located on the active layer 204, and the hole injection layer 22 is located on the first on the second semiconductor layer 205 .
  • the second semiconductor layer 205 is an electron blocking layer, which may be a second type of gallium nitride layer, or may be a second type of aluminum gallium nitride layer, or may be made of non- or low-doped magnesium AlGaN
  • the second semiconductor layer 205 includes a P-type GaN layer and a P-type AlGaN layer cycled for 3-10 cycles.
  • the second semiconductor layer 205 is a P-type AlGaN layer, and the active AlGaN with a thickness of 5-10 nm is grown on the layer 204 to form a P-type AlGaN layer, wherein the Mg doping concentration is 0-1 ⁇ 10 16 atom/cm 3 .
  • the second semiconductor layer 205 includes a single-layer P-type GaN layer and a P-type AlGaN layer, and the temperature may be, for example, 700 ⁇ 900° C., and the pressure may be, for example, 200° C. Under the condition of ⁇ 500 Torr, GaN with a thickness of, for example, 20 to 30 nm is grown to form a P-type GaN layer, wherein the doping concentration of Mg is 1 ⁇ 10 19 to 1 ⁇ 10 20 atom/cm 3 . Then, under the conditions of a temperature of 800-950° C.
  • AlGaN with a thickness of 5-10 nm is grown on the P-type GaN layer to form a P-type AlGaN layer, wherein the Mg doping concentration is, for example, 1 ⁇ 10 19 atom/cm 3 .
  • the second semiconductor layer 205 includes a periodic P-type GaN layer and a P-type AlGaN layer.
  • GaN with a thickness of, for example, 5-10 nm is grown on the active layer 204 to form a P-type GaN layer, wherein the Mg doping concentration is 1 ⁇ 10E 19 atom/cm 3 .
  • AlGaN with a thickness of, for example, 5-10 nm is grown on the P-type GaN layer to form a P-type AlGaN layer, wherein the Mg doping concentration is 0-1 ⁇ 10E16atom/cm 3 .
  • the P-type GaN layer and the P-type AlGaN layer are alternately and continuously grown for 3 to 10 cycles.
  • the hole injection layer 22 is located on the second semiconductor layer 205, and the hole injection layer 22 includes a non- or low-doped InxGayN layer, and/or a doped InxGayN layer , That is, the hole injection layer 22 includes an InxGayN layer, and 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 .
  • the non-doped InxGayN layer is an InxGayN layer that is not doped with other ions, and the doped InxGayN layer is made of InxGayN doped with Mg, for example.
  • the second semiconductor layer 205 is, for example, a P-type aluminum gallium nitride layer
  • the hole injection layer 22 disposed thereon includes at least a first doping layer 206 and a second doping layer layer 207 , the first doped layer 206 is located on the second semiconductor layer 205 , and the second doped layer 207 is located on the first doped layer 206 .
  • the first doping layer 206 is a non- or low-doped InxGayN layer, and the doping concentration of the first doping layer 206 is, for example, the first doping concentration, the second doping layer 207 is a doped InxGayN layer, and the second doping concentration is The doping concentration of the impurity layer 207 is, for example, the second doping concentration, and the second semiconductor layer 205 has, for example, the third doping concentration.
  • the first doping concentration is smaller than the second doping concentration
  • the third doping concentration is smaller than the second doping concentration
  • the range of the first doping concentration is 0 ⁇ 1 ⁇ 10 19 atom/cm 3 .
  • the thickness of the first doping layer 206 is smaller than the thickness of the second doping layer 207 . 30% of the thickness of layer 207.
  • the hole injection layer 22 includes a first doped layer 206 and a second doped layer 207 , and the first doped layer 206 is an undoped InxGayN layer.
  • the second doping layer 207 is a doped InxGayN layer, that is, the first doping concentration of the first doping layer 206 is zero, and the second doping layer 207 is an InxGayN layer doped with magnesium.
  • the hole injection layer 22 further includes a third doped layer, the third doped layer is located on the second doped layer 207 , and the third doped layer is, for example, doped with magnesium of InxGayN, and the fourth doping concentration of the third doping layer is greater than the second doping concentration.
  • the first doped layer 206 is an undoped InxGayN layer
  • the second doped layer 207 is a low-doped InxGayN layer
  • the third doped layer is a doped InxGayN layer.
  • GaN with a thickness of, for example, 5 to 50 nm is grown at a temperature of, for example, 800 to 950° C., and a pressure of, for example, 200 to 500 Torr, where the doping concentration of magnesium is, for example, 1 ⁇ 10 16 to 1 ⁇ 10 17 .
  • a low-doped InxGayN layer is formed as the second doped layer 207 .
  • GaN with a thickness of, for example, 10 to 20 nm is grown, wherein the doping concentration of magnesium is 1 ⁇ 10 18 to 1 ⁇ 10 19 atom/ cm 3 , forming a doped InxGayN layer as the third doped layer.
  • the doped InxGayN layer includes but is not limited to the superposition of n layers of Inx1Gay1N , Inx2Gay2N , and Inx3Gay3N , Or n cycles of alternating In x1 Ga y1 N and In x2 Ga y2 N, where n ⁇ 1, X3 ⁇ X2 ⁇ X1 ⁇ 1, Xn ⁇ ... ⁇ X3 ⁇ X2 ⁇ X1 ⁇ 1.
  • N is equal to 3
  • X1 is equal to 1
  • X2 is equal to 0.2
  • X3 is equal to 0.05
  • the hole injection layer 22 includes InN, In 0.2 Ga 0.8 N, and In 0.05 Ga 0.95 N doped layers arranged in sequence.
  • the hole injection layer 22 described in this application can effectively increase the hole concentration of the epitaxial structure and improve the luminous efficiency.
  • a semiconductor epitaxial structure 20 with high wavelength stability is also provided, and the semiconductor epitaxial structure 20 is a green light epitaxial structure, and the active layer 204 For example, it includes a stress release layer 208 , a first active layer 209 and a second active layer 210 , and the first active layer 209 is located on the stress release layer 208 and the second active layer 210 is located on the first active layer 209 .
  • the materials of the stress release layer 208 are InxGa(1-x)N and GaN, where 0.17 ⁇ x ⁇ 0.35, and GaN is doped with silicon ions, and the doping concentration of silicon ions is, for example, a, And the range of a is 5 ⁇ 10 17 to 1 ⁇ 10 18 atoms/cm 3 , and the thickness of the stress release layer 208 is 3 to 40 nm.
  • the stress release layer 208 may include periodic quantum well layers and quantum barrier layers, and the growth period of the stress release layer 208 is, for example, 2-6, or, for example, three.
  • ammonia gas having a flow rate of, for example, 30,000-60,000 sccm
  • triethyl gas having a flow rate of 50-100 sccm
  • ammonia gas (NH 3 ) with a flow rate of 30,000-60,000 sccm and trimethylgallium (TMGa) with a flow rate of 100-200 sccm can be introduced , 100-130 L/min nitrogen (N2) and 1-2 sccm silane (SiH 4 ), and then grow a 30-40 nm N-type GaN layer on the quantum well layer to form a quantum barrier layer.
  • the stress release layer 208 can be obtained by repeatedly growing the quantum well layer and the quantum barrier layer for 2-6 cycles.
  • the first active layer 209 includes, for example, a barrier layer and a potential well layer with 3 to 8 cycles, and the number of cycles is 5, for example.
  • the material of the barrier layer is, for example, AlzGa(1-z)N, and 0 ⁇ z ⁇ 0.3
  • the material of the well layer is, for example, InyGa(1-y)N, and 0.17 ⁇ y ⁇ 0.4.
  • the barrier layer is doped with silicon ions, and the doping concentration of silicon ions is b, and a>b, and the range of b is 5 ⁇ 10 16 to 1 ⁇ 10 17 atoms/cm 3 .
  • the material of the barrier layer may also be GaN, or a 2-6 period superlattice layer grown alternately between AlGaN and GaN, and the thickness L1 of the barrier layer is, for example, 70-150 angstroms, and For example, 120 angstroms.
  • ammonia gas (NH 3 ) with a flow rate of 50000-70000 sccm, 200-1000 sccm of ammonia gas (NH 3 ), 200-1000 sccm can be introduced into the reaction chamber under the conditions that the temperature is, for example, 750-900° C. and the pressure of the reaction chamber is, for example, 200-500 Torr.
  • the temperature is, for example, 710 to 760°C.
  • the reaction chamber pressure is, for example, 200 to 500 Torr, a layer of InGaN with a thickness of 2 to 6 nm is grown on the barrier layer to form a well layer.
  • the first active layer 209 can be formed by repeatedly growing the barrier layer and the potential well layer for 3-8 cycles.
  • the second active layer 210 includes 2-6 cycles of In u Ga 1-u N and GaN, and the cycle is, for example, 3, and the second active layer 210 includes In u Ga 1
  • the indium content of -u N is 0.17 ⁇ u ⁇ 0.40
  • the GaN of the second active layer 210 is doped with silicon ions, and the doping concentration of silicon ions is c, and a>c>b
  • the range of c is 5 ⁇ 10 16 -1 ⁇ 10 17 atoms/cm 3 and c may be 1.4 times as large as b.
  • the second active layer 210 includes a quantum well layer made of N-type GaN and a quantum barrier layer made of InGaN.
  • the quantum well layer may also be a superlattice layer of non-Si-doped GaN and Si-doped GaN.
  • the temperature is, for example, 750-900° C.
  • a layer of InGaN with a thickness of 2-6 nm is grown on the quantum barrier layer to form a quantum well layer under the conditions of a temperature of 710-760° C. and a reaction chamber pressure of 200-500 Torr, for example.
  • the second active layer 210 can be formed by repeatedly growing the quantum barrier layer and the quantum well layer for 2-6 cycles.
  • the second semiconductor structure 21 includes a second semiconductor layer 205, a third semiconductor layer 211 and a fourth semiconductor layer 212, and the third semiconductor layer 211 is located on the second semiconductor layer 205, and the fourth semiconductor layer 212 is located on the on the third semiconductor layer 211 .
  • the second semiconductor layer 205 is a P-type AlGaN layer
  • the third semiconductor layer 211 and the fourth semiconductor layer 212 are P-type GaN layers
  • the P-type GaN layer is, for example, a Mg-doped GaN layer
  • the fourth semiconductor layer 212 is doped with Mg.
  • the impurity concentration is greater than that of the third semiconductor layer 211 .
  • the second semiconductor layer 205 can be formed by growing AlGaN with a thickness of 5-10 nm on the active layer 204 under the conditions that the temperature is, for example, 700-800° C. and the reaction chamber pressure is, for example, 200-500 Torr.
  • the doping concentration of Mg in the second semiconductor layer 205 is 1 ⁇ 10 18 to 1 ⁇ 10 19 atom/cm 3 .
  • GaN with a thickness of 20-30 nm is grown to form the third semiconductor layer 211 .
  • the doping concentration of Mg is 1 ⁇ 10 19 to 1 ⁇ 10 20 atom/cm 3 .
  • the temperature is, for example, 800-950° C.
  • the pressure of the reaction chamber is, for example, 200-500 Torr
  • GaN with a thickness of 10-20 nm is grown to form the fourth semiconductor layer 212 .
  • the doping concentration of Mg is 1 ⁇ 10 18 to 1 ⁇ 10 19 atom/cm 3 .
  • a device in order to ensure that the formed miniature light-emitting diode does not flicker due to too fast response, a device may be arranged between the first semiconductor layer 203 and the active layer 204 .
  • a resistive layer 214 with a special structure can delay the time when the diode is extinguished.
  • the semiconductor epitaxial structure 20 with the special structure of the resistance layer 214 can be made into a miniature light-emitting diode, which can be used with an energy-saving power supply to reduce the total power-on time to save energy consumption, and at the same time, the human eye can feel the same brightness and reduce the flicker. Influence, thereby reducing the damage of strong light to human eyes.
  • the first semiconductor layer 203 is a gallium nitride layer, and a superlattice structure 213 is disposed on the gallium nitride layer, and the resistance layer 214 is disposed on the gallium nitride layer and located on the gallium nitride layer and the superlattice structure 213.
  • the gallium nitride layer includes, for example, a lightly doped N-type gallium nitride layer 203a and a heavily doped N-type gallium nitride layer 203b.
  • a resistive layer 214 is provided on the heavily doped N-type gallium nitride layer 203b, and a superlattice structure 213 is provided on the resistive layer 214, and the active layer 204 is located on the superlattice structure 213.
  • the resistive layer 214 provided in this embodiment can slow down the discharge speed of the finally formed micro LED, prolong the discharge time of the micro LED, and avoid flickering of the micro LED due to unstable power supply or low duty cycle.
  • the material of the resistance layer 214 is, for example, AlxGa1-xN, and x ⁇ 0.15, and the thickness of the resistance layer 214 is, for example, 50-200 nm, which can avoid that the resistance layer 214 is too thin to control the growth, and the resistance layer 214 is too thin Thick cracks appear.
  • a plurality of openings 215 are etched on the photoresist layer. The direction of the openings 215 is parallel to the growth direction of the resistive layer 214. 3 ⁇ 10um.
  • gas triethylgallium (TEGa), trimethylaluminum (TMAL) and ammonia can be introduced into the reaction chamber under the conditions that the temperature is, for example, 700-900°C, and the pressure of the reaction chamber is, for example, 500 mbar.
  • MOCVD metal organic compound chemical vapor deposition
  • C is the equivalent capacitance of the semiconductor epitaxial structure 20 without the addition of the resistance layer 214
  • R 0 is the equivalent capacitance of the semiconductor epitaxial structure 20 without the addition of the resistance layer 214
  • the equivalent resistance, RL is the equivalent resistance of the resistance layer 214
  • RL can be adjusted by adjusting the number or diameter of the openings on the resistance layer 214
  • E is the voltage across the semiconductor epitaxial structure 20 .
  • the size of RL can be adjusted according to actual needs, that is, the equivalent resistance of the resistance layer 214 can be adjusted by the number and diameter of the openings 215, and the more the number of openings and the larger the diameter, the smaller the equivalent resistance of the resistance layer 214. And the opening can also limit the outflow of current.
  • the high-quality films formed in this application can be applied to various semiconductor structures, electronic components or electronic devices, such as switching elements, power elements, radio frequency elements, light emitting diodes, micro light emitting diodes, display panels, mobile phones, watches, notebook computers, Portable devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles or other electronic devices.
  • switching elements power elements, radio frequency elements, light emitting diodes, micro light emitting diodes, display panels, mobile phones, watches, notebook computers, Portable devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles or other electronic devices.
  • VR virtual reality
  • AR augmented reality
  • a miniature light-emitting diode provided in this embodiment includes a substrate 200 , a semiconductor epitaxial structure 20 disposed on the substrate 200 , and the semiconductor epitaxial structure 20 includes a first semiconductor layer 203 and an active layer 204 and the second semiconductor structure 21 , the micro light emitting diode further includes a first electrode 226 connected to the first semiconductor layer 203 and a second electrode 227 connected to the second semiconductor structure 21 .
  • the substrate 200 is, for example, a sapphire substrate 200
  • the semiconductor epitaxial structure 20 may be the semiconductor epitaxial structure 20 shown in FIG. 15 , FIG. 16 or FIG. 17 . In some embodiments, as shown in FIG. 15 and FIG.
  • a notch 23 may be provided on one side of the semiconductor epitaxial structure 20 .
  • the semiconductor layer 203 is in contact.
  • the notch 23 is in contact with the surface of the first semiconductor layer 203 .
  • the second semiconductor structure 21 , the active layer 204 and a part of the first semiconductor layer 203 may be etched to form the notch 23 .
  • a transparent conductive layer 220 is formed on the second semiconductor structure 21, the transparent conductive layer 220 covers the second semiconductor structure 21, and the transparent conductive layer 220 can be made of indium tin oxide, gallium zinc oxide, zinc oxide or oxide Made of indium zinc and other materials.
  • the transparent conductive layer 220 covers part of the second semiconductor structure 21 , and steps 228 are formed between the transparent conductive layer 220 and the second semiconductor layer on both sides of the transparent conductive layer 220 .
  • the transparent conductive layer 220 may completely cover the second semiconductor structure 21 .
  • the transparent conductive layer 220 can cover the first semiconductor layer 203 .
  • metal materials can be deposited on the first semiconductor layer 203 and the transparent conductive layer 220, for example, a titanium/titanium nitride barrier layer and metal tungsten can be deposited on the first semiconductor layer.
  • a first conductive plug 221 is formed on 203
  • a second conductive plug 222 is formed on the transparent conductive layer 220 .
  • the first conductive plug 221 and the second conductive plug 222 are flush, and the first conductive plug 221 covers part of the first semiconductor layer 203 , and the second conductive plug 222 covers part of the transparent conductive layer 220 .
  • an opening may be formed on one side of the semiconductor epitaxial structure 20 , and the bottom wall of the opening is in contact with the first semiconductor layer 203 , an insulating substance is laid on the sidewall of the opening, and inside the opening and A first conductive plug 221 is formed on the opening.
  • the semiconductor epitaxial structure 20 is provided with a notch 23 , and the first conductive plug 221 can be directly formed on the notch 23 .
  • a reflective layer 223 and a protective layer 224 are sequentially deposited on the first semiconductor layer 203 and the transparent conductive layer 220 .
  • the reflective layer 223 covers the transparent conductive layer 220 and the step 228, and exposes part of the first conductive plug 221 and the second conductive plug 222.
  • the protective layer 224 covers the reflective layer 223 and part or all of the first conductive plugs 221 and the second conductive plugs 222 .
  • An insulating layer 225 is deposited in the trench 229 and on the protective layer 224 , and the insulating layer 225 completely covers the first conductive plug 221 and the second conductive plug 222 .
  • the insulating layer 225 and the protective layer 224 are etched, openings are formed over the first conductive plugs 221 and the second conductive plugs 222, and the openings expose part of the first conductive plugs 221 and part of the second conductive plugs 222, and The area of the opening is larger than the radial dimensions of the first conductive plug 221 and the second conductive plug 222, and metal is deposited in the opening to form a first electrode 226 connected to the first conductive plug 221 and connected to the second conductive plug 222.
  • the second electrode 227 is connected. Then through laser cutting and splitting, after the point division is completed, a miniature light-emitting diode is formed.
  • other structures can be added to the light emitting diode to change the light emitting direction of the micro light emitting diode.
  • the light emitting direction of the micro light emitting diode can be changed according to specific requirements.
  • micro light-emitting diodes with a large angle can be set.
  • the astigmatism stack 230 can be arranged to increase the light emitting angle of the micro light emitting diode, so that the angle of the micro light emitting diode is increased. greater than or equal to 160 degrees.
  • the present application defines the side where the semiconductor epitaxial structure 20 is located as the upper surface of the substrate 200 , and defines the side of the substrate 200 opposite to the semiconductor epitaxial structure 20 as the lower surface.
  • the light scattering stack 230 includes a light guide layer 231 , a first reflection layer 232 , an optical oscillation layer 233 and a second reflection layer 234 disposed on the lower surface of the substrate 200 .
  • the light guiding layer 231 covers the lower surface of the light guiding layer 231 , and the refractive index of the light guiding layer 231 is the same as that of the substrate 200 , which can ensure that the light does not deflect on the light guiding layer 231 .
  • the substrate 200 is a sapphire substrate 200, and the refractive index of sapphire is 1.77, and the light-guiding layer 231 is made of aluminum oxide (Al 2 O 3 ) or magnesium oxide (MgO) with the same refractive index as sapphire. .
  • the thickness of the light guide layer 231 is specifically, for example, 10 to 200 nm, or, for example, 60 to 80 nm. In other embodiments, when the substrate 200 is made of other materials, the corresponding material of the light guiding layer 231 can be selected, and the thickness of the light guiding layer 231 can be correspondingly set.
  • the first reflection layer 232 is located on the side of the light guide layer 231 opposite to the substrate 200 , and the first reflection layer 232 covers the light guide layer 231 .
  • the first reflective layer 232 is the forward reflective layer 223, allowing the light emitted from the direction of the substrate 200 to pass through the first reflective layer 232, and the light emitted by the first reflective layer 232 relative to the direction of the substrate 200 will be reflected by the first reflective layer 232 reflection.
  • the first reflective layer 232 is a titanium oxide (Ti 2 O 3 ) layer and a silicon dioxide (SiO 2 ) layer grown periodically, and the first reflective layer 232 includes, for example, 4-6 periods.
  • the titania layer covers the light guiding layer 231, and the thickness of the titania layer is, for example, 55-60 nm, and the silicon dioxide layer covers the titania layer, and the thickness of the silica layer is, for example, 90-100 nm.
  • the light shock layer 233 is located on the side of the first reflection layer 232 opposite to the light guide layer 231 , and the light shock layer 233 covers the first reflection layer 232 .
  • the refractive index of the optical oscillation layer 233 is smaller than the refractive index of the substrate 200 .
  • the optical oscillation layer 233 can be selected from silicon dioxide (SiO 2 ) with a refractive index of 1.46 and magnesium fluoride (MgF) with a refractive index of 1.38. 2 ), made of one or more of titanium nitride (TiN) with a refractive index of 1.351 or calcium fluoride (CaF 2 ) with a refractive index of 1.433.
  • the thickness of the light oscillating layer 233 is, for example, 100-500 nm, or 300-400 nm, which can prevent the light oscillating layer 233 from being too thick and easy to crack, and the oscillating layer being too thin, resulting in a large loss of brightness. strength is weaker.
  • the second reflective layer 234 is located on the side of the optical oscillation layer 233 opposite to the first reflective layer 232 , and the second reflective layer 234 covers the optical oscillation layer 233 .
  • the second reflective layer 234 is the retroreflective layer 223 , the light emitted from the second reflective layer 234 relative to the direction of the substrate 200 passes through, and the light emitted from the direction of the substrate 200 will be reflected by the second reflective layer 234 .
  • the second reflective layer 234 is a silicon dioxide (SiO 2 ) layer and a titanium trioxide (Ti 2 O 3 ) layer grown periodically, and the second reflective layer 234 includes, for example, 2-3 periods. SiO 2 and Ti 2 O 3 , and the thickness of the silicon dioxide layer is, for example, 90-100 nm, and the titanium oxide layer covers the silicon dioxide layer, and the thickness of the titanium oxide layer is, for example, 55-60 nm.
  • the angle between the final emitted light and the plane where the substrate 200 is located is greater than 160 degrees.
  • the light-emitting angle of the micro-LEDs is too large, causing the colors of adjacent micro-LEDs of different colors to interfere with each other.
  • the light-emitting angle of the micro light-emitting diode can also be reduced by adding a shielding layer 235 on the outside of the substrate 200 .
  • the shielding layer 235 can be formed on the outer side of the micro light-emitting diode to reduce the light-emitting angle.
  • the shielding layer 235 is arranged on the outer side of the micro light-emitting diode. Specifically, as shown in FIGS. 23 , 24 and 25 , the shielding layer 235 is arranged on the outer side of the substrate 200 and is attached to the sidewall of the substrate 200 . combine.
  • the shielding layer 235 can cover one or more side surfaces of the substrate 200 , and the shielding layer 235 can be arranged at different positions on the sidewall of the substrate 200 to change the light-emitting range of the micro light emitting diode.
  • the shielding layer 235 may cover, for example, two opposite sides of the substrate 200 .
  • the light-emitting angle of the micro light-emitting diode ranges from 90 to 115 degrees, for example, and the maximum light-emitting angle is 115 degrees, for example. Spend.
  • the shielding layer 235 may cover, for example, four sides of the substrate 200 .
  • the light-emitting angle of the micro-LEDs ranges from 90 to 105 degrees, for example, and the maximum light-emitting angle is 105 degrees, for example. .
  • the shielding layer 235 covers, for example, one side surface of the substrate 200 .
  • the light-emitting angle of the micro LEDs ranges from 90 to 120 degrees, for example, and the maximum light-emitting angle is 120 degrees, for example.
  • the shielding layer 235 covers, for example, three side surfaces of the substrate 200 .
  • the light-emitting angle of the micro light-emitting diode ranges from 90 to 110 degrees, for example, and the maximum light-emitting angle is, for example, 110 degrees.
  • the shielding layer 235 includes a reduction layer 236 and a coating layer 237 , wherein the reduction layer 236 is formed by recrystallization and roughening of the surface of the sidewall of the substrate 200 .
  • the substrate 200 is, for example, a sapphire substrate 200, and the sidewalls of the substrate 200 can be recrystallized and roughened by means of laser scribing.
  • the wavelength of the laser light is, for example, 800-1200 nm.
  • the sapphire substrate 200 Al 2 O 3
  • the sidewall surface of the substrate 200 after the final recrystallization can be naturally roughened.
  • the Al or AlO formed by recrystallization are both opaque layers and can reflect light, and the naturally roughened sidewalls of the substrate 200 can also increase the reflection.
  • the coating layer 237 covers the reduction layer 236, and can, for example, be evaporated or sputtered under a vacuum environment and a pressure of, for example, 1 ⁇ 10 3 to 9 ⁇ 10 3 torr
  • a coating layer 237 is formed on the reduction layer 236 in the manner of the above-mentioned method.
  • the coating layer 237 includes a multi-layer combination layer, for example, a first combination layer 238 and a second combination layer 239 , and the second combination layer 239 covers the first combination layer 238 .
  • the coating layer 237 may be a metal layer combination layer or an oxide layer combination layer.
  • the material of the first combined layer 238 is Al, or Al and Ni
  • the material of the second combined layer 239 is Ti or Pt
  • the thickness of the coating layer 237 is, for example, 20-300 nm.
  • the material of the first combined layer 238 is SiO 2 or MgF 2
  • the material of the second combined layer 239 is Ti 2 O 5 or SiNx
  • the thickness of the coating layer 237 is, for example, 50-100 nm.
  • the coating layer 237 when the coating layer 237 is an oxide combination layer, the coating layer 237 may include a plurality of cyclically arranged first combination layers 238 and second combination layers 239 .
  • the surface of the semiconductor epitaxial structure may have uneven defects, resulting in poor effect of the reflective layer 223 .
  • the micro light emitting diode provided in this embodiment can fill the surface of the semiconductor epitaxial structure, and at the same time, it can ensure the stress balance of the whole film layer, avoid the cracking of the coating layer caused by the tensile stress, and can also increase the light extraction effect.
  • the transparent conductive layer 220 A composite filling and leveling layer 240 is arranged between the reflective layer 223 and the semiconductor epitaxial structure to improve the defects on the semiconductor epitaxial structure, and a pressing layer 243 is arranged between the protective layer 224 and the insulating layer 225 to ensure the overall film stress balance and avoid stress caused by tension. cause the coating to crack.
  • the leveling layer 240 is located on one side of the transparent conductive layer 220 opposite to the semiconductor epitaxial structure, and covers the transparent conductive layer 220 .
  • the leveling layer 240 is transparent and non-conductive, and the particles in the leveling layer 240 are first coarse and then fine.
  • the leveling layer 240 includes a first leveling layer 240a and a second leveling layer 240b, and the first leveling layer 240a covers the transparent conductive layer 220, and the thickness of the first leveling layer 240a is, for example, 200-500 nm, Another specific example is 250 nm or 300 nm, so as to completely cover the defects on the semiconductor epitaxial structure.
  • the second leveling layer 240b covers the first leveling layer 240a, and the thickness of the second leveling layer 240b is, for example, 50-300 nm, so as to fill the gaps between the particles in the first leveling layer 240a.
  • a PECVD deposition or evaporation method can be used to form a leveling layer 240 on the transparent conductive layer 220 , wherein the particle density of the first leveling layer 240 a is, for example, 3 ⁇ 4 g/cm 3 , and the material of the first leveling layer 240a is, for example, aluminum oxide (Al 2 O 3 ) or magnesium fluoride (MgF 3 ), the density of aluminum oxide is 3.5-3.9 g/cm 3 , and the density of magnesium fluoride is 3.148 g/cm 3 .
  • Al 2 O 3 aluminum oxide
  • MgF 3 magnesium fluoride
  • the particle density of the second leveling layer 240b is, for example, 1.5 ⁇ 3 g/cm 3
  • the material of the second leveling layer 240b is, for example, silicon dioxide (SiO 2 ) or silicon nitride (SiN).
  • the density of silicon dioxide is 2.2 g/cm 3
  • the density of silicon nitride is 1.8 to 2.7 g/cm 3 .
  • the filling and leveling layer 240 first uses coarse particles to form the first filling and leveling layer 240a, the plating speed is fast, and then fills with fine particles to form the second filling and leveling layer 240b, there will be no voids, and the film material is good, and it is not easy to fall off.
  • the filling layer 240 is provided with a plurality of openings 241 , and the openings 241 are arranged in an array.
  • the openings 241 can be etched by wet etching with BOE etchant, or the openings 241 can be etched by dry etching using inductively coupled plasma (ICP).
  • ICP inductively coupled plasma
  • the openings 241 are arranged in a column shape and penetrate the first filling layer 240a and the second filling layer 240b, wherein the cross-section of the openings 241 can be circular, square, polygonal or other shapes.
  • the diameter of the openings 241 is, for example, 3-5um
  • the interval between adjacent openings 241 is, for example, 3-5um.
  • the aperture and the spacing between the adjacent openings 241 can prevent the openings 241 and the spacing from being too small to meet the process requirements, and at the same time prevent the openings from being too large, and the contact area between the filling layer 240 and the conductive layer is too small, resulting in The voltage difference between the two sides of the filling layer 240 is too high.
  • the protective layer 224 covers the reflective layer 223
  • the pressing layer 243 covers the protective layer 224
  • the insulating layer 225 covers the pressing layer 243 .
  • the pressing layer 243 includes a first pressing layer and a second pressing layer, and the second pressing layer covers the first pressing layer. Under the condition of room temperature, the ratio of the thickness of the first pressing layer and the second pressing layer is, for example, 3:8. Moreover, the thickness of the first lamination layer and the second lamination layer is, for example, 30-600 nm, which can avoid problems such as the lamination layer 243 being too thin to function, and cracking when too thick.
  • lamination layer 243 includes, for example, 1 first lamination layer and, for example, 1 second lamination layer. In other embodiments, the lamination layer 243 includes a plurality of periodic cycles of the first lamination layer and the second lamination layer.
  • a pressing layer 243 may be formed on the transparent conductive layer 220 by means of PECVD deposition or evaporation, wherein the material of the first pressing layer is silicon dioxide (SiO 2 ), for example, and the second pressing layer is made of silicon dioxide (SiO 2 ).
  • the material of the lamination layer is, for example, titanium dioxide (TiO 2 ) or Ti 2 O 5 .
  • the first electrode 226 can be welded on the substrate 244 through the first pad 245
  • the second electrode 227 can be welded through the second pad 246 . on substrate 244 .
  • both sides of the substrate 244 and the thin film will warp to one side of the thin film.
  • both sides of the substrate 244 and the thin film will warp toward the substrate 244 side.
  • the substrate 244 exhibits a small tensile stress at room temperature
  • the stress variation of the lamination layer 243 is as follows: the thickness of the second lamination layer (TiO 2 or Ti 2 O 5 ) is When the thickness of the first lamination layer (SiO 2 ) is 400 nm, the tensile stress is exhibited at room temperature, for example, 114 Mpa, and the thickness of the first lamination layer (SiO 2 ) is 400 nm, and the compressive stress is exhibited at room temperature, such as -56 Mpa. Because the substrate 244 itself is the tensile stress in the other direction, the thickness of the first lamination layer and the second lamination layer should be a combination of 3:8.
  • the stress exhibited by the lamination layer 243 is nearly 0, and there are many A little compressive stress, can offset the tensile stress exhibited by the substrate 244 .
  • the substrate 244 will warp due to excessive stress, and the substrate 244 and the thin film on the substrate 244 can be balanced by adjusting the stress of the thin film.
  • the brightness of flip chips also needs to be higher and higher.
  • the surface is uneven, so that after the mirror is plated on the back, a complete mirror surface will not be formed, resulting in dispersion, light is not concentrated, after packaging into white light , resulting in poor light efficiency.
  • the flip-chip miniature light-emitting diode provided by this embodiment, as shown in FIG. 29 and FIG. 30 , uses a special composite filling layer 240 to fill the epitaxial surface and increase the vertical light reflection capability.
  • a lamination layer 243 is used to ensure the overall stress balance of the film layer and avoid cracking of the coating layer 237 due to tensile stress. At the same time, these two designs also enhance the vertical reflection capability of light required for flip-chip to increase the light output effect. .
  • the miniature light-emitting diode needs to be soldered on the circuit through the solder pad during use.
  • voids are easily formed between the solder pad and the electrode, and a special-shaped metal stack 250 can be formed on the electrode. , to increase the yield of electrode solderability.
  • the thickness of the metal stack 250 is, for example, 20-100um, and includes a dielectric layer 251 and a soft metal layer 252.
  • the dielectric layer 251 is disposed on the first electrode 226 and the second electrode 227, and the soft metal layer 252 is provided on the dielectric layer 251 .
  • the dielectric layer 251 is made of an alloy, and includes, for example, a nickel (Ni) layer, and an alloy of gold (Au) and tin (Sn). Under yellow light conditions, a layer of nickel with a thickness of, for example, 10 to 15 nm can be first evaporated or sputtered on the first electrode 226 and the second electrode 227, and then a layer of nickel with a thickness of, for example, 30 to 15 nm is evaporated or sputtered on the nickel.
  • a 1000 nm gold and tin alloy forms the dielectric layer 251 , and the ratio of gold to tin in the gold and tin alloy is, for example, 80:20.
  • the thickness of the dielectric layer 251 at each point is the same, and the overall shape of the dielectric layer 251 is cylindrical.
  • a dielectric layer 251 is formed on the first electrode 226 and the second electrode 227 to prevent the soft metal layer 252 from diffusing.
  • the soft metal layer 252 is disposed on the dielectric layer 251 and covers the dielectric layer 251 .
  • the soft metal layer 252 is made of metal or alloy, such as gold (Au), tin (Sn) or silver (Ag), or an alloy of tin (Sn).
  • the soft metal layer 252 may be formed by plating or sputtering a layer of metal or alloy with a thickness of, for example, 20-100um on the medium under the condition of yellow light. Wherein, as the thickness of the soft metal layer 252 increases, the radius of the soft metal layer 252 gradually decreases.
  • the soft metal layer 252 may be provided in a circular truncated shape, for example.
  • the voids between the pad and the electrode can be driven out, and then the characteristics of the soft metal can be used to fill the uneven pad area, and the warpage of the substrate 200 can be increased. window to increase product reliability.
  • the functions of the conductive plugs and electrodes can be replaced by a special pad, for example, the first conductive structure 260 is used to replace the first conductive plugs 221 and the first electrodes 226, The second conductive plug 222 is replaced with the second conductive structure 261 .
  • the first conductive structure 260 and the second conductive structure 261 have flexibility, which can be caused by the use of uneven substrates and the stress caused by the thermal expansion of reflow during soldering, and at the same time reduce the void rate of the package.
  • the first conductive structure 260 is electrically connected to the first semiconductor layer
  • the second conductive structure 261 is electrically connected to the second semiconductor layer.
  • the first conductive structure 260 includes a backing layer 262 , an adhesive layer 263 , a stretch layer 264 , a ridge layer 265 and a solder layer 266
  • the second conductive structure 261 includes an adhesive layer 263 , a stretch layer 264 , a ridge layer 265 and a solder layer 266 .
  • the leveling layer 262 is disposed on the first semiconductor layer of the semiconductor epitaxial structure 20 , and the height of the leveling layer 262 is equal to that of the transparent conductive layer 220 .
  • the pad leveling layer 262 By arranging the pad leveling layer 262, the heights of the first conductive structure 260 and the second conductive structure 261 can be made equal to avoid skew.
  • a pad leveling layer 262 may be deposited on the first semiconductor layer by chemical vapor deposition at a temperature of 200-300 degrees.
  • the material of the leveling layer 262 is, for example, SiO 2 , SiNx, Al 2 O 3 , MgO or AlN, and the thickness of the leveling layer 262 is, for example, 900-1500 nm, which can be the same as the height of the transparent conductive layer 220 .
  • the adhesive layer 263 of the first conductive structure 260 is disposed on the pad layer 262
  • the adhesive layer 263 of the second conductive structure 261 is disposed on the transparent conductive layer 220
  • the first conductive structure 260 and the second conductive structure The adhesive layers 263 of 261 have the same height.
  • An adhesive layer 263 may be evaporated or sputtered on the pad leveling layer 262 or the transparent conductive layer 220 under the condition of bright yellow.
  • the material of the adhesive layer 263 is, for example, Cr, Ni, Ti, or indium tin oxide (ITO).
  • a stretchable layer 264 is provided on the adhesive layer 263 of the first conductive structure 260 and the second conductive structure 261 , and the stretchable layer 264 on the first conductive structure 260 and the stretchable layer 264 on the second conductive structure 261 Equal height.
  • a stretchable layer 264 may be evaporated or sputtered on the adhesive layer 263 under the condition of turning on the yellow light.
  • the stretchable layer 264 is formed by, for example, an alloy of titanium and aluminum (Ti/Al), an alloy of nickel and aluminum (Ni/AL), an alloy of titanium and silver (Ti/Ag), or an alloy of nickel and silver (Ni/Ag). composite layer.
  • the stretchable layer 264 is higher than the insulating layer 225, and the thickness of the stretchable layer 264 is, for example, (50-200)*N nm, and the range of N is 3-9. When the value of N is too small, the stretchable layer 264 has no stretching effect. If it is too large, the voltage of the stretchable layer 264 is too high.
  • a ridge layer 265 is provided on the stretchable layer 264 of the first conductive structure 260 and the second conductive structure 261 , and the ridge layer 265 on the first conductive structure 260 and the ridge layer 265 on the second conductive structure 261 Equal height.
  • a layered ridge layer 265 may be evaporated or sputtered on the stretchable layer 264 under the condition of turning on the yellow light.
  • the material of the ridge layer 265 is, for example, an alloy of platinum (Pt) and titanium (Ti), or an alloy of titanium (Ti) and nickel (Ni), and the thickness of the ridge layer 265 is, for example, 100-300 nm.
  • a solder layer 266 is provided on the stacked layer 265 of the first conductive structure 260 and the second conductive structure 261 , and the solder layer 266 on the first conductive structure 260 and the solder layer 266 on the second conductive structure 261 Equal height.
  • a welding layer 266 may be evaporated or sputtered on the stacked layer 265 under the condition of turning on the yellow light.
  • the material of the soldering layer 266 is, for example, tin (Sn) or gold-tin alloy (AuSn), and the thickness of the soldering layer 266 is, for example, 80000-100000 nm.
  • micro-LEDs when micro-LEDs are used for backlighting and lighting, the micro-LEDs often fail due to the influence of various adverse environments, especially the infiltration of water vapor, which is particularly serious damage to the micro-LEDs.
  • the present application provides a miniature light emitting diode.
  • a special waterproof protective layer 270 is arranged on the light emitting area and the electrodes, which can prevent moisture from staying on the chip and keep the chip dry, thereby avoiding moisture defects and preventing moisture intrusion.
  • the waterproof protective layer 270 includes a protective film layer 271 , a hydrophobic film layer 272 and a water fence layer 273 .
  • the waterproof protective layer 270 is provided on the transparent conductive layer 220 and part of the first electrode 226 and the second electrode 227
  • the hydrophobic film layer 272 is provided on the waterproof protective layer 270
  • the water barrier layer 273 is provided on the hydrophobic film layer 272 .
  • the waterproof protective layer 270 covers the transparent conductive layer 220, extends toward the first electrode 226 and the second electrode 227, and covers the sidewalls and part of the top wall of the first electrode 226 and the second electrode 227. As shown in FIG.
  • the protective film layer 271 includes a first waterproof protective layer 274 , a second waterproof protective layer 275 and a third waterproof protective layer 276 .
  • the second waterproof protective layer 275 is disposed on the first waterproof protective layer 274
  • the third waterproof protective layer 275 The waterproof protective layer 276 is disposed on the second waterproof protective layer 275 .
  • the first waterproof protective layer 274 , the second waterproof protective layer 275 and the third waterproof protective layer 276 can be deposited respectively by using the ion-enhanced chemical vapor deposition method.
  • the first waterproof protection layer 274 is an oxide layer, and the thickness is, for example, 100-300 nm.
  • the second waterproof protection layer 275 is a graded layer of an oxide layer and a nitride layer, and the thickness is, for example, 20 nm
  • the third waterproof protection layer 276 is a nitride layer of a non-hydrophilic material, and the thickness is, for example, 20-50 nm.
  • the material of the first waterproof protection layer 274 is, for example, silicon dioxide (SiO 2 )
  • the material of the second waterproof protection layer 275 is, for example, silicon oxynitride (SiON)
  • the material of the third waterproof protection layer 276 is, for example, nitride Silicon ((SiNx).
  • the hydrophobic film layer 272 is disposed on the waterproof protective layer 270 and covers the waterproof protective layer 270, and the hydrophobic film layer 272 can be formed by electron beam evaporation (Electron Beam Evaporation).
  • the thickness of the layer 272 is, for example, 2 ⁇ 5 ⁇ m.
  • the hydrophobic film layer 272 is a super-hydrophobic nitride layer, such as a metal nitride layer, for example, boron nitride (BN) or aluminum nitride (AlN), and other super-hydrophobic metal nitride layers.
  • the water barrier layer 273 is disposed on the hydrophobic film layer 272, and the hydrophobic film layer 272 can be annealed and recrystallized to form a plurality of protruding structures on the hydrophobic film layer 272 to form water Fence layer 273.
  • the thickness of the water fence layer 273 is greater than or equal to 1 um, for example, 2 um, and the thickness of the water fence layer 273 is, for example, the height of the protruding structure.
  • a thicker hydrophobic film layer 272 may be provided when the hydrophobic film layer 272 is formed.
  • the thickness of the hydrophobic film layer 272 before annealing and crystallization is equal to the thickness of the finally formed hydrophobic film layer 272 and the water barrier.
  • the top of the hydrophobic film layer 272 is subjected to rapid high temperature annealing or furnace tube annealing at a temperature of 200 to 300 degrees, and after 30 to 60 minutes, the surface of the hydrophobic film layer 272 is annealed.
  • the top surface is granulated to form protruding structures, and a plurality of protruding structures constitute the water fence layer 273 .
  • the angle between the tangent line of the droplet edge and the reference plane on the hydrophilic surface is generally less than 90 degrees.
  • the tangent line of the droplet edge on the hydrophobic surface and the reference plane The included angle between them can be, for example, 90-150 degrees.
  • the included angle between the tangent to the edge of the droplet on the superhydrophobic surface and the reference plane is greater than 150 degrees.
  • the hydrophobicity of the protective film layer 271 provided by the present application is gradually enhanced, a super-hydrophobic surface is formed on the outermost layer of the protective film layer 271, and a water fence layer 273 with a protruding structure is formed on the surface of the super-hydrophobic metal nitride layer, and further Prevent water vapor intrusion.
  • the substrate 200 needs to be peeled off to improve the brightness. Since the electrodes are disposed on both sides of the semiconductor epitaxial structure, and there is a hollow structure between the two electrodes, when the substrate 200 is peeled off, the semiconductor epitaxial structure is likely to be cracked, resulting in leakage of the lamp.
  • the present application provides a miniature light emitting diode, which can prevent the semiconductor epitaxial structure from breaking when the substrate 200 is peeled off.
  • a support layer 280 is formed between the first electrode 226 and the second electrode 227 , and the support layer 280 fills the space between the first electrode 226 and the second electrode 227 gap between.
  • the supporting layer 280 can be formed by evaporation, sputtering or chemical vapor deposition, and the material of the supporting layer 280 is, for example, SiO 2 , SiNx, Al 2 O 3 or a diamond-like film (DLC).
  • the height of the support layer 280 is not higher than the first pad 245 and the second pad 246 , and the thickness of the support layer 280 may be, for example, 300 ⁇ 4000 nm.
  • the miniature light-emitting diode uses a special support layer 280, which can form a support for the cracked part, so that it will not crack, avoid the top damage of the crystal, and also avoid the diffusion of the underlying flux or solder paste. resulting in leakage.
  • the present application provides a semiconductor device that can cut a plurality of micro light emitting diodes and transfer them to a substrate.
  • the semiconductor device described in this embodiment is, for example, a miniature light-emitting diode transfer device.
  • the micro-LED transfer device is provided with a matrix cutting strip, which can separate a plurality of miniature light-emitting diodes on the substrate into independent wafers, and each wafer includes at least one Mini LED or Micro LED.
  • Matrix suction cups transfer miniature light-emitting diodes onto substrates.
  • the miniature light-emitting diode transfer device provided in this embodiment can perform integrated cutting, which can improve the operation efficiency.
  • the miniature light-emitting diode transfer device includes a base 301 , a cylinder base 302 is arranged above the base 301 , and an empty slot is arranged in the cylinder base 302 , and the neutral line of the empty slot coincides with the neutral line of the cylinder base 302 .
  • the lifting platform 303 is arranged in the hollow groove, and the top surface of the lifting platform 303 is higher than the top surface of the cylinder seat 302 .
  • the rotating table 304 is arranged on the lifting table 303 , one end of the cantilever 305 is connected to the rotating table 304 , and the fixed arm 306 is connected to one end of the cantilever 305 away from the rotating table 304 .
  • the transfer plate 308 is disposed under the fixed arm 306 , the matrix cutting bars 309 and the matrix suction cups 310 are fixed on the transfer plate 308 , and the matrix suction cups 310 are located between adjacent matrix cutting bars 309 .
  • the base 301 is arranged at the bottom of the micro-LED transfer device, and supports the entire micro-LED transfer device.
  • the base 301 may be provided with a motion wheel set, and the motion wheel set may be configured with a stopper plate.
  • the flexible adjustment of the position of the entire miniature light-emitting diode transfer device is realized under the action of the moving wheel set and the stop plate.
  • a cylinder seat 302 may be provided above the base 301 , and the cylinder base 302 is fixed at the center position of the upper surface of the base 301 .
  • the shape of the cylinder seat 302 may be a cylinder, or may be a structure such as a prism.
  • the orthographic projection of the cylinder seat 302 falls within the range of the upper surface of the base 301 .
  • a hollow groove may be provided inside the cylinder seat 302 , and in some embodiments, the hollow groove may be a cylindrical hollow groove, and the rotation axis of the cylindrical hollow groove is coincident with the central axis of the cylinder seat 302 .
  • a lubricating groove may also be provided on the inner wall of the hollow groove of the cylinder seat 302, and the lubricating liquid plays a lubricating role in the lubricating groove.
  • the lifting platform 303 is arranged in the cylindrical cavity, and the lifting platform 303 can be a cylinder.
  • the top of the lift table 303 is higher than the cylinder seat 302 , and a lift motor is arranged inside the lift table 303 to control the movement of the lift table 303 in the vertical direction.
  • the rotary table 304 is arranged on the lifting table 303 , the rotary table 304 can be a cylinder, the central axis of the rotary table 304 coincides with the central axis of the lifting table 303 , and the diameter of the rotary table 304 is smaller than that of the lifting table 303 .
  • a rotary motor is disposed inside the rotary table 304, and the rotary motor controls the rotary table 304 to perform bidirectional circular motion.
  • the side surface of the rotary table 304 is connected to the cantilever 305 .
  • the cantilever 305 is connected to the rotary table 304 by welding.
  • the interior of the cantilever 305 may be a hollow structure and may be provided with reinforcing ribs.
  • the cantilever 305 is driven by the rotating motor inside the rotary table 304 to perform a bidirectional circular motion along the movement trajectory 314 of the cantilever end.
  • one end of the cantilever arm 305 away from the rotary table 304 is connected to the fixed arm 306 , and the fixed arms 306 can be arranged crosswise.
  • two fixed arms 306 may be provided, which are arranged at 90 degrees across each other.
  • the number of the fixing arms 306 can also be three, four or other numbers that can play a fixing role.
  • the intersecting angles thereof may also be different angles such as 30 degrees, 45 degrees, and 60 degrees.
  • An end of the fixed arm 306 is provided with a bolt hole.
  • the transfer plate 308 is provided below the fixed arm 306 .
  • Bolt holes are provided on the upper surface of the transfer plate 308 at positions corresponding to the fixing arms 306 .
  • the transfer plate 308 is connected to the fixing plate 306 by bolts 307 .
  • the transfer plate 308 performs bidirectional circular motion along the movement trajectory 314 of the end of the cantilever through the cantilever 305 driven by the rotating motor inside the rotary table 304 to realize the transfer of wafers in different processing chambers.
  • the lower surface of the transfer plate 308 is provided with a matrix cutting bar 309 and a matrix suction cup 310 .
  • the connecting transfer plate 308 and the matrix cutting strips 309 are fixed under the transfer plate 308, and the matrix suction cups 310 are located between the adjacent matrix cutting strips 309.
  • the matrix suction cups 310 can batch extract and fix the wafers 311 to be transferred to the target array substrate. .
  • the matrix cutting bars 309 and the matrix suction cups 310 are fixed on the lower surface of the transfer plate 308 , and the matrix cutting bars 309 can be distributed in a grid shape. area between bars.
  • the height of the matrix suction cups 310 is less than the height of the matrix cutting bar.
  • the end of the matrix cutting bar 309 may be an inverted trapezoid structure, a pyramid structure, or a combination or combination of other similar structures.
  • the wafers 311 undergo different processing processes on the carrier 12, and cutting grooves are formed between adjacent wafers.
  • the dicing grooves can be divided into transverse dicing grooves 315 and longitudinal dicing grooves 316 , and the number of the dicing grooves varies according to the number of different wafers to be processed.
  • h1 - h8 are transverse cutting grooves 315
  • S1 - S8 are longitudinal cutting grooves 316 .
  • the matrix cutting bars 309 correspond to the transverse cutting grooves 315 and the longitudinal cutting grooves 316 , and perform integrated cutting of the wafers 311 , and divide different wafers 311 in the transverse and longitudinal directions. As shown in FIG.
  • a sawing force line 317 may be determined between adjacent wafers 311 , and a cutting surface at a vertical distance from the sawing force line 317 is a stress concentration surface 318 .
  • the cutting force acts on the stress concentration surface 318 by the sawing force line 317 .
  • the matrix suction cup 310 adsorbs and fixes the wafer 311 .
  • the adsorbed wafer 311 makes a bidirectional circular motion along the movement trajectory 314 of the end of the cantilever along with the transfer plate 308 driven by the rotating motor of the rotary table 304 .
  • the matrix suction cup can be replaced with a matrix suction body that adopts a similar principle, such as mechanical grasping, gluing, electrostatic adsorption, gas adsorption, electromagnetic adsorption, etc., to realize the integrated cutting and cutting of the wafer 311. transfer.
  • the saw blade cuts across the surface of the wafer 311 .
  • the saw blade is lowered to the surface of the wafer to draw a shallow groove deep into 1/3 of the wafer thickness.
  • the chip separation method is still completed by the cylindrical roller pressing described in the scribing method and the diamond scribing method.
  • a saw blade is used to saw the wafer completely apart from individual chips.
  • the chip to be fully sawn or cut through it is first pasted on a polyester film with good elasticity and good adhesion, usually a blue film or a UV film. Then the high-speed rotating saw blade completely saws the wafer according to the set program.
  • the chip is also pasted on the polyester film, which will help in the next step of extracting the chip.
  • Packaging is performed after the integrated dicing and transfer of the wafer is completed. Measure appropriate proportions of epoxy resin, expansion monomer and curing agent according to the needs of the encapsulant, add the expansion monomer and curing agent to the epoxy resin in turn, and mix them evenly to obtain the encapsulant.
  • the epoxy resin and the curing agent to a molten transparent liquid state respectively, add the expanding monomer to the molten epoxy resin, mix evenly to obtain a compound resin, add the molten curing agent to the compound resin, and stir at high speed for 5 minutes , until the mixture is uniform to obtain a molten encapsulant.
  • the encapsulation glue is coated on the diode through the glue filling equipment, the diode coated with the encapsulation glue is cured, and the encapsulation glue encapsulates the diode.
  • the coating thickness is greater than the thickness of the diode, and the specific coating thickness can be selected according to the actual thickness of the diode and packaging requirements.
  • the substrate 244 is provided with a driving circuit 296, and the light-emitting diodes are connected with the driving circuit 296 through the pads to form a miniature light-emitting diode display panel.
  • a miniature light emitting diode display panel is also provided, which includes a substrate 244 and a miniature light emitting diode with a plurality of nanoholes disposed on the substrate 244, and quantum dots are arranged in the nanoholes.
  • the micro light emitting diode in this embodiment includes a first semiconductor layer 291 and a second semiconductor layer 292 disposed on the first semiconductor layer 291 .
  • the first semiconductor layer 291 may be connected with an electrode, and the first semiconductor layer 291 is, for example, an N-type gallium nitride layer.
  • the second semiconductor layer 292 is disposed on the first semiconductor layer 291, and the second semiconductor layer 292 is also a gallium nitride layer, such as an N-type gallium nitride layer.
  • a plurality of array-shaped nanopores 293 are provided on the second semiconductor layer 292.
  • the N-type gallium nitride layer can be immersed in an acid solution and a bias voltage is applied to form nano-scale pores in the N-type gallium nitride layer, thereby Electrochemical etching of the N-type gallium nitride layer is driven to form nanoholes 293, and the density and size of nanoholes 293 can be changed by changing the applied bias voltage or the silicon doping concentration in the GaN.
  • the nanoholes 293 penetrate the second semiconductor layer 292 , and when the quantum dots are not arranged in the nanoholes 293 , the miniature light-emitting diode emits ultraviolet light or blue light.
  • the red quantum dots 295 are arranged in the nanohole 293, the micro light emitting diode can emit red light
  • the green quantum dots 294 are arranged in the nano hole 293, the micro light emitting diode can emit green light.
  • red quantum dots 295, green quantum dots 294 and vacant nanoholes 293 are arranged in sequence. Arranging the quantum dots in the sub nanoholes 293 can improve the absorption rate of the quantum dots and prolong the service life of the quantum dots.
  • the substrate 244 when forming the miniature LED display panel, the substrate 244 is provided with a driver circuit 296 , and the driver circuit 296 can be arranged on the surface of the substrate 244 or inside the substrate 244 .
  • the driving circuit 296 can drive the micro-LEDs to emit light.
  • the nano-holes 293 are arranged on the miniature light-emitting diodes, and quantum dots of different colors are filled in the nano-holes 293, which can avoid the sorting of light-emitting diodes of different colors and reduce the production cost.
  • the present disclosure further provides an electronic device, the electronic device includes a micro LED display panel 600 and an electronic device body 601 , the micro LED panel 600 is connected to the electronic device body 601 , wherein the micro LED panel 600 includes A circuit substrate and a plurality of miniature light-emitting diode chips.
  • the electronic device body 601 includes a controller 602 , a memory 603 , and a power source 604 .
  • the power supply 604 can convert the commercial power (220V alternating current) into the direct current required by the controller 602 and the memory 603 , and provide power for the micro-LED panel 600 at the same time.
  • the memory 603 is connected to the power supply 604 for storing data related to the operation of the electronic device.
  • the controller 602 is connected to the power supply 604 and is connected to the memory 603 at the same time.
  • the power supply 604 is used to supply power to the controller 602.
  • a program controls the electronic device.
  • the electronic device may be, for example, a display panel, a mobile phone, a watch, a notebook computer, a portable device, a charging device, a charging pile, a virtual reality (VR) device, an augmented reality (AR) device, a portable electronic device, a game console or other electronic devices.
  • the semiconductor device when the semiconductor epitaxial structure of the present disclosure is applied to manufacture a semiconductor device, the semiconductor device includes a substrate 200, a buffer layer 201, a first semiconductor layer 203, a second semiconductor layer 205, a source electrode 701, a drain electrode pole 702 and gate 703 .
  • the buffer layer 1401 is formed on the substrate 200
  • the first semiconductor layer 203 is formed on the buffer layer 201
  • the second semiconductor layer 205 is formed on the first semiconductor layer 203
  • the source electrode 701 is formed on the second semiconductor layer 205
  • the drain electrode 702 is formed on the second semiconductor layer 205
  • the gate electrode 703 is formed on the second semiconductor layer 203 between the source electrode 701 and the drain electrode 702 .
  • a source doped region 705 and a drain doped region 704 are provided on the second semiconductor layer 205 , and the source doped region 705 and the drain doped region 704 are, for example, N-type heavily doped regions, and the source electrode 701 is set on the source doped region.
  • the drain 702 is disposed on the drain impurity region 704 .
  • the radio frequency module when the semiconductor device of the present disclosure is applied to a radio frequency module, the radio frequency module includes the semiconductor device.
  • the radio frequency module mainly includes a radio frequency (radio frequency, RF) switching device 511 , a radio frequency (radio frequency, RF) active device 514 , a radio frequency (radio frequency, RF) passive device 512 and a control device 513 .
  • the radio frequency (RF) active device 514 may be the semiconductor device described in this application, and the radio frequency (RF) passive device 512 may be passive devices such as capacitors, resistors, and inductors.
  • a radio frequency (radio frequency, RF) switching device 511 a radio frequency (radio frequency, RF) active device 514 , a radio frequency (radio frequency, RF) passive device 512 and a control device 513 are all formed on the semiconductor substrate 200 .

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Abstract

一种半导体设备（100），包括预热腔（140），且预热腔（140）包括：壳体（140a）；加热器（142），设置在壳体（140a）的底部，以放置基板（144）；电极（149），设置在壳体（140a）的顶部，且位于基板（144）上方；以及升降旋转机构（146），与电极（149）连接。

Description

一种半导体设备 技术领域
本申请涉及半导体领域，特别涉及一种半导体设备。
背景技术
随着集成电路生产技术的不断进步，电路芯片的集成度得到大幅提升。目前，在一片芯片中所集成的晶体管数量已经达到了惊人的几千万个，数量如此庞大的有源元件的信号集成需要多达十层以上的高密度金属互联层进行连接。因此，作为制备上述金属互联层的重要工艺，气相沉积技术得到了广泛应用。
传统的半导体设备在生产中仅提供单盘传输，在量产中影响整体的生产时间。在目前的工艺流程中，预热腔对衬底预热后将衬底传输至清洗腔通入气体进行等离子清洗，传输过程中会导致热辐射的流失。且清洗腔与传输腔之间无门阀遮挡，在进行等离子清洗时无法传盘。另外，清洗腔无法同时完成等离子清洗和托盘冷却，在量产中沉积腔成为一个卡顿节点，影响加工效率。
发明内容
鉴于上述现有技术的缺陷，本申请提出一种半导体设备，以改善工艺流程，简化半导体设备的结构，提高工作效率。
为实现上述目的及其他目的，本申请提出一种半导体设备，包括预热腔，且所述预热腔包括：壳体；加热器，设置在所述壳体的底部，以放置基板；电极，设置在所述壳体的顶部，且位于所述基板上方；以及升降旋转机构，与所述电极连接。
在本申请一实施例中，所述预热腔的底部设置抽气口。
在本申请一实施例中，所述预热腔内设置有射频电源，所述射频电源与所述电极连接。
在本申请一实施例中，所述半导体设备包括传送腔，且所述传送腔上设置基板装卸机械手臂。
在本申请一实施例中，所述半导体设备包括过渡腔，且所述过渡腔内设置有升降基座电机。
在本申请一实施例中，所述升降基座电机设置在所述过渡腔腔体底部，且所述升降基座电机上设置载台。
在本申请一实施例中，所述载台上设置托盘，所述托盘设置多层开口式传送盒。
在本申请一实施例中，所述载台呈圆柱形或矩形。
在本申请一实施例中，所述过渡腔设置有抽气口，且所述抽气口连接真空泵。
在本申请一实施例中，所述半导体设备包括清洗腔，所述清洗腔的侧壁上设置有循环水冷装置。
在本申请一实施例中，所述循环水冷装置呈波浪状设置。
在本申请一实施例中，所述半导体设备包括生长腔，所述生长腔内设置有靶材，且所述靶材的受轰击面的直径设置为大于或等于400mm～600mm。
在本申请一实施例中，所述生长腔内设置有保护环，所述保护环环绕所述靶材。
在本申请一实施例中，所述保护环为陶瓷环或不锈钢环。
在本申请一实施例中，所述半导体设备还包括至少一可拆卸腔，且所述可拆卸腔设置在所述传送腔的一侧。
在本申请一实施例中，所述半导体设备还包括进气管路，其连接所述可拆卸腔体，以向所述可拆卸腔体内输送气体。
在本申请一实施例中，所述进气管路通过进气口连接所述可拆卸腔体，所述进气口设置在所述可拆卸腔体的顶部。
在本申请一实施例中，所述进气管路包括第一进气管路和第二进气管路，所述第一进气管路和所述第二进气管路通过转换接头连接。
在本申请一实施例中，所述可拆卸腔体还包括一基板入口，所述基板入口连接锁紧单元，所述锁紧单元用于锁紧所述基板入口。
在本申请一实施例中，所述可拆卸腔体还包括一基板出口，所述基板出口连接锁紧单元，所述锁紧单元用于锁紧所述基板出口。
综上所述，本申请提出一种半导体设备，通过在预热腔内加装多条气路通道和电源，在烘烤预热的同时进行等离子清洗，节省中间传盘频繁的气体充抽时间。通过在传送腔内假装冷却装置，在传盘过程中进行冷却，可减少冷却时间。利用多层开口式传送盒达到同时传输的目的。使得整个工艺流程更加顺畅，节省整体耗时。也保证了整个半导体设备的真空密封性，提高了成膜的质量，提高了镀膜的均匀性，同时该半导体设备结构简单，工作效率高。
附图说明
图1为本申请一实施例中半导体设备结构示意图。
图2为本申请一实施例中一过渡腔结构示意图。
图3为本申请一实施例中清洗腔结构示意图。
图4为本申请一实施例中预热腔结构示意图。
图5为本申请一实施例中生长腔结构示意图。
图6为本申请一实施例中靶材及背板结构简要示意图。
图7为本申请一实施例中另一半导体设备结构简要示意图。
图8为本申请实施例中沉积腔结构示意图。
图9为第一沉积腔体的结构示意图。
图10为扩散板的示意图。
图11为第一进气管路和第二进气管路的结构示意图。
图12为基板入口的示意图。
图13为第二管路的示意图。
图14为一种半导体设备的结构示意图。
图15为一种设置有空穴注入层的半导体外延结构图。
图16为一种极性面与非极性面示意图。
图17为一种具有稳定波长的半导体外延结构图。
图18为一种设置有电阻层的半导体外延结构图。
图19为图18所示的半导体外延结构等效电路图。
图20为一种微型发光二极管结构示意图。
图21为一种大角度微型发光二极管结构示意图。
图22为一种小角度微型发光二极管结构示意图。
图23为图21所示的遮挡层结构示意图。
图24为一种覆盖两个侧面的遮挡层示意图。
图25为一种覆盖四个侧面的遮挡层示意图。
图26为一种设置有填平层的微型发光二极管结构示意图。
图27为图25所示的填平层的结构示意图。
图28为图25所示的微型发光二极管焊接在基板上的受力示意图。
图29为未设置填平层的微型发光二极管结构的发光角度示意图。
图30为图25所示微型发光二极的发光角度示意图。
图31为一种电极上设置有金属叠层的微型发光二极管示意图。
图32为一种具有特殊导电结构的微型发光二极管示意图。
图33为一种具有防水保护层的微型发光二极管示意图。
图34为图32所示的保护膜层的结构示意图。
图35为图33所示的突出结构的电镜图。
图36为疏水性不同的表面，液滴边缘切线与基准面之间的夹角示意图。
图37为一种电极之间设置支撑层的微型发光二极管示意图。
图38为一种微型发光二极管转移装置结构示意图。
图39为一种微型发光二极管转移装置的结构俯视图。
图40为一种微型发光二极管转移装置的切割槽示意图。
图41为一种微型发光二极管转移装置的切割位置示意图。
图42为一种微型发光二极管显示面板的结构示意图。
图43为一种微型发光二极管显示面板的俯视图。
图44为一种电子装置结构示意图。
图45为一种半导体器件结构示意图。
图46为一种射频模组结构示意图。
具体实施方式
以下通过特定的具体实例说明本申请的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本申请的其他优点与功效。本申请还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本申请的精神下进行各种修饰或改变。
请参阅图1，本实施例提出一种半导体设备100，例如可以为化学气相沉积设备，也可以为物理气相沉积设备，当然也可以是物理气相沉积设备、化学气相沉积设备或其他半导体设备的组合。
如图1所示，在本申请一实施例中，半导体设备100内设置多个腔室，在本申请一实施例中，半导体设备100例如可以包括传送腔110，预热腔140，清洗腔130，过渡腔120及多个生长腔150。在半导体器件制造过程中，可先对基板进行衬底预热以及等离子清洗，将清洗完成后的衬底转移至生长腔150，在生长腔150中进行薄膜生长，之后进行冷却处理。
如图1所示，在本实施例中，传送腔110包括基板装卸机械手臂111，可操作基板装卸机械手臂111，以于各腔室之间传送基板。还可以根据不同腔体的空间尺寸大小调整基板装卸机械手臂111的大小。更具体地，基板装卸机械手臂111可具有适以同时将两基板从一个腔室传送至另一个腔室的双基板装卸叶片。基板可经由狭缝阀112在传送腔110与其它腔室之间传送。基板装卸机械手臂111的移动可由马达驱动系统(未示出)控制，而马达驱动系统可包括伺服电动机或步进电动机。
如图1，在一些实施例中，该半导体设备还包括一制造界面113，在制造界面113内包括卡匣及基板装卸机械手臂(未示出)，卡匣含有需要进行处理的基板，基板装卸机械手臂可包含基板规划系统，以将卡匣内的基板装载至过渡腔120内，具体地，将基板放置在载台的托盘上。
如图1，在本实施例中，预热腔140连接传送腔110，预热腔140位于传送腔110的侧壁上，当基板进入过渡腔120时，传送腔110内的基板装卸机械手臂111随后将基板从过渡腔120传送至预热腔140中以进行预热并进行等离子体清洁。
如图1，在本实施例中，在该传送腔110的侧壁上设置多个生长腔150，当基板完成相应的工艺后，传送腔110内的基板装卸机械手臂111将基板传送至生长腔150内进行作业，由于在生长腔150内形成均匀的磁场，由此可在基板的表面形成均匀的溅射离子，从而在基板上形成均匀的薄膜。
如图2，在本实施例中，该过渡腔120连接传送腔110，其中该过渡腔120位于制造界面113与传送腔110之间。过渡腔120在制造界面113与传送腔110之间提供真空界面。
如图1和图2，在一些实施例中，过渡腔120可实现基板的传递、预热以及清洗的过程。该过渡腔120包括一壳体120a，该壳体120a例如为密封的圆柱体，同时在该壳体120a的侧壁上设有抽气口及排气口。过渡腔120设置多条气路通道例如进气口128。在过渡腔120内加装多条气路例如进气口128以及电源实现烘烤预热和等离子清洗过程，使用单独泵进行气体抽充，使整个工艺流程更加顺畅以节省整体耗时。
如图2，在一些实施例中，该过渡腔120内设有一载台122，载台122通过升降基座电机121固定在壳体120a的底部。载台122上可以设置托盘123，托盘123上可以设置多层开口式传送盒124以起到同时传盘的作用。在本实施例中，该载台122可例如为圆柱形或矩形或其他形状，该载台122可例如通过升降基座电机121固定在壳体120a内。在壳体120a的内部可以设置激光传感器125。过渡腔120允许多盘同时进入，只需在开始时抽真空一次，结束时充大气一次，节省中间传盘频繁的充抽时间，减少了传输节点的充抽耗时。
如图1和图2，在一些实施例中，该过渡腔120还包括一抽气口，该抽气口连接真空泵127，通过该真空泵127对过渡腔120进行抽真空。在过渡腔120中新增多路N2气路以通入气体，使腔室未传盘时可提供气冷以代替冷却腔。本实施例通过多个步骤实现抽真空处理，例如先使用干泵(Dry Pump)将该过渡腔120真空度由大气压抽至例如5.00E-04Pa的时间不超过2.5min。将原有预热腔140中的气路和电源移装到过渡腔120中，使用单独泵进行气体的充抽作业。既可以实现对衬底的预热，同时可以进行等离子清洗。未做传盘动作时通入气体带走其中的热量以达到冷却托盘的作用。在本实施例中，该过渡腔120连接至传送腔110，传送腔110内的基板装卸机械手臂111将基板从过渡腔120内传送至传送腔110，然后在由基板装卸机械手臂111将该基板传输至其他腔体，例如预热腔，沉积腔或生长腔150，在生长腔150内，可在基板的表面上形成薄膜，该薄膜的材料可包括三氧化二铝，氧化铪，氧化钛，氮化钛，氮化铝，氮化铝镓或氮化镓中的一种或多种。当该基板完成镀膜工作后，在该壳体120a的一侧上还包括一排气口，该排气口连接一气源126，当对过渡腔120进行破真空处理，通过气源126通过排气口向过渡腔120内通入氮气或氩气，对该过渡腔120进行破真空处理，从而避免基板在冷却的同时，由于氮气的通入使得基板上产生裂纹。当该过渡腔120完成破真空后，可将该基板取出，进行保存分析。
如图2，在本实施例中，需要注意的是，在将基板放入过渡腔120或其他腔体时，首先通过排气口向腔体通入氮气或氩气，使得该腔体达到大气压力平衡，或者该腔体内的压力大于大气压力，避免由于负压差导致污染物进入到该腔体内。
请再参阅图1和图2，在本申请另一实施例中，过渡腔120仅实现基板的传递功能，在清洗腔130内实现基板的等离子清洗以及冷却。在本实施例中，清洗腔130连接传送腔110，清洗腔130位于传送腔110的侧壁上，当基板进入过渡腔120时，传送腔110内的基板装卸机械手臂111随后将基板从过渡腔120传送至清洗腔130中以进行清洗，在基板上生长薄膜后，将基板传递至清洗腔130冷却。
如图3，在该清洗腔130内设置有基板支撑组件131，基板支撑组件131设置在清洗腔130的底部，且基板支撑组件131未接触清洗腔130。基板支撑组件131包括台座电极1311及静电卡盘1312，静电卡盘1312设置在台座电极1311上，静电卡盘1312用于放置基板，该静电卡盘1312上可至少放置一个基板，在一些实施例中，可在静电卡盘1312上设置多个基板，同时对多个基板进行清洗工作，从而提高工作效率。
如图3，在本实施例中，该基板支撑组件131连接有升降旋转机构134，具体地，该升降旋转机构134连接在台座电极1311上，通过该升降旋转机构134可实现基板支撑组件131的升降或旋转，间接实现基板的升降或旋转。当基板支撑组件131旋转上升或下降时，基板与电极132的距离发生变化，以调整台座电极1311与电极132之间的电场强度，使得等离子体能够更好的清洗基板。
如图3，在本实施例中，该清洗腔130内还包括一电极132，该电极132相对设置在基板支撑组件131的上方，该电极132未接触清洗腔130的顶部，在一些实施例中，电极132与基板支撑组件131的距离可在2-25cm。该电极132同时还连接一升降旋转机构133，该升降旋转机构133的与升降旋转机构134的结构一致。当电极132进行旋转上升或下降时，电极132与基板之间的距离发生变化，以调节电极132与基板之间的电场强度，使得等离子体能够均匀的清洗基板。当电极132与基板支撑组件131同时发生旋转时，电极132的旋转速度与基板支撑组件131的旋转速度可相同或存在一定的速度差，以使得等离子体均匀的清洗基板。
如图3，在本实施例中，该基板支撑组件131还连接至少一个射频偏压电源138，具体地，该射频偏压电源138连接台座电极1311上。该射频偏压电源138的射频频率可以是高频、中频或低频。其中，可利用高频射频可以进行硅刻蚀，利用中频或者低频射频可以进行电介质的刻蚀，因此，可以在台座电极1311上同时连接不同频率的射频偏压电源138以实现同时刻蚀硅和电介质。在本实施例中，该电极132还连接至少一射频电源137，该射频电源137的射频频率例如为10～15MHZ。该射频电源137和射频偏压电源138均由同步脉冲来驱动，能够同时开关，降低清洗腔130内的电子温度，并且同步脉冲对于基板密集区域的清洗(刻蚀深度)具有良好的控制。
如图3，在本实施例中，该清洗腔130还包括进气口，该进气口靠近电极132，该进气口连接气体源135，通过气体源135向清洗腔130内输送气体，该气体为用于清洗应用的前驱物气体。当启动射频电源 137和/或射频偏压电源138时，以在基板表面附件产生等离子体。所产生的等离子体一般含有由气体混合物形成的自由基和离子。在一些情况下，等离子体用来修改基板的表面结构，以确保在基板与沉积的外延薄膜层(例如含AlN的缓冲层)之间有更好的晶体对准。可调节等离子体密度、偏压和处理时间以高效地处理基板表面，但不损害基板表面。在本实施例中，该清洗腔130还包括抽气口，该抽气口靠近基板支撑组件131，该抽气口连接一真空泵136，该真空泵136用于抽取清洗腔130内的气体。
如图3，在本实施例中，清洗腔130不仅需要实现清洗的功能，且在生长腔150内形成薄膜后，需要再将基板转移至清洗腔130内进行冷却，为保证冷却效果。可在清洗腔130的侧壁内加装水循环装置，以加速基板上薄膜的冷却。为保证冷却效果，可将清洗腔130侧壁内的水循环装置可例如图6所示的波浪状设置的循环水冷装置1508，以增加水循环装置的冷却效果。
如图1、图3和图4所示，在本申请又一实施例中，在进行半导体制备时，需要在基板上生长薄膜前需要将基板放在预热腔140内进行预加热，预热后的基板传输至清洗腔130清洁，将清洁后的基板传输至生长腔150生长薄膜，在薄膜生长完成后，再传送至清洗腔130中冷却。在形成薄膜的过程中，因在预热腔140内预热基板与清洗腔130内清洁的过程中，易导致热辐射流失，在本实施例中，在预热腔140内加装清洗结构，可在对基板进行预热时，同时对基板进行等离子清洗。
如图4所示，在本申请又一实施例中，该预热腔140包括壳体140a，在该壳体140a的底部设有支架141，该支架141可例如为空心结构，然后将导线放置在支架141的内部结构中，将导线连接在加热器142上。在本实施例中，该支架141可例如为耐高温材料。
如图4，在预热腔140内设置有加热器142，该加热器142固定在支架141上，该加热器142可包括底盘以及设置在地盘底部的加热线圈。在托盘143上靠近基板144的一面上还设有多个测量点，然后将多个测量点连接一测温装置，该测温装置可设置在预热腔140内或者设置在该预热腔140的外侧，通过该测温装置可实时测出基板144上的温度，从而可控制基板144的表面温度及其热均匀性。
如图4，在该预热腔140的底部还可设有至少一抽气口，该抽气口连接真空泵145，通过该真空泵145对预热腔140进行抽真空处理，以获得真空状态的预热腔140。在预热腔140内设置至少一个加热器142，需要说明的是，还可以在预热腔140的侧壁上设置多个加热器142，或者在预热腔140的顶部上设置多个加热器，以保证预热腔140整体温度的均匀性。
请再参阅图4，在预热腔140的顶部，且位于基板144上方，可以设置至少一电极149，该电极149未接触预热腔140的顶部，且电极149与基板144的距离可在2～25cm，例如在10～20cm，又例如在16～18cm。该电极149同时还连接升降旋转机构146，该升降旋转机构146可以与图3中的升降旋转机构133的结构一致，当电极149进行旋转上升或下降时，电极149与基板之间的距离发生变化，以调节电极149与基板之间的电场强度，使得等离子体能够均匀的清洗基板。
请一并参阅图3和图4，在支架141和加热器142上还可以有设置升降旋转机构134和射频偏压电源138。当电极149与基板144同时发生旋转时，电极149的旋转速度与加热器142上基板144的旋转速度可相同或存在预设的速度差，以使得等离子体均匀的清洗基板。且电极149还连接至少一射频电源148，该射频电源148与图3所示的射频电源148相同设置。
请再参阅图4，在预热腔140的侧壁上还设置有进气口，该进气口靠近电极149，该进气口连接气体源147，通过气体源147向预热腔140内输送气体，该气体为用于清洗应用的前驱物气体。
请一并参阅图1、图3和图4，等离子清洗的过程需要在高温恒定的环境中进行，在预热腔140内加装等离子清洗装置，在进行预热基板的同时，可同步对基板进行等离子清洗。将基板在预热腔140中加热后，可以不需要再转移至清洗腔130进行清洁，可在预热腔140内进行预热及清洁后，直接转移至生长腔150内形成薄膜。
请参阅图5至图7，生长腔150包括生长腔壳体151，基座152，靶材153及磁体154。在生长腔150内部或侧壁加装循环水冷装置1508，如图5所示。基座152可设置在生长腔壳体151的底端，在基座152上允许放置一个或多个基板155，例如可放置四个或六个或更多或更少个基板155。在一些实施例中，基座152的直径范围可例如在200mm-800mm，又例如在400-600mm。在一些实施例中，基座152的尺寸例如为2-12英寸。基座152可由多种材料形成，包括碳化硅或涂有碳化硅的石墨。在一些实施例中，基座152具有2000平方厘米或以上的表面积，例如为5000平方厘米、6000平方厘米或以上。基座152还连接一驱动单元156，驱动单元156连接控制单元(未显示)，驱动单元156用于驱动基座152上升或下降，驱动单元156可以采用诸如伺服电机或步进电机等的驱动装置，控制单元用于在磁控溅射的过程中控制驱动单元156驱动基座152上升，以使靶材153与基座152的间距始终保持预定值不变。因此，可在磁控溅射的过程中，通过控制驱动单元156驱动基座152上升，以使靶基间距始终保持最优值不变，可以提高薄膜均匀性和沉积速率，进而可以提高工艺质量。在一些实施例中，基座152还可连接有旋转单元，旋转单元用于在膜沉积期间使基座152旋转，进一步改善镀膜的厚度均匀性，及改善镀膜的应力均匀性。
请参阅图5至图7，在本实施例中，靶材153设置在生长腔壳体151的顶部，靶材153与溅射电源(未显示)电连接，在磁控溅射过程中，溅射电源向靶材153输出溅射功率，以使在生长腔壳体151内形成的等离子体刻蚀靶材153。靶材153具有至少一个表面部分是由将在设置在基座152上的基板155上溅射沉积的材料组成的。在一些实施例中，当例如形成氮化铝缓冲层时，可使用大体上的纯铝靶材形成含氮化铝缓冲层，通过使用包括惰性气体和含氮气体的等离子体而溅射所述纯铝靶材。机台工艺腔中磁体154与托盘一样大，例如小于或等于330mm时，托盘外圈靠外位置氮化铝沉积厚度偏薄，会影响整体厚度均匀性。在本实施例中，靶材153及背板1509整体扩大，将靶材153受轰击面的直径设置为大于或等于例如400mm～600mm，则磁铁运转覆盖面直径大于或等于400mm～600mm。在靶材153和背板1509的外侧，使 用保护环1510将其包围，且保护环为陶瓷环或不锈钢环。在一些实施例中，在将基板155载入生长腔壳体151之后，可通过使用含铝靶材和含氮处理气体在基板155上沉积连续的氮化铝薄膜，在溅射工艺期间使用的处理气体可包括但不限于含氮气体和惰性气体。
请参阅图5至图7，在本实施例中，磁体154位于靶材153的上方，磁体154围绕靶材153的中心轴进行旋转，且磁体154可围绕靶材153的中心轴旋转任意角度。在本实施例中，该磁体154连接一驱动机构，该驱动机构带动该磁体154进行旋转的同时，还可以进行上下往复运动。该驱动机构包括第一电机157，传动杆158，第二电机159及升降组件。其中第一电机157通过传动杆158连接第二电机159，第一电机157可通过传动杆158带动第二电机159进行上下往复运动，第一电机157驱动传动杆158正向，或反向转动可使第二电机159作往复运动。在本实施例中，该升降组件包括外轴1501及内轴1502，在本实施例中，第二电机159通过输出轴1504连接内轴1502，输出轴1504部分位于外轴1501内，第二电机159通过输出轴1504可带动内轴1502进行旋转，同时第一电机157通过传动杆158带动第二电机159进行上下往复运动，当同时打开第一电机157及第二电机159时，内轴1502可在进行上下往复运动的同时，还可以进行旋转运动，从而可以带动内轴1502上的磁体154也作相应的运动。当打开第一电机157，关闭第二电机159时，该内轴1502可只进行上下往复运动。当关闭第一电机157，打开第二电机159时，该内轴1502可只进行旋转运动。由此工作人员可根据实现情况选择打开和/或关闭第一电机157和/或第二电机159。
请参阅图5至图7，在一些实施中，磁体154在作旋转运动时，靶材153可保持静止状态，也可绕自身中心轴旋转，但是靶材153和磁体154之间存在速度差。靶材153和磁体154的相对运动，可使得磁体154所产生的磁场均匀地扫描过靶材153的溅射面，且由于本实施例中电场与均匀分布于靶材153溅射面的磁场同时作用于二次电子，可调整二次电子的运动轨迹以增加二次电子与氩原子的碰撞次数，使得靶材153溅射面附近的氩原子被充分电离，以产生更多的氩离子。且通过更多的氩离子轰击靶材153，可有效地提高靶材153的溅射利用率和溅射均匀性，进一步提高沉积薄膜的质量和均匀性。
在本申请一实施例中，对于过渡腔可实现预热以及清洗功能的半导体设备，本申请还提出一种半导体设备的使用方法，包括：
S10：将所述多层开口式传送盒放置在所述托盘上，在过渡腔中烘烤预热，通入气体进行等离子清洗；
S20：在生长腔中进行喷雾热分解工艺处理；
S30：清洗腔冷却处理，同时过渡腔通入气体进行托盘冷却。
在本申请又一实施例中，对于预热腔可实现预热以及清洗功能的半导体设备，本申请还提出一种半导体设备的使用方法，包括：
S11：将过渡腔中的所述多层开口式传送盒放置在所述托盘上，并将基板传送至预热腔；S12：在预
热腔中烘烤预热，并通入气体进行等离子清洗；
S13：在生长腔中生长薄膜；
S14：在清洗腔中腔通入气体，进行托盘冷却。
如图1和图8所示，在本申请一实施例中，在半导体设备100例如为化学气相沉积设备，则在传送腔110的侧壁上，设置有多个沉积腔。在本实施例中显示出四个沉积腔，即第一沉积腔161，第二沉积腔162，第三沉积腔163和第四沉积腔164。传送腔110内的机械臂可以将基板或晶圆依次送入第一沉积腔161，第二沉积腔162，第三沉积腔体163和第四沉积腔164中，以在基板或晶圆上形成薄膜。在本实施例中，第一沉积腔161，第二沉积腔162，第三沉积腔163和第四沉积腔164中至少包括一个可拆卸腔体，所述可拆卸腔体是指该腔体可以单独拆卸下来，不会影响整个半导体设备100的工作。本实施例例如将第一沉积腔161设置成可拆卸腔体。在其他实施例中，可单独设置一可拆卸腔体。
如图8所示，在本实施例中，第一沉积腔161例如可以为无掺杂及/或N型氮化镓MOCVD反应腔室。第二沉积腔162例如可以为多量子阱MOCVD反应腔室。第三沉积腔163例如可以为P型氮化镓MOCVD反应腔室106。
如图9所示，图9显示为第一沉积腔161的剖面图。从图中可以看出，该第一沉积腔161包括主腔体101，主腔体101内设置有底座102，底座102可以设置在主腔体101的底部。在主腔体102的顶部设置有射频组件103，射频组件103和底座102相对设置。射频组件103和底座102形成等离子产生区域。主腔体101的材料例如为不锈钢。在一些实施例中，射频组件103在沉积过程中还可以进行旋转，从而使得薄膜沉积更均匀。
如图9所示，在本实施例中，该底座102用于放置基板，在本实施例中，在底座102的正面上允许放置多个基板，例如可放置四个或六个或更多或更少个基板。本实施例在底座102上设置一个基板，以减少第一沉积腔161的质量，方便拆卸第一沉积腔161。
如图9所示，在一些实施例中，底座102还可连接一旋转单元，用于在膜沉积期间使底座102旋转，进一步改善镀膜的厚度均匀性，及改善镀膜的应力均匀性。
如图9所示，当然，在一些实施例中，还可以在底座102的背面设置一加热单元，通过该加热单元可以对基板进行加热。在一些实施例中，所述加热单元具体可以为射频加热器、红外辐射加热器或电阻加热器等，可以根据主腔体101的尺寸和材料进行不同的选择。在射频加热方式中，石墨的底座102被射频线圈通过诱导耦合加热，这种加热形式可以应用于大型的主腔体101，但是通常系统过于复杂。为了避免系统的复杂性，在稍小的主腔体101中，通常采用红外辐射加热方式，卤钨灯产生的热能被转化为红外辐射能，石墨的底座102吸收这种辐射能并将其转化回热能。在电阻加热方式中，通过电阻丝的发热，进而实现对底座102的加热。所述加热单元还可以集成于所述底座102内。
如图9所示，在本实施例中，该射频组件103还连接一射频电源，通过射频电源向射频组件103提供电压，从而将反应源气体电离成等离子体。
如图9所示，在本实施例中，在主腔体101的顶部还包括一进气口，进气管路104连接该进气口，进气管路104的一端连接所述进气口，进气管路104的另一端连接外部气源105。通过该外部气源105，进气管路104和进气口可将反应气体输送至主腔体101内。
如图9所示，在本实施例中，该进气口设置在射频组件103的一侧，进气管路104包括第一管路1041和第二管路1042。第一管路1041的一端连接外部气源105，第一管路1041的另一端连接第二管路1042。第一管路1041例如通过快速接头107连接第二管路1042。通过旋转该快速结构107即可将第一管路1041和第二管路1042连接或分开。在第一管路1041上设置有第一阀体106，当向主腔体101内输送气体时，第一阀体106例如是打开状态，当需要拆卸该腔体时，该第一阀体106例如是关闭状态，从而可以防止重金属粉尘进入无尘室内。
如图9和图10所示，在本实施例中，第二管路1042的一端延伸至主腔体101内，且在第二管路1042的一端设置有扩散板108。扩散板108上具有多个扩散孔1081。反应气体通过扩散孔1081可以均匀的扩散到主腔体101内。需要说明的时，这些扩散孔1081的直径可以相同也可以不同，这些扩散孔1081的排列密度也可以进行改变。
如图9和图11所示，在一些实施例中，还可以主腔体101的顶部设置多个进气口，也就是设置多个进气管路104，例如设置第一进气管路104a和第二进气管路104b，第一进气管路104a可以连接第一进气装置，第二进气管路104b可以连接第二进气装置。第一进气管路104a和第二进气管路104b位于主腔体101的两侧，且第一进气管路104a的高度大于第二进气管路104b的高度，由于第一进气管路104a和第二进气管路104b具有高度差，通过第一进气管路104a和第二进气管路104b向主腔体101输送的气体不会相互影响。第一进气管路104a向主腔体101内输送的气体例如为第一气体，所述第一气体包括反应前体、载气、吹扫气体中的一种或多种。第二进气管路104b向主腔体101内输送的气体例如为第二气体，所述第二气体也包括反应前体、载气、吹扫气体中的一种或多种，可以根据传输气体的不同，使所述第一进气装置与所述第二进气装置具有不同的温度，因此所述第一气体与所述第二气体具有不同的温度。在本实施例中，所述第一进气装置用于传输III族金属有机源，所述第二进气装置用于传输V族氢化物源为例进行说明。由于MOCVD生长工艺要求极高，通常需要极高的温度控制，且需要精确控制反应气体的配比，而III族金属有机源的分解温度与V族氢化物源的分解温度有较大差异，因此当控制使III族金属有机源和V族氢化物源的温度不同时，可以减少副反应的发生，提高III-V族化合物半导体薄膜的质量和沉积速率，同时防止III族金属有机源和V族氢化物源的浪费。此时所述第一进气装置的温度小于所述第二进气装置的温度，但不应以此限制本申请的保护范围。值得说明的是，在第一进气装置传输III族金属有机源和第二进气装置传输V族氢化物源的同时，第一进气装置和第二进气装置还可以同时传输载气，如氢气或氮气。
如图9所示，在本实施例中，在主腔体101的底部还设置至少一排气口，排气管路109的一端连接排气口，另一端连接抽气泵1013，通过该抽气泵1013对主腔体101进行抽气作业，以抽走多余的等离子体，进而减少多余的离子落到薄膜上的几率，提高薄膜的质量。在主腔体101的底部还设置第二阀体1014，第二阀体1014位于排气口上，当进行抽气作业时，第二阀体1014
处于打开状态，当完成沉积作业时，第二阀体1014可以处于关闭状态，以防止等离子体扩散出去。
如图8和图12所示，在本实施例中，该主腔体101还包括基板入口，传送腔110内的机械臂通过该基板入口将基板放置在主腔体101内。该基板入口包括两个伸缩门1011。当两个伸缩门1011打开时，也就是打开基板入口。当两个伸缩门1011关闭时，也就是关闭基板出口。该主腔体101还连接一锁紧单元1012，当拆卸该主腔体101时，该锁紧单元1012可以使得基板入口保持锁紧状态，也就是当主腔体101断电后，锁紧单元1012可以使得基板入口保持关闭或锁紧状态。当基板入口保持锁紧状态时，可以防止主腔体101内剩余的等离子体向无尘室内扩散，从而防止造成无尘室重金属污染。
如图9所示，在本实施例中，该基板入口还可以作为基板出口，也就是说机械臂通过该基板入口将基板放进主腔体101内或者将基板拿出主腔体101。在一些实施例中，主腔体101还可以包括一基板出口，也就是说基板出口与基板入口相对设置，因此当机械臂通过基板入口将基板放置在主腔体101内，然后通过基板出口将基板拿出主腔体101。由于基板出口和基板入口相对设置，因此打开基板出口时，主腔体101内的重金属粉尘不会扩散至无尘室内，因此不会造成无尘室污染。
如图13所示，在一些实施例中，第二管路1042的端部还可以设计成弯折状，所述弯折状朝向射频组件103和底座102之间，使得气体在射频组件103和底座102之间扩散。
如图1和图9所示，在本实施例中，半导体设备100包括传送腔110和可拆卸腔体，传送腔110内的机械臂将基板传送或传出可拆卸腔体内，当在任意一腔体完成作业时(包括预热、清洗、沉积、生长以及冷却)，通过关闭第一阀体和第二阀体，从而气源内的气体无法进入可拆卸腔体内，同时可拆卸腔体内的反应气体也无法从排气口内排出，同时通过锁紧单元关闭可拆卸腔体的基板入口，然后将该可拆卸腔体移动至另一无尘室内，打开基板入口，然后取出基板，从而避免造成原来无尘室的重金属污染，然后可以对可拆卸腔体进行保养，然后在将该可拆卸腔体设置在传送腔110的外侧。
如图14，在一些实施例中，半导体设备100的镀膜系统180内设置有多个反应腔170，反应腔170可以是物理气相沉积设备中的生长腔，也可以是化学沉积设备中的沉积腔。在本实施例中，反应腔170例如包括第一反应腔171和第二反应腔172。且第一反应腔171和第二反应腔172上均设置有两个腔门，例如为第一腔门173和第二腔门174。每个腔门与一个基板装卸机械手臂111对应传送，例如包括与第一腔门173对应的第一机械手臂111a，以及与第二腔门174对应的第二机械手臂111b，且反应腔170的一侧还设 有进气管路183以及传输轨道181。且第一反应腔171和第二反应腔172之间通过开闭阀门连接，可方便运输基片，并提高加工效率。
如图14所示，第一腔门173和第二腔门174设置在第一反应腔171和第二反应腔172上，在一些实施例中，第一腔门173和第二腔门174设置在反应腔的同侧，在其他实施例中，第一腔门173和第二腔门174设置在反应腔的相对侧设置。第一腔门173和第二腔门174的具体结构可以为图12所示的伸缩门，在此不再次叙述。且在实际的薄膜生长过程中，第一腔门173作为基板入口/基板出口，第二腔门174作为基板出口/基板入口。将基板出口与基板入口分开，可减少基片的污染。与腔门对应设置的基板装卸机械手臂111，包括第一机械手臂111a和第二机械手臂111b。在基板的传送过程中，第一机械手臂111a例如可以通过第一腔门173将基板传入反应腔170内，第二机械手臂111b例如可以通过第二腔门174将基板从反应腔170内传出。设置两个机械臂可方便基板的拾取，同时传入和传出基板，且将传入和传出的基板装卸机械手臂111区分，可进一步减少基片的污染，进而可以提高沉积薄膜的质量和均匀性。
如图14所示，基座152(或底座102)设置在反应腔170的顶部，靶材153(或射频组件103)设置在反应腔170的底部。与图5(或图9)中的位置相反，反应物由下而上运动。在一些实施例中，基座152上具有固定卡扣，用于固定基片。在本实施例中，基座152为磁性基座，允许在靶材153的相对侧放置多个磁性基座，此时，基座152可直接将基板吸附在基座152上，而不需要其他的结构固定基板。基座152可包括蓝宝石，碳化硅，硅，氮化镓，金刚石，铝酸锂，氧化锌，钨，铜和/或铝氮化镓等材料制成，且可以将基座152蒸镀上金属层，使得基座152具有金属性。在基座152内设置磁体，使基座152具有吸附功能。磁体在作旋转运动时，基座152可绕自身中心轴旋转。当磁体进行旋转时，可以通过动力源如电机来驱动基座152环绕自身中心轴旋转，使得磁体所产生的磁场紧紧吸附基座152，进一步提高沉积薄膜的质量和均匀性，且基座152的尺寸例如为2-12英寸。
如图14所示，传输轨道181将反应腔170与其他半导体设备连接，例如将腔门与其他半导体设备连接，其中其他半导体设备可以为清洗设备、预热设备或其他半导体设备。进气管路182连接外部气源，外部气源通过进气管路182向该反应腔170内送入气体。进气管路182可包括第一进气管路和第二进气管路，第一进气管路连接第一反应腔171，第二进气管路连接第而反应腔172，该进气管路的设计方便气体的输入输出。
本申请的半导体设备可制造高质量无污染的薄膜，例如金属薄膜、半导体薄膜、绝缘薄膜、化合物薄膜或其他材料的薄膜。
如图15所示，在本申请一实施例中，当利用本公开的半导体设备来制造一半导体外延结构20时，半导体外延结构20可包括衬底200，以及依次设于衬底200上的第一半导体层203、有源层204和第二半导体结构21。
如图15所示，衬底200可以为蓝宝石衬底200。在其他实施例中，衬底200也可以采用硅(Si)、碳化硅(SiC)、砷化镓(GaAs)、铝酸锂(LiAlO 2)等材料制成。
如图15至图16所示，在一些实施例中，衬底200可选用无极化效应的晶轴材料制成，或者在衬底200上形成一层特殊的铺平层，以对衬底200的晶相方向进行选择，消除压电效应对衬底200的影响。在一些实施例中，衬底200可以选用N面(1100)或A面(1120)的材料制成，例如可以选用SiCO 3，GaN以及SiC等材料制成。在其他实施例中，当衬底200为其他衬底200时，可在衬底200上形成铺平层，以消除晶格缺陷。铺平层的材料可以选用第IIA族元素与氮组成的化合物作，具体例如为非极性的AlN材料或者非极性GaN材料。选用特殊的晶轴材料或设置铺平层，可避免导入大电流时导致衬底200内晶格扭力的产生，进而产生压电空洞，导致材料的发热裂化。
如图15所示，在一些实施例中，为获取平整的衬底200表面，可对衬底200表面进行碎晶颗粒处理，并将衬底200表面的碎晶颗粒进行氧化，形成碎晶氧化物，再使用氧化物刻蚀液清洗碎晶氧化物，进而获取平整的衬底200表面。在一具体实施例中，衬底200例如为硅衬底，可通过研磨或者刨削等工艺进行初步表面加工，在衬底200表面形成硅的碎晶颗粒。碎晶颗粒的产生导致晶体晶格上出现应力痕，影响晶体的生长，因而需要对碎晶颗粒进行处理。在本实施例中，可选用物理或者化学的方法消除碎晶颗粒带来的影响。当使用物理方法时，可以在预热腔种加热衬底200，使得衬底200表面达到例如300～400度，同时向腔内通入氧气、或其他氧化物，使碎晶颗粒发生氧化反应，以生成碎晶氧化物。当使用化学方法时，可以使用双氧水等氧化剂与碎晶颗粒反应生成碎晶氧化物。在反应过程中，可以通过升温的方法提高氧化反应速率，温度的范围例如为40～80度。在本实施例中，碎晶氧化物为二氧化硅，在进行氧化后，衬底200表面形成一层致密的二氧化硅层，可通过氧化物刻蚀液清洗，进而获取完整晶型。在本实施例中，可以使用氢氟酸或氨去除碎晶氧化物。在其他实施例中，衬底200材料不限于硅衬底200，也可以选取SiC衬底200以及其他衬底200，因衬底200的材料不同，可以选用不同的方法氧化碎晶颗粒，以及不同的溶液去除碎晶氧化物。
如图15所示，在一些实施例中，会在第一半导体层203和衬底200之间设置缓冲层201，以减缓第一半导体层203和衬底200之间的晶格不匹配，进而导致位错、层错或者空洞型的缺陷。缓冲层201的材料可以但不仅限制为氮化铝、氮化镓等材料，但缓冲层201并不足以解决晶格不匹配的问题。在本实施例中，通过在衬底200和缓冲层201之间设置一层过渡金属层，可进一步减缓第一半导体层203和和缓冲层201之间的晶格不匹配问题。过渡金属层的材料可选用第IIA族元素，例如可以选用铝。在衬底200上沉积一层过渡金属层后，再对过渡金属层进行退火处理，在硅衬底200表面和过渡层之间形成退火界面，在退火时，过渡金属层中的金属Al和衬底200中的Si的晶格转换，进而减少了直接在硅底上生长缓冲层201产生的位错等缺陷。其中退火温度的范围可以为例如400-600度，退火处理的时间范围可以为例如5～30分钟。
如图15所示，在另一些实施例中，缓冲层201例如包括周期性的氮化铝层和遮挡层，因只有氮化铝层作为缓冲层的缺陷过多，可进行在氮化铝层内周期性插入遮挡层，以改善晶格缺陷。具体可先生长厚度例如为10～25nm的氮化铝层，并停止生长。此时将反应腔的温度设置为例如500～1000度，并使用氮氧化物或氧气吹扫氮化铝层的表面，进而在氮化铝层的表面形成厚度例如为3～5nm氧化铝层，作为遮挡层。遮挡层可阻挡晶格缺陷，以改善缓冲层201的质量。其中氮氧化物可以为一氧化二氮(N 2O)、二氧化氮(NO 2)或氧气(O 2)。如此重复生长氮化铝层，再在氮化铝层上形成遮挡层，最终形成厚度例如为20～300nm的缓冲层201。其中每层遮挡层都可减缓其上一层氮化铝层中的晶格缺陷，使缓冲层201的厚度越高，缺陷越少。具体跟根据所需缓冲层201的厚度设置每次生长的氮化铝层厚度，本申请对此并无限制。
如图15所示，在其他实施例中，缓冲层201例如为氮化镓层。具体可在温度例如为500～850℃，又例如为500～550℃，反应腔压力例如为100Torr～650Torr，又例如为200～500Torr的条件下，向反应腔内通入氨气和三甲基镓(TMGa)，进而在衬底200上生长一层厚度例如为200～400埃或400～600埃的氮化镓，形成缓冲层201。
如图15所示，在形成缓冲层201后，可在缓冲层201上生长一层无掺杂的氮化镓层202，具体可在温度例如为1000～1200℃，又例如为1050℃～1200℃，反应腔压力例如为100Torr～500Torr，有例如为200～500Torr的条件下，向反应腔内通入氨气和三甲基镓(TMGa)，进而在缓冲层201上生长一层厚度例如为10000～30000埃的氮化镓，形成无掺杂的氮化镓层202。通过设置在衬底200和第一半导体层203之间设置缓冲层201和无掺杂的氮化镓层202，可减缓衬底200和第一半导体层203之间的晶格不匹配问题，提高半导体外延结构20的质量。
如图15所示，第一半导体层203例如为第一类型的氮化镓层，具体例如为N型氮化镓层，则第一半导体层203的掺杂离子可为硅。在本实施例中，可在温度例如为1000～1200℃，又例如为1050℃～1200℃，在反应腔压力例如为100Torr～600Torr，又例如为200～500Torr的条件下，向反应腔内通入氨气、三甲基镓(TMGa)和硅烷(SiH 4)，进而在无掺杂的氮化镓层202上生长一层厚度例如为10000～30000埃，又例如为20000～40000埃的N型氮化镓层。第一半导体层203中硅离子的离子浓度例如为1×10 18～7×10 18atom/cm 3，又例如为8×10 18～2×10 19atoms/cm 3。在一些实施例中，第一半导体层203可以为掺杂了硅离子的N型氮化镓层和非掺杂的氮化镓层的超晶格结构，在其他实施例中，第一半导体层203可以包括N型氮化镓层以及设置在N型氮化镓上的超晶格结构。
如图15所示，有源层204位于第一半导体层203上，在本实施例中，有源层204包括一个或多个交替形成的周期性量子垒层和量子阱层，且量子垒层例如包括GaN/AlGaN超晶格结构，量子阱层例如包括InGaN。有源层204的厚度例如为200nm～300nm，且每个周期的量子阱层的厚度例如为3nm～4nm，每个周期的量子垒层的厚度例如为12nm～16nm，其中，构成量子垒层的中GaN的厚度例如为1.5nm～3nm，构成量子垒层的中AlGaN的厚度例如为1.5nm～3nm。本实施例中的有源层204采用调制掺杂的GaN/AlGaN超晶格结构，可有效的引导冲击电流，使脉冲电流在GaN/AlGaN结构的二维电子气中，在横向方向上传导，使得脉冲电流的密度分布更加均匀，可以有效的提升电子与空穴的复合效率。
如图15所示，可在温度例如为810～860℃、压力例如为200～500Torr的条件下，生长一层厚度例如为1nm～3nm的GaN，然后在GaN上生长一层厚度例如为1nm～3nm调制掺杂的AlGaN。GaN和AlGaN组成一超晶格单元结构，交替连续生长2～6个周期的超晶格单元结构，可形成超晶格结构的量子垒层。在形成量子垒层后，改变生长条件，在温度例如为710～760℃、压力例如为200～500Torr的条件下，在量子垒层上生长厚度例如为2～6nm的InGaN，形成量子阱层，其中铟源例如为三甲基铟(TMIn)。交替连续生长2～6或9～12个周期的量子垒层和量子阱层，可形成有源层204。
如图15所示，在一些实施例中，第二半导体结构21可包括第二半导体层205和空穴注入层22，第二半导体层205位于有源层204上，空穴注入层22位于第二半导体层205上。其中第二半导体层205为电子阻挡层，可以为第二类型的氮化镓层，或可以为第二类型的氮化铝镓层，也可以为采用非或低掺杂镁的AlGaN制成，在一些实施例中，第二半导体层205包括3～10周期循环的P型GaN层和P型AlGaN层。
具体的，如图15所示，在一实施例中，第二半导体层205为P型AlGaN层，则可以在温度例如为700～950℃、压力例如为50～500Torr的条件下，在有源层204上生长厚度为5～10nm的AlGaN，形成P型AlGaN层，其中Mg掺杂浓度为0～1×10 16atom/cm 3。
具体的，如图15所示，在其他实施例中，第二半导体层205包括单层的P型GaN层和P型AlGaN层，则可以在温度为例如为700～900℃，压力例如为200～500Torr的条件下，生长厚度例如为20～30nm的GaN，形成P型GaN层，其中Mg的掺杂浓度为1×10 19～1×10 20atom/cm 3。之后在温度例如为800～950℃、压力例如为200～500Torr的条件下，在P型GaN层上生长厚度例如为5～10nm的AlGaN，形成P型AlGaN层，其中Mg掺杂浓度例如为1×10 19atom/cm 3。
具体的，如图15所示，在又一实施例中，第二半导体层205包括周期性的P型GaN层和P型AlGaN层，则可以在温度例如为700～800℃、压力例如为200～500Torr的条件下，在有源层204上生长厚度例如为5～10nm的GaN，形成P型GaN层，其中Mg掺杂浓度为1×10E 19atom/cm 3。在温度例如为700～950℃、压力例如为50～500Torr的条件下，在P型GaN层上生长厚度例如为5～10nm的AlGaN，形成P型AlGaN层，其中Mg掺杂浓度为0～1×10E16atom/cm 3。并交替连续生长3～10个周期的P型GaN层和P型AlGaN层。
如图15所示，空穴注入层22位于第二半导体层205上，且空穴注入层22包括非或低掺杂In xGa yN层，和/或掺杂In xGa yN层，即空穴注入层22包括In xGa yN层，且0≤x≤1,0≤y≤1。其中非掺杂In xGa yN层为未掺杂其他离子的In xGa yN层，掺杂In xGa yN层例如由掺杂了Mg的In xGa yN制成。
如图15所示，在一具体实施例中，第二半导体层205例如为P型氮化铝镓层，其上设置的空穴注入层22至少包括第一掺杂层206和第二掺杂层207，第一掺杂层206位于第二半导体层205上，第二掺杂层207位于第一掺杂层206上。第一掺杂层206为非或低掺杂InxGayN层，且第一掺杂层206的掺杂浓度例如为第一掺杂浓度，第二掺杂层207为掺杂InxGayN层，且第二掺杂层207的掺杂浓度例如为第二掺杂浓度，第二半导体层205例如具有第三掺杂浓度。其中第一掺杂浓度小于第二掺杂浓度，第三掺杂浓度小于第二掺杂浓度，且第一掺杂浓度的范围为0～1×10 19atom/cm 3。且第一掺杂层206的厚度小于第二掺杂层207的厚度，第一掺杂层206的厚度例如为第二掺杂层207厚度的40％～50％，具体例如为第二掺杂层207厚度的30％。
如图15所示，在本申请又一实施例中，空穴注入层22包括第一掺杂层206和第二掺杂层207，且第一掺杂层206为非掺杂InxGayN层，第二掺杂层207为掺杂InxGayN层，即第一掺杂层206的第一掺杂浓度为零，第二掺杂层207为掺杂了镁的InxGayN层。
如图15所示，在其他实施例中，空穴注入层22还包括第三掺杂层，第三掺杂层位于第二掺杂层207上，第三掺杂层例如为掺杂了镁的InxGayN，且第三掺杂层的第四掺杂浓度大于第二掺杂浓度。
如图15所示，在一具体实施例中，第一掺杂层206为非掺杂InxGayN层，第二掺杂层207为低掺杂InxGayN层，第三掺杂层为掺杂InxGayN层。则在温度例如为800～950℃，压力例如为200～500Torr的条件下，生长厚度例如为2～5nm的GaN，形成的非掺杂InxGayN层为第一掺杂层206。其次，在在温度例如为800～950℃，压力例如为200～500Torr的条件下，生长厚度为例如5～50nm的GaN，其中，镁的掺杂浓度例如为1×10 16～1×10 17atom/cm 3，形成低掺杂InxGayN层为第二掺杂层207。最后，在温度例如为800～950℃，压力例如为200～500Torr的条件下，生长厚度例如为10～20nm的GaN，其中，镁的掺杂浓度为1×10 18～1×10 19atom/cm 3，形成掺杂InxGayN层为第三掺杂层。
如图15所示，在本申请再一实施例中，掺杂In xGa yN层包括但不限由n层In x1Ga y1N、In x2Ga y2N、In x3Ga y3N的叠加，或是交替的In x1Ga y1N与In x2Ga y2N的n个周期循环，其中n≥1，X3<X2<X1≤1，Xn<...<X3<X2<X1≤1。在一具体实施例中，N等于3，X1等于1，X2等于0.2，X3等于0.05，即空穴注入层22包括依次设置的InN、In 0.2Ga 0.8N、In 0.05Ga 0.95N掺杂层。本申请中所述的空穴注入层22能有效提高外延结构的空穴浓度，提高发光效率。
如图17所示，在本申请另一实施例中，还提供一种高波长稳定性好的半导体外延结构20，且所述半导体外延结构20为一种绿光外延结构，且有源层204例如包括应力释放层208、第一有源层209和第二有源层210，且第一有源层209位于应力释放层208上，第二有源层210位于第一有源层209上。
如图17所示，应力释放层208的材料为InxGa(1-x)N和GaN，其中0.17<x<0.35，且GaN中掺杂有硅离子，且硅离子的掺杂浓度例如为a，且a范围为5×10 17～1×10 18atoms/cm 3，且应力释放层208的厚度为3～40nm。具体的，应力释放层208可包周期循环的量子阱层和量子垒层，且应力释放层208的生长周期例如为2～6，又例如为3。在本实施例中，可在温度例如为750～950℃，反应腔压力例如为200～500Torr的条件下，通入流量例如为30000～60000sccm的氨气(NH3)、50～100sccm的三乙基镓(TEGa)和500～1000sccm的三甲基铟(TMIn)和100～130L/min的氮气(N2)，进而在第一半导体层203上生长一层1nm～3nm的InGaN，形成量子阱层。之后，可以在温度例如为750～950℃，反应腔压力例如为200～500Torr的条件下，通入流量为30000～60000sccm的氨气(NH 3)、100～200sccm的三甲基镓(TMGa)、100～130L/min的氮气(N2)及1～2sccm的硅烷(SiH 4)，进而在量子阱层上生长一层30～40nm的N型GaN层，形成量子垒层。重复生长2～6个周期的量子阱层和量子垒层，可获得应力释放层208。
如图17所示，第一有源层209包括例如3～8个周期循环的势垒层和势阱层，所述周期数具体例如为5。在一些实施例中，势垒层的材料例如为AlzGa(1-z)N，且0≤z<0.3，势阱层的材料例如为InyGa(1-y)N，且0.17<y<0.4。其中势垒层中掺杂有硅离子，且硅离子的掺杂浓度为b，且a>b，且b范围为5×10 16～1×10 17atoms/cm 3。在其他实施例中，势垒层的材料还可以为GaN，或AlGaN与GaN的交替生长的2～6个周期的超晶格层，且势垒层的厚度L1例如为70～150埃，又例如为120埃。在本实施例中，可以在温度例如为750～900℃，反应腔压力例如为200～500Torr的条件下，向反应腔通入流量为50000-70000sccm的氨气(NH 3)、200-1000sccm的三乙基镓(TEGa)、1-2sccm的硅烷(SiH 4)及100-130L/min的氮气(N 2)，进而在应力释放层208上生长一层1nm～3nm的N型GaN，形成势垒层。进一步的，在温度例如为710～760℃。反应腔压力例如为200～500Torr的条件下，在势垒层上生长一层厚度为2～6nm的InGaN，形成势阱层。重复生长3～8个周期的势垒层和势阱层，可形成第一有源层209。
如图17所示，第二有源层210包括2～6个周期循环的In uGa 1-uN和GaN，所述周期具体例如为3，且第二有源层210内In uGa 1-uN的铟含量为0.17<u<0.40，第二有源层210的GaN内掺杂有硅离子，且硅离子的掺杂浓度为c，且a>c>b，c范围为5×10 16-1×10 17atoms/cm 3且c可以是b的1.4倍。在本申请一具体实施例中，第二有源层210包括材料为N型GaN的量子阱层，以及材料为InGaN的量子垒层。在其他实施例中，量子阱层也可以为非掺杂Si的GaN与掺Si层的GaN的超晶格层。在本实施例中，例如在温度例如为750～900℃，反应腔压力例如为200～500Torr的条件下，向反应腔内通入流量例如为50000-70000sccm的氨气(NH 3)、200-1000sccm的三乙基镓(TEGa)、1-2sccm的硅烷(SiH 4)及100-130L/min的氮气(N 2)，进而在第一有源层209上生长除一层1nm～3nm的N型GaN，可形成量子阱层，量子阱层的厚度L2的范围为70～150埃，且L1>L2＝100埃。进一步的，在在温度例如为710～760℃，反应腔压力例如为200～500Torr的条件下，在量子垒层上生长一层厚度为2～6nm的InGaN，形成量子阱层。重复生长2～6个周期的量子垒层和量子阱层，可形成第二有源层210。
如图17所示，第二半导体结构21包括第二半导体层205、第三半导体层211和第四半导体层212， 且第三半导体层211位于第二半导体层205上，第四半导体层212位于第三半导体层211上。且第二半导体层205为P型AlGaN层，第三半导体层211和第四半导体层212为P型GaN层，P型GaN层例如是掺杂Mg的GaN层，且第四半导体层212的掺杂浓度大于第三半导体层211的掺杂浓度。在本实施例中，可在温度例如为700～800℃，反应腔压力例如为200～500Torr的条件下，有源层204上生长厚度为5～10nm的AlGaN，形成第二半导体层205。其中，第二半导体层205中Mg的掺杂浓度为1×10 18～1×10 19atom/cm 3。之后，在温度例如为800～950℃，反应腔压力例如为200～500Torr的条件下，生长厚度为20～30nm的GaN，形成第三半导体层211。其中，Mg的掺杂浓度为1×10 19～1×10 20atom/cm 3。最后，在温度例如为800～950℃，反应腔压力例如为200～500Torr的条件下，生长厚度为10～20nm的GaN，形成第四半导体层212。其中，Mg的掺杂浓度为1×10 18～1×10 19atom/cm 3。
如图18所示，在本申请又一实施例中，为保证形成的微型发光二极管不会因反应过快，而出现闪烁的情况，可在第一半导体层203和有源层204之间设置一特殊结构的电阻层214，可延迟二极管熄灭的时间。且具有特殊结构的电阻层214的半导体外延结构20可制成微型发光二极管，配合节能电源使用，可减少总通电时间，以节约能耗，同时可保持人眼感受相同亮度，减少闪烁带来的影响，进而降低强光对于人眼的伤害。
如图18所示，第一半导体层203为氮化镓层，且在氮化镓层上设置有超晶格结构213，将电阻层214设置在氮化镓层上，且位于氮化镓层和超晶格结构213之间。在本实施例中，氮化镓层例如包括轻掺杂的N型氮化镓层203a和重掺杂的N型氮化镓层203b。在重掺杂的N型氮化镓层203b设置一层电阻层214，并在电阻层214上设置超晶格结构213，有源层204位于超晶格结构213上。本实施例提供的电阻层214可减缓最终形成的微型发光二极管的放电速度，延长微型发光二极管的放电时间，避免因电源不稳定或占空比低导致的微型发光二极管的闪烁。
如图18所示，电阻层214的材料例如为AlxGa1-xN，且x<0.15，电阻层214的厚度例如为50～200nm，可避免电阻层214太薄不好控制生长，以及电阻层214太厚出现开裂现象。在光阻层上蚀刻有多个开孔215，开孔215的方向平行于电阻层214的生长方向，且开孔215的直径例如为3～20um，相邻开孔215之间的间距例如为3～10um。在本实施例中，可在温度例如为700～900，反应腔的压力例如为500mbar的条件下，在反应腔内通入气体三乙基镓(TEGa)、三甲基铝(TMAL)以及氨气(NH3)，采用金属有机化合物化学气相沉淀(MOCVD)的方式生成电阻层214。在生成的电阻层214后，采用电感耦合等离子体的蚀刻方法，蚀刻电阻层214形成开孔215，且开孔215穿透电阻层214，与重掺杂的N型氮化镓层203b接触。
如图19所示的蚀刻后的的半导体外延结构20的等效电路，C为不添加电阻层214时半导体外延结构20的等效电容，R 0为不添加电阻层214时半导体外延结构20的等效电阻，R L为电阻层214的等效电阻，且R L可通过调节电阻层214上开孔的数量或直径调节，E为半导体外延结构20两端的电压。则电容的放电公式为：Vt＝E×(exp(-t/R*C))，电容的放电时间为：t＝RC×Ln[E/Vt]，且R＝R 0+R L。由上述公式可知，放电时间的长短与电阻R呈正比，电阻R越大，电子流动越困难，放电时间越长。可根据实际需求调节R L的大小，即可通过开孔215的数量和直径调整电阻层214的等效电阻，且开口的数量越多、直径越大，电阻层214的等效电阻越小，且开孔还可限制电流流出。
本申请中所形成高质量薄膜可应用于各种半导体结构、电子原件或电子装置中，例如开关元件、功率元件、射频元件、发光二极管、微型发光二极管、显示面板、手机、手表、笔记本电脑、投载式装置、充电装置、充电桩、虚拟现实(VR)装置、扩充现实(AR)装置、可携式电子装置、游戏机或其他电子装置。
如图20所示，本实施例提供的一种微型发光二极管，包括衬底200、设置在衬底200上的半导体外延结构20，且半导体外延结构20包括第一半导体层203、有源层204和第二半导体结构21，所述微型发光二极管还包括与第一半导体层203连接的第一电极226以及与第二半导体结构21连接的第二电极227。且衬底200例如为蓝宝石衬底200，所述半导体外延结构20可以为如图15、图16或图17所示的半导体外延结构20。在一些实施例中，在半导体外延结构20的一侧，如图15以及图16所示，可设置一缺口23，缺口23设置在半导体外延结构20的一侧，且缺口23的底部与第一半导体层203接触。在一些实施例中，缺口23与第一半导体层203的表面接触，在其他实施例中，可蚀刻第二半导体结构21、有源层204以及部分第一半导体层203，形成缺口23。
如图20所示，在第二半导体结构21上形成一层透明导电层220，透明导电层220覆盖第二半导体结构21，透明导电层220可采用氧化铟锡、氧化镓锌、氧化锌或氧化铟锌等材料制成。在一些实施例中，透明导电层220覆盖部分第二半导体结构21，在透明导电层220的两侧，透明导电层220与第二半导体层形成台阶228。在其他实施例中，透明导电层220可完全覆盖第二半导体结构21。当半导体外延结构20上设置有缺口23时，透明导电层220可覆盖第一半导体层203。
如图20所示，在形成透明导电层220后，可分别在第一半导体层203和透明导电层220上沉积金属材料，例如沉积钛/氮化钛阻挡层及金属钨，在第一半导体层203上形成第一导电插塞221，在透明导电层220上形成第二导电插塞222。第一导电插塞221和第二导电插塞222齐平，且第一导电插塞221覆盖部分第一半导体层203，第二导电插塞222覆盖部分透明导电层220。在一些实施例中，可在半导体外延结构20的一侧开设开孔，且开孔的底壁与第一半导体层203接触，在开孔的侧壁上铺设绝缘物质，并在开孔内以及开口上形成第一导电插塞221。在其他实施例中，半导体外延结构20上设置有缺口23，可直接在缺口23上形成第一导电插塞221。
如图20所示，在形成第一导电插塞221和第二导电插塞222后，在第一半导体层203和透明导电层220上依次沉积反射层223和保护层224。反射层223覆盖透明导电层220和台阶228，且暴露部分第一导 电插塞221和第二导电插塞222。保护层224覆盖反射层223，以及部分或全部第一导电插塞221和第二导电插塞222。在形成反射层223和保护层224后，蚀刻二极管芯片外侧的保护层224、反射层223和半导体外延结构20，形成沟槽229。在沟槽229内以及保护层224上沉积绝缘层225，绝缘层225完全覆盖第一导电插塞221和第二导电插塞222。对绝缘层225和保护层224进行蚀刻，在第一导电插塞221和第二导电插塞222上方形成开口，且开口暴露出部分第一导电插塞221和部分第二导电插塞222，且开口的面积大于第一导电插塞221和第二导电插塞222的径向尺寸，在开口内沉积金属，形成与第一导电插塞221连接的第一电极226，与第二导电插塞222连接的第二电极227。再经过激光切割与劈裂，点分完成后，形成微型发光二极管。
如图21所示，可在发光二极管上增加其他结构以改变微型发光二极管的出光方向，具体可根据具体需求改变微型发光二极管的出光方向。当微型发光二极管作为背光时，为减少混光距离，进而实现显示器等电子设备的超薄需求，可设置大角度的微型发光二极管。在一实施例中，可在微型发光二极管的衬底200上，且位于相对于半导体外延结构20的一侧，设置散光叠层230，以增加微型发光二极管的出光角度，使微型发光二极管的角度大于等于160度。为方便描述，本申请将半导体外延结构20所在的一侧定义为衬底200的上表面，将衬底200相对于半导体外延结构20的一侧定义为下表面。
如图21所示，散光叠层230包括设置在衬底200下表面的引光层231、第一反射层232、光震荡层233和第二反射层234。具体的，引光层231覆盖引光层231的下表面，且引光层231的折射率与衬底200的折射率相同，可保证光在引光层231上不发生偏转。引光层231的厚度可根发光层发出的光的波长以及引光层231的厚度设定，且引光层231的厚度符合的关系为：引光层231的厚度＝波长/4×折射率。在一些实施例中，衬底200为蓝宝石衬底200，蓝宝石的折射率为1.77，则引光层231选用与蓝宝石折射率相同的氧化铝(Al 2O 3)或氧化镁(MgO)制成。引光层231的厚度具体例如为10～200nm，又例如为60～80nm。在其他实施例中，当衬底200为其它材料制成时，可选择对应的引光层231材料，以及对应设置引光层231的厚度。
如图21所示，第一反射层232位于引光层231相对于衬底200的一侧，且第一反射层232覆盖引光层231。第一反射层232为正向反射层223，允许由衬底200方向发出的光穿过第一反射层232，第一反射层232相对于衬底200方向发出的光将被第一反射层232反射。在一些实施例中，第一反射层232为周期循环生长的三氧化二钛(Ti 2O 3)层和二氧化硅(SiO 2)层，且第一反射层232例如包括4～6个周期的Ti 2O 3和SiO 2，又例如包括5个周期的Ti 2O 3和SiO 2。其中三氧化二钛层覆盖引光层231，且三氧化二钛层的厚度例如为55～60nm，二氧化硅层覆盖三氧化二钛层，且二氧化硅层的厚度例如为90～100nm。
如图21所示，光震荡层233位于第一反射层232相对于引光层231的一侧，且光震荡层233覆盖第一反射层232。光震荡层233的折射率小于衬底200的折射率，在一些实施例中，光震荡层233可选用折射率为1.46的二氧化硅(SiO 2)、折射率为1.38的氟化镁(MgF 2)，折射率为1.351的氮化钛(TiN)或折射率为1.433的氟化钙(CaF 2)中的一种或多种制成。光震荡层233的厚度例如为100～500nm，又例如为300～400nm，可避免光震荡层233过厚，容易开裂，以及震荡层太薄，导致亮度损失太大，微型发光二极管最终发光的光的强度较弱。
如图21所示，第二反射层234位于光震荡层233相对于第一反射层232的一侧，且第二反射层234覆盖光震荡层233。第二反射层234为反向反射层223，第二反射层234相对于衬底200方向发出的光穿过，由衬底200方向发出的光将被第二反射层234反射。在一些实施例中，第二反射层234为周期循环生长的二氧化硅(SiO 2)层和三氧化二钛(Ti 2O 3)层，且第二反射层234例如包括2～3个周期的SiO 2和Ti 2O 3，且二氧化硅层的厚度例如为90～100nm，三氧化二钛层覆盖二氧化硅层，三氧化二钛层的厚度例如为55～60nm。
如图21所示，通过在微型发光二极管的衬底200下表面设置散光叠层230，当半导体外延结构20发出的光依次穿过引光层231、第一反射层232、光震荡层233后，被第二反射层234反射，在光震荡层233内发生偏折，当光反射或第一反射层232时，再被第一反射层232反射，最终从光震荡层233的侧边溢出。导致最终发出的光与衬底200所在的平面所呈的角度大于160度。
如图22所示，在另一实施例中，为避免在形成显示装置或照明装置时，微型发光二极管的发光角度过大，造成相邻不同颜色的微型发光二极管颜色互相干预。还可以通过在衬底200外侧加遮挡层235，以缩小微型发光二极管的发光角度。在本实施例中，可通过在微型发光二极管的外侧形成遮挡层235，以缩小发光角度。
如图22所示，遮挡层235设置在微型发光二极管的外侧，具体如图23、图24以及图25所示，遮挡层235设置在衬底200的外侧，且与衬底200的侧壁贴合。遮挡层235可覆盖衬底200的一个或多个侧面，可通过在衬底200侧壁的不同位置设置遮挡层235，以改变微型发光二极管的发光范围。在一些实施例中，如图24所示，遮挡层235可以覆盖例如衬底200相对的两个侧面，此时微型发光二极管的发光角度的范围例如为90～115度，最大发光角度例如为115度。在另一些实施例中，如图25所示，遮挡层235可以覆盖衬底200的例如四个侧面，此时微型发光二极管的发光角度的范围例如为90～105，最大发光角度例如为105度。在其他实施例中，遮挡层235覆盖衬底200的例如一个侧面，此时微型发光二极管的发光角度的范围例如为90～120，最大发光角度例如为120度。遮挡层235覆盖衬底200的例如三个侧面，此时微型发光二极管的发光角度的范围例如为90～110，最大发光角度例如为110度。
如图23，遮挡层235包括还原层236和镀膜层237，其中还原层236为衬底200侧壁的表面重新结晶与粗化形成。在本实施例中，衬底200例如是蓝宝石衬底200，可通过激光划边的方式将衬底200的侧壁重新结晶粗化。其中激光的光线波长例如为800～1200nm，通过激光将蓝宝石衬底200(Al 2O 3)重新结晶 成Al或AlO，最终重结晶后的衬底200侧壁表面可自然粗化。且重新结晶形成的Al或AlO均为不透光层且可以对光线进行反射，自然粗化的衬底200侧壁也可以增加反射。
如图22和图23，镀膜层237覆盖在还原层236上，且例如可以在真空环境下，且在压力例如为1×10 3～9×10 3torr的条件下，通过蒸镀或溅射的方式在还原层236上形成镀膜层237。其中镀膜层237包括多层组合层，例如包括第一组合层238和第二组合层239，且第二组合层239覆盖在第一组合层238上。镀膜层237可以为金属层组合层，也可以为氧化层组合层。在一些实施例中，第一组合层238的材料为Al，或者为Al和Ni，第二组合层239的材料为Ti或Pt，且镀膜层237的厚度例如为20～300nm。在其他实施例中，第一组合层238的材料为SiO 2或MgF 2，第二组合层239的材料为Ti 2O 5或SiNx，且镀膜层237的厚度例如为50～100nm。其中，当镀膜层237是氧化组合层时，镀膜层237可以包括多个循环设置的第一组合层238和第二组合层239。
如图26所示，在一些实施例中，半导体外延结构在长晶的过程中，半导体外延结构的表面可能会存在凹凸不平的缺陷，导致反射层223的效果不好。本实施例提供的一种微型发光二极管，可填平半导体外延结构的表面，同时可保证整体的膜层的应力平衡，避免因张应力造成镀膜层裂开，还可以增加出光效果。
如图26所示，半导体外延结构20与透明导电层220接触的表面上存在凹凸不平的缺陷，可在图20、图21或图22所示的微型发光二极管的基础上，在透明导电层220和反射层223之间设置复合填平层240，以改善半导体外延结构上的缺陷，在保护层224和绝缘层225之间设置压合层243，以确保整体的膜层应力平衡，避免因张造成镀膜裂开。
如图26至图27，填平层240位于透明导电层220相对于半导体外延结构的一侧，且覆盖透明导电层220。填平层240透明且不导电，且填平层240中的颗粒先粗后细。具体的，填平层240包括第一填平层240a和第二填平层240b，且第一填平层240a覆盖透明导电层220，且第一填平层240a的厚度例如为200～500nm，具体又例如为250nm或300nm，以完全覆盖半导体外延结构上的缺陷。第二填平层240b覆盖第一填平层240a，且第二填平层240b的厚度例如为50～300nm，以填满第一填平层240a内颗粒之间的间隙。
如图26至图27，在本实施例中，可采用PECVD沉积或蒸镀的方法在透明导电层220上形成填平层240，其中第一填平层240a的颗粒密度例如3～4g/cm 3，且第一填平层240a的材料例如为氧化铝(Al 2O 3)或氟化镁(MgF 3)，氧化铝的密度为3.5～3.9g/cm 3，氟化镁的的密度为3.148g/cm 3。第二填平层240b的颗粒密度例如为1.5～3g/cm 3，且第二填平层240b的材料例如为二氧化硅(SiO 2)或氮化硅(SiN)，二氧化硅的密度为2.2g/cm 3，氮化硅的密度为1.8～2.7g/cm 3。填平层240先使用粗颗粒形成第一填平层240a，镀的速度快，后面再补细颗粒填平形成第二填平层240b，就不会有空洞，且膜层质料好，不容易脱落。
如图26至图27，填平层240上设置有多个开孔241，且多个开孔241呈阵列设置。例如可以采用BOE蚀刻液湿蚀刻出开孔241，或采用电感耦合等离子体(ICP)干蚀刻的方法蚀刻出开孔241。开孔241呈柱状设置，且穿透第一填平层240a和第二填平层240b，其中开孔241的截面可呈圆形、方形、多边形或其他形状。在本实施例中，开孔241的孔径例如为3～5um，相邻开孔241之间的间隔例如为3～5um。孔径以及相邻开孔241之间的间隔设置可避免开孔241与间距过小，无法满足工艺需求，同时避免开口过大，填平层240与导电层之间的接触面积过小，而导致填平层240两侧电压差过高。
如图26所示，保护层224覆盖在反射层223上，压合层243覆盖在保护层224上，绝缘层225覆盖在压合层243上。压合层243包括第一压合层和第二压合层，且第二压合层覆盖在第一压合层上。在室温条件下，第一压合层和第二压合层的厚度之比例如为3：8。且第一压合层和第二压合层的厚度例如为30～600nm，可避免压合层243太薄无法作用，以及太厚会出现开裂等问题。在一些施例中，压合层243包括例如1层第一压合层和例如1第二压合层。在其他实施例中，压合层243包括多个周期循环的第一压合层和第二压合层。
如图26和图27所示，可采用PECVD沉积或蒸镀的方法在透明导电层220上形成压合层243，其中第一压合层的材料例如为二氧化硅(SiO 2)，第二压合层的材料例如为二氧化钛(TiO 2)或Ti 2O 5。
请结合图26和图28所示，微型发光二极管安装在基板244上时，可通过第一焊盘245将第一电极226焊接在基板244上，通过第二焊盘246将第二电极227焊接在基板244上。当基板244表现出压应力，基板244上设置的薄膜表现出张应力时，基板244和薄膜的两侧会向薄膜一侧翘曲。当基板244表现出张应力，基板244上设置的薄膜表现出压应力时，基板244和薄膜的两侧会向基板244一侧翘曲。在本实施例中，基板244在室温条件下会表现出较小的张应力，而压合层243薄膜的应力变化情况如下：第二压合层(TiO 2或Ti 2O 5)的厚度在300nm时，在室温下表现出的是张应力，例如为114Mpa，第一压合层(SiO 2)的厚度在400nm时，在室温表现出是压应力，例如为-56Mpa。因基板244本身是另一个方向的张应力，所以第一压合层与第二压合层厚度要在3:8的组合，此时压合层243表现出的应力将近为0，且有多一点压应力，可与基板244的表现出的张应力抵消。在其他温度时，基板244会因应力过大翘曲，可通过调整薄膜的应力，使基板244和基板244上的薄膜达到平衡。
如图29和图30所示，为了配合微型发光二极管高效节能的要求，对于倒装的亮度也需要越来越高。半导体外延结构在长晶的过程之中，由于表面易形成缺陷，产生表面凹凸不平，导致后面镀上反射镜之后，不会形成完全的镜面，导致于色散，光不集中，在封装成白光后，导致光效不好。本实施例提供的倒装微型发光二极管，如图29和图30所示，利用一特殊复合填平层240，使外延表面填平，且使得光垂直反射能力增加。同时使用一压合层243，确保整体的膜层应力平衡，避免因张应力造成镀膜层237裂开，同时此两种设计，也将倒装所需要的光垂直反射能力强化，以增加出光效。
如图31所示，微型发光二极管在使用时需要通过焊垫焊接在电路上，在焊接时，在焊垫与电极之间 易产生空洞，可在电极上形成一层特殊形状的金属叠层250，以增加电极可焊性的良率。在本实施例中，金属叠层250的厚度例如为20～100um，且包括介质层251和软性金属层252，介质层251设置在第一电极226和第二电极227上，软性金属层252设置在介质层251上。具体的，介质层251采用合金制成，且例如包括镍(Ni)层，以及金(Au)、锡(Sn)的合金。可在黄光条件下，在第一电极226和第二电极227上首先蒸镀或溅镀一层厚度例如为10～15nm的镍，再在镍上面蒸镀或溅镀一层厚度例如30～1000nm的金、锡合金，形成介质层251，且金、锡合金中金与锡的比例例如为80：20。其中介质层251在各点的厚度相同，整体呈柱状，具体可呈圆柱状。在第一电极226和第二电极227上形成一层介质层251，可防止软性金属层252扩散。
如图31所示，软性金属层252设置在介质层251上，且覆盖介质层251。软性金属层252采用金属或合金制成，例如为金(Au)、锡(Sn)或银(Ag)制成，或采用锡(Sn)的合金制成。可在黄光条件下，在介质呈上镀或溅镀一层厚度例如为20～100um的金属或者合金，形成软性金属层252。其中随着软性金属层252厚度的增加，软性金属层252的半径逐渐减小，软性金属层252具体例如可呈圆台设置。当微型发光二极管与焊垫焊接时，可以将焊垫与电极之间的空洞顺势赶出去，再利用软性金属的特性，可填补不平的焊垫区域，更可以加大容许衬底200翘曲的窗口，增加产品的可靠性。
如图32所示，在另一实施例中，可通过一种特殊的焊盘代替导电插塞和电极的作用，例如使用第一导电结构260代替第一导电插塞221和第一电极226，使用第二导电结构261代替第二导电插塞222。第一导电结构260和第二导电结构261具有伸缩性，可以是使用不平整的基板，以及焊接中回流焊的热膨胀产生的应力所产生的不良，同时减少封装空洞率。在本实施例中，第一导电结构260电性连接于第一半导体层，第二导电结构261电性连接于第二半导体层。第一导电结构260包括垫平层262、黏合层263、伸缩层264、叠嶂层265以及焊接层266，第二导电结构261包括黏合层263、伸缩层264、叠嶂层265以及焊接层266。
如图32所示，垫平层262设置在半导体外延结构20的第一半导体层上，且垫平层262的高度与透明导电层220的高度相等。通过设置垫平层262，可使第一导电结构260和第二导电结构261的高度相等，避免造成歪斜。可以在200～300度的条件下，采用化学气相沉积法在第一半导体层上沉积一层垫平层262。且垫平层262的材料例如为SiO 2、SiNx、Al 2O 3、MgO或AlN，垫平层262的厚度例如为900～1500nm，具体可与透明导电层220的高度相同。
如图32所示，第一导电结构260的黏合层263设置在垫平层262上，第二导电结构261的黏合层263设置在透明导电层220上，第一导电结构260和第二导电结构261的黏合层263高度相等。可以在开光黄的条件下，在垫平层262或透明导电层220上蒸镀或溅镀一层黏合层263。黏合层263的材料例如为Cr、Ni、Ti或氧化铟锡(ITO)，黏合层263的厚度例如为5～100nm，且黏合层263低于绝缘层225的高度。
如图32所示，第一导电结构260和第二导电结构261的黏合层263上设置有伸缩层264，且第一导电结构260上的伸缩层264和第二导电结构261上的伸缩层264高度相等。可以在开黄光的条件下，在黏合层263上蒸镀或溅镀一层伸缩层264。伸缩层264例为钛和铝的合金(Ti/Al)、镍和铝的合金(Ni/AL)、钛和银的合金(Ti/Ag)、或镍和银的合金(Ni/Ag)形成的复合层。伸缩层264高于绝缘层225，且伸缩层264的厚度例如为(50～200)*N nm，N的范围为3～9，当N值太小时，伸缩层264没有伸缩作用，当N数字太大，伸缩层264的电压偏高。
如图32所示，第一导电结构260和第二导电结构261的伸缩层264上设置有叠嶂层265，且第一导电结构260上的叠嶂层265和第二导电结构261上的叠嶂层265高度相等。可以在开黄光的条件下，在伸缩层264上蒸镀或溅镀一层叠嶂层265。叠嶂层265的材料例如为铂(Pt)和钛(Ti)的合金，或钛(Ti)和镍(Ni)的合金，且叠嶂层265的厚度例如为100～300nm。
如图32所示，第一导电结构260和第二导电结构261的叠嶂层265上设置有焊接层266，且第一导电结构260上的焊接层266和第二导电结构261上的焊接层266高度相等。可以在开黄光的条件下，在叠嶂层265上蒸镀或溅镀一层焊接层266。焊接层266的材料例如为锡(Sn)或金锡合金(AuSn)，且焊接层266的厚度例如为80000～100000nm。
如图33所示，微型发光二极管用于背光及照明时，由于各种不良环境的影响，常常造成微型发光二极管失效，尤其是水汽的渗入，对于微型发光二极管的损坏特别严重。本申请提供一种微型发光二极管，在发光区和电极上设置一特殊的防水保护层270，可以让水份不致停留在芯片上，使芯片保持干燥，进而避免水气的不良可防止水汽入侵。
如图33所示，防水保护层270包括保护膜层271、疏水性膜层272和水栅栏层273。其中，防水保护层270设置在透明导电层220以及部分第一电极226和第二电极227上，疏水性膜层272设置在防水保护层270上，水栅栏层273设置在疏水性膜层272上。请结合图32所示，防水保护层270覆盖透明导电层220，并向着第一电极226和第二电极227延伸，且覆盖第一电极226和第二电极227的侧壁以及部分顶壁。如图34所示，保护膜层271包括第一防水保护层274、第二防水保护层275和第三防水保护层276，第二防水保护层275设置再第一防水保护层274上，第三防水保护层276设置在第二防水保护层275上。且可以采用离子体增强化学的气相沉积法分别沉积第一防水保护层274、第二防水保护层275和第三防水保护层276。其中，第一防水保护层274为氧化层，且厚度例如为100～300nm。第二防水保护层275为氧化层与氮化层的渐变层，且厚度例如为20nm，第三防水保护层276为非亲水性材料的氮化层，且厚度例如为20～50nm。具体的，第一防水保护层274的材料例如为二氧化硅(SiO 2)，第二防水保护层275的材料例如为氮氧化硅(SiON)，第三防水保护层276的材料例如为氮化硅((SiNx)。
如图33所示，疏水性膜层272设置在防水保护层270上，并覆盖防水保护层270，且可以使用电子束 蒸镀(Electron Beam Evaporation)的方式形成疏水性膜层272，疏水性膜层272的厚度例如为2～5um。其中疏水性膜层272为超疏水的氮化层，例如可以为金属氮化层，具体例如可以为氮化硼(BN)或氮化铝(AlN)，以及其他超疏水的金属氮化层。
如图33和图35所示，水栅栏层273设置在疏水性膜层272上，可通过对疏水性膜层272退火再结晶，在疏水性膜层272上形成多个突出结构，以形成水栅栏层273。水栅栏层273的厚度大于或等于1um，具体例如为2um，且水栅栏层273的厚度具体例如为突出结构的高度。具体可以在形成疏水性膜层272的时候，设置较厚的疏水性膜层272，具体的，退火结晶前的疏水性膜层272的厚度等于最终形成的疏水性膜层272的厚度与水栅栏层273的厚度之和。在形成疏水性膜层272后，将疏水性膜层272的顶部在200～300度的条件下，快速高温退火或炉管退火，并持续时间30～60分后，使疏水性膜层272的顶部表面颗粒化，形成突出结构，多个突出结构组成水栅栏层273。
如图36(a)所示，一般亲水性表面上液滴边缘切线与基准面之间的夹角小于90度，如图36(b)所示，疏水性表面液滴边缘切线与基准面之间的夹角范围可以为例如90-150度，如图36(c)所示，超疏水性表面液滴边缘切线与基准面之间的夹角大于150度。本申请提供的保护膜层271的疏水性逐渐增强，在保护膜层271的最外层形成超疏水性表面，且在超疏水性的金属氮化层表面形成突出结构的水栅栏层273，进一步防止水汽入侵。
如图37所示，在将发光二极管转移至显示基板上后，需要将衬底200剥离，以提高亮度。因电极设置在半导体外延结构的两侧，且两个电极之间为空洞结构，在衬底200剥离时，易导致半导体外延结构产生龟裂，造成漏电死灯。本申请提供一种微型发光二极管，可防止衬底200剥离时，半导体外延结构断裂。
如图37所示，本实施例提供的一种微型发光二极管，在第一电极226和第二电极227之间形成支撑层280，且支撑层280填满第一电极226和第二电极227之间的间隙。具体可采用蒸镀、溅射或化学气相沉积法形成支撑层280，且支撑层280的材料例如为SiO 2、SiNx、Al 2O 3或类钻石膜(DLC)。支撑层280的高度不高于第一焊盘245和第二焊盘246，支撑层280的厚度具体例如可为300～4000nm。该微型发光二极管利用一个特殊的支撑层280，可以将会裂开的部份形成一个支撑，使其不会裂开，避免取晶顶伤，同时也可以避免因底层助焊剂或是锡膏扩散而导致漏电。
如图38，形成微型发光二极管后，需要将多个微型发光二极管转移至基板上，本申请提供一种半导体设备，可将多个微型发光二极管切割后转移至基板上。其中，本实施例所述的半导体设备例如为一种微型发光二极管转移装置，所述微型发光二极管转移装置上设置有矩阵切割条，可将衬底上的多个微型发光二极管的区分成独立的晶圆，且每个晶圆上中至少包括一个Mini LED或Micro LED。矩阵吸盘可将微型发光二极管转移至基板上。本实施例提供的微型发光二极管转移装置可进行一体化切割，可提高作业效率。
如图38所示，微型发光二极管转移装置包括基座301，筒座302设置在基座301上方，且筒座302内设置空槽，空槽的中性线与筒座302的中性线重合。升降台303设置在所述空槽内，升降台303顶面高出筒座302的顶面。旋转台304设置在升降台303上，悬臂305一端连接旋转台304，固定臂306连接悬臂305远离旋转台304的一端。转移板308设置在固定臂306下方，矩阵切割条309和矩阵吸盘310固定在转移板308，且矩阵吸盘310位于相邻矩阵切割条309之间。
如图38，基座301设置在微型发光二极管转移装置的底部，对整个微型发光二极管转移装置起支撑作用。且在一些实施例中，为了实现微型发光二极管转移装置的移动，基座301可以设置运动轮组，运动轮组可以配置止动板。在运动轮组和止动板的作用下实现整个微型发光二极管转移装置位置的灵活调节。基座301上方可以设置筒座302，筒座302固定在基座301的上表面中心位置。筒座302的形状可以为圆柱体，也可以为棱柱体等结构。筒座302的正投影落入基座301的上表面范围内。筒座302内部可以设置空槽，在一些实施例中，空槽可以为圆柱形空槽，圆柱形空槽的旋转轴线与筒座302的中轴线重合。筒座302的空槽内壁还可以设置润滑槽，润滑液在润滑槽中起润滑作用。升降台303设置在圆柱形空槽内，升降台303可以为圆柱体。升降台303的顶部高出筒座302，升降台303的内部设置有升降电机，控制升降台303在垂直方向上的运动。
如图38，旋转台304设置在升降台303上，旋转台304可以为圆柱体，旋转台304的中心轴线与升降台303的中心轴线重合，且旋转台304的直径小于升降台303的直径。在一些实施例中，旋转台304的内部设置有旋转马达，旋转马达控制旋转台304做双向圆周运动。旋转台304的侧面连接悬臂305。悬臂305与旋转台304焊接连接。悬臂305内部可以为中空结构，并可以设置有加强筋。悬臂305在旋转台304内部旋转电机的带动下沿着悬臂端部运动轨迹线314做双向圆周运动。
如图38和图39，悬臂305远离旋转台304的一端连接固定臂306，且固定臂306可以交叉设置。在一些实施例中，固定臂306可以设置两条，相互交叉呈90度设置。在其他实施例中，固定臂306的数量也可以为三条、四条或其他可以起到固定作用的数量。在固定臂306设置为两条的情况下，其交叉角度还可以为30度、45度、60度等不同的角度。固定臂306的端部设置有螺栓孔。
如图38和图39，转移板308设置在固定臂306的下方。转移板308上表面与固定臂306对应的位置设置有螺栓孔。转移板308通过螺栓307和固定板306连接。转移板308通过悬臂305在旋转台304内部旋转电机的带动下沿着悬臂端部运动轨迹线314做双向圆周运动，实现晶圆在不同加工工艺腔中的转移。转移板308的下表面设置矩阵切割条309和矩阵吸盘310。连接转移板308和矩阵切割条309固定在转移板308下方，且矩阵吸盘310位于相邻矩阵切割条309之间，矩阵吸盘310可批量提取并固定待转移至目标阵列基板的晶圆311裸片。
如图38和图39，矩阵切割条309和矩阵吸盘310固定在转移板308的下表面，且矩阵切割条309可以呈网格状分布，矩阵吸盘310交叉设置在矩阵切割条309的相邻切割条之间的区域。矩阵吸盘310的高 度小于矩阵切割条的高度。矩阵切割条309端部可以为倒梯形结构，也可以为棱锥形结构，也可以为其他类似结构的组合或者结合。
如图38和图41，晶圆311在载台12上完成不同的加工工艺过程，相邻晶圆之间形成切割槽。切割槽可以分为横向切割槽315和纵向切割槽316，切割槽的数量根据不同待加工晶圆的数量而不同。在一些实施例中，h1～h8为横向切割槽315，S1～S8为纵向切割槽316。矩阵切割条309对应横向切割槽315和纵向切割槽316，对晶圆311进行一体化切割，在横向和纵向上分割不同晶圆311。如图39所示，相邻晶圆311之间可以确定锯力线317，锯力线317垂直距离的切割面为应力集中面318。切割力由锯力线317作用于应力集中面318，分割完成后，矩阵吸盘310对晶圆311进行吸附固定。被吸附的晶圆311随着转移板308在旋转台304的旋转电机带动下沿着悬臂端部运动轨迹线314做双向圆周运动。在本申请的其他实施例中，可以将矩阵吸盘替换为如机械抓取、胶粘、静电吸附、气体吸附、电磁吸附等采用了相近原理的矩阵吸附体，实现晶圆311的一体化切割与转移。
如图41，在本实施例中，锯片从晶圆311表面划过，对于薄的晶圆，锯片降低到晶圆的表面划出一条深入1/3晶圆厚度的浅槽。芯片分离方法仍沿用划片法和钻石划线法中所述的圆柱滚轴施压完成。在其他实施例中，使用锯片将晶圆完全锯开单个芯片。对于要被完全锯开或切割透的芯片，首先将其粘贴在弹性较好且粘性较好的聚酯膜上，通常是蓝膜或UV膜。接着高速旋转的锯片按设定好的程式完全锯开晶圆。之后芯片还粘贴在聚酯膜上，这样会对下一步的提取芯片有所帮助。从聚酯膜上取下芯片，然后准备安放在封装中。在完成晶圆的一体化切割与转移后进行封装。按照封装胶的需要量取合适比例的环氧树脂、膨胀单体和固化剂，将膨胀单体和固化剂依次加入环氧树脂中，混合均匀，获得封装胶。分别将环氧树脂和固化剂预热至熔融透明液体状态，将膨胀单体添加至熔融的环氧树脂中，混合均匀，获得复配树脂，将熔融固化剂添加至复配树脂，高速搅拌5min，至混合均匀，获得熔融封装胶。通过灌胶设备将封装胶涂覆在二极管上，将涂覆了封装胶的二极管固化处理，封装胶将二极管封装。为保证二极管表面的平整性以及能够牢固的将二极管芯片封装，涂覆厚度大于二极管的厚度，其具体涂覆厚度可结合二极管的实际厚度以及封装要求进行选择。
如图42至图43，在一些实施例中，将微型发光二极管转移至基板244上后，基板244上设置有驱动电路296，发光二极管通过焊盘与驱动电路296连接，可形成微型发光二极管显示面板。在本实施例中，还提供一种微型发光二极管显示面板，包括基板244以及设置在基板244上的一种具有多个纳米孔的微型发光二极管，且纳米孔内设置有量子点。
如图42至图43，本实施例中的微型发光二极管包括第一半导体层291以及设置在第一半导体层291上的第二半导体层292。其中，第一半导体层291可以连接有电极，第一半导体层291例如为N型氮化镓层。第二半导体层292设置在第一半导体层291上，且第二半导体层292也为氮化镓层，且例如为N型氮化镓层。在第二半导体层292上设置有多个阵列状的纳米孔293，具体可以将N型氮化镓层浸入酸性溶液中并施加偏压，在N型氮化镓层中形成纳米级孔隙，从而驱动N型氮化镓层的电化学蚀刻，形成纳米孔293，且可以通过改变施加的偏压或GaN中硅掺杂浓度，改变纳米孔293的密度以及大小。
如图42至图43，在本实施例中，纳米孔293穿透第二半导体层292，当纳米孔293中不设置量子点时，微型发光二极管发出紫外光或蓝色光。在纳米孔内293中设置有红色量子点295时，微型发光二极管可以发出红色的光，在纳米孔293内设置有绿色量子点294时，微型发光二极管可以发出绿色的光。在第二半导体层292上，红色量子点295、绿色量子点294以及空置的纳米孔293依次排列。将量子点设置子纳米孔293内可以提高量子点的吸收率，延长量子点的使用寿命。
如图42至图43，在形成微型发光二极管显示面板时，基板244上设置有驱动电路296，且驱动电路296可以设置在基板244的表面，也可以设置在基板244内。将微型发光二极管与基板244键合后，驱动电路296可驱动微型发光二极管显示发光。在微型发光二极管上设置纳米孔293，并在纳米孔293内填充不同颜色的量子点，可避免不同色发光二极管的分拣，降低生产成本。
请参阅图44，本公开还提供一种电子装置，所述电子装置包括微型发光二极管显示面板600以及电子装置本体601，微发光二极管面板600与电子装置本体601连接，其中微发光二极管面板600包括电路基板和多个微型发光二极管芯片。电子装置本体601包括控制器602、存储器603、电源604。其中，电源604可以将市电(220V交流电)转换为控制器602和存储器603所需要的直流电，同时为微发光二极管面板600提供电源。存储器603与电源604连接，用于存储电子装置工作的相关数据，控制器602与电源604连接，同时与存储器603连接，电源604用于为控制器602供电，控制器所述执行存储器603内的程序控制所述电子装置。其中，电子装置可例如是显示面板、手机、手表、笔记本电脑、投载式装置、充电装置、充电桩、虚拟现实(VR)装置、扩充现实(AR)装置、可携式电子装置、游戏机或其他电子装置。
如图45所示，当应用本公开的半导体外延结构来制造半导体器件时，所述半导体器件包括衬底200、缓冲层201、第一半导体层203、第二半导体层205、源极701、漏极702以及栅极703。其中，缓冲层1401设置于衬底200上，第一半导体层203设置于缓冲层201上，第二半导体层205设置于第一半导体层203上，源极701形成于第二半导体层205上，漏极702形成于第二半导体层205上，栅极703形成于第二半导体层203上，且位于源极701和漏极702之间。在第二半导体层205上设置有源掺杂区705和漏掺杂区704，且源掺杂区705和漏掺杂区704例如为N型重掺杂区，且源极701设置在源掺杂区705上，漏极702设置在漏掺杂区704上。
如图46，当应用本公开的半导体器件来射频模组时，所述射频模组包括所述半导体器件。所述射频模组主要包括射频(radio frequency，RF)切换器件511、射频(radio frequency，RF)有源器件514、射频(radio frequency，RF)无源器件512和控制器件513。其中射频(radio frequency，RF)有源器件514可 以是本申请中的所述半导体器件，射频(radio frequency，RF)无源器件512可以是电容器、电阻器和电感器等无源器件。其中，射频(radio frequency，RF)切换器件511、射频(radio frequency，RF)有源器件514、射频(radio frequency，RF)无源器件512和控制器件513均形成于半导体衬底200上。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明，本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案，例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
除说明书所述的技术特征外，其余技术特征为本领域技术人员的已知技术，为突出本申请的创新特点，其余技术特征在此不再赘述。

Claims (20)

  1. 一种半导体设备，包括预热腔，且所述预热腔包括：
    壳体；
    加热器，设置在所述壳体的底部，以放置基板；
    电极，设置在所述壳体的顶部，且位于所述基板上方；以及
    升降旋转机构，与所述电极连接。
  2. 根据权利要求1所述的半导体设备，其中，所述预热腔的底部设置抽气口。
  3. 根据权利要求2所述的半导体设备，其中，所述预热腔内设置有射频电源，所述射频电源与所述电极连接。
  4. 根据权利要求1所述的半导体设备，其中，所述半导体设备包括传送腔，且所述传送腔上设置基板装卸机械手臂。
  5. 根据权利要求1所述的半导体设备，其中，所述半导体设备包括过渡腔，且所述过渡腔内设置有升降基座电机。
  6. 根据权利要求5所述的半导体设备，其中，所述升降基座电机设置在所述过渡腔腔体底部，且所述升降基座电机上设置载台。
  7. 根据权利要求6所述的半导体设备，其中，所述载台上设置托盘，所述托盘设置多层开口式传送盒。
  8. 根据权利要求7所述的半导体设备，其中，所述载台呈圆柱形或矩形。
  9. 根据权利要求5所述的半导体设备，其中，所述过渡腔设置有抽气口，且所述抽气口连接真空泵。
  10. 根据权利要求1所述的半导体设备，其中，所述半导体设备包括清洗腔，所述清洗腔的侧壁上设置有循环水冷装置。
  11. 根据权利要求10所述的半导体设备，其中，所述循环水冷装置呈波浪状设置。
  12. 根据权利要求1所述的半导体设备，其中，所述半导体设备包括生长腔，所述生长腔内设置有靶材，且所述靶材的受轰击面的直径设置为大于或等于400mm～600mm。
  13. 根据权利要求12所述的半导体设备，其中，所述生长腔内设置有保护环，所述保护环环绕所述靶材。
  14. 根据权利要求13所述的半导体设备，其中，所述保护环为陶瓷环或不锈钢环。
  15. 根据权利要求4所述的半导体设备，其中，所述半导体设备还包括至少一可拆卸腔，且所述可拆卸腔设置在所述传送腔的一侧。
  16. 根据权利要求15所述的半导体设备，其中，所述半导体设备还包括进气管路，其连接所述可拆卸腔体，以向所述可拆卸腔体内输送气体。
  17. 根据权利要求16所述的半导体设备，其中，所述进气管路通过进气口连接所述可拆卸腔体，所述进气口设置在所述可拆卸腔体的顶部。
  18. 根据权利要求16所述的半导体设备，其中，所述进气管路包括第一进气管路和第二进气管路，所述第一进气管路和所述第二进气管路通过转换接头连接。
  19. 根据权利要求18所述的半导体设备，其中，所述可拆卸腔体还包括一基板入口，所述基板入口连接锁紧单元，所述锁紧单元用于锁紧所述基板入口。
  20. 根据权利要求18所述的半导体设备，其中，所述可拆卸腔体还包括一基板出口，所述基板出口连接锁紧单元，所述锁紧单元用于锁紧所述基板出口。
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