WO2022062281A1 - 一种高阈值的功率半导体器件及其制造方法 - Google Patents

一种高阈值的功率半导体器件及其制造方法 Download PDF

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WO2022062281A1
WO2022062281A1 PCT/CN2021/072830 CN2021072830W WO2022062281A1 WO 2022062281 A1 WO2022062281 A1 WO 2022062281A1 CN 2021072830 W CN2021072830 W CN 2021072830W WO 2022062281 A1 WO2022062281 A1 WO 2022062281A1
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layer
region
columnar
metal electrode
manufacturing
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French (fr)
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孙伟锋
刘斯扬
张弛
辛树轩
李胜
钱乐
葛晨
时龙兴
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东南大学
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Definitions

  • the present invention relates to the technical field of semiconductor devices, in particular to a high-threshold power semiconductor device and a manufacturing method thereof.
  • the mainstream power devices on the market mainly include silicon-laterally diffused metal oxide semiconductor devices, gallium arsenide, indium phosphide, and silicon carbide materials. Due to the limitation of the physical properties of the material itself, it cannot meet the needs of the application. Therefore, the development of power devices with new materials is imminent.
  • wide-bandgap gallium nitride materials have become a research hotspot due to their excellent electrical and thermal properties.
  • Gallium nitride devices have high electron mobility, high breakdown voltage, high current density, high power density, low noise and good frequency characteristics, and have very broad application prospects.
  • Existing GaN field effect transistors are divided into a lateral structure and a vertical structure.
  • the distance between the active region must be increased, which will inevitably increase the chip area, and its performance is easily affected by the surface state of the material.
  • the typical representative of the vertical structure device is the fin device. Although it relatively improves the withstand voltage, it also faces many problems: because the electrons in the channel region are difficult to be depleted, the threshold voltage of the device is small, and the gate control ability is relatively low.
  • the general method is to increase the length of the source field plate and the gate field plate, but too long field plates will increase the parasitic capacitance of the device; since the electrons from the source to the drain must be buffered
  • the method of increasing the concentration of the drift region has to be adopted, which in turn reduces the voltage withstand capability of the device.
  • a traditional fin device is shown in Figure 1, and its structure mainly includes a drain metal electrode 1, a substrate 2, a buffer layer 3, a drift region 4, a heavily doped semiconductor layer 5c, a dielectric layer 6c, a gate metal electrode 7, and a passivation layer 6b , Source metal electrode 8 .
  • the channel region above the drift region is only depleted by the metal-semiconductor barrier to achieve the purpose of channel electron depletion so that the device is normally off, so the threshold voltage is often small.
  • the field plates of the gate metal electrode and the source metal electrode are indispensable and need to cover the terminal area.
  • the relatively large metal area brings about the problem of increasing gate capacitance, which will seriously affect the device switching characteristics.
  • the low threshold and high gate capacitance severely limit the application of fin devices in high voltage and high power fields.
  • the present invention proposes a high-threshold power semiconductor device capable of reducing the effective channel width of the device and its manufacture method.
  • a high-threshold power semiconductor device includes: a drain metal electrode, a substrate, a buffer layer and a drift region stacked from bottom to top, a drift region protrusion is formed protruding from a part of the drift region, and a drift region protrusion is formed on the drift region.
  • a columnar p region and a columnar n region are sequentially arranged on the protrusion, and a composite column is formed by the drift region protrusion, columnar p region and columnar n region, on the upper surface of the drift region, the outside of the composite column and the top of the composite column
  • a channel layer There is a channel layer, a passivation layer is arranged on the bottom surface of the channel layer, part of the drift region and part of the channel layer, passivation layer and composite column above it is divided into a cell region, and another part of the drift region and its upper part are divided into cell regions.
  • the part of the channel layer, passivation layer and composite column is divided into a terminal area, a dielectric layer is provided on the surface of the passivation layer and the outer side of the channel layer in the cell area, and a gate metal electrode is provided on the outer side of the dielectric layer.
  • a heavily doped semiconductor layer is arranged on the top surface of the channel layer in the cell region, and a source metal electrode is arranged on the heavily doped semiconductor layer; the passivation layer in the terminal region extends and wraps around the outside the channel layer.
  • the upper surface of the passivation layer is not higher than the lower surface of the columnar p region
  • the upper surface of the dielectric layer is not higher than the upper surface of the columnar n region, and is not lower than the upper surface of the columnar p region, the columnar p region
  • the lower surface of the p-region is higher than the lower surface of the gate metal electrode and the upper surface of the columnar p region is lower than the upper surface of the gate metal electrode;
  • the material of the channel layer is one of gallium nitride, aluminum gallium nitride and graphene, and its concentration is not less than the concentration of the drift region;
  • the composite cylinders are strip-shaped, or the composite cylinders are cylinders, and the composite cylinders are arranged in a honeycomb shape.
  • the method for manufacturing the high-threshold power semiconductor device according to the present invention includes the following steps:
  • Forming a columnar arrangement of composite pillars sequentially epitaxially forming a p-type semiconductor layer and an n-type semiconductor layer on the drift region, and then etching the p-type semiconductor layer, the n-type semiconductor layer and the drift region to form a parallel arrangement of A composite pillar formed by superimposing the drift region protrusion, the columnar p region and the columnar n region, the etching depth of the drift region is equal to the thickness of the drift region protrusion, and the thickness is 0.8 to 1.2 times the thickness of the columnar p region;
  • the channel layer deposit a layer of n-type gallium nitride material on the upper surface of the drift region, the outer side of the composite column and the top of the composite column by atomic layer deposition or chemical vapor deposition to obtain a channel Floor;
  • a layer of oxide is deposited at the bottom of the channel layer by atomic layer deposition or chemical vapor deposition to form a passivation layer, and the upper surface of the passivation layer is not higher than the lower surface of the columnar p-region; A part of the channel layer and the passivation layer thereon are used as the cell area, and the remaining part of the channel layer and the passivation layer thereon are used as the terminal area;
  • Atomic layer deposition or chemical vapor deposition method is used to deposit a layer of high-K dielectric material with a dielectric constant greater than silicon dioxide on the surface of the passivation layer and the sidewall of the channel layer in the cell region to obtain a dielectric
  • the dielectric layer on the sidewall of the channel layer is not higher than the upper surface of the columnar n region, not lower than the upper surface of the columnar p region, and the upper surface of the bottom of the dielectric layer is not higher than the lower surface of the columnar p region;
  • Manufacturing the gate metal electrode depositing metal on the sidewall of the dielectric layer of the cell region by magnetron sputtering to obtain the gate metal electrode, and the upper surface of the gate metal electrode is not higher than the upper surface of the columnar n region;
  • a layer of n-type gallium nitride is deposited on top of the channel layer in the cell region by atomic layer deposition or chemical vapor deposition, and the n-type nitride is heavily doped with magnesium ions.
  • a heavily doped semiconductor layer is prepared, the doping concentration of which is not lower than that of the drift region, and not higher than 2 ⁇ 10 19 cm -3 ;
  • Manufacturing the source metal electrode depositing metal on the heavily doped semiconductor layer in the cell region by magnetron sputtering or electron beam evaporation, and forming ohmic contact with the surface of the heavily doped semiconductor layer to obtain the source metal electrode;
  • Drain metal electrode thin the substrate by etching or grinding, deposit metal on the lower surface of the substrate by magnetron sputtering or electron beam evaporation, and form ohmic contact with the surface of the substrate to obtain drain metal electrode;
  • the gate metal electrode is selected from Ni/9u alloy or Pt/9u alloy
  • the source metal electrode is selected from Ti/Au alloy or Ti/Al/Ni/Au alloy;
  • the dielectric material is sapphire, rutile, calcium titanate or magnesium titanate, and the dielectric constant of the high-K dielectric material is greater than 3.7.
  • the present invention has the following advantages:
  • a columnar p-region 5a is arranged in the composite column, and the channel of the device is formed by secondary deposition on the surface of the composite column to form a highly doped channel layer 6a, which is shaped like a thin shell, so that the present invention is
  • the inventive channel layer is very thin, and in the on-state of the device, the on-current passes through the thin shell channel layer outside the columnar p-region 5a, therefore, compared with the conventional structure, the effective channel width of the device is significantly reduced (See channel layer 6a in FIG. 13).
  • the invention provides a method for manufacturing a columnar p-region, that is, a method of deposition and etching is used, which greatly reduces the difficulty of the process.
  • a p-type semiconductor layer is formed by MOCVD (vapor phase epitaxy), which is very suitable for It is suitable for growing various heterojunction materials, and the thickness is easy to control, so that the depth of the columnar p region can be easily controlled by controlling the thickness of the p-type semiconductor layer, and the large-area uniformity of the epitaxial layer is good; while the traditional ion implantation process needs to achieve the same It is technically difficult to achieve large-area high-concentration implantation, and high-energy ion implantation will cause more lattice damage, the ion implantation depth is difficult to control, and its cost is higher than MOCVD method is higher.
  • MOCVD vapor phase epitaxy
  • the etching process can easily determine the diameter of the columnar p region, and the requirements for the line width are low, which can be carried out under the current process level.
  • the width of the conductive channel is only determined by the thickness of the conductive material deposited on the outside of the columnar p-region. Depth is difficult to control.
  • the specific steps are: sequentially epitaxially forming a columnar p region 5a and a columnar n region 5b on the drift region, and then etching the columnar p region 5a and the columnar n region 5b in parallel at a certain interval, thereby forming a plurality of parallel arrangement and columnar extension
  • a channel layer 6a is prepared by depositing a layer of n-type gallium nitride material on the surfaces of the columnar p region 5a and the columnar n region 5b.
  • the present invention has a smaller effective channel width, thereby enhancing the effect of the Schottky barrier generated by the gold-semi-contact.
  • the electrons are further depleted, and the two effects superimpose each other, further reducing the concentration of electrons in the channel region, so the threshold value of the device can be greatly improved under the current process conditions (ie, the total channel width is not reduced).
  • the present invention can effectively refer to the capacitance characteristics of the device and further improve the switching characteristics of the device.
  • the traditional structure relies too much on the large-area source field plate to reduce the electric field at the bottom of the trench, thereby ensuring high blocking capability of the device, but greatly increases the parasitic capacitance of the device, resulting in poor switching characteristics; the present invention cleverly
  • the columnar p-region 5a is used to reduce the electric field at the bottom of the trench, which ensures the blocking capability of the device to a certain extent, and at the same time plays the role of replacing the source field plate, which greatly reduces the capacitance of the device and optimizes the switching of the device. characteristic.
  • the concentration of the drift region can be further increased, thereby greatly reducing the on-resistance and avoiding the waste of the breakdown voltage margin.
  • the composite column structure in the present invention is distributed in a honeycomb shape on the upper surface of the buffer layer, which meets the requirements of the minimum size of the through holes in the process requirements, and can maximize the lateral area of the device.
  • FIG. 1 is a front cross-sectional view of a conventional fin device.
  • FIG. 2 is a schematic diagram 1 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 3 is a schematic diagram 2 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 4 is a schematic diagram 3 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 5 is a schematic diagram 4 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 6 is a schematic diagram 5 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 7 is a schematic diagram 6 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 8 is a seventh schematic diagram of the method for manufacturing the high-threshold power semiconductor device according to the present invention.
  • FIG. 9 is a schematic diagram 8 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 10 is a schematic diagram 9 of the manufacturing method of the high-threshold power semiconductor device according to the present invention.
  • FIG. 11 is a tenth schematic diagram of the method for manufacturing the high-threshold power semiconductor device according to the present invention.
  • FIG. 12 is a flow chart of the method for manufacturing the high-threshold power semiconductor device according to the present invention.
  • FIG. 13 illustrates a front cross-sectional perspective view of a high-threshold power semiconductor device having a honeycomb arrangement of fin regions according to one embodiment.
  • FIG. 14 illustrates an isometric cross-sectional view of a high-threshold power semiconductor device in which the fin regions are arranged in straight strips, according to an embodiment.
  • FIG. 15 illustrates an isometric cross-sectional view of a high-threshold power semiconductor device with a channel layer of a graphene material, according to one embodiment.
  • FIG. 16 illustrates a front cutaway perspective view of a termination region p-buried grounded high-threshold power semiconductor device according to an implementation example.
  • FIG. 17 is a comparison diagram of the threshold voltage of the present invention and a conventional vertical gallium nitride semiconductor device. It can be seen from the figure that the threshold voltage of the present invention is approximately raised to about 1.5V.
  • FIG. 18 is a comparison diagram of the breakdown voltage of the present invention and a conventional vertical gallium nitride semiconductor device. It can be seen from the figure that the breakdown voltage of the present invention is significantly higher than that of the conventional device.
  • FIG. 19 is a comparison diagram of the input capacitance of the present invention and a conventional vertical gallium nitride semiconductor device. It can be seen from the figure that the input capacitance (Ciss) is reduced by about 93%.
  • a high-threshold power semiconductor device includes: a drain metal electrode 1, a substrate 2, a buffer layer 3 and a drift region 4 stacked from bottom to top, and part of the drift region 4 protrudes to form a drift region convex From 4a, a columnar p region 5a and a columnar n region 5b are sequentially arranged on the drift region bump 4a, and a composite column is formed by the drift region bump 4a, the columnar p region 5a and the columnar n region 5b.
  • a channel layer 6a is provided on the surface, the outer side of the composite column and the top of the composite column, a passivation layer 6b is provided on the bottom surface of the channel layer 6a, part of the drift region 4 and part of the channel layer 6a on it, passivation
  • the layer 6b and the composite pillar are demarcated as the cell region 9, and another part of the drift region 4 and part of the channel layer 6a, the passivation layer 6b and the composite pillar on it are demarcated as the terminal region 10, and the passivation in the cell region 9
  • the surface of the chemical layer 6b and the outer side of the channel layer 6a are provided with a dielectric layer 6c, the gate metal electrode 7 is provided on the outer side of the dielectric layer 6c, and a heavily doped semiconductor is provided on the top surface of the channel layer 6a in the cell region 9 Layer 5c, a source metal electrode 8 is provided on the heavily doped semiconductor layer 5c; the passivation layer 6b in the termination region 10 extends and wraps around the outside of
  • the upper surface of the passivation layer 6b is not higher than the lower surface of the columnar p region 5a
  • the upper surface of the dielectric layer 6c is not higher than the upper surface of the columnar n region 5b, and is not lower than the upper surface of the columnar p region 5a
  • the lower surface of the p region 5 a is higher than the lower surface of the gate metal electrode 7 and the upper surface of the columnar p region 5 a is lower than the upper surface of the gate metal electrode 7 .
  • the material of the channel layer 6 a is one of gallium nitride, aluminum gallium nitride and graphene, and its concentration is not less than that of the drift region 4 .
  • the composite cylinders are strip-shaped, or the composite cylinders are cylinders, and the composite cylinders are arranged in a honeycomb shape.
  • the dielectric layer 6c can be made of Al 2 O 3 or other materials.
  • the passivation layer 6b can be made of SiO 2 or other materials to form a single-layer or combined multi-layer structure, which plays the role of isolation and increasing withstand voltage.
  • the drain metal electrode 1 is in ohmic contact with the surface of the substrate 2, and is used as a current output port when the high-threshold power semiconductor device is turned on; the source metal electrode 8 is in ohmic contact with the surface of the heavily doped semiconductor layer 5c, which is in high
  • the power semiconductor device with the threshold value is used as the input port of current when it is turned on.
  • the concentration and thickness of the buffer layer 3 determine the withstand voltage characteristics, and the withstand voltage characteristics can be enhanced by appropriately reducing the doping concentration of the buffer layer 3 or increasing the thickness of the buffer layer 3 .
  • the gate metal electrode 7 is used to regulate the electron concentration in the fin channel to control the turn-on and turn-off of the gallium nitride semiconductor device.
  • the method for manufacturing the high-threshold power semiconductor device according to the present invention includes the following steps:
  • Forming a columnar arrangement of composite pillars sequentially epitaxially forming a p-type semiconductor layer and an n-type semiconductor layer on the drift region 4, and then etching the p-type semiconductor layer, the n-type semiconductor layer and the drift region 4 to form a parallel arrangement
  • the composite column is composed of the drift region protrusion 4a, the columnar p region 5a and the columnar n region 5b.
  • the etching depth of the drift region 4 is equal to the thickness of the drift region protrusion 4a and the thickness is equal to the thickness of the columnar p region 5a. 0.8 to 1.2 times;
  • the channel layer 6a using the atomic layer deposition or chemical vapor deposition method to deposit a layer of n-type gallium nitride material on the upper surface of the drift region 4, the outer side of the composite column and the top of the composite column to obtain The channel layer 6a, in this way, the channel layer 6a formed on the surface of the composite cylinder presents a thin shell with a very small thickness wrapped outside the composite cylinder. It can be seen that the effective channel width of the present invention can be made very small;
  • dielectric layer 6c Manufacture of dielectric layer 6c: using atomic layer deposition or chemical vapor deposition method to deposit a layer of high-K dielectric material with a dielectric constant greater than silicon dioxide on the surface of the passivation layer 6b and the sidewall of the channel layer 6a in the cell region 9 , the dielectric layer 6c is obtained, and the dielectric layer 6c on the sidewall of the channel layer 6a is not higher than the upper surface of the columnar n region 5b, not lower than the upper surface of the columnar p region 5a, and the upper surface of the bottom of the dielectric layer 6c is not higher than the lower surface of the columnar p-region 5a;
  • Manufacturing the gate metal electrode 7 depositing metal on the sidewall of the dielectric layer 6c of the cell region 9 by magnetron sputtering to obtain the gate metal electrode 7, and the upper surface of the gate metal electrode is not higher than the columnar n region The upper surface of 5b.
  • Manufacturing the heavily doped semiconductor layer 5c depositing a layer of n-type gallium nitride on the top of the channel layer 6a of the cell region 9 by atomic layer deposition or chemical vapor deposition, and performing magnesium ion heavy-duty on the n-type nitride. Doping to obtain a heavily doped semiconductor layer 5c, the doping concentration of which is not lower than that of the drift region 4 and not higher than 2 ⁇ 10 19 cm ⁇ 3 ;
  • Source metal electrode 8 depositing metal on the heavily doped semiconductor layer 5c of the cell region 9 by magnetron sputtering or electron beam evaporation, and forming an ohmic contact with the surface of the heavily doped semiconductor layer 5c to obtain source metal electrode 8;
  • drain metal electrode 1 Manufacture of drain metal electrode 1: thinning the substrate 2 by etching or grinding, depositing metal on the lower surface of the substrate 2 by magnetron sputtering or electron beam evaporation, and forming an ohmic contact with the surface of the substrate 2 , the drain metal electrode 1 is prepared;
  • the passivation layer 6b in the termination region 10 can extend and wrap around the outside of the channel layer 6a in the termination region 10.
  • the gate metal electrode 7 selects Ni/9u alloy or Pt/9u alloy
  • the source metal electrode 8 selects Ti/Au alloy or Ti/Al/Ni/Au alloy
  • the dielectric material is sapphire, rutile, calcium titanate or magnesium titanate, and the dielectric constant of the high-K dielectric material is greater than 3.7.
  • the buffer layer 3 and the drift region 4 are sequentially grown on the substrate 2 to obtain a wafer;
  • a p-type semiconductor layer is epitaxially formed on the drift region 4 by chemical vapor deposition; then an n-type semiconductor layer is epitaxially formed on the p-type semiconductor layer by chemical vapor deposition , and the thickness is the same as that of the p-type semiconductor layer.
  • the p-type semiconductor layer and the n-type semiconductor layer are etched until the drift region drift region 4 is exposed, and a plurality of columnar p regions 5a and columnar n regions 5b arranged in parallel and extending in columnar shape are formed; continue to etch A series of drift region protrusions 4a arranged in parallel are formed on the lower surface of the columnar p region 5a, and the columnar p region 5a, the columnar n region 5b and the drift region protrusions 4a together form a composite column.
  • a layer of n-type gallium nitride material is deposited on the upper surface of the drift region 4 , the outer side of the composite column and the top of the composite column by atomic layer deposition or chemical vapor deposition to obtain channel layer 6a.
  • a layer of oxide is deposited on the bottom of the channel layer 6a by atomic layer deposition or chemical vapor deposition to form a passivation layer 6b, and the upper surface of the passivation layer 6b is not higher than the columnar p-region the lower surface of 5a;
  • atomic layer deposition or chemical vapor deposition is used to deposit a layer of dielectric constant greater than silicon dioxide on the surface of the passivation layer 6b and the sidewall of the channel layer 6a in the cell region 9 3.7) high-K dielectric material, the dielectric layer 6c is obtained, and the dielectric layer 6c on the sidewall of the channel layer 6a is not higher than the upper surface of the columnar n region 5b, not lower than the upper surface of the columnar p region 5a, the dielectric layer The lower surface of 6c is not higher than the upper surface of columnar p-region 5a;
  • metal is deposited on the sidewall of the dielectric layer 6c of the cell region 9 by magnetron sputtering to obtain the gate metal electrode 7, and the upper surface of the gate metal electrode is not higher than the columnar n region 5b
  • the upper surface of the gate metal electrode 7 can be selected from Ni/9u alloy or Pt/9u alloy;
  • a layer of n-type gallium nitride material is deposited on the top surface of the channel layer 6a of the cell region 9 by means of atomic layer deposition or chemical vapor deposition, and the region is heavily doped to make A heavily doped semiconductor layer 5c is obtained;
  • a metal is deposited on the heavily doped semiconductor layer 5c by magnetron sputtering or electron beam evaporation, and an ohmic contact is formed with the surface of the heavily doped semiconductor layer 5c to obtain a source metal electrode 8.
  • the source metal electrode 8 is obtained.
  • the metal electrode 8 can be selected from Ti/Au alloy or Ti/Al/Ni/Au alloy; etching or grinding to thin the substrate 2, and using magnetron sputtering or electron beam evaporation on the lower surface of the substrate 2 Metal is deposited to form ohmic contact with the surface of the substrate 2 to prepare the drain metal electrode 1 .
  • a layer of oxide is deposited on the surface of the passivation layer 6b of the termination region 10 by atomic layer deposition or chemical vapor deposition, and the upper surface of the redeposited oxide is not higher than the surface of the passivation layer 6b.
  • the upper surface of the semiconductor layer 5c is doped so that the passivation layer 6b in the termination region 10 extends and wraps around the outside of the channel layer 6a in the termination region 10 .
  • the flow chart of the method for manufacturing a high-threshold power semiconductor device includes but is not limited to the important steps shown in the figure.
  • FIG. 13 it is a front cross-sectional perspective view of a high-threshold power semiconductor device of the present embodiment.
  • the composite cylinders are arranged in a honeycomb shape.
  • the honeycomb arrangement meets the minimum size requirement of the through hole in the process requirements, and can maximize the lateral area of the device.
  • this embodiment is different in that the columnar p region 5a, columnar n region 5b, channel layer 6a, and heavily doped power semiconductor device of the high-threshold power semiconductor device
  • the semiconductor layer 5c, the passivation layer 6b, the dielectric layer 6c, the gate metal electrode 7, and the source metal electrode 8 are distributed in straight stripes without the passivation layer 6b1, and other structures are the same as those in the first embodiment.
  • the manufacturing process of the straight-striped fingers is simpler and metal interconnection lines are reduced.
  • this embodiment is different in that the channel layer 6a of the high-threshold power semiconductor device is made of graphene, and other structures are the same as Embodiment 1.
  • Graphene has extremely high strength and flexibility, which improves the stability of the device; its thermal conductivity is higher than that of gallium nitride materials, so it has higher temperature stability; graphene is the best conductive material at room temperature, and its electronic
  • the mobility is about 140 times that of electrons in silicon, which is lower than that of copper or silver, and the conductivity can reach 10 6 S/m, so it has lower on-resistance under the same conditions.
  • this embodiment is different in that the p-ring structure of the high-threshold power semiconductor device is not in a floating state, but is grounded.
  • the specific method is as follows: before the last passivation process in Example 1, etching treatment is performed on some composite pillar regions of the cell region 9 and the terminal region 10, and then the metal tungsten 11 is filled, and the source metal electrode 8 is short-circuited. catch. The rest of the procedures are exactly the same as in Example 1.
  • the reason for filling metal tungsten is that tungsten has a high melting point and good electrical conductivity, and is not easy to chemically react with other non-metals.
  • the depletion layer formed by the columnar p region 5a has the same potential. This process can make the potential of part of the p-ring structure not float, effectively smooth the electric field at the bottom of the gate, and improve the voltage withstand capability of the device. .
  • the device is in the equilibrium state, that is, when the gate metal electrode 7 applies a voltage of 0V, the gate metal electrode 7 and the conductive channel 6a form a gold semi-contact, and the conductive channel 6a is close to the side of the gate metal electrode 7 through the Schottky barrier effect.
  • the columnar p-region 5a in the channel region assists in depleting the surrounding electrons. The two work together to completely deplete the electrons in the conductive channel 6a to achieve the purpose of pinch-off of the channel. Therefore, no current can be formed between the source metal electrode 8 and the drain metal electrode 1, and the device is in an off state.
  • the voltage of the gate metal electrode 7 starts to increase, the electrons on the side close to the dielectric layer gradually accumulate; at the same time, due to the gradual increase of the potential, the depletion layer formed by the columnar p region 5a gradually narrows, and the two work together , a stable electronic conduction channel is formed, and the current flows from the source metal electrode 8 through the heavily doped semiconductor layer 5c, the channel layer 6a, the columnar n region 5b, the columnar p region 5a, the drift region protrusion 4a, the drift region 4, The buffer layer 3 and the substrate 2 reach the drain metal electrode 1 , so that the device is turned on.

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Abstract

本发明公开了一种高阈值的功率半导体器件及其制造方法，自下而上顺次包括：漏金属电极、衬底、缓冲层、漂移区；还包括：漂移区上由漂移区凸起、柱状p区和柱状n区共同构成的复合柱体，沟道层、钝化层、介质层、重掺杂半导体层、栅金属电极和源金属电极；复合柱体是通过在漂移区上依次淀积p型半导体层和n型半导体层而后对其进行刻蚀形成；沟道层和钝化层依次通过淀积形成；由此以上器件被划分为元胞区和终端区，介质层、重掺杂半导体层、栅金属电极和源金属电极仅存在于元胞区，终端区的钝化层向上延伸并包裹于沟道层外侧。该结构可以提高器件阈值电压、提高器件阻断特性、降低栅电容大小。

Description

一种高阈值的功率半导体器件及其制造方法 技术领域
本发明涉及半导体器件技术领域，具体涉及一种高阈值的功率半导体器件及其制造方法。
背景技术
随着半导体器件材料和工艺的迅速发展，功率晶体管在各种集成电路中得到越来越广泛的应用。目前市场上主流的功率器件主要有硅-横向扩散金属氧化物半导体器件，砷化镓、磷化铟、碳化硅材料的器件等。由于受到材料本身物理特性的限制，其无法满足应用的需求，因此，发展新型材料的功率器件迫在眉睫。作为第三代半导体材料的代表，宽禁带氮化镓材料凭借其优异的电学和热学性能成为研究热点。氮化镓器件具有高电子迁移率、高击穿电压、大电流密度、高功率密度、低噪声及良好的频率特性，有着十分广泛的应用前景。
现有的氮化镓场效应晶体管分为横向结构和纵向结构。横向结构器件为了提高耐压必须增加有源区距离，这样势必会增加芯片面积，且其性能易受材料表面态的影响。纵向结构器件的典型代表是fin器件，虽然其相对提高了耐压能力，但是同样面临诸多问题：由于沟道区域内的电子难以被耗尽，导致器件的阈值电压偏小，栅极控制能力较差；为了提升器件耐压能力，一般采用的方法是增加源极场板和栅极场板的长度，但是场板过长会增加器件的寄生电容；由于电子从源极到达漏极必须经过缓冲层，势必会增加导通电阻，为了降低导通电阻，不得不采用增加漂移区浓度的方法，这种做法反过来又降低了器件的耐压能力。
传统fin器件如图1所示，其结构主要包括漏金属电极1、衬底2、缓冲层3、漂移区4、重掺杂半导体层5c、介质层6c、栅金属电极7、钝化层6b、源金属电极8。在该结构中，漂移区上方的沟道区域仅仅通过金属-半导体势垒耗尽来达到沟道电子耗尽的目的从而实现器件常关，因此阈值电压往往偏小。若要提高阈值，通常做法是减小fin的宽度，但该方法对刻蚀工艺要求较高。同时为了保证器件一定的阻断特性，栅金属电极、源金属电极的场板不可缺少，且需要覆盖到终端区域，相对较大的金属面积带来了栅电容增大的问题，从而会严重影响器件的开关特性。低阈值以及较高的栅电容严重限制了fin器件在高电压、大功率领域的应用。
发明内容
为了解决传统fin器件面临的阈值电压偏小、栅电容偏大、击穿电压无法满足实际要求等问题，本发明提出一种能够减小器件有效沟道宽度的高阈值的功率半导体器件及其制造方法。
本发明的技术方案如下：
本发明所述的一种高阈值的功率半导体器件，包括：由下至上层叠的漏金属电极、衬底、缓冲层以及漂移区，漂移区的部分区域上突形成漂移区凸起，在漂移区凸起上依次设有柱状p区和柱状n区并由漂移区凸起、柱状p区和柱状n区构成复合柱体，在漂移区的上表面、复合柱体的外侧及复合柱体的顶部设有沟道层，在沟道层的底面设有钝化层，部分漂移区及其上的部分沟道层、钝化层和复合柱体划作元胞区，另一部分漂移区及其上的部分沟道层、钝化层和复合柱体划作终端区，在元胞区内的钝化层表面及沟道层的外侧设有介质层，在介质层的外侧设有栅金属电极，在元胞区内的沟道层顶面上设有重掺杂半导体层，在重掺杂半导体层上设有源金属电极；所述终端区内的钝化层延伸并包裹于终端区内的沟道层外侧。
进一步地，所述钝化层的上表面不高于柱状p区的下表面，介质层的上表面不高于柱状n区的上表面、且不低于柱状p区的上表面，柱状p区的下表面高于栅金属电极的下表面且柱状p区的上表面低于栅金属电极的上表面；
进一步地，所述沟道层的材料为氮化镓、铝镓氮和石墨烯材料的一种，其浓度不小于漂移区的浓度；
进一步地，所述复合柱体为条状，或者，所述复合柱体为圆柱，各复合柱体呈蜂窝状排列。
本发明所述的一种制造所述一种高阈值的功率半导体器件的制造方法，包括以下步骤：
制造晶圆片：在衬底上依次生长缓冲层、漂移区制得圆晶片；
形成柱状排列的复合柱体：在漂移区上依次外延形成p型半导体层和n型半导体层，再对所述p型半导体层、n型半导体层和漂移区进行刻蚀，形成平行排列的由漂移区凸起、柱状p区和柱状n区叠加构成的复合柱体，漂移区的刻蚀深度等于漂移区凸起的厚度且所述厚度为柱状p区厚度的0.8～1.2倍；
制造沟道层：采用原子层沉积或化学气相沉积的方法在所述漂移区的上表面、复合柱体的外侧及复合柱体的顶部淀积一层n型氮化镓材料，制得沟道层；
制造钝化层：采用原子层沉积或化学气相沉积的方法在沟道层的底部淀积一层氧化物，形成钝化层，且钝化层的上表面不高于柱状p区的下表面；将沟道层的一部分区域及其上的钝化层作为元胞区，将沟道层的剩余部分区域及其上的钝化层作为终端区；
制造介质层：采用原子层沉积或化学气相沉积的方法在元胞区的钝化层表面和沟道层侧壁淀积一层介电常数大于二氧化硅的高K介电材料，制得介质层，且沟道层侧壁的介质层不高于柱状n区的上表面、不低于柱状p区的上表面，介质层底部的上表面不高于柱状p区的下表面；
制造栅金属电极：采用磁控溅射方式在所述元胞区的介质层的侧壁上沉积金属，制得栅金属电极，且栅金属电极的上表面不高于柱状n区的上表面；
制造重掺杂半导体层：采用原子层沉积或化学气相沉积的方法在元胞区的沟道层的顶部淀积一层n型氮化镓，并对n型氮化进行镁离子重掺杂，制得重掺杂半导体层，其掺杂浓度不低于漂移区的浓度，且不高于2×10 19cm -3；
制造源金属电极：采用磁控溅射或电子束蒸发的方法在所述元胞区的重掺杂半导体层上沉积金属，并与重掺杂半导体层表面形成欧姆接触，制得源金属电极；
制造漏金属电极：刻蚀或研磨减薄所述衬底，采用磁控溅射或电子束蒸发的方法在所述衬底下表面沉积金属，与所述衬底表面形成欧姆接触，制得漏金属电极；
完成终端区钝化层的延伸：采用原子层沉积或化学气相沉积的方法在终端区的钝化层的表面再淀积一层氧化物，并使再次淀积的氧化物的上表面不高于重掺杂半导体层的上表面，以使终端区内的钝化层得以延伸并包裹于终端区内的沟道层外侧。
进一步地，栅金属电极选用Ni/9u合金或Pt/9u合金；
进一步地，源金属电极选用Ti/Au合金或Ti/Al/Ni/Au合金；
进一步地，所述介电材料为白宝石、金红石、钛酸钙或钛酸镁，所述高K介电材料的介电常数大于3.7。
与现有技术相比，本发明具有如下优点：
(1)本发明通过在复合柱体中设置柱状p区5a，器件的沟道采用在复合柱体表面二次淀积形成高掺杂的沟道层6a，形如一层薄壳，从而使本发明的沟道层很薄，在器件导通状态下，导通电流从柱状p区5a外侧的薄壳沟道层经过，因此，与传统结构相比，显著减小了器件的有效沟道宽度(参见图13中的沟道层6a)。
(2)在传统结构中，器件的沟道宽度越小，对工艺的线宽要求越高。如果通过传统的刻蚀方式形成导电沟道，会面临沟槽底部形貌难以控制等问题以及无法刻蚀的风险；如果通过注入工艺在沟道中形成埋层的方式来减小器件有效宽度，则会面临激活难、晶格易损伤等问题。
本发明提供了一种柱状p区的制造方法，即采用淀积及刻蚀的方法，极大降低了工艺难度，首先通过MOCVD(气相外延生长)方式形成p型半导体层，这种方式非常适合于生长各种异质结材料，且厚度易于控制，从而可以方便地通过控制p型半导体层厚度来控制柱状p区的深度，同时外延层大面积均匀性良好；而传统离子注入工艺要达到相同的掺杂浓度，需要进行更高剂量的高能离子注入，在技术上难以实现大面积高浓度注入，且高能离子注入会带来更多的晶格损伤，离子注入深度难以控制，其成本也比MOCVD方式更高。其次，通过对p型半导体层进行刻蚀形成柱状p区，刻蚀工艺可以方便地确定柱状p区的直径大小，对线宽要求较低，可以在当前工艺水平下进行，在确定柱状p区的直径大小以后，导电沟道的宽度仅由柱状p区外侧淀积的导电材料的厚度决定，若直接通过刻蚀形成导电沟道区域，则无法实现极小的沟道区域宽度，且沟道深度难以控制。
具体步骤为：在漂移区上依次外延形成柱状p区5a和柱状n区5b，再以一定间隔平行地刻蚀所述柱状p区5a、柱状n区5b，从而形成多条平行排列、柱状延伸的柱状p区5a、柱状n区5b，通过在所述柱状p区5a和柱状n区5b表面淀积一层n型氮化镓 材料，制得沟道层6a。
(3)与传统结构相比，本发明具有更小的有效沟道宽度，从而增强了金-半接触产生的肖特基势垒带来的效果，同时，由于p型区域5a可以将沟道中电子进一步耗尽，两种效果相互叠加，进一步降低了沟道区域电子的浓度，因此可以在当前工艺条件(即不减小沟道总宽度)下，极大提高器件的阈值。
(4)本发明可以有效提到器件的电容特性，进一步改善器件的开关特性。传统结构过度依赖大面积源极场板来降低沟槽底部的电场，从而保证器件较高的阻断能力，但是却极大增加了器件的寄生电容，导致较差的开关特性；本发明巧妙地利用了柱状p区5a来降低沟槽底部的电场，在一定程度上保证了器件的阻断能力，同时起到了替代源极场板的作用，极大减少了器件的电容，优化了器件的开关特性。
(5)本发明中，由于柱状p区5a的存在，在相同耐压要求下，可以进一步提高漂移区的浓度，从而大大降低了导通电阻，同时避免了击穿电压裕度的浪费。
(6)本发明中的复合柱体结构在缓冲层上表面呈蜂窝状分布，符合了工艺要求中通孔最小尺寸要求，可以最大程度利用器件的横向面积。在缓冲层上存在多个鳍式区域单元，产生多段沟道电流，有效提高了电流能力，使得器件在导通时获得更高的开态电流，从而降低了器件的导通电阻。
附图说明
图1是传统fin器件正视截面剖视图。
图2是本发明所述高阈值的功率半导体器件的制造方法示意图一。
图3是本发明所述高阈值的功率半导体器件的制造方法示意图二。
图4是本发明所述高阈值的功率半导体器件的制造方法示意图三。
图5是本发明所述高阈值的功率半导体器件的制造方法示意图四。
图6是本发明所述高阈值的功率半导体器件的制造方法示意图五。
图7是本发明所述高阈值的功率半导体器件的制造方法示意图六。
图8是本发明所述高阈值的功率半导体器件的制造方法示意图七。
图9是本发明所述高阈值的功率半导体器件的制造方法示意图八。
图10是本发明所述高阈值的功率半导体器件的制造方法示意图九。
图11是本发明所述高阈值的功率半导体器件的制造方法示意图十。
图12是本发明所述高阈值的功率半导体器件的制造方法流程图。
图13图示了根据一种实施案例的鳍式区域为蜂窝状排列的高阈值的功率半导体器件的正剖立体图。
图14图示了根据一种实施案例的鳍式区域为插指直条状排列的高阈值的功率半导体器件的正剖立体图。
图15图示了根据一种实施案例的沟道层为石墨烯材料的高阈值的功率半导体器件的正剖立体图。
图16图示了根据一种实施案例的终端区p埋层接地的高阈值的功率半导体器件的正剖立体图。
图17是本发明与传统纵向氮化镓半导体器件的阈值电压对比图，由图示可知，本发明的阈值电压近似提升到1.5V左右。
图18是本发明与传统纵向氮化镓半导体器件的击穿电压对比图，由图示可知，本发明的击穿电压明显高于传统器件击穿电压。
图19是本发明与传统纵向氮化镓半导体器件的输入电容对比图，由图示可知，输入电容(Ciss)降低了93％左右。
具体实施方式
以下结合附图对本发明的实施案例进行说明，应当理解，此处描述的实施案例仅用于说明和解释本发明，并不用于限定本发明。
实施例1
本发明所述的一种高阈值的功率半导体器件，包括：由下至上层叠的漏金属电极1、衬底2、缓冲层3以及漂移区4，漂移区4的部分区域上突形成漂移区凸起4a，在漂移区凸起4a上依次设有柱状p区5a和柱状n区5b并由漂移区凸起4a、柱状p区5a和柱状n区5b构成复合柱体，在漂移区4的上表面、复合柱体的外侧及复合柱体的顶部设有沟道层6a，在沟道层6a的底面设有钝化层6b，部分漂移区4及其上的部分沟道层6a、钝化层6b和复合柱体划作元胞区9，另一部分漂移区4及其上的部分沟道层6a、钝化层6b和复合柱体划作终端区10，在元胞区9内的钝化层6b表面及沟道层6a的外侧设有介质层6c，在介质层6c的外侧设有栅金属电极7，在元胞区9内的沟道层6a顶面上设有重掺杂半导体层5c，在重掺杂半导体层5c上设有源金属电极8；所述终端区10内的钝化层6b延伸并包裹于终端区10内的沟道层6a外侧。在本实施例中，
所述钝化层6b的上表面不高于柱状p区5a的下表面，介质层6c的上表面不高于柱状n区5b的上表面、且不低于柱状p区5a的上表面，柱状p区5a的下表面高于栅金属电极7的下表面且柱状p区5a的上表面低于栅金属电极7的上表面。
所述沟道层6a的材料为氮化镓、铝镓氮和石墨烯材料的一种，其浓度不小于漂移区4的浓度。
所述复合柱体为条状，或者，所述复合柱体为圆柱，各复合柱体呈蜂窝状排列。
所述介质层6c可以采用Al 2O 3或其他材料。
所述钝化层6b可以采用SiO 2或其他材料，构成单层或组合的多层结构，起隔离和增加耐压的作用。
所述漏金属电极1与衬底2表面为欧姆接触，在高阈值的功率半导体器件导通时作为电流输出端口；所述源金属电极8与重掺杂半导体层5c表面为欧姆接触，在高阈值的功率半导体器件导通时作为电流的输入端口。
所述缓冲层3的浓度和厚度决定耐压特性，可通过适当降低缓冲层3的掺杂浓度或增加缓冲层3厚度来增强耐压特性。
所述栅金属电极7用于调控鳍式沟道中的电子浓度以控制氮化镓半导体器件的导通和关断。
本发明所述的一种制造所述一种高阈值的功率半导体器件的制造方法，包括以下步骤：
制造晶圆片：在衬底2上依次生长缓冲层3、漂移区4制得圆晶片；
形成柱状排列的复合柱体：在漂移区4上依次外延形成p型半导体层和n型半导体层，再对所述p型半导体层、n型半导体层和漂移区4进行刻蚀，形成平行排列的由漂移区凸起4a、柱状p区5a和柱状n区5b叠加构成的复合柱体，漂移区4的刻蚀深度等于漂移区凸起4a的厚度且所述厚度为柱状p区5a厚度的0.8～1.2倍；
制造沟道层6a：采用原子层沉积或化学气相沉积的方法在所述漂移区4的上表面、复合柱体的外侧及复合柱体的顶部淀积一层n型氮化镓材料，制得沟道层6a，这样，形成于复合柱体表面的沟道层6a就呈现一层包裹在复合柱体外的厚度很小的薄壳，可见，本发明的有效沟道宽度可以做得很小；
制造钝化层6b：采用原子层沉积或化学气相沉积的方法在沟道层6a的底部淀积一层氧化物，形成钝化层6b，且钝化层6b的上表面不高于柱状p区5a的下表面；将沟道层6a的一部分区域及其上的钝化层作为元胞区9，将沟道层6a的剩余部分区域及其上的钝化层作为终端区10；
制造介质层6c：采用原子层沉积或化学气相沉积的方法在元胞区9的钝化层6b表面和沟道层6a侧壁淀积一层介电常数大于二氧化硅的高K介电材料，制得介质层6c，且沟道层6a侧壁的介质层6c不高于柱状n区5b的上表面、不低于柱状p区5a的上表面，介质层6c底部的上表面不高于柱状p区5a的下表面；
制造栅金属电极7：采用磁控溅射方式在所述元胞区9的介质层6c的侧壁上沉积金属，制得栅金属电极7，且栅金属电极的上表面不高于柱状n区5b的上表面。
制造重掺杂半导体层5c：采用原子层沉积或化学气相沉积的方法在元胞区9的沟道层6a的顶部淀积一层n型氮化镓，并对n型氮化进行镁离子重掺杂，制得重掺杂半导体层5c，其掺杂浓度不低于漂移区4的浓度，且不高于2×10 19cm -3；
制造源金属电极8：采用磁控溅射或电子束蒸发的方法在所述元胞区9的重掺杂半导体层5c上沉积金属，并与重掺杂半导体层 5c表面形成欧姆接触，制得源金属电极8；
制造漏金属电极1：刻蚀或研磨减薄所述衬底2，采用磁控溅射或电子束蒸发的方法在所述衬底2下表面沉积金属，与所述衬底2表面形成欧姆接触，制得漏金属电极1；
完成钝化层6b的延伸：采用原子层沉积或化学气相沉积的方法在终端区10的钝化层6b的表面再淀积一层氧化物，并使再次淀积的氧化物的上表面不高于重掺杂半导体层5c的上表面，以使终端区10内的钝化层6b得以延伸并包裹于终端区10内沟道层6a外侧。
在本实施例中，
进一步地，栅金属电极7选用Ni/9u合金或Pt/9u合金；
进一步地，源金属电极8选用Ti/Au合金或Ti/Al/Ni/Au合金；
进一步地，所述介电材料为白宝石、金红石、钛酸钙或钛酸镁，所述高K介电材料的介电常数大于3.7。
下面参照附图，对本实施例作出如下声明：
如图2所示，在衬底2上依次生长缓冲层3、漂移区4制得圆晶片；
如图3所示，先利用化学气相淀积的方法在漂移区4上外延形成一层p型半导体层；接着利用化学气相淀积的方法在p型半导体层上外延形成一层n型半导体层，且厚度与p型半导体层的厚度相同。
如图4所示，刻蚀所述p型半导体层和n型半导体层，直至暴露出漂移区漂移区4，形成多条平行排列、柱状延伸的柱状p区5a、柱状n区5b；继续刻蚀，在柱状p区5a的下表面形成一系列平行排列的漂移区凸起4a，柱状p区5a、柱状n区5b与漂移区凸起4a共同构成复合柱体。
如图5所示，采用原子层沉积或化学气相沉积的方法在所述漂移区4的上表面、复合柱体的外侧及复合柱体的顶部淀积一层n型氮化镓材料，制得沟道层6a。
如图6所示，采用原子层沉积或化学气相沉积的方法在沟道层6a的底部淀积一层氧化物，形成钝化层6b，且钝化层6b的上表面不高于柱状p区5a的下表面；
如图7所示，采用原子层沉积或化学气相沉积的方法在元胞区9的钝化层6b表面和沟道层6a侧壁淀积一层介电常数大于二氧化硅(介电常数为3.7)的高K介电材料，制得介质层6c，且沟道层6a侧壁的介质层6c不高于柱状n区5b的上表面、不低于柱状p区5a的上表面，介质层6c的下表面不高于柱状p区5a的上表面；
如图8所示，采用磁控溅射方式在所述元胞区9的介质层6c的侧壁沉积金属，制得栅金属电极7，且栅金属电极的上表面不高于柱状n区5b的上表面，所述栅金属电极7可以选用Ni/9u合金或Pt/9u合金；
如图9所示，采用原子层沉积或化学气相沉积的方法在元胞区9的沟道层6a的顶面淀积一层n型氮化镓材料，并对该区域进行重掺杂，制得重掺杂半导体层5c；
如图10所示，采用磁控溅射或电子束蒸发的方法在重掺杂半导体层5c上沉积金属，与重掺杂半导体层5c表面形成欧姆接触，制得源金属电极8，所述源金属电极8可以选用Ti/Au合金或Ti/Al/Ni/Au合金；刻蚀或研磨减薄所述衬底2，采用磁控溅射或电子束蒸发的方法在所述衬底2下表面沉积金属，与所述衬底2表面形成欧姆接触，制得漏金属电极1。
如图11所示，采用原子层沉积或化学气相沉积的方法在终端区10的钝化层6b的表面再淀积一层氧化物，并使再次淀积的氧化物的上表面不高于重掺杂半导体层5c的上表面，以使终端区10内的钝化层6b得以延伸并包裹于终端区10内沟道层6a外侧。
如图12所示，所述一种高阈值的功率半导体器件的制造方法流程图包括但不限于图中所示的重要步骤。
如图13所示，为本实施例一种高阈值的功率半导体器件的正剖立体图。所述复合柱体呈蜂窝状排列。蜂窝状排列结构符合了工艺要求中通孔最小尺寸要求，可以最大程度地利用器件的横向面积。
实施例2
参照图14所示，与实施例1相比，本实施例不同之处在于，所述一种高阈值的功率半导体器件的柱状p区5a、柱状n区5b、沟道层6a、重掺杂半导体层5c及钝化层6b、介质层6c、栅金属电极7、源金属电极8为插指直条状分布，无钝化层6b1，其它结构与实施例1相同。插指直条状分布的制造工艺更为简单，且减少了金属互联线。
实施例3
参照图15所示，与实施例1相比，本实施例不同之处在于，所述一种高阈值的功率半导体器件的沟道层6a为石墨烯材料，其它结构与实施例1相同。石墨烯具有极高的强度与柔韧性，提高了器件的稳定性；其热导率比氮化镓材料更高，因此温度稳定性更高；石墨烯是室温下导电最好的材料，其电子迁移率约为硅中电子迁移率的140倍，比铜或银更低，电导率可达10 6S/m，因此在相同条件下具有更低的导通电阻。
实施例4
参照图16所示，与实施例1相比，本实施例不同之处在于，所述一种高阈值的功率半导体器件的p环结构并非处于浮空状态，而是进行了接地处理。
具体做法是：在实施例1的最后一步钝化工序之前，对元胞区9和终端区10的某些复合柱体区域进行刻蚀处理，再填充金属钨11，与源金属电极8进行短接。其余工序与实施例1完全一样。填充金属钨的原因是，钨具有较高的熔点和良好的导电性，不易与其他非金属发生化学反应。通过接地处理，在关态情况下，柱状p区5a所形成的耗尽层电位相同，此工艺可以使得部分p环结构电位不浮空，有效平缓栅极底部电场，提高了器件的耐压能力。
本发明的工作原理和过程如下：
器件在平衡态下，即当栅金属电极7施加0V电压时，栅金属电极7和导电沟道6a形成金半接触，通过肖特基势垒作用将导电沟道6a靠近栅金属电极7一侧的电子耗尽；同时，沟道区域中的柱状p区5a将周围电子辅助耗尽。两者共同作用，将导电沟道6a中的电子完全耗尽，达到沟道夹断的目的，因此源金属电极8与漏金属电极1之间无法形成电流，器件处于关断状态。当开始增大栅金属电极7的电压时，靠近介质层一侧的电子逐渐积累；与此同时，由于电势逐渐增加，柱状p区5a所形成的的耗尽层逐渐变窄，两者共同作用，形成稳定的电子导通沟道，电流从源金属电极8依次经过重掺杂半导体层5c、沟道层6a、柱状n区5b、柱状p区5a、漂移区凸起4a、漂移区4、缓冲层3、衬底2到达漏金属电极1，进而使器件导通。
对于本领域的技术人员来说，可根据以上描述的技术方案以及构思，做出其它各种相应的改变以及形变，而所有的这些改变以及形变都应该属于本发明权利要求的保护范围之内。

Claims (10)

  1. 一种高阈值的功率半导体器件，包括：由下至上层叠的漏金属电极(1)、衬底(2)、缓冲层(3)以及漂移区(4)，其特征在于，漂移区(4)的部分区域上突形成漂移区凸起(4a)，在漂移区凸起(4a)上依次设有柱状p区(5a)和柱状n区(5b)并由漂移区凸起(4a)、柱状p区(5a)和柱状n区(5b)构成复合柱体，在漂移区(4)的上表面、复合柱体的外侧及复合柱体的顶部设有沟道层(6a)，在沟道层(6a)的底面设有钝化层(6b)，部分漂移区(4)及其上的部分沟道层(6a)、钝化层(6b)和复合柱体划作元胞区(9)，另一部分漂移区(4)及其上的部分沟道层(6a)、钝化层(6b)和复合柱体划作终端区(10)，在元胞区(9)内的钝化层(6b)表面及沟道层(6a)的外侧设有介质层(6c)，在介质层(6c)的外侧设有栅金属电极(7)，在元胞区(9)内的沟道层(6a)顶面上设有重掺杂半导体层(5c)，在重掺杂半导体层(5c)上设有源金属电极(8)；所述终端区(10)内的钝化层(6b)延伸并包裹于终端区(10)内的沟道层(6a)外侧。
  2. 根据权利要求1所述一种高阈值的功率半导体器件，其特征在于，所述钝化层(6b)的上表面不高于柱状p区(5a)的下表面，介质层(6c)的上表面不高于柱状n区(5b)的上表面、且不低于柱状p区(5a)的上表面，柱状p区(5a)的下表面高于栅金属电极(7)的下表面且柱状p区(5a)的上表面低于栅金属电极(7)的上表面。
  3. 根据权利要求1所述一种高阈值的功率半导体器件，其特征在于，所述沟道层(6a)的材料为氮化镓、铝镓氮和石墨烯材料的一种，其浓度不小于漂移区(4)的浓度。
  4. 根据权利要求1所述一种高阈值的功率半导体器件，其特征在于，所述复合柱体为条状。
  5. 根据权利要求1所述一种高阈值的功率半导体器件，其特征在于，所述复合柱体为圆柱，各复合柱体呈蜂窝状排列。
  6. 一种制造权利要求1至5中任一权利要求所述一种高阈值的功率半导体器件的制造方法，其特征在于，包括以下步骤：
    制造晶圆片：在衬底(2)上依次生长缓冲层(3)、漂移区(4)制得圆晶片；
    形成柱状排列的复合柱体：在漂移区(4)上依次外延形成p型半导体层和n型半导体层，再对所述p型半导体层、n型半导体层和漂移区(4)进行刻蚀，形成平行排列的由漂移区凸起(4a)、柱状p区(5a)和柱状n区(5b)叠加构成的复合柱体，漂移区(4)的刻蚀深度等于漂移区凸起(4a)的厚度且所述厚度为柱状p区(5a)厚度的0.8～1.2倍；
    制造沟道层(6a)：采用原子层沉积或化学气相沉积的方法在所述漂移区(4)的上表面、复合柱体的外侧及复合柱体的顶部淀积一层n型氮化镓材料，制得沟道层(6a)；
    制造钝化层(6b)：采用原子层沉积或化学气相沉积的方法在沟道层(6a)的底部淀积一层氧化物，形成钝化层(6b)，且钝化层(6b)的上表面不高于柱状p区(5a)的下表面；将沟道层(6a)的一部分区域及其上的钝化层作为元胞区(9)，将沟道层(6a)的剩余部分区域及其上的钝化层作为终端区(10)；
    制造介质层(6c)：采用原子层沉积或化学气相沉积的方法在元胞区(9)的钝化层(6b)表面和沟道层(6a)侧壁淀积一层介电常数大于二氧化硅的高K介电材料，制得介质层(6c)，且沟道层(6a)侧壁的介质层(6c)不高于柱状n区(5b)的上表面、不低于柱状p区(5a)的上表面，介质层(6c)底部的上表面不高于柱状p区(5a)的下表面。
    制造栅金属电极(7)：采用磁控溅射方式在所述元胞区(9)的介质层(6c)的侧壁上沉积金属，制得栅金属电极(7)，且栅金属电极的上表面不高于柱状n区(5b)的上表面。
    制造重掺杂半导体层(5c)：采用原子层沉积或化学气相沉积的方法在元胞区(9)的沟道层(6a)的顶部淀积一层n型氮化镓材料，并对n型氮化镓材料进行镁离子重掺杂，制得重掺杂半导体层(5c)，且其掺杂浓度不低于漂移区(4)的浓度、不高于2×10 19cm -3；
    制造源金属电极(8)：采用磁控溅射或电子束蒸发的方法在所述元胞区(9)的重掺杂半导体层(5c)上沉积金属，并与重掺杂半导体层(5c)表面形成欧姆接触，制得源金属电极(8)；
    制造漏金属电极(1)：刻蚀或研磨减薄所述衬底(2)，采用磁控溅射或电子束蒸发的方法在所述衬底(2)下表面沉积金属，与所述衬底(2)表面形成欧姆接触，制得漏金属电极(1)。
    完成钝化层(6b)的延伸：采用原子层沉积或化学气相沉积的方法在终端区(10)的钝化层(6b)的表面再淀积一层氧化物，并使再次淀积的氧化物的上表面不高于重掺杂半导体层(5c)的上表面，以使终端区(10)内的钝化层(6b)得以延伸并包裹于终端区(10)内的沟道层(6a)外侧。
  7. 根据权利要求6所述的制造方法，其特征在于，栅金属电极(7)选用Ni/9u合金或Pt/9u合金；
  8. 根据权利要求6所述的制造方法，其特征在于，源金属电极(8)选用Ti/Au合金或Ti/Al/Ni/Au合金。
  9. 根据权利要求6所述的制造方法，其特征在于，所述介电材料为白宝石、金红石、钛酸钙或钛酸镁。
  10. 根据权利要求6所述的制造方法，其特征在于，所述高K介电材料的介电常数大于3.7。
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