WO2022057342A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022057342A1
WO2022057342A1 PCT/CN2021/100314 CN2021100314W WO2022057342A1 WO 2022057342 A1 WO2022057342 A1 WO 2022057342A1 CN 2021100314 W CN2021100314 W CN 2021100314W WO 2022057342 A1 WO2022057342 A1 WO 2022057342A1
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Prior art keywords
isolation
layer
sealing
bit line
top surface
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English (en)
French (fr)
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程明
金星
李冉
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/446,957 priority Critical patent/US12512374B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure and a fabrication method thereof.
  • DRAM Dynamic Random Access Memory
  • the spacing between adjacent conductors becomes smaller, and the thickness of the dielectric layer separating the adjacent conductors becomes thinner.
  • the dielectric constant of the dielectric layer is constant, the thinner the thickness of the dielectric layer is, the more serious the problem of parasitic capacitance between adjacent conductors is.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are beneficial to improve the structural stability of the semiconductor structure.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate and a bit line structure on the substrate, the bit line structure including a top dielectric layer, and the bit line structure is opposite to two A capacitor contact hole is formed on the side; a first isolation spacer covering the sidewall of the top dielectric layer is formed, and a second isolation spacer covering the sidewall of the first isolation spacer is formed, and the first isolation spacer is located at the Between the bit line structure and the capacitor contact hole, the top surface of the second isolation spacer is higher than the top surface of the first isolation spacer; at least part of the top dielectric layer is removed to form a first gap; performing a deposition process to form a first sealing film covering the top surface of the first isolation sidewall and blocking the top opening of the void, the top surface of the first sealing film being higher than the top surface of the second isolation sidewall; In the first planarization process, the first sealing film that is higher than the top surface of the second isolation sidewall is removed,
  • the method further includes: filling a sacrificial layer between adjacent bit line structures; forming a mask layer, and in the same etching process, passing through the mask The film layer removes part of the sacrificial layer, part of the first sealing layer, part of the first isolation spacer and part of the second isolation spacer, so as to etch part of the first void into a second void.
  • the first sealing The layer and the second seal layer constitute the seal layer.
  • the process steps of forming the isolation layer and the second sealing layer include: in the same deposition process, forming an isolation film between adjacent bit line structures and blocking the second sealing layer. A second sealing film with an opening at the top of the void; performing a second planarization process to form the isolation layer and the second sealing layer, the top surfaces of the isolation layer and the second sealing layer and the first sealing layer The top surface is flush.
  • the remaining sacrificial layer is removed to form the capacitor contact hole; the capacitor contact hole is filled to form a capacitor contact window.
  • the remaining sacrificial layer and the remaining second isolation spacer are removed to form the capacitor contact hole.
  • embodiments of the present application further provide a semiconductor structure, including: a substrate, a bit line structure on the substrate, and capacitor contact holes on opposite sides of the bit line structure; a first isolation spacer, the The first isolation spacer is located between the bit line structure and the capacitor contact hole, and there are gaps between the first isolation spacers located on opposite sides of the bit line structure; a sealing layer, the sealing layer covers The top surface of the first isolation sidewall blocks the top opening of the void, and in a direction perpendicular to the substrate, the thickness of the sealing layer on the first isolation sidewall is greater than or equal to 30 nm.
  • the voids include a first void located between the opposite capacitor contact holes, and a second void located between adjacent first voids in the extending direction of the bit line structure .
  • the semiconductor structure further includes: an isolation layer, the isolation layer is located on opposite sides of the bit line structure, the isolation layer is used to isolate the adjacent capacitor contact holes, the second gap between the opposing isolation layers.
  • the sealing layer includes a first sealing layer for sealing the first void and a second sealing layer for sealing the second void.
  • the top surface of the first void is higher than the top surface of the second void in a direction perpendicular to the substrate surface.
  • the thickness of the void is less than or equal to 80 nm.
  • the thickness of the first sealing layer can be defined by the multi-layer isolation sidewalls with height differences, that is, the isolation sidewalls with the lower top surface provide support, and the top surface is supported by the isolation sidewalls.
  • the higher isolation sidewall provides positional limitation to form a thicker first sealing layer, which ensures better support for the first sealing layer and better structural stability of the semiconductor structure.
  • the thickness of the second sealing layer is larger than that of the first sealing layer, and the second sealing layer can bear more compressive stress, thereby further reducing the bearing pressure of the first sealing layer, avoiding the collapse of the first sealing layer, and avoiding the corresponding occurrence of
  • the damage to the semiconductor structure and the increase of parasitic capacitance ensure that the semiconductor structure has good structural stability and a small parasitic capacitance between adjacent capacitive contact windows.
  • 1 to 17 are schematic structural diagrams corresponding to each step of the method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • 1 to 17 are schematic structural diagrams corresponding to each step of the method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • a substrate 10 is provided, a bottom dielectric film 101, a first conductive film 111a, a second conductive film 112a, a top dielectric film 113a, a first mask layer 121, a second mask layer 122 and The third mask layer 123 .
  • the underlying dielectric film 101 is used to isolate the first conductive film 111a from the active region (not shown) in the substrate 10, and the material of the underlying dielectric film 101 includes silicon nitride; part of the first conductive film 111a is in contact with the active region, so as to As a bit line contact, the material of the first conductive film 111a includes polysilicon; the material of the second conductive film 112a includes tungsten; the top dielectric film 113a functions as a dielectric layer and protects the second conductive film 112a, and the material of the top dielectric film 113a Including silicon nitride.
  • the mask layer includes a first mask layer 121 and a second mask layer 122.
  • the hardness of the first mask layer 121 is greater than the hardness of the second mask layer 122, so as to improve the etching in the subsequent etching process Precision; in other embodiments, an anti-reflection coating is also provided between the first mask layer and the second mask layer to reduce problems such as reflection and standing waves.
  • the material of the first mask layer 121 may include silicon nitride
  • the material of the second mask layer 122 may include polysilicon
  • the anti-reflection coating is usually a carbon coating.
  • the third mask layer 123 is used to define the position of the subsequently formed bit line structure.
  • a fourth mask layer 124 covering the top surface and sidewalls of the third mask layer 123 and the top surface of the second mask layer 122 is formed, and the fourth mask layer 124 is used to define the bit line structure formed subsequently The width in the direction parallel to the substrate 10 .
  • the second mask layer 122 is etched using a Self-aligned Double Patterning (SADP) technique, and the width of the remaining second mask layer 122 is the same as that of the third mask layer 123 (refer to FIG. 2)
  • the widths of the fourth mask layers 124 (refer to FIG. 2 ) of the sidewalls are equal.
  • the remaining second mask layer 122 is used as a mask for etching to form the bit line structure, and the width of the remaining second mask layer 122 is equal to the width of the subsequently formed bit line structure.
  • the top dielectric film 113a, the second conductive film 112a, the first conductive film 111a and the bottom dielectric film 101 are etched through the remaining second mask layer 122 to form the bit line structure 11.
  • the bit line structure 11 includes a bottom dielectric layer (not shown), a conductive layer and a top dielectric layer 113, and the conductive layer includes a first conductive layer 111 and a second conductive layer 112; in other embodiments, the conductive layer A single layer or more than two conductive layers may be included.
  • a deposition process is used to form a first isolation film 131a, a second isolation film 132a and a third isolation film 133a which are stacked in sequence.
  • the first isolation film 131a covers the top surface and sidewalls of the bit line structure 11 and the surface of the substrate 10; the second isolation film 132a covers the surface of the first isolation film 131a; the third isolation film 133a covers the surface of the second isolation film 132a.
  • the hardness of the first isolation film 131a is greater than that of the second isolation film 132a, so as to better support the bit line structure 11 and ensure better structural stability of the semiconductor structure.
  • the hardness of the first isolation film 131a The material can be the same as the material of the top dielectric layer 113, so that the first isolation film 131a and the top dielectric layer 113 can be removed simultaneously by the same removal process; the material of the third isolation film 133a is the same as the material of the sacrificial layer used later, so , the sacrificial layer and the third isolation film 133a can be removed at the same time by the same removal process, which is beneficial to reduce process steps and shorten the process cycle;
  • the isolation films 133a have a large etching selectivity ratio among them.
  • the material of the first isolation film 131a may be silicon nitride
  • the material of the second isolation film 132a may be silicon oxynitride
  • the material of the third isolation film 133a may be silicon oxide.
  • a maskless dry etching process is used to remove part of the third isolation film 133 a (refer to FIG. 5 ), and the remaining third isolation film 133 a serves as the second isolation spacer 133 .
  • the second isolation film 132 a (refer to FIG. 6 ) is etched by using the third isolation spacer 133 as a mask, and the remaining second isolation film 132 a is used as the first isolation spacer 132 .
  • the top surface of the first isolation film 131a is exposed.
  • the top surface of the first isolation sidewall 132 is lower than the top surface of the second isolation sidewall 133
  • the first height difference d1 between the top surface of the first isolation sidewall 132 and the top surface of the second isolation sidewall 133 is determined by
  • the thickness of the first sealing layer should not only ensure that the first sealing layer can be effectively supported without collapse, but also prevent the first sealing layer from being too thick and increasing the overall size of the semiconductor structure. .
  • the range of the first height difference d1 is 5 nm ⁇ 15 nm, for example, 8 nm, 10 nm or 13 nm.
  • the top surface of the first isolation sidewall 132 may be lower than, flush with or higher than the top surface of the first isolation film 131a.
  • a first sacrificial layer 141 filled between adjacent bit line structures 11 is formed.
  • the formation of the first sacrificial layer 141 is used to avoid etching the first isolation film 131 a covering the surface of the substrate 10 when the first isolation film 131 a and the top dielectric layer 113 are removed by subsequent etching to form the first void, so as to protect the substrate 10 .
  • the material of the first sacrificial layer 141 and the material of the second isolation spacer 133 are different. Specifically, under the same grinding process, the first sacrificial layer 141 and the second isolation spacer 133 have different removals. rate.
  • the progress of the polishing process can be controlled by obtaining the removal rate of the polishing process, so that the subsequent planarization process can be accurately stopped at the plane where the top surface of the second isolation sidewall 133 is located, thereby improving the automation degree of the planarization process without the need for staff Detect the progress of the process; further, the planarization process is accurately stopped at the plane where the top surface of the second isolation layer 133 is located, which is beneficial to ensure that the thickness of the first sealing layer can be defined by the first height difference d1, thereby improving the thickness of the first sealing layer. accuracy.
  • the removal rate of the first sacrificial layer 141 is greater than the removal rate of the second isolation spacer 133.
  • the material of the first sacrificial layer 141 includes photoresist; in other embodiments , the material of the first sacrificial layer is the same as that of the second isolation spacer or the removal rate of the first sacrificial layer is lower than that of the second isolation spacer, specifically, the material of the first sacrificial layer includes silicon dioxide.
  • first isolation film 131a and the top dielectric layer 113 between the opposite second isolation spacers 133 are removed to form a first void 134.
  • the etching selectivity ratio is not infinite, in the process of etching the first isolation film 131 a and the top dielectric layer 113 , the first sacrificial layer 141 , the second isolation spacer 133 and the first isolation spacer 132 will also be correspondingly removed.
  • a second height difference d2 in the direction perpendicular to the substrate 10 will be formed; at the same time, since the etchant itself is directed against The first isolation film 131a and the top dielectric layer 113, so the first sacrificial layer 141 and the second isolation spacer 133 are etched to a smaller thickness, and correspondingly, the second height difference d2 is also smaller. Generally speaking, the second height difference d2 is negligible compared to the first height difference d1.
  • the etched thicknesses of the first isolation spacer 132 and the second isolation spacer 133 may be different, which may cause the value of the first height difference d1 to change, that is, to form the first height difference fluctuation ⁇ d1; and since the etchant itself is directed to the first isolation film 131a and the top dielectric layer 113, the first height difference fluctuation ⁇ d1 formed by etching the first isolation spacer 132 and the second isolation spacer 133 is relative to the first height difference fluctuation ⁇ d1.
  • a height difference d1 is negligible.
  • a first sealing film 151a is formed by a deposition process.
  • the first sealing film 151a covers the side wall of the first isolation sidewall 132 and the top surface of the first isolation sidewall 132 to block the top opening of the first space 134; in other embodiments, the first sealing film also covers the top surface of the top dielectric layer.
  • the formation of the first sealing film 151a will squeeze the space of the first void 134.
  • the first void 134 refers to the remaining void space after being squeezed.
  • the sealing layer formed is usually thinner. Specifically, the first sealing film 151a located between the opposite first isolation sidewalls 132 and located on the first gap 134 is thinner.
  • a planarization process is used to remove part of the first sealing film 151 a (refer to FIG. 10 ) and part of the first sacrificial layer 141 , the remaining first sealing film 151 a is used as the first sealing layer 151 , and the top of the first sealing layer 151 is removed.
  • the surface is flush with the top surface of the second isolation sidewall 133 .
  • the first sealing layer 151 with a preset thickness can be formed without using a mask, thereby It is ensured that the first sealing layer 151 has good supporting performance and the semiconductor structure has good structural stability.
  • the first sacrificial layer 141 (refer to FIG. 11 ) is removed, a second sacrificial layer 142 is formed to replace the first sacrificial layer 141 , and a fifth mask layer 152 is formed on the top surface of the second sacrificial layer 142 .
  • the top surface of the second sacrificial layer 142 is higher than the top surface of the first sealing layer 151 of the isolation spacer; in other embodiments, the top surface of the second sacrificial layer is flush with or lower than the top surface of the isolation spacer.
  • the material of the second sacrificial layer 142 is the same as that of the second isolation spacer 133 , so that the same etchant can be used to quickly remove the second sacrificial layer 142 and the second isolation spacer 133 subsequently.
  • a dry etching process is performed through the fifth mask layer 152 .
  • the substrate 10 can be divided into a first region A and a second region B arranged at intervals along the extending direction parallel to the bit line structures 11 , and the first region A between adjacent bit line structures 11 is used for For forming the capacitor contact holes and filling the capacitor contact windows, the second region B between adjacent bit line structures 11 is used to form an isolation layer, and the isolation layer is used to divide the capacitor contact holes and isolate the adjacent capacitor contact windows.
  • the fifth mask layer 152 (refer to FIG. 13 ) covers the top surface of the second sacrificial layer 142 in the first region A, and exposes the top surface of the second sacrificial layer 142 in the second region B.
  • the dry etching process is performed through the fifth mask layer 152 , including: removing the second sacrificial layer 142 in the second region B and removing the second isolation spacer 133 in the second region B.
  • the etchant of the dry etching process is aimed at the material of the second sacrificial layer 142.
  • the etchant since the etching rate of the second sacrificial layer 142 is relatively fast, when When the etchant etches the first sealing layer 151, the first isolation spacer 132 is gradually exposed; at the same time, because the angle of the dry etching process is not always perpendicular to the surface of the substrate 10 (either the etching The reason for the setting of the etching process itself, may also be the reason for the stability of the process), the etchant will etch the exposed first isolation sidewall 132 and the further exposed sidewall of the first sealing layer 151, resulting in In the dry etching process, not only the second sacrificial layer 142 and the second isolation spacer 133 will be removed, but also part of the first isolation spacer 132 and part of the first sealing layer 151 will be removed. At this time, the second region The first void 134
  • the thickness of the removed first isolation spacer 132 is related to the etching selectivity ratio between the second isolation spacer 133 and the first isolation spacer 132, and the removed first seal
  • the thickness of the layer 151 is related to the etching selectivity ratio between the second isolation spacer 133 and the first sealing layer 151 .
  • the thinner the removed first isolation spacer 132 is, and the remaining first isolation sidewall is thinner.
  • the thicker the wall 132 is; correspondingly, the greater the etching selectivity ratio between the second isolation sidewall 133 and the first sealing layer 151 is, the thinner the first sealing layer 151 is removed, and the thicker the remaining first sealing layer 151 is.
  • a deposition process and a planarization process are performed.
  • the fifth mask layer 152 is removed before the deposition process, so as to avoid the need for the polishing device to be in contact with at least three materials (the material of the fifth mask layer 152, the second The material of the sacrificial layer 142 and the material deposited by the deposition process), so as to avoid the impact of the concave-convex structure formed by the large difference in the removal rate of different materials on the polishing device, so as to ensure that the polishing device has a longer service life, or, there is no need to avoid The removal rate difference is too large to change the slurry or mask part in the middle, thereby improving the process efficiency.
  • the fifth mask layer is retained during the deposition process, and a planarization process is subsequently used to simultaneously remove the fifth mask layer and other film layers. In this way, it is beneficial to reduce the process steps and shorten the process cycle.
  • the deposition process is used to form the isolation layer 16, and the isolation layer 16 includes a second sealing layer (not shown) for sealing the second voids 135 and an isolation layer (not shown) for isolating adjacent capacitor contact windows. Not marked), that is, in the same deposition process, the first sealing layer and the isolation layer are formed simultaneously.
  • the isolation film and the second sealing film whose top surface is higher than the top surface of the first sealing layer 151 are firstly formed, and then a planarization process is performed on the isolation film and the second sealing film, so that the top surface is flush with the first sealing layer 151 The isolation layer and the second sealing layer on the top surface.
  • the second sacrificial layer 142 located on the first sealing layer 151 in the first region A is also removed to expose the first sealing layer 151 .
  • the second sacrificial layer 142 and the second isolation spacer 133 (refer to FIG. 14 ) in the remaining first region A are etched to form initial capacitor contact holes 161 .
  • the first isolation film 131a between the initial capacitor contact hole 161 and the substrate 10 also needs to be removed, so as to Capacitive contact holes exposing the surface of the substrate 10 are formed.
  • the first isolation film 131a between the initial capacitor contact hole 161 and the substrate 10 is further removed to form a capacitor contact hole.
  • a second void 135 is formed.
  • the capacitive contact window 17 includes a first capacitive contact window 171 located at the top and a second capacitive contact window 172 located at the bottom.
  • the contact resistance between the second capacitive contact window 172 and the substrate 10 is smaller than that between the first capacitive contact window 171 and the substrate 10 .
  • Contact resistance of substrate 10 In this way, it is beneficial to improve the signal transmission performance.
  • the material of the first capacitive contact window 171 includes tungsten, and the material of the second capacitive contact window 172 includes polysilicon.
  • the thickness of the first sealing layer can be defined by the multi-layer isolation sidewalls with height differences, that is, the isolation sidewalls with the lower top surface provide support, and the top surface is supported by the isolation sidewalls.
  • the higher isolation sidewall provides positional limitation to form a thicker first sealing layer, which ensures better support for the first sealing layer and better structural stability of the semiconductor structure.
  • the embodiments of the present application further provide a semiconductor structure, which can be fabricated by the above-mentioned fabrication method of the semiconductor structure.
  • the semiconductor structure includes: a substrate 10 , a bit line structure 11 on the substrate 10 , and capacitor contact holes (not shown) on opposite sides of the bit line structure 11 ; a first isolation spacer 132 , a first isolation spacer 132 is located between the bit line structure 11 and the capacitor contact hole, and there is a gap between the first isolation spacers 132 located on opposite sides of the bit line structure 11; a sealing layer, the sealing layer covers the top surface of the first isolation spacer 132 and blocks The top of the void is opened, and in the direction perpendicular to the substrate 10 , the thickness of the sealing layer on the first isolation spacer 132 is greater than or equal to 30 nm.
  • the gaps include a first gap (not shown) located between opposite capacitor contact holes, and a second gap 135 located between adjacent first gaps in the extending direction of the bit line structure 11 .
  • the top surface of the first void is higher than the top surface of the second void 135 .
  • the semiconductor structure further includes: isolation layers, the isolation layers are located on opposite sides of the bit line structure 11, the isolation layers are used to isolate adjacent capacitor contact holes, and the second gap 135 is located between the opposite isolation layers.
  • the sealing layer includes a first sealing layer 151 for sealing the first gap and a second sealing layer for sealing the second gap 135 .
  • the thickness of the first sealing layer 151 is greater than or equal to 30 nm, for example, 32 nm, 34 nm or 36 nm.
  • the thickness of the void is less than or equal to 80 nm, for example, 72 nm, 75 nm or 78 nm. In this way, it is beneficial to avoid the collapse of the structure caused by the inability to provide support for the gap, and to ensure that the semiconductor structure has better structural stability.
  • the thickness of the sealing layer is greater than the preset value, which is beneficial to ensure that the sealing layer has good supporting performance, and avoids collapse of the sealing layer due to not meeting the pressure bearing requirements, thereby ensuring good structural stability of the semiconductor structure.
  • the bit line structure includes a top dielectric layer, and opposite sides of the bit line structure have capacitor contact holes; a first isolation spacer covering the sidewalls of the top dielectric layer is formed.
  • the first isolation spacer is located between the bit line structure and the capacitor contact hole, and the top surface of the second isolation spacer is higher than the first isolation spacer top surface; at least part of the top dielectric layer is removed to form a first void; a deposition process is performed to form a first sealing film covering the top surface of the first isolation sidewall and blocking the top opening of the gap, and the top surface of the first sealing film is higher than the second sealing film isolating the top surface of the sidewall; performing a first planarization process to remove the first sealing film higher than the top surface of the second isolating sidewall, and the remaining first sealing film is used as the first sealing layer. In this way, it is beneficial to improve the structural stability of the semiconductor structure.

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Abstract

本申请实施例提供一种半导体结构及其制作方法，半导体结构的制作方法包括：提供基底和位于基底上的位线结构，位线结构包括顶层介质层，位线结构相对两侧具有电容接触孔；形成覆盖顶层介质层侧壁的第一隔离侧墙，以及形成覆盖第一隔离侧墙侧壁的第二隔离侧墙，第一隔离侧墙位于位线结构和电容接触孔之间，第二隔离侧墙的顶面高于第一隔离侧墙的顶面；去除至少部分顶层介质层，形成第一空隙；进行沉积工艺，形成覆盖第一隔离侧墙顶面且封堵空隙顶部开口的第一封口膜，第一封口膜顶面高于第二隔离侧墙顶面；进行第一平坦化工艺，去除高于第二隔离侧墙顶面的第一封口膜，剩余第一封口膜作为第一封口层。本申请有利于提高半导体结构的结构稳定性。

Description

半导体结构及其制作方法
相关申请的交叉引用
本申请要求在2020年09月18日提交中国专利局、申请号为202010988656.4、申请名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
随着半导体集成电路特征尺寸的不断减小，对动态随机存取存储器(Dynamic Random Access Memory，DRAM)制程的制作工艺提出了更高的要求。
具体地，随着特征尺寸的不断缩小，相邻导体之间的间距越来越小，隔离相邻导体的介电层的厚度越来越薄。在介电层的介电常数不变的情况下，介电层的厚度越薄，相邻导体之间的寄生电容问题越严重。
发明内容
本申请实施例提供一种半导体结构及其制作方法，有利于提高半导体结构的结构稳定性。
为解决上述问题，本申请实施例提供一种半导体结构的制作方法，包括：提供基底和位于所述基底上的位线结构，所述位线结构包括顶层介质层，所述位线结构相对两侧具有电容接触孔；形成覆盖所述顶层介质层侧壁的第一隔离侧墙，以及形成覆盖所述第一隔离侧墙侧壁的第二隔离侧墙，所述第一隔离侧墙位于所述位线结构和所述电容接触孔之间，所述第二隔离侧墙的顶面高于所述第一隔离侧墙的顶面；去除至少部分所述顶层介质层，形成第一空隙；进行 沉积工艺，形成覆盖所述第一隔离侧墙顶面且封堵所述空隙顶部开口的第一封口膜，所述第一封口膜顶面高于所述第二隔离侧墙顶面；进行第一平坦化工艺，去除高于所述第二隔离侧墙顶面的所述第一封口膜，剩余所述第一封口膜作为第一封口层。
在一些实施例中，在形成所述第一封口层之后，还包括：在相邻所述位线结构之间填充牺牲层；形成掩膜层，且在同一刻蚀工艺中，通过所述掩膜层去除部分所述牺牲层、部分所述第一封口层、部分所述第一隔离侧墙以及部分所述第二隔离侧墙，以将部分所述第一空隙刻蚀为第二空隙。
在一些实施例中，在形成所述第二空隙之后，形成位于相邻所述位线结构之间的隔离层以及封堵所述第二空隙顶部开口的第二封口层，所述第一封口层和所述第二封口层构成所述封口层。
在一些实施例中，形成所述隔离层以及所述第二封口层的工艺步骤包括：在同一沉积工艺中，形成位于相邻所述位线结构之间的隔离膜以及封堵所述第二空隙顶部开口的第二封口膜；进行第二平坦化工艺，形成所述隔离层和所述第二封口层，所述隔离层和所述第二封口层的顶面与所述第一封口层顶面平齐。
在一些实施例中，在形成所述第二封口层之后，去除剩余所述牺牲层，形成所述电容接触孔；填充所述电容接触孔，以形成电容接触窗。
在一些实施例中，在同一刻蚀工艺中，去除剩余所述牺牲层和剩余所述第二隔离侧墙，形成所述电容接触孔。
相应地，本申请实施例还提供一种半导体结构，包括：基底、位于所述基底上的位线结构以及位于所述位线结构相对两侧的电容接触孔；第一隔离侧墙，所述第一隔离侧墙位于所述位线结构与所述电容接触孔之间，位于所述位线结构相对两侧的所述第一隔离侧墙之间具有空隙；封口层，所述封口层覆盖所述第一隔离侧墙顶面且封堵所述空隙顶部开口，在垂直于所述基底的方向上，位于所述第一隔离侧墙上的所述封口层的厚度大于等于30nm。
在一些实施例中，所述空隙包括位于相对的所述电容接触孔之间的第一空隙，以及在所述位线结构延伸方向上，位于相邻所述第一空隙之间的第二空隙。
在一些实施例中，所述半导体结构还包括：隔离层，所述隔离层位于所述位线结构相对两侧，所述隔离层用于隔离相邻所述电容接触孔，所述第二空隙位于相对的所述隔离层之间。
在一些实施例中，所述封口层包括用于封堵所述第一空隙的第一封口层和用于封堵所述第二空隙的第二封口层。
在一些实施例中，在垂直于所述基底表面的方向上，所述第一空隙的顶面高于所述第二空隙的顶面。
在一些实施例中，在垂直于所述基底表面的方向上，所述空隙的厚度小于等于80nm。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
上述技术方案中，可在不使用额外掩膜的情况下，由具有高度差的多层隔离侧墙定义第一封口层的厚度，即由顶面较低的隔离侧墙提供支撑，由顶面较高的隔离侧墙提供位置限定，以形成厚度较厚的第一封口层，保证第一封口层具有较好的支撑性，以及保证半导体结构具有较好的结构稳定性。
另外，第二封口层的厚度大于第一封口层，第二封口层可承担更多的压应力，从而进一步减轻第一封口层的承压，避免第一封口层的坍塌，以及避免相应发生的半导体结构损伤以及寄生电容增大，保证半导体结构具有较好的结构稳定性以及相邻的电容接触窗之间具有较小的寄生电容。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至图17为本申请实施例提供的半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图17为本申请实施例提供的半导体结构的制作方法各步骤对应的结构示意图。
参考图1，提供基底10、在基底10上依次堆叠底层介质膜101、第一导电膜111a、第二导电膜112a、顶层介质膜113a、第一掩膜层121、第二掩膜层122以及第三掩膜层123。
底层介质膜101用于隔离第一导电膜111a和基底10内的有源区(未图示)，底层介质膜101的材料包括氮化硅；部分第一导电膜111a与有源区接触，以作为位线接触，第一导电膜111a的材料包括多晶硅；第二导电膜112a的材料包括钨；顶层介质膜113a起到介电层和保护第二导电膜112a的作用，顶层介质膜113a的材料包括氮化硅。
本实施例中，掩膜层包括第一掩膜层121以及第二掩膜层122，第一掩膜层121的硬度大于第二掩膜层122的硬度，以提高后续刻蚀工艺的刻蚀精度；在其他实施例中，第一掩膜层与第二掩膜层之间还具有抗反射涂层，以减少反射和驻波等问题。
其中，第一掩膜层121的材料可包括氮化硅，第二掩膜层122的材料可包括多晶硅，抗反射涂层通常为碳涂层。
本实施例中，第三掩膜层123用于限定后续形成的位线结构的位置。
参考图2，形成覆盖第三掩膜层123顶面和侧壁以及覆盖第二掩膜层122顶面的第四掩膜层124，第四掩膜层124用于限定后续形成的位线结构在平行于基底10方向上的宽度。
参考图3，采用自对准双重成像技术(Self-aligned Double Patterning，SADP)刻蚀第二掩膜层122，剩余的第二掩膜层122的宽度与覆盖第三掩膜层123(参考图2)侧壁的第四掩膜层124(参考图2)的宽度相等。剩余的第二掩膜层122作为刻蚀形成位线结构的掩膜版，剩余的第二掩膜层122的宽度与后续形成的位线结构的宽度相等。
参考图4，通过剩余的第二掩膜层122对顶层介质膜113a、第二导电膜112a、第一导电膜111a以及底层介质膜101(参考图3)进行刻蚀，形成位线结构11。
本实施例中，位线结构11包括底层介质层(未图示)、导电层和顶层介质层113，导电层包括第一导电层111和第二导电层112；在其他实施例中，导电层可以包括单层或两层以上的导电层。
参考图5，采用沉积工艺，形成依次堆叠的第一隔离膜131a、第二隔离膜132a以及第三隔离膜133a。
第一隔离膜131a覆盖位线结构11顶面和侧壁，以及覆盖基底10表面；第二隔离膜132a覆盖第一隔离膜131a表面；第三隔离膜133a覆盖第二隔离膜132a表面。
本实施例中，第一隔离膜131a的硬度大于第二隔离膜132a的硬度，以较好地支撑位线结构11，保证半导体结构具有较好的结构稳定性，同时，第一隔离膜131a的材料可与顶层介质层113的材料相同，如此，后续可采用同一去除工艺同时去除第一隔离膜131a和顶层介质层113；第三隔离膜133a的材料与后续使用的牺牲层的材料相同，如此，可采用同一去除工艺同时去除牺牲层和第三隔离膜133a，有利于减少工艺步骤和缩短工艺周期；此外，在同一刻蚀工艺下，第二隔离膜132a与第一隔离膜131a和第三隔离膜133a之间具有较大的刻蚀选择比。
具体地，第一隔离膜131a的材料可以是氮化硅，第二隔离膜132a的材料可以是氮氧化硅，第三隔离膜133a的材料可以是氧化硅。
参考图6，采用无掩膜干法刻蚀工艺去除部分第三隔离膜133a(参考图5)，剩余的第三隔离膜133a作为第二隔离侧墙133。
参考图7，以第三隔离侧墙133为掩膜对第二隔离膜132a(参考图6)进行刻蚀，剩余的第二隔离膜132a作为第一隔离侧墙132，第一隔离侧墙132暴露出第一隔离膜131a顶面。
本实施例中，第一隔离侧墙132顶面低于第二隔离侧墙133顶面，第一隔离侧墙132顶面和第二隔离侧墙133顶面之间的第一高度差d1用于定义后续形成的第一封口层的厚度，第一封口层的厚度既需要保证第一封口层能够有效支撑而不会坍塌，又要避免第一封口层过厚而增大半导体结构的整体尺寸。
具体地，第一高度差d1的范围为5nm～15nm，例如8nm、10nm或13nm。
需要说明的是，由于第一高度差d1可以根据需要自定义，因此，第一隔离侧墙132的顶面可能低于、平齐于或高于第一隔离膜131a顶面。
参考图8，形成填充于相邻位线结构11之间的第一牺牲层141。
第一牺牲层141的形成用于避免后续刻蚀去除第一隔离膜131a和顶层介质层113以形成第一空隙时对覆盖基底10表面的第一隔离膜131a进行刻蚀，从而保护基底10。
本实施例中，第一牺牲层141的材料与第二隔离侧墙133的材料不同，具体地，在同一研磨工艺下，第一牺牲层141与第二隔离侧墙133具有差异较大的去除速率。如此，可通过获取研磨工艺的去除速率控制研磨工艺的进程，使得后续进行的平坦化工艺可准确停止于第二隔离侧墙133顶面所在平面，从而提高平坦化工艺的自动化程度，无需工作人员检测工艺进度；进一步地，平坦化工艺准确停止于第二隔离层133顶面所在平面，有利于保证第一封口层的厚度能由第一高度差d1定义，从而提高第一封口层的厚度的准确性。
本实施例中，在同一研磨工艺下，第一牺牲层141的去除速率大于第二隔离侧墙133的去除速率，具体地，第一牺牲层141的材料包括光刻胶；在其他实施例中，第一牺牲层的材料与第二隔离侧墙的材料相同或者第一牺牲层的去除速率小于第二隔离侧墙的去除速率，具体地，第一牺牲层的材料包括二氧化硅。
参考图9，去除相对的第二隔离侧墙133之间的第一隔离膜131a和顶层介 质层113，形成第一空隙134。
由于刻蚀选择比不是无限大，因此在刻蚀第一隔离膜131a和顶层介质层113的过程中，第一牺牲层141、第二隔离侧墙133以及第一隔离侧墙132也会被相应刻蚀，当第一牺牲层141与第二隔离侧墙133被刻蚀的厚度不同时，就会形成在垂直于基底10方向上的第二高度差d2；同时，由于刻蚀剂本身是针对第一隔离膜131a以及顶层介质层113，因此第一牺牲层141和第二隔离侧墙133被刻蚀的厚度较小，相应地，形成的第二高度差d2也较小。通常来说，第二高度差d2相较于第一高度差d1可忽略不计。
相应地，由于刻蚀选择比的不同，第一隔离侧墙132和第二隔离侧墙133被刻蚀的厚度可能不同，进而可能导致第一高度差d1的数值发生变化，即形成第一高度差波动Δd1；而由于刻蚀剂本身是针对第一隔离膜131a以及顶层介质层113，因此刻蚀第一隔离侧墙132和第二隔离侧墙133形成的第一高度差波动Δd1相对于第一高度差d1可忽略不计。
参考图10，采用沉积工艺，形成第一封口膜151a。
本实施例中，第一封口膜151a覆盖第一隔离侧墙132侧壁以及第一隔离侧墙132顶面，以封堵第一空隙134的顶部开口；在其他实施例中，第一封口膜还覆盖顶层介质层顶面。
需要说明的是，第一封口膜151a的形成会挤压第一空隙134的空间，本申请实施例中，第一空隙134指的是被挤压后的剩余的空隙空间。
还需要说明的是，在没有额外支撑的情况下，形成的封口层通常较薄。具体地，位于相对的第一隔离侧墙132之间的且位于第一空隙134上的第一封口膜151a较薄。
参考图11，采用平坦化工艺，去除部分第一封口膜151a(参考图10)以及部分第一牺牲层141，剩余的第一封口膜151a作为第一封口层151，第一封口层151的顶面与第二隔离侧墙133的顶面平齐。
本实施例中，依靠第二隔离侧墙133的位置限定，以及第一隔离侧墙132的支撑，可在不采用掩膜版的情况下，形成具有预设厚度的第一封口层151， 从而保证第一封口层151具有良好的支撑性能，以及保证半导体结构具有良好的结构稳定性。
参考图12和图13，去除第一牺牲层141(参考图11)，形成替换第一牺牲层141的第二牺牲层142，并在第二牺牲层142顶面形成第五掩膜层152。
本实施例中，第二牺牲层142顶面高于隔离侧墙第一封口层151顶面；在其他实施例中，第二牺牲层顶面平齐于或低于隔离侧墙顶面。
本实施例中，第二牺牲层142的材料与第二隔离侧墙133的材料相同，如此，后续可采用同一刻蚀剂快速去除第二牺牲层142和第二隔离侧墙133。
参考图14，通过第五掩膜层152进行干法刻蚀工艺。
本实施例中，在平行于位线结构11的延伸方向上，可将基底10划分为间隔排列的第一区域A和第二区域B，相邻位线结构11之间的第一区域A用于形成电容接触孔和填充电容接触窗，相邻位线结构11之间的第二区域B用于形成隔离层，隔离层用于划分电容接触孔和隔离相邻的电容接触窗。
本实施例中，第五掩膜层152(参考图13)覆盖第一区域A的第二牺牲层142顶面，并暴露出第二区域B的第二牺牲层142顶面。相应地，通过第五掩膜层152进行干法刻蚀工艺，包括：去除第二区域B的第二牺牲层142以及去除第二区域B的第二隔离侧墙133。
本实施例中，干法刻蚀工艺的刻蚀剂针对的是第二牺牲层142的材料，在进行干法刻蚀工艺的过程中，由于第二牺牲层142的刻蚀速率较快，当刻蚀剂对第一封口层151进行刻蚀时，第一隔离侧墙132逐渐被暴露出来；同时，又由于干法刻蚀工艺的角度并不总是垂直于基底10表面(既可能是刻蚀工艺本身设定的原因，也可能是工艺稳定性的原因)，刻蚀剂会对暴露出的第一隔离侧墙132以及进一步暴露出来的第一封口层151侧壁进行刻蚀，从而导致在干法刻蚀工艺中，不仅第二牺牲层142和第二隔离侧墙133会被去除，部分第一隔离侧墙132以及部分第一封口层151也会被去除，此时，第二区域B中的第一空隙134(参考图13)被转换为第二空隙135，第二空隙135的顶面低于第一空隙134的顶面。
其中，在垂直于基底10表面的方向上，被去除的第一隔离侧墙132的厚度与第二隔离侧墙133和第一隔离侧墙132的刻蚀选择比有关，被去除的第一封口层151的厚度与第二隔离侧墙133与第一封口层151的刻蚀选择比有关。具体地，在干法刻蚀工艺下，第二隔离侧墙133和第一隔离侧墙132的刻蚀选择比越大，被去除的第一隔离侧墙132越薄，剩余的第一隔离侧墙132越厚；相应地，第二隔离侧墙133与第一封口层151的刻蚀选择比越大，被去除的第一封口层151越薄，剩余的第一封口层151越厚。
参考图15，进行沉积工艺和平坦化工艺。
本实施例中，在进行沉积工艺之前去除第五掩膜层152，以避免后续进行平坦化工艺的过程中，研磨装置需要与至少三种材料接触(第五掩膜层152的材料、第二牺牲层142的材料以及沉积工艺沉积的材料)，进而避免因不同材料去除速率差异较大而形成的凹凸结构对研磨装置造成影响，从而保证研磨装置具有较长的使用寿命，或者，无需因避免去除速率差异过大而中途更换研磨液或掩膜部件，从而提高工艺效率。
在其他实施例中，在进行沉积工艺时保留第五掩膜层，且后续采用平坦化工艺同时去除第五掩膜层和其他膜层。如此，有利于减少工艺步骤，缩短工艺周期。
本实施例中，沉积工艺用于形成封隔层16，封隔层16包括用于封堵第二空隙135的第二封口层(未标示)以及用于隔离相邻电容接触窗的隔离层(未标示)，即在同一沉积工艺中，同时形成第一封口层和隔离层。
具体地，先形成顶面高于第一封口层151顶面的隔离膜和第二封口膜，再对隔离膜和第二封口膜进行平坦化工艺，形成顶面平齐于第一封口层151顶面的隔离层和第二封口层。
本实施例中，在平坦化工艺中，还去除第一区域A中的位于第一封口层151上的第二牺牲层142，暴露出第一封口层151。
参考图16，对剩余的第一区域A中的第二牺牲层142和第二隔离侧墙133(参考图14)进行刻蚀，形成初始电容接触孔161。
要形成电容接触孔，以使填充于电容接触孔内的电容接触窗与基底10内的有源区接触，还需要去除位于初始电容接触孔161与基底10之间的第一隔离膜131a，以形成暴露基底10表面的电容接触孔。
本实施例中，在去除第二牺牲层142之后，进一步去除位于初始电容接触孔161与基底10之间的第一隔离膜131a，以形成电容接触孔。
参考图17，形成第二空隙135。
本实施例中，电容接触窗17包括位于顶部的第一电容接触窗171以及位于底部的第二电容接触窗172，第二电容接触窗172与基底10的接触电阻小于第一电容接触窗171与基底10的接触电阻。如此，有利于提高信号传输性能。
其中，第一电容接触窗171的材料包括钨，第二电容接触窗172的材料包括多晶硅。
本实施例中，可在不使用额外掩膜的情况下，由具有高度差的多层隔离侧墙定义第一封口层的厚度，即由顶面较低的隔离侧墙提供支撑，由顶面较高的隔离侧墙提供位置限定，以形成厚度较厚的第一封口层，保证第一封口层具有较好的支撑性，以及保证半导体结构具有较好的结构稳定性。
相应地，本申请实施例还提供一种半导体结构，可采用上述半导体结构的制作方法制成。
参考图17，半导体结构包括：基底10、位于基底10上的位线结构11以及位于位线结构11相对两侧的电容接触孔(未标示)；第一隔离侧墙132，第一隔离侧墙132位于位线结构11和电容接触孔之间，位于位线结构11相对两侧的第一隔离侧墙132之间具有空隙；封口层，封口层覆盖第一隔离侧墙132顶面且封堵空隙顶部开口，在垂直于基底10的方向上，位于第一隔离侧墙132上的封口层的厚度大于等于30nm。
本实施例中，空隙包括位于相对的电容接触孔之间的第一空隙(未图示)，以及在位线结构11延伸方向上，位于相邻第一空隙之间的第二空隙135。其中，第一空隙的顶面高于第二空隙135的顶面。
本实施例中，半导体结构还包括：隔离层，隔离层位于位线结构11相对两 侧，隔离层用于隔离相邻电容接触孔，第二空隙135位于相对的隔离层之间。
本实施例中，封口层包括用于封堵第一空隙的第一封口层151以及用于封堵第二空隙135的第二封口层。其中，在垂直于基底10表面的方向上，第一封口层151的厚度大于等于30nm，例如为32nm、34nm或36nm。
本实施例中，在垂直于基底10表面的方向上，空隙的厚度小于等于80nm，例如为72nm、75nm或78nm。如此，有利于避免因空隙无法提供支撑而导致的结构崩塌，保证半导体结构具有较好的结构稳定性。
本实施例中，封口层的厚度大于预设值，有利于保证封口层具有良好的支撑性能，避免封口层因不满足承压要求而发生坍塌，从而保证半导体结构具有良好的结构稳定性。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例中，通过提供基底和位于基底上的位线结构，位线结构包括顶层介质层，位线结构相对两侧具有电容接触孔；形成覆盖顶层介质层侧壁的第一隔离侧墙，以及形成覆盖第一隔离侧墙侧壁的第二隔离侧墙，第一隔离侧墙位于位线结构和电容接触孔之间，第二隔离侧墙的顶面高于第一隔离侧墙的顶面；去除至少部分顶层介质层，形成第一空隙；进行沉积工艺，形成覆盖第一隔离侧墙顶面且封堵空隙顶部开口的第一封口膜，第一封口膜顶面高于第二隔离侧墙顶面；进行第一平坦化工艺，去除高于第二隔离侧墙顶面的第一封口膜，剩余第一封口膜作为第一封口层。这样，有利于提高半导体结构的结构稳定性。

Claims (12)

  1. 一种半导体结构的制作方法，包括：
    提供基底和位于所述基底上的位线结构，所述位线结构包括顶层介质层，所述位线结构相对两侧具有电容接触孔；
    形成覆盖所述顶层介质层侧壁的第一隔离侧墙，以及形成覆盖所述第一隔离侧墙侧壁的第二隔离侧墙，所述第一隔离侧墙位于所述位线结构和所述电容接触孔之间，所述第二隔离侧墙的顶面高于所述第一隔离侧墙的顶面；
    去除至少部分所述顶层介质层，形成第一空隙；
    进行沉积工艺，形成覆盖所述第一隔离侧墙顶面且封堵所述空隙顶部开口的第一封口膜，所述第一封口膜顶面高于所述第二隔离侧墙顶面；
    进行第一平坦化工艺，去除高于所述第二隔离侧墙顶面的所述第一封口膜，剩余所述第一封口膜作为第一封口层。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，在形成所述第一封口层之后，还包括：在相邻所述位线结构之间填充牺牲层；形成掩膜层，且在同一刻蚀工艺中，通过所述掩膜层去除部分所述牺牲层、部分所述第一封口层、部分所述第一隔离侧墙以及部分所述第二隔离侧墙，以将部分所述第一空隙刻蚀为第二空隙。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，在形成所述第二空隙之后，形成位于相邻所述位线结构之间的隔离层以及封堵所述第二空隙顶部开口的第二封口层，所述第一封口层和所述第二封口层构成所述封口层。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，形成所述隔离层以及所述第二封口层的工艺步骤包括：在同一沉积工艺中，形成位于相邻所述位线结构之间的隔离膜以及封堵所述第二空隙顶部开口的第二封口膜；进行第二平坦化工艺，形成所述隔离层和所述第二封口层，所述隔离层和所述第二封口层的顶面与所述第一封口层顶面平齐。
  5. 根据权利要求3所述的半导体结构的制作方法，其中，在形成所述第二 封口层之后，去除剩余所述牺牲层，形成所述电容接触孔；填充所述电容接触孔，以形成电容接触窗。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，在同一刻蚀工艺中，去除剩余所述牺牲层和剩余所述第二隔离侧墙，形成所述电容接触孔。
  7. 一种半导体结构，包括：
    基底、位于所述基底上的位线结构以及位于所述位线结构相对两侧的电容接触孔；
    第一隔离侧墙，所述第一隔离侧墙位于所述位线结构与所述电容接触孔之间，位于所述位线结构相对两侧的所述第一隔离侧墙之间具有空隙；
    封口层，所述封口层覆盖所述第一隔离侧墙顶面且封堵所述空隙顶部开口，在垂直于所述基底的方向上，位于所述第一隔离侧墙上的所述封口层的厚度大于等于30nm。
  8. 根据权利要求7所述的半导体结构，其中，所述空隙包括位于相对的所述电容接触孔之间的第一空隙，以及在所述位线结构延伸方向上，位于相邻所述第一空隙之间的第二空隙。
  9. 根据权利要求8所述的半导体结构，其中，还包括：隔离层，所述隔离层位于所述位线结构相对两侧，所述隔离层用于隔离相邻所述电容接触孔，所述第二空隙位于相对的所述隔离层之间。
  10. 根据权利要求8所述的半导体结构，其中，所述封口层包括用于封堵所述第一空隙的第一封口层和用于封堵所述第二空隙的第二封口层。
  11. 根据权利要求8所述的半导体结构，其中，在垂直于所述基底表面的方向上，所述第一空隙的顶面高于所述第二空隙的顶面。
  12. 根据权利要求7所述的半导体结构，其中，在垂直于所述基底表面的方向上，所述空隙的厚度小于等于80nm。
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