WO2022062547A1 - 存储器的制造方法和存储器 - Google Patents

存储器的制造方法和存储器 Download PDF

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Publication number
WO2022062547A1
WO2022062547A1 PCT/CN2021/103820 CN2021103820W WO2022062547A1 WO 2022062547 A1 WO2022062547 A1 WO 2022062547A1 CN 2021103820 W CN2021103820 W CN 2021103820W WO 2022062547 A1 WO2022062547 A1 WO 2022062547A1
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Prior art keywords
bit line
layer
forming
line contact
dielectric layer
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PCT/CN2021/103820
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English (en)
French (fr)
Inventor
平尔萱
周震
张令国
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长鑫存储技术有限公司
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Priority to US17/479,162 priority Critical patent/US11985815B2/en
Publication of WO2022062547A1 publication Critical patent/WO2022062547A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a method for manufacturing a memory and a memory.
  • Memory is a memory component used to store programs and various data information. Random access memory is divided into static random access memory and dynamic random access memory.
  • a dynamic random access memory typically includes a capacitor, which is used to store charge representing the stored information, and a transistor connected to the capacitor, which is a switch that controls the flow of charge into and out of the capacitor.
  • the word line gives a high level, the transistor is turned on, and the bit line charges the capacitor.
  • the word line also gives a high level, the transistor is turned on, and the capacitor is discharged, so that the bit line obtains the read signal.
  • the technical problem solved by the embodiments of the present application is to provide a method for manufacturing a memory and a memory, so as to improve the performance of the memory.
  • the method for manufacturing the memory includes: providing a substrate and a plurality of discrete initial bit line contact structures, the substrate has a plurality of active regions, and each The initial bit line contact structure is electrically connected to the active region; the initial bit line contact structure is partially located in the substrate; a dummy bit line structure is formed on top of the initial bit line contact structure; the initial bit line contact structure is etched an initial bit line contact structure, forming a bit line contact layer, and a gap between the side wall of the bit line contact layer and the substrate; forming a first dielectric layer on the side wall of the dummy bit line structure, and the The first dielectric layer is also located directly above the gap.
  • the step of forming the dummy bit line structure includes: forming a dummy bit line layer on the substrate, the dummy bit line layer covering the initial bit line contact structure; on the dummy bit line layer A patterned mask layer is formed thereon; using the patterned mask layer as a mask, the dummy bit line layer is etched to form a dummy bit line structure.
  • the step of forming the patterned mask layer includes: forming a plurality of discrete cores on the dummy bit line layer; forming a top and sidewall covering the core and the dummy bit lines The sidewall film of the layer; the sidewall film is etched to form the sidewall layer located on the opposite sidewall of the core part; the core part is removed, and the sidewall layer is used as the patterned mask layer.
  • the step of forming the gap includes: after forming the dummy bit line structure, using the patterned mask layer as a mask, etching the initial bit line contact structure to form the bit line contact structure. line contact layer and the gap.
  • the step of forming the first dielectric layer includes forming an initial first dielectric on sidewalls and tops of the dummy bitline structures, a portion of the sidewalls of the bitline contact layer, and the substrate film; etching the initial first dielectric film to form the first dielectric layer located on the sidewall of the dummy bit line structure and part of the sidewall of the bit line contact layer.
  • the material of the first dielectric layer includes a low dielectric constant material.
  • the method further includes: forming a second dielectric layer covering the sidewalls of the dummy bit line structure, and the first dielectric layer also covers the second dielectric layer. side wall.
  • the material of the second dielectric layer includes a low dielectric constant material.
  • the method further includes: forming a sacrificial layer filling the area between the adjacent dummy bit line structures, and the sacrificial layer also covers the first dielectric layer. sidewalls; after forming the sacrificial layer, removing the dummy bit line structure to form a through hole exposing the bit line contact layer; forming a bit line conductive portion filling the through hole and covering the bit line contact layer .
  • the step of forming the bit line conductive portion includes: forming a barrier layer on the bottom and sidewalls of the through hole; and forming a conductive layer filling the through hole on the surface of the barrier layer.
  • the method further includes: forming an insulating cap layer on top of the bit line conductive portion; after forming the insulating cap layer, removing the sacrificial layer; removing the sacrificial layer After layering, a protective layer is formed on the surfaces of the first dielectric layer and the insulating cap layer.
  • An embodiment of the present application further provides a memory manufactured by the aforementioned manufacturing method, comprising: a substrate and a plurality of discrete bit line contact layers, the substrate has a plurality of active regions, and each of the bit line contact layers electrically connected to the active region; the bit line contact layer is partially located in the substrate, and there is a gap between the sidewall of the bit line contact layer located in the substrate and the substrate; the bit line is conductive part, the bit line conductive part is located on the top of the bit line contact layer; a first dielectric layer, the first dielectric layer is located on the sidewall of the bit line conductive part, and the first dielectric layer is also located on the above the gap.
  • the memory further includes: a second dielectric layer, and the second dielectric layer covers the sidewall of the bit line conductive portion, and the first dielectric layer covers the sidewall of the second dielectric layer wall.
  • the material of the first dielectric layer is a low dielectric constant material. Low-k materials can reduce parasitic capacitance and improve memory performance.
  • the material of the second dielectric layer is a low dielectric constant material. Low-k materials can reduce parasitic capacitance and improve memory performance.
  • 1 to 16 are schematic structural diagrams corresponding to each step in the manufacturing method of the memory provided by the first embodiment of the present application;
  • FIG. 17 is a schematic structural diagram of a memory provided by a second embodiment of the present application.
  • embodiments of the present application provide a method for manufacturing a memory, by forming a gap between the sidewall of the bit line contact layer and the substrate, thereby reducing the parasitic between the bit line contact layer and the buried word line capacitors to improve memory performance.
  • FIGS. 1 to 16 are schematic structural diagrams corresponding to each step in the manufacturing method.
  • a substrate 100 and a plurality of discrete initial bit line contact structures 101 are provided, the substrate 100 has a plurality of active regions 102 , and each initial bit line contact structure 101 is electrically connected to the active region 102 .
  • the material of the substrate 100 includes silicon, germanium or other semiconductor materials.
  • the regions between adjacent active regions 102 are filled with first isolation layers 103 , and the first isolation layers 103 are used to isolate the plurality of active regions 102 .
  • the material of the first isolation layer 103 is an insulating material, such as silicon dioxide.
  • each initial bit line contact structure 101 is located in the substrate 100 , and a part is higher than the surface of the substrate 100 .
  • the initial bit line contact structure 101 is partially buried in the substrate 100, which can reduce the parasitic capacitance of the memory and improve the performance of the memory.
  • the initial bit line contact structure can also be completely buried in the substrate, and the upper surface of the initial bit line contact structure is flush with the upper surface of the substrate.
  • the material of the initial bit line contact structure 101 is a conductive material, such as polysilicon.
  • a second isolation layer 104 may also be formed on the surface of the substrate 100 .
  • the second isolation layer 104 fills the area between the discrete initial bit line contact structures 101 for isolating a plurality of initial bit line contact structures 101; the top of the second isolation layer 104 may be flush with the top of the initial bit line contact structure 101, or May not be flush.
  • the material of the second isolation layer 104 is an insulating material, such as silicon nitride.
  • a dummy bit line structure 117 is formed on top of the initial bit line contact structure 101 , and the initial bit line contact structure 101 is etched to form a bit line contact layer 132 and a side wall of the bit line contact layer 132 and Gap 130 between substrates 100 .
  • the dummy bit line structure 117 is used to define the position and size of the subsequently formed bit line structure, that is, the size of the dummy bit line structure 117 is the same as that of the subsequently formed bit line structure. Since the dummy bit line structure 117 does not need to have conductive properties, an insulating material may be used as the material of the dummy bit line structure 117 .
  • the steps of forming the dummy bit line structure 117 include: forming a dummy bit line layer 105 on the substrate 100, the dummy bit line layer 105 covering the initial bit line contact structure 101; forming a patterned mask layer 115 on the dummy bit line layer 105; Using the patterned mask layer 115 as a mask, the dummy bit line layer 105 is etched to form a dummy bit line structure 117 .
  • the dummy bit line structure 117 is formed by a double patterning (SADP) method.
  • SADP double patterning
  • a dummy bit line layer 105 is formed on a substrate 100 , and the dummy bit line layer 105 covers the initial bit line contact structure 101 .
  • a bottom mask layer 106 and a core layer 109 are sequentially stacked on the dummy bit line layer 105 .
  • the underlying mask layer 106 includes: a first underlying mask layer 107 and a second underlying mask layer 108 .
  • the materials of the first underlying mask layer 107 and the second underlying mask layer 108 are different. Specifically, the material of the first underlying mask layer 107 may be silicon oxynitride, and the material of the second underlying mask layer 108 may be hydrogen-containing Silicon oxide.
  • the underlying mask layer may also be a single-layer structure.
  • the core layer 109 includes a first core layer 110 and a second core layer 111 .
  • the material of the first core layer 110 includes: silicon oxynitride.
  • the material of the second core layer 111 includes: containing silicon hydroxide.
  • the core layer may also be a single-layer structure.
  • a patterned photoresist layer 112 is formed on the core layer 109 .
  • the core layer 109 (refer to FIG. 1 ) is etched to form a plurality of discrete core portions 113 .
  • the core portion 113 has a double-layer structure, and in other embodiments, the core portion may also have a single-layer structure.
  • the patterned photoresist layer 112 is removed.
  • a spacer film 114 covering the top and sidewalls of the core portion 113 and the underlying mask layer 106 is formed.
  • the spacer film 114 is deposited by the atomic layer deposition technique; the thickness of the spacer film 114 formed by the atomic layer deposition technique is more uniform.
  • chemical vapor deposition, physical vapor deposition and other methods can be used to form the spacer film.
  • the material of the spacer film 114 is different from that of the core portion 113 , and may be silicon oxide, for example.
  • the spacer film 114 (refer to FIG. 3 ) is etched to form spacer layers 115 located on opposite sidewalls of the core portion 113 . Due to the etching load effect, the larger the etching area, the easier it is to be etched, and the spacer film 114 (refer to FIG. 3 ) deposited on the sidewall of the core portion 113 is not easily etched, thereby forming the spacer layer 115 .
  • the core portion 113 (refer to FIG. 4 ) is removed, and the spacer layer 115 is used as a patterned mask layer 115 .
  • the underlying mask layer 106 (refer to FIG. 4 ) is etched to form the patterned underlying mask layer 116 .
  • the patterned bottom mask layer 116 has a double-layer structure.
  • the patterned underlying mask layer can also be a single-layer structure.
  • the dummy bit line layer 105 is etched to form a dummy bit line structure 117 .
  • the patterned mask layer 115 (refer to FIG. 4 ) transfers the pattern to the dummy bit line structure 117 through the patterned underlying mask layer 116 . Therefore, the width of the dummy bit line structure 117 is the same as the width of the patterned mask layer 115. The smaller the width of the patterned mask layer 115 is, the smaller the width of the dummy bit line structure 117 is, and the smaller the size of the memory is. little.
  • the material of the dummy bit line structure 117 includes silicon nitride, silicon oxynitride or silicon carbonitride.
  • the dummy bit line structure may not be formed by a double patterning process.
  • a single-layer hard mask layer is directly formed on the dummy bit line layer, and the hard mask layer is subjected to photolithography.
  • forming a plurality of discrete core parts on the dummy bit line layer forming a spacer film covering the top and side walls of the core part and the dummy bit line layer; etching the spacer film to form opposite The sidewall layer of the sidewall is removed; the core part is removed, the sidewall layer is a patterned mask layer, and the dummy bit line layer is etched by using the patterned mask layer to form a dummy bit line structure.
  • the step of forming the gap 130 includes: after forming the dummy bit line structure 117 , using the patterned underlying mask layer 116 (refer to FIG. 5 ) as a mask, etching the second isolation layer 104 As well as the initial bit line contact structure 101 , a bit line contact layer 132 and a gap 130 between the sidewall of the bit line contact layer 132 and the substrate 100 are formed.
  • the formation of the dummy bit line structure 117 and the formation of the initial bit line structure 101 are performed in the same photolithography process, so that the process steps can be reduced.
  • the patterned underlying mask layer may be removed, and the initial bit line contact structure may be etched using the dummy bit line structure as a mask.
  • the initial bit line contact structure 101 is etched using the patterned underlying mask layer 116 as a mask.
  • a single-layer hard mask layer can also be formed only on the dummy bit line layer, the hard mask layer is photolithographically formed to form a core portion, and a sidewall layer is formed on the sidewall of the core portion to form a sidewall layer.
  • the wall layer is a patterned mask layer, and the dummy bit line layer and the initial bit line contact structure are etched to form the bit line contact layer.
  • bit line contact layer 132 There is a gap 130 between the sidewall of the bit line contact layer 132 and the substrate 100 (refer to FIG. 5 ), which can reduce the parasitic capacitance between the bit line contact layer 132 and the buried word line (not shown).
  • a first dielectric layer 131 is formed on the sidewalls of the dummy bit line structures 117 , and a second dielectric layer 118 is formed covering the sidewalls of the dummy bit line structures 117 , and the first dielectric layer 131 also covers the second dielectric layer 131 . sidewalls of the dielectric layer 118 .
  • the material of the first dielectric layer 131 includes a low dielectric constant material.
  • the material of the second dielectric layer 118 includes a low dielectric constant material.
  • a dielectric with a lower dielectric constant than silicon dioxide is a low dielectric constant material.
  • the low dielectric constant material can reduce the parasitic capacitance of the memory and improve the operation speed of the memory.
  • the process steps of forming the first dielectric layer 131 and the second dielectric layer 118 include: referring to FIG. A preliminary second dielectric film 128 is formed on the surface of the second isolation layer 104 and the bottom of the gap 130 .
  • an initial first dielectric film 129 is formed on the sidewall and top of the dummy bit line structure 117 , part of the sidewall of the bit line contact layer 132 , and the second isolation layer 104 , and the initial first dielectric film 129 also covers part of the initial dielectric film 129 .
  • the second dielectric film 128 is formed on the sidewall and top of the dummy bit line structure 117 , part of the sidewall of the bit line contact layer 132 , and the second isolation layer 104 , and the initial first dielectric film 129 also covers part of the initial dielectric film 129 .
  • the second dielectric film 128 is formed on the sidewall and top of the dummy bit line structure 117 , part of the sidewall of the bit line contact layer 132 , and the second isolation layer 104 , and the initial first dielectric film 129 also covers part of the initial dielectric film 129 .
  • the second dielectric film 128 is formed on the sidewall and top of the dummy bit line structure 117 , part
  • the initial first dielectric film 129 is formed by a rapid deposition technique, such as a plasma chemical vapor deposition technique or a plasma physical vapor deposition technique.
  • the deposition rate is fast, the step coverage is poor, and the gap 130 is not filled.
  • the dielectric constant of the air in the gap 130 is extremely low, which can effectively reduce the parasitic capacitance between the bit line contact layer 132 and the buried word line (not shown).
  • the initial first dielectric film 129 may be formed by using a plasma chemical vapor deposition technique.
  • the initial first dielectric film 129 (refer to FIG. 8 ) and the initial second dielectric film 128 (refer to FIG. 8 ) are etched to form a sidewall of the dummy bit line structure 117 and a part of the bit line contact layer 132
  • the first dielectric layer 131 is located directly above the gap 130 .
  • the first dielectric layer may not be located on part of the sidewall of the bit line contact layer.
  • a sacrificial layer 119 filling the region between adjacent dummy bit line structures 117 is formed, and the sacrificial layer 119 also covers the sidewalls of the first dielectric layer 131 .
  • the sacrificial layer 119 also covers the surface of the second isolation layer 104 .
  • the material of the sacrificial layer 119 is different from that of the first dielectric layer 131 , and can be silicon oxide, for example.
  • the dummy bit line structure 117 (refer to FIG. 10 ) is removed to form a via hole exposing the bit line contact layer 132 .
  • the etching rate of the dummy bit line structure 117 is greater than the etching rate of the sacrificial layer 119 , and the etching selectivity ratio between the material of the dummy bit line structure 117 and the material of the sacrificial layer 119 is 5-15, for example, 8 , 10, 13.
  • the dummy bit line structure 117 is removed by wet etching, and the etching solvent is a hot phosphoric acid solution. In other embodiments, the dummy bit line structure may also be removed by dry etching.
  • bit line conductive portion 120 filling the via hole and covering the bit line contact layer 132 is formed.
  • the bit line conductive portion 120 is a conductive structure in the bit line structure.
  • the bit line conductive portion 120 is formed by filling the via hole, and the bit line conductive portion 120 is supported by the sacrificial layer 119 during the formation process. Therefore, even if the width of the bit line conductive portion 120 is narrow, it is not easy to tilt or collapse. In addition, because the etching process is not used, impurities generated by etching will not remain in the bit line conductive portion 120 , thereby reducing the resistance of the bit line conductive portion 120 and improving the operating speed of the memory.
  • the steps of forming the bit line conductive portion 120 include: forming a barrier layer 121 on the bottom and sidewalls of the via hole; and forming a conductive layer 122 filling the via hole on the surface of the barrier layer 121 .
  • the thicknesses of the conductive layer 122 and the barrier layer 121 formed by the atomic deposition layer deposition technology are more uniform. In other embodiments, other deposition techniques may also be employed.
  • the material of the barrier layer 121 includes one or both of tantalum nitride or titanium nitride. Tantalum nitride or titanium nitride can conduct electricity and have good blocking ability, which can block the diffusion of the conductive layer 122 .
  • the material of the conductive layer 122 includes one or more of ruthenium, tungsten, gold or silver. Ruthenium, tungsten, gold or silver are all low-resistance metals, which can further reduce the resistance of the conductive layer 122 and improve the running speed of the memory.
  • bit line conductive portion may also be a single-layer structure.
  • the conductive layer 122 and the barrier layer 121 are also formed on the top surface of the sacrificial layer 119 ; as shown in FIG. 13 , the bit line conductive portion 120 is planarized to remove the layers higher than the sacrificial layer. Conductive layer 122 and barrier layer 121 on the top surface of 119 (refer to FIG. 12 ).
  • a chemical mechanical polishing technique is used to planarize the bit line conductive portion 120 .
  • an insulating capping layer 123 is formed on top of the bit line conductive portion 120 .
  • the insulating capping layer 123 serves as an insulating structure in the bit line structure.
  • the insulating capping layer 123 is formed by a double patterning process (SADP), and the size of the insulating capping layer 123 formed by the double patterning process (SADP) is more precise.
  • SADP double patterning process
  • the sacrificial layer 119 is removed (refer to FIG. 14).
  • the etching rate of the sacrificial layer 119 is greater than the etching rate of the insulating cap layer 123 , and the etching selectivity ratio between the material of the sacrificial layer 119 and the material of the insulating cap layer 123 is 5-15, such as 8, 10, and 13.
  • the high etching selectivity ratio can ensure that in the process of removing the sacrificial layer 119, the insulating cap layer 123 maintains the original shape and size.
  • the sacrificial layer 119 is removed by wet etching, and the etching reagent is a hydrofluoric acid solution. In other embodiments, the sacrificial layer may also be removed by dry etching.
  • a protective layer 124 is formed on the surfaces of the first dielectric layer 131120 and the insulating cap layer 123 .
  • the protective layer 124 is also located on the surface of the second isolation layer 104 .
  • the protective layer 124 is formed by using the atomic layer deposition technique.
  • the material of the protective layer 124 includes silicon carbonitride.
  • bit line contact layer 132 there is a gap between the bit line contact layer 132 and the substrate 100 , which can reduce the parasitic capacitance between the bit line contact layer 132 and the buried word line, thereby improving the operating speed of the memory.
  • FIG. 17 is a schematic structural diagram of a memory provided in this embodiment.
  • the memory includes: a substrate 200 and a plurality of discrete bit line contact layers 232, the substrate 200 has a plurality of active regions 202, and each bit line contact layer 232 is electrically connected to the active region 202; bit line contact The layer 232 is partially located in the substrate 200, and there is a gap 230 between the sidewall of the bit line contact layer 232 in the substrate 200 and the substrate 200; the bit line conductive part 220 is located on the top of the bit line contact layer 232 ; The first dielectric layer 231, the first dielectric layer 231 is located on the sidewall of the bit line conductive portion 220, and the first dielectric layer 231 is also located directly above the gap 230.
  • a first isolation layer 203 is further included between the active regions 202 , and the first isolation layer 203 is used to isolate the active regions 202 .
  • the surface of the substrate 200 further includes a second isolation layer 204 for isolating the bit line contact layer 232 .
  • the bit line conductive portion 220 further includes: a conductive layer 222 on top of the bit line contact layer 232 ;
  • the material of the conductive layer 222 includes one or more of ruthenium, tungsten, gold or silver. Ruthenium, tungsten, gold or silver are all low-resistance metals, which can reduce the resistance of the conductive layer 206 and improve the running speed of the memory.
  • the material of the barrier layer 221 is a conductive material, such as tantalum nitride or titanium nitride.
  • the thickness of the barrier layer 221 is 2.5-6 nm, for example, 3 nm, and the barrier layer 221 with this thickness has a good ability of blocking the diffusion of the conductive layer 222 .
  • the memory of this embodiment further includes: the second dielectric layer 218 located on the bit line conductive portion 220, the sidewall of the bit line contact layer 232, and the bottom of the gap 230; the insulating cap layer 223 located on the top of the bit line conductive portion 220; the insulating cap layer 223 and the protective layer 224 on the surface of the first dielectric layer 231 , and the protective layer 224 is also located on the surface of the second isolation layer 204 .
  • the method for manufacturing a memory includes: providing a substrate and a plurality of discrete initial bit line contact structures, the substrate has a plurality of active regions, and each initial bit line contact structure is electrically connected to the active region;
  • the bit line contact structure is partially located in the substrate; a dummy bit line structure is formed on the top of the initial bit line contact structure; the initial bit line contact structure is etched to form a bit line contact layer, and is located between the sidewall of the bit line contact layer and the substrate
  • the gap is formed; the first dielectric layer is formed on the sidewall of the dummy bit line structure, and the first dielectric layer is also located directly above the gap. In this way, the parasitic capacitance of the bit line contact layer and the buried word line can be reduced, thereby increasing the operating speed of the memory.

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Abstract

本申请实施例提供一种存储器的制造方法和存储器，存储器的制造方法包括：提供基底以及多个分立的初始位线接触结构，基底内具有多个有源区，且每一初始位线接触结构与有源区电连接；初始位线接触结构部分位于基底内；在初始位线接触结构的顶部形成伪位线结构；刻蚀初始位线接触结构，形成位线接触层，以及位于位线接触层的侧壁与基底之间的间隙；形成位于伪位线结构侧壁的第一介质层，且第一介质层还位于间隙正上方。如此，可以减小位线接触层与埋入式字线的寄生电容，从而提高存储器的运行速率。

Description

存储器的制造方法和存储器
相关申请的交叉引用
本申请要求在2020年09月24日提交中国专利局、申请号为202011018122.5、申请名称为“存储器的制造方法和存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体领域，特别涉及一种存储器的制造方法和存储器。
背景技术
存储器是用来存储程序和各种数据信息的记忆部件，随机存储器分为静态随机存储器和动态随机存储器。动态随机存储器通常包括电容器以及与电容器连接的晶体管，电容器用来存储代表存储信息的电荷，晶体管是控制电容器的电荷流入和释放的开关。在写入数据时字线给出高电平，晶体管导通，位线向电容器充电。读出时字线同样给出高电平，晶体管导通，电容器放电，使位线获得读出信号。
然而，随着存储器工艺节点的不断缩小，存储器的性能有待提高。
发明内容
本申请实施例解决的技术问题为提供一种存储器的制造方法和存储器，以提高存储器的性能。为解决上述问题，本申请实施例提供一种存储器的制造方法，存储器的制造方法包括：提供基底以及多个分立的初始位线接触结构，所述基底内具有多个有源区，且每一所述初始位线接触结构与所述有源区电连接；所述初始位线接触结构部分位于所述基底内；在初始所述位线接触结构的顶部形成伪位线结构；刻蚀所述初始位线接触结构，形成位线接触层，以及位于所述位线接触层的侧壁与所述基底之间的间隙；形成位于所述伪位线结构侧壁的第一介质层，且所述第一介质层还位于所述间隙正上方。
在一些实施例中，形成所述伪位线结构的步骤包括：在所述基底上形成伪位线层，所述伪位线层覆盖所述初始位线接触结构；在所述伪位线层上形成图形化的掩膜层；以所述图形化的掩膜层为掩膜，刻蚀所述伪位线层，形成伪位线结构。
在一些实施例中，形成所述图形化的掩膜层步骤包括：在所述伪位线层上形成多个分立的核心部；形成覆盖所述核心部顶部和侧壁以及所述伪位线层的侧墙膜；对所述侧墙膜进行刻蚀处理，形成位于所述核心部的相对的侧壁的侧墙层；去除所述核心部，所述侧墙层作为所述图形化的掩膜层。
在一些实施例中，形成所述间隙的步骤包括：形成所述伪位线结构后，以所述图形化的掩膜层为掩模，刻蚀所述初始位线接触结构，形成所述位线接触层以及所述间隙。
在一些实施例中，形成所述第一介质层的步骤包括：在所述伪位线结构的侧壁和顶部、所述位线接触层的部分侧壁以及所述基底上形成初始第一介质膜；对所述初始第一介质膜进行刻蚀，形成位于所述伪位线结构侧壁以及所述位线接触层的部分侧壁的所述第一介质层。
在一些实施例中，所述第一介质层的材料包括低介电常数材料。
在一些实施例中，形成所述伪位线结构后，还包括：形成覆盖所述伪位线结构侧壁的第二介质层，且所述第一介质层还覆盖所述第二介质层的侧壁。
在一些实施例中，所述第二介质层的材料包括低介电常数材料。
在一些实施例中，形成所述第一介质层后，还包括：形成填充相邻所述伪位线结构之间的区域的牺牲层，且所述牺牲层还覆盖所述第一介质层的侧壁；在形成所述牺牲层之后，去除所述伪位线结构，形成露出所述位线接触层的通孔；形成填充所述通孔且覆盖所述位线接触层的位线导电部。
在一些实施例中，形成所述位线导电部的步骤包括：在所述通孔的底部及侧壁形成阻挡层；在所述阻挡层表面形成填充满所述通孔的导电层。
在一些实施例中，形成所述位线导电部后，还包括：在所述位线导电部的顶部形成绝缘盖层；形成所述绝缘盖层后，去除所述牺牲层；去除所述牺牲层 后，在所述第一介质层和绝缘盖层的表面形成保护层。
本申请实施例还提供一种采用前述的制造方法制造的存储器，包括：基底以及多个分立的位线接触层，所述基底内具有多个有源区，且每一所述位线接触层与所述有源区电连接；所述位线接触层部分位于所述基底内，且位于所述基底内的所述位线接触层的侧壁与所述基底之间具有间隙；位线导电部，所述位线导电部位于所述位线接触层的顶部；第一介质层，所述第一介质层位于所述位线导电部的侧壁，且所述第一介质层还位于所述间隙正上方。
在一些实施例中，所述存储器还包括：第二介质层，且所述第二介质层覆盖所述位线导电部的侧壁，所述第一介质层覆盖所述第二介质层的侧壁。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
本申请实施例的位线接触层的侧壁与基底之间具有间隙，可以减少位线接触层与埋入式字线的寄生电容，提升存储器的运行速率。
另外，第一介质层的材料为低介电常数材料。低介电常数材料可以减小寄生电容，提高存储器的性能。
另外，第二介质层的材料为低介电常数材料。低介电常数材料可以减小寄生电容，提高存储器的性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1至图16为本申请第一实施例提供的存储器的制造方法中各步骤对应的结构示意图；
图17为本申请第二实施例提供的存储器的结构示意图。
具体实施方式
由背景技术可知，现有技术的存储器的性能有待提高。
分析发现，导致上述问题的主要原因包括：随着工艺节点的不断缩小，位线接触层与埋入式字线的距离越来越窄，二者之间的寄生电容越来越大，从而影响存储器的运行速率。
为解决上述问题，本申请实施例提供一种存储器的制造方法，通过在位线接触层的侧壁与基底之间形成间隙，从而减小位线接触层与埋入式字线之间的寄生电容，提高存储器的性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请第一实施例提供一种存储器的制造方法，图1至图16为该制造方法中各步骤对应的结构示意图。
参考图1，提供基底100以及多个分立的初始位线接触结构101，基底100内具有多个有源区102，且每一初始位线接触结构101与有源区102电连接。
基底100的材料包括硅、锗或者其它半导体材料。
相邻的有源区102之间的区域填充有第一隔离层103，第一隔离层103用于隔离多个有源区102。第一隔离层103的材料为绝缘材料，例如可以为二氧化硅。
在本实施例中，每一初始位线接触结构101一部分位于基底100内，一部分高于基底100表面。初始位线接触结构101部分埋入基底100，能够减小存储器的寄生电容，提高存储器的性能。在其他实施例中，初始位线接触结构也可全部埋入基底，初始位线接触结构的上表面与基底上表面齐平。
初始位线接触结构101的材料为导电材料，例如可以为多晶硅。
本实施例中，基底100表面还可以形成有第二隔离层104。第二隔离层104填充分立的初始位线接触结构101之间的区域，用于隔离多个初始位线接触结构101；第二隔离层104顶部可以与初始位线接触结构101顶部齐平，也可以 不齐平。
第二隔离层104的材料为绝缘材料，例如可以为氮化硅。
结合参考图1至图6，在初始位线接触结构101的顶部形成伪位线结构117，以及刻蚀初始位线接触结构101，形成位线接触层132和位于位线接触层132侧壁与基底100之间的间隙130。
伪位线结构117用于定义后续形成的位线结构的位置和尺寸，也就是说，伪位线结构117的尺寸与后续形成的位线结构的尺寸相同。由于伪位线结构117不需要具有导电特性，因此可以采用绝缘材料作为伪位线结构117的材料。
形成伪位线结构117的步骤包括：在基底100上形成伪位线层105，伪位线层105覆盖初始位线接触结构101；在伪位线层105上形成图形化的掩膜层115；以图形化的掩膜层115为掩膜，刻蚀伪位线层105，形成伪位线结构117。
具体的，在本实施例中，以双重图形化(SADP)的方法形成伪位线结构117。
以下将结合附图对伪位线结构117的形成方法做详细说明。
参考图1，在基底100上形成伪位线层105，伪位线层105覆盖初始位线接触结构101。
在伪位线层105上形成依次堆叠的底层掩膜层106和核心层109。本实施例中，底层掩膜层106包括：第一底层掩膜层107和第二底层掩模层108。
第一底层掩膜层107与第二底层掩膜层108的材料不同，具体地，第一底层掩膜层107的材料可以为氮氧化硅，第二底层掩膜层108的材料可以为含氢氧化硅。
可以理解的是，在其他实施例中，底层掩膜层也可以为单层结构。
本实施例中，核心层109包括第一核心层110和第二核心层111。第一核心层110的材料包括：氮氧化硅。第二核心层111的材料包括：含氢氧化硅。
在其他实施例中，核心层也可以为单层结构。
在核心层109上形成图形化的光刻胶层112。
参考图2，以图形化的光刻胶层为112(参考图1)为掩膜，刻蚀核心层109 (参考图1)，形成多个分立的核心部113。核心部113为双层结构，在其他实施例中，核心部也可以为单层结构。
在形成核心部113之后，去除图形化的光刻胶层112。
参考图3，形成覆盖核心部113顶部和侧壁以及底层掩膜层106的侧墙膜114。
在本实施例中，采用原子层沉积技术沉积侧墙膜114；通过原子层沉积技术形成的侧墙膜114厚度更为均匀。在其他实施例中，可采用化学气相沉积、物理气相沉积等方法形成侧墙膜。
侧墙膜114的材料与核心部113的材料不同，例如可以为氧化硅。
参考图4，对侧墙膜114(参考图3)进行刻蚀处理，形成位于核心部113的相对的侧壁的侧墙层115。由于刻蚀负载效应，即刻蚀面积越大，越容易被刻蚀，沉积在核心部113侧壁的侧墙膜114(参考图3)不容易被刻蚀，从而形成了侧墙层115。
参考图5，去除核心部113(参考图4)，侧墙层115作为图形化的掩膜层115。
以图形化的掩膜层115为掩膜，刻蚀底层掩膜层106(参考图4)，形成图形化的底层掩模层116。本实施例中，图形化的底层掩膜层116为双层结构。在其他实施例中，图形化的底层掩膜层也可以为单层结构。
参考图6，以图形化的底层掩膜层116(参考图5)为掩膜，刻蚀伪位线层105(参考图5)，形成伪位线结构117。
在本实施例中，图形化的掩膜层115(参考图4)通过图形化的底层掩膜层116，将图案传递给了伪位线结构117。因此，伪位线结构117的宽度与图形化的掩膜层115的宽度一致，图形化的掩膜层115的宽度越小，伪位线结构117的宽度就越小，进而存储器的尺寸也越小。
伪位线结构117的材料包括氮化硅、氮氧化硅或碳氮化硅。
值得注意的是，在其他实施例中，也可以不采用双重图形化工艺形成伪位线结构，例如：直接在伪位线层上形成单层硬掩膜层，对该硬掩膜层进行光刻， 形成位于伪位线层上的多个分立的核心部；形成覆盖核心部顶部和侧壁以及伪位线层的侧墙膜；对侧墙膜进行刻蚀处理，形成位于核心部的相对的侧壁的侧墙层；去除核心部，侧墙层为图形化的掩膜层，利用该图形化的掩膜层刻蚀伪位线层，形成伪位线结构。
继续参考图6，本实施例中，形成间隙130的步骤包括：形成伪位线结构117后，以图形化的底层掩膜层116(参考图5)为掩模，刻蚀第二隔离层104以及初始位线接触结构101，形成位线接触层132，以及位于位线接触层132的侧壁与基底100之间的间隙130。在本实施例中，形成伪位线结构117与形成初始位线结构101在同一道光刻工艺中进行，如此，可以减少工艺步骤。在其他实施例中，也可以在形成伪位线结构后，去除图形化的底层掩膜层，以伪位线结构为掩模刻蚀初始位线接触结构。
值得注意的是，由于本实施例采用双重图形化工艺形成间隙130，因此是以图形化的底层掩膜层116为掩模刻蚀初始位线接触结构101。在其他实施例中，也可只在伪位线层上形成单层硬掩模层，对该硬掩膜层进行光刻后形成核心部，在核心部的侧壁形成侧墙层，以侧墙层为图形化的掩膜层，刻蚀伪位线层及初始位线接触结构，形成位线接触层。
位线接触层132的侧壁与基底100(参考图5)之间具有间隙130，可以减小位线接触层132与埋入式字线(未图示)之间的寄生电容。
参考图7至图9，形成位于伪位线结构117侧壁的第一介质层131，以及形成覆盖伪位线结构117侧壁的第二介质层118，且第一介质层131还覆盖第二介质层118的侧壁。
第一介质层131的材料包括低介电常数材料。
第二介质层118的材料包括低介电常数材料。介电常数低于二氧化硅的电介质为低介电常数材料。低介电常数材料可以减小存储器的寄生电容，提高存储器的运行速率。
具体地，本实施例中，形成第一介质层131及第二介质层118的工艺步骤包括：参考图7，在伪位线结构117的侧壁和顶部、位线接触层132的侧壁、 第二隔离层104的表面以及间隙130底部形成初始第二介质膜128。
参考图8，在伪位线结构117的侧壁和顶部、位线接触层132的部分侧壁、第二隔离层104上形成初始第一介质膜129，初始第一介质膜129还覆盖部分初始第二介质膜128。
本实施例中，以快速沉积技术形成初始第一介质膜129，如等离子化学气相沉积技术或等离子物理气相沉积技术。沉积速率较快，台阶覆盖性较差，间隙130不会被填充。间隙130内的空气的介电常数极低，可以有效降低位线接触层132与埋入式字线(未图示)的寄生电容。
本实施例中，可以采用等离子化学气相沉积技术形成初始第一介质膜129。
参考图9，对初始第一介质膜129(参考图8)和初始第二介质膜128(参考图8)进行刻蚀，形成位于伪位线结构117侧壁以及位线接触层132的部分侧壁的第一介质层131，以及覆盖伪位线结构117侧壁、位线接触层132侧壁以及间隙130底部的第二介质层118。第一介质层131位于间隙130的正上方。
在其他实施例中，第一介质层也可不位于位线接触层的部分侧壁。
在其他实施例中，也可没有第二介质层。
参考图10，形成填充相邻伪位线结构117之间的区域的牺牲层119，且牺牲层119还覆盖第一介质层131的侧壁。
牺牲层119还覆盖第二隔离层104的表面。
牺牲层119的材料与第一介质层131的材料不同，例如可以为氧化硅。
参考图11，去除伪位线结构117(参考图10)，形成露出位线接触层132的通孔。
在本实施例中，伪位线结构117的刻蚀速率大于牺牲层119的刻蚀速率，且伪位线结构117的材料与牺牲层119的材料的刻蚀选择比为5-15，例如8、10、13。采用湿法刻蚀的方法去除伪位线结构117，刻蚀溶剂采用热磷酸溶液。在其他实施例中，也可采用干法刻蚀的方法去除伪位线结构。
参考图12及图13，形成填充通孔且覆盖位线接触层132的位线导电部120。
位线导电部120是位线结构中的导电结构。采用填充通孔的方法形成位线 导电部120，位线导电部120在形成过程中受到牺牲层119的支撑，因此，即使位线导电部120的宽度窄，也不易发生倾斜或坍塌的现象。另外，由于不采用刻蚀工艺，在位线导电部120中不会残留由刻蚀产生的杂质；从而降低位线导电部120的电阻，提高存储器的运行速度。
形成位线导电部120的步骤包括：在通孔的底部及侧壁形成阻挡层121；在阻挡层121表面形成填充满通孔的导电层122。
在本实施例中，通过原子沉积层沉积技术形成的导电层122以及阻挡层121的厚度更为均匀。在其他实施例，也可采用其他沉积技术。
阻挡层121的材料包括氮化钽或氮化钛中的一种或两种。氮化钽或氮化钛能够导电，且具有良好的阻挡能力，能够阻挡导电层122的扩散。导电层122的材料包括钌、钨、金或银中的一种或多种。钌、钨、金或银都属于低电阻金属，能够进一步降低导电层122的电阻，提高存储器的运行速度。
在其他实施例中，位线导电部也可以为单层结构。
本实施例中，如图12所示，形成导电层122以及阻挡层121还位于牺牲层119顶部表面上；如图13所示，对位线导电部120进行平坦化处理，去除高于牺牲层119顶部表面的导电层122以及阻挡层121(参考图12)。
本实施例中，采用化学机械抛光技术对位线导电部120进行平坦化处理。
参考图14，在位线导电部120的顶部形成绝缘盖层123。
绝缘盖层123作为位线结构中的绝缘结构。
本实施例中，采用双重图形化工艺(SADP)形成的绝缘盖层123，双重图形化工艺(SADP)使得形成的绝缘盖层123的尺寸更加精准。
参考图15，形成绝缘盖层123后，去除牺牲层119(参考图14)。
牺牲层119的刻蚀速率大于绝缘盖层123的刻蚀速率，且牺牲层119的材料与绝缘盖层123的材料的刻蚀选择比为5-15，比如可以为8、10、13。高的刻蚀选择比能够保证在去除牺牲层119的过程中，绝缘盖层123保持原有的形貌和尺寸。本实施例采用湿法刻蚀的方法去除牺牲层119，刻蚀试剂采用氢氟酸溶液。在其他实施例中，也可采用干法刻蚀的方法去除牺牲层。
参考图16，在第一介质层131120和绝缘盖层123的表面形成保护层124。
本实施例中，保护层124还位于第二隔离层104的表面。
在本实施例中，采用原子层沉积技术形成保护层124。
保护层124的材料包括碳氮化硅。
综上所述，本实施例中位线接触层132与基底100之间具有间隙，可以减小位线接触层132与埋入式字线的寄生电容，从而提高存储器的运行速率。
本申请第二实施例还提供的一种存储器，该存储器可由第一实施例中的存储器的制造方法制造。图17为本实施例提供的存储器的结构示意图。参考图17，存储器包括：基底200以及多个分立的位线接触层232，基底200内具有多个有源区202，且每一位线接触层232与有源区202电连接；位线接触层232部分位于基底200内，且位于基底200内的位线接触层232的侧壁与基底200之间具有间隙230；位线导电部220，位线导电部220位于位线接触层232的顶部；第一介质层231，第一介质层231位于位线导电部220的侧壁，且第一介质层231还位于间隙230正上方。
以下将结合附图对本实施例提供的存储器进行详细说明。
有源区202之间还包括第一隔离层203，第一隔离层203用于隔离有源区202。
基底200表面还包括第二隔离层204，第二隔离层204用于隔离位线接触层232。
位线导电部220还包括：位于位线接触层232顶部的导电层222；位于位线接触层232与导电层222之间的阻挡层221，阻挡层221还覆盖导电层222的侧壁。
导电层222的材料包括钌、钨、金或银中的一种或多种。钌、钨、金或银均为低电阻金属，能够降低导电层206的电阻，提高存储器的运行速度。
阻挡层221的材料为导电材料，例如可以为氮化钽或氮化钛。
阻挡层221的厚度为2.5-6nm，比如可以为3nm，该厚度的阻挡层221具有良好的阻挡导电层222扩散的能力。
本实施例的存储器还包括：位于位线导电部220、位线接触层232侧壁、间隙230底部的第二介质层218；位于位线导电部220顶部的绝缘盖层223；位于绝缘盖层223及第一介质层231表面的保护层224，保护层224还位于第二隔离层204的表面上。
综上所述，本实施例提供的存储器的位线接触层232的侧壁与基底200之间具有间隙230，如此，可以减小位线接触层232与埋入式字线之间的寄生电容，提高存储器的性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例中，存储器的制造方法包括：提供基底以及多个分立的初始位线接触结构，基底内具有多个有源区，且每一初始位线接触结构与有源区电连接；初始位线接触结构部分位于基底内；在初始位线接触结构的顶部形成伪位线结构；刻蚀初始位线接触结构，形成位线接触层，以及位于位线接触层的侧壁与基底之间的间隙；形成位于伪位线结构侧壁的第一介质层，且第一介质层还位于间隙正上方。如此，可以减小位线接触层与埋入式字线的寄生电容，从而提高存储器的运行速率。

Claims (13)

  1. 一种存储器的制造方法，包括：
    提供基底以及多个分立的初始位线接触结构，所述基底内具有多个有源区，且每一所述初始位线接触结构与所述有源区电连接；
    所述初始位线接触结构部分位于所述基底内；
    在初始所述位线接触结构的顶部形成伪位线结构；
    刻蚀所述初始位线接触结构，形成位线接触层，以及位于所述位线接触层的侧壁与所述基底之间的间隙；
    形成位于所述伪位线结构侧壁的第一介质层，且所述第一介质层还位于所述间隙正上方。
  2. 根据权利要求1所述的存储器的制造方法，其中，形成所述伪位线结构的步骤包括：在所述基底上形成伪位线层，所述伪位线层覆盖所述初始位线接触结构；在所述伪位线层上形成图形化的掩膜层；以所述图形化的掩膜层为掩膜，刻蚀所述伪位线层，形成伪位线结构。
  3. 根据权利要求2所述的存储器的制造方法，其中，形成所述图形化的掩膜层步骤包括：在所述伪位线层上形成多个分立的核心部；形成覆盖所述核心部顶部和侧壁以及所述伪位线层的侧墙膜；对所述侧墙膜进行刻蚀处理，形成位于所述核心部的相对的侧壁的侧墙层；去除所述核心部，所述侧墙层作为所述图形化的掩膜层。
  4. 根据权利要求2所述的存储器的制造方法，其中，形成所述间隙的步骤包括：形成所述伪位线结构后，以所述图形化的掩膜层为掩模，刻蚀所述初始位线接触结构，形成所述位线接触层以及所述间隙。
  5. 根据权利要求1所述的存储器的制造方法，其中，形成所述第一介质层的步骤包括：在所述伪位线结构的侧壁和顶部、所述位线接触层的部分侧壁以及所述基底上形成初始第一介质膜；对所述初始第一介质膜进行刻蚀，形成位于所述伪位线结构侧壁以及所述位线接触层的部分侧壁的所述第一介质层。
  6. 根据权利要求1所述的存储器的制造方法，其中，所述第一介质层的材料包括低介电常数材料。
  7. 根据权利要求1所述的存储器的制造方法，其中，形成所述伪位线结构后，还包括：形成覆盖所述伪位线结构侧壁的第二介质层，且所述第一介质层还覆盖所述第二介质层的侧壁。
  8. 根据权利要求7所述的存储器的制造方法，其中，所述第二介质层的材料包括低介电常数材料。
  9. 根据权利要求1所述的存储器的制造方法，其中，形成所述第一介质层后，还包括：形成填充相邻所述伪位线结构之间的区域的牺牲层，且所述牺牲层还覆盖所述第一介质层的侧壁；在形成所述牺牲层之后，去除所述伪位线结构，形成露出所述位线接触层的通孔；形成填充所述通孔且覆盖所述位线接触层的位线导电部。
  10. 根据权利要求9所述的存储器的制造方法，其中，形成所述位线导电部的步骤包括：在所述通孔的底部及侧壁形成阻挡层；在所述阻挡层表面形成填充满所述通孔的导电层。
  11. 根据权利要求9所述的存储器的制造方法，其中，形成所述位线导电部后，还包括：在所述位线导电部的顶部形成绝缘盖层；形成所述绝缘盖层后，去除所述牺牲层；去除所述牺牲层后，在所述第一介质层和绝缘盖层的表面形成保护层。
  12. 一种采用如权利要求1-11任一项所述的制造方法制造的存储器，包括：
    基底以及多个分立的位线接触层，所述基底内具有多个有源区，且每一所述位线接触层与所述有源区电连接；
    所述位线接触层部分位于所述基底内，且位于所述基底内的所述位线接触层的侧壁与所述基底之间具有间隙；
    位线导电部，所述位线导电部位于所述位线接触层的顶部；
    第一介质层，所述第一介质层位于所述位线导电部的侧壁，且所述第一介质层还位于所述间隙正上方。
  13. 根据权利要求12所述的存储器的制造方法，其中，还包括：第二介质层，且所述第二介质层覆盖所述位线导电部的侧壁，所述第一介质层覆盖所述第二介质层的侧壁。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170005166A1 (en) * 2015-06-30 2017-01-05 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
CN109979940A (zh) * 2017-12-27 2019-07-05 长鑫存储技术有限公司 半导体存储器件及其制作方法
US10622249B2 (en) * 2017-09-29 2020-04-14 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170005166A1 (en) * 2015-06-30 2017-01-05 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US10622249B2 (en) * 2017-09-29 2020-04-14 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US10923390B2 (en) * 2017-09-29 2021-02-16 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
CN109979940A (zh) * 2017-12-27 2019-07-05 长鑫存储技术有限公司 半导体存储器件及其制作方法

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