WO2022053236A1 - Bauelement mit verbesserter anschlussstruktur und verfahren zur herstellung eines bauelements - Google Patents
Bauelement mit verbesserter anschlussstruktur und verfahren zur herstellung eines bauelements Download PDFInfo
- Publication number
- WO2022053236A1 WO2022053236A1 PCT/EP2021/072058 EP2021072058W WO2022053236A1 WO 2022053236 A1 WO2022053236 A1 WO 2022053236A1 EP 2021072058 W EP2021072058 W EP 2021072058W WO 2022053236 A1 WO2022053236 A1 WO 2022053236A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- component
- vias
- connection
- openings
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Definitions
- a component with an improved connection structure is specified. Furthermore, a method for producing a component, in particular such a component, is specified.
- One object is to specify a component, in particular an optoelectronic component, which can be mounted on a target substrate quickly, precisely, reliably and in a simplified manner.
- a further object is to specify a reliable and cost-effective method for producing a component, in particular a component with a structured mounting area.
- a component has a semiconductor body and a connection structure, with a rear side of the component being designed as a structured mounting surface which is formed at least in regions by the surface of the connection structure.
- the component is a light-emitting component, for example a pLED.
- a lateral width and/or a lateral length of the component is less than 1000 pm, 500 pm, 300 pm, 200 pm, 100 pm, 50 pm, 30 pm, 20 pm or less than 10 pm.
- the lateral width or the lateral length of the device is between 10 pm and 1000 pm, 10 pm and 500 pm, 10 pm and 300 pm inclusive, or between 10 pm and 100 pm inclusive.
- the device has an overall vertical height that is, for example, between 1 pm and 500 pm, 1 pm and 300 pm, 1 pm and 200 pm, 1 pm and 100 pm, or between 1 pm and 50 pm inclusive.
- the total vertical height can be between 1 pm and 10 pm inclusive, or between 1 pm and 5 pm inclusive, around 2-3 pm.
- the component described here is not limited to the above-mentioned geometric information and can have other widths, lengths or overall heights that are larger or smaller.
- a lateral direction is understood as meaning a direction which runs in particular parallel to a main extension area of the component, in particular parallel to a main extension area of the semiconductor body of the component.
- the lateral direction is parallel to a front side of the device.
- a vertical direction is understood to mean a direction that is in particular perpendicular to the main extension surface of the Component, the semiconductor body or the front side of the component.
- the vertical direction and the lateral direction are orthogonal to one another.
- the latter has an insulation structure which adjoins both the semiconductor body and the connection structure.
- the connection structure has vias, which extend along the vertical direction, for example through the insulating structure.
- the structured rear side of the component designed as a mounting surface is formed in regions by surfaces of the vias.
- the number of vias of the component can be at least 3, 5, 10, 20, 50 or 100.
- the number of vias of the device is between 3 and 500, 3 and 400, 3 and 300, 3 and 200, 3 and 100, 3 and 50, or between 3 and 20 inclusive.
- the selectively arranged vias each have a diameter that is, for example, less than 5 ⁇ m, 3 ⁇ m or less than 1 ⁇ m.
- the diameter is between 100 nm and 5 pm inclusive, 200 nm and 5 pm inclusive, or between 500 nm and 5 pm inclusive.
- the diameter of the vias is not limited to the information given above.
- the vias can each be in the form of strips and can have a greater or lesser length or width.
- connection structure Components or regions of the connection structure that have overlaps with the connection layer in a top view and extend along the vertical direction through the insulating structure for electrical contacting of the connection layer are referred to as vias.
- vias can be used as individual be designed as separate components or as integral components of the connection structure, such as integral components of a coherent contact layer of the connection structure.
- the components or regions of the connection structure referred to or defined as vias are each located in particular within one of the contact openings of the insulating structure and therefore have no overlaps with the insulating structure.
- this has a semiconductor body, an insulating structure and a connection structure.
- the semiconductor body has a first semiconductor layer, a second semiconductor layer and an active zone in between.
- the connection structure comprises a connection layer, which is in particular in direct electrical contact with the second semiconductor layer.
- the insulating structure borders both the second semiconductor layer and the connection layer, with the insulating structure laterally enclosing the connection layer and partially covering it in a top view.
- the connection structure has vias which are in electrical contact with the connection layer and extend through the insulation structure in the vertical direction.
- the component has a rear side as a mounting surface, which is structured and formed at least in regions by the surface of the connection structure, in particular by surfaces of the vias.
- the component instead of a smooth rear side, the component thus has a structured rear side as the mounting surface.
- the structured mounting surface thus facilitates the attachment of the component to a target mounting surface, such as on a target substrate .
- the structuring can be in the form of roughening and/or in the form of local depressions and elevations.
- the connection structure can have a plurality of punctiform through contacts or be designed as a bar-shaped connection structure and/or as a roughened connection structure. The contacting, in particular through intervia material, to the target mounting surface can be improved by the structured rear side.
- a part or the entire rear side of the component can be designed as a connection pad of the component, which is designed in particular to have a large surface area, which minimizes the risk of the component tilting when it is placed on the target mounting surface. Due to the presence of a plurality of through contacts, which are in particular implemented at certain points, it is possible for the structured rear side not to be interrupted over a large area, as a result of which the electrical connection between the component and the target mounting surface is optimized.
- the connection structure has vias, the vias being in the form of individual, one-piece contact columns.
- the vias are arranged in the openings of the insulation structure on the connection layer, with the vias projecting beyond the insulation structure along the vertical direction.
- the vias on the back of the component are freely accessible.
- a via is integral when the via is formed in one piece.
- the via does not have any individual, separate layers, which are arranged, for example, on top of one another or against one another.
- the via is made of a single layer educated .
- the via has no internal interface between two sub-layers of the same material or different materials.
- the via is not formed from two or more different layers.
- connection structure can have a continuous contact layer, with the through contacts being designed as integral components of the continuous contact layer.
- the back can have local depressions, the bottom areas of which are at least partially formed by surfaces of the vias.
- the through contacts and the contact layer can be designed in one piece.
- the vias and the contact layer are designed in one piece if they are formed from one piece, for example, and in particular if there are no internal interfaces between the contact layer and the vias.
- the vias and the contact layer are in particular formed from a single layer.
- the vias and the contact layer can have the same material composition or be formed from the same material. Seen locally, the vias can each be made in one piece.
- the through contacts protrude beyond the insulating structure.
- the vias can be freely accessible at least in regions on the rear side of the component.
- the vias can be components of a contact layer of the connection structure.
- the connection structure is exclusively for making electrical contact with the second semiconductor layer set up .
- the second semiconductor layer is preferably p-conductive, but can also be n-conductive.
- the rear side of the component can be free of a further connection structure, which is set up for making electrical contact with the first semiconductor layer.
- the first semiconductor layer can be n-conductive or p-conductive.
- the component has at least one contact point on its front side, which is provided for making electrical contact with the first semiconductor layer.
- the rear side has local depressions or local elevations, the surfaces of which are at least partially formed by surfaces of the vias. If the through contacts are spatially spaced apart from one another in lateral directions and are only electrically conductively connected to one another, for example via the connection layer, the through contacts form local elevations on the rear side of the component.
- the vias may have exposed surfaces that form parts of the surface of the back side of the device.
- Each of the vias can be arranged within one of the openings, for example within one of the contact openings of the insulating structure.
- the via arranged in the opening of the isolation structure can be spatially spaced apart from the isolation structure in lateral directions.
- the vias are spatially spaced apart from one another along the lateral direction.
- the vias are formed as individual contact columns of the component.
- the individual contact columns are electrically conductively connected to one another exclusively via the connection layer. If the contact columns are connected to one another in an electrically conductive manner exclusively via the connection layer, they would be electrically isolated from one another if the connection layer were not present.
- the insulation structure has openings on the connection layer, in which openings the vias are arranged.
- the vias project along the vertical direction, in particular beyond the insulating structure.
- the vias are spaced apart from the insulating structure, in particular by an intermediate area or by intermediate areas.
- One of the vias or each of the vias can be laterally completely surrounded by an intermediate area associated with it.
- the vias can be freely accessible on the rear side of the component.
- the vias only partially cover the connection layer, in particular.
- the vias cover at most 3%, 5%, 10%, 20%, 30%, 40%, 50%, 60% or at most 70% of a surface of the connection layer in plan view.
- the connection structure which is set up for making electrical contact with the second semiconductor layer, to be formed exclusively from the connection layer and the vias.
- the connection layer can have a plurality of have partial layers.
- the connection structure can be free of a further contact layer for lateral current expansion, the further contact layer being different from the connection layer and being in electrical contact with the vias.
- the connection structure can be free of a further connection pad, with the via or the plurality of vias being arranged in the vertical direction between the further connection pad and the connection layer.
- the rear side has local depressions, the bottom areas of which are at least partially formed by surfaces of the vias. However, it is not absolutely necessary for all depressions to have bottom surfaces that are at least partially formed from surfaces of the vias.
- the back it is possible, for example, for the back to have local indentations whose bottom surfaces are formed by surfaces of the insulating structure. Furthermore, it is possible for the rear side to have local indentations, the bottom surfaces of which are formed by surfaces of other components of the connection structure that do not extend through the insulating structure. Such local components of the connection structure are located, for example, on the insulation structure or only penetrate into the connection structure and not through it. For local indentations, in particular for all local indentations that have no overlaps with the insulation structure in a plan view, it is possible that their bottom surfaces at least are partially or completely formed by surfaces of the vias.
- connection structure has a coherent contact layer.
- the vias are designed in particular as integral components of the coherent contact layer.
- the contact layer and the vias form an integral unit.
- the contact layer and the vias can be formed from the same material. It is possible for the contact layer and the vias to be produced in a common process step.
- the continuous contact layer with the vias can completely cover the underlying connection layer. It is possible that at least 50%, 60%, 70%, 80%, 90% or at least 95%, for example between 50% and 98%, 50% and 95%, 60% and 95%, 70% and 95% or between 80% and 95% inclusive of the total area of the backside of the total area of the backside are formed by surfaces of the continuous contact layer.
- the rear side or mounting surface of the component can be formed exclusively by surfaces of the connection structure and the insulation structure, for example exclusively by surfaces of the contact layer, the vias and the insulation structure.
- the rear side is freely accessible and structured.
- the back has local depressions and local elevations on .
- the local elevations are part of the connection structure and are different from the vias.
- the elevations can be arranged on the insulation structure.
- the local elevations, which are different from the vias are located in particular outside the openings in the insulation structure.
- Both the local elevations and the local depressions can be embodied as components, for example as integral components of the connected contact layer of the connection structure.
- the local bumps and the vias have the same material composition.
- the back is structured, the back, in particular the electrically conductive surface of the back, can be roughened and/or have bar-shaped structures.
- the rear side is therefore not designed to be smooth or planar.
- the structured back has local depressions or local elevations with vertical depths or heights of at least 1 pm, 3 pm, 5 pm, 7 pm, 10 pm, 20 pm or at least 30 pm, approximately between 1 pm and 100 pm inclusive, between 1 pm and 50 pm inclusive, between 1 pm and 10 pm inclusive, between 1 pm and 5 pm inclusive or between 1 pm and 3 pm inclusive.
- the back has bar-shaped structures, bars arranged in parallel, for example with a bar width of 1-5 ⁇ m or 1-2 ⁇ m, can run over the entire back to edges, for example to the mesa edges of the component. If the back is roughened, can these have at least partially rough nanostructures. In this case, the local depressions or local elevations can be smaller than 1 ⁇ m, at least in some areas.
- the rear side is freely accessible and structured.
- the rear has local depressions and local elevations, the local elevations being components of the connection structure and different from the vias.
- the local elevations are bar-shaped, so that those local depressions located between two adjacent local elevations each form a channel-shaped structure on the rear side.
- the rear side of the component can thus have bar-shaped elevations and channel-shaped depressions arranged alternately next to one another.
- a bonding material such as that used to attach the component to the target mounting surface, can be easily and reliably forced out from under the component, particularly along the channel-shaped structures.
- the connection structure can form a large-area connection pad on the rear side of the component, as a result of which the risk of tilting when the component is placed on the target mounting surface is minimized.
- the structured surface can also bring about improved anchoring of the component when the component is placed on the target mounting surface. Furthermore, the high electric Conductivity and the high thermal conductivity between the component and a target substrate are ensured.
- the connection layer is radiation-impermeable, in particular radiation-reflecting.
- the connection layer can have a single layer or a layer sequence made up of several partial layers, for example a layer sequence made up of Pt, Ag, Ni and/or WTi partial layers.
- the connection layer can cover a large part of a surface of the semiconductor body, for example at least 40%, 50%, 60%, 70%, 80% or at least 90% of the surface of the semiconductor body. If the connection layer does not completely cover the surface of the semiconductor body, it is preferable for the connection layer to be arranged centrally on the semiconductor body in a plan view. If the connection layer is arranged in the middle or centrally on the semiconductor body, current injection into the semiconductor body can be optimally configured.
- the component has a radiation-transmissive substrate.
- the substrate can be a growth substrate, such as a sapphire substrate. It is also possible for the substrate to be different from a growth substrate.
- a front side of the component can be formed by the surface of the radiation-transmissive substrate. The front side is designed in particular as a radiation passage area of the component.
- the component can have a plurality of radiation passage surfaces.
- the component can be designed as a volume emitter and have side surfaces that are also designed as radiation passage surfaces.
- the insulation structure has a multilayer design.
- the insulation structure can have at least two different partial layers directly adjacent to one another with different material compositions, for example made of different oxide materials. At least one of the partial layers can be structured and have a rough structure or a bar structure.
- the rough structure or the bar structure is simulated on the back of the component.
- the insulation structure has at least one SiO2 layer or two SiO2 layers and at least one Al2O3 layer.
- the insulation structure is not necessarily limited to such materials. It is possible for the insulation structure to be formed as a layer sequence from a plurality of partial layers, with the adjacent partial layers being able to be formed from different materials, so that the insulation structure acts as a dielectric mirror, at least in the areas on the side of the connection layer.
- a method for producing a component, in particular a component described here, is specified.
- a semiconductor body In at least one embodiment of a method for producing a component, a semiconductor body is provided.
- the semiconductor body has, in particular, a first semiconductor layer, a second semiconductor layer and an active zone located in between.
- a connection layer is formed, which in particular is in direct electrical contact with the second semiconductor layer.
- An insulation structure is formed that is attached to both the second semiconductor layer and also adjoins the connection layer, in particular directly adjoins.
- the insulation structure can enclose the connection layer laterally and initially cover it completely in a plan view.
- the insulation structure is structured to expose the connection layer in certain areas, so that the insulation structure only partially covers the connection layer in a plan view.
- the vias are applied to the uncovered areas of the connection layer, with the vias being in electrical contact with the connection layer and extending through the insulation structure in the vertical direction, so that the component has a rear side as a mounting surface that is structured and is at least partially through Surfaces of the vias is formed.
- the vias are configured as individual, one-piece contact columns, are arranged in openings in the insulation structure on the connection layer, and protrude beyond the insulation structure in the vertical direction.
- the vias on the back of the component are freely accessible.
- the connection structure has a coherent contact layer, with the vias being designed as integral components of the coherent contact layer.
- the back has local depressions, the bottom areas of which are at least partially formed by surfaces of the vias.
- a temporary and removable layer is applied to the insulating structure. Openings are formed in the temporary and removable layer to form a mask layer.
- the temporary and removable layer can be a photostructurable lacquer layer.
- a negative resist or a positive resist can be used as the material of the resist layer.
- the negative resist can polymerize by exposure to light. For example, after a subsequent heating step, in particular after development, the exposed areas can remain.
- positive resists the already solidified resist is made soluble again, for example by exposure, and after development only those areas remain that were protected from exposure, for example by a mask.
- the temporary and removable layer is a resist layer formed from a photostructurable negative resist or from a photostructurable positive resist, the resist layer being photostructured to form the mask layer.
- contact openings are formed in the openings in the mask layer, which contact openings extend through the insulating structure to the connection layer.
- the vias are formed in the contact openings before the mask layer is removed.
- the mask layer which is formed in particular from the lacquer layer, is removed from the component, in particular completely removed.
- the contact openings are formed by means of an etching process, in which the connection layer serves as an etching stop layer.
- the insulation structure has a first partial layer and a second partial layer, with openings being formed in the second partial layer in order to create a roughened structure or a bar structure in the second partial layer transferred to .
- the rough structure or the bar structure is reproduced in particular below on the back of the component.
- the rough structure has a rough nanostructure or regions with rough nanostructures, at least in regions.
- the rough structure or the bar structure can be applied in particular by photolithography and dry etching, for example by RIE (reactive ion etching ) , be generated .
- the first partial layer and the second partial layer of the insulation structure have different material compositions, the first partial layer being more etch-resistant than the second partial layer.
- the openings in the second partial layer can be formed by means of an etching process, in which the first partial layer serves in particular as an etching stop layer.
- a temporary mask layer is used to form the openings in the second partial layer and is then removed.
- a third partial layer of the insulating structure is applied to the second structured partial layer and/or to the first partial layer, whereby the rough structure or the bar structure is reproduced on a surface of the third partial layer facing away from the semiconductor body.
- a further mask layer with openings is formed on the third partial layer, contact openings being formed in the openings in the further mask layer, which contact openings extend through the first partial layer of the insulating structure to the connection layer.
- a coherent contact layer of the connection structure is formed, through contacts being formed in the contact openings and as integral components of the coherent contact layer, and the rough structure or the bar structure being reproduced on a surface of the coherent contact layer that faces away from the semiconductor body.
- the rough structure or the bar structure of the connection structure is formed exclusively by flat application of the material or materials of the connection structure to the structured insulation structure. It is thus possible for the rough structure or the bar structure to be applied to the insulation structure in a structured manner without post-processing.
- the method described here is particularly suitable for the production of a component described here.
- the features described in connection with the component can therefore also used for the procedure and vice versa.
- FIGS. 1A and 1B schematic representations of a first exemplary embodiment of a component in a sectional view and in a plan view
- FIGS. 2A and 2B schematic representations of a second exemplary embodiment of a component in a sectional view and in a plan view
- FIGS. 3A and 3B schematic representations of a third exemplary embodiment of a component in a sectional view and in a plan view
- FIGS. 4A, 4B, 4C and 4D show schematic representations of some method steps for producing a component, in particular according to the first embodiment
- FIGS. 5A, 5B, 5C and 5D show schematic representations of some method steps for producing a component, in particular according to the second embodiment
- FIGS. 6A, 6B, 6C and 6D show schematic representations of some method steps for producing a component, in particular according to the third embodiment. Elements that are the same, of the same type or have the same effect are provided with the same reference symbols in the figures. The figures are each schematic representations and are therefore not necessarily true to scale. Rather, comparatively small elements and in particular layer thicknesses can be exaggerated for the sake of clarity.
- a component 10 according to a first embodiment is shown schematically in FIG. 1A.
- the component 10 has a semiconductor body 2 which has a first semiconductor layer 21 , a second semiconductor layer and an active zone 23 arranged between the semiconductor layers 21 and 22 .
- the first semiconductor layer 21 is, for example, n-conductive and the second semiconductor layer 22 is p-conductive, or vice versa.
- the semiconductor body 2 has a buffer layer 20 which is arranged between the first semiconductor layer 21 and a substrate 9 .
- the substrate 9 is a growth substrate.
- the component 10 has a front side 11 which is formed in particular by an exposed surface of the substrate 9 .
- the front side 11 is in particular a radiation passage area of the component 10 .
- the active zone 23 is set up to generate or to detect electromagnetic radiation, for example in the ultraviolet, infrared or in the visible spectral range.
- the active zone 23 is a pn junction zone.
- the semiconductor body can be based on a II IV or on a II-VI semiconductor compound material.
- the semiconductor body 2 is based on a II-IV compound semiconductor material if this contains at least one element from the main group III, such as Al, Ga, In, and one element from the main group V, such as N, P, ace , has .
- the semiconductor body 2 is based on GaN.
- II IV semiconductor compound material includes the group of binary, tertiary and quaternary compounds containing at least one element from main group III and at least one element from main group V, for example nitride and phosphide compound semiconductors a semiconductor body 2 based on the Group I I-VI compound semiconductor material.
- the component 10 has an insulation structure 3 .
- the insulation structure 3 has at least a first partial layer 31 and a second partial layer 32 .
- the first sub-layer 31 is, for example, a metal oxide layer , such as an Al2O3 layer.
- the second partial layer 32 is, for example, a TEOS layer 10, such as a SiO2 layer 10.
- TEOS is an abbreviation for tetraethylorthosilicate and is a liquid that is used in particular in semiconductor technology to produce oxide layers.
- a TEOS layer is an electrically insulating layer, TEOS being used to produce the TEOS layer.
- the insulation structure 3 can have more than two partial layers 31 and 32, approximately at least or exactly 3, 4 or five partial layers.
- the insulation structure 3, in particular the first partial layer 31, adjoins the second semiconductor layer 22 in some areas. It is possible for the first partial layer 31 to directly adjoin the second semiconductor layer 22 in some areas.
- the component 10 has a contact structure 4 .
- the contact structure 4 for electrical Contacting the second semiconductor layer 22 set up can have a further contact structure which is set up for making electrical contact with the first semiconductor layer 21 .
- the further contact structure is not shown in FIG. 1A.
- the contact structure 4 has a connection layer 42 which is in electrical contact with the second semiconductor layer 22 .
- the connection layer 42 directly adjoins the second semiconductor layer 22 .
- the connection layer 42 can be formed from one or more of the following materials, namely from Pt , Ag, Ni , WTi , ZnO . It is possible for the connection layer 42 to be a layer sequence composed of a plurality of partial layers made of different materials. In lateral directions, the connection layer 42 is surrounded by the insulating structure 3, in particular completely surrounded. In a plan view, the insulation structure 3 covers the connection layer 42 in regions.
- the insulation structure 3 has openings on the connection layer 42 , the bottom surfaces of which can be formed by surfaces of the connection layer 42 . It is also possible for the connection layer 42 to the second semiconductor layer 22 to be formed from a transparent, electrically conductive oxide, for example from ITO.
- the contact structure 4 has a plurality of vias 420 which are in electrical contact with the connection layer 42 .
- the vias 420 are arranged in particular in the openings of the insulation structure 3 .
- Vias 420 extend in particular through insulating structure 3 along the vertical direction and protrude beyond insulating structure 3 .
- the vias 420 are spatially spaced from each other in the lateral direction.
- the vias 420 are thus designed as individual contact columns which are arranged on the connection layer 22 in a plan view, are in electrical contact with it and are formed as local elevations 52 on a rear side 12 of the component 10 .
- each of the through contacts 420 can be arranged in one of the openings in the insulating structure 3, the through contact 420 being spatially spaced apart from the insulating structure 3 in lateral directions.
- FIG. 1A there is therefore an intermediate region 8 between the insulating structure 3 and the via 420.
- the intermediate region 8 can be filled with a gaseous medium, such as air.
- the intermediate area 8 it is also possible for the intermediate area 8 to be filled with an electrically conductive material that differs in particular from a material of the insulating structure 3 .
- the via 420 therefore has a smaller diameter than a diameter of the opening in the insulating structure 3 associated with it. Deviating from this, however, it is possible for the via 420 to be directly adjacent to the insulating structure 3 . In this case, the through contact 420 and the opening in the insulating structure 3 associated with it can have the same diameter.
- the rear side 12 of the component 10 is formed in some areas by surfaces of the insulating structure 3 and the vias 420 .
- the rear side 12 of the component 10 is shown schematically in FIG. 1B.
- the back 12 has a plurality of local elevations 52, which are formed in particular by the vias 420, the vias 420 each in one of the Openings of the insulation structure 3 are arranged and protrude over the insulation structure 3 along the vertical direction.
- the rear side 12 is structured, the structuring of the rear side 12 being mainly defined by the distribution of the vias 420 .
- the vias 420 are preferably evenly distributed on the connection layer 42 or distributed on the back 12 .
- the insulation structure 3 On the side of the connection layer 42 , the insulation structure 3 has frame-shaped areas that do not overlap with the connection layer 42 in a plan view. These frame-shaped areas of the insulating structure 3 can thus form a stop 7 , in particular a frame-shaped stop 7 , or multiple stops 7 of the component 10 .
- the exemplary embodiment shown in FIG. 2A essentially corresponds to the exemplary embodiment of a component 10 shown in FIG. 1A.
- the insulation structure 3 has a roughened structure, the roughened structure of the insulation structure 3 on the rear side 12 of the component 10 being reproduced by a roughened surface of the contact structure 4 .
- the contact structure 4 is designed to be continuous.
- the contact structure 4 has a contact layer 40 which mechanically and electrically connects the vias 420 , in particular all vias 420 , to one another.
- the contact layer 40 and the vias 420 can be formed from the same materials. In particular, the contact layer 40 and the vias 420 during a common process step on the insulation structure 3 or on the semiconductor body 2 are formed.
- the insulating structure 3 has a further partial layer 33 in addition to the first and second partial layers 31 and 32 .
- the second partial layer 32 and the further third partial layer 33 can be formed from the same material or from different materials.
- the further partial layer 33 is arranged in the vertical direction between the second partial layer 32 and the contact layer 40 .
- the further third partial layer 33 and the contact layer 40 have an identical or a similar structuring pattern.
- the structuring pattern of the contact layer 40 is predetermined by the structuring pattern of the further partial layer 33 .
- the back 12 has a plurality of local depressions 51 and local elevations 52 . Some of the local depressions 51 have bottom surfaces formed by surfaces of the vias 420 . Further local depressions 51 have bottom areas which are formed by surfaces of the contact layer 40 . These further local depressions 51 have smaller vertical depths than the local depressions 51 whose bottom areas are formed by surfaces of the vias 420 .
- the vias 420 are located in the respective openings of the insulating structure 3 in a plan view. In particular, the vias 420 directly adjoin the insulating structure 3 . The vias 420 and the respective openings in the insulating structure 3 can thus have the same diameter in pairs. Within the Openings border the vias 420 in particular directly on the partial layers 31 , 32 and 33 . Outside the openings, the contact layer 40 is directly adjacent to the insulating structure 3, but only to the further partial layer 33 of the insulating structure 3. Vias 420 extend along the vertical direction through sublayers 31 , 32 and 33 of insulating structure 3 and protrude beyond insulating structure 3 .
- the component 10 is shown schematically in a plan view of the rear side 12 .
- the rear side 12 is structured, the structuring of the rear side 12 being essentially defined by the arrangement of the vias 420 and the structuring of the contact layer 40 .
- the rear side 12 has exposed, in particular frame-shaped, areas of the insulating structure 3 which are not covered by the contact structure 4 in a plan view.
- the back side 12 has a stop 7 formed by a widespread exposed area of the insulation structure 3 .
- the exemplary embodiment shown in FIG. 3A essentially corresponds to the exemplary embodiment of a component 10 shown in FIG. 2A.
- the rear side 12 of the component 10 does not have a rough structure but a bar structure, which is shown schematically, for example, in FIG. 3B.
- the second partial layer 32 and/or the further partial layer 33 of the insulation structure 3 can also have a bar structure which, in comparison to the bar structure on the rear side 12, has approximately the same or a similar structuring pattern.
- Both the vias 420 and the respective openings in the insulating structure 3 can be designed in the form of strips.
- the strip-shaped vias 420 are located below the strip-shaped channel-shaped indentations 510 such as shown in FIGS. 3A and 3B.
- the vias 420 in particular directly adjoin the insulating structure 3 .
- the vias 420 and the respective openings in the insulating structure 3 can thus have the same width and/or length in pairs.
- the component 10 has local indentations 51 which are embodied as channel-shaped indentations 510 in FIGS. 3A and 3B.
- the channel-shaped depressions 510 whose bottom areas are formed by surfaces of the vias 420 generally have a greater depth than the channel-shaped depressions 510 whose bottom areas are formed by surfaces of the contact layer 40 .
- the channel-shaped indentations 510 may extend from a first edge of the back 12 to a second edge of the back 12 opposite the first edge. Such channel-shaped depressions 510 are shown schematically in FIG. 3B. If a component 10 with such channel-shaped indentations 510 is attached to a target surface by means of a connecting material, excess connecting material can be guided outwards along the channel-shaped indentations 510 in a simple manner.
- the further partial layer 33 of the insulating structure 3 is designed in such a way that it encapsulates the first partial layer 31 and/or the second partial layer 32 at least in the areas of the openings.
- the side walls of the openings are in particular formed exclusively by surfaces of the further partial layer 33 .
- the vias 420 in particular exclusively directly adjoin the further partial layer 33 of the insulating structure 3 .
- the contact layer 40 is exclusively adjacent to the further partial layer 33 . In other words, there is no direct physical contact between sublayers 31 and 32 and contact layer 40 or vias 420 .
- the rear side 12 of the component 10 according to FIG. 3B has two stops 7 which are arranged on two opposite edges of the rear side 12 and run parallel to the channel-shaped depressions 510 .
- the local elevations 52 form the bars of the bar structure on the rear side 12 of the component 10 .
- Figures 4A, 4B, 4G and 4D show some process steps for the production of a component 10, which is shown in particular in Figures 1A and 1B schematically.
- a semiconductor body 2 is provided on a substrate 9 .
- the semiconductor body 2 with a buffer layer 20, a first semiconductor layer 21, a active zone 23 and a second semiconductor layer 22 can be grown epitaxially in the order mentioned in layers on the substrate 9 , which is in particular a growth substrate.
- connection layer 42 of a contact structure 4 is formed on the second semiconductor layer 22 in order to make electrical contact with the second semiconductor layer 22 .
- a first photolithography level can be formed using photoresist, which defines the position of the connection layer 42 .
- the connection layer 42 can be designed as a single layer or as a layer sequence.
- the connection layer 42 is sputtered on the second semiconductor layer 22 .
- the connection layer 42 can optionally be structured by means of a lift-off process.
- the second semiconductor layer 22 and the connection layer 42 can be encapsulated, for example laterally, by an insulating structure 3 .
- a first partial layer 31, for example an Al2O3 layer, and a second partial layer 32, for example an SiO2 layer, of the insulating structure 3 are formed by applying suitable insulating materials to the semiconductor body 2 and to the connection layer 42.
- the insulation structure 3 can be formed by a full-area deposition process.
- the A12O3 layer is formed by a blanket deposition process such as atomic layer deposition (ALD).
- the SiO2 layer can be formed using TEOS.
- the insulation structure 3, in particular the first partial layer 31 or the second partial layer 32 can be coated in plan view Cover the semiconductor body 3 and/or the connection layer 42 completely.
- a second photolithography level is formed, for example, using a photostructurable material, such as negative lacquer.
- a mask layer 62 is formed on the insulating structure 3, the mask layer 62 defining the positions of the contact openings, also known as vias.
- the mask layer 62 is a temporary mask layer, in particular a lacquer layer with openings.
- the contact openings are formed through the insulating structure 3 by means of an etching process, for example by means of a dry etching process, for example RIE, for the purpose of exposing the connection layer 42 in certain areas.
- the connection layer 42 can serve as an etch stop layer in the etching process.
- the vias 420 are formed within the contact openings in a plan view.
- a contact layer 40 can be formed outside the contact openings.
- the vias 420 and the contact layer 40 can be formed in a common process step, such as by sputter coating.
- the contact layer 40 can have local depressions 51 and local elevations 52 .
- the vias 420 and/or the contact layer 40 can be formed from an electrically conductive material, for example a metal such as Ti, Pt, Au or a transparent electrically conductive oxide such as ITO. It is also possible for the vias 420 and/or the contact layer 40 to be formed from a layer sequence made from a plurality of such materials.
- the mask layer 62 is removed.
- the insulation structure 3 is uncovered in certain areas.
- the contact layer 40 is also removed, so that the vias 420 are formed as individual contact columns that are spatially spaced apart from one another in lateral directions in the contact openings of the insulating structure 3 .
- the exemplary embodiment of a component 10 illustrated in FIG. 4D corresponds to the component 10 illustrated in FIG. 1A. Deviating from FIG. 4D, however, it is also conceivable that the contact layer 40 is still present even after the removal of the mask layer 62, so that the vias 420 are electrically conductively connected to one another via the contact layer 40.
- the method described in Figures 4A to 4D for producing a component 10 or a plurality of components 10 is characterized in particular by the fact that the photolithography is used to define the contact openings and immediately to structure the through contacts 420 and the rear side of the component 10, so that the Vias 420 are automatically optimally adjusted in the areas of the contact openings, as a result of which undefined topography effects due to possible misalignment of two photo planes can be avoided.
- the component 10 produced by this method has a plurality of vias 420 arranged in a punctiform manner. It can therefore prove to be advantageous if the component 10 connects to the target mounting surface only at certain points. This allows the intervia material , i . e. the connecting material , through which contact gaps are pushed out laterally . A mechanical and electrical The connection between the component 10 and a target substrate with the target mounting area can thus be made in a simplified and reliable manner. If the component 10 rests on a plurality of vias 420 , the risk of tilting when the component 10 is placed on the target substrate is prevented. The electric current would flow vertically directly to the connection layer 42 via the vias 420 .
- the component 10 is in particular free of a contact layer for lateral current widening.
- the component 10 is better fixed when it is placed on the target substrate than a component with a planar mounting surface due to the through contacts 420 arranged in a punctiform manner and protruding beyond the insulating structure 3 .
- FIGS. 5A, 5B, 5C and 5D show a number of method steps for producing a component 10, which is illustrated schematically in particular in FIGS. 2A and 2B, the exemplary embodiment of a method step illustrated in FIG. 5A corresponding to the method step illustrated in FIG. 4A.
- a second photolithography level is formed, for example, with a photostructurable material, for example with positive resist.
- a mask layer 61 is formed on the insulating structure 3, the mask layer 61 defining rough structures.
- the rough structures can be nanostructures.
- the mask layer 61 is a temporary mask layer, in particular a lacquer layer with openings.
- the roughened structures are transferred into the insulating structure 3 , in particular into the second partial layer 32 of the insulating structure 3 , by means of an etching process, for example RIE. In this case, material of the second partial layer 32 in the areas of Openings of the mask layer 61 are removed.
- the roughened structures in particular in the form of openings, can be formed in the second partial layer 32 .
- the other first partial layer 31 can serve as an etching stop layer in the etching process.
- the first partial layer 31 is preferably formed from a material that is more resistant to etching than a material of the second partial layer 32 .
- the first sub-layer 31 is an Al2O3 layer.
- the second partial layer 32 can be an SiO2 layer.
- a further third partial layer 33 is first applied, preferably over the entire surface, to the partial layers 31 and 32 of the insulating structure 3, for example by means of a coating method using TEOS.
- the further third partial layer 33 can be an SiO2 layer.
- the further third partial layer 33 can completely cover the partial layers 31 and/or 32 .
- the first partial layer 31 is encapsulated in the openings of the second partial layer 32 by the further third partial layer 33 .
- the further third partial layer 33 can directly adjoin both the first partial layer 31 and the second partial layer 32 .
- a third photolithography level which defines the positions of the contact openings, is formed, for example, with a photostructurable material, such as positive resist.
- a mask layer 62 is formed on the insulating structure 3 .
- the mask layer 62 has openings in which contact openings through the insulating structure 3, in this Case formed through the sub-layers 31 and 33 .
- the contact openings are formed through the insulating structure 3 in order to uncover the connection layer 42 in some areas, in particular by means of an etching process, for example by means of a dry etching process, for example RIE.
- the connection layer 42 can serve as an etch stop layer in the etching process.
- the mask layer 62 can then be removed.
- the mask layer 62 is removed.
- the further third partial layer 33 of the insulating structure 3 is uncovered. Outside the contact openings, the roughened structures of the partial layer 32 are reproduced on exposed surfaces of the further partial layer 33 .
- the vias 420 are formed in the contact openings and the contact layer 40 is formed outside the contact openings according to FIG. 5D. Since the mask layer 62 has been completely removed in FIG. 5D, in contrast to FIG. The exemplary embodiment of a component 10 illustrated in FIG. 5D corresponds to the component 10 illustrated in FIG. 2A.
- the method for producing a component 10 or a plurality of components 10 described in FIGS. transferred to the back 12 will .
- the rear side 12, which serves as a mounting surface of the component 10 is therefore designed to be rough at least in regions, as a result of which the contacting through the intervia material to the target substrate is improved.
- the electrical connection surface can thus be designed with a large surface area with respect to the rear side 12, as a result of which the risk of tilting when the component 10 is placed on the target substrate is minimized.
- the rough mounting surface is not interrupted over a large area, and at the same time the electrical connection is optimized.
- FIGS. 6A, 6B, 6C and 6D show a number of method steps for producing a component 10, which is illustrated schematically in particular in FIGS. 3A and 3B, the exemplary embodiment of a method step illustrated in FIG. 6A corresponding to the method step illustrated in FIG. 4A.
- the exemplary embodiment of a method step shown in FIG. 6B essentially corresponds to the method step shown in FIG. 5B.
- a mask layer 61 is formed on the insulating structure 3, the mask layer 61 not defining rough structures but rather bar structures.
- the bar structures are transferred into the insulating structure 3 , in particular into the second partial layer 32 of the insulating structure 3 , by means of an etching process, for example RIE.
- material of the partial layer 32 can be removed in the areas of the openings of the mask layer 61 .
- bar structures, in particular in the form of strip-shaped openings can be formed in the partial layer 32 will .
- the other first partial layer 31 can serve as an etching stop layer in the etching process.
- the partial layer 31 is preferably formed from a material that is more resistant to etching than a material of the further partial layer 32 .
- sub-layer 31 is an Al2O3 layer.
- the partial layer 32 can be an SiO2 layer.
- the further partial layer 33 can be an SiO2 layer.
- the further sub-layer 33 completely covers the sub-layers 31 and/or 32 and thus encapsulates the sub-layers
- the further third sub-layer 33 borders both on the first sub-layer 31 and on the second sub-layer
- a third photolithographic level is formed, in particular with a photostructurable material, for example with positive resist, which defines the positions of the contact openings.
- a mask layer 62 is formed on the insulating structure 3 .
- the mask layer 62 has openings in which contact openings are formed through the insulating structure 3 , in this case only through the third partial layer 33 .
- the contact openings are opened through the insulating structure 3 in particular by means of an etching process, for example by means of a dry etching process, such as RIE regional exposure of the connection layer 42 is formed.
- the connection layer 42 can serve as an etch stop layer in the etching process.
- the mask layer 62 is removed.
- the third partial layer 33 of the insulating structure 3 is uncovered.
- the bar structures of the partial layer 32 are reproduced on exposed surfaces of the further partial layer 33 .
- the vias 420 are formed in the contact openings and the contact layer 40 is formed outside the contact openings according to FIG. 6D.
- the beam structure of the second partial layer 32 on the rear side 12 of the component 10 is reproduced in particular by applying the material of the contact layer 40 over the whole area to the exposed surfaces of the third partial layer 33 .
- the exemplary embodiment of a component 10 illustrated in FIG. 6D corresponds to the component 10 illustrated in FIG. 3A.
- the method for producing a component 10 or a plurality of components 10 described in FIGS. be transferred to the back 12 .
- the rear side 12, which serves as the mounting surface of the component 10 thus has bar-shaped structures, which simplifies and improves contacting through the intervia material to the target substrate, since the connecting material is more easily pushed outwards when the component 10 is attached to the target substrate can . This increases the area and reliability of the electrical connection optimized.
- the bar-shaped structure acts as a kind of anchor structure and reduces the risk of displacement.
- Additional process steps can be used in all exemplary embodiments of a method for producing a component 10 .
- Such further process steps include, for example, steps for defining a support structure, applying a sacrificial release layer, connecting to a temporary carrier, laser lift-off (LLO), n-contact coating, mesa etching, passivation, release etching and pick-and -Place on a target mounting surface.
- LLO laser lift-off
- the substrate 9 is removed from the semiconductor body 2.
- the component 10 is free of a substrate 9, in particular free of a growth substrate.
- the buffer layer 20 exposed by the removal of the substrate 9 can be roughened or are structured, so that the ef fi ciency of the component 10 is improved with respect to the light extraction or the light in-coupling.
- the invention is not limited to the description of the invention based on the exemplary embodiments. Rather, the invention comprises each new feature and each combination of features, which in particular includes each combination of features in the claims, even if this Feature or this combination itself is not explicitly stated in the claims or embodiments.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202180050836.0A CN115956302A (zh) | 2020-09-08 | 2021-08-06 | 带有改进的连接结构的构件和用于制造构件的方法 |
US18/044,210 US20230317900A1 (en) | 2020-09-08 | 2021-08-06 | Component with improved connection structure and method for producing a component |
JP2023515404A JP2023539920A (ja) | 2020-09-08 | 2021-08-06 | 改善された接続構造体を有する素子および素子を製造する方法 |
KR1020237006071A KR20230041782A (ko) | 2020-09-08 | 2021-08-06 | 개선된 접속 구조를 구비한 컴포넌트 및 컴포넌트를 제조하기 위한 방법 |
EP21755785.9A EP4211728A1 (de) | 2020-09-08 | 2021-08-06 | Bauelement mit verbesserter anschlussstruktur und verfahren zur herstellung eines bauelements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102020123386.8 | 2020-09-08 | ||
DE102020123386.8A DE102020123386A1 (de) | 2020-09-08 | 2020-09-08 | Bauelement mit verbesserter anschlussstruktur und verfahren zur herstellung eines bauelements |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022053236A1 true WO2022053236A1 (de) | 2022-03-17 |
Family
ID=77367442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2021/072058 WO2022053236A1 (de) | 2020-09-08 | 2021-08-06 | Bauelement mit verbesserter anschlussstruktur und verfahren zur herstellung eines bauelements |
Country Status (7)
Country | Link |
---|---|
US (1) | US20230317900A1 (de) |
EP (1) | EP4211728A1 (de) |
JP (1) | JP2023539920A (de) |
KR (1) | KR20230041782A (de) |
CN (1) | CN115956302A (de) |
DE (1) | DE102020123386A1 (de) |
WO (1) | WO2022053236A1 (de) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015112538A1 (de) * | 2015-07-30 | 2017-02-02 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und ein Verfahren zur Herstellung eines optoelektronischen Bauelements |
DE102015115722A1 (de) * | 2015-09-17 | 2017-03-23 | Osram Opto Semiconductors Gmbh | Träger für ein Bauelement, Bauelement und Verfahren zur Herstellung eines Trägers oder eines Bauelements |
DE102016113193A1 (de) * | 2016-07-18 | 2018-01-18 | Osram Opto Semiconductors Gmbh | Bauteil mit geometrisch angepasster Kontaktstruktur und dessen Herstellungsverfahren |
WO2018122103A1 (de) * | 2016-12-29 | 2018-07-05 | Osram Opto Semiconductors Gmbh | Halbleiterlaserdiode |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI318013B (en) | 2006-09-05 | 2009-12-01 | Epistar Corp | A light emitting device and the manufacture method thereof |
KR20160027875A (ko) | 2014-08-28 | 2016-03-10 | 서울바이오시스 주식회사 | 발광소자 |
-
2020
- 2020-09-08 DE DE102020123386.8A patent/DE102020123386A1/de active Pending
-
2021
- 2021-08-06 CN CN202180050836.0A patent/CN115956302A/zh active Pending
- 2021-08-06 WO PCT/EP2021/072058 patent/WO2022053236A1/de unknown
- 2021-08-06 EP EP21755785.9A patent/EP4211728A1/de active Pending
- 2021-08-06 JP JP2023515404A patent/JP2023539920A/ja active Pending
- 2021-08-06 US US18/044,210 patent/US20230317900A1/en active Pending
- 2021-08-06 KR KR1020237006071A patent/KR20230041782A/ko unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015112538A1 (de) * | 2015-07-30 | 2017-02-02 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und ein Verfahren zur Herstellung eines optoelektronischen Bauelements |
DE102015115722A1 (de) * | 2015-09-17 | 2017-03-23 | Osram Opto Semiconductors Gmbh | Träger für ein Bauelement, Bauelement und Verfahren zur Herstellung eines Trägers oder eines Bauelements |
DE102016113193A1 (de) * | 2016-07-18 | 2018-01-18 | Osram Opto Semiconductors Gmbh | Bauteil mit geometrisch angepasster Kontaktstruktur und dessen Herstellungsverfahren |
WO2018122103A1 (de) * | 2016-12-29 | 2018-07-05 | Osram Opto Semiconductors Gmbh | Halbleiterlaserdiode |
Also Published As
Publication number | Publication date |
---|---|
EP4211728A1 (de) | 2023-07-19 |
JP2023539920A (ja) | 2023-09-20 |
DE102020123386A1 (de) | 2022-03-10 |
CN115956302A (zh) | 2023-04-11 |
KR20230041782A (ko) | 2023-03-24 |
US20230317900A1 (en) | 2023-10-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102015119353B4 (de) | Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils | |
DE3245064C2 (de) | ||
DE19832852C2 (de) | Halbleiter-Lichtemissionsvorrichtung mit Elektroden-Drahtbondpads | |
EP1709694B1 (de) | Dünnfilm-led mit einer stromaufweitungsstruktur | |
EP2013917A1 (de) | Strahlungsemittierender halbleiterkörper mit trägersubstrat und verfahren zur herstellung eines solchen | |
DE4236609A1 (de) | Verfahren zur Erzeugung einer Struktur in der Oberfläche eines Substrats | |
DE102007022947A1 (de) | Optoelektronischer Halbleiterkörper und Verfahren zur Herstellung eines solchen | |
DE102007032555A1 (de) | Halbleiterchip und Verfahren zur Herstellung eines Halbleiterchips | |
DE3043289C2 (de) | ||
DE3933965C2 (de) | ||
DE10244986B4 (de) | Strahlungsemittierendes Halbleiterbauelement | |
DE102009037319A1 (de) | Verfahren zur Herstellung einer Licht emittierenden Halbleitervorrichtung und Licht emittierende Halbleitervorrichtung | |
DE2615438A1 (de) | Verfahren zur herstellung von schaltungskomponenten integrierter schaltungen in einem siliziumsubstrat | |
DE2556038A1 (de) | Verfahren zur herstellung von feldeffekttransistoren fuer sehr hohe frequenzen nach der technik integrierter schaltungen | |
WO2018114483A1 (de) | Optoelektronischer halbleiterchip und verfahren zur herstellung eines optoelektronischen halbleiterchips | |
DE10026262A1 (de) | Vcsel | |
WO2022053236A1 (de) | Bauelement mit verbesserter anschlussstruktur und verfahren zur herstellung eines bauelements | |
DE19905526C2 (de) | LED-Herstellverfahren | |
WO2020035419A1 (de) | Optoelektronisches halbleiterbauelement mit kontaktelementen und dessen herstellungsverfahren | |
WO2002059981A2 (de) | Herstellen elektrischer verbindungen in substratöffnungen von schaltungseinheiten mittels schräg gerichteter abscheidung leitfähiger schichten | |
DE102008038852A1 (de) | Verfahren zur Herstellung eines optoelektronischen Bauelementes und optoelektronisches Bauelement | |
WO2003030221A2 (de) | Verfahren zur herstellung eines halbleiterbauelements auf der basis eines nitrid-verbindungshalbleiters | |
WO2021028185A1 (de) | Bauelement mit reduzierter absorption und verfahren zur herstellung eines bauelements | |
DE10261364B4 (de) | Verfahren zur Herstellung einer temperbarer Mehrschichtkontaktbeschichtung, insbesondere einer temperbaren Mehrschichtkontaktmetallisierung | |
WO2020070022A1 (de) | BAUELEMENT MIT VERGRÖßERTER AKTIVER ZONE UND VERFAHREN ZUR HERSTELLUNG |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21755785 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 20237006071 Country of ref document: KR Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 2023515404 Country of ref document: JP Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2021755785 Country of ref document: EP Effective date: 20230411 |