WO2022052204A1 - 显示基板及其制备方法和显示面板 - Google Patents

显示基板及其制备方法和显示面板 Download PDF

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Publication number
WO2022052204A1
WO2022052204A1 PCT/CN2020/121239 CN2020121239W WO2022052204A1 WO 2022052204 A1 WO2022052204 A1 WO 2022052204A1 CN 2020121239 W CN2020121239 W CN 2020121239W WO 2022052204 A1 WO2022052204 A1 WO 2022052204A1
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Prior art keywords
opening
sub
display area
display
openings
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PCT/CN2020/121239
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English (en)
French (fr)
Inventor
张元其
张毅
嵇凤丽
张顺
文平
宋永杰
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002319.1A priority Critical patent/CN114762124A/zh
Priority to US17/432,549 priority patent/US20220344420A1/en
Publication of WO2022052204A1 publication Critical patent/WO2022052204A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the embodiments of the present disclosure belong to the field of display technology, and in particular relate to a display substrate, a method for manufacturing the same, and a display panel.
  • OLED display panels prepared by Organic Light-Emitting Display (OLED) technology have become the mainstream development direction in the field of display technology due to their advantages of self-luminescence, high brightness, good picture quality, and low energy consumption. For this newly developed technology, more designs can be done to meet people's needs. Among them, the technology of punching holes in the screen display area is one direction of the current screen development.
  • Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display panel.
  • a display substrate including:
  • a pixel defining layer disposed on the substrate
  • the display substrate further includes a display area, a non-display area and a light-transmitting area, the display area and the non-display area at least partially surrounding the light-transmitting area;
  • the pixel defining layer extends from the display area to the non-display area
  • a first opening is formed in the pixel defining layer, and the first opening includes a plurality of first sub-openings and a plurality of second sub-openings; the plurality of first sub-openings are distributed in the display area, and the plurality of A plurality of second sub-openings are distributed in the non-display area; and the second sub-openings are closer to the light-transmitting area than the first sub-openings.
  • the first sub-opening is provided with a first electrode layer and a light-emitting functional layer
  • the substrate includes a pixel circuit, the pixel circuit includes a driving transistor, and the driving transistor is electrically connected to the first electrode layer;
  • the first electrode layer and the light-emitting functional layer are stacked in a direction away from the substrate;
  • the light-emitting functional layer is disposed in the second sub-opening
  • the display substrate further includes a second electrode layer, the second electrode layer is disposed on the side of the pixel defining layer away from the substrate, and the second electrode layer covers the first sub-opening and the the second child opens;
  • the orthographic projection of the driving transistor on the substrate does not overlap with the orthographic projection of the second sub-opening on the substrate.
  • the display substrate further includes a signal line, the signal line is disposed on a side of the pixel defining layer close to the substrate, and the signal line extends from the display area to the non-display area area, and the signal line includes an arc portion in the non-display area;
  • the arc portion is disposed at least partially around the light-transmitting region, and the arc portion at least partially overlaps the orthographic projection of the second sub-opening on the substrate.
  • the signal lines include data lines.
  • the width of the distribution area of the second sub-openings ranges from 2 to 8 times the width of the second sub-openings along the radial direction thereof.
  • the display substrate further includes a dam, the dam is located in the non-display area and at least partially surrounds the light-transmitting area;
  • the cofferdam surrounds the edge of the light transmission area, and the second sub-openings are distributed around the cofferdam on a side of the cofferdam away from the light transmission area;
  • the shortest separation distance between the cofferdam and the distribution area of the second sub-opening is greater than 0 and less than 300 microns.
  • a touch film layer is further included, and the touch film layer is disposed on a side of the second electrode layer away from the substrate;
  • the touch film layer includes touch electrodes; the touch electrodes are grid-shaped; the pixel defining layer is grid-shaped; the orthographic projection of the touch electrodes on the substrate and the pixel defining layer The orthographic projection regions on the substrates at least partially overlap.
  • the orthographic projection of the touch electrodes on the substrate and the orthographic projection of the pixel defining layer between the second sub-openings on the substrate at least partially overlap.
  • the size difference between the first sub-opening and the second sub-opening is less than a set threshold.
  • the second sub-opening includes a first shape opening, a second shape opening, and a third shape opening
  • the first shape opening, the second shape opening and the third shape opening are different in shape and size
  • Two of the first-shaped openings, one of the second-shaped openings, and one of the third-shaped openings form an opening period; a plurality of the opening periods are distributed in the non-display area.
  • the distance between the two first-shaped openings ranges from 6 to 27 ⁇ m
  • the distance between the first shape opening and the second shape opening ranges from 15 to 30 ⁇ m
  • the distance between the openings in the second shape and the openings in the third shape ranges from 15 to 30 ⁇ m;
  • the distance between the first shape opening and the third shape opening ranges from 50 to 80 ⁇ m.
  • the distance between the first shape opening and the third shape opening is 1.5-2.5 times the distance between the first shape opening and the second shape opening
  • the distance between the first shape opening and the second shape opening is 0.8-1.2 times the distance between the second shape opening and the third shape opening;
  • the distance between the two first shape openings is 0.6-1 times the distance between the first shape opening and the second shape opening.
  • the distribution uniformity of the first sub-opening and the second sub-opening is the same.
  • the display area surrounds the periphery of the non-display area
  • the non-display area is located at a corner of the display area
  • the non-display area is located at one edge of the display area.
  • a flat layer is further included, the flat layer is disposed on a side of the pixel defining layer close to the substrate;
  • the substrate further includes a base, the pixel circuit is disposed on the base, a via hole is opened in the flat layer, and the first electrode layer is connected to the driving transistor in the pixel circuit through the via hole .
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned display substrate.
  • an embodiment of the present disclosure further provides a method for fabricating a display substrate, including:
  • the display substrate further includes a display area, a non-display area and a light-transmitting area, the display area and the non-display area at least partially surround the light-transmitting area; the pixel defining layer extends from the display area to the light-transmitting area. non-display area;
  • Preparing the pixel defining layer includes: forming a pattern of the pixel defining layer, and opening a first opening in the pixel defining layer;
  • the first opening includes a plurality of first sub-openings and a plurality of second sub-openings; the plurality of first sub-openings are distributed in the display area, and the plurality of second sub-openings are distributed in the non-display area ; and the second sub-opening is closer to the light-transmitting area than the first sub-opening.
  • the pattern of the pixel defining layer and the pattern of the first opening are formed through a single patterning process.
  • FIG. 1 is a partial structural cross-sectional view of an opening in a pixel defining layer in a display region of an OLED display panel in the disclosed technology
  • FIG. 2 is a top view of the structure of punching holes in the display area of an OLED screen in the disclosed technology
  • 3 is a top view of the arrangement structure of the touch electrode pattern when the OLED screen display area is punched in the disclosed technology
  • FIG. 4 is a top view of the structure in which the touch electrode pattern is expanded and distributed outside the display area when the display area of the OLED screen is punched in the disclosed technology;
  • FIG. 5 is a top view of the structure of a display substrate according to an embodiment of the disclosure.
  • FIG. 6 is a structural cross-sectional view of the substrate shown in FIG. 5 along the AA section line;
  • FIG. 7 is a partial structural cross-sectional view of a display area of a display substrate according to an embodiment of the disclosure.
  • FIG. 8 is a schematic cross-sectional view of a partial structure of a display substrate from a display area to a non-display area in an embodiment of the disclosure
  • FIG. 9 is a schematic top view showing the structure of the arc portion of the signal line in the substrate according to an embodiment of the present disclosure.
  • FIG. 10 is an enlarged schematic top view showing the structure of part C of the substrate shown in FIG. 5;
  • FIG. 11 is a schematic cross-sectional view showing the structure of an isolation column in a substrate according to an embodiment of the disclosure.
  • FIG. 12 is a top view of the structure of a display substrate provided with a touch film layer according to an embodiment of the disclosure
  • FIG. 13 is a structural cross-sectional view of the substrate shown in FIG. 7 along the BB section line;
  • FIG. 14 is another schematic diagram of the distribution of the display area and the non-display area on the display substrate according to the embodiment of the disclosure.
  • 15 is another schematic diagram of the distribution of the display area and the non-display area on the display substrate according to the embodiment of the disclosure.
  • 16 is another schematic diagram of the distribution of the display area and the non-display area on the display substrate according to the embodiment of the disclosure.
  • 17 is a top view of the structure of the second sub-opening in the non-display area of the display substrate according to another embodiment of the disclosure.
  • FIG. 18 is an enlarged schematic top view showing another structure of part C of the substrate shown in FIG. 5 .
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Accordingly, the regions illustrated in the figures are of schematic nature and the shapes of the regions shown in the figures are illustrative of the specific shapes of the regions and are not intended to be limiting.
  • OLED display panel of organic light-emitting diode display (OLED) technology has become the mainstream development direction in the field of display technology due to its advantages of self-luminescence, high brightness, good picture quality, and low energy consumption.
  • the function of the opening defined by the pixel-defining layer in the OLED display panel is to determine the evaporation area of each sub-pixel; at the same time, the pixel-defining layer plays a flattening role to prepare for the evaporation of subsequent film layers.
  • the usual design is to open an opening in the pixel defining layer of the display area of the OLED display panel, and the red, green, and blue sub-pixel luminescent materials that are subsequently evaporated are formed on the anode at the opening, and the cathode and anode located on the upper and lower sides of the luminescent material layer are provided respectively. Electrons and holes combine to emit light in the luminescent material layer, wherein the cross-section of the opening 14 in the pixel defining layer 2 in the display area is shown in FIG.
  • the punching technology in the screen display area is a direction of the current screen development, and the punching in the screen display area is used to place screens such as cameras. lower detection device. As shown in FIG.
  • a problem brought by this technique of punching holes 8 in the display area 101 of the screen is: since only the sub-pixel openings 9 are opened in the pixel defining layer 2 of the display area 101 , the non-display area of the screen where the punch holes 8 are located The size of the 100-sub-pixel opening 9 at the junction of 102 and the display area 101 is uneven, which affects the display effect of the screen; for the screen integrated with the touch film layer, another problem brought by the punching technology in the display area of the screen is the touch The integrity of the electrode pattern 10 at the position of the punch hole 8 cannot be guaranteed. As shown in FIG. 3 , the four touch electrode patterns 10 around the punch hole 8 are obviously incomplete. For completeness, as shown in FIG.
  • a solution is to extend the border of the touch electrode pattern 10 to the area of the punch hole 8 beyond the junction 100 of the display area 101 and the non-display area 102 , which requires the punch hole 8 to be within the area
  • the lower film layer of the touch electrode traces is relatively flat, so as to avoid defects in the touch electrode traces.
  • the grooves 13 in the pixel definition layer (and the flat layer under the pixel definition layer) need to be as far away from the display area 101 as possible to ensure the traces of the touch electrodes. Not above the groove 13 in the pixel defining layer.
  • the area of the pixel-defining layer remaining between the grooves and the boundary of the display area is larger.
  • embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display panel.
  • An embodiment of the present disclosure provides a display substrate, as shown in FIG. 5 and FIG. 6 , including: a substrate 1 ; a pixel defining layer 2 disposed on the substrate 1 ; the display substrate further includes a display area 101 , a non-display area 102 and a light-transmitting area area 103, the display area 101 and the non-display area 102 at least partially surround the light-transmitting area 103; the pixel defining layer 2 extends from the display area 101 to the non-display area 102; the pixel defining layer 2 is provided with a first opening 21, and the first opening 21 It includes a plurality of first sub-openings 211 and a plurality of second sub-openings 212; the plurality of first sub-openings 211 are distributed in the display area 101, and the plurality of second sub-openings 212 are distributed in the non-display area 102; and the second sub-openings 212 It is closer to the light-transmitting area 103 than the first
  • the first sub-openings 211 distributed in the display area 101 are used for arranging sub-pixels.
  • the light-transmitting area 103 corresponds to an opening formed in the display substrate, and the opening is used to set an under-screen detection device, such as a camera, a fingerprint recognition sensor, and the like.
  • the positional relationship between the display area 101 and the non-display area 102 may be: the display area 101 surrounds the periphery of the non-display area 102; or, the non-display area 102 is located at a corner of the display area 101; or, the non-display area 102 is located in the display area 101 at one side edge and so on.
  • a first opening is formed in the pixel defining layer 2, and a plurality of first sub-openings 211 are distributed in the display area 101, and a plurality of second sub-openings 212 are distributed in the non-display area 102; and the second sub-openings 212 It is closer to the light-transmitting area 103 than the first sub-opening 211 .
  • the pixel-defining layer 2 extends to the non-display area 102 .
  • a plurality of second sub-openings 212 are opened in part, so that the openings in the pixel-defining layer 2 can be extended and distributed to the area of the junction 100 between the non-display area 102 and the display area 101, so as to ensure the
  • the size of the first sub-opening 211 at the junction 100 is uniform, that is, the size of the first sub-opening 211 at the junction 100 is the same as the size of the first sub-opening 211 in the display area 101, thereby ensuring the display effect of the display substrate.
  • the first sub-opening 211 is provided with a first electrode layer 3 and a light-emitting functional layer 4;
  • the substrate 1 includes a pixel circuit 12, the pixel circuit 12 includes a driving transistor, and the driving transistor is electrically connected to the first electrode layer 3;
  • the first electrode layer 3 and the light-emitting functional layer 4 are stacked in a direction away from the substrate 1;
  • the light-emitting functional layer 4 is disposed in the second sub-opening 212;
  • the display substrate further includes a second electrode layer 5, and the second electrode layer 5 is disposed on the pixel
  • the side of the defining layer 2 facing away from the substrate 1, and the second electrode layer 5 covers the first sub-opening 211 and the second sub-opening 212; the orthographic projection of the driving transistor on the substrate 1 and the second sub-opening 212 on the substrate Orthographic projections do not overlap.
  • the first electrode layer 3 and the second electrode layer 5 can respectively provide holes and electrons, and the holes and electrons recombine in the light-emitting functional layer 4, that is, the sub-pixels in the first sub-openings 211 can Normal light is emitted for display; while the second sub-openings 212 distributed in the non-display area 102 are only provided with the light-emitting functional layer 4, and the light-emitting functional layer 4 is covered with the second electrode layer 5, which is distributed in the non-display area.
  • the second sub-opening 212 of 102 lacks the first electrode layer 3, so the area of the second sub-opening 212 distributed in the non-display area 102 does not emit light, thus satisfying the requirement that the area of the second sub-opening 212 in the non-display area 102 does not emit light. Require.
  • the light-emitting functional layer 4 distributed in the second sub-opening 212 of the non-display area 102 may have the same film structure as the light-emitting functional layer 4 distributed in the first sub-opening 211 of the display area 101 , and the distribution The light-emitting functional layer 4 in the second sub-opening 212 of the non-display area 102 may also be a part of the film layer of the light-emitting functional layer 4 distributed in the first sub-opening 211 of the display area 101 , such as the layer distributed in the display area 101 .
  • the light-emitting functional layer 4 in the first sub-opening 211 includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and the light-emitting functional layer in the second sub-opening 212 of the non-display area 102 is distributed. Only two, three or four of the five layers (eg, the light-emitting layer and the hole injection layer) may be included.
  • the display substrate further includes a flat layer 7, and the flat layer 7 is disposed on the side of the pixel defining layer 2 close to the substrate 1; the substrate 1 further includes a base 11, the pixel circuit 12 is disposed on the base 11, and the flat layer 7 A via hole 70 is opened in the middle, and the first electrode layer 3 is connected to the driving transistor in the pixel circuit 12 through the via hole 70 .
  • the pixel circuit includes a buffer layer 17 and a transistor circuit sequentially stacked on the substrate 11 .
  • the transistor circuit includes a plurality of transistors (including driving transistors), a storage 1 and a plurality of signal lines connected to the transistors.
  • the transistor circuit includes a transistor active layer 18 , a first gate insulating layer 19 , a gate 20 of the same layer, a first scan line 25 , a second gate insulating layer 26 , and a second scan line 27 , which are sequentially stacked on the buffer layer 17 . , an intermediate dielectric layer 28 , a source electrode 29 and a drain electrode 30 in the same layer, and a passivation layer 31 .
  • the source electrode 29 and the drain electrode 30 are respectively located at opposite ends of the active layer 18, and the source electrode 29 and the drain electrode 30 are respectively formed on the intermediate dielectric layer 28, the second gate insulating layer 26 and the first gate insulating layer by opening Vias in layer 19 connect active layer 18 .
  • the flattening layer 7 includes two layers, a first flattening layer 71 and a second flattening layer 72 , the first flattening layer 71 and the second flattening layer 72 are sequentially stacked on the passivation layer 31 , and the first flattening layer 72
  • a layer of conductive layer 32 can also be arranged between 71 and the second flat layer 72, the first electrode layer 3 is connected to the conductive layer 32 through the via holes opened in the second flat layer 72, and the conductive layer 32 is opened on the first flat layer 72.
  • Vias in layer 71 and passivation layer 31 connect the drain 30 of the transistor.
  • the first scan line 25 is a gate line
  • the second scan line 27 is a light emission control signal line.
  • the pixel circuit may be a 2T1C driver circuit, or a 7T1C driver circuit or the like.
  • an insulating layer 61 is further provided on the side of the second electrode layer 5 away from the substrate, and the insulating layer 61 includes a first inorganic encapsulation layer 611, an organic encapsulation layer 612, a second inorganic encapsulation layer 613, Inorganic buffer layer 614 .
  • the insulating layer 61 encapsulates the first sub-opening 211 and the second sub-opening 212 .
  • each film layer on the display substrate corresponding to the region where the light-transmitting area 103 is located is hollowed out, that is, the light-transmitting area 103 on the display substrate is correspondingly opened as a through hole; or, the light-transmitting area 103 on the display substrate corresponds to In the area where only the substrate 11 remains, all other film layers in this area are hollowed out; or, the opaque metal film layers in the area corresponding to the light-transmitting area 103 on the display substrate are hollowed out, and the rest of the light-transmitting film layers are reserved.
  • the display substrate further includes a signal line 15 , the signal line 15 is disposed on the side of the pixel defining layer close to the substrate, and the signal line 15 extends from the display area 101 to the non-display area 102; and in the non-display area 102, the signal line 15 includes an arc portion; the arc portion is disposed at least partially around the light-transmitting area 103, and the arc portion at least partially overlaps with the orthographic projection of the second sub-opening 212 on the substrate.
  • some signal lines 15 in the substrate cannot extend in the original extension direction.
  • Circumferential lines are formed, thereby forming the arc portion of the signal line 15 . At least part of the signal line 15 passes under the orthographic projection of the second sub-opening 212. Since the area of the second sub-opening 212 will not be illuminated for display, the passage of the signal line 15 under the second sub-opening 212 will not cause any impact on the second sub-opening 212; However, no signal line passes under the orthographic projection of the first sub-opening 211 in the display area 101 .
  • signal lines 15 include data lines 150 .
  • some data lines 150 in the substrate cannot normally extend in the vertical direction.
  • some data lines 150 passing through the light-transmitting area 103 need to be in the second opening 22.
  • the circumference is surrounded by lines, thereby forming an arc portion of the data line 150 , and the arc portion of the data line 150 at least partially passes under the orthographic projection of the second sub-opening 211 .
  • the signal lines 15 further include scan lines 151 such as gate lines, light-emitting control signal lines, and reset lines. These scan lines 151 originally extend in the horizontal direction, but some of the scan lines 151 passing through the light-transmitting region 103 need to surround the light-transmitting region 103 , thereby forming the arc portion of the scan lines 151 . The arc portion of the scan line 151 at least partially passes under the orthographic projection of the second sub-opening 211 .
  • the arc part, the arc part of the data line 150 is distributed in two layers, one layer is the same layer as the source electrode 29 and the drain electrode 30, and the other layer is the same layer as the conductive layer 32, and the arc part of the data line 150 is distributed in two layers , the frame of the display substrate can be saved.
  • the arc portion of the data line 150 can also be distributed in multiple layers, and the data line 150 in each layer can be prepared by one process using the same material as the metal conductive film layer of the same layer.
  • the multi-layer winding structure of the signal line saves the frame of the display substrate.
  • the arc portion of the signal line 15 may also include the arc portion of the scan line 151, and the arc portion of the scan line 151 may also be distributed in two or more layers. As shown in FIG.
  • the arc portion of the scan line 151 adopts two Layer distribution, one layer is the arc portion of the gate line on the same layer as the gate electrode 20 and the first scan line 25 , and the other layer is the light-emitting control signal wire winding on the same layer as the second scan line 27 .
  • the arc portion of the scan line 151 adopts a multi-layer winding structure to save the frame of the display substrate.
  • the arc portion of the scan line 151 can also be distributed in multiple layers, and the scan line 151 in each layer can be prepared by one process using the same material as the metal conductive film layer of the same layer.
  • the scanning lines 151 when the scanning lines 151 adopt the double-sided driving mode, the scanning lines 151 do not need to be wound at the light-transmitting region 103 , that is, no arc portions are required.
  • the width of the second sub-opening 212 along its radial direction refers to the maximum opening size of the second sub-opening 212 along the radial direction of the light-transmitting area 103 .
  • the radial width is the diameter of the circle; when the second sub-opening 212 is a rectangle, the radial width of the second sub-opening 212 is the length of the broad side of the rectangle, that is, the broad side of the second sub-opening 212 transmits light.
  • the radial direction of the region 103 extends; when the second sub-opening 212 has any other shape, the same is true.
  • the second sub-openings 212 are distributed around the light-transmitting area 103 , the distribution area of the second sub-openings 212 refers to an annular area distributed around the second sub-openings 212 of the light-transmitting area 103 , and the width L of the distribution area of the second sub-openings 212 Refers to the distance between the inner ring and the outer ring of the annular area along the radial direction of the light-transmitting area 103 .
  • the width of the second sub-opening 212 along its radial direction is in the range of 5-40 ⁇ m, for example, the width of the second sub-opening 212 along its radial direction is 7-8 ⁇ m, 20-30 ⁇ m, etc., the second sub-opening 212
  • the width of the distribution area ranges from 10-320 ⁇ m.
  • the size difference between the first sub-opening 211 and the second sub-opening 212 is smaller than a set threshold.
  • the set threshold may be 0 or a value close to 0. That is, the sizes of the first sub-opening 211 and the second sub-opening 212 are approximately the same.
  • the arrangement uniformity of the first sub-openings 211 and the second sub-openings 212 is the same.
  • the distribution uniformity of the first sub-openings 21 refers to the distribution density of the first sub-openings 21 in the display area 101, that is, the distribution density of the first sub-openings 21 in the display area 101;
  • the distribution uniformity of the second sub-openings 212 refers to The distribution density of the second sub-openings 212 in the annular area surrounding the second sub-openings 212 of the light-transmitting area 103 is the distribution density of the second sub-openings 212 in the annular area where the second sub-openings 212 are distributed.
  • the display substrate further includes a dam 24 , the dam 24 is located in the non-display area 102 and at least partially surrounds the light-transmitting area 103 , the dam 24 surrounds the edge of the light-transmitting area 103 , and the second sub-opening 212 surrounds
  • the cofferdam 24 is distributed on the side of the cofferdam 24 away from the light-transmitting area 103 ; the shortest distance M between the cofferdam 24 and the distribution area of the second sub-opening 212 is greater than 0 and less than 300 ⁇ m.
  • the bank 24 is formed by opening a first groove 23 in a part of the insulating layer (eg, a flat layer, a pixel defining layer, and a support layer) at the edge of the light-transmitting region 103 .
  • the width E of the portion of the first groove 23 close to the second sub-opening 212 is in the range of 40 ⁇ m-80 ⁇ m.
  • the edge of the first groove 23 close to the second sub-opening 212 side and the distribution area of the second sub-opening 212 are between The distance F is greater than 0 and less than 260 ⁇ m; or, the distance F between the edge of the first groove 23 close to the side of the second sub-opening 212 and the distribution area of the second sub-opening 212 is greater than 0 and less than 220 ⁇ m.
  • the distribution area of the second sub-openings 212 refers to an annular area distributed around the second sub-openings 212 of the light-transmitting area 103 .
  • the shortest separation distance between the cofferdam 24 and the distribution area of the second sub-opening 212 refers to the outer edge of the cofferdam 24 facing away from the transparent area 103 and the inner ring of the annular distribution area of the second sub-opening 212 close to the transparent area 103 distance between edges.
  • the separation distance M is much smaller than the distance between the sub-pixel opening area and the grooves in the pixel-defining layer in the disclosed technology, that is, the dam 24 and the groove in the pixel-defining layer.
  • the area of the pixel defining layer remaining between the distribution areas of the second sub-openings 212 is small, so that the gas released from the inner film layer of the display substrate during and after the process can pass through the first grooves 23 and the second sub-openings 212 is released in time, so as to avoid the release of gas to open up some internal film layers to form small gaps or small cavities, thereby preventing the film layers from absorbing water vapor through small gaps or small cavities during the production process.
  • the cofferdam 24 is usually composed of at least two organic layers such as a flat layer, a pixel defining layer, a support layer 33, etc., but is not limited to this structure, as long as the cofferdam 24 can meet a certain height, It is enough to prevent the overflow of the organic encapsulation layer 612.
  • the cofferdam 24 can be provided with one circle or two circles.
  • the shortest distance between the cofferdam 24 and the distribution area of the second sub-opening 212 refers to the distance between the outer edge of the cofferdam 24 closest to the distribution area of the second sub-opening 212 that faces away from the transparent area 103 and the inner edge of the annular distribution area of the second sub-opening 212 close to the transparent area 103 .
  • the support layer 33 and the spacers in the display area 101 are formed by one process of the same material, or the support layer 33 can also be prepared by one process of organic resin material alone.
  • the dam 24 is used when encapsulating the substrate area around the light-transmitting area 103 , specifically: when the substrate area around the light-transmitting area 103 is encapsulated, the encapsulation film layer corresponds to the dam 24 Press bonding to encapsulate the substrate area around the light-transmitting area 103 .
  • isolation columns 16 are further disposed between the dam 24 and the arc portion of the signal line 15 .
  • an isolation column 16 is further provided on the side of the cofferdam 24 away from the arc portion of the signal line 15 (ie, the side of the cofferdam 24 close to the light-transmitting area 103 ).
  • the isolation column 16 is used to cut off the conductive film layer (eg, the second electrode layer) on the side of the pixel defining layer away from the substrate.
  • isolation pillars 16 may be isolation trench structures as shown in FIG. 8 .
  • the isolation pillar 16 may also be an isolation bump structure as shown in FIG. 11 , and the isolation bump structure may actually be an I-shaped isolation pillar formed by a source-drain metal layer on the substrate side.
  • the display substrate further includes a touch film layer 6 , and the touch film layer 6 is disposed on the side of the second electrode layer 5 away from the substrate 1 ; the touch film layer 6 Including touch electrodes 62; the touch electrodes 62 are grid-shaped; the pixel defining layer 2 is grid-shaped; the orthographic projection of the touch electrodes 62 on the substrate 1 and the orthographic projection area of the pixel defining layer 2 on the substrate 1 are at least partially overlap.
  • the size of the light-transmitting area 103 can be sufficient to accommodate the under-screen detection device.
  • the distance between the first groove 23 in the pixel defining layer 2 and the junction 100 can be set sufficiently large so that the touch electrode 62 can extend from the display area 101 to the first groove 23 in the non-display area 102 away from the edge of the light-transmitting area 103, and the pixel-defining layer under the coverage area of the touch electrodes 62 is relatively flat, which can not only avoid poor wiring of the touch electrodes 62, but also improve the setting of the light-transmitting area in the non-display area 102.
  • the second sub-openings 212 in the pixel defining layer 2 affects the pattern integrity of the touch electrodes 62; at the same time, since the second sub-openings 212 in the pixel defining layer 2 are distributed in the non-display area 102 near the junction 100 of the display area 101 and the non-display area 102, the The area of the pixel defining layer 2 remaining between the groove 23 and the distribution area of the second sub-opening 212 is small, so the gas released from the inner film layer of the display substrate during and after the process can pass through the first groove 23 and the first opening 21 are released in time, so as to avoid the release of gas to form small gaps or small cavities between some internal film layers, thereby preventing the film layers from absorbing water vapor through small gaps or small cavities during the production process.
  • the defect occurs, that is, the distribution of the second sub-openings 212 in the pixel defining layer 2 in the non-display area 102 in this embodiment makes the expansion and distribution of the touch electrodes 62 from the display area 101 to the first grooves 23 in the non-display area 102 and It will not cause defects in the film layers inside the display substrate due to the absorption of water vapor during the production process.
  • the touch electrodes 62 are designed in a grid shape, which can improve the etching uniformity during the preparation process and improve the capacitance compensation effect.
  • the touch electrodes 62 are disposed on a side of the insulating layer 61 away from the substrate 1 .
  • the touch electrode 62 includes a bridge structure 620 disposed on the inorganic buffer layer 614, a first insulating layer 621 and a touch electrode pattern 622 (including driving electrodes and sensing electrodes), and the driving electrodes or the sensing electrodes in the touch electrode pattern 622 pass through
  • the bridge structure 620 is connected to the via hole opened in the first insulating layer 621 .
  • the orthographic projection of the touch electrodes 62 on the substrate and the orthographic projection of the pixel defining layer 2 between the second sub-openings 212 on the substrate at least partially overlap.
  • the orthographic projection of the light-transmitting region 103 on the substrate 1 includes a circle, a rectangle or a regular hexagon.
  • the shape of the light-transmitting region 103 can also be other shapes.
  • the positional relationship between the display area 101 and the non-display area 102 may also be: the display area 101 surrounds the periphery of the non-display area 102, as shown in FIG. 14; or, the non-display area 102 is located at one edge of the display area 101; for example, the non-display area 102 is located in the middle area of one side edge of the substrate 1, and the display area 101 is surrounded by the non-display area 101.
  • the periphery of zone 102 is shown in FIG. 15 .
  • the display area 101 may also be located in the central area of the substrate 1 , and the non-display area 102 is surrounded by the periphery of the display area 101 .
  • an embodiment of the present disclosure further provides a method for preparing a display substrate, including: preparing the substrate.
  • a pixel defining layer is prepared on the substrate.
  • the display substrate further includes a display area, a non-display area and a light-transmitting area, the display area and the non-display area at least partially surround the light-transmitting area; the pixel defining layer extends from the display area to the non-display area.
  • the preparation of the pixel defining layer includes: forming a pattern of the pixel defining layer, and opening a first opening in the pixel defining layer.
  • the first opening includes a plurality of first sub-openings and a plurality of second sub-openings; the plurality of first sub-openings are distributed in the display area, and the plurality of second sub-openings are distributed in the non-display area; and the second sub-openings are larger than the first sub-openings.
  • the opening is closer to the light-transmitting area.
  • the pattern of the pixel defining layer and the pattern of the first opening are formed through a single patterning process.
  • the preparation of other film layer structures in the display substrate adopts a traditional preparation process, which will not be repeated here.
  • first openings are opened in the pixel defining layer, and a plurality of first sub-openings are distributed in the display area, and a plurality of second sub-openings are distributed in the non-display area; and the second The sub-openings are closer to the light-transmitting area than the first sub-openings.
  • the part of the pixel-defining layer extending to the non-display area is provided.
  • a plurality of second sub-openings are opened, so that the openings in the pixel-defining layer can be extended and distributed to the area at the junction of the non-display area and the display area, thereby ensuring the size of the first sub-opening at the junction of the display area and the non-display area.
  • Uniform that is, the size of the first sub-opening at the interface is the same as the size of the first sub-opening in the display area, thereby ensuring the display effect of the display substrate; at the same time, by distributing the second sub-opening in the non-display area, the cofferdam and the The distance between the distribution areas of the second sub-openings is shortened, so that the gas released from the inner film layer of the display substrate during the process and after the process can be released in time through the first groove and the second sub-opening, thereby avoiding the release of gas.
  • the touch electrodes can extend from the display area to the edge of the first groove in the non-display area, and the pixel defining layer under the coverage area of the touch electrodes is relatively flat, which not only avoids the touch electrode layer Poor wiring occurs, and the influence of the arrangement of the light-transmitting area in the non-display area on the integrity of the touch electrode pattern can be improved.
  • the second sub-opening 212 includes a first-shaped opening 34 , a first-shaped opening 34 , a Two shape openings 35 and third shape openings 36; first shape openings 34, second shape openings 35 and third shape openings 36 have different shapes and sizes; two first shape openings 34, one second shape opening 35 and one The openings 36 of the third shape form an opening period 37 ; a plurality of opening periods 37 are distributed in the non-display area.
  • the shape of the first shape opening 34 is a pentagon
  • the shape of the second shape opening 35 is a hexagon
  • the shape of the third shape opening 36 is a hexagon
  • the second shape opening 35 and the third shape opening The hexagonal shapes of the shape openings 36 are different.
  • the shapes of the first shape opening 34 , the second shape opening 35 and the third shape opening 36 are not limited to the above-mentioned shapes.
  • the two first shape openings 34 are mirror-symmetrical with the horizontal X-axis direction as the axis of symmetry; the first shape opening 34, the second shape opening 35 and the third shape opening 36 are along the X axis.
  • the axis directions are arranged at intervals in sequence.
  • the arrangement of openings of various shapes in the opening period 37 is not limited to the above arrangement.
  • the arrangement and shape of the first sub-openings 211 in the display area are exactly the same as those of the second sub-openings 212 .
  • the first shape opening 34 is used for accommodating green sub-pixels
  • the second shape opening 35 is used for accommodating blue sub-pixels
  • the third shape opening 36 is used for accommodating red sub-pixels.
  • the distance T between the two first shape openings 34 ranges from 6 to 27 ⁇ m; the distance P between the first shape opening 34 and the second shape opening 35 ranges from 15 to 30 ⁇ m
  • the distance T between the two first-shaped openings 34 is the shortest linear distance between two adjacent sides of the two first-shaped openings 34 that are parallel to the X-axis and mirror-symmetrical with the X-axis direction as the axis of symmetry.
  • the spacing P between the first shape opening 34 and the second shape opening 35 , the spacing Q between the second shape opening 35 and the third shape opening 36 , and the spacing Z between the first shape opening 34 and the third shape opening 36 Both are the shortest straight-line distances between two adjacent sides of the two-shaped openings along the Y-axis direction perpendicular to the X-axis.
  • the distance T between the two first shape openings 34 is 16.5 ⁇ m; the distance P between the first shape openings 34 and the second shape openings 35 is 26 ⁇ m; the second shape openings The distance Q between the openings 35 and the third shape openings 36 is 26 ⁇ m; the distance Z between the openings 34 and the third shape openings 36 is 72 ⁇ m.
  • the width a of the first shape opening 34 along the X-axis direction ranges from 15 to 30 ⁇ m; optionally, for example, the width a of the first shape opening 34 along the X-axis direction is 20 ⁇ m.
  • the width b of the second-shaped opening 35 along the X-axis direction ranges from 15 to 30 ⁇ m; optionally, the width b of the second-shaped opening 35 along the X-axis direction is 22 ⁇ m.
  • the width d of the third-shaped opening 36 along the X-axis direction ranges from 6 to 15 ⁇ m; optionally, the width d of the third-shaped opening 36 along the X-axis direction is 10 ⁇ m.
  • the width of each shape opening along the X-axis direction is the maximum dimension of each shape opening along the X-axis direction.
  • the width a of the first shape opening 34 is 1-1.2 times the width b of the second shape opening 35 ; the width b of the second shape opening 35 is the width of the third shape opening 36 . 1.5 to 2 times of d.
  • the length e of the first shape opening 34 along the Y-axis direction ranges from 5 to 25 ⁇ m; optionally, for example, the length e of the first shape opening 34 along the Y-axis direction is 16 ⁇ m.
  • the length f of the second shape opening 35 along the Y-axis direction ranges from 10 to 50 ⁇ m; optionally, the length f of the second shape opening 35 along the Y-axis direction is 35 ⁇ m.
  • the length g of the third-shaped opening 36 along the Y-axis direction ranges from 15 to 60 ⁇ m; optionally, the length g of the third-shaped opening 36 along the Y-axis direction is 45 ⁇ m.
  • the length of each shape opening along the Y-axis direction is the maximum dimension of each shape opening along the Y-axis direction.
  • the length e of the first shape opening 34 is 0.5-0.7 times the length f of the second shape opening 35 ; the length f of the second shape opening 35 is the length of the third shape opening 36 0.8 to 1 times of g.
  • the area of the first-shaped opening 34 is 0.5-0.7 times the area of the second-shaped opening 35 ; the area of the second-shaped opening 35 is 1.5-0.7 times the area of the third-shaped opening 36 . 2 times.
  • the area of each shape opening refers to the orthographic projection area of each shape opening on the substrate.
  • openings of the same shapes in the non-display area and the display area have the same area.
  • the area of each shape opening in the non-display area is 1.1-1.5 times the area of each shape opening in the display area having the same shape.
  • the area of each shape opening in the non-display area is 0.6-0.9 times the area of each shape opening in the display area having the same shape.
  • the setting of the area ratios of the openings of the same shapes in the non-display area and the display area can ensure that the size of the first sub-opening at the junction between the display area and the non-display area is uniform, and at the same time, the display substrate can be used in the process.
  • the gas released from the inner film layer can be released in time through the first groove and the second sub-opening, so as to avoid the released gas from pushing up some inner film layers to form small gaps or small cavities , so as to avoid defects caused by each film layer absorbing water vapor through small gaps or small cavities during the production process.
  • Embodiments of the present disclosure further provide a display panel, including the above-mentioned display substrate.
  • the display effect of the display panel can be improved, and at the same time, the poor water absorption of the display panel during the production process can be avoided.
  • the display panel provided by the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, a display, a mobile phone, and a navigator.
  • the present invention is based on the PCT international patent application with the application number of PCT/CN2020/114589 filed on September 10, 2020, and claims priority according to the relevant regulations in the Patent Law. The entire content of the application is incorporated into this application by reference .

Abstract

一种显示基板及其制备方法和显示面板。显示基板包括：基板（1）；设置在基板（1）上的像素限定层（2）；显示基板还包括显示区（101），非显示区（102）和透光区（103），显示区（101）和非显示区（102）至少部分围绕所述透光区（103）；像素限定层（2）由显示区（101）延伸至非显示区（102）；像素限定层（2）中开设有第一开口（21），第一开口（21）包括多个第一子开口（211）和多个第二子开口（212）；多个第一子开口（211）分布于显示区（101），多个第二子开口（212）分布于非显示区（102）；且第二子开口（212）比第一子开口（211）更靠近透光区（103）。

Description

显示基板及其制备方法和显示面板 技术领域
本公开实施例属于显示技术领域，具体涉及一种显示基板及其制备方法和显示面板。
背景技术
有机发光二极管显示(Organic Light-Emitting Display,OLED)技术制备的OLED显示面板，由于其具有自发光、亮度高、画质好、能耗低等优点，已经成为显示技术领域的主流发展方向。对于这种新型发展的技术，可以做更多的设计去满足人们的需求，其中屏幕显示区打孔技术是现在屏幕发展的一个方向。
发明内容
本公开实施例提供一种显示基板及其制备方法和显示面板。
第一方面，本公开实施例提供一种显示基板，包括：
基板；
设置在所述基板上的像素限定层；
所述显示基板还包括显示区，非显示区和透光区，所述显示区和所述非显示区至少部分围绕所述透光区；
所述像素限定层由所述显示区延伸至所述非显示区；
所述像素限定层中开设有第一开口，所述第一开口包括多个第一子开口和多个第二子开口；所述多个第一子开口分布于所述显示区，所述多个第二子开口分布于所述非显示区；且所述第二子开口比所述第一子开口更靠近所述透光区。
在一些实施例中，所述第一子开口中设置有第一电极层和发光功能层；
所述基板包括像素电路，所述像素电路包括驱动晶体管，所述驱动晶 体管与所述第一电极层电连接；
所述第一电极层和所述发光功能层沿远离所述基板的方向叠置；
所述第二子开口中设置有所述发光功能层；
所述显示基板还包括第二电极层，所述第二电极层设置于所述像素限定层的背离所述基板的一侧，且所述第二电极层覆盖所述第一子开口和所述第二子开口；
所述驱动晶体管在所述基板上的正投影与所述第二子开口在所述基板上的正投影不重叠。
在一些实施例中，所述显示基板还包括信号线，所述信号线设置于所述像素限定层的靠近所述基板的一侧，所述信号线由所述显示区延伸至所述非显示区，且在所述非显示区中所述信号线包括弧线部分；
所述弧线部分至少部分围绕所述透光区设置，且所述弧线部分与所述第二子开口在所述基板上的正投影至少部分重叠。
在一些实施例中，所述信号线包括数据线。
在一些实施例中，沿所述透光区的径向方向，所述第二子开口的分布区域的宽度范围为2～8倍的所述第二子开口沿其径向的宽度。
在一些实施例中，所述显示基板还包括围堰，所述围堰位于所述非显示区，且至少部分围绕所述透光区；
所述围堰围绕于所述透光区的边缘，所述第二子开口围绕所述围堰分布于所述围堰的背离所述透光区的一侧；
所述围堰与所述第二子开口的分布区域之间的最短间隔距离大于0且小于300微米。
在一些实施例中，还包括触控膜层，所述触控膜层设置于所述第二电极层的背离所述基板的一侧；
所述触控膜层包括触控电极；所述触控电极呈网格状；所述像素限定层呈网格状；所述触控电极在所述基板上的正投影与所述像素限定层在所 述基板上的正投影区域至少部分交叠。
在一些实施例中，所述触控电极在所述基板上的正投影与所述第二子开口之间的所述像素限定层在所述基板上的正投影至少部分交叠。
在一些实施例中，所述第一子开口与所述第二子开口的尺寸差小于设定阈值。
在一些实施例中，所述第二子开口包括第一形状开口、第二形状开口和第三形状开口；
所述第一形状开口、所述第二形状开口和所述第三形状开口的形状和大小不同；
两个所述第一形状开口、一个所述第二形状开口和一个所述第三形状开口组成一个开口周期；所述非显示区内分布有多个所述开口周期。
在一些实施例中，所述开口周期内，两个所述第一形状开口之间的间距范围为6～27μm；
所述第一形状开口与所述第二形状开口之间的间距范围为15～30μm；
所述第二形状开口与所述第三形状开口之间的间距范围为15～30μm；
所述第一形状开口与所述第三形状开口之间的间距范围为50～80μm。
在一些实施例中，所述第一形状开口与所述第三形状开口之间的间距是所述第一形状开口与所述第二形状开口之间的间距的1.5～2.5倍；
所述第一形状开口与所述第二形状开口之间的间距是所述第二形状开口与所述第三形状开口之间的间距的0.8～1.2倍；
两个所述第一形状开口之间的间距是所述第一形状开口与所述第二形状开口之间的间距的0.6～1倍。
在一些实施例中，所述第一子开口与所述第二子开口的排布均匀度相同。
在一些实施例中，所述显示区围绕于所述非显示区的外围；
或者，所述非显示区位于所述显示区的一个角落处；
或者，所述非显示区位于所述显示区的一侧边缘处。
在一些实施例中，还包括平坦层，所述平坦层设置于所述像素限定层的靠近所述基板的一侧；
所述基板还包括基底，所述像素电路设置在所述基底上，所述平坦层中开设有过孔，所述第一电极层通过所述过孔连接所述像素电路中的所述驱动晶体管。
第二方面，本公开实施例还提供一种显示面板，包括上述显示基板。
第三方面，本公开实施例还提供一种显示基板的制备方法，包括：
制备基板；
在所述基板上制备像素限定层；
所述显示基板还包括显示区，非显示区和透光区，所述显示区和所述非显示区至少部分围绕所述透光区；所述像素限定层由所述显示区延伸至所述非显示区；
制备所述像素限定层包括：形成所述像素限定层的图形，并在所述像素限定层中开设第一开口；
所述第一开口包括多个第一子开口和多个第二子开口；所述多个第一子开口分布于所述显示区，所述多个第二子开口分布于所述非显示区；且所述第二子开口比所述第一子开口更靠近所述透光区。
在一些实施例中，通过一次构图工艺形成所述像素限定层的图形和所述第一开口的图形。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为公开技术中OLED显示面板显示区内像素限定层中开设开口的局 部结构剖视图；
图2为公开技术中OLED屏幕显示区打孔的结构俯视图；
图3为公开技术中OLED屏幕显示区打孔时触控电极图案的设置结构俯视图；
图4为公开技术中OLED屏幕显示区打孔时触控电极图案向显示区外扩展分布的结构俯视图；
图5为本公开实施例中显示基板的结构俯视图；
图6为图5中显示基板沿AA剖切线的结构剖视图；
图7为本公开实施例中显示基板显示区的局部结构剖视图；
图8为本公开实施例中显示基板显示区至非显示区的局部结构剖视示意图；
图9为本公开实施例显示基板中信号线的弧线部分的结构俯视示意图；
图10为图5中显示基板C部分的结构俯视放大示意图；
图11为本公开实施例显示基板中隔离柱的结构剖视示意图；
图12为本公开实施例中设置有触控膜层的显示基板的结构俯视图；
图13为图7中显示基板沿BB剖切线的结构剖视图；
图14为本公开实施例中显示基板上显示区与非显示区的另一种分布示意图；
图15为本公开实施例中显示基板上显示区与非显示区的又一种分布示意图；
图16为本公开实施例中显示基板上显示区与非显示区的又一种分布示意图；
图17为本公开另一实施例中显示基板非显示区内第二子开口的结构俯视图；
图18为图5中显示基板C部分的另一种结构俯视放大示意图。
其中附图标记为：
1、基板；11、基底；12、像素电路；2、像素限定层；21、第一开口；211、第一子开口；212、第二子开口；23、第一凹槽；24、围堰；101、显示区；102、非显示区；103、透光区；100、交界处；3、第一电极层；4、发光功能层；5、第二电极层；6、触控膜层；61、绝缘层；611、第一无机封装层；612、有机封装层；613、第二无机封装层；614、无机缓冲层；62、触控电极；620、桥结构；621、第一绝缘层；622、触控电极图形；7、平坦层；70、过孔；71、第一平坦层；72、第二平坦层；8、孔；9、子像素开口；10、触控电极图案；13、槽；14、开口；15、信号线；150、数据线；151、扫描线；16、隔离柱；17、缓冲层；18、有源层；19、第一栅绝缘层；20、栅极；25、第一扫描线；26、第二栅绝缘层；27、第二扫描线；28、中间介电层；29、源极；30、漏极；31、钝化层；32、导电层；33、支撑层；34、第一形状开口；35、第二形状开口；36、第三形状开口；37、开口周期。
具体实施方式
为使本领域技术人员更好地理解本公开实施例的技术方案，下面结合附图和具体实施方式对本公开实施例提供的一种显示基板及其制备方法和显示面板作进一步详细描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了区的具体形状，但并不是旨在限制性的。
有机发光二极管显示(Organic Light-Emitting Display,OLED)技术的OLED显示面板，由于其具有自发光、亮度高、画质好、能耗低等优点， 已经成为显示技术领域的主流发展方向。
OLED显示面板中像素限定层所限定的开口的作用是确定每个子像素的蒸镀区域；同时，像素限定层起平坦作用，为蒸镀后续各膜层做准备。通常设计是在OLED显示面板显示区的像素限定层中开设开口，后续蒸镀的红、绿、蓝子像素发光材料形成在开口处的阳极上，位于发光材料层上下两侧的阴阳极分别提供电子和空穴在发光材料层复合发光，其中，显示区内像素限定层2中开设开口14的截面如图1所示，像素限定层2下面为OLED显示面板背板的各膜层。
对于这种新型发展的OLED显示技术，可以做更多的设计去满足人们的需求，其中屏幕显示区打孔技术是现在屏幕发展的一个方向，屏幕显示区打孔用于安置如摄像头等的屏下检测器件。如图2所示，这种屏幕显示区101打孔8技术带来的一个问题是：由于仅在显示区101像素限定层2中开设子像素开口9，打孔8位置所在的屏幕非显示区102与显示区101交界处100子像素开口9尺寸大小不均匀，影响屏幕的显示效果；对于集成有触控膜层的屏幕，这种屏幕显示区打孔技术带来的另一个问题是触控电极图案10在打孔8位置的完整性得不到保障，如图3所示，打孔8周围的四个触控电极图案10显然不完整，为了改善打孔8周围触控电极图案10的完整性，如图4所示，一种解决办法是将触控电极图案10的边界往显示区101与非显示区102交界处100以外的打孔8区域扩展，这需要打孔8位置区域内触控电极走线的下面膜层较为平坦，以避免触控电极走线发生不良。然而，为了形成打孔8位置区域内的封装坝24，需要在打孔8位置区域内的像素限定层(以及像素限定层下方的平坦层)中进行挖槽13，这个挖槽13使得像素限定层变得不平坦，为了保证触控电极走线良好，需要像素限定层(以及像素限定层下方的平坦层)中的挖槽13距离显示区101越远越好，以保证触控电极走线不在像素限定层中挖槽13的上方。当像素限定层中的挖槽远离显示区时，挖槽与显示区边界之间保留的像素限定层区域较 大，由于显示面板工艺过程中和过程后内部膜层中会向外释放气体，挖槽与显示区边界之间保留的像素限定层区域较大，会导致内部膜层释放气体无法从像素限定层的挖槽开口处及时释放，以致释放气体会将某些内部膜层之间顶开形成小缝隙或小空腔，这会导致生产过程中各膜层容易吸收水汽而产生不良。
针对上述屏幕显示区打孔技术所带来的一系列问题，本公开实施例提供一种显示基板及其制备方法和显示面板。
本公开实施例提供一种显示基板，如图5和图6所示，包括：基板1；设置在基板1上的像素限定层2；显示基板还包括显示区101，非显示区102和透光区103，显示区101和非显示区102至少部分围绕透光区103；像素限定层2由显示区101延伸至非显示区102；像素限定层2中开设有第一开口21，第一开口21包括多个第一子开口211和多个第二子开口212；多个第一子开口211分布于显示区101，多个第二子开口212分布于非显示区102；且第二子开口212比第一子开口211更靠近透光区103。
其中，分布于显示区101的第一子开口211中用于设置子像素。透光区103对应为开设在显示基板中的开口，开口中用于设置屏下检测器件，如摄像头、指纹识别传感器等。显示区101和非显示区102的位置关系可以是：显示区101围绕于非显示区102的外围；或者，非显示区102位于显示区101的一个角落处；或者，非显示区102位于显示区101的一侧边缘处等等。
该显示基板通过在像素限定层2中开设第一开口，并使多个第一子开口211分布于显示区101，多个第二子开口212分布于非显示区102；且第二子开口212比第一子开口211更靠近透光区103，相对于公开技术中仅在显示区像素限定层中开设子像素开口的情况，本实施例中在像素限定层2的延伸至非显示区102的部分中开设多个第二子开口212，使像素限定层2 中的开口能扩展分布至非显示区102的与显示区101的交界处100的区域，从而确保显示区101与非显示区102的交界处100处第一子开口211的尺寸大小均匀，即交界处100第一子开口211的尺寸与显示区101内第一子开口211的尺寸相同，从而确保了显示基板的显示效果。
在一些实施例中，第一子开口211中设置有第一电极层3和发光功能层4；基板1包括像素电路12，像素电路12包括驱动晶体管，驱动晶体管与第一电极层3电连接；第一电极层3和发光功能层4沿远离基板1的方向叠置；第二子开口212中设置有发光功能层4；显示基板还包括第二电极层5，第二电极层5设置于像素限定层2的背离基板1的一侧，且第二电极层5覆盖第一子开口211和第二子开口212；驱动晶体管在基板1上的正投影与第二子开口212在基板1上的正投影不重叠。其中，分布于显示区101的第一子开口211中的第一电极层3、发光功能层4以及设置在像素限定层2上的第二电极层5相互叠置构成一个子像素，该子像素在像素电路12的驱动下，第一电极层3和第二电极层5能分别提供空穴和电子，空穴和电子在发光功能层4复合发光，即第一子开口211中的子像素能够正常发光，以进行显示；而分布于非显示区102的第二子开口212中由于只设置有发光功能层4，且发光功能层4上方覆盖有第二电极层5，由于分布于非显示区102的第二子开口212中缺少第一电极层3，所以分布于非显示区102的第二子开口212区域不会发光，从而满足了非显示区102内第二子开口212区域不发光的要求。
在一些实施例中，分布于非显示区102的第二子开口212中的发光功能层4可以和分布于显示区101的第一子开口211中的发光功能层4的膜层结构一致，分布于非显示区102的第二子开口212中的发光功能层4也可以是分布于显示区101的第一子开口211中的发光功能层4中的部分膜层，如分布于显示区101的第一子开口211中的发光功能层4包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层，分布于非显示区 102的第二子开口212中的发光功能层可以只包括这五个膜层中的两个(如发光层和空穴注入层)、三个或四个膜层。
在一些实施例中，显示基板还包括平坦层7，平坦层7设置于像素限定层2的靠近基板1的一侧；基板1还包括基底11，像素电路12设置在基底11上，平坦层7中开设有过孔70，第一电极层3通过过孔70连接像素电路12中的驱动晶体管。
在一些实施例中，如图7和图8所示，像素电路包括依次叠置于基底11上的缓冲层17和晶体管电路。晶体管电路中包括多个晶体管(其中包括驱动晶体管)、存储1以及多条与晶体管连接的信号线。晶体管电路包括依次叠置于缓冲层17上的晶体管有源层18、第一栅绝缘层19、同层的栅极20和第一扫描线25、第二栅绝缘层26、第二扫描线27、中间介电层28、同层的源极29和漏极30、钝化层31。其中，源极29和漏极30分别对应位于有源层18的相对两端，且源极29和漏极30分别通过开设在中间介电层28、第二栅绝缘层26和第一栅绝缘层19中的过孔连接有源层18。
在一些实施例中，平坦层7包括两层，第一平坦层71和第二平坦层72，第一平坦层71、第二平坦层72依次叠置于钝化层31上，第一平坦层71与第二平坦层72之间还可以设置一层导电层32，第一电极层3通过开设在第二平坦层72中的过孔连接导电层32，导电层32再通过开设在第一平坦层71和钝化层31中的过孔连接晶体管的漏极30。其中，第一扫描线25为栅线，第二扫描线27为发光控制信号线。
在一些实施例中，像素电路可以是2T1C驱动电路，也可以是7T1C驱动电路等。
在一些实施例中，第二电极层5背离基板的一侧还设置有绝缘层61，绝缘层61包括依次叠置的第一无机封装层611、有机封装层612、第二无机封装层613、无机缓冲层614。绝缘层61对第一子开口211和第二子开口212形成封装。
在一些实施例中，显示基板上对应透光区103所在区域的各个膜层都是挖空的，即显示基板上透光区103对应开设为通孔；或者，显示基板上对应透光区103的区域只有基底11保留，该区域内的其他膜层全部挖空；或者，显示基板上对应透光区103的区域的不透光金属膜层都挖空，其余透光膜层保留。
在一些实施例中，如图9和图10所示，显示基板还包括信号线15，信号线15设置于像素限定层的靠近基板的一侧，信号线15由显示区101延伸至非显示区102；且在非显示区102中信号线15包括弧线部分；弧线部分至少部分围绕透光区103设置，且弧线部分与第二子开口212在基板上的正投影至少部分重叠。其中，由于透光区103的设置，使得基板中的部分信号线15无法按照原来的延伸方向延伸，在透光区103的周围，部分经过透光区103的信号线15需要在透光区103周围绕线，从而形成了信号线15的弧线部分。第二子开口212的正投影下方至少有部分信号线15经过，由于第二子开口212区域不会进行发光显示，所以信号线15在其下方通过不会对第二子开口212造成任何影响；而位于显示区101的第一子开口211的正投影下方没有信号线经过。
在一些实施例中，信号线15包括数据线150。其中，由于透光区103的设置，使得基板中的部分数据线150无法正常沿竖直方向延伸，在透光区103的周围，部分经过透光区103的数据线150需要在第二开口22周围绕线，从而形成了数据线150的弧线部分，该数据线150的弧线部分至少部分经过第二子开口211的正投影下方。
在一些实施例中，信号线15还包括栅线、发光控制信号线、复位线等扫描线151。这些扫描线151本是沿着水平方向延伸，但经过透光区103的部分扫描线151需要在透光区103周围绕线，从而形成了扫描线151的弧线部分。该扫描线151的弧线部分至少部分经过第二子开口211的正投影下方。
在一些实施例中，如图8所示，在第二子开口212分布区的下方，对应分布有多条信号线15的弧线部分，如该信号线15的弧线部分包括数据线150的弧线部分，数据线150的弧线部分分两层分布，一层与源极29和漏极30同层，另一层与导电层32同层，数据线150的弧线部分采用两层分布，可以节省显示基板边框。数据线150的弧线部分也可以分多层分布，各层中的数据线150可以与同层的金属导电膜层采用相同材料通过一次工艺制备。或者，当显示基板还有其他金属层结构时，如对于LTPO面板，还有氧化物晶体管的栅极层以及转接层等金属层结构，或者显示面板还有其他转接金属层时，可以利用信号线多层绕线结构，节省显示基板边框。该信号线15的弧线部分还可以包括扫描线151的弧线部分，扫描线151的弧线部分也可以分两层或多层分布，如图8中，扫描线151的弧线部分采用两层分布，一层为与栅极20和第一扫描线25同层的栅线弧线部分，另一层为与第二扫描线27同层的发光控制信号线绕线。扫描线151的弧线部分采用多层绕线结构，节省显示基板边框。扫描线151的弧线部分也可以分多层分布，各层中的扫描线151可以与同层的金属导电膜层采用相同材料通过一次工艺制备。
需要说明的是，当扫描线151采用双边驱动模式时，则扫描线151无需在透光区103处进行绕线，即无需设置弧线部分。
在一些实施例中，如图5和图6所示，沿透光区103的径向方向，第二子开口212的分布区域的宽度L范围为2～8倍的第二子开口212沿其径向的宽度。第二子开口212沿其径向的宽度指第二子开口212沿透光区103的径向方向的最大开口尺寸，如当第二子开口212为圆形时，第二子开口212沿其径向的宽度为圆形的直径；当第二子开口212为矩形时，第二子开口212沿其径向的宽度为矩形的宽边的长度，即第二子开口212的宽边沿透光区103的径向方向延伸；当第二子开口212为其他任意形状时，也同理。其中，第二子开口212围绕透光区103分布，第二子开口212的分布 区域指围绕透光区103的第二子开口212分布的环形区域，第二子开口212的分布区域的宽度L指该环形区域的沿透光区103径向的内圈与外圈之间的间距。在一些实施例中，第二子开口212沿其径向的宽度范围为5-40μm，如第二子开口212沿其径向的宽度为7-8μm、20-30μm等，第二子开口212的分布区域的宽度范围为10-320μm。在一些实施例中，第一子开口211与第二子开口212的尺寸差小于设定阈值。该设定阈值可以为0或者接近于0的值。即第一子开口211与第二子开口212的尺寸近似完全相同。在一些实施例中，第一子开口211与第二子开口212的排布均匀度相同。第一子开口21的排布均匀度指显示区101内第一子开口21的分布密度，即显示区101内第一子开口21分布的密集程度；第二子开口212的排布均匀度指围绕透光区103的第二子开口212分布的环形区域内第二子开口212的分布密度，即第二子开口212分布的环形区域内第二子开口212分布的密集程度。上述设置，能够很好地确保显示区101与非显示区102的交界处100第一子开口211的尺寸大小均匀，从而很好地确保显示基板的显示效果。
在一些实施例中，显示基板还包括围堰24，围堰24位于非显示区102，且至少部分围绕透光区103，围堰24围绕于透光区103的边缘，第二子开口212围绕围堰24分布于围堰24的背离透光区103的一侧；围堰24与第二子开口212的分布区域之间的最短间隔距离M大于0且小于300微米。其中，围堰24通过在透光区103边缘的部分绝缘层(如平坦层、像素限定层、支撑层)中开设第一凹槽23形成。靠近第二子开口212的第一凹槽23部分的宽度E范围为40μm-80μm，因此，第一凹槽23的靠近第二子开口212一侧的边缘与第二子开口212分布区域之间的距离F大于0且小于260μm；或者，第一凹槽23的靠近第二子开口212一侧的边缘与第二子开口212分布区域之间的距离F大于0且小于220μm。第二子开口212的分布区域指围绕透光区103的第二子开口212分布的环形区域。围堰24与第二子开口212的分布区域之间的最短间隔距离指围堰24的背离透光区103的外圈边缘与 第二子开口212环形分布区域的靠近透光区103的内圈边缘之间的距离。相对于公开技术中仅在显示区像素限定层中开设子像素开口的情况，该间隔距离M远小于公开技术中子像素开口区域与像素限定层中凹槽之间的距离，即围堰24与第二子开口212分布区域之间保留的像素限定层区域较小，使该显示基板在工艺过程中和过程后内部膜层中向外释放的气体能够通过第一凹槽23和第二子开口212及时进行释放，从而避免释放气体将某些内部膜层之间顶开形成小缝隙或小空腔，进而避免生产过程中各膜层通过小缝隙或小空腔吸收水汽而产生不良。
在一些实施例中，如图8所示，围堰24通常由平坦层，像素限定层，支撑层33等至少两层有机层组成，但不限于该结构，只要围堰24能满足一定高度，阻挡有机封装层612溢流即可，围堰24可以设置一圈，也可以设置两圈，如果围堰24设置有两圈，则围堰24与第二子开口212的分布区域之间的最短间隔距离指最靠近第二子开口212分布区域的一个围堰24的背离透光区103的外圈边缘与第二子开口212环形分布区域的靠近透光区103的内圈边缘之间的距离。其中，支撑层33与显示区101内的隔垫物采用相同材料一次工艺制备形成，或者，支撑层33也可以采用有机树脂材料单独通过一次工艺制备。
在一些实施例中，围堰24用于对透光区103周围的基板区域进行封装时使用，具体为：当对透光区103周围的基板区域进行封装时，封装膜层与围堰24对应压合，以对透光区103周围的基板区域进行封装。
在一些实施例中，如图10中从俯视角度观看显示基板，围堰24与信号线15弧线部分之间还设置有隔离柱16。另外，在围堰24的远离信号线15弧线部分的一侧(即围堰24的靠近透光区103的一侧)还设置有隔离柱16。隔离柱16用于将位于像素限定层背离基板一侧的导电膜层(如第二电极层)截断。
在一些实施例中，隔离柱16可以是如图8中所示的隔离槽结构。在一 些实施例中，隔离柱16也可以是如图11中所示的隔离凸起结构，该隔离凸起结构实际可以是由基板侧的源漏金属层形成的工字型隔离柱。
在一些实施例中，如图12和图13所示，显示基板还包括触控膜层6，触控膜层6设置于第二电极层5的背离基板1的一侧；触控膜层6包括触控电极62；触控电极62呈网格状；像素限定层2呈网格状；触控电极62在基板1上的正投影与像素限定层2在基板1上的正投影区域至少部分交叠。由于像素限定层2中的第二子开口212分布于非显示区102内靠近显示区101与非显示区102交界处100的区域，所以在确保透光区103的大小能够足以安置屏下检测器件的情况下，像素限定层2中第一凹槽23距离交界处100的距离可以设置的足够大，以使触控电极62能由显示区101一直延伸覆盖至非显示区102第一凹槽23的背离透光区103边缘处，且触控电极62的覆盖区域下方的像素限定层较为平坦，从而不仅能避免触控电极62走线发生不良，而且能改善非显示区102内设置透光区103对触控电极62图案完整性的影响；同时，由于像素限定层2中的第二子开口212分布于非显示区102内靠近显示区101与非显示区102交界处100的区域，使第一凹槽23与第二子开口212分布区域之间保留的像素限定层2区域较小，所以该显示基板在工艺过程中和过程后内部膜层中向外释放的气体能够通过第一凹槽23和第一开口21及时进行释放，从而避免释放气体将某些内部膜层之间顶开形成小缝隙或小空腔，进而避免生产过程中各膜层通过小缝隙或小空腔吸收水汽而产生不良，即本实施例像素限定层2中第二子开口212在非显示区102的分布，使触控电极62由显示区101向非显示区102的第一凹槽23处的扩展分布并不会导致生产过程中显示基板内部各膜层由于吸收水汽而产生不良。另外，触控电极62呈网格状设计，能够提升其制备过程中的刻蚀均匀性，并提高其电容补偿效果。
在一些实施例中，如图7和图8所示，触控电极62设置于绝缘层61的背离基板1的一侧。触控电极62包括设置于无机缓冲层614上的桥结构 620、第一绝缘层621和触控电极图形622(包括驱动电极和感应电极)，触控电极图形622中的驱动电极或者感应电极通过开设在第一绝缘层621的过孔连接桥结构620。
在一些实施例中，触控电极62在基板上的正投影与第二子开口212之间的像素限定层2在基板上的正投影至少部分交叠。
在一些实施例中，透光区103在基板1上的正投影包括圆形、矩形或正六边形。当然，透光区103的形状也可以是其他形状。
在一些实施例中，显示区101和非显示区102的位置关系也可以是：显示区101围绕于非显示区102的外围，如图5所示；或者，非显示区102位于显示区101的一个角落处，如图14所示；或者，非显示区102位于显示区101的一侧边缘处；例如：非显示区102位于基板1一侧边缘的中间区域，显示区101围设于非显示区102的外围，如图15所示。
在一些实施例中，如图16所示，显示区101也可以位于基板1的中心区域，非显示区102围设于显示区101的外围。
基于显示基板的上述结构，本公开实施例还提供一种显示基板的制备方法，包括：制备基板。
在基板上制备像素限定层。
显示基板还包括显示区，非显示区和透光区，显示区和非显示区至少部分围绕透光区；像素限定层由显示区延伸至非显示区。
制备像素限定层包括：形成像素限定层的图形，并在像素限定层中开设第一开口。
第一开口包括多个第一子开口和多个第二子开口；多个第一子开口分布于显示区，多个第二子开口分布于非显示区；且第二子开口比第一子开口更靠近透光区。
在一些实施例中，通过一次构图工艺形成像素限定层的图形和第一开口的图形。
本实施例中，显示基板中其他膜层结构的制备采用传统制备工艺，这里不再赘述。
本公开实施例中所提供的显示基板，通过在像素限定层中开设第一开口，并使多个第一子开口分布于显示区，多个第二子开口分布于非显示区；且第二子开口比第一子开口更靠近透光区，相对于公开技术中仅在显示区像素限定层中开设子像素开口的情况，本实施例中在像素限定层的延伸至非显示区的部分中开设多个第二子开口，使像素限定层中的开口能扩展分布至非显示区的与显示区的交界处的区域，从而确保显示区与非显示区的交界处处第一子开口的尺寸大小均匀，即交界处第一子开口的尺寸与显示区内第一子开口的尺寸相同，从而确保了显示基板的显示效果；同时，通过使第二子开口分布于非显示区，使围堰与第二子开口分布区域之间的间距缩短，使该显示基板在工艺过程中和过程后内部膜层中向外释放的气体能够通过第一凹槽和第二子开口及时进行释放，从而避免释放气体将某些内部膜层之间顶开形成小缝隙或小空腔，进而避免生产过程中各膜层通过小缝隙或小空腔吸收水汽而产生不良；另外，通过使第二子开口分布于非显示区，使触控电极能由显示区一直延伸覆盖至非显示区第一凹槽的边缘处，且触控电极的覆盖区域下方的像素限定层较为平坦，从而不仅能避免触控电极层走线发生不良，而且能改善非显示区内透光区的设置对触控电极图案完整性的影响。
本公开实施例还提供一种显示基板，如图17和图18所示，在上述实施例中的显示基板的基础上，本实施例中，第二子开口212包括第一形状开口34、第二形状开口35和第三形状开口36；第一形状开口34、第二形状开口35和第三形状开口36的形状和大小不同；两个第一形状开口34、一个第二形状开口35和一个第三形状开口36组成一个开口周期37；非显示区内分布有多个开口周期37。
在一些实施例中，第一形状开口34的形状为五边型，第二形状开口35的形状为六边形，第三形状开口36的形状为六边形，第二形状开口35与第三形状开口36的六边形形状不同。当然，第一形状开口34、第二形状开口35和第三形状开口36的形状并不局限于上述形状。
在一些实施例中，同一个开口周期37内，两个第一形状开口34以水平X轴方向为对称轴镜像对称；第一形状开口34、第二形状开口35和第三形状开口36沿X轴方向依次间隔排布。当然，开口周期37内各形状开口的排布并不局限于上述排布方式。
在一些实施例中，显示区内第一子开口211的设置和形状与第二子开口212完全相同。其中，第一形状开口34中用于容纳绿色子像素，第二形状开口35中用于容纳蓝色子像素，第三形状开口36中用于容纳红色子像素。
在一些实施例中，开口周期37内，两个第一形状开口34之间的间距T范围为6～27μm；第一形状开口34与第二形状开口35之间的间距P范围为15～30μm；第二形状开口35与第三形状开口36之间的间距Q范围为15～30μm；第一形状开口34与第三形状开口36之间的间距Z范围为50～80μm。其中，两个第一形状开口34之间的间距T为两第一形状开口34的平行于X轴的且以X轴方向为对称轴镜像对称的相邻两条边之间的最短直线距离。第一形状开口34与第二形状开口35之间的间距P、第二形状开口35与第三形状开口36之间的间距Q以及第一形状开口34与第三形状开口36之间的间距Z均为两形状开口的沿垂直于X轴的Y轴方向的相邻两条边之间的最短直线距离。
在一些实施例中，开口周期37内，两个第一形状开口34之间的间距T为16.5μm；第一形状开口34与第二形状开口35之间的间距P为26μm；第二形状开口35与第三形状开口36之间的间距Q为26μm；第一形状开口34与第三形状开口36之间的间距Z为72μm。
在一些实施例中，开口周期37内，第一形状开口34沿X轴方向的宽度a范围为15～30μm；可选地，例如第一形状开口34沿X轴方向的宽度a为20μm。第二形状开口35沿X轴方向的宽度b范围为15～30μm；可选地，第二形状开口35沿X轴方向的宽度b为22μm。第三形状开口36沿X轴方向的宽度d范围为6～15μm；可选地，第三形状开口36沿X轴方向的宽度d为10μm。其中，各形状开口沿X轴方向的宽度为各形状开口沿X轴方向的最大尺寸。
在一些实施例中，开口周期37内，第一形状开口34的宽度a是第二形状开口35的宽度b的1～1.2倍；第二形状开口35的宽度b是第三形状开口36的宽度d的1.5～2倍。
在一些实施例中，开口周期37内，第一形状开口34沿Y轴方向的长度e范围为5～25μm；可选地，例如第一形状开口34沿Y轴方向的长度e为16μm。第二形状开口35沿Y轴方向的长度f范围为10～50μm；可选地，第二形状开口35沿Y轴方向的长度f为35μm。第三形状开口36沿Y轴方向的长度g范围为15～60μm；可选地，第三形状开口36沿Y轴方向的长度g为45μm。其中，各形状开口沿Y轴方向的长度为各形状开口沿Y轴方向的最大尺寸。
在一些实施例中，开口周期37内，第一形状开口34的长度e是第二形状开口35的长度f的0.5～0.7倍；第二形状开口35的长度f是第三形状开口36的长度g的0.8～1倍。
在一些实施例中，开口周期37内，第一形状开口34的面积是第二形状开口35的面积的0.5～0.7倍；第二形状开口35的面积是第三形状开口36的面积的1.5～2倍。其中，各形状开口的面积指各形状开口在基板上的正投影面积。
在一些实施例中，非显示区内与显示区内形状相同的各形状开口面积相同。
在一些实施例中，非显示区内各形状开口的面积是显示区内形状相同的各形状开口面积的1.1～1.5倍。
在一些实施例中，非显示区内各形状开口的面积是显示区内形状相同的各形状开口面积的0.6～0.9倍。
上述非显示区内与显示区内形状相同的各形状开口的面积比例设置，均能确保显示区与非显示区的交界处处第一子开口的尺寸大小均匀，同时还能使该显示基板在工艺过程中和过程后内部膜层中向外释放的气体能够通过第一凹槽和第二子开口及时进行释放，从而避免释放气体将某些内部膜层之间顶开形成小缝隙或小空腔，进而避免生产过程中各膜层通过小缝隙或小空腔吸收水汽而产生不良。
本实施例中显示基板的其他结构以及制备方法与上述实施例中相同，此处不再赘述。
本公开实施例还提供一种显示面板，包括上述显示基板。
通过采用上述显示基板，能够提升该显示面板的显示效果，同时还能避免该显示面板在生产过程中出现吸水不良。
本公开实施例所提供的显示面板可以为OLED面板、OLED电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。
本发明以2020年09月10日提交的申请号为PCT/CN2020/114589的PCT国际专利申请为基础，根据《专利法》中相关法规主张优先权，该申请的全部内容作为参照引入本申请中。

Claims (18)

  1. 一种显示基板，其特征在于，包括：
    基板；
    设置在所述基板上的像素限定层；
    所述显示基板还包括显示区，非显示区和透光区，所述显示区和所述非显示区至少部分围绕所述透光区；
    所述像素限定层由所述显示区延伸至所述非显示区；
    所述像素限定层中开设有第一开口，所述第一开口包括多个第一子开口和多个第二子开口；所述多个第一子开口分布于所述显示区，所述多个第二子开口分布于所述非显示区；且所述第二子开口比所述第一子开口更靠近所述透光区。
  2. 根据权利要求1所述的显示基板，其特征在于，所述第一子开口中设置有第一电极层和发光功能层；
    所述基板包括像素电路，所述像素电路包括驱动晶体管，所述驱动晶体管与所述第一电极层电连接；
    所述第一电极层和所述发光功能层沿远离所述基板的方向叠置；
    所述第二子开口中设置有所述发光功能层；
    所述显示基板还包括第二电极层，所述第二电极层设置于所述像素限定层的背离所述基板的一侧，且所述第二电极层覆盖所述第一子开口和所述第二子开口；
    所述驱动晶体管在所述基板上的正投影与所述第二子开口在所述基板上的正投影不重叠。
  3. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包 括信号线，所述信号线设置于所述像素限定层的靠近所述基板的一侧，所述信号线由所述显示区延伸至所述非显示区，且在所述非显示区中所述信号线包括弧线部分；
    所述弧线部分至少部分围绕所述透光区设置，且所述弧线部分与所述第二子开口在所述基板上的正投影至少部分重叠。
  4. 根据权利要求3所述的显示基板，其特征在于，所述信号线包括数据线。
  5. 根据权利要求2所述的显示基板，其特征在于，沿所述透光区的径向方向，所述第二子开口的分布区域的宽度范围为2～8倍的所述第二子开口沿其径向的宽度。
  6. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括围堰，所述围堰位于所述非显示区，且至少部分围绕所述透光区；
    所述围堰围绕于所述透光区的边缘，所述第二子开口围绕所述围堰分布于所述围堰的背离所述透光区的一侧；
    所述围堰与所述第二子开口的分布区域之间的最短间隔距离大于0且小于300微米。
  7. 根据权利要求2所述的显示基板，其特征在于，还包括触控膜层，所述触控膜层设置于所述第二电极层的背离所述基板的一侧；
    所述触控膜层包括触控电极；所述触控电极呈网格状；所述触控电极在所述基板上的正投影与所述像素限定层在所述基板上的正投影区域至少部分交叠。
  8. 根据权利要求7所述的显示基板，其特征在于，所述触控电极在所述基板上的正投影与所述第二子开口之间的所述像素限定层在所述基板上的正投影至少部分交叠。
  9. 根据权利要求1所述的显示基板，其特征在于，所述第一子开口与所述第二子开口的尺寸差小于设定阈值。
  10. 根据权利要求1所述的显示基板，其特征在于，所述第二子开口包括第一形状开口、第二形状开口和第三形状开口；
    所述第一形状开口、所述第二形状开口和所述第三形状开口的大小不同；
    两个所述第一形状开口、一个所述第二形状开口和一个所述第三形状开口组成一个开口周期；所述非显示区内分布有多个所述开口周期。
  11. 根据权利要求10所述的显示基板，其特征在于，所述开口周期内，两个所述第一形状开口之间的间距范围为6～27μm；
    所述第一形状开口与所述第二形状开口之间的间距范围为15～30μm；
    所述第二形状开口与所述第三形状开口之间的间距范围为15～30μm；
    所述第一形状开口与所述第三形状开口之间的间距范围为50～80μm。
  12. 根据权利要求10所述的显示基板，其特征在于，所述第一形状开口与所述第三形状开口之间的间距是所述第一形状开口与所述第二形状开口之间的间距的1.5～2.5倍；
    所述第一形状开口与所述第二形状开口之间的间距是所述第二形状开口与所述第三形状开口之间的间距的0.8～1.2倍；
    两个所述第一形状开口之间的间距是所述第一形状开口与所述第二形 状开口之间的间距的0.6～1倍。
  13. 根据权利要求1所述的显示基板，其特征在于，所述第一子开口与所述第二子开口的排布均匀度相同。
  14. 根据权利要求1所述的显示基板，其特征在于，所述显示区围绕于所述非显示区的外围；
    或者，所述非显示区位于所述显示区的一个角落处；
    或者，所述非显示区位于所述显示区的一侧边缘处。
  15. 根据权利要求2所述的显示基板，其特征在于，还包括平坦层，所述平坦层设置于所述像素限定层的靠近所述基板的一侧；
    所述基板还包括基底，所述像素电路设置在所述基底上，所述平坦层中开设有过孔，所述第一电极层通过所述过孔连接所述像素电路中的所述驱动晶体管。
  16. 一种显示面板，其特征在于，包括权利要求1-15任意一项所述的显示基板。
  17. 一种显示基板的制备方法，其特征在于，包括：
    制备基板；
    在所述基板上制备像素限定层；
    所述显示基板还包括显示区，非显示区和透光区，所述显示区和所述非显示区至少部分围绕所述透光区；所述像素限定层由所述显示区延伸至所述非显示区；
    制备所述像素限定层包括：形成所述像素限定层的图形，并在所述像 素限定层中开设第一开口；
    所述第一开口包括多个第一子开口和多个第二子开口；所述多个第一子开口分布于所述显示区，所述多个第二子开口分布于所述非显示区；且所述第二子开口比所述第一子开口更靠近所述透光区。
  18. 根据权利要求17所述的显示基板的制备方法，其特征在于，通过一次构图工艺形成所述像素限定层的图形和所述第一开口的图形。
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