WO2022051913A1 - 晶体振荡器、芯片和电子设备 - Google Patents

晶体振荡器、芯片和电子设备 Download PDF

Info

Publication number
WO2022051913A1
WO2022051913A1 PCT/CN2020/114079 CN2020114079W WO2022051913A1 WO 2022051913 A1 WO2022051913 A1 WO 2022051913A1 CN 2020114079 W CN2020114079 W CN 2020114079W WO 2022051913 A1 WO2022051913 A1 WO 2022051913A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
circuit
multiplying
miller
crystal oscillator
Prior art date
Application number
PCT/CN2020/114079
Other languages
English (en)
French (fr)
Inventor
张孟文
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2020/114079 priority Critical patent/WO2022051913A1/zh
Priority to US17/484,841 priority patent/US11482969B2/en
Publication of WO2022051913A1 publication Critical patent/WO2022051913A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/06—Modifications of generator to ensure starting of oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H03B5/366—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device and comprising means for varying the frequency by a variable voltage or current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/003—Circuit elements of oscillators
    • H03B2200/005—Circuit elements of oscillators including measures to switch a capacitor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0094—Measures to ensure starting of oscillations

Definitions

  • the embodiments of the present application relate to the field of electronic circuits, and more particularly, to a crystal oscillator, a chip, and an electronic device.
  • a crystal oscillator is a crystal component encapsulated with a quartz crystal and its oscillating circuit. It can use the piezoelectric effect to provide stable and accurate single-frequency oscillation in the state of resonance, thereby generating a processor , such as the clock frequency signal necessary for the central processing unit (Central Processing Unit, CPU) to execute instructions. Therefore, as long as it is an electronic product that contains a processor, it must contain at least one clock source, that is, a crystal oscillator must be included. Crystal oscillators are used in many electronic products. In order to ensure the normal operation of electronic products, the crystal oscillator's Performance is important.
  • Embodiments of the present application provide a crystal oscillator, a chip and an electronic device, which can improve the overall performance of the crystal oscillator.
  • a crystal oscillator including: an oscillation circuit, including: a crystal, an amplifier circuit, a first load capacitor and a second load capacitor, two ends of the crystal are respectively connected to the input end and the output end of the amplifier circuit , the first load capacitor and the second load capacitor are respectively connected to the first end and the second end of the crystal;
  • a first Miller multiplier circuit the input end and the output end of the first Miller multiplier circuit are respectively connected to both ends of the first load capacitor, and the first Miller multiplier circuit is used to increase the first load of the oscillator circuit capacitance, wherein the first load capacitance is the capacitance between the first end of the crystal and the ground.
  • a Miller multiplier circuit is connected in parallel at both ends of the load capacitor of the crystal oscillator, thereby increasing the load capacitance thereof, so that the crystal oscillator has a larger oscillating transconductance region when it starts to vibrate, Improved start-up stability of crystal oscillators.
  • the area occupied by the load capacitor can be reduced, and the circuit cost can be reduced.
  • the first Miller multiplying circuit is used to increase the first load capacitance to (A+1) times the capacitance of the first load capacitor, where A is the first Miller multiplying gain of the circuit.
  • the first Miller multiplying circuit includes: a first multiplying transistor and a second multiplying transistor, and the first multiplying transistor and the second multiplying transistor are connected in series to form an inverting amplifier circuit;
  • the gate of the first multiplying transistor is connected to the drain, the source of the first multiplying transistor is connected to the power supply voltage, and the drain of the first multiplying transistor is connected to the drain of the second multiplying transistor;
  • the gate of the second multiplying transistor is the input end of the first Miller multiplying circuit, which is connected to one end of the first load capacitor, and the drain of the second multiplying transistor is the output end of the first Miller multiplying circuit, which is connected to The other end of the first load capacitor and the source of the second multiplying transistor are connected to ground.
  • the first multiplier transistor works stably in a saturated state, which can provide a stable DC bias for the second multiplier transistor, and the entire first Miller multiplier circuit is easy to control and works in a relatively stable working state, At the same time, a more suitable gain can be provided, and the first load capacitance can be multiplied to a more suitable size range, so as to provide a suitable start-up transconductance range of the second oscillating transistor.
  • the crystal oscillator further includes: a first switch group, configured to connect the first Miller multiplier circuit and the first load capacitor when the crystal oscillator starts to vibrate, where the crystal oscillator is connected to the first load capacitor.
  • a first switch group configured to connect the first Miller multiplier circuit and the first load capacitor when the crystal oscillator starts to vibrate, where the crystal oscillator is connected to the first load capacitor.
  • a large-capacity load capacitor can be provided when the crystal starts to vibrate, and a small-capacity load capacitor can be provided to save the power consumption of the crystal oscillator after the crystal oscillator is maintained in the oscillation stage to save the power consumption of the crystal oscillator.
  • Oscillators can be used in more low-power application scenarios.
  • the first switch group includes: a first switch, a second switch and a third switch;
  • the first switch is connected to the gate of the second multiplication transistor and one end of the first load capacitor, the second switch is connected to the drain of the first multiplication transistor and the other end of the first load capacitor, and the third switch is connected the gate and supply voltage of the second multiplying transistor;
  • the first switch and the second switch are closed, and the third switch is opened, and the first Miller multiplier circuit is connected to the first load capacitor to increase the oscillation circuit the first load capacitance;
  • the third switch When the crystal oscillator maintains oscillation, the third switch is closed, the first switch and the second switch are open, and the first load capacitance of the oscillation circuit is equal to the capacitance of the first load capacitor.
  • the first Miller multiplying circuit further includes:
  • each first adjustment transistor in the at least one first adjustment transistor is connected to the source and drain of the first multiplication transistor, respectively, in the at least one first adjustment transistor
  • the gate of each first regulating transistor is connected to a gate control voltage.
  • the first Miller multiplying circuit further includes:
  • At least one first adjustment switch the at least one first adjustment switch is connected to the at least one first adjustment transistor in a one-to-one correspondence, and the first adjustment switch is used to control whether the first adjustment transistor is connected to the first multiplier transistor.
  • the at least one first adjustment switch is used to adjust the transconductance of the first multiplying transistor, so as to adjust the gain A of the first Miller multiplying circuit.
  • the first load capacitance in the crystal oscillator is adjusted to an appropriate value, so that the crystal oscillator is easy to start-up, and at the same time, it is also Adjusting the oscillation frequency of crystal oscillators provides a new means.
  • the at least one first regulating transistor is a plurality of first regulating transistors
  • the plurality of first regulating transistors are transistors of the same structure.
  • the first Miller multiplying circuit further includes:
  • At least one second regulating transistor, the gate, source and drain of each second regulating transistor of the at least one second regulating transistor are respectively connected to the gate, source and drain of the second multiplying transistor.
  • the first Miller multiplying circuit further includes:
  • At least one second adjustment switch the at least one second adjustment switch is connected to the at least one second adjustment transistor in a one-to-one correspondence, and the second adjustment switch is used to control whether the second adjustment transistor is connected to the second multiplying transistor .
  • the at least one second adjustment switch is used to adjust the transconductance of the second multiplying transistor, so as to adjust the gain A of the first Miller multiplying circuit.
  • the at least one second regulating transistor is a plurality of second regulating transistors
  • the plurality of second regulating transistors are transistors of the same structure.
  • the structure of the at least one second regulating transistor is the same as that of the second multiplying transistor.
  • the amplifier circuit includes a first oscillation transistor, a second oscillation transistor and a feedback resistor, and the first oscillation transistor, the second oscillation transistor and the feedback resistor form an inverting amplifier circuit;
  • the gate of the first oscillation transistor is connected to the gate control voltage, the drain of the first oscillation transistor is connected to the second end of the crystal, and the source of the first oscillation transistor is connected to the power supply voltage;
  • the gate of the second oscillation transistor is connected to the first end of the crystal, the drain of the second oscillation transistor is connected to the second end of the crystal, and the source of the second oscillation transistor is connected to the ground;
  • Two ends of the feedback resistor are respectively connected to two ends of the crystal.
  • the ratio of the width to length ratio of the second multiplication transistor to the width to length ratio of the second oscillation transistor is used to adjust the transconductance of the second multiplication transistor and the transconductance of the first multiplication transistor , to adjust the gain A of the first Miller multiplier circuit.
  • the ratio of the width to length ratio of the second adjustment transistor to the width to length ratio of the first oscillation transistor is used to adjust the transconductance of the first multiplication transistor, so as to adjust the first Miller multiplication Gain A of the circuit.
  • it further includes: a second Miller multiplying circuit, the input end and the output end of the second Miller multiplying circuit are respectively connected to two ends of the second load capacitor, the second Miller multiplying circuit The circuit is used to increase the second load capacitance of the oscillation circuit, wherein the second load capacitance is the capacitance between the second end of the crystal and the ground.
  • the circuit structure of the second Miller multiplying circuit is the same as the circuit structure of the first Miller multiplying circuit.
  • a chip including: the first aspect or the crystal oscillator in any possible implementation manner of the first aspect.
  • the chip is a clock chip, and the clock chip is used to provide a clock signal.
  • a third aspect provides an electronic device, including: the second aspect or a chip in any possible implementation manner of the second aspect.
  • Figure 1 is a schematic diagram of the structure of a typical crystal oscillator.
  • Figure 2 is a root locus diagram of the closed-loop transfer function of a crystal oscillator with different load capacitances.
  • FIG. 3 is an equivalent circuit diagram of the crystal in FIG. 1 .
  • FIG. 4 is a schematic structural block diagram of a crystal oscillator according to an embodiment of the present application.
  • FIG. 5 is a circuit structure diagram of a crystal oscillator according to an embodiment of the present application.
  • FIG. 6 is a schematic structural block diagram of another crystal oscillator according to an embodiment of the present application.
  • the embodiments of the present application may be applied to an electronic device or an electronic system including a processor, where the processor may be an integrated circuit chip and has signal processing capability.
  • the processor can be a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable Logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the general-purpose processor can be a microprocessor or the processor can also be any conventional processor or the like.
  • FIG. 1 is a schematic diagram of a typical structure of a crystal oscillator 100 .
  • the crystal oscillator 100 is a Pierce oscillator (Pierce oscillator, also called a Pierce crystal oscillator) structure.
  • the crystal oscillator 100 includes a first transistor 110 , a second transistor 120 , a crystal 130 , a first capacitor 140 , a second capacitor 150 and a feedback resistor 160 .
  • the gate of the first transistor 110 is connected to the gate control voltage V bp , the source of the first transistor is connected to the power supply voltage V cc , the drain of the first transistor 110 is connected to the drain of the second transistor 120 , the second The drain of the transistor 120 is connected to the ground, that is, the first transistor 110 and the second transistor 120 form a connection structure of an inverting amplifier circuit.
  • the first transistor 110 acts as a current source to provide bias to the second transistor 120, the feedback resistor 160 and the second transistor 120 form negative feedback to stabilize the DC voltage of V a and V b , and the first capacitor 140 and the second capacitor 150 act as a crystal oscillator
  • the load capacitance of 100, the first transistor 110 and the second transistor 120 are used to provide transconductance for the start-up and sustain oscillation of the crystal 130.
  • the crystal oscillator 100 shown in FIG. 1 has the following problems:
  • the transconductance required for the crystal oscillator 100 to start oscillating is larger than the transconductance required to maintain oscillation, and an excessively large transconductance or an excessively small transconductance will cause the oscillator not to oscillate. Therefore, the transconductance of the first transistor 110 and the second transistor 120 , especially the transconductance of the second transistor 120 needs to be designed in a proper range, otherwise the oscillator cannot start-up. There are many factors for determining the transconductance interval, one of which is related to the load capacitance of the crystal oscillator 100 , that is, related to the capacitances of the first capacitor 140 and the second capacitor 150 in FIG. 1 .
  • the capacitance of the load capacitors (the first capacitor 140 and the second capacitor 150 ) of the crystal oscillator 100 is very small, which will cause the transconductance interval in which the crystal oscillator 100 can oscillate to become very small, so A challenge is presented to setting a reasonable transconductance.
  • the deviation of the transconductance can be as high as ⁇ 50% or more, which may cause the crystal oscillator to not vibrate, thereby affecting its yield.
  • Figure 2 shows the root locus diagram of the closed-loop transfer function of a crystal oscillator with different load capacitances.
  • the root locus diagram is a locus diagram of the change of the zero and pole of the transfer function with the gain.
  • the real axis of the abscissa in the figure and the imaginary axis of the ordinate is the zero and pole.
  • the crystal oscillator starts to oscillate.
  • the oscillating transconductance region of the crystal oscillator is 0.199 ⁇ s to 199.5 ⁇ s.
  • the oscillating transconductance region of the crystal oscillator is 1.259 ⁇ s to 3162 ⁇ s. Therefore, when the load capacitance is increased, the oscillating transconductance range of the crystal oscillator is greatly increased. Even if there are influences of different processes, temperatures and voltages, resulting in the deviation of the transconductance, due to the oscillating transconductance range of the crystal oscillator If it is larger, the crystal oscillator can still start normally.
  • FIG. 3 shows an equivalent circuit diagram of the crystal 130 in FIG. 1 .
  • the crystal 130 is equivalent to the equivalent circuit shown by the dotted box in the figure, including a parallel capacitor 131 , an equivalent capacitor 132 , an equivalent inductor 133 and an equivalent resistor 134 .
  • the crystal oscillator can oscillate as long as the impedance Z C viewed from both ends of the parallel capacitor 131 to the circuit and the negative resistance at the resonance frequency is greater than the resistance R S of the equivalent resistance 134 of the crystal.
  • C 1 is the capacitance of the first capacitor 140
  • C 2 is the capacitance of the second capacitor 150
  • C 3 is the capacitance of the parallel capacitor 131
  • g m is the transconductance of the second transistor 120 .
  • the minimum value g m,min and the maximum value g m,max of g m can be calculated, and the calculation expressions of the two are as follows:
  • g m,min and g m,max can be further simplified to the following expressions:
  • the value range of the transconductance g m of the second transistor 120 is shown in the following expression:
  • the value interval of the transconductance g m of the second transistor 120 is proportional to the capacitance C 1 of the first capacitor 140 and the capacitance C 2 of the second capacitor 150 .
  • the embodiments of the present application use the Miller effect to multiply the load capacitance in the crystal oscillator.
  • a large load capacitance is multiplied to be able to generate Large oscillating transconductance region, thus improving the start-up stability of crystal oscillators.
  • the area occupied by the load capacitor can be reduced, the circuit cost can be reduced, and the miniaturization development of the crystal oscillator can be facilitated.
  • FIG. 4 shows a schematic structural block diagram of a crystal oscillator provided by an embodiment of the present application.
  • the crystal oscillator 200 includes an oscillation circuit and a first Miller multiplier circuit 250 , wherein the oscillation circuit includes an amplifying circuit 210 , a crystal 220 , a first load capacitor 230 and a second load capacitor 240 .
  • the amplifier circuit 210 is connected in parallel with the crystal 220 , and the first load capacitor 230 and the second load capacitor 240 are connected to the first end and the second end of the crystal 220 , respectively.
  • the first Miller multiplying circuit 250 is connected in parallel with the first load capacitor 230 . In other words, the input end and the output end of the first Miller multiplying circuit are connected to both ends of the first load capacitor 230 , respectively.
  • the amplifying circuit 210 may be an inverting amplifying circuit, for example, an inverting amplifying circuit formed by the first transistor 110 and the second transistor 120 in the Pierce crystal oscillator shown in FIG. 1 . , therefore, the first transistor and the second transistor in the amplifying circuit 210 can provide transconductance for the oscillation of the crystal, which is beneficial to the rapid start-up of the crystal.
  • the amplifying circuit 210 can be other than the inverting amplifying circuit in the Pierce crystal oscillator, and other types of amplifying circuits in the related art, and the specific circuit structure of the amplifying circuit 210 is not described in this embodiment of the present application. limited.
  • the crystal 220 , the first load capacitor 230 and the second load capacitor 240 in the embodiment of the present application may be the crystal 130 , the first capacitor 140 and the second capacitor 150 in the Pierce crystal oscillator 100 in FIG. 1 , respectively.
  • the circuit structure formed by the oscillation circuit in the embodiment of the present application is the circuit structure of the Pierce crystal oscillator shown in FIG. 1 .
  • the first Miller multiplier circuit 250 is connected in parallel with the first load capacitor 230 to increase the first load capacitance of the oscillation circuit, wherein the first load capacitance is the connection between the first end of the crystal 220 and the ground. capacitance.
  • the first Miller multiplier circuit 250 may be an inverting amplifier circuit. According to the principle of the Miller effect, in the inverting amplifier circuit, the capacitance between the input and the output is equivalent to the amplification effect of the amplifier. The capacitance value of the input terminal will be expanded by (A+1) times, where A is the gain (also called the amplification factor) of the inverting amplifier circuit.
  • the first Miller multiplier circuit 250 is used to increase the first load capacitance to be (A+1) times the capacitance of the first load capacitor 230 , and A is the first Miller multiplier gain of circuit 250, and A is a positive number.
  • a Miller multiplier circuit is connected in parallel at both ends of the load capacitor of the crystal oscillator, thereby increasing the load capacitance thereof, so that the crystal oscillator has a larger oscillating transconductance region when it starts to vibrate, Improved start-up stability of crystal oscillators.
  • the area occupied by the load capacitor can be reduced, and the circuit cost can be reduced.
  • FIG. 5 shows a circuit structure diagram of a crystal oscillator provided by an embodiment of the present application.
  • the amplifying circuit 210 may include a first oscillation transistor 211 , a second oscillation transistor 212 and a feedback resistor 213 .
  • the above-mentioned first Miller multiplying circuit 250 may include a first multiplying transistor 251 and a second multiplying transistor 252, the two multiplying transistors are used to form an inverting amplifier, and the first load capacitor 230 is connected to the input terminal V a of the inverting amplifier. and the output terminal V oa , which is also the first terminal of the crystal 220 .
  • the first multiplying transistor 251 is a P-channel metal oxide semiconductor (Positive Channel Metal Oxide Semiconductor, PMOS) transistor
  • the second multiplying transistor 252 is an n-channel metal oxide semiconductor.
  • the first Miller multiplying circuit 250 is a class A amplifier circuit, wherein the gate (Gate) of the first multiplying transistor 251 is connected to the drain (Drain), and the The source (Source) is connected to the power supply voltage V cc , so that the first multiplying transistor 251 operates in the saturation region.
  • the gate of the second multiplying transistor 252 is the input V a of the first Miller multiplying circuit 250 and is connected to one end of the first load capacitor 230 , and the drain of the second multiplying transistor 252 is connected to the drain of the first multiplying transistor 251 , which is the output terminal V oa of the first Miller multiplying circuit 250 , which is connected to the other terminal of the first load capacitor 230 , and the source of the second multiplying transistor 252 is connected to the ground V gd .
  • the gain of the first Miller multiplying circuit 250 is A , looking from the input terminal Va of the first multiplying circuit 250 to the first load capacitor 230, the capacitance between Va and V gd , that is, The first load capacitance C′ 1 of the oscillation circuit is multiplied to (1+A)C 1 , where C 1 is the capacitance of the first load capacitor 230 .
  • the first Miller multiplier circuit 250 can also be other types of inverting amplifiers, for example, the first multiplier
  • the gate of the transistor 251 is not connected to the drain, but is connected to the bias voltage; for another example, the gates of the first multiplying transistor 251 and the second multiplying transistor 252 are connected as the input terminals of the first Miller multiplying circuit 250 .
  • the specific circuit structure of the first Miller multiplying circuit 250 is not limited in this embodiment of the present application.
  • the first Miller multiplying circuit 250 is designed as a circuit structure as shown in FIG. 5 .
  • the first multiplying transistor 251 works stably in a saturated state and can provide a stable DC bias for the second multiplying transistor 252 .
  • the first Miller multiplier circuit 250 is easy to control and works in a relatively stable working state, and at the same time, it can provide a relatively appropriate gain, multiply the first load capacitance to a relatively appropriate size range, so as to provide the second oscillation transistor 212 suitable for The startable transconductance range of .
  • the crystal oscillator 200 only includes the first Miller multiplying circuit 250 , which is connected in parallel to both ends of the first load capacitor 230 for multiplying the first load capacitor.
  • FIG. 6 and FIG. 7 show structural block diagrams and schematic circuit structural diagrams of another two examples of crystal oscillators 200 provided by the embodiments of the present application.
  • the crystal oscillator 200 further includes: a second Miller multiplying circuit 260 connected in parallel to both ends of the second load capacitor 240 for multiplying the second load capacitor, wherein the second The load capacitance is the capacitance between the second end of the crystal 220 and the ground.
  • the circuit structure of the second Miller multiplying circuit 260 is the same as the circuit structure of the first Miller multiplying circuit 250 shown in FIG. 5 above, which includes a third multiplying transistor 261 and a fourth The inverting amplifier formed by the multiplying transistor 262, the second load capacitor 240 is connected between the input terminal V b and the output terminal V ob of the inverting amplifier, and the input terminal V b is also the second terminal of the crystal 220 .
  • the second Miller multiplying circuit 260 can also be other types of inverting amplifier circuits, and the specific circuit type and circuit structure can be the same as those of the first meter.
  • the Lex multiplication circuits 250 are the same or different, which is not specifically limited in this embodiment of the present application.
  • the load capacitance in the crystal oscillator is multiplied by the Miller multiplier circuit, thereby facilitating the start-up of the crystal oscillator and improving the start-up stability.
  • the capacitance that maintains the crystal oscillation is often smaller than the capacitance required for the start-up, especially in low-power application scenarios, only a small load capacitance is required. Capacitors reserved for stability are wasted.
  • an embodiment of the present application provides a crystal oscillator including a switch unit group, which can provide a large-capacity load capacitance when the crystal starts to oscillate, and provides a small-capacity load capacitance after the oscillation is maintained during the oscillation stage.
  • the load capacitance can save the power consumption of the crystal oscillator, so that the crystal oscillator can be used in more low-power application scenarios.
  • the crystal oscillator 200 may include: a first switch unit group, the first switch group is used to connect the above-mentioned first Miller multiplier circuit and the above-mentioned first load capacitor when the crystal oscillator starts to vibrate, and when the crystal oscillator starts, the above-mentioned first Miller multiplier circuit and the above-mentioned first load capacitor are connected. When the oscillator keeps oscillating, the first Miller multiplier circuit and the first load capacitor are disconnected.
  • FIG. 8 shows a schematic diagram of the circuit structure of another crystal oscillator 200 .
  • the first switch group in the crystal oscillator 200 includes: a first switch 253 , a second switch 254 and a third switch 255 .
  • the first switch 253 is connected to the gate of the second multiplication transistor 252 and one end (V a ) of the first load capacitor 230
  • the second switch 254 is connected to the drain of the first multiplication transistor 251 and the other end of the first load capacitor 230 (V oa )
  • the third switch 255 is connected to the gate of the second multiplying transistor 252 and the power supply voltage V cc .
  • the first load capacitor 230 is connected between the input terminal and the output terminal of the first Miller multiplier circuit 250 to provide the first load The capacitance is multiplied.
  • the third switch 255 When the third switch 255 is turned on, and the first switch 253 and the second switch 254 are turned off at the same time, the second multiplying transistor 252 is turned on, and one end (V oa ) of the first load capacitor 230 is grounded. At this time, the first load capacitor is the capacitance of the first load capacitor 230 .
  • the state of each switch in the first switch group may be controlled by the control unit, wherein, at the same moment, the switch states of the first switch 253 and the second switch 254 are kept consistent, and are consistent with the state of each switch in the first switch group.
  • the switching states of the third switch 255 are reversed.
  • the number and positions of the switches in the first switch group in FIG. 8 are only illustrative, and the switches may be located in other positions in the circuit besides the positions shown in FIG. 8 , for example: the second A switch 254 may be used to connect the source of the first multiplying transistor 251 to the supply voltage Vcc , and/or a third switch 255 may be used to connect the gate of the second multiplying transistor 252 to other supply voltages, and so on.
  • the embodiments of the present application do not specifically limit the switch positions in the first switch group, and aim to control whether the first Miller multiplier circuit 250 is connected to the first load capacitor 230 through the first switch group.
  • the crystal oscillator 200 may further include: a second switch unit group, the second switch group is used to connect the second Miller multiplier circuit and the second load capacitor when the crystal oscillator starts to vibrate, and When the crystal oscillator keeps oscillating, the second Miller multiplier circuit and the second load capacitor are disconnected.
  • FIG. 9 shows a schematic diagram of the circuit structure of another crystal oscillator 200 .
  • the second switch group in the crystal oscillator 200 includes: a fourth switch 263 , a fifth switch 264 and a sixth switch 265 .
  • the fourth switch 263 is connected to the gate of the fourth multiplication transistor 262 and one end (V b ) of the second load capacitor 240
  • the fifth switch 264 is connected to the drain of the third multiplication transistor 261 and the other end of the second load capacitor 240 (V ob ).
  • the sixth switch 265 is connected to the gate of the fourth multiplication transistor 262 and the power supply voltage V cc .
  • the second load capacitor 240 is connected between the input terminal and the output terminal of the second Miller multiplying circuit 260 to The load capacitance is multiplied.
  • the fourth multiplying transistor 262 is turned on, and one end (V ob ) of the second load capacitor 240 is grounded. At this time, the second load capacitor is The capacitance of the second load capacitor 240 .
  • the state of each switch in the second switch group may be controlled by the control unit, wherein, at the same moment, the switch states of the fourth switch 263 and the fifth switch 264 remain consistent, and are consistent with the state of each switch in the second switch group.
  • the switching state of the sixth switch 265 is reversed.
  • control unit may control the switch states of the first switch 253 , the second switch 254 , the fourth switch 263 , and the fifth switch 264 to be consistent, and control the third switch 255 and the third switch 255 .
  • the switch states of the six switches 265 are the same.
  • the number and positions of the switches in the second switch group in FIG. 9 are only illustrative, and the switches may be located at other positions in the circuit besides the positions shown in FIG. 9 , for example, the fifth switch 264
  • the sixth switch 265 may be used to connect the source of the third multiplication transistor 261 to the supply voltage Vcc , and/or the sixth switch 265 may be used to connect the gate of the fourth multiplication transistor 262 to other supply voltages, and so on.
  • the embodiments of the present application do not specifically limit the switch positions in the second switch group.
  • the first load capacitor 230 may be connected in parallel to the first Miller multiplying circuit 250 to multiply the first load capacitance, and/or the second load capacitor 240 may be connected in parallel to the second Miller multiplying circuit
  • the circuit 260 multiplies the second load capacitance.
  • the multiplication amount of the load capacitance is related to the gain of the Miller multiplier circuit.
  • the gain calculation formula is as follows:
  • g m51 and g m52 are the transconductance of the first multiplication transistor 251 and the transconductance of the second multiplication transistor 252, respectively, and the multiplication increment of the load capacitance can be adjusted by adjusting g m51 and g m52 .
  • the calculation formula of the transconductance g m51 of the first multiplying transistor 251 is as follows:
  • ⁇ is the electron mobility
  • C ox is the gate oxide capacitance of the first multiplying transistor 251
  • W/L is the aspect ratio of the first multiplying transistor 251
  • I d51 is the drain current of the first multiplying transistor 251 .
  • the second multiplication transistor 252 is mirrored to the second oscillation transistor 212 in the amplifying circuit, and the calculation formulas of the drain current I d52 of the second multiplication transistor 252 and the transconductance g m52 are as follows:
  • N is the ratio of the width to length ratio of the second multiplication transistor 252 to the width to length ratio of the second oscillation transistor 212
  • IB is the drain current of the second oscillation transistor 212, and is also the drain current of the first oscillation transistor 211
  • g m12 is the transconductance of the second oscillation transistor 212 .
  • the transconductance of the first multiplication transistor 251 can be adjusted by adjusting the process conditions of the first multiplication transistor 251, such as the aspect ratio, etc.; and/or the drain of the first multiplication transistor 251 can be adjusted
  • the pole current is used to adjust the transconductance of the first multiplying transistor 251 , thereby adjusting the gain of the first Miller multiplying circuit 250 .
  • the transconductance of the second multiplication transistor 252 can also be adjusted by adjusting the process conditions of the second multiplication transistor 252, such as the aspect ratio, etc.; and/or, the drain current of the second multiplication transistor 252 can be adjusted to adjust the second multiplication transistor 252.
  • the transconductance of the transistor 252 is multiplied, thereby adjusting the gain of the first Miller multiplier circuit 250 .
  • circuit structure of the second Miller multiplying circuit 260 shown in FIG. 7 and FIG. 9 is consistent with the circuit structure of the first Miller multiplying circuit 250, and the calculation method of its gain and the adjustment method of its gain can be referred to.
  • the adjustment method of the first Miller multiplying circuit 250 in the context will not be repeated here.
  • the transconductance g m52 of the second multiplication transistor 252 can be adjusted in the design and manufacturing stages by adjusting the above N, that is, the ratio of the width to length ratio of the second multiplication transistor 252 to the width to length ratio of the second oscillation transistor 212 , thereby adjusting the second multiplication transistor 252 .
  • a gain A of the Miller multiplier circuit 250 is adjusting the Miller multiplier circuit 250 .
  • FIG. 10 shows a schematic diagram of the circuit structure of another crystal oscillator 200 in this embodiment.
  • the first Miller multiplying circuit 250 further includes:
  • n second regulating transistors ( 2521 to 252n ), the gate, source and drain of each of the n second regulating transistors are connected to the gate, source and drain of the second multiplying transistor 252 , respectively drain, where n is a positive integer.
  • the first Miller multiplying circuit 250 further includes: n second adjustment switches ( 2511 to 251n ), the n second adjustment switches are connected to the n second adjustment transistors in a one-to-one correspondence, and the second adjustment switches The adjustment switch is used to control whether to connect the second adjustment transistor to the second multiplying transistor 252 .
  • the n second adjustment switches are connected to the drains of the n second adjustment transistors and one end (V oa ) of the first load capacitor 230 in a one-to-one correspondence.
  • the n second adjustment transistors may all be NMOS transistors. Further, the n second adjustment transistors may be transistors of the same structure. Furthermore, the n second adjustment transistors may be transistors with the same structure as the second multiplying transistor 252 . With this embodiment, the drain current I d52 and the transconductance g m52 of the second multiplying transistor 252 after the second adjusting transistor can be more conveniently adjusted, thereby adjusting the gain A of the first Miller multiplying circuit 250 .
  • n second adjustment transistors are transistors with the same structure as the second multiplication transistor 252 , in the circuit structure shown in FIG. 10 , the second multiplication transistor 252 after the second adjustment transistor is connected
  • the calculation formulas of drain current I d52 and transconductance g m52 are as follows:
  • i represents the number of the second regulating transistors connected to the second multiplying transistor 252, 1 ⁇ i ⁇ n, and i is a positive integer.
  • N is the ratio of the width to length ratio of the second multiplication transistor 252 to the width to length ratio of the second oscillation transistor 212
  • IB is the drain current of the second oscillation transistor 212
  • g m12 is the transconductance of the second oscillation transistor 212 .
  • one or more parameters of i and N can be adjusted to adjust the transconductance g m52 of the second multiplication transistor 252 after the parallel transistors.
  • the transconductance g m51 of the first multiplying transistor 251 can be adjusted by adjusting the drain current I d51 of the first multiplying transistor 251 , thereby adjusting the gain A of the first Miller multiplying circuit 250 .
  • FIG. 11 shows a schematic diagram of the circuit structure of another crystal oscillator 200 in this embodiment.
  • the first Miller multiplying circuit 250 further includes:
  • each of the m first adjustment transistors 2531 to 253m
  • the source and drain of each of the m first adjustment transistors are connected to the source and drain of the first multiplying transistor 251, respectively, the m first adjustment transistors
  • the gate of each of the first regulating transistors is connected to a gate control voltage V bp , where m is a positive integer.
  • the first Miller multiplying circuit 250 further includes:
  • the m first adjustment switches (2541 to 254m), the m first adjustment switches are connected to the m first adjustment transistors in a one-to-one correspondence, and the first adjustment switches are used to control whether the first adjustment transistors are connected to The first multiplying transistor 251 .
  • the m first adjustment switches are connected to the drains of the m first adjustment transistors and the drains of the first multiplying transistors 251 in a one-to-one correspondence.
  • the m first adjustment transistors are all PMOS transistors, and further, the m first adjustment transistors may be transistors with the same structure.
  • the m first adjustment transistors are transistors of the same structure, and the drain current of each first adjustment transistor is I d53 , then in the circuit structure shown in FIG. 11 , the first multiplication transistor
  • the formula for calculating the drain I d51 of 251 is as follows:
  • I d51 I d52 -jI d53 ;
  • I d52 NI B
  • N is the ratio of the width to length ratio of the second multiplication transistor 252 to the width to length ratio of the second oscillation transistor 212
  • I B is the drain current of the second oscillation transistor 212
  • j represents the parallel connection to the second oscillation transistor 212 .
  • the number of the first adjustment transistors of the multiplying transistor 251 is 1 ⁇ j ⁇ m, and j is a positive integer.
  • the above m first adjustment transistors are transistors of the same structure, and the ratio of the width to length ratio of each first adjustment transistor to the width to length ratio of the first oscillation transistor 211 is M, then the The formulas for calculating the drain current I d53 of a regulating transistor, the drain I d51 of the first multiplying transistor 251 and the transconductance g m51 are as follows:
  • I d53 MI B
  • I d51 NI B -jMI B
  • the transconductance g m51 of the first multiplying transistor 251 can be adjusted by adjusting one or more parameters among j, M, and N.
  • the span of the second multiplying transistor 252 can be adjusted by controlling the number of the second adjusting transistors connected in parallel on the second multiplying transistor 252 in the actual use stage.
  • the conductance g m52 is adjusted, and the transconductance g m51 of the first multiplying transistor 251 is adjusted by adjusting the drain current I d51 of the first multiplying transistor 251 , thereby adjusting the gain A of the first Miller multiplying circuit 250 .
  • FIG. 12 shows a schematic diagram of a circuit structure of another crystal oscillator 200 in this embodiment.
  • the first Miller multiplying circuit 250 further includes: m first regulating transistors and m first regulating switches, and n second regulating transistors and n second regulating transistors Adjust the switch.
  • m first regulating transistors and m first regulating switches as well as the n second adjustment transistors and the n second adjustment switches, reference may be made to the relevant descriptions of FIG. 10 and FIG. 11 above, which will not be repeated here.
  • i represents the number of the second adjusting transistors connected to the second multiplying transistor 252, 1 ⁇ i ⁇ n, and i is a positive integer
  • N is the width-length ratio of the second multiplying transistor 252 and the width of the second oscillation transistor 212
  • the ratio of the length ratio, I B is the drain current of the second oscillation transistor 212
  • g m12 is the transconductance of the second oscillation transistor 212 .
  • the calculation formulas of the drain I d51 and the transconductance g m51 of the first multiplying transistor 251 are as follows:
  • I d51 iNI B -jMI B ,
  • j represents the number of the first regulating transistors connected to the first multiplying transistor 251, 1 ⁇ j ⁇ m, and j is a positive integer.
  • M is the ratio of the width to length ratio of the second adjustment transistor to the width to length ratio of the first oscillation transistor 211 .
  • the transconductance gm52 of the second multiplying transistor 252 and the transconductance gm52 of the first multiplying transistor 251 can be adjusted by controlling one or more parameters of i, j, M, and N. Derive g m51 to adjust the gain A of the first Miller multiplying circuit 250 .
  • the gain A of the first Miller multiplying circuit 250 by adjusting the gain A of the first Miller multiplying circuit 250, the first load capacitance in the crystal oscillator is adjusted to an appropriate value, so that the crystal oscillator is easy to start-up, and at the same time, the A new method is provided for adjusting the oscillation frequency of the crystal oscillator.
  • the circuit structure of the second Miller multiplying circuit 260 can be the same as that of any one of the first Miller multiplying circuits above.
  • the circuit structure of the multiplier circuit 250 is the same.
  • FIG. 13 shows a schematic diagram of a circuit structure of a preferred crystal oscillator 200 in the present application.
  • the crystal oscillator 200 includes a first Miller multiplying circuit 250 and a second Miller multiplying circuit 260 .
  • the circuit structure of the first Miller multiplying circuit 250 is the same as that of the first Miller multiplying circuit 250 in FIG. 12 .
  • the circuit structure of the second Miller multiplying circuit 260 is mirrored to that of the first Miller multiplying circuit 250 .
  • the second Miller multiplying circuit 260 may include: n third adjustment switches ( 2611 to 261n ) and n third adjustment transistors ( 2621 to 262n ).
  • the n third adjustment transistors are all NMOS transistors. Further, the n third adjustment transistors may be transistors of the same structure. Furthermore, the n third adjustment transistors may be transistors with the same structure as the fourth multiplication transistor 262 .
  • the second Miller multiplying circuit 260 may further include: m fourth adjustment switches (2641 to 264m) and m fourth adjustment transistors (2631 to 263m).
  • the m fourth adjustment transistors are all PMOS transistors, and further, the m fourth adjustment transistors may be transistors with the same structure.
  • the method for adjusting the gain of the second Miller multiplying circuit 260 can also refer to the method for adjusting the gain of the first Miller multiplying circuit 250 above, which will not be described in detail here.
  • the numbers of the third adjustment transistors and the third adjustment switches include but are not limited to n
  • the numbers of the fourth adjustment transistors and the fourth adjustment switches include but are not limited to n. m
  • the embodiments of the present application do not specifically limit this.
  • the second Miller multiplying circuit 260 in FIG. 13 is mirrored to the first Miller multiplying circuit 250 in FIG. 12 .
  • the second Miller multiplying circuit 260 may also be mirrored on the first Miller multiplying circuit 260 in FIG. 10 or FIG. 11 .
  • the structures of the first Miller multiplying circuit 250 and the second Miller multiplying circuit 260 may be the same or different, which are not specifically limited in this embodiment of the present application.
  • the first Miller multiplying circuit 250 may be the circuit structure shown in FIG. 10
  • the second Miller multiplying circuit 260 may be a mirror image The circuit structure shown in Figure 11 or Figure 12. If the structures of the first Miller multiplying circuit 250 and the second Miller multiplying circuit 260 are the same, the first Miller multiplying circuit 250 is the circuit structure shown in FIG. 10 , and the second Miller multiplying circuit 260 is a mirror image of FIG. 10 .
  • the circuit structure shown, alternatively, the first Miller multiplying circuit 250 is the circuit structure shown in FIG. 11
  • the second Miller multiplying circuit 260 is a mirror image of the circuit structure shown in FIG. 11 .
  • An embodiment of the present application further provides a chip, including the crystal oscillator in the various embodiments of the present application.
  • the chip may be a clock chip, such as a real time clock (Real Time Clock, RTC) chip, and the clock chip may provide clock signals for other types of chips such as processors.
  • RTC Real Time Clock
  • the embodiment of the present application also provides an electronic device, the electronic device includes: the chip in the above-mentioned embodiment.
  • the electronic device in this embodiment of the present application may be any device that requires a clock signal, such as a terminal device, a mobile phone, a tablet computer, a notebook computer, a desktop computer, a game device, a vehicle-mounted electronic device, or a wearable smart device such as portable or mobile computing devices, as well as other electronic devices such as electronic databases, automobiles, etc.
  • a terminal device such as a mobile phone, a tablet computer, a notebook computer, a desktop computer, a game device, a vehicle-mounted electronic device, or a wearable smart device such as portable or mobile computing devices, as well as other electronic devices such as electronic databases, automobiles, etc.

Landscapes

  • Oscillators With Electromechanical Resonators (AREA)

Abstract

一种晶体振荡器、芯片和电子设备，能够提高晶体振荡器的整体性能。一种晶体振荡器，包括：振荡电路，包括：晶体、放大电路、第一负载电容器和第二负载电容器，第一负载电容器和第二负载电容器分别连接于晶体的第一端和第二端；第一米勒倍增电路，第一米勒倍增电路的输入端与输出端分别连接于第一负载电容器的两端，第一米勒倍增电路用于增大振荡电路的第一负载电容，第一负载电容为晶体的第一端与地之间的电容。通过该技术方案，在晶体振荡器的负载电容器的两端并联米勒倍增电路，从而增大其负载电容，使得晶体振荡器在起振时具有较大的可振荡跨导区域，提高了晶体振荡器的起振稳定性。与此同时，能够减少负载电容器占用的面积，降低电路成本。

Description

晶体振荡器、芯片和电子设备 技术领域
本申请实施例涉及电子电路领域，并且更具体地，涉及一种晶体振荡器、芯片和电子设备。
背景技术
晶体振荡器(crystal oscillator)是一种封装有石英晶体及其振荡电路的晶体元件，能够利用压电效应(piezoelectric effect)，在共振的状态下提供稳定、精确的单频振荡，从而产生处理器，例如中央处理器(Central Processing Unit，CPU)执行指令所必须的时钟频率信号。因此，只要是包含处理器的电子产品，都至少包含一个时钟源，即必须包含晶体振荡器，晶体振荡器在许多电子产品当中都得以运用，在为了保证电子产品能够正常运行，晶体振荡器的性能十分重要。
因此，如何提高晶体振荡器的整体性能，是一项亟待解决的技术问题。
发明内容
本申请实施例提供一种晶体振荡器、芯片和电子设备，能够提高晶体振荡器的整体性能。
第一方面，提供一种晶体振荡器，包括：振荡电路，包括：晶体、放大电路、第一负载电容器和第二负载电容器，该晶体的两端分别连接于该放大电路的输入端与输出端，该第一负载电容器和该第二负载电容器分别连接于该晶体的第一端和第二端；
第一米勒倍增电路，该第一米勒倍增电路的输入端与输出端分别连接于该第一负载电容器的两端，该第一米勒倍增电路用于增大该振荡电路的第一负载电容，其中，该第一负载电容为该晶体的第一端与地之间的电容。
通过本申请实施例的技术方案，在晶体振荡器的负载电容器的两端并联米勒倍增电路，从而增大其负载电容，使得晶体振荡器在起振时具有较大的可振荡跨导区域，提高了晶体振荡器的起振稳定性。与此同时，能够减少负载电容器占用的面积，降低电路成本。
在一种可能的实现方式中，该第一米勒倍增电路用于将该第一负载电容 增大为该第一负载电容器的电容的(A+1)倍，A为该第一米勒倍增电路的增益。
在一种可能的实现方式中，该第一米勒倍增电路包括：第一倍增晶体管和第二倍增晶体管，该第一倍增晶体管和该第二倍增晶体管串联形成反相放大电路；
该第一倍增晶体管的栅极与漏极连接，该第一倍增晶体管的源极连接至电源电压，该第一倍增晶体管的漏极连接至该第二倍增晶体管的漏极；
该第二倍增晶体管的栅极为该第一米勒倍增电路的输入端，连接至该第一负载电容器的一端，该第二倍增晶体管的漏极为该第一米勒倍增电路的输出端，连接至该第一负载电容器的另一端，该第二倍增晶体管的源极连接至地。
通过本申请实施例的技术方案，第一倍增晶体管稳定工作在饱和状态，能够为第二倍增晶体管提供稳定的直流偏置，整个第一米勒倍增电路易于控制且工作在较为稳定的工作状态，与此同时，还能提供较为合适的增益，倍增第一负载电容至较为合适的大小范围，从而提供第二振荡晶体管合适的可起振跨导范围。
在一种可能的实现方式中，该晶体振荡器还包括：第一开关组，用于在该晶体振荡器起振时，连接该第一米勒倍增电路与该第一负载电容器，在该晶体振荡器维持振荡时，断开该第一米勒倍增电路与该第一负载电容器。
通过本申请实施例的技术方案，能够在晶体起振时提供大容量的负载电容，而在起振之后，维持振荡阶段，提供小容量的负载电容以节约晶体振荡器的功耗，使得该晶体振荡器可以用于更多的低功耗的应用场景中。
在一种可能的实现方式中，该第一开关组包括：第一开关，第二开关以及第三开关；
该第一开关连接该第二倍增晶体管的栅极以及该第一负载电容器的一端，该第二开关连接该第一倍增晶体管的漏极以及该第一负载电容器的另一端，该第三开关连接该第二倍增晶体管的栅极以及电源电压；
在该晶体振荡器起振时，该第一开关和该第二开关闭合，且该第三开关断开，该第一米勒倍增电路连接于该第一负载电容器，以增大该振荡电路的第一负载电容；
在该晶体振荡器维持振荡时，该第三开关闭合，且该第一开关和该第二 开关断开，该振荡电路的第一负载电容等于该第一负载电容器的电容。
在一种可能的实现方式中，该第一米勒倍增电路还包括：
至少一个第一调节晶体管，该至少一个第一调节晶体管中每个第一调节晶体管的源极和漏极分别连接至该第一倍增晶体管的源极和漏极，该至少一个第一调节晶体管中每个第一调节晶体管的栅极连接至栅极控制电压。
在一种可能的实现方式中，该第一米勒倍增电路还包括：
至少一个第一调节开关，该至少一个第一调节开关一一对应的连接于与该至少一个第一调节晶体管，该第一调节开关用于控制是否将该第一调节晶体管连接至该第一倍增晶体管。
在一种可能的实现方式中，该至少一个第一调节开关用于调整该第一倍增晶体管的跨导，以调整该第一米勒倍增电路的增益A。
在上述申请实施例中，通过调整第一米勒倍增电路的增益A，从而调整晶体振荡器中的第一负载电容至合适的值，从而使得晶体振荡器易于起振，与此同时，也为调节晶体振荡器的振荡频率提供了一种新的手段。
在一种可能的实现方式中，若该至少一个第一调节晶体管为多个第一调节晶体管，该多个第一调节晶体管为相同结构的晶体管。
在一种可能的实现方式中，该第一米勒倍增电路还包括：
至少一个第二调节晶体管，该至少一个第二调节晶体管中每个第二调节晶体管的栅极、源极和漏极分别连接至该第二倍增晶体管的栅极、源极和漏极。
在一种可能的实现方式中，该第一米勒倍增电路还包括：
至少一个第二调节开关，该至少一个第二调节开关一一对应的连接于该至少一个第二调节晶体管，该第二调节开关用于控制是否将该第二调节晶体管连接至该第二倍增晶体管。
在一种可能的实现方式中，该至少一个第二调节开关用于调整该第二倍增晶体管的跨导，以调整该第一米勒倍增电路的增益A。
在一种可能的实现方式中，若该至少一个第二调节晶体管为多个第二调节晶体管，该多个第二调节晶体管为相同结构的晶体管。
在一种可能的实现方式中，该至少一个第二调节晶体管的结构与该第二倍增晶体管的结构相同。
在一种可能的实现方式中，该放大电路包括第一振荡晶体管和第二振荡 晶体管和反馈电阻，该第一振荡晶体管、该第二振荡晶体管和该反馈电阻形成反相放大电路；
该第一振荡晶体管的栅极连接至栅极控制电压，该第一振荡晶体管的漏极连接至该晶体的第二端，该第一振荡晶体管的源极连接至电源电压；
该第二振荡晶体管的栅极连接至该晶体的第一端，该第二振荡晶体管的漏极连接至该晶体的第二端，该第二振荡晶体管的源极连接至地；
该反馈电阻的两端分别连接至该晶体的两端。
在一种可能的实现方式中，该第二倍增晶体管的宽长比与该第二振荡晶体管的宽长比之比用于调整该第二倍增晶体管的跨导以及该第一倍增晶体管的跨导，以调整该第一米勒倍增电路的增益A。
在一种可能的实现方式中，该第二调节晶体管的宽长比与该第一振荡晶体管的宽长比之比用于调整该第一倍增晶体管的跨导，以调整该第一米勒倍增电路的增益A。
在一种可能的实现方式中，还包括：第二米勒倍增电路，该第二米勒倍增电路的输入端与输出端分别连接于该第二负载电容器的两端，该第二米勒倍增电路用于增大该振荡电路的第二负载电容，其中，该第二负载电容为该晶体的第二端与地之间的电容。
在一种可能的实现方式中，该第二米勒倍增电路的电路结构与该第一米勒倍增电路的电路结构相同。
第二方面，提供一种芯片，包括：第一方面或者第一方面中任一种可能的实现方式中的晶体振荡器。
在一种可能的实现方式中，该芯片为时钟芯片，该时钟芯片用于提供时钟信号。
第三方面，提供一种电子设备，包括：第二方面或者第二方面中任一种可能的实现方式中的芯片。
通过在电子设备以及芯片中使用上述晶体振荡器，通过提高其中晶体振荡器的性能，从而提高电子设备以及芯片的整体性能。
附图说明
图1是一种典型的晶体振荡器的结构示意图。
图2是一种晶体振荡器在不同负载电容下的闭环传递函数的根轨迹图。
图3是图1中晶体的等效电路图。
图4是根据本申请实施例的一种晶体振荡器的示意性结构框图。
图5是根据本申请实施例的一种晶体振荡器的电路结构图。
图6是根据本申请实施例的另一种晶体振荡器的示意性结构框图。
图7至图13是根据本申请实施例的另几种晶体振荡器的电路结构图。
具体实施方式
下面将结合本申请实施例的附图，对本申请实施例进行描述。
本申请实施例可适用于包括处理器的电子设备或者电子系统，该处理器可以是一种集成电路芯片，具有信号的处理能力。该处理器可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。其中，通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
应理解，本文中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围。
还应理解，本说明书中描述的各种实施方式，既可以单独实施，也可以组合实施，本申请实施例对此并不限定。
除非另有说明，本申请实施例所使用的所有技术和科学术语与本申请的技术领域的技术人员通常理解的含义相同。本申请中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请的范围。本申请所使用的术语“和/或”包括一个或多个相关的所列项的任意的和所有的组合。
图1是一种晶体振荡器100的典型结构的示意图。该晶体振荡器100为一种皮尔斯振荡器(Pierce oscillator，或称皮尔斯晶体振荡器)结构。
如图1所示，该晶体振荡器100包括第一晶体管110、第二晶体管120、晶体130、第一电容器140、第二电容器150以及反馈电阻160。
其中，第一晶体管110的栅极连接至栅极控制电压V bp，第一晶体管的源极连接至电源电压V cc，第一晶体管110的漏极和第二晶体管120的漏极连接，第二晶体管120的漏极连接至地，即第一晶体管110和第二晶体管120形成反相放大电路的连接结构。第一晶体管110作为电流源给第二晶体管 120提供偏置，反馈电阻160与第二晶体管120形成负反馈稳定V a和V b的直流电压，第一电容器140和第二电容器150作为晶体振荡器100的负载电容，第一晶体管110和第二晶体管120用于为晶体130的起振和维持振荡提供跨导。
但是，图1所示的晶体振荡器100存在如下问题：
晶体振荡器100起振所需的跨导比维持振荡所需的跨导大，且过大的跨导或者过小的跨导都会导致振荡器不起振。因此，第一晶体管110和第二晶体管120，尤其是第二晶体管120的跨导需要设计在合适的区间中，否则振荡器无法起振。决定该跨导区间的因素有很多，其中一个与晶体振荡器100的负载电容有关，即与图1中的第一电容器140和第二电容器150的电容有关。
在极低功耗应用下，晶体振荡器100的负载电容器(第一电容器140和第二电容器150)的电容非常小，这将导致晶体振荡器100可振荡的跨导区间变得很小，因此对设置合理的跨导提出了挑战。尤其是不同工艺、温度和电压下，跨导的偏差可高达±50％以上，造成晶体振荡器可能不起振，从而影响其良率。
图2示出了一种晶体振荡器在不同负载电容下的闭环传递函数的根轨迹图。
具体地，该根轨迹图为传递函数的零极点随增益变化的轨迹图。图中横坐标的零极点的实轴，纵坐标为零极点的虚轴，零极点的实轴大于等于0时，晶体振荡器开始振荡。
由图2中可以看出，负载电容为4pF时，晶体振荡器的可振荡跨导区域为0.199μs至199.5μs。而负载电容为16pF时，晶体振荡器的可振荡跨导区域为1.259μs至3162μs。因此，当增大负载电容时，晶体振荡器的可振荡跨导区间大幅增加，即使会有不同工艺、温度和电压的影响，造成跨导的偏差，但由于晶体振荡器的可振荡跨导区间较大，晶体振荡器仍然能够正常起振。
另外，图3示出了图1中晶体130的等效电路图。
如图3所示，晶体130等效为图中虚线框所示的等效电路，包括并联电容131，等效电容132，等效电感133以及等效电阻134。
根据巴克豪森判据，当LC谐振电路在谐振频率时，电路整体等效阻抗的虚部为0，若此时实部为负则LC谐振电路振荡。因此只要保证从并联电 容131两端看向电路的阻抗Z C，在谐振频率处的负电阻阻值大于晶体的等效电阻134的阻值R S，那么晶体振荡器即可振荡。
具体地，Z C的计算公式如下：
Figure PCTCN2020114079-appb-000001
Z C的实部的计算公式如下：
Figure PCTCN2020114079-appb-000002
其中，C 1为第一电容器140的电容，C 2为第二电容器150的电容，C 3为并联电容器131的电容，g m为第二晶体管120的跨导。
为了让晶体振荡器起振，只要取合适的g m保证实部的负阻阻值大于等效电阻134的阻值R S，联立如下方程并求根即可得到晶体振荡器临界起振的g m大小。
Figure PCTCN2020114079-appb-000003
对上述方程求解得到：
Figure PCTCN2020114079-appb-000004
将上述求解得到的g m进行一阶泰勒展开，得到其近似表达式如下：
Figure PCTCN2020114079-appb-000005
根据上述表达式，可以计算得到g m的最小值g m,min以及最大值g m,max，二者的计算表达式如下：
Figure PCTCN2020114079-appb-000006
Figure PCTCN2020114079-appb-000007
若C 1、C 2远大于C 3，g m,min以及g m,max可以进一步简化为下述表达式：
g m,min≈ω 2R SC 1C 2；
Figure PCTCN2020114079-appb-000008
因此，第二晶体管120的跨导g m取值范围大小如下式表达式所示：
Figure PCTCN2020114079-appb-000009
通过上述表达式可以看出，若要使得晶体振荡器100起振，第二晶体管120的跨导g m取值区间与第一电容器140的电容C 1、第二电容器150的电容C 2成正比。
通过上述图2以及图3的相关说明可知，随着负载电容器的电容增大，晶体振荡器的可振荡跨导区间增加。为了提高晶体振荡器起振的稳定性和可靠性，提高其生产良率，需要在晶体振荡器中设计一个大电容的负载电容器。但大电容的负载电容器意味着大的电容面积，对于晶体振荡器这种电容器面积占主导的电路而言，增大电容器的电容意味着增加电路成本。
因此，为了解决上述问题，本申请实施例利用米勒效应(miller effect)对晶体振荡器中的负载电容进行倍增，在采用小的负载电容器的情况下，倍增得到大的负载电容，以能够产生大的可振荡跨导区域，从而提高晶体振荡器的起振稳定性。与此同时，能够减少负载电容器占用的面积，降低电路成本，有利于晶体振荡器的小型化发展。
图4示出了本申请实施例提供的一种晶体振荡器的示意性结构框图。
如图4所示，该晶体振荡器200包括：振荡电路和第一米勒倍增电路250，其中，该振荡电路包括：放大电路210、晶体220、第一负载电容器230以及第二负载电容器240。
可选地，如图4所示，放大电路210与晶体220并联，第一负载电容器230和第二负载电容器240分别连接于该晶体220的第一端和第二端。第一米勒倍增电路250并联于上述第一负载电容器230，换言之，该第一米勒倍增电路的输入端与输出端分别连接于第一负载电容器230的两端。
可选地，在本申请实施例中，上述放大电路210可以为反相放大电路，例如，图1中所示的皮尔斯晶体振荡器中第一晶体管110和第二晶体管120形成的反相放大电路，因此，放大电路210中的第一晶体管和第二晶体管可以为晶体的振荡提供跨导，有利于晶体的快速起振。
可以理解的是，放大电路210除了可以为皮尔斯晶体振荡器中的反相放大电路以外，还可以为相关技术中其它类型的放大电路，本申请实施例对该放大电路210的具体电路结构不做限定。
对应的，本申请实施例中的晶体220、第一负载电容器230和第二负载电容器240可以分别为图1中皮尔斯晶体振荡器100中的晶体130、第一电容器140和第二电容器150。本申请实施例中的振荡电路形成的电路结构即为图1中所示的皮尔斯晶体振荡器的电路结构。
在此基础上，第一米勒倍增电路250并联于第一负载电容器230，用于增大振荡电路的第一负载电容，其中，第一负载电容为晶体220的第一端与地之间的电容。
可选地，该第一米勒倍增电路250可以为反相放大电路，根据米勒效应的原理，在反相放大电路中，输入与输出之间的电容由于放大器的放大作用，其等效到输入端的电容值会扩大(A+1)倍，其中A是该反相放大电路的增益(也称放大倍数)。换言之，在本申请实施例中，该第一米勒倍增电路250用于将第一负载电容增大为第一负载电容器230的电容的(A+1)倍，A为该第一米勒倍增电路250的增益，且A为正数。
通过本申请实施例的技术方案，在晶体振荡器的负载电容器的两端并联米勒倍增电路，从而增大其负载电容，使得晶体振荡器在起振时具有较大的可振荡跨导区域，提高了晶体振荡器的起振稳定性。与此同时，能够减少负载电容器占用的面积，降低电路成本。
以下，结合图5至图9中的具体示例，详细介绍本申请实施例的晶体振荡器的实现方式。
图5示出了本申请实施例提供的一种晶体振荡器的电路结构图。
如图5所示，上述放大电路210可以包括第一振荡晶体管211、第二振荡晶体管212以及反馈电阻213。上述第一米勒倍增电路250可以包括第一倍增晶体管251和第二倍增晶体管252，该两个倍增晶体管用于形成反相放大器，第一负载电容器230连接于该反相放大器的输入端V a和输出端V oa，该输入端V a也为晶体220的第一端。
可选地，在第一米勒倍增电路中，第一倍增晶体管251为P型沟道金属氧化物半导体(Positive Channel Metal Oxide Semiconductor，PMOS)晶体管，第二倍增晶体管252为n型沟道金属氧化物半导体(Negative Channel Metal Oxide Semiconductor，NMOS)晶体管。
作为示例，如图5所示，该第一米勒倍增电路250为A类放大电路，其中，第一倍增晶体管251的栅极(Gate)与漏极(Drain)连接，第一倍增晶 体管251的源极(Source)连接至电源电压V cc，使得第一倍增晶体管251工作在饱和区。第二倍增晶体管252的栅极为该第一米勒倍增电路250的输入端V a，连接至第一负载电容器230的一端，第二倍增晶体管252的漏极连接至第一倍增晶体管251的漏极，其为第一米勒倍增电路250的输出端V oa，连接至第一负载电容器230的另一端，该第二倍增晶体管252的源极连接至地V gd。
在该情况下，若第一米勒倍增电路250的增益为A，则从第一倍增电路250的输入端V a看向第一负载电容器230，V a至V gd之间的电容，也即振荡电路的第一负载电容C’ 1被倍增为(1+A)C 1，其中，C 1为第一负载电容器230的电容。
可以理解的是，在本申请实施例中，第一米勒倍增电路250除了可以为图5中所示的反相放大器结构以外，其还可以为其它类型的反相放大器，例如，第一倍增晶体管251的栅极不与漏极连接，而接入偏置电压；又例如，第一倍增晶体管251和第二倍增晶体管252的栅极连接，作为第一米勒倍增电路250的输入端。本申请实施例对该第一米勒倍增电路250的具体电路结构不做限定。
优选地，第一米勒倍增电路250设计为如图5所示的电路结构，此时，第一倍增晶体管251稳定工作在饱和状态，能够为第二倍增晶体管252提供稳定的直流偏置，整个第一米勒倍增电路250易于控制且工作在较为稳定的工作状态，与此同时，还能提供较为合适的增益，倍增第一负载电容至较为合适的大小范围，从而提供第二振荡晶体管212合适的可起振跨导范围。
上文图4以及图5的申请实施例中，晶体振荡器200仅包括第一米勒倍增电路250，并联在第一负载电容器230两端，用于对第一负载电容进行倍增。
图6和图7示出了本申请实施例提供另两例晶体振荡器200的结构框图以及电路结构示意图。
如图6和图7所示，该晶体振荡器200还包括：第二米勒倍增电路260，并联在第二负载电容器240两端，用于对第二负载电容进行倍增，其中，该第二负载电容为晶体220的第二端与地之间的电容。
可以理解的是，该第二米勒倍增电路260的相关技术方案可以参见上文中第一米勒倍增电路250的相关说明，此处不赘述。
作为示例，如图7所示，该第二米勒倍增电路260的电路结构与上文中图5所示的第一米勒倍增电路250的电路结构相同，其包括第三倍增晶体管261以及第四倍增晶体管262形成的反相放大器，第二负载电容器240连接在该反相放大器的输入端V b和输出端V ob之间，该输入端V b也即晶体220的第二端。
还可以理解的是，该第二米勒倍增电路260除了可以为图7所示的电路结构以外，其还可以为其它类型的反相放大电路，具体的电路类型和电路结构可以与第一米勒倍增电路250相同或者不同，本申请实施例对此不做具体限定。
上文实施例中，通过米勒倍增电路对晶体振荡器中的负载电容进行了倍增，从而便于晶体振荡器起振提高起振稳定性。但是，在晶体起振之后，维持晶体振荡的电容往往小于起振所需的电容，特别是在低功耗的应用场景下，仅需要较小的负载电容，此时，负载电容中为了起振稳定性预留的电容会被浪费。
基于此问题，进一步地，本申请实施例提供了一种包括开关单元组的晶体振荡器，能够在晶体起振时提供大容量的负载电容，而在起振之后，维持振荡阶段，提供小容量的负载电容以节约晶体振荡器的功耗，使得该晶体振荡器可以用于更多的低功耗的应用场景中。
可选地，晶体振荡器200可以包括：第一开关单元组，该第一开关组用于在晶体振荡器起振时，连接上述第一米勒倍增电路与上述第一负载电容器，而在晶体振荡器维持振荡时，断开上述第一米勒倍增电路与上述第一负载电容器。
基于图5所示的申请实施例，图8示出了另一种晶体振荡器200的电路结构示意图。
如图8所示，在本申请实施例中，该晶体振荡器200中的第一开关组包括：第一开关253，第二开关254以及第三开关255。
其中，第一开关253连接第二倍增晶体管252的栅极以及第一负载电容器230的一端(V a)，第二开关254连接第一倍增晶体管251的漏极以及第一负载电容器230的另一端(V oa)，第三开关255连接第二倍增晶体管252的栅极以及电源电压V cc。
当第一开关253和第二开关254同时闭合，且第三开关255断开时，第 一负载电容器230接入第一米勒倍增电路250的输入端与输出端之间，以对第一负载电容进行倍增。
当第三开关255闭合，且第一开关253和第二开关254同时断开时，第二倍增晶体管252导通，第一负载电容器230的一端(V oa)接地，此时，第一负载电容为第一负载电容器230的电容。
可选地，在本申请实施例中，可以通过控制单元控制第一开关组中每个开关的状态，其中，在同一时刻，第一开关253和第二开关254的开关状态保持一致，且与第三开关255的开关状态相反。
可以理解的是，图8中第一开关组中各开关的数量和位置仅为示例性说明，各开关除了位于图8所示的位置以外，还可以位于电路中的其它位置，例如：第二开关254可以用于连接第一倍增晶体管251的源极和电源电压V cc，和/或，第三开关255用于连接第二倍增晶体管252的栅极和其它电源电压，等等。本申请实施例对该第一开关组中的开关位置不做具体限定，旨在通过第一开关组控制是否将第一米勒倍增电路250连接至第一负载电容器230即可。
可选地，晶体振荡器200还可以包括：第二开关单元组，该第二开关组用于在晶体振荡器起振时，连接上述第二米勒倍增电路与上述第二负载电容器，而在晶体振荡器维持振荡时，断开上述第二米勒倍增电路与上述第二负载电容器。
基于图7所示的申请实施例，图9示出了另一种晶体振荡器200的电路结构示意图。
如图9所示，在本申请实施例中，该晶体振荡器200中的第二开关组包括：第四开关263，第五开关264以及第六开关265。
其中，第四开关263连接第四倍增晶体管262的栅极以及第二负载电容器240的一端(V b)，第五开关264连接第三倍增晶体管261的漏极以及第二负载电容器240的另一端(V ob)。第六开关265连接第四倍增晶体管262的栅极以及电源电压V cc。
当第四开关263和第五开关264同时闭合，且第六开关265断开时，第二负载电容器240接入第二米勒倍增电路260的输入端与输出端之间，以对该第二负载电容进行倍增。
当第六开关265闭合，且第四开关263和第五开关264同时断开时，第 四倍增晶体管262导通，第二负载电容器240的一端(V ob)接地，此时第二负载电容为第二负载电容器240的电容。
可选地，在本申请实施例中，可以通过控制单元控制第二开关组中每个开关的状态，其中，在同一时刻，第四开关263和第五开关264的开关状态保持一致，且与第六开关265的开关状态相反。
进一步地，在本申请实施例中，在同一时刻，控制单元可以控制第一开关253、第二开关254、第四开关263以及第五开关264的开关状态一致，且控制第三开关255和第六开关265的开关状态一致。
类似的，图9中第二开关组中各开关的数量和位置仅为示例性说明，各开关除了位于图9所示的位置以外，还可以位于电路中的其它位置，例如：第五开关264可以用于连接第三倍增晶体管261的源极和电源电压V cc，和/或，第六开关265用于连接第四倍增晶体管262的栅极和其它电源电压，等等。本申请实施例对该第二开关组中的开关位置不做具体限定，
通过上文的介绍的实施例，第一负载电容器230可以并联至第一米勒倍增电路250，以对第一负载电容倍增，和/或，第二负载电容器240可以并联至第二米勒倍增电路260，以对第二负载电容倍增，具体的，负载电容的倍增量与米勒倍增电路的增益相关。
在上文实施例中，以图7至图9中的第一米勒倍增电路250为例，其增益计算公式如下：
Figure PCTCN2020114079-appb-000010
其中，g m51和g m52分别为第一倍增晶体管251的跨导和第二倍增晶体管252的跨导，可以通过调整g m51和g m52来调整负载电容的倍增量。
具体地，第一倍增晶体管251的跨导g m51的计算公式如下：
Figure PCTCN2020114079-appb-000011
其中，μ为电子迁移率，C ox为第一倍增晶体管251的栅氧化层电容，W/L为第一倍增晶体管251的宽长比，I d51为第一倍增晶体管251的漏极电流。
具体地，第二倍增晶体管252镜像于放大电路中的第二振荡晶体管212，第二倍增晶体管252的漏极电流I d52以及跨导g m52的计算公式如下：
I d52＝NI B，g m52＝Ng m12；
其中，N为第二倍增晶体管252的宽长比与第二振荡晶体管212的宽长比之比，I B为第二振荡晶体管212的漏极电流，也为第一振荡晶体管211的漏极电流，g m12为第二振荡晶体管212的跨导。
因此，由以上公式可以看出，可以通过调整第一倍增晶体管251的工艺条件，例如宽长比等，来调整第一倍增晶体管251的跨导；和/或，调整第一倍增晶体管251的漏极电流，来调整第一倍增晶体管251的跨导，从而调整第一米勒倍增电路250的增益。
或者，也可以通过调整第二倍增晶体管252的工艺条件，例如宽长比等，调整第二倍增晶体管252的跨导；和/或，调整第二倍增晶体管252的漏极电流，来调整第二倍增晶体管252的跨导，从而调整第一米勒倍增电路250的增益。
可以理解的是，图7和图9中所示的第二米勒倍增电路260的电路结构与第一米勒倍增电路250的电路结构一致，其增益的计算方式以及其增益的调整方式可以参见上下文中第一米勒倍增电路250的调整方式，此处不再赘述。
下面，结合图10至图12说明可调增益的第一米勒倍增电路250的电路结构。
(1)在第一种实施例中：
可以在设计以及制造阶段，通过调整上述N，即第二倍增晶体管252的宽长比与第二振荡晶体管212的宽长比之比，调整第二倍增晶体管252的跨导g m52，从而调整第一米勒倍增电路250的增益A。
(2)进一步地，在第二种实施例中：
可以在实际使用阶段，通过在第二倍增晶体管252上并联至少一个晶体管，通过调整并联的晶体管的数量，调整并联晶体管后的第二倍增晶体管252的跨导g m52，从而调整第一米勒倍增电路250的增益A。
作为示例，图10示出了本实施例中另一种晶体振荡器200的电路结构示意图。
如图10所示，在本申请实施例中，该第一米勒倍增电路250还包括：
n个第二调节晶体管(2521至252n)，该n个第二调节晶体管中每个第二调节晶体管的栅极、源极和漏极分别连接至第二倍增晶体管252的栅极、源极和漏极，其中，n为正整数。
可选地，该第一米勒倍增电路250还包括：n个第二调节开关(2511至251n)，该n个第二调节开关一一对应的连接于n个第二调节晶体管，该第二调节开关用于控制是否将第二调节晶体管连接至第二倍增晶体管252。
作为示例，如图10所示，该n个第二调节开关一一对应的连接上述n个第二调节晶体管的漏极与第一负载电容器230的一端(V oa)。
可选地，n个第二调节晶体管(2521至252n)可以均为NMOS晶体管。进一步地，该n个第二调节晶体管可以为相同结构的晶体管。更进一步地，该n个第二调节晶体管可以为与第二倍增晶体管252相同结构的晶体管。采用该实施方式，能够更为便捷的调控第二调节晶体管后的第二倍增晶体管252的漏极电流I d52以及跨导g m52，从而调整第一米勒倍增电路250的增益A。
若该n个第二调节晶体管(2521至252n)为与第二倍增晶体管252相同结构的晶体管，则在如图10所示的电路结构中，连接第二调节晶体管后的第二倍增晶体管252的漏极电流I d52以及跨导g m52的计算公式如下：
I d52＝iNI B，g m52＝iNg m12；
其中，i表示连接至第二倍增晶体管252的第二调节晶体管的数量，1≤i≤n，且i为正整数。N为第二倍增晶体管252的宽长比与第二振荡晶体管212的宽长比之比，I B为第二振荡晶体管212的漏极电流，g m12为第二振荡晶体管212的跨导。
在实际应用过程中，可以通过调整i和N中一个或者多个参数，从而调整并联晶体管后的第二倍增晶体管252的跨导g m52。
(3)在第三种实施例中：
可以通过调整第一倍增晶体管251的漏极电流I d51，来调整第一倍增晶体管251的跨导g m51，从而调整第一米勒倍增电路250的增益A。
作为示例，图11示出了本实施例中另一种晶体振荡器200的电路结构示意图。
如图11所示，在本申请实施例中，该第一米勒倍增电路250还包括：
m个第一调节晶体管(2531至253m)，该m个第一调节晶体管中每个第一调节晶体管的源极和漏极分别连接至第一倍增晶体管251的源极和漏极，该m个第一调节晶体管中每个第一调节晶体管的栅极连接至栅极控制电压V bp，其中，m为正整数。
可选地，该第一米勒倍增电路250还包括：
m个第一调节开关(2541至254m)，该m个第一调节开关一一对应的连接于与上述m个第一调节晶体管，该第一调节开关用于控制是否将第一调节晶体管连接至第一倍增晶体管251。
作为示例，如图11所示，该m个第一调节开关一一对应的连接上述m个第一调节晶体管的漏极与第一倍增晶体管251的漏极。
可选地，m个第一调节晶体管均为PMOS晶体管，进一步地，该m个第一调节晶体管可以为相同结构的晶体管。
若该m个第一调节晶体管(2531至253m)为相同结构的晶体管，其中每个第一调节晶体管的漏极电流为I d53，则在如图11所示的电路结构中，第一倍增晶体管251的漏极I d51的计算公式如下：
I d51＝I d52-jI d53；
其中，I d52＝NI B，N为第二倍增晶体管252的宽长比与第二振荡晶体管212的宽长比之比，I B为第二振荡晶体管212的漏极电流，j表示并联至第一倍增晶体管251的第一调节晶体管的数量，1≤j≤m，且j为正整数。
进一步地，若上述m个第一调节晶体管(2531至253m)为相同结构的晶体管，且每个第一调节晶体管的宽长比与第一振荡晶体管211的宽长比之比为M，则第一调节晶体管的漏极电流I d53、第一倍增晶体管251的漏极I d51和跨导g m51的计算公式如下：
I d53＝MI B，I d51＝NI B-jMI B，
Figure PCTCN2020114079-appb-000012
由上述公式可以看出，在实际应用过程中，可以通过调整j、M、N中的一个或者多个参数，从而调整第一倍增晶体管251的跨导g m51。
(4)在第四种实施例中：
综合上述第二种实施例以及第三种实施例的技术方案，可以在实际使用阶段，通过控制在第二倍增晶体管252上并联的第二调节晶体管的数量，来调整第二倍增晶体管252的跨导g m52，并通过调整第一倍增晶体管251的漏极电流I d51，来调整第一倍增晶体管251的跨导g m51，从而调整第一米勒倍增电路250的增益A。
作为示例，图12示出了本实施例中另一种晶体振荡器200的电路结构示意图。
如图12所示，在本申请实施例中，该第一米勒倍增电路250还包括：m 个第一调节晶体管和m个第一调节开关，以及n个第二调节晶体管和n个第二调节开关。该m个第一调节晶体管和m个第一调节开关，以及n个第二调节晶体管和n个第二调节开关可以参见上文图10和图11的相关描述，此处不再赘述。
在如图12所示的电路结构中，第二倍增晶体管252的漏极电流I d52和跨导g m52和的计算公式如下：
I d52＝iNI B，g m52＝iNg m12；
其中，i表示连接至第二倍增晶体管252的第二调节晶体管的数量，1≤i≤n，且i为正整数，N为第二倍增晶体管252的宽长比与第二振荡晶体管212的宽长比之比，I B为第二振荡晶体管212的漏极电流，g m12为第二振荡晶体管212的跨导。
第一倍增晶体管251的漏极I d51和跨导g m51的计算公式如下：
I d51＝iNI B-jMI B，
Figure PCTCN2020114079-appb-000013
其中，j表示连接至第一倍增晶体管251的第一调节晶体管的数量，1≤j≤m，且j为正整数。M为第二调节晶体管的宽长比与第一振荡晶体管211的宽长比之比。
由上述公式可以看出，在实际应用过程中，可以通过控制i、j、M、N中的一个或者多个参数，调整第二倍增晶体管252的跨导g m52和第一倍增晶体管251的跨导g m51，以调整第一米勒倍增电路250的增益A。
在上述申请实施例中，通过调整第一米勒倍增电路250的增益A，从而调整晶体振荡器中的第一负载电容至合适的值，从而使得晶体振荡器易于起振，与此同时，也为调节晶体振荡器的振荡频率提供了一种新的手段。
结合上述图10至图12中的可调增益的第一米勒倍增电路250的电路结构，可以理解的是，第二米勒倍增电路260的电路结构可以与上文任意一种第一米勒倍增电路250的电路结构一致。
作为示例，图13示出了本申请中一种优选的晶体振荡器200的电路结构的示意图。
如图13所示，该晶体振荡器200包括第一米勒倍增电路250以及第二米勒倍增电路260，第一米勒倍增电路250的电路结构与图12中的第一米勒倍增电路250的电路结构一致，第二米勒倍增电路260的电路结构镜像于该 第一米勒倍增电路250。
具体地，如图13所示，该第二米勒倍增电路260可以包括：n个第三调节开关(2611至261n)与n个第三调节晶体管(2621至262n)。
可选地，n个第三调节晶体管(2621至262n)均为NMOS晶体管。进一步地，该n个第三调节晶体管可以为相同结构的晶体管。更进一步地，该n个第三调节晶体管可以为与第四倍增晶体管262相同结构的晶体管。
可选地，该第二米勒倍增电路260还可以包括：m个第四调节开关(2641至264m)与m个第四调节晶体管(2631至263m)。
可选地，m个第四调节晶体管均为PMOS晶体管，进一步地，该m个第四调节晶体管可以为相同结构的晶体管。
可以理解的是，本申请实施例中，第二米勒倍增电路260中的调节开关以及调节晶体管的相关技术方案可以参见上文中第一米勒倍增电路250中的调节开关和调节晶体管的相关描述，第二米勒倍增电路260的增益的调整方法也可以参见上文中第一米勒倍增电路250的增益的调整方法，此处不再具体赘述。
还可以理解的是，在图13所示的实施例中，第三调节晶体管和第三调节开关的数量包括但不限于是n，第四调节晶体管和第四调节开关的数量包括但不限于是m，本申请实施例对此不做具体限定。
另外，图13中的第二米勒倍增电路260镜像于图12中的第一米勒倍增电路250，除此之外，第二米勒倍增电路260还可以镜像于图10或者图11的第一米勒倍增电路250。在晶体振荡器200中，第一米勒倍增电路250和第二米勒倍增电路260的结构可以相同或者也可以不相同，本申请实施例对此也不做具体限定。
例如，若第一米勒倍增电路250和第二米勒倍增电路260的结构不相同，第一米勒倍增电路250可以为图10所示的电路结构，第二米勒倍增电路260可以为镜像于图11或者图12所示的电路结构。若第一米勒倍增电路250和第二米勒倍增电路260的结构相同，则第一米勒倍增电路250为图10所示的电路结构，且第二米勒倍增电路260为镜像于图10所示的电路结构，或者，第一米勒倍增电路250为图11所示的电路结构，且第二米勒倍增电路260为镜像于图11所示的电路结构。
本申请实施例还提供一种芯片，包括上述本申请各种实施例中的晶体振 荡器。
在一些可能的实施方式中，该芯片可以为时钟芯片，例如实时时钟(Real Time Clock，RTC)芯片，该时钟芯片可以为处理器等其它类型的芯片提供时钟信号。
本申请实施例还提供了一种电子设备，该电子设备包括：上述实施例中的芯片。
作为示例而非限定，本申请实施例中的电子设备可以为任意需要时钟信号的设备，例如终端设备、手机、平板电脑、笔记本电脑、台式机电脑、游戏设备、车载电子设备或穿戴式智能设备等便携式或移动计算设备，以及电子数据库、汽车等其他电子设备。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围，本领域技术人员可以在上述实施例的基础上进行各种改进和变形，而这些改进或者变形均落在本申请的保护范围内。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种晶体振荡器，其特征在于，包括：
    振荡电路，包括：晶体、放大电路、第一负载电容器和第二负载电容器，所述晶体的两端分别连接于所述放大电路的输入端与输出端，所述第一负载电容器和所述第二负载电容器分别连接于所述晶体的第一端和第二端；
    第一米勒倍增电路，所述第一米勒倍增电路的输入端与输出端分别连接于所述第一负载电容器的两端，所述第一米勒倍增电路用于增大所述振荡电路的第一负载电容，其中，所述第一负载电容为所述晶体的第一端与地之间的电容。
  2. 根据权利要求1所述的晶体振荡器，其特征在于，所述第一米勒倍增电路用于将所述第一负载电容增大为所述第一负载电容器的电容的(A+1)倍，A为所述第一米勒倍增电路的增益。
  3. 根据权利要求2所述的晶体振荡器，其特征在于，所述第一米勒倍增电路包括：第一倍增晶体管和第二倍增晶体管，所述第一倍增晶体管和所述第二倍增晶体管串联形成反相放大电路；
    所述第一倍增晶体管的栅极与漏极连接，所述第一倍增晶体管的源极连接至电源电压，所述第一倍增晶体管的漏极连接至所述第二倍增晶体管的漏极；
    所述第二倍增晶体管的栅极为所述第一米勒倍增电路的输入端，连接至所述第一负载电容器的一端，所述第二倍增晶体管的漏极为所述第一米勒倍增电路的输出端，连接至所述第一负载电容器的另一端，所述第二倍增晶体管的源极连接至地。
  4. 根据权利要求1至3中任一项所述的晶体振荡器，其特征在于，还包括：
    第一开关组，用于在所述晶体振荡器起振时，连接所述第一米勒倍增电路与所述第一负载电容器，在所述晶体振荡器维持振荡时，断开所述第一米勒倍增电路与所述第一负载电容器。
  5. 根据权利要求4所述的晶体振荡器，其特征在于，所述第一开关组包括：第一开关，第二开关以及第三开关；
    所述第一开关连接所述第二倍增晶体管的栅极以及所述第一负载电容器的一端，所述第二开关连接所述第一倍增晶体管的漏极以及所述第一负载 电容器的另一端，所述第三开关连接所述第二倍增晶体管的栅极以及电源电压；
    在所述晶体振荡器起振时，所述第一开关和所述第二开关闭合，且所述第三开关断开，所述第一米勒倍增电路连接于所述第一负载电容器，以增大所述振荡电路的第一负载电容；
    在所述晶体振荡器维持振荡时，所述第三开关闭合，且所述第一开关和所述第二开关断开，所述振荡电路的第一负载电容等于所述第一负载电容器的电容。
  6. 根据权利要求3至5中任一项所述的晶体振荡器，其特征在于，所述第一米勒倍增电路还包括：
    至少一个第一调节晶体管，所述至少一个第一调节晶体管中每个第一调节晶体管的源极和漏极分别连接至所述第一倍增晶体管的源极和漏极，所述至少一个第一调节晶体管中每个第一调节晶体管的栅极连接至栅极控制电压。
  7. 根据权利要求6所述的晶体振荡器，其特征在于，所述第一米勒倍增电路还包括：
    至少一个第一调节开关，所述至少一个第一调节开关一一对应的连接于与所述至少一个第一调节晶体管，所述第一调节开关用于控制是否将所述第一调节晶体管连接至所述第一倍增晶体管。
  8. 根据权利要求7所述的晶体振荡器，其特征在于，所述至少一个第一调节开关用于调整所述第一倍增晶体管的跨导，以调整所述第一米勒倍增电路的增益A。
  9. 根据权利要求6至8中任一项所述的晶体振荡器，其特征在于，若所述至少一个第一调节晶体管为多个第一调节晶体管，所述多个第一调节晶体管为相同结构的晶体管。
  10. 根据权利要求3至9中任一项所述的晶体振荡器，其特征在于，所述第一米勒倍增电路还包括：
    至少一个第二调节晶体管，所述至少一个第二调节晶体管中每个第二调节晶体管的栅极、源极和漏极分别连接至所述第二倍增晶体管的栅极、源极和漏极。
  11. 根据权利要求10所述的晶体振荡器，其特征在于，所述第一米勒 倍增电路还包括：
    至少一个第二调节开关，所述至少一个第二调节开关一一对应的连接于所述至少一个第二调节晶体管，所述第二调节开关用于控制是否将所述第二调节晶体管连接至所述第二倍增晶体管。
  12. 根据权利要求11所述的晶体振荡器，其特征在于，所述至少一个第二调节开关用于调整所述第二倍增晶体管的跨导，以调整所述第一米勒倍增电路的增益A。
  13. 根据权利要求10至12中任一项所述的晶体振荡器，其特征在于，若所述至少一个第二调节晶体管的数量为多个第二调节晶体管，所述多个第二调节晶体管为相同结构的晶体管。
  14. 根据权利要求13所述的晶体振荡器，其特征在于，所述至少一个第二调节晶体管的结构与所述第二倍增晶体管的结构相同。
  15. 根据权利要求3至14中任一项所述的晶体振荡器，其特征在于，所述放大电路包括第一振荡晶体管、第二振荡晶体管和反馈电阻；
    所述第一振荡晶体管的栅极连接至栅极控制电压，所述第一振荡晶体管的漏极连接至所述晶体的第二端，所述第一振荡晶体管的源极连接至电源电压；
    所述第二振荡晶体管的栅极连接至所述晶体的第一端，所述第二振荡晶体管的漏极连接至所述晶体的第二端，所述第二振荡晶体管的源极连接至地；
    所述反馈电阻的两端分别连接至所述晶体的两端。
  16. 根据权利要求15所述的晶体振荡器，其特征在于，所述第二倍增晶体管的宽长比与所述第二振荡晶体管的宽长比之比用于调整所述第二倍增晶体管的跨导以及所述第一倍增晶体管的跨导，以调整所述第一米勒倍增电路的增益A。
  17. 根据权利要求15或16所述的晶体振荡器，其特征在于，所述第二调节晶体管的宽长比与所述第一振荡晶体管的宽长比之比用于调整所述第一倍增晶体管的跨导，以调整所述第一米勒倍增电路的增益A。
  18. 根据权利要求1至17中任一项所述的晶体振荡器，其特征在于，还包括：第二米勒倍增电路，所述第二米勒倍增电路的输入端与输出端分别连接于所述第二负载电容器的两端，所述第二米勒倍增电路用于增大所述振 荡电路的第二负载电容，其中，所述第二负载电容为所述晶体的第二端与地之间的电容。
  19. 根据权利要求1至18中任一项所述的晶体振荡器，其特征在于，所述第二米勒倍增电路的电路结构与所述第一米勒倍增电路的电路结构相同。
  20. 一种芯片，其特征在于，包括：
    如权利要求1至19中任一项所述的晶体振荡器。
  21. 根据权利要求20所述的芯片，其特征在于，所述芯片为时钟芯片，所述时钟芯片用于提供时钟信号。
  22. 一种电子设备，其特征在于，包括：
    如权利要求20或21所述的芯片。
PCT/CN2020/114079 2020-09-08 2020-09-08 晶体振荡器、芯片和电子设备 WO2022051913A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/114079 WO2022051913A1 (zh) 2020-09-08 2020-09-08 晶体振荡器、芯片和电子设备
US17/484,841 US11482969B2 (en) 2020-09-08 2021-09-24 Crystal oscillator, chip, and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/114079 WO2022051913A1 (zh) 2020-09-08 2020-09-08 晶体振荡器、芯片和电子设备

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/484,841 Continuation US11482969B2 (en) 2020-09-08 2021-09-24 Crystal oscillator, chip, and electronic device

Publications (1)

Publication Number Publication Date
WO2022051913A1 true WO2022051913A1 (zh) 2022-03-17

Family

ID=80470104

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/114079 WO2022051913A1 (zh) 2020-09-08 2020-09-08 晶体振荡器、芯片和电子设备

Country Status (2)

Country Link
US (1) US11482969B2 (zh)
WO (1) WO2022051913A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030025579A1 (en) * 2001-07-31 2003-02-06 Christensen Kaare Tais IGFET and tuning circuit
CN1607726A (zh) * 2003-09-15 2005-04-20 三星电子株式会社 电容倍增器
CN102832903A (zh) * 2012-08-16 2012-12-19 中国科学院微电子研究所 一种电容倍增器
CN104426479A (zh) * 2013-08-29 2015-03-18 京微雅格（北京）科技有限公司 一种低功耗、低抖动、宽工作范围的晶体振荡器电路
CN107565928A (zh) * 2017-08-10 2018-01-09 宁波大学 一种高倍增系数的电容倍增器
CN108401476A (zh) * 2018-03-09 2018-08-14 深圳市汇顶科技股份有限公司 晶体振荡器
CN111108684A (zh) * 2019-11-19 2020-05-05 深圳市汇顶科技股份有限公司 振荡电路、芯片、电子设备

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000307344A (ja) * 1999-04-16 2000-11-02 Fujitsu Ltd 電圧制御発振器及び半導体集積回路装置
JP2001013011A (ja) * 1999-06-30 2001-01-19 Toshiba Corp 温度検出回路
JP3998233B2 (ja) * 2001-11-09 2007-10-24 セイコーＮｐｃ株式会社 発振回路および発振用集積回路
US7183868B1 (en) * 2004-09-09 2007-02-27 Sandia Corporation Triple inverter pierce oscillator circuit suitable for CMOS
JP2007158882A (ja) * 2005-12-07 2007-06-21 Matsushita Electric Ind Co Ltd 電圧制御型発振器
WO2007069455A1 (ja) * 2005-12-15 2007-06-21 Asahi Kasei Emd Corporation 電圧制御発振器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030025579A1 (en) * 2001-07-31 2003-02-06 Christensen Kaare Tais IGFET and tuning circuit
CN1607726A (zh) * 2003-09-15 2005-04-20 三星电子株式会社 电容倍增器
CN102832903A (zh) * 2012-08-16 2012-12-19 中国科学院微电子研究所 一种电容倍增器
CN104426479A (zh) * 2013-08-29 2015-03-18 京微雅格（北京）科技有限公司 一种低功耗、低抖动、宽工作范围的晶体振荡器电路
CN107565928A (zh) * 2017-08-10 2018-01-09 宁波大学 一种高倍增系数的电容倍增器
CN108401476A (zh) * 2018-03-09 2018-08-14 深圳市汇顶科技股份有限公司 晶体振荡器
CN111108684A (zh) * 2019-11-19 2020-05-05 深圳市汇顶科技股份有限公司 振荡电路、芯片、电子设备

Also Published As

Publication number Publication date
US20220077823A1 (en) 2022-03-10
US11482969B2 (en) 2022-10-25

Similar Documents

Publication Publication Date Title
TW512585B (en) Crystal oscillator with peak detector amplitude control
US7355489B2 (en) High gain, high frequency CMOS oscillator circuit and method
CN106067762A (zh) 快速起振的晶体振荡器电路
US7782146B2 (en) Interleaved voltage controlled oscillator
US20130141171A1 (en) Method to Shorten Crystal Oscillator's Startup Time
JP2004194336A (ja) 高品質並列共振発振器
US7183868B1 (en) Triple inverter pierce oscillator circuit suitable for CMOS
TW201228242A (en) Amplitude control for oscillator
CN111953315B (zh) 晶体振荡器、芯片和电子设备
WO2022051913A1 (zh) 晶体振荡器、芯片和电子设备
JP2001326560A (ja) 半導体集積回路およびフェーズ・ロックド・ループ回路
JPH01161906A (ja) 発振回路
US20230291352A1 (en) Oscillator acceleration circuit, chip and electronic device
TWI713300B (zh) 壓控振盪器
CN115664383B (zh) 一种流控振荡器ico的振幅调试方法
US8653898B2 (en) Crystal oscillator circuit
CN108123683A (zh) 一种晶振电路
JP5987403B2 (ja) 回路装置、発振装置及び電子機器
JP2004023109A (ja) 発振回路及び半導体集積回路
US20130300476A1 (en) Low noise and low power voltage controlled oscillators
Kackar et al. Differential voltage controlled ring oscillators—A review
US8558630B2 (en) Oscillator circuit and electronic apparatus including the same
CN209545549U (zh) 一种数字可调的振荡器
JPH10200382A (ja) 低電圧駆動の電圧制御発振回路
Shivhare et al. Low Power Ring Oscillator at 180nm CMOS Technology

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20952701

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20952701

Country of ref document: EP

Kind code of ref document: A1