WO2022048240A1 - 存储装置的读写方法及存储装置 - Google Patents

存储装置的读写方法及存储装置 Download PDF

Info

Publication number
WO2022048240A1
WO2022048240A1 PCT/CN2021/100676 CN2021100676W WO2022048240A1 WO 2022048240 A1 WO2022048240 A1 WO 2022048240A1 CN 2021100676 W CN2021100676 W CN 2021100676W WO 2022048240 A1 WO2022048240 A1 WO 2022048240A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
recovery time
temperature
write recovery
storage
Prior art date
Application number
PCT/CN2021/100676
Other languages
English (en)
French (fr)
Inventor
寗树梁
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21863308.9A priority Critical patent/EP4024396B1/en
Priority to US17/470,879 priority patent/US11862229B2/en
Publication of WO2022048240A1 publication Critical patent/WO2022048240A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Definitions

  • the present application relates to the field of semiconductor storage, and in particular, to a reading and writing method for a storage device and a storage device.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • the technical problem to be solved by the present application is to provide a method for reading and writing a storage device and a storage device, which can avoid the occurrence of the next precharging before the previous writing is completed, and improve the stability of the writing of the storage device.
  • the present application provides a method for reading and writing a storage device.
  • the storage device includes a storage chip. During the operation of the storage chip, the temperature of the storage chip is measured, and the writing of the storage chip is adjusted according to the temperature. Recovery Time.
  • adjusting the write recovery time of the memory chip includes extending the write recovery time or shortening the write recovery time.
  • the write recovery time is shortened, and when the temperature of the storage chip decreases, the write recovery time is extended.
  • the corresponding relationship between the temperature and the write recovery time is provided, after measuring the temperature of the storage chip, the write recovery time corresponding to the temperature is set to the current write recovery time of the storage chip according to the corresponding relationship between the temperature and the write recovery time .
  • the corresponding relationship between the temperature and the write recovery time is preset.
  • the storage chip has a default write recovery time, and when the storage chip is started, the default write recovery time is used as the current write recovery time of the storage chip.
  • the temperature of the storage chip is detected, and the write recovery time corresponding to the temperature is used as the current write recovery time of the storage chip.
  • the temperature of the memory chip is measured according to a set period, and the write recovery time of the memory chip is adjusted according to the temperature.
  • the temperature of the memory chip is measured, and the write recovery time of the memory chip is adjusted according to the temperature.
  • the present application also provides a storage device, which includes: a storage chip; a temperature detection unit for detecting the temperature of the storage chip; a control chip, electrically connected to the storage chip and the temperature detection unit, for The temperature adjusts the write recovery time of the memory chip.
  • the storage device has a look-up table, the look-up table records the corresponding relationship between the temperature and the write recovery time, and the control chip can adjust the write recovery time of the storage chip according to the records of the look-up table.
  • the temperature detection unit is provided in the storage chip or the control chip.
  • the storage device further includes a circuit substrate, the circuit substrate has connection lines, the storage chip and the control chip are both located on the circuit substrate, and the storage chip and the control chip pass through all the circuit substrates.
  • the connection circuit is electrically connected, and the temperature detection unit is arranged on the circuit substrate.
  • the advantage of the present application is that the write recovery time of the memory chip can be adjusted according to the temperature of the memory chip, so that the write recovery time performed by the memory chip is basically the same as the write recovery time that actually occurs when the memory chip performs read and write operations. Consistent to avoid data loss or slowdown.
  • Fig. 1 is the timing chart of the read-write operation of the existing storage device
  • Fig. 2 is the flow chart of the first embodiment of the read-write method of the storage device of the present application
  • Fig. 3 is the schematic diagram of the corresponding relation of temperature and write recovery time
  • Fig. 4 is the flow chart of the second embodiment of the read-write method of the storage device of the present application.
  • FIG. 5 is a schematic structural diagram of a first embodiment of the storage device of the present application.
  • FIG. 6 is a schematic structural diagram of a second embodiment of the storage device of the present application.
  • FIG. 7 is a schematic structural diagram of a third embodiment of the storage device of the present application.
  • FIG. 8 is a schematic structural diagram of a fourth embodiment of the storage device of the present application.
  • FIG. 1 is a timing diagram of a read and write operation of a conventional storage device, please refer to FIG. 1 , in the timing diagram, the write recovery time tWR is 12, and the precharge is performed after the write recovery time tWR, and the precharge time is tRP.
  • the write recovery time tWR is a preset write recovery time set by the storage device at the factory, which cannot be changed.
  • the actual write recovery time tWR of the storage device will be prolonged, which is greater than the preset write recovery time tWR. If the storage device If the operation is still performed according to the preset write recovery time, it may cause the next precharge and addressing before the previous write is completed, and the data written in the previous write will be incomplete, resulting in data loss. In a high temperature environment, the actual write recovery time tWR of the storage device will be shortened and will be less than the preset write recovery time tWR. If the storage device still performs operations according to the preset write recovery time, time will be wasted and storage will be reduced. The operating speed of the device.
  • the present application provides a method for reading and writing a storage device, which can change the write recovery time of the storage device according to the temperature of the storage device, so that the write recovery time performed by the storage chip is the same as when the storage chip performs the read and write operations.
  • the actual write recovery time is basically the same, to avoid data loss or reduced running speed.
  • the method for reading and writing a storage device of the present application includes, during the operation of the storage chip, measuring the temperature of the storage chip, and adjusting the write recovery time of the storage chip according to the temperature.
  • the temperature of the storage chip is not static, it depends on the external environment and its own operating time, the lower the external environment, the lower its own temperature, the longer the operating time, the higher its own temperature.
  • the writing method can monitor the temperature of the storage chip in real time, and adjust and adjust the writing recovery time of the storage chip according to the temperature.
  • the operation period of the memory chip refers to the period from when the memory chip is powered on to when the memory chip is powered off and shut down.
  • FIG. 2 is a schematic flowchart of a first embodiment of a reading and writing method for a storage device of the present application.
  • the storage device includes a storage chip and a control chip. Please refer to FIG. 2 , the reading and writing method of the storage device includes the following steps:
  • the memory chip is powered on.
  • the control chip applies a voltage to the memory chip, so that the memory chip starts up.
  • the storage chip has a default write recovery time, and when the storage chip is started, the control chip uses the default write recovery time as the current write recovery time of the storage chip .
  • the default write recovery time may be a write recovery time preset when the memory chip is shipped from the factory.
  • Detect the temperature of the memory chip In this step, after the memory chip is powered on and started, the temperature of the memory chip is detected to obtain the real-time temperature of the memory chip.
  • the temperature of the memory chip can be detected by a device such as a temperature detection unit.
  • the write recovery time of the memory chip is adjusted according to the temperature. In this step, the write recovery time is prolonged or shortened according to the temperature. When it is detected that the temperature of the storage chip increases, the write recovery time of the storage chip is shortened; when it is detected that the temperature of the storage chip decreases, the write recovery time of the storage chip is prolonged.
  • the control chip when the memory chip is powered on, the control chip takes the default write recovery time as the current write recovery time of the memory chip, for example, the default write recovery time is 12 cycle, then the current write recovery time of the memory chip is 12 cycles, then after the memory chip is started, the temperature of the memory chip is detected, if the temperature is higher than the temperature corresponding to the default write recovery time of the memory chip, then in the default On the basis of the write recovery time, shorten the write recovery time as the current write recovery time, for example, shorten the write recovery time to 10 cycles as the current write recovery time; if the temperature is lower than the default write recovery time of the memory chip If the temperature corresponds to the time, on the basis of the default write recovery time, the write recovery time is extended as the current write recovery time, for example, the write recovery time is extended to 14 cycles as the current write recovery time.
  • the default write recovery time is 12 cycle
  • the current write recovery time of the memory chip is 12 cycles
  • the temperature of the memory chip is detected, if the temperature is higher than the temperature corresponding
  • a corresponding relationship between temperature and write recovery time is provided, and after measuring the temperature of the memory chip, the write recovery time corresponding to the temperature is set as the storage chip according to the corresponding relationship between temperature and write recovery time.
  • the current write recovery time of the chip may be preset, for example, it is preset in the storage chip or the control chip when the storage chip leaves the factory.
  • the corresponding relationship between the temperature and the write recovery time can be obtained by testing the memory chip.
  • FIG. 3 is a schematic diagram of the corresponding relationship between temperature and write recovery time, and the numerical values thereof are for illustrative purposes only, and are not intended to limit the present application.
  • the schematic diagram of the correspondence between temperature and write recovery time includes a column of temperature T and a column of write recovery time tWR, each temperature corresponds to a write recovery time, and the corresponding write recovery time is obtained according to the detected temperature of the memory chip, The write recovery time is taken as the current write recovery time of the storage chip, and the storage chip performs operations according to the write recovery time.
  • the write recovery time corresponding to 10°C is found in the corresponding relationship. For example, if the write recovery time is 14 cycles, the control chip will set the 14 cycles as the current value of the memory chip.
  • the memory chip performs operations according to the write recovery time; when it is detected that the temperature of the memory chip is 20°C, find the write recovery time corresponding to 20°C in the corresponding relationship, for example, the write recovery time is 12 cycles, Then, the control chip sets 12 cycles as the current write recovery time of the memory chip, and the memory chip performs operations according to the write recovery time.
  • the temperature of the memory chip is measured according to a set period, and the write recovery time of the memory chip is adjusted according to the temperature.
  • the set period may be a preset time period after the memory chip is powered on. For example, after the memory chip is powered on, 10 minutes are used as a set period to measure the temperature of the memory chip, that is, every ten minutes after the memory chip is powered on. Measure the temperature of the storage chip once; or measure the temperature of the storage chip with one hour as a set period, that is, measure the temperature of the storage chip every one hour after the storage chip is powered on.
  • the temperature of the memory chip is measured, and the write recovery time of the memory chip is adjusted according to the temperature.
  • the setting command may be a trigger operation received by the memory chip.
  • the trigger operation may be any operation of issuing a trigger instruction, such as an operation of clicking a trigger button by a user, or an operation of closing a trigger button, which is not limited in this application.
  • the read/write method of the storage device of the present application can adjust the write recovery time of the storage chip according to the temperature of the storage chip, so that the write recovery time performed by the storage chip is the same as the actual write recovery when the storage chip performs the read/write operation.
  • the time is basically the same to avoid data loss or reduced running speed.
  • the storage chip has a default write recovery time, and when the storage chip is started, the default write recovery time is used as the current write recovery time of the storage chip.
  • the temperature of the memory chip is detected before the memory chip is started, and the The write recovery time corresponding to the temperature is taken as the current write recovery time of the memory chip.
  • FIG. 4 is a flowchart of a second embodiment of a method for reading and writing a storage device according to the present application.
  • the control chip Before the storage chip is powered on, the control chip starts up; the control chip obtains the temperature of the storage chip, and Obtain the write recovery time corresponding to the temperature of the storage chip; the control chip controls the power-on of the storage chip, and uses the write recovery time as the current write recovery time of the storage chip.
  • the write recovery time of the memory chip is adjusted according to the temperature before the memory chip is started, so that the write recovery time when the memory chip is started is the actual required write recovery time to avoid errors.
  • FIG. 5 is a schematic structural diagram of the first embodiment of the storage device of the present application.
  • the storage device includes a storage chip 50 , a temperature detection unit 51 and a control chip 52 .
  • the memory chip 50 is an existing memory capable of data writing, data reading and/or data deletion, and the memory chip 50 is formed by a semiconductor integrated manufacturing process.
  • the memory chip 50 may include a memory array and peripheral circuits connected to the memory array.
  • the memory array includes a plurality of memory cells and bit lines, word lines, and metal connection lines (metal contact lines) connected to the memory cells. part), the storage unit is used for storing data, and the peripheral circuit is a related circuit when operating the storage array.
  • the memory chip 50 is a DRAM memory chip, and the DRAM memory chip includes a plurality of memory cells.
  • the memory cells generally include capacitors and transistors, the gates of the transistors are connected to the word lines, and the drains are connected to the word lines. It is connected to the bit line, and the source is connected to the capacitor.
  • the memory chip 50 may be other types of memory chips.
  • the temperature detection unit 51 is used to detect the temperature of the memory chip 50 .
  • the temperature detection unit 51 includes a temperature sensor, and the temperature sensor is used for sensing temperature and converting the sensed temperature into an electrical signal.
  • the temperature sensor may be a PN junction diode temperature sensor or a capacitive temperature sensor.
  • the storage device includes one or more storage chips 50 and one or more temperature detection units 51 .
  • the temperature detection unit 51 can be used to detect the temperature of one or more memory chips 50 .
  • the temperature detection unit 51 and the memory chip 50 may have a one-to-one relationship or a one-to-many relationship.
  • the storage device includes a plurality of storage chips 50 and a plurality of temperature detection units 51 , a plurality of the storage chips 50 are stacked, and the temperature detection units 51 are in one-to-one correspondence with the storage chips 50 .
  • Four memory chips 50 and four temperature detection units 51 are schematically shown in FIG. 5 .
  • the control chip 52 is electrically connected to the memory chip 50 and the temperature detection unit 51 .
  • the control chip 52 is used to control the startup and operation of the memory chip 50 and the temperature detection unit 51 , and the control chip 52 is also used to adjust the temperature of the memory chip 50 detected by the temperature detection unit 51 .
  • Write recovery time of the memory chip 10 is used to control the startup and operation of the memory chip 50 and the temperature detection unit 51 .
  • the storage device has a look-up table
  • the look-up table records the corresponding relationship between the temperature and the write recovery time
  • the control chip 52 can adjust the write recovery time of the storage chip 50 according to the records of the look-up table.
  • the look-up table may be stored in the memory chip 50 or in the control chip 52 .
  • a plurality of memory chips 50 are stacked on the control chip 53 , and the control chip 53 is bonded to the bottommost memory chip 50 in the stacked structure.
  • the memory chip 50 is disposed on the control chip 53 , and the control chip 53 and the memory chip 50 are bonded together.
  • the temperature detection unit 51 may be formed in the memory chip 50 through a semiconductor integrated fabrication process. If the temperature detection unit 51 is only used to detect the temperature of one memory chip 50 , it can be formed in the memory chip 50 .
  • the temperature detection unit 51 is connected to the memory chip 50 . 50 are in one-to-one correspondence, and each memory chip 50 is provided with a temperature detection unit 51 . If the temperature detection unit 51 is used to detect the temperature of a plurality of memory chips 50 , it may be formed in any one of the plurality of memory chips 50 , or formed in the center or the lowest memory chip 50 .
  • FIG. 6 is a schematic structural diagram of the second embodiment of the storage device of the present application.
  • the temperature detection unit 51 is arranged in the lowest memory chip 50 and can measure four storage devices. temperature of the chip 50 .
  • the temperature detection unit 51 is not provided in the memory chip 50 , but is provided in the control chip 53 .
  • FIG. 7 is a schematic structural diagram of the third embodiment of the memory device of the present application.
  • the temperature detection unit 51 is arranged in the control chip 53 and can measure the four memory chips 50 stacked on the control chip 53 . temperature.
  • FIG. 8 is a schematic structural diagram of the fourth embodiment of the storage device of the present application.
  • the storage device further includes a circuit substrate 53 , and the circuit substrate 53 is provided with a connection circuit (Fig. (not shown in the figure), the memory chip 50 and the control chip 52 are both located on the circuit substrate 53 , and the memory chip 50 and the control chip 52 are electrically connected through the connection lines in the circuit substrate 53 .
  • the temperature detection unit 51 is also disposed on the circuit substrate 53 to measure the ambient temperature, which is close to the temperature of the memory chip 50 , which can be approximated as the temperature of the memory chip 50 .
  • the circuit substrate 53 includes but is not limited to a PCB circuit board.
  • the temperature detection unit 51 may not be disposed on the circuit substrate 53, but is disposed in the memory chip 50 as shown in FIG. 5 , FIG. 6 and FIG. 7 . Or in the control chip 53 .
  • the memory chip 50 and the control chip 53 can be electrically connected through the through silicon via interconnection structure, and the temperature detection unit 52 and the control chip 53 can be electrically connected.
  • each memory chip 50 can be connected to the control chip 53 through different through silicon via interconnect structures; when there are multiple temperature detection units 52, each temperature detection unit 52 may exist In the case where the unit 52 is connected to the control chip 53 through different through silicon via interconnection structures, there may also be a situation where a plurality of temperature detection units 52 share the through silicon via interconnection structure to be connected to the control chip 53 .
  • the memory chip 50 and the temperature detection unit 52 are connected to the control chip 53 through different through-silicon via interconnect structures, so that the temperature detection unit 52 and the memory chip 50 can use different Power supply.
  • the power supply of a plurality of the temperature detection units 52 may also share the process through-silicon via interconnection structure.
  • the storage device of the present application can perform temperature detection on the storage chip, and can adjust the write recovery time of the storage chip according to the temperature, so that the write recovery time performed by the storage chip is the same as the actual write recovery when the storage chip performs read and write operations. The time is basically the same to avoid data loss or reduced running speed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)

Abstract

本申请提供一种存储装置的读写方法及存储装置，所述存储装置包括存储芯片，所述存储装置读写方法是，在存储芯片运行期间，测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。本申请的优点在于，能够根据所述存储芯片的温度调节所述存储芯片的写恢复时间，从而使得存储芯片执行的写恢复时间与存储芯片在进行读写操作时的实际发生的写恢复时间基本一致，避免出现数据丢失或者运行速度降低的情况。

Description

存储装置的读写方法及存储装置
相关申请的交叉引用
本申请基于申请号为202010919721.8、申请日为2020年09月04日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体存储领域，尤其涉及一种存储装置的读写方法及存储装置。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
温度对存储器写入存在较大影响，在低温环境中，对存储器进行写入时，存在写入时间较长的情况，可能会导致前一次写入未完成就开始下一次预充电，进行寻址，那么前一次写入的数据就会不完整，造成丢数据的情况，从而导致写入的稳定性不高。
发明内容
本申请所要解决的技术问题是，提供一种存储装置的读写方法及存储装置，其能够避免前一次写入未完成就开始下一次预充电的情况发生，提 高存储装置写入的稳定性。
为了解决上述问题，本申请提供了一种存储装置的读写方法，所述存储装置包括存储芯片，在存储芯片运行期间，测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。
进一步，调节所述存储芯片的写恢复时间包括延长所述写恢复时间或缩短所述写恢复时间。
进一步，当所述存储芯片的温度升高时，缩短所述写恢复时间，当所述存储芯片的温度降低时，延长所述写恢复时间。
进一步，提供温度与写恢复时间的对应关系，测量所述存储芯片的温度后，根据温度与写恢复时间的对应关系将所述温度对应的写恢复时间设置为所述存储芯片的当前写恢复时间。
进一步，所述温度与写恢复时间的对应关系被预先设置。
进一步，所述存储芯片具有默认的写恢复时间，当所述存储芯片启动时，以所述默认的写恢复时间作为所述存储芯片的当前的写恢复时间。
进一步，在存储芯片启动前，检测所述存储芯片的温度，并将所述温度对应的写恢复时间作为所述存储芯片的当前写恢复时间。
进一步，在存储芯片运行期间，按设定周期测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。
进一步，在存储芯片运行期间，在所述存储芯片收到设定命令后，测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。
本申请还提供一种存储装置，其包括：存储芯片；温度检测单元，用于检测所述存储芯片的温度；控制芯片，与所述存储芯片及所述温度检测单元电连接，用于根据所述温度调节存储芯片的写恢复时间。
进一步，所述存储装置具有查询表，所述查询表记录所述温度与写恢复时间的对应关系，所述控制芯片能够根据所述查询表的记录调节存储芯片的写恢复时间。
进一步，所述温度检测单元设置在所述存储芯片或者所述控制芯片中。
进一步，所述存储装置还包括线路基板，所述线路基板中具有连接线路，所述存储芯片以及控制芯片均位于所述线路基板上，所述存储芯片和控制芯片通过所述线路基板中的所述连接线路电连接，所述温度检测单元设置在所述线路基板上。
本申请的优点在于，能够根据所述存储芯片的温度调节所述存储芯片的写恢复时间，从而使得存储芯片执行的写恢复时间与存储芯片在进行读写操作时的实际发生的写恢复时间基本一致，避免出现数据丢失或者运行速度降低的情况。
附图说明
图1是现有的存储装置的读写操作的时序图；
图2是本申请存储装置的读写方法的第一实施例的流程图；
图3是温度与写恢复时间的对应关系的示意图；
图4是本申请存储装置的读写方法的第二实施例的流程图，
图5是本申请存储装置的第一实施例的结构示意图；
图6是本申请存储装置的第二实施例的结构示意图；
图7是本申请存储装置的第三实施例的结构示意图；
图8是本申请存储装置的第四实施例的结构示意图。
具体实施方式
下面结合附图对本申请提供的存储装置的读写方法及存储装置的具体实施方式做详细说明。
图1是现有的存储装置的读写操作的时序图，请参阅图1，在该时序图中，写恢复时间tWR为12，在写恢复时间tWR后执行预充电，预充电时间为tRP。该写恢复时间tWR为存储装置在出厂时设置的预设的写恢复时 间，其不能够改变。
而如背景技术所述，温度对存储装置的写入存在较大的影响，在低温环境中，存储装置的实际发生写恢复时间tWR会延长，会大于预设的写恢复时间tWR，若存储装置还是按照预设的写恢复时间执行操作，则可能会导致前一次写入未完成就开始下一次预充电，进行寻址，那么前一次写入的数据就会不完整，造成丢数据的情况。在高温环境中，存储装置的实际发生写恢复时间tWR会缩短，会小于预设的写恢复时间tWR，若存储装置还是按照预设的写恢复时间执行操作，则会导致时间的浪费，降低存储装置的运行速度。
鉴于上述原因，本申请提供一种存储装置的读写方法，其能够根据存储装置的温度而更改存储装置的写恢复时间，从而使得存储芯片执行的写恢复时间与存储芯片在进行读写操作时的实际发生的写恢复时间基本一致，避免出现数据丢失或者运行速度降低的情况。
本申请存储装置的读写方法包括，在存储芯片运行期间，测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。
所述存储芯片的温度并非一成不变，其取决于外界环境及其自身运行时长，外界环境越低，其自身温度越低，运行时长越长，其自身温度越高，因此，本申请存储装置的读写方法能够实时监测存储芯片的温度，并根据所述温度调节调节存储芯片的写恢复时间。
在本申请一些实施例中，所述存储芯片运行期间是指自存储芯片上电启动至存储芯片下电关闭。
图2是本申请存储装置的读写方法的第一实施例的流程示意图。所述存储装置包括存储芯片及控制芯片。请参阅图2，所述存储装置的读写方法包括如下步骤：
存储芯片上电启动。在该步骤中，控制芯片对存储芯片施加电压，使得存储芯片启动。其中，在本实施例中，所述存储芯片具有默认的写恢复 时间，当所述存储芯片启动时，所述控制芯片将所述默认的写恢复时间作为所述存储芯片的当前的写恢复时间。所述默认的写恢复时间可为存储芯片出厂时预设的写恢复时间。
检测存储芯片的温度。在该步骤中，在存储芯片上电启动后，检测所述存储芯片的温度，以获取所述存储芯片的实时温度。其中，可通过温度检测单元等器件检测所述存储芯片的温度。
根据所述温度调节存储芯片的写恢复时间。在该步骤中，根据所述温度延长所述写恢复时间或缩短所述写恢复时间。当检测到所述存储芯片的温度升高时，缩短所述存储芯片的写恢复时间；当检测到所述存储芯片的温度降低时，延长所述存储芯片的写恢复时间。
具体地说，在本实施例中，在存储芯片上电启动时，控制芯片将所述默认的写恢复时间作为所述存储芯片的当前写恢复时间，例如，所述默认的写恢复时间为12周期，则所述存储芯片的当前写恢复时间为12周期，则在存储芯片启动后，检测所述存储芯片的温度，若该温度高于存储芯片默认的写恢复时间对应的温度，则在默认的写恢复时间的基础上，缩短所述写恢复时间，作为当前写恢复时间，例如，将所述写恢复时间缩短为10周期作为当前写恢复时间；若该温度低于存储芯片默认的写恢复时间对应的温度，则在默认的写恢复时间的基础上，延长所述写恢复时间，作为当前写恢复时间，例如，将所述写恢复时间延长为14周期作为当前写恢复时间。
进一步，在本实施例中，提供温度与写恢复时间的对应关系，测量所述存储芯片的温度后，根据温度与写恢复时间的对应关系将所述温度对应的写恢复时间设置为所述存储芯片的当前写恢复时间。所述温度与写恢复时间的对应关系可预先设置，例如，在存储芯片出厂时，预先设置在存储芯片或者控制芯片中。该温度与写恢复时间的对应关系可通过对存储芯片进行测试获得。
图3是温度与写恢复时间的对应关系的示意图，其数值仅为示意之用，并不用于限定本申请。请参阅图3，温度与写恢复时间的对应关系的示意图中包含温度T栏与写恢复时间tWR栏，每一温度对应一个写恢复时间，根据检测的存储芯片的温度获取对应的写恢复时间，并将该写恢复时间作为存储芯片当前的写恢复时间，存储芯片按照该写恢复时间执行操作。
例如，当检测所述存储芯片的温度为10℃时，在所述对应关系中查找10℃对应的写恢复时间，例如写恢复时间为14周期，则控制芯片将14周期设置为存储芯片的当前写恢复时间，存储芯片按照该写恢复时间执行操作；当检测所述存储芯片的温度为20℃时，在所述对应关系中查找20℃对应的写恢复时间，例如写恢复时间为12周期，则控制芯片将12周期设置为存储芯片的当前写恢复时间，存储芯片按照该写恢复时间执行操作。
进一步，在本实施例中，在存储芯片运行期间，按设定周期测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。所述设定周期可为存储芯片上电后的预设时间周期，例如存储芯片上电后以10分钟作为一个设定周期测量所述存储芯片的温度，即存储芯片上电后每隔十分钟测量一次所述存储芯片的温度；或者以一个小时作为一个设定周期测量所述存储芯片的温度，即存储芯片上电后每隔一个小时测量一次所述存储芯片的温度。
进一步，在本申请另一实施例中，在存储芯片运行期间，在所述存储芯片收到设定命令后，测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。所述设定命令可为所述存储芯片接收到的触发操作。例如，存储芯片接收到的关闭存储芯片的操作、重启存储芯片的操作、用户或者系统设定的包含检测存储芯片温度指令的触发操作等。其中，所述触发操作可以为用户点击某一触发按钮的操作、或者关闭某一触发按钮的操作等任何发出触发指令的操作，本申请对此不做任何限定。
本申请存储装置的读写方法能够根据所述存储芯片的温度调节所述存 储芯片的写恢复时间，从而使得存储芯片执行的写恢复时间与存储芯片在进行读写操作时的实际发生的写恢复时间基本一致，避免出现数据丢失或者运行速度降低的情况。
在本申请第一实施例中，所述存储芯片具有默认的写恢复时间，当所述存储芯片启动时，以所述默认的写恢复时间作为所述存储芯片的当前的写恢复时间。而在本申请另一实施例中，在所述存储芯片启动时并非将默认的写恢复时间作为当前写恢复时间，而是在存储芯片启动前，检测所述存储芯片的温度，并将所述温度对应的写恢复时间作为所述存储芯片的当前写恢复时间。具体地说，请参阅图4，其为本申请存储装置的读写方法的第二实施例的流程图，在存储芯片上电前，控制芯片启动；控制芯片获取所述存储芯片的温度，并获得所述存储芯片的温度对应的写恢复时间；控制芯片控制所述存储芯片上电，并将该写恢复时间作为所述存储芯片当前写恢复时间。在该实施例中，根据存储芯片启动前的温度调整存储芯片的写恢复时间，能够使得存储芯片启动时的写恢复时间即为其实际需要的写恢复时间，避免产生误差。
本申请还提供一种采用上述读写方法的存储装置。图5是本申请存储装置的第一实施例的结构示意图。请参阅图5，所述存储装置包括存储芯片50、温度检测单元51及控制芯片52。
所述存储芯片50为现有能进行数据写入、数据读取和/或数据删除的存储器，所述存储芯片50通过半导体集成制作工艺形成。具体的说，所述存储芯片50可以包括存储阵列和与存储阵列连接的外围电路，所述存储阵列包括多个存储单元和与存储单元连接的位线、字线、以及金属连线(金属接触部)，所述存储单元用于存储数据，所述外围电路为在对存储阵列进行操作时的相关电路。本实施例中，所述存储芯片50为DRAM存储芯片，所述DRAM存储芯片中包括多个存储单元，所述存储单元通常包括电容器和晶体管，所述晶体管的栅极与字线相连、漏极与位线相连、源极与电容 器相连。在其他实施例中所述存储芯片50可以为其他类型的存储芯片。
所述温度检测单元51用于检测所述存储芯片50的温度。所述温度检测单元51中包括温度传感器，所述温度传感器用于感应温度，将感应的温度转化为电信号。其中，所述温度传感器可为PN结二极管温度传感器或者电容式温度传感器。
所述存储装置包括一个或多个存储芯片50及一个或多个温度检测单元51。所述温度检测单元51可用于检测一个或者多个存储芯片50的温度。其中，所述温度检测单元51与所述存储芯片50可为一对一关系，或者一对多关系。
在本实施例中，所述存储装置包括多个存储芯片50及多个温度检测单元51，多个所述存储芯片50堆叠设置，所述温度检测单元51与所述存储芯片50一一对应。在图5中示意性地绘示四个存储芯片50及四个温度检测单元51。
所述控制芯片52与所述存储芯片50及所述温度检测单元51电连接。所述控制芯片52用于控制所述存储芯片50及所述温度检测单元51的启动及运行，并且所述控制芯片52还用于根据所述温度检测单元51检测的存储芯片50的温度而调节存储芯片10的写恢复时间。
进一步，所述存储装置具有查询表，所述查询表记录所述温度与写恢复时间的对应关系，所述控制芯片52能够根据所述查询表的记录调节存储芯片50的写恢复时间。其中，所述查询表可存储在存储芯片50中，也可存储在控制芯片52中。
多个存储芯片50堆叠设置在所述控制芯片53上，所述控制芯片53与堆叠结构中最底层的存储芯片50键合在一起。而在本申请另一实施例中，当只有一个存储芯片50时，所述存储芯片50设置在控制芯片53上，所述控制芯片53与该存储芯片50键合在一起。
进一步，所述温度检测单元51可通过半导体集成制作工艺形成在存储 芯片50中。若所述温度检测单元51仅用于检测一个存储芯片50的温度，则其可形成在该存储芯片50中，例如，在本实施例中，如图5所示，温度检测单元51与存储芯片50一一对应，在每一存储芯片50中均设置一个温度检测单元51。若所述温度检测单元51用于检测多个存储芯片50的温度时，其可形成在该多个存储芯片50中的任意一个存储芯片50内，或者形成在居中的或最底层的存储芯片50内。例如，在本申请第二实施例中，请参阅图6，其为本申请存储装置第二实施例的结构示意图，温度检测单元51设置在最底层的存储芯片50内，其能够测量四个存储芯片50的温度。
在本申请另一实施例中，所述温度检测单元51并未设置在存储芯片50中，而是设置在控制芯片53中。具体地说，请参阅图7，其为本申请存储装置第三实施例的结构示意图，温度检测单元51设置在控制芯片53内，其能够测量堆叠设置在控制芯片53上的四个存储芯片50的温度。
在本申请另一实施例中，请参阅图8，其为本申请存储装置第四实施例的结构示意图，所述存储装置还包括线路基板53，所述线路基板53中具有连接线路(附图中未绘示)，所述存储芯片50以及控制芯片52均位于所述线路基板53上，所述存储芯片50和控制芯片52通过所述线路基板53中的所述连接线路电连接。在该实施例中，所述温度检测单元51也设置在所述线路基板53上，以测量环境温度，该环境温度与存储芯片50温度接近，其可近似作为存储芯片50的温度。其中，所述线路基板53包括但不限于PCB电路板。可以理解的是，在本申请其他实施例中，所述温度检测单元51也可不设置在所述线路基板53上，而是如图5、图6及图7所示，设置在存储芯片50中或者控制芯片53中。
进一步，可通过硅通孔互连结构将存储芯片50与控制芯片53进行电连接，将温度检测单元52与控制芯片53电连接。具体地说，多个存储芯片50堆叠设置时，每一个存储芯片50可以通过不同的硅通孔互连结构与控制芯片53连接；当具有多个温度检测单元52时，可能存在每一个温度 检测单元52通过不同的硅通孔互连结构与控制芯片53连接的情况，也可能存在多个温度检测单元52共用硅通孔互连结构与控制芯片53连接的情况。可以理解的是，所述存储芯片50与所述温度检测单元52通过不同的硅通孔互连结构与控制芯片53连接，以使所述温度检测单元52及所述存储芯片50能够采用不同的电源供电。
进一步，多个所述温度检测单元52的供电也可共用工艺硅通孔互连结构。本申请存储装置能够对存储芯片进行温度检测，并能够根据所述温度调整存储芯片的写恢复时间，从而使得存储芯片执行的写恢复时间与存储芯片在进行读写操作时的实际发生的写恢复时间基本一致，避免出现数据丢失或者运行速度降低的情况。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (13)

  1. 一种存储装置的读写方法，所述存储装置包括存储芯片，在存储芯片运行期间，测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。
  2. 根据权利要求1所述的存储装置的读写方法，其中，调节所述存储芯片的写恢复时间包括延长所述写恢复时间或缩短所述写恢复时间。
  3. 根据权利要求2所述的存储装置的读写方法，其中，当所述存储芯片的温度升高时，缩短所述写恢复时间，当所述存储芯片的温度降低时，延长所述写恢复时间。
  4. 根据权利要求1所述的存储装置的读写方法，其中，提供温度与写恢复时间的对应关系，测量所述存储芯片的温度后，根据温度与写恢复时间的对应关系将所述温度对应的写恢复时间设置为所述存储芯片的当前写恢复时间。
  5. 根据权利要求4所述的存储装置的读写方法，其中，所述温度与写恢复时间的对应关系被预先设置。
  6. 根据权利要求1所述的存储装置的读写方法，其中，所述存储芯片具有默认的写恢复时间，当所述存储芯片启动时，以所述默认的写恢复时间作为所述存储芯片的当前的写恢复时间。
  7. 根据权利要求1所述的存储装置的读写方法，其中，在存储芯片启动前，检测所述存储芯片的温度，并将所述温度对应的写恢复时间作为所述存储芯片的当前写恢复时间。
  8. 根据权利要求1所述的存储装置的读写方法，其中，在存储芯片运行期间，按设定周期测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。
  9. 根据权利要求1所述的存储装置的读写方法，其中，在存储芯片运 行期间，在所述存储芯片收到设定命令后，测量所述存储芯片的温度，并根据所述温度调节存储芯片的写恢复时间。
  10. 一种存储装置，包括：存储芯片；
    温度检测单元，用于检测所述存储芯片的温度；
    控制芯片，与所述存储芯片及所述温度检测单元电连接，用于根据所述温度调节存储芯片的写恢复时间。
  11. 根据权利要求10所述的存储装置，其中，所述存储装置具有查询表，所述查询表记录所述温度与写恢复时间的对应关系，所述控制芯片能够根据所述查询表的记录调节存储芯片的写恢复时间。
  12. 根据权利要求10所述的存储装置，其中，所述温度检测单元设置在所述存储芯片或者所述控制芯片中。
  13. 根据权利要求10所述的存储装置，其中，所述存储装置还包括线路基板，所述线路基板中具有连接线路，所述存储芯片以及控制芯片均位于所述线路基板上，所述存储芯片和控制芯片通过所述线路基板中的所述连接线路电连接，所述温度检测单元设置在所述线路基板上。
PCT/CN2021/100676 2020-09-04 2021-06-17 存储装置的读写方法及存储装置 WO2022048240A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21863308.9A EP4024396B1 (en) 2020-09-04 2021-06-17 Read/write method for storage device, and storage device
US17/470,879 US11862229B2 (en) 2020-09-04 2021-09-09 Reading and writing method of memory device and memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010919721.8 2020-09-04
CN202010919721.8A CN114141287B (zh) 2020-09-04 2020-09-04 存储装置的读写方法及存储装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/470,879 Continuation US11862229B2 (en) 2020-09-04 2021-09-09 Reading and writing method of memory device and memory device

Publications (1)

Publication Number Publication Date
WO2022048240A1 true WO2022048240A1 (zh) 2022-03-10

Family

ID=80438218

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/100676 WO2022048240A1 (zh) 2020-09-04 2021-06-17 存储装置的读写方法及存储装置

Country Status (2)

Country Link
CN (1) CN114141287B (zh)
WO (1) WO2022048240A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050018507A1 (en) * 2003-07-17 2005-01-27 Stephan Schroder Circuit and method for controlling an access to an integrated memory
US20140359242A1 (en) * 2013-06-03 2014-12-04 Samsung Electronics Co., Ltd. Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device
US20150279446A1 (en) * 2014-03-27 2015-10-01 John B. Halbert Method, apparatus and system for determining a write recovery time of a memory based on temperature
CN107978329A (zh) * 2016-10-21 2018-05-01 爱思开海力士有限公司 包括存储器件和存储器控制器的存储系统
CN110910927A (zh) * 2018-09-17 2020-03-24 美光科技公司 用于运用反向温度系数延迟控制dram字线的设备和方法
WO2020101975A1 (en) * 2018-11-15 2020-05-22 Micron Technology, Inc. Temperature-based memory management

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434082B1 (en) * 2001-03-13 2002-08-13 International Business Machines Corporation Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock
TWI473103B (zh) * 2011-09-14 2015-02-11 威剛科技股份有限公司 快閃記憶體儲存裝置及其不良儲存區域的判定方法
JP2014102741A (ja) * 2012-11-21 2014-06-05 Ricoh Co Ltd メモリコントローラ及びメモリコントローラのライトレベリング制御方法
KR20160074920A (ko) * 2014-12-19 2016-06-29 에스케이하이닉스 주식회사 메모리 장치
CN109445982A (zh) * 2018-09-17 2019-03-08 至誉科技（武汉）有限公司 实现数据可靠读写的数据存储装置
CN111240582B (zh) * 2018-11-29 2022-01-28 长鑫存储技术有限公司 数据读写方法、读写装置和动态随机存储器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050018507A1 (en) * 2003-07-17 2005-01-27 Stephan Schroder Circuit and method for controlling an access to an integrated memory
US20140359242A1 (en) * 2013-06-03 2014-12-04 Samsung Electronics Co., Ltd. Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device
US20150279446A1 (en) * 2014-03-27 2015-10-01 John B. Halbert Method, apparatus and system for determining a write recovery time of a memory based on temperature
CN107978329A (zh) * 2016-10-21 2018-05-01 爱思开海力士有限公司 包括存储器件和存储器控制器的存储系统
CN110910927A (zh) * 2018-09-17 2020-03-24 美光科技公司 用于运用反向温度系数延迟控制dram字线的设备和方法
WO2020101975A1 (en) * 2018-11-15 2020-05-22 Micron Technology, Inc. Temperature-based memory management

Also Published As

Publication number Publication date
CN114141287A (zh) 2022-03-04
CN114141287B (zh) 2024-03-26

Similar Documents

Publication Publication Date Title
US7898892B2 (en) Method and system for controlling refresh to avoid memory cell data losses
JP4778889B2 (ja) 可変リフレッシュ制御を有するメモリおよびその方法
US7464315B2 (en) Semiconductor memory device
US6084812A (en) Device and method for varying bit line precharge voltage in semiconductor memory
TWI736714B (zh) 包括虛擬故障產生器的記憶體裝置及其記憶單元修復方法
JP2006114205A (ja) 温度センサーの不良を感知するメモリ装置、これを用いたメモリ装置の動作方法及びテスト方法
WO2021189887A1 (zh) 半导体结构及其预热方法
US11862229B2 (en) Reading and writing method of memory device and memory device
WO2022048240A1 (zh) 存储装置的读写方法及存储装置
WO2022000927A1 (zh) 半导体装置
US20220310620A1 (en) Memory device including calibration operation and transistor having adjustable threshold voltage
US6876590B2 (en) 2T2C signal margin test mode using a defined charge exchange between BL and/BL
WO2022000926A1 (zh) 半导体装置
WO2005027140A1 (en) Signal margin test mode for feram with ferroelectric reference capacitor.
WO2023134002A1 (zh) 存储器的检测方法、装置及模拟检测方法
US20210407554A1 (en) Semiconductor device
KR100338817B1 (ko) 복합 반도체장치의 리프레쉬 특성 자가 테스터
WO2022000928A1 (zh) 半导体装置
WO2022011955A1 (zh) 半导体装置
WO2023197399A1 (zh) 一种存储器的测试方法、装置及存储器系统
US20220020426A1 (en) Semiconductor device
JP2002056672A (ja) 半導体記憶装置
KR20020076547A (ko) 번인 테스트 모드 회로
KR20050055976A (ko) 반도체 메모리 소자의 기록마진 시간의 개선 방법
JPH03156792A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2021863308

Country of ref document: EP

Effective date: 20220329

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21863308

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE