WO2022000928A1 - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
WO2022000928A1
WO2022000928A1 PCT/CN2020/128136 CN2020128136W WO2022000928A1 WO 2022000928 A1 WO2022000928 A1 WO 2022000928A1 CN 2020128136 W CN2020128136 W CN 2020128136W WO 2022000928 A1 WO2022000928 A1 WO 2022000928A1
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WIPO (PCT)
Prior art keywords
memory chip
semiconductor device
temperature detection
temperature
unit
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Application number
PCT/CN2020/128136
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English (en)
French (fr)
Inventor
寗树梁
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020227033535A priority Critical patent/KR20220139406A/ko
Priority to JP2022552660A priority patent/JP7352750B2/ja
Priority to EP20943341.6A priority patent/EP4092675A4/en
Priority to US17/389,654 priority patent/US20210407571A1/en
Publication of WO2022000928A1 publication Critical patent/WO2022000928A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations

Definitions

  • the present invention relates to the field of memory, and in particular, to a semiconductor device.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and its memory array area is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line The data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • the technical problem to be solved by the present invention is to provide a semiconductor device, which can measure the temperature of the memory chip, avoid the memory chip from starting and running at low temperature, shorten the writing time, and improve the writing stability of the memory chip; It can ensure the measurement accuracy of the area that needs to be accurately measured, and can improve the measurement efficiency.
  • the present invention provides a semiconductor device, which is characterized by comprising a memory chip and a temperature detection module, the temperature detection module is used to detect the temperature of the memory chip, and the temperature detection module includes: a temperature detection module a unit, used to detect the temperature of the memory chip, and output an analog signal corresponding to the temperature; an A/D conversion module, including a plurality of comparison units, the comparison units include an input end, a reference end and an output end, so The input terminal receives an analog signal output by the temperature detection unit, the output terminal outputs a digital signal, and the reference voltages received by the reference terminals of the plurality of comparison units increase non-uniformly.
  • the increase of the reference voltage is smaller than the increase of the reference voltage in other reference voltage ranges.
  • the memory chip is activated.
  • the set threshold corresponds to a threshold voltage, and the threshold voltage is within the preset reference voltage range.
  • the A/D conversion module further includes a resistance unit, the resistance unit has a plurality of lead-out terminals, the voltages of the plurality of lead-out ends increase non-uniformly, and the voltage of the lead-out ends is received as the reference end of the comparison unit the reference voltage.
  • the resistance unit has a first end and a second end, the first end of the resistance unit is electrically connected to the power supply, the second end of the resistance unit is electrically connected to the ground end, and the lead-out end is arranged on the between the first end and the second end.
  • the resistance unit includes a plurality of sub-resistors connected in series, and the number of the sub-resistors spaced between each lead end of the resistance unit and the second end of the resistance unit is different, so that the voltage of each lead end is different. different.
  • the number of sub-resistors spaced between adjacent lead-out terminals includes two states of the same and different states, so that the reference voltages received by the reference terminals of the plurality of comparison units are non-uniform. Increase.
  • the number of sub-resistors spaced between adjacent lead terminals is smaller than the number of sub-resistors spaced between adjacent lead ends in other regions.
  • the resistance values of the sub-resistors are the same.
  • sub-resistors are polysilicon resistors, and the sub-resistors are electrically connected through the first layer of metal wires.
  • the lead-out terminal is formed by the second-layer metal wire of the resistance unit.
  • the A/D conversion module further includes an encoding unit, and the encoding unit receives and encodes the digital signal of the comparison unit.
  • the A/D conversion module further includes an output unit, the output unit is connected to the comparison unit, and is used for outputting the digital signal.
  • the temperature detection unit includes: a fixed-value resistor with a first end and a second end, the first end is electrically connected to a power supply; a diode is connected in series with the fixed-value resistor, and the positive end of the diode is connected to the The second terminal of the constant-value resistor is electrically connected, and the negative terminal of the diode is electrically connected to the ground terminal.
  • the temperature detection unit further includes an adjustable resistor, and the adjustable resistor is connected in parallel with the diode.
  • the temperature detection unit is provided in the memory chip.
  • the temperature detection unit and the memory chip share the same ground terminal.
  • the temperature detection unit and the memory chip are powered by different power sources.
  • the power supply of the temperature detection unit is earlier than the power supply of the memory chip.
  • the semiconductor device further includes a control chip, and the memory chip and the temperature detection unit are electrically connected to the control chip.
  • control chip is used to heat the memory chip before the memory chip is started, and determine whether the temperature detected by the temperature detection unit reaches a set threshold, and if it reaches the set threshold, control the memory chip to start.
  • the advantage of the present invention is that the temperature of the memory chip is detected by the temperature detection module, when the temperature detected by the temperature detection module reaches a set threshold, the memory chip starts up, and the temperature detected by the temperature detection module is the startup and operation of the memory chip Provide a reference, so as to prevent the memory chip from starting and running at low temperature, shorten the writing time, and improve the writing stability of the memory chip; at the same time, it is controlled by the non-uniform increase of the reference voltage received by the reference terminals of the plurality of comparison units.
  • the measurement accuracy of different voltage regions can not only ensure the measurement accuracy of the region that needs to be accurately measured, but also save the circuit and improve the measurement efficiency.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a semiconductor device of the present invention
  • FIG. 2 is a circuit diagram of a temperature detection module of the semiconductor device of the present invention.
  • FIG. 3 is a circuit diagram of a resistance unit of the first embodiment of the semiconductor device of the present invention.
  • FIG. 4 is a circuit diagram of a resistance unit of another embodiment of the semiconductor device of the present invention.
  • FIG. 5 is a schematic structural diagram of a second embodiment of the semiconductor device of the present invention.
  • FIG. 6 is a schematic structural diagram of a third embodiment of the semiconductor device of the present invention.
  • FIG. 7 is a schematic structural diagram of a fourth embodiment of the semiconductor device of the present invention.
  • FIG. 8 is a schematic diagram of electrical connection of the first embodiment of the semiconductor device of the present invention.
  • the present invention provides a semiconductor device, which uses a temperature detection module to detect the temperature of the memory chip, so as to provide a reference for the start-up and operation of the memory chip, thereby preventing the memory chip from starting and operating at low temperature, shortening the writing time, and improving the performance of the memory chip. Stability of memory chip writing.
  • the semiconductor device of the present invention can also improve the accuracy of temperature measurement.
  • FIG. 1 is a schematic structural diagram of a first embodiment of the semiconductor device of the present invention
  • FIG. 2 is a circuit diagram of a temperature detection module in the semiconductor device of the present invention.
  • the semiconductor device of the present invention includes a memory chip 100 and a temperature detection module 110.
  • the semiconductor device further includes a control chip 120 , the memory chip 100 and the temperature detection module 110 are electrically connected to the control chip 120 .
  • the control chip 120 is used to control the startup and operation of the memory chip 100 and the temperature detection module 110 .
  • the startup of the memory chip 100 includes power-on and self-checking.
  • the operation of the memory chip 100 may include writing data into the memory chip 100 , reading data from the memory chip 100 , and accessing the data in the memory chip 100 . delete etc.
  • the memory chip 100 is an existing memory capable of data writing, data reading and/or data deletion, and the memory chip 100 is formed by a semiconductor integrated manufacturing process.
  • the memory chip 100 may include a memory array and peripheral circuits connected to the memory array.
  • the memory array includes a plurality of memory cells and bit lines, word lines, and metal wirings (metal contact lines) connected to the memory cells. part), the storage unit is used for storing data, and the peripheral circuit is a related circuit when operating the storage array.
  • the memory chip 100 is a DRAM memory chip, and the DRAM memory chip includes a plurality of memory cells.
  • the memory cells generally include capacitors and transistors, the gates of the transistors are connected to the word lines, and the drains are connected to the word lines. It is connected to the bit line, and the source is connected to the capacitor.
  • the memory chip 100 may be other types of memory chips.
  • the temperature detection module 110 is used to detect the temperature of the memory chip 100 and provide a signal to the control chip 120. When the temperature detected by the temperature detection module 110 reaches a set threshold, the control chip 120 controls the memory chip 100 to start up.
  • the specific size of the set threshold may be set according to actual needs or experience.
  • the temperature detection module 110 includes a temperature detection unit 111 and an A/D conversion module 112 .
  • the temperature detection unit 111 is configured to detect the temperature of the memory chip 100 and output an analog voltage signal corresponding to the temperature.
  • the A/D conversion module 112 is configured to convert the analog voltage signal output by the temperature detection unit 111 into a digital signal, and the digital signal is provided to the control chip 120 as a reference signal for whether the memory chip 100 is activated.
  • the A/D conversion module 112 includes a plurality of comparison units Px, and the comparison units Px include an input terminal, a reference terminal and an output terminal.
  • the input terminal receives an analog voltage signal output by the temperature detection unit 111
  • the reference terminal receives a reference voltage signal
  • the output terminal outputs a digital signal.
  • the analog voltage signal of the input terminal is compared with the reference voltage signal of the reference terminal, and the output terminal outputs a comparison result, and the comparison result is the digital signal.
  • the reference voltages received by the reference terminals of the plurality of comparison units Px increase non-uniformly, so that in different voltage regions, the reference voltages have different increases, thereby changing the measurement accuracy of the voltage region.
  • the increase of the reference voltage is smaller than the increase of the reference voltage in other reference voltage ranges. Specifically, for the voltage region that needs accurate measurement, a small reference voltage increase can be used to improve the measurement accuracy of the region, and for the voltage region that does not require accurate measurement, a large reference voltage increase can be used to improve the measurement efficiency.
  • the voltage region that needs to be accurately measured is 1.2V ⁇ 1.7V
  • the corresponding reference voltage range is 1.2V ⁇ 1.7V
  • the increase of the reference voltage in the 1.2V ⁇ 1.7V voltage region can be set to 0.1V
  • increase sampling The number of points can improve the measurement accuracy
  • the increase of the reference voltage in the voltage region with voltage less than 1.2V and greater than 1.7V can be set to 0.3V, appropriately reducing the number of sampling points, improving the measurement efficiency, and reducing the circuit used.
  • the 1.2V-1.7V voltage region can be further divided into smaller regions, for example, 1.2V-1.3V is the first voltage region, 1.3V-1.5V is the second voltage region, 1.5V V ⁇ 1.7V is the third voltage region, the first voltage region and the third voltage region can use the same reference voltage increase, eg, 0.1V, and the second voltage region can use a smaller voltage increase, such as 0.05V.
  • the selection of the preset reference voltage range may be determined according to the startup temperature of the memory chip 100, so that the startup temperature can be accurately detected. Specifically, when the temperature detection module 110 detects that the temperature of the memory chip 100 reaches a set threshold, the control chip 120 controls the memory chip 100 to start up, and the set threshold is the start of the memory chip 100 temperature. In order to enable the temperature detection module 110 to accurately detect the set threshold, it is necessary to improve the measurement accuracy of the voltage region where the threshold voltage corresponding to the set threshold is located, and to accurately detect the threshold voltage, Thus, the startup temperature of the memory chip can be accurately determined. Therefore, the voltage region where the threshold voltage corresponding to the set threshold is located is set as a preset reference voltage range, and within the preset reference voltage range, the increase of the reference voltage is smaller than the increase of the reference voltage in other reference voltage ranges .
  • the semiconductor device of the present invention controls the measurement accuracy of different voltage regions through the non-uniform increase of the reference voltages received by the reference terminals of the plurality of comparison units, thereby not only ensuring the measurement accuracy of the region requiring accurate measurement, but also improving the measurement efficiency.
  • the present invention provides a structure capable of non-uniformly increasing the reference voltages received by the reference terminals of a plurality of the comparison units.
  • the A/D conversion module 112 further includes a resistance unit 1121 .
  • the resistance unit 1121 has a first end and a second end. The first end of the resistance unit 1121 is electrically connected to a power source.
  • the resistance unit 1121 and the temperature detection unit 111 may use the same power source, or may use different power sources. For example, if the A/D conversion module 112 is arranged in the memory chip 100, the first end of the resistance unit 1121 and the temperature detection unit 111 can use the same power supply Vtemp; if the A/D conversion module 112 If disposed in the control chip 120, the first end of the resistance unit 1121 and the temperature detection unit 111 may use different power supplies, and the resistance unit may use the power supply VDD.
  • the second terminal of the resistance unit is electrically connected to the ground terminal VSS.
  • the resistance unit 1121 has a plurality of lead terminals Ax, the voltage of each lead end Ax is different, and the voltages of the plurality of lead ends Ax increase non-uniformly.
  • Each of the extraction terminals Ax is electrically connected to the reference terminal of the comparison unit Px, and the voltage of each of the extraction terminals Ax is used as the reference voltage of the reference terminal of the comparison unit Px.
  • the lead-out terminal Ax corresponds to the comparison unit Px one-to-one.
  • the resistance unit includes a plurality of sub-resistors Rn connected in series.
  • the resistance values of the sub-resistors Rn may be the same.
  • FIG. 3 is a circuit diagram of the resistor unit according to the first embodiment.
  • the resistance values of the sub-resistors Rn are the same, so as to simplify the layout difficulty, be simple and easy to manufacture.
  • the number of the sub-resistors Rx spaced between the adjacent lead-out terminals Ax includes the same and different states, so that the reference voltages received by the reference terminals of the plurality of comparison units Px are non-uniform increase.
  • the number of sub-resistors Rx spaced between adjacent terminals Ax is different.
  • the adjacent terminals Ax The number of spaced sub-resistors Rx is the same.
  • the number of sub-resistors spaced between adjacent lead-out terminals is the same, but smaller than the adjacent lead-out ends in other regions
  • the number of sub-resistors spaced therebetween is used to increase the preset sampling number of the resistance unit region corresponding to the reference voltage, thereby improving the measurement accuracy of the region.
  • the resistance unit includes sub-resistors R1 to R23 connected in series, and a lead-out end A1 is formed at three sub-resistors R1, R2 and R3 spaced apart from the second end VSS of the resistance unit, and the lead-out end is connected to the lead-out end.
  • A1 is separated from three sub-resistors R4, R5 and R6 to form a lead-out end A2, and a lead-out end A3 is formed at three sub-resistors R7, R8 and R9 separated from the lead-out end A2, and the lead-out end A1, the lead-out end A2 and the lead-out end A3 are spaced
  • the number of sub-resistors is the same, and they are all three; the lead-out end A4 is formed at the three sub-resistors R10 and R11 separated from the lead-out end A3, and the lead-out end A5 is formed at the three sub-resistors R12 and R13 separated from the lead-out end A4.
  • the leading end A5 is separated from the three sub-resistors R14 and R15 to form the leading end A6, and the leading end A7 is formed at the three sub-resistors R16 and R17 separated from the leading end A6.
  • the leading end A3, the leading end A4, the leading end A5, the leading end A6 and the The number of sub-resistors spaced between the lead-out end A7 is the same, both are 2; the lead-out end A8 is formed at the three sub-resistors R18, R19 and R20 separated from the lead-out end A7, and the three sub-resistors R21 and R22 are separated from the lead-out end A8.
  • a lead end A9 is formed at and R23, and the number of sub-resistors spaced between the lead end A7, the lead end A8 and the lead end A9 is the same, and all are three.
  • the range formed by the voltages output by the lead terminals A3 to A7 is a preset reference voltage range, and the voltage increase is reduced, thereby improving the measurement accuracy.
  • a lead end is added between the lead ends A3 to A7 to further increase the number of samples and improve the measurement accuracy.
  • FIG. 4 is a circuit diagram of a resistor unit according to another embodiment.
  • a lead end A31 is added between the lead ends A3 and A4 , and the lead end A31 and the lead ends A3 and A4 are both connected to each other.
  • a sub-resistor is spaced apart; a lead-out end A41 is added between the lead-out ends A4 and A5, and a sub-resistor is spaced between the lead-out end A41 and the lead-out ends A4 and A5; a lead-out end is added between the lead-out ends A5 and A6 A51, a sub-resistor is spaced between the lead-out end A51 and the lead-out ends A5 and A6; a lead-out end A61 is added between the lead-out ends A6 and A7, and the lead-out end A61 is connected to the lead-out ends A6 and A7. There is a sub-resistor between them.
  • the sub-resistors Rx are polysilicon resistors, and the sub-resistors are electrically connected through a first-layer metal wire.
  • the resistance unit forms the lead-out terminal Ax through the second-layer metal wire.
  • the A/D conversion module 112 further includes an output unit 1120, the output unit 1120 is connected to the comparison unit Px, and is used for outputting the digital signal. Further, in this embodiment, the A/D conversion module 112 further includes an encoding unit EEC, the encoding unit EEC receives the digital signal output by the comparison unit Px, and performs encoding, and the formed signal is input to the output Unit 1120, the output unit 1120 outputs the encoded digital signal.
  • the semiconductor device includes one or more memory chips 100 , and the temperature detection module 110 includes one or more temperature detection units 111 .
  • the temperature detection unit 111 can be used to detect the temperature of one or more memory chips 100 .
  • the temperature detection unit 111 and the memory chip 100 may be in a one-to-one relationship or a one-to-many relationship.
  • the temperature detection unit 111 and the memory chip 100 are in a one-to-one relationship, and the temperature detection unit 111 It is only used to detect the temperature of the memory chip 100 .
  • the temperature detection unit 111 and the memory chip 100 are in a one-to-many relationship, and the temperature detection unit 111 has a one-to-many relationship. It is used for detecting the temperature of a plurality of the memory chips 100 .
  • the The temperature detection unit 111 and the memory chip 100 may have a one-to-one relationship and a one-to-many relationship at the same time, or only a one-to-many relationship. That is, there may be a situation in which one temperature detection unit 111 detects the temperature of only one memory chip 100 and one temperature detection unit 100 detects the temperature of a plurality of the memory chips 100 , or only one temperature detection unit 100 detects a plurality of the temperature of the memory chip 100 .
  • the The temperature detection unit 111 is in a one-to-one relationship with the memory chip 100 , and one of the temperature detection units 111 is used to detect the temperature of one of the memory chips 100 .
  • the number of the memory chips 100 is plural, and the number of the temperature detection units 111 is also plural, as shown in FIG. 1 , which is schematically drawn in FIG. 1 .
  • Four memory chips 100 and four temperature detection units 111 are shown, a plurality of the memory chips 100 are stacked and arranged, and the temperature detection units 111 are in one-to-one correspondence with the memory chips 100 .
  • the temperature detection unit 111 includes a constant-value resistor Ra and a diode D.
  • the constant-value resistor Ra has a first end and a second end, and the first end is electrically connected to the power supply Vtemp.
  • the diode D is connected in series with the fixed-value resistor Ra, the positive terminal of the diode D is connected to the second terminal of the fixed-value resistor Ra, and the negative terminal of the diode D is electrically connected to the ground terminal VSS.
  • the diode D is sensitive to temperature, and as the temperature of its surrounding environment changes, its current changes, which can then be used to measure the temperature of the surrounding environment.
  • the temperature detection unit 111 further includes an adjustable resistor Rb, and the adjustable resistor Rb is connected in parallel with the diode D for calibrating the diode D.
  • the resistance value of the adjustable resistor Rb can be changed, for example, the resistance value of the adjustable resistor Rb can be changed through the control of the control chip 120 , so that the calibration of the diode D can be realized.
  • the temperature detection unit 111 may be formed in the memory chip 100 through a semiconductor integrated fabrication process. If the temperature detection unit 111 is only used to detect the temperature of one memory chip 100, it can be formed in the memory chip 100. For example, in this embodiment, as shown in FIG. 1, the temperature detection unit 111 and the memory chip 100 are in one-to-one correspondence, and each memory chip 100 is provided with a temperature detection unit 111 . If the temperature detection unit 111 is used to detect the temperature of a plurality of memory chips 100 , it can be formed in any one of the memory chips 100 of the plurality of memory chips 100 , or formed in the middle or bottommost memory chip 100 . Inside. For example, in the second embodiment of the present invention, please refer to FIG. 5 , which is a schematic structural diagram of the second embodiment of the semiconductor device of the present invention. The temperature detection unit 111 is arranged in the bottommost memory chip 100 and can measure four memory chips. temperature of the chip 100 .
  • the temperature detection unit 111 is not provided in the memory chip 100 , but is provided in the control chip 120 .
  • FIG. 6 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present invention.
  • the temperature detection unit 111 is disposed in the control chip 120 and can measure the four memory chips 100 stacked on the control chip 120 . temperature.
  • FIG. 7 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present invention.
  • the semiconductor device further includes a circuit substrate 130 having connection lines therein (Fig. (not shown), the memory chip 100 and the control chip 120 are both located on the circuit substrate 130 , and the memory chip 100 and the control chip 120 are electrically connected through the connection lines in the circuit substrate 130 .
  • the temperature detection unit 111 is also disposed on the circuit substrate 130 to measure the ambient temperature, which is close to the temperature of the memory chip 100 , which can be approximated as the temperature of the memory chip 100 .
  • the circuit substrate 130 includes but is not limited to a PCB circuit board.
  • the temperature detection unit 111 may not be disposed on the circuit substrate 130 , but is disposed in the memory chip 100 as shown in FIG. 1 , FIG. 5 and FIG. 6 . Or in the control chip 120 .
  • control chip 120 in controlling the startup of the memory chip 100 in the embodiment of the present invention can also be realized by setting a control circuit in the memory chip 100.
  • the existence of the control chip 120 is not required, and the art Those skilled in the art should understand that it can be set by themselves as required.
  • the temperature detection unit 111 and the memory chip 100 are powered by different power sources.
  • 8 is a schematic diagram of electrical connection of the semiconductor device according to the first embodiment of the present invention. Please refer to FIG. 8 .
  • the temperature detection unit 111 is powered by the power supply Vtemp
  • the memory chip 100 is powered by the VDD.
  • the ground terminal VSS, the power supply VDD and the power supply Vtemp are provided by the control chip 120 . Since the temperature detection unit 111 and the memory chip 100 are powered by different power sources, the power supply of the temperature detection unit 111 and the memory unit 100 can be independently controlled, so that the temperature detection unit 111 and the storage unit 100 can be independently controlled.
  • the memory chip 100 is not activated at the same time.
  • the present invention can control the activation of the temperature detection unit 111 and the memory chip 100 respectively, that is, the activation of the temperature detection unit 111 is not affected by whether the memory chip 100 is activated, so that the temperature detection of the memory chip 100 is not affected by the memory chip 100.
  • the influence of whether the chip 100 is started can provide a reference for the start and operation of the memory chip 100 , thereby preventing the memory chip 100 from starting or running at a low temperature, and improving the stability of the memory chip 100 .
  • temperature has a great influence on the performance of the memory chip 100 , especially when the memory chip 100 is started up. If the memory chip 100 is started at a low temperature, the time for writing data into the memory chip 100 will change (eg, lengthen), which will affect the stability of the memory chip 100 writing. temperature so that the memory chip 100 can be activated within a suitable temperature.
  • the power supply of the temperature detection unit 111 in the present invention is earlier than the power supply of the memory chip 100 , that is, before the memory chip 100 is started, the temperature detection unit 111 has been started, so that the temperature before the start of the memory chip 100 can be obtained.
  • the temperature provides a reference for the startup of the memory chip 100 .
  • the power supply time difference between the temperature detection unit 111 and the memory chip 100 depends on the temperature change rate of the memory chip 100.
  • the temperature change rate of the memory chip 100 is large, the time for the memory chip 100 to reach the preset temperature is short, the power supply time difference between the temperature detection unit 111 and the memory chip 100 is small, and if the temperature change rate of the memory chip 100 is small and the time for the memory chip 100 to reach the preset temperature is long, the temperature detection The power supply time difference between the unit 111 and the memory chip 100 is large.
  • the temperature detection unit 111 and the memory chip 100 share the same ground terminal VSS.
  • the advantage is that, on the one hand, the leakage current of the memory chip 100 in the non-starting stage will not be increased, and on the other hand, the number of pins will be reduced and space will be saved.
  • a plurality of memory chips 100 are stacked on the control chip 120 , and the control chip 120 is bonded to the bottommost memory chip 100 in the stacked structure.
  • the memory chip 100 is disposed on the control chip 120, and the control chip 120 and the memory chip 100 are bonded together.
  • the memory chip 100 is formed with a through silicon via interconnection structure 101 , and the memory chip 100 and the control chip 120 are electrically connected through the through silicon via interconnection structure 101 , and the temperature detection unit 111 is electrically connected with the control chip 120 . That is, the memory chip 100 is electrically connected to the ground terminal VSS and the power supply VDD through the through silicon via interconnection structure 101 , and the temperature detection unit 111 is electrically connected to the power supply Vtemp and the ground terminal VSS.
  • each memory chip 100 when a plurality of memory chips 100 are stacked and arranged, each memory chip 100 can be connected to the control chip 120 through different through-silicon via interconnect structures; when there are multiple temperature detection units 111, There may be a situation where each temperature detection unit 111 is connected to the control chip 120 through different through silicon via interconnect structures, and there may also be a situation where multiple temperature detection units 111 share a through silicon via interconnect structure to be connected to the control chip 120 . It can be understood that the memory chip 100 and the temperature detection unit 111 are connected to the control chip 120 through different through-silicon via interconnect structures, so that the temperature detection unit 111 and the memory chip 100 can use different Power supply. Further, the power supply of a plurality of the temperature detection units 111 can also share the process through-silicon via interconnection structure.
  • the memory chip 100 and the temperature detection unit may also be electrically connected to the control chip 120 through metal wires (formed by a wire bonding process).
  • the control chip 120 of the present invention can also be started before the memory chip 100 is started, and the control chip 120 uses the heat generated by itself to heat the memory chip 100 after being started to rapidly increase the temperature of the memory chip 100 .
  • control chip 120 controls the temperature detection unit 111 to be activated to detect the temperature of the memory chip 100 .
  • the temperature detection unit 111 can also transmit the detected temperature to the control chip 120 as data of the control chip 120 .
  • the control chip 120 can determine whether the temperature detected by the temperature detection unit 111 reaches the set threshold, and if the temperature reaches the set threshold, the memory chip 100 is controlled to start up.
  • the control unit 120 determines that the temperature detected by the temperature detection unit 111 reaches the set threshold, Then the control chip 120 controls the memory chip 100 to start up.
  • the control unit 120 determines that the temperature detected by the temperature detection unit 111 reaches the set threshold, then The control unit 120 first controls the memory chip 100 closest to the control chip 120 to start up, and then controls the other memory chips 100 above to start up in sequence.
  • temperature detection units 111 and multiple memory chips 100 there are multiple temperature detection units 111 and multiple memory chips 100, and there may be a temperature detection unit 111 that detects the temperature of only one memory chip 100 and a temperature detection unit 111 that detects the temperature of multiple memory chips 100 situation, or only one temperature detection unit 111 detects the temperature of a plurality of the memory chips 100, when the control unit 120 determines that the temperature detected by a certain temperature detection unit 111 reaches the set threshold, it controls the temperature detection unit 111 corresponding to If the temperature detection unit 111 detects the temperature of multiple memory chips 100, it first controls the memory chip 100 closest to the control chip 120 to start up, and then controls the other memory chips 100 above to start up in sequence.
  • the control unit 110 determines that the temperature detected by a certain temperature detection unit 111 reaches the set threshold
  • the memory chip 100 corresponding to the temperature detection unit 111 is controlled to start up.
  • there are 4 memory chips 100 in the stacked structure shown in FIG. 1 and each memory chip 100 has a corresponding temperature detection unit 111 , so each temperature detection unit 111 can detect the temperature of the corresponding memory chip 100 .
  • the control chip 120 will sequentially determine whether the temperature detected by the four temperature detection units 111 reaches the set threshold value, if the temperature detected by a certain temperature detection unit 111 reaches the set threshold value , then control the memory chip corresponding to the temperature detection unit 111 to start up. For example, when the temperature detected by the temperature detection unit 111 in the bottommost memory chip 100 in the stack structure first reaches the set threshold, the control chip 120 first controls the stack structure. The memory chip 100 at the bottom layer starts up, and then, when the temperature detected by the temperature detection unit 111 corresponding to the memory chip 100 in the penultimate layer in the stack structure also reaches the set threshold, the control unit 301 then controls the temperature in the stack structure. The memory chip 100 in the penultimate layer is activated, and the memory chips 100 in the upper two layers are activated and so on.
  • the aforementioned control structure and control method can further improve the accuracy of the start-up timing of each memory chip 100, and can further reduce the need for each memory chip 100 in a low temperature environment.
  • the writing time during data writing further improves the stability of writing to each memory chip 100 .
  • the temperature of the memory chip 100 can be increased to a set threshold by controlling the chip 120, thereby preventing the bit lines, word lines, and metal connections (metal contacts) in the memory chip 100 from The resistance increases due to the low ambient temperature, thereby reducing the writing time when writing data to the storage chip in a low temperature environment, and improving the writing stability of the storage chip.
  • the set threshold can be set in the control chip 120, and the specific size of the set threshold can be set according to actual needs or experience.
  • control chip 120 may have an additional heating circuit (not shown in the drawings).
  • the heating circuit is used for heating the memory chip 100 .
  • the control chip 120 determines whether the temperature of the memory chip 100 detected by the temperature detection unit 111 reaches the set threshold, and if it does not reach the set threshold, Then, the heating circuit is controlled to heat the memory chip 100 , and if the set threshold is reached, the heating circuit is controlled to stop heating the memory chip 100 .
  • precise control of the heating process is achieved, so that the temperature of the memory chip 100 can be kept near the set threshold, preventing the temperature of the memory chip 100 from being too high or too low, so that the writing time to the memory can always be kept short.

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Abstract

一种半导体装置，其包括存储芯片（100）及温度检测模块（110），所述温度检测模块（110）用于检测所述存储芯片（100）的温度，所述温度检测模块（110）包括：温度检测单元（111），用于检测所述存储芯片（100）的温度，并输出与所述温度对应的模拟信号；A/D转换模块（112），包括多个比较单元（Px），所述比较单元（Px）包括输入端、参考端和输出端，所述输入端接收所述温度检测单元（111）输出的模拟信号，所述输出端输出数字信号，多个所述比较单元（Px）参考端所接收的参考电压非均匀的增加。利用温度检测模块（110）检测存储芯片（100）温度，避免存储芯片（100）在低温下启动及运行，缩短写入时间，提高存储芯片（100）写入稳定性；同时，控制不同电压区域测量精度，从而既能够保证需要精确测量区域的测量精度，又能够提高测量效率。

Description

半导体装置
相关申请引用说明
本申请要求于2020年06月30日递交的中国专利申请号202010612720.9，申请名为“半导体装置”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及存储器领域，尤其涉及一种半导体装置。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
温度对存储器写入存在较大影响，在低温环境中，对存储器进行写入时，存在写入时间较长，写入的稳定性不高的问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体装置，其能够测量存储芯片的温度，避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性；同时既能够保证需要精确测量区域的测量精度，又能够提高测量效率。
为了解决上述问题，本发明提供了一种半导体装置，其特征在于，包括存储芯片及温度检测模块，所述温度检测模块用于检测所述存储芯片的温度，所述温度检测模块包括：温度检测单元，用于检测所述存储芯片的温度，并输出与所述温度对应的模拟信号；A/D转换模块，包括多个比较单元，所述比较单元包括输入端、参考端和输出端，所述输入端接收所述温度检测单元输出的模拟信号，所述输出端输出数字信号，多个所述比较单元参考端所接收的参考电压非均匀的增加。
进一步，在预设的参考电压范围内，所述参考电压的增幅小于其他参考电压范围内的参考电压的增幅。
进一步，所述温度检测模块检测的温度达到设定阈值时，所述存储芯片启动。
进一步，所述设定阈值对应阈值电压，所述阈值电压位于预设的所述参考电压范围内。
进一步，所述A/D转换模块还包括电阻单元，所述电阻单元具有多个引出端，多个所述引出端的电压非均匀的增加，所述引出端的电压作为所述比较单元参考端所接收的参考电压。
进一步，所述电阻单元具有第一端及第二端，所述电阻单元的第一端与电源电连接，所述电阻单元的第二端与接地端电连接，所述引出端设置在所述第一端与所述第二端之间。
进一步，所述电阻单元包括多个串联连接的子电阻，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量不同，以使每一引出端的电压不同。
进一步，在所述电阻单元中，相邻的所述引出端之间间隔的子电阻的数量包括相同及不同两种状态，以使得多个所述比较单元参考端所接收的参考电压非均匀的增加。
进一步，在预设的所述参考电压对应的电阻单元区域，相邻的所述引出端之间间隔的子电阻的数量小于其他区域相邻的所述引出端之间间隔的子电阻的数量。
进一步，所述子电阻的电阻值相同。
进一步，所述子电阻为多晶硅电阻，所述子电阻之间通过第一层金属线电连接。
进一步，所述电阻单元通过第二层金属线形成所述引出端。
进一步，所述A/D转换模块还包括编码单元，所述编码单元接收所述比较单元的数字信号，并进行编码。
进一步，所述A/D转换模块还包括输出单元，所述输出单元与所述比较单元连接，用于将所述数字信号输出。
进一步，所述温度检测单元包括：定值电阻，具有第一端及第二端，所述第一端与电源电连接；二极管，与所述定值电阻串联，所述二极管的正端与所 述定值电阻的第二端电连接，所述二极管的负端与接地端电连接。
进一步，所述温度检测单元还包括可调电阻，所述可调电阻与所述二极管并联。
进一步，所述温度检测单元设置在所述存储芯片中。
进一步，所述温度检测单元与所述存储芯片共用同一接地端。
进一步，所述温度检测单元与所述存储芯片采用不同的电源供电。
进一步，所述温度检测单元的供电早于所述存储芯片的供电。
进一步，所述半导体装置还包括控制芯片，所述存储芯片及所述温度检测单元与所述控制芯片电连接。
进一步，所述控制芯片用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
本发明的优点在于，利用温度检测模块检测存储芯片的温度，当所述温度检测模块检测的温度达到设定阈值时，所述存储芯片启动，温度检测模块检测的温度为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性；同时，通过多个所述比较单元参考端所接收的参考电压非均匀的增加来控制不同电压区域的测量精度，从而既能够保证需要精确测量区域的测量精度，又能够节省电路，提高测量效率。
附图说明
图1是本发明半导体装置的第一实施例的结构示意图；
图2是本发明半导体装置的温度检测模块的电路图；
图3是本发明半导体装置的第一实施例的电阻单元的电路图；
图4是本发明半导体装置另一实施例的电阻单元的电路图；
图5是本发明半导体装置第二实施例的结构示意图；
图6是本发明半导体装置第三实施例的结构示意图；
图7是本发明半导体装置第四实施例的结构示意图；
图8是本发明半导体装置第一实施例的电连接示意图。
具体实施方式
下面结合附图对本发明提供的半导体装置的实施例做详细说明。
如背景技术所言，温度对存储器写入存在较大影响，在低温环境中，对存储器进行写入时，存在写入时间较长，写入的稳定性不高的问题。
研究发现，现有的存储器工作在低温环境中时，由于温度下降会使得存储器中的位线、字线、以及金属连线(金属接触部)等的电阻会增大，电阻的增大，会使得向存储器中写入数据时的时间会变化或加长，影响了存储器写入的稳定性。
因此，本发明提供一种半导体装置，其采用温度检测模块检测所述存储芯片的温度，以为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性。同时，本发明半导体装置还能够提高温度测量的精确度。
图1是本发明半导体装置的第一实施例的结构示意图，图2是本发明半导体装置中温度检测模块的电路图，请参阅图1及图2，本发明半导体装置包括存储芯片100及温度检测模块110。
所述半导体装置还包括控制芯片120，所述存储芯片100及所述温度检测模块110与所述控制芯片120电连接。所述控制芯片120用于控制所述存储芯片100及所述温度检测模块110的启动及运行。所述存储芯片100的启动包括上电以及自检测，所述存储芯片100的运行可以包括向存储芯片100中写入数据，从存储芯片100读取数据，以及将存储芯片100中存取的数据删除等。
所述存储芯片100为现有能进行数据写入、数据读取和/或数据删除的存储器，所述存储芯片100通过半导体集成制作工艺形成。具体的说，所述存储芯片100可以包括存储阵列和与存储阵列连接的外围电路，所述存储阵列包括多个存储单元和与存储单元连接的位线、字线、以及金属连线(金属接触部)，所述存储单元用于存储数据，所述外围电路为在对存储阵列进行操作时的相关电路。本实施例中，所述存储芯片100为DRAM存储芯片，所述DRAM存储芯片中包括多个存储单元，所述存储单元通常包括电容器和晶体管，所述晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连。在其他实施例中所述存储芯片100可以为其他类型的存储芯片。
所述温度检测模块110用于检测所述存储芯片100的温度，并将信号提供 给控制芯片120。当所述温度检测模块110检测的温度达到设定阈值时，所述控制芯片120控制所述存储芯片100启动。其中，设定阈值的具体大小可以根据实际需要或者经验进行设定。
其中，所述温度检测模块110包括温度检测单元111及A/D转换模块112。
所述温度检测单元111用于检测所述存储芯片100的温度，并输出与所述温度对应的模拟电压信号。所述A/D转换模块112用于将所述温度检测单元111输出的模拟电压信号转换为数字信号，该数字信号作为所述存储芯片100是否启动的参考信号提供给控制芯片120。
所述A/D转换模块112包括多个比较单元Px，所述比较单元Px包括输入端、参考端和输出端。所述输入端接收所述温度检测单元111输出的模拟电压信号，所述参考端接收一参考电压信号，所述输出端输出数字信号。所述输入端的模拟电压信号与所述参考端的参考电压信号进行比较，所述输出端输出比较结果，该比较结果为所述数字信号。
其中，多个所述比较单元Px参考端所接收的参考电压非均匀的增加，使得在不同的电压区域，所述参考电压的增幅不同，进而能够改变该电压区域的测量精度。
进一步，在预设的参考电压范围内，所述参考电压的增幅小于其他参考电压范围内的参考电压的增幅。具体地说，对需要精确测量的电压区域，可采用小的参考电压增幅，以提高该区域的测量精度，对不需要精确测量的电压区域，可采用大的参考电压增幅，以提高测量效率。
例如，需要精确测量的电压区域为1.2V～1.7V，其对应的参考电压范围即为1.2V～1.7V，则1.2V～1.7V电压区域的参考电压的增幅可设置为0.1V，增加取样点数量，提高测量精度，而电压小于1.2V及大于1.7V的电压区域的参考电压的增幅可设置为0.3V，适当减少取样点数量，提高测量效率，同时也减少了所用的电路。
再例如，为了进一步提高测量精度，可再将1.2V～1.7V电压区域划分为更小的区域，例如1.2V～1.3V为第一电压区域，1.3V～1.5V为第二电压区域，1.5V～1.7V为第三电压区域，则第一电压区域与第三电压区域可采用相同的参考电压增幅，例如为0.1V，而第二电压区域可采用更小的电压增幅，例如0.05V。
其中，预设的参考电压范围的选取可根据存储芯片100的启动温度确定，以能够精确地检测到所述启动温度。具体地说，当所述温度检测模块110检测到存储芯片100的温度达到设定阈值时，所述控制芯片120控制所述存储芯片100启动，该设定阈值即为所述存储芯片100的启动温度。为了使所述温度检测模块110能够精确地检测到所述设定阈值，则需要提高与所述设定阈值对应的阈值电压所处的电压区域的测量精度，精确地检测到所述阈值电压，从而能够精确地确定存储芯片的启动温度。因此，将设定阈值对应的阈值电压所处的电压区域设置为预设的参考电压范围，在预设的参考电压范围内，所述参考电压的增幅小于其他参考电压范围内的参考电压的增幅。
本发明半导体装置通过多个所述比较单元参考端所接收的参考电压非均匀的增加来控制不同电压区域的测量精度，从而既能够保证需要精确测量区域的测量精度，又能够提高测量效率。
进一步，本发明提供一种能够使多个所述比较单元参考端所接收的参考电压非均匀增加的结构。
请参阅图2，所述A/D转换模块112还包括电阻单元1121。所述电阻单元1121具有第一端及第二端。所述电阻单元1121的第一端与电源电连接。所述电阻单元1121可与所述温度检测单元111采用同一电源，也可采用不同电源。例如，若所述A/D转换模块112设置在存储芯片100中，则所述电阻单元1121的第一端可与所述温度检测单元111采用同一电源Vtemp；若所述A/D转换模块112设置在控制芯片120中，则所述电阻单元1121的第一端可与所述温度检测单元111采用不同的电源，所述电阻单元可采用电源VDD。所述电阻单元的第二端与接地端VSS电连接。
其中，所述电阻单元1121具有多个引出端Ax，每一引出端Ax的电压不同，多个所述引出端Ax的电压非均匀的增加。每一所述引出端Ax与比较单元Px的参考端电连接，每一所述引出端Ax的电压作为所述比较单元Px的参考端的参考电压。所述引出端Ax与所述比较单元Px一一对应。
在本实施例中，所述电阻单元包括多个串联连接的子电阻Rn。所述子电阻Rn的阻值可相同。请参阅图3，其为本第一实施例的电阻单元的电路图，在该实施例中，所述子电阻Rn的阻值相同，以简化版图布局难度，简单易行， 便于制造。其中，在所述电阻单元中，相邻的所述引出端Ax之间间隔的子电阻Rx的数量包括相同及不同两种状态，以使得多个所述比较单元Px参考端所接收的参考电压非均匀的增加。具体地说，对测量精度要求不同的区域，其相邻的所述引出端Ax之间间隔的子电阻Rx的数量不同，对于测量精度要求相同的区域，相邻的所述引出端Ax之间间隔的子电阻Rx的数量相同。
例如，在本实施例中，在预设的所述参考电压对应的电阻单元区域，相邻的所述引出端之间间隔的子电阻的数量相同，但小于其他区域相邻的所述引出端之间间隔的子电阻的数量，以提高预设的所述参考电压对应的电阻单元区域的取样数量，进而提高该区域测量精度。
具体地说，请参阅图3，所述电阻单元包括串联连接的子电阻R1～R23在与电阻单元的第二端VSS间隔三个子电阻R1、R2及R3处形成引出端A1，在与引出端A1间隔三个子电阻R4、R5及R6处形成引出端A2，在与引出端A2间隔三个子电阻R7、R8及R9处形成引出端A3，引出端A1、引出端A2及引出端A3之间间隔的子电阻的数量相同，均为3个；在与引出端A3间隔三个子电阻R10及R11处形成引出端A4，在与引出端A4间隔三个子电阻R12及R13处形成引出端A5，在与引出端A5间隔三个子电阻R14及R15处形成引出端A6，在与引出端A6间隔三个子电阻R16及R17处形成引出端A7，引出端A3、引出端A4、引出端A5、引出端A6及引出端A7之间间隔的子电阻的数量相同，均为2个；在与引出端A7间隔三个子电阻R18、R19及R20处形成引出端A8，在与引出端A8间隔三个子电阻R21、R22及R23处形成引出端A9，引出端A7、引出端A8及引出端A9之间间隔的子电阻的数量相同，均为3个。在该实施例中，引出端A3～A7输出的电压所形成的范围为预设的参考电压范围，其电压增幅减小，提高测量精度。
进一步，在本发明另一实施例中，在引出端A3～A7之间增加引出端，进一步增加取样数量，提高测量精度。具体地说，请参阅图4，其为另一实施例的电阻单元的电路图，在引出端A3及A4之间增加引出端A31，所述引出端A31与所述引出端A3及A4之间均间隔一个子电阻；在引出端A4及A5之间增加引出端A41，所述引出端A41与所述引出端A4及A5之间均间隔一个子电阻；在引出端A5及A6之间增加引出端A51，所述引出端A51与所述引出 端A5及A6之间均间隔一个子电阻；在引出端A6及A7之间增加引出端A61，所述引出端A61与所述引出端A6及A7之间均间隔一个子电阻。
进一步，所述子电阻Rx为多晶硅电阻，所述子电阻之间通过第一层金属线电连接。所述电阻单元通过第二层金属线形成所述引出端Ax。这种方式能够进一步易于制造，提高稳定性和测量精确性。
上述仅为本发明提供一种能够使多个所述比较单元参考端所接收的参考电压非均匀增加的结构的实施例，在本发明其他实施例中，也可采用其他能够实现该功能的结构。
进一步，所述A/D转换模块112还包括输出单元1120，所述输出单元1120与所述比较单元Px连接，用于将所述数字信号输出。进一步，在本实施例中，所述A/D转换模块112还包括编码单元EEC，所述编码单元EEC接收所述比较单元Px输出的数字信号，并进行编码，其形成的信号输入所述输出单元1120，所述输出单元1120将编码后的数字信号输出。
所述半导体装置包括一个或者多个存储芯片100，所述温度检测模块110包括一个或者多个温度检测单元111。所述温度检测单元111可用于检测一个或者多个存储芯片100的温度。其中，所述温度检测单元111与所述存储芯片100可为一对一关系，或者一对多关系。
当所述存储芯片100的个数为一个，所述温度检测单元111的个数也为一个时，所述温度检测单元111与所述存储芯片100为一对一关系，所述温度检测单元111仅用于检测该存储芯片100的温度。
当所述存储芯片100的个数为多个，所述温度检测单元111的个数为一个时，所述温度检测单元111与所述存储芯片100为一对多关系，所述温度检测单元111用于检测多个所述存储芯片100的温度。
当所述存储芯片100的个数为多个，所述温度检测单元111的个数也为多个，但所述温度检测单元111的个数小于所述存储芯片100的个数时，所述温度检测单元111与所述存储芯片100可能同时存在一对一关系及一对多关系，或者仅存在一对多关系。即可能存在一个所述温度检测单元111仅检测一个存储芯片100的温度和一个温度检测单元100检测多个所述存储芯片100的温度的情况，或者仅存在一个温度检测单元100检测多个所述存储芯片100的温度 的情况。
当所述存储芯片100的个数为多个，所述温度检测单元111的个数也为多个，且所述温度检测单元100的个数与所述存储芯片100的个数相同时，所述温度检测单元111与所述存储芯片100为一对一关系，一个所述温度检测单元111用于检测一个所述存储芯片100的温度。具体地说，在本实施例中，所述存储芯片100的个数为多个，所述温度检测单元111的个数也为多个，如图1所示，在图1中示意性地绘示四个存储芯片100及四个温度检测单元111，多个所述存储芯片100堆叠设置，所述温度检测单元111与所述存储芯片100一一对应。
进一步，请继续参阅图2，在本实施例中，所述温度检测单元111包括定值电阻Ra及二极管D。所述定值电阻Ra具有第一端及第二端，所述第一端与电源Vtemp电连接。所述二极管D与所述定值电阻Ra串联，所述二极管D的正端与所述定值电阻Ra的第二端连接，所述二极管D的负端与接地端VSS电连接。所述二极管D对温度敏感，随着其周围环境温度的变化，其电流发生变化，进而能够用于测量周围环境的温度。
进一步，在本实施例中，所述温度检测单元111还包括可调电阻Rb，所述可调电阻Rb与所述二极管D并联，用于校准所述二极管D。所述可调电阻Rb的电阻值可变化，例如，通过控制芯片120的控制而改变所述可调电阻Rb的电阻值，从而能够实现对二极管D的校准。
进一步，所述温度检测单元111可通过半导体集成制作工艺形成在存储芯片100中。若所述温度检测单元111仅用于检测一个存储芯片100的温度，则其可形成在该存储芯片100中，例如，在本实施例中，如图1所示，温度检测单元111与存储芯片100一一对应，在每一存储芯片100中均设置一个温度检测单元111。若所述温度检测单元111用于检测多个存储芯片100的温度时，其可形成在该多个存储芯片100中的任意一个存储芯片100内，或者形成在居中的或最底层的存储芯片100内。例如，在本发明第二实施例中，请参阅图5，其为本发明半导体装置第二实施例的结构示意图，温度检测单元111设置在最底层的存储芯片100内，其能够测量四个存储芯片100的温度。
在本发明另一实施例中，所述温度检测单元111并未设置在存储芯片100 中，而是设置在控制芯片120中。具体地说，请参阅图6，其为本发明半导体装置第三实施例的结构示意图，温度检测单元111设置在控制芯片120内，其能够测量堆叠设置在控制芯片120上的四个存储芯片100的温度。
在本发明另一实施例中，请参阅图7，其为本发明半导体装置第四实施例的结构示意图，所述半导体装置还包括线路基板130，所述线路基板130中具有连接线路(附图中未绘示)，所述存储芯片100以及控制芯片120均位于所述线路基板130上，所述存储芯片100和控制芯片120通过所述线路基板130中的所述连接线路电连接。在该实施例中，所述温度检测单元111也设置在所述线路基板130上，以测量环境温度，该环境温度与存储芯片100温度接近，其可近似作为存储芯片100的温度。其中，所述线路基板130包括但不限于PCB电路板。可以理解的是，在本发明其他实施例中，所述温度检测单元111也可不设置在所述线路基板130上，而是如图1、图5及图6所示，设置在存储芯片100中或者控制芯片120中。
需要注意的是，本发明实施例中控制芯片120在控制存储芯片100启动等方面的功能，也可通过在存储芯片100设置控制电路来实现，此时，可无需控制芯片120的存在，本领域内技术人员应当理解，可根据需要自行设置。
进一步，所述温度检测单元111与所述存储芯片100采用不同的电源供电。图8是本发明半导体装置的第一实施例的电连接示意图，请参阅图8，所述温度检测单元111采用电源Vtemp供电，所述存储芯片100采用VDD供电。其中，所述接地端VSS、电源VDD及电源Vtemp由所述控制芯片120提供。由于所述温度检测单元111与所述存储芯片100采用不同的电源供电，因此，可独立地控制所述温度检测单元111及所述存储单元100的供电，从而实现所述温度检测单元111与所述存储芯片100的不同时启动。
因此，本发明可分别控制所述温度检测单元111与所述存储芯片100的启动，即温度检测单元111的启动不受存储芯片100是否启动的影响，使得对存储芯片100温度的检测不受存储芯片100是否启动的影响，从而能够为存储芯片100的启动及运行提供参考，进而能够避免存储芯片100在低温下启动或者运行，提高存储芯片100的稳定性。
如前所述，温度对存储芯片100的性能有很大影响，特别是在存储芯片100 启动时。若存储芯片100在低温下启动，会使向存储芯片100中写入数据的时间变化(如加长)，影响了存储芯片100写入的稳定性，则在存储芯片100启动之前需要测量存储芯片的温度，以使存储芯片100能够在合适的温度内启动。
因此，本发明所述温度检测单元111的供电早于所述存储芯片100的供电，即在所述存储芯片100启动之前，所述温度检测单元111已经启动，从而可获得存储芯片100启动之前的温度，为存储芯片100的启动提供参考。所述温度检测单元111与所述存储芯片100的供电时间差取决于所述存储芯片100的温度变化速率，若所述存储芯片100的温度变化速率大，所述存储芯片100达到预设温度的时间短，则所述温度检测单元111与所述存储芯片100的供电时间差小，若所述存储芯片100的温度变化速率小，所述存储芯片100达到预设温度的时间长，则所述温度检测单元111与所述存储芯片100的供电时间差大。
进一步，请参阅图8，所述温度检测单元111与所述存储芯片100共用同一接地端VSS。其优点在于，一方面不会增加存储芯片100未启动阶段的泄露电流，另一方面，会减少引脚的数目，节省空间。
请继续参阅图1，多个存储芯片100堆叠设置在所述控制芯片120上，所述控制芯片120与堆叠结构中最底层的存储芯片100键合在一起。而在本发明另一实施例中，当只有一个存储芯片100时，所述存储芯片100设置在控制芯片120上，所述控制芯片120与该存储芯片100键合在一起。
所述存储芯片100中形成有硅通孔互连结构101，通过硅通孔互连结构101将存储芯片100与控制芯片120进行电连接，将温度检测单元111与控制芯片120电连接。即通过硅通孔互连结构101将存储芯片100与接地端VSS及电源VDD电连接，将温度检测单元111与电源Vtemp及接地端VSS电连接。具体地说，在本实施例中，多个存储芯片100堆叠设置时，每一个存储芯片100可以通过不同的硅通孔互连结构与控制芯片120连接；当具有多个温度检测单元111时，可能存在每一个温度检测单元111通过不同的硅通孔互连结构与控制芯片120连接的情况，也可能存在多个温度检测单元111共用硅通孔互连结构与控制芯片120连接的情况。可以理解的是，所述存储芯片100与所述温度检测单元111通过不同的硅通孔互连结构与控制芯片120连接，以使所述温度检测单元111及所述存储芯片100能够采用不同的电源供电。进一步，多个所述 温度检测单元111的供电也可共用工艺硅通孔互连结构。
在其他实施例中，所述存储芯片100及所述温度检测单元还可以通过金属引线(通过引线键合工艺形成)与所述控制芯片120电连接。
当存储芯片100处于低温环境中，若对其进行加热，则能够迅速提高存储芯片100的温度，从而加快存储芯片100的启动。因此，本发明所述控制芯片120还能够在存储芯片100启动之前先进行启动，控制芯片120利用启动后自身产生的热量对存储芯片100进行加热，以快速提高存储芯片100的温度。
在所述控制芯片120启动后，所述控制芯片120控制所述温度检测单元111启动，以检测所述存储芯片100的温度。所述温度检测单元111还能够将检测的温度传送给控制芯片120，以作为控制芯片120的数据。
所述控制芯片120能够判断所述温度检测单元111检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片100启动。
若仅有一个温度检测单元111及一个存储芯片100，一个所述温度检测单元111仅用于检测一个存储芯片的温度时，当控制单元120判定该温度检测单元111检测的温度达到设定阈值，则所述控制芯片120控制该存储芯片100启动。
若存在一个温度检测单元111及多个存储芯片100，且一个所述温度检测单元111检测多个存储芯片100的温度，当控制单元120判定该温度检测单元111检测的温度达到设定阈值，则控制单元120先控制离所述控制芯片120最近的存储芯片100启动，然后再控制上面的其他存储芯片100依次启动。
若存在多个温度检测单元111及多个存储芯片100，且可能存在一个所述温度检测单元111仅检测一个存储芯片100的温度和一个温度检测单元111检测多个所述存储芯片100的温度的情况，或者仅存在一个温度检测单元111检测多个所述存储芯片100的温度的情况，当控制单元120判断某一个温度检测单元111检测的温度达到设定阈值，则控制该温度检测单元111对应的存储芯片100启动，若该温度检测单元111检测多个存储芯片100的温度，则先控制离所述控制芯片120最近的存储芯片100启动，然后再控制上面的其他存储芯片100依次启动。
若存在多个温度检测单元111及多个存储芯片100，且所述温度检测单元 111与所述存储芯片100一一对应，当控制单元110判断某一个温度检测单元111检测的温度达到设定阈值，则控制该温度检测单元111对应的存储芯片100启动。具体地说，如图1所示的堆叠结构中有4个存储芯片100，每一个存储芯片100中对应具有一个温度检测单元111，因而每一个温度检测单元111会对对应的存储芯片100的温度进行检测，获得四个温度检测值，所述控制芯片120会依次判断4个所述温度检测单元111检测的温度是否达到设定阈值时，若某一个温度检测单元111检测的温度达到设定阈值，则控制该温度检测单元111对应的存储芯片启动，比如堆叠结构中最底层的存储芯片100中的温度检测单元111检测的温度先达到设定阈值时，则控制芯片120先控制所述堆叠结构最底层的那一个存储芯片100启动，接着，堆叠结构中倒数第二层中那个存储芯片100中对应的温度检测单元111检测的温度也达到设定阈值时，则控制单元301接着控制堆叠结构中倒数第二层的那个存储芯片100启动，上面两层的存储芯片100的启动以此类推。
对于半导体装置存在多个存储芯片100时，前述的这种控制结构和控制方式能使得每一个存储芯片100启动时机的精度进一步提高，并能进一步减小低温环境下的对每一个存储芯片100进行数据写入时的写入时间，进一步提高了对每一个存储芯片100写入的稳定性。
当本发明半导体装置工作在低温环境时，通过控制芯片120可以使得存储芯片100升温到设定阈值，从而可以防止存储芯片100中的位线、字线、以及金属连线(金属接触部)由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储芯片进行数据写入时的写入时间，提高了存储芯片写入的稳定性。所述设定阈值可以设定在控制芯片120中，设定阈值的具体大小可以根据实际需要或者经验进行设定。
在另一实施例中，所述控制芯片120中可以具有额外的加热电路(附图中未绘示)。所述加热电路用于对所述存储芯片100进行加热。所述控制芯片120在对所述存储芯片100进行加热之前或之后，所述控制芯片120判断所述温度检测单元111检测的存储芯片100的温度是否达到设定阈值，若未达到设定阈值，则控制所述加热电路对存储芯片100进行加热，如达到设定阈值，则控制所述加热电路停止对存储芯片100进行加热。从而实现对加热过程的精确控制， 使得存储芯片100的温度能保持在设定阈值附近，防止存储芯片100的温度过高或过低，从而使得对存储器的写入时间始终能保持较短。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (22)

  1. 一种半导体装置，其特征在于，包括存储芯片及温度检测模块，所述温度检测模块用于检测所述存储芯片的温度，所述温度检测模块包括：
    温度检测单元，用于检测所述存储芯片的温度，并输出与所述温度对应的模拟信号；
    A/D转换模块，包括多个比较单元，所述比较单元包括输入端、参考端和输出端，所述输入端接收所述温度检测单元输出的模拟信号，所述输出端输出数字信号，多个所述比较单元参考端所接收的参考电压非均匀的增加。
  2. 根据权利要求1所述的半导体装置，其特征在于，在预设的参考电压范围内，所述参考电压的增幅小于其他参考电压范围内的参考电压的增幅。
  3. 根据权利要求2所述的半导体装置，其特征在于，当所述温度检测模块检测的温度达到设定阈值时，所述存储芯片启动。
  4. 根据权利要求3所述的半导体装置，其特征在于，所述设定阈值对应阈值电压，所述阈值电压位于预设的所述参考电压范围内。
  5. 根据权利要求2所述的半导体装置，其特征在于，所述A/D转换模块还包括电阻单元，所述电阻单元具有多个引出端，多个所述引出端的电压非均匀的增加，所述引出端的电压作为所述比较单元参考端所接收的参考电压。
  6. 根据权利要求5所述的半导体装置，其特征在于，所述电阻单元具有第一端及第二端，所述电阻单元的第一端与电源电连接，所述电阻单元的第二端与接地端电连接，所述引出端设置在所述第一端与所述第二端之间。
  7. 根据权利要求6所述的半导体装置，其特征在于，所述电阻单元包括多个串联连接的子电阻，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量不同，以使每一引出端的电压不同。
  8. 根据权利要求7所述的半导体装置，其特征在于，在所述电阻单元中，相邻的所述引出端之间间隔的子电阻的数量包括相同及不同两种状态，以使得多个所述比较单元参考端所接收的参考电压非均匀的增加。
  9. 根据权利要求8所述的半导体装置，其特征在于，在预设的所述参考电压对应的电阻单元区域，相邻的所述引出端之间间隔的子电阻的数量小于其他区域相邻的所述引出端之间间隔的子电阻的数量。
  10. 根据权利要求7所述的半导体装置，其特征在于，所述子电阻的电阻值相同。
  11. 根据权利要求7所述的半导体装置，其特征在于，所述子电阻为多晶硅电阻，所述子电阻之间通过第一层金属线电连接。
  12. 根据权利要求11所述的半导体装置，其特征在于，所述电阻单元通过第二层金属线形成所述引出端。
  13. 根据权利要求5所述的半导体装置，其特征在于，所述A/D转换模块还包括编码单元，所述编码单元接收所述比较单元的数字信号，并进行编码。
  14. 根据权利要求5所述的半导体装置，其特征在于，所述A/D转换模块还包括输出单元，所述输出单元与所述比较单元连接，用于将所述数字信号输出。
  15. 根据权利要求1所述的半导体装置，其特征在于，所述温度检测单元包括：
    定值电阻，具有第一端及第二端，所述第一端与电源电连接；
    二极管，与所述定值电阻串联，所述二极管的正端与所述定值电阻的第二端电连接，所述二极管的负端与接地端电连接。
  16. 根据权利要求15所述的半导体装置，其特征在于，所述温度检测单元还包括可调电阻，所述可调电阻与所述二极管并联。
  17. 根据权利要求1所述的半导体装置，其特征在于，所述温度检测单元设置在所述存储芯片中。
  18. 根据权利要求17所述的半导体装置，其特征在于，所述温度检测单元与所述存储芯片共用同一接地端。
  19. 根据权利要求17所述的半导体装置，其特征在于，所述温度检测单元与所述存储芯片采用不同的电源供电。
  20. 根据权利要求19所述的半导体装置，其特征在于，所述温度检测单元的供电早于所述存储芯片的供电。
  21. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置还包括控制芯片，所述存储芯片及所述温度检测单元与所述控制芯片电连接。
  22. 根据权利要求21所述的半导体装置，其特征在于，所述控制芯片用于在存 储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
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