Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/124—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed the encapsulations having cavities other than that occupied by chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/04—Manufacture or treatment of leadframes
  • H10W70/041—Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/40—Leadframes
  • H10W70/411—Chip-supporting parts, e.g. die pads
  • H10W70/417—Bonding materials between chips and die pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/40—Leadframes
  • H10W70/464—Additional interconnections in combination with leadframes
  • H10W70/465—Bumps or wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
  • H10W74/016—Manufacture or treatment using moulds
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/811—Multiple chips on leadframes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
  • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/66—Conductive materials thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/221—Structures or relative sizes
  • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/853—On the same surface
  • H10W72/859—Bump connectors and bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/884—Die-attach connectors and bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

• semiconductor chips also commonly referred to as “dies”
• die pads of lead frames are wire-bonded, clipped, or otherwise coupled to leads of the lead frame.
• Other devices may similarly be mounted on the die pad or on another lead frame pad.
• the assembly is later covered by a mold compound, such as epoxy, to protect the assembly from potentially damaging heat, physical trauma, moisture, and other deleterious factors.
• the finished assembly is called a semiconductor package or, more simply, a package.
• the conductive terminals e.g., leads
• a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die.
• the semiconductor package has a surface and a cavity formed in the surface.
• the device also comprises an electronic device positioned within the cavity. The electronic device couples to the semiconductor die via a conductive terminal extending through the mold compound.
• a method comprises coupling an inactive surface of a semiconductor die to a die pad.
• the method includes forming a redistribution layer (RDL) on an active surface of the semiconductor die.
• the method comprises coupling an electronic device to a conductive terminal, the conductive terminal coupled to the RDL.
• the method comprises covering the die pad, the semiconductor die, and the RDL with a mold compound such that the electronic device is positioned in a cavity formed in a surface of the mold compound.
• the RDL is positioned between the surface and the semiconductor die.
• FIGs. 1A, 2A, 3A, and 4A are profile, cross-sectional views of various semiconductor packages having cavities to store electronic devices, in various examples.
• FIGs. IB, 2B, 3B, and 4B are top-down views of semiconductor packages having cavities to store electronic devices, in various examples.
• FIGs. 1C, 2C, 3C, and 4C are perspective views of semiconductor packages having cavities to store electronic devices, in various examples.
• FIG. ID shows a semiconductor package positioned on a printed circuit board, in various examples.
• FIGs. 5 A, 5D, and 5E are profile, cross-sectional views of semiconductor packages having cavities, each cavity storing multiple electronic devices, in various examples.
• FIG. 5B is a top-down view of a semiconductor package having a cavity storing multiple electronic devices, in various examples.
• FIG. 5C is a perspective view of a semiconductor package having a cavity storing multiple electronic devices, in various examples.
• FIG. 6A is a profile, cross-sectional view of a semiconductor package having a cavity storing another semiconductor package, in various examples.
• FIG. 6B is a top-down view of a semiconductor package having a cavity storing another semiconductor package, in various examples.
• FIG. 6C is a perspective view of a semiconductor package having a cavity storing another semiconductor package, in various examples.
• FIG. 7 is a flow diagram of a method for fabricating a semiconductor device comprising a semiconductor package having a cavity to store an electronic device, in various examples.
• FIGs. 8A-8F depict a process flow for fabricating a redistribution layer (RDL) in a semiconductor package having a cavity to store an electronic device, in various examples.
• RDL redistribution layer
• FIGs. 9A-9E2 depict a process flow for fabricating a redistribution layer (RDL) in a semiconductor package having a cavity to store an electronic device, in various examples.
• RDL redistribution layer
• FIGs. 10A-10G depict a process flow for fabricating a redistribution layer (RDL) in a semiconductor package having a cavity to store an electronic device, in various examples.
• RDL redistribution layer
• FIGs. 11A-11G depict a process flow for fabricating a redistribution layer (RDL) in a semiconductor package having a cavity to store an electronic device, in various examples.
• RDL redistribution layer
• FIGs. 12A-12C depict profile cross-sectional, top-down, and perspective views of a semiconductor package having a cavity to store a quad flat no lead (QFN) style semiconductor package, in various examples.
• QFN quad flat no lead
• the functionality of a semiconductor package is typically determined by the components housed within the package. In some cases, it is desirable to expand the functionality of a first semiconductor package without increasing the footprint of that semiconductor package. This can be accomplished by stacking other electronic devices, for example a second semiconductor package, on top of the first semiconductor package. Such stacking may include coupling the second semiconductor package on top of the first semiconductor package such that the conductive terminals (e.g., balls in a ball grid array (BGA) package) of the second semiconductor package extend through the mold compound that covers the first semiconductor package.
• BGA ball grid array
• the width of the first semiconductor package is reduced relative to the width of the second semiconductor package so that the conductive terminals (e.g., balls) of both the first and second semiconductor packages can reach the underlying printed circuit board (PCB).
• PCB printed circuit board
• the second semiconductor package is not positioned inside the first semiconductor package, the second semiconductor package is nonetheless said to expand the functionality of the first semiconductor package because it is stacked on top of the first semiconductor package and thus is considered to be part of the first semiconductor package.
• Such configurations can expand the functionality of a semiconductor package, they come with numerous disadvantages. For example, although stacking packages as described above avoids increasing the PCB space occupied, it still increases the volume of the combined package structure, particularly in the vertical direction.
• the stacked package configuration results in poor electrical properties due to the increase in distance that electrical signals travel, and it results in poor thermal properties because the top semiconductor package blocks and traps heat being radiated by the bottom semiconductor package.
• This description describes a semiconductor device that includes a semiconductor package and an electronic device (e.g., another semiconductor package, a passive component).
• the semiconductor package includes a mold compound that comprises a cavity formed in a top surface of the mold compound.
• the electronic device is positioned inside the cavity and electrically couples to circuitry inside the semiconductor package via one or more conductive terminals that extend into (or are exposed to) the cavity from within the semiconductor package.
• This semiconductor device presents numerous advantages over the stacked package configuration described above. For example, because the electronic device partially or entirely fits within the cavity of the semiconductor package, the volume of the resulting structure is the same as, or is not substantially greater than, the volume of the semiconductor package alone. In addition, the semiconductor device is inexpensive and efficient to manufacture.
• RDL redistribution layer
• the examples described herein are also advantageous over stacked die packages, in which multiple dies are covered by a common mold compound.
• the functionality provided by the package is limited to that provided by the dies that are already covered by the mold compound.
• the functionality of the completed package cannot be changed.
• the examples described in this description provide one or more dies within the package that can couple to any of a variety of electronic devices that are positioned outside of the package, e.g., in a cavity of the package.
• a user may purchase a package having the cavity and conductive terminals described herein and may have the flexibility to choose any suitable electronic device that he or she wishes to couple to the package.
• the user may choose, for example, to couple any suitable package, active component, passive component, etc. to the conductive terminals in the cavity.
• any suitable package, active component, passive component, etc. to the conductive terminals in the cavity.
• the user has greater flexibility to control the functionality of the resulting semiconductor device than he or she would have with a stacked die package, the functionality of which is predetermined.
• the semiconductor device is now described in relation to the drawings.
• FIGs. 1A, 2A, 3A, and 4A are profile, cross-sectional views of various semiconductor packages having cavities to store electronic devices, in various examples.
• FIG. 1A depicts an example semiconductor package 100 comprising a die pad 102, conductive terminals 104 (e.g., leads), and a semiconductor die 108 having an inactive surface coupled to the die pad 102 by way of a die attach layer 106.
• An RDL 110 is formed on an active surface of the semiconductor die 108.
• the RDL 110 includes, for example, various metals formed in a suitable pattern to enable communications between the active surface of the semiconductor die 108 and other components.
• the conductive contacts of these patterned metals are defined by dielectrics such as polyimide and/or polybenzoxazole, meaning that the areas of the patterned metals abutting dielectric material do not conduct to other metals, and areas of the patterned metals not abutting dielectric material may conduct to other metals.
• dielectrics such as polyimide and/or polybenzoxazole
• this description describes the dielectrics (e.g., polyimide, polybenzoxazole) as being part of the RDLs described herein because the dielectrics define the conductive contacts of the patterned metals.
• the active surface of the semiconductor die 108 couples to the conductive terminals 104, as shown.
• conductive terminals 116 couple to the active surface of the semiconductor die 108.
• the conductive terminals 116 extend from the RDL 110, through a mold compound 112, and into a cavity 114. In other examples, the conductive terminals 116 do not extend into the cavity 114 but are exposed to the cavity 114, meaning that the distal ends of the conductive terminals 116 are not covered by the mold compound 112 and thus are accessible from within the cavity 114.
• the distal ends of the conductive terminals 116 may be flush with a bottom surface 115 of the cavity 114 or may be positioned lower than the bottom surface 115.
• the cavity 114 and the conductive terminals 116 are positioned in a central location of the semiconductor package 100 (e.g., between the bond wires 126), because positioning the conductive terminals 116 to the left or to the right relative to their positions in FIG. 1 A would result in the accommodation of fewer bond wires 126.
• the bond wire 126 shown on the left side of the semiconductor package 100 would have to be omitted, thereby reducing the input and output signaling capabilities of the semiconductor package 100.
• the centralized location of the cavity 114 and the conductive terminals 116 facilitates a high conductive terminal (e.g., lead or pin) count.
• the outer perimeter of the cavity 114 is spaced at least 50 microns away from adjacent bond pads on the RDL 110 to which the bond wires 126 couple.
• the mold compound 112 covers the various structures shown in FIG. 1A, such as the die pad 102, the conductive terminals 104, the die attach layer 106, the semiconductor die 108, the RDL 110, and the bond wires 126.
• the cavity 114 is formed in a top surface 113 of the mold compound 112.
• the cavity 114 may have any suitable shape and size.
• the bottom surface 115 has a sufficiently large area to accommodate one or more electronic devices, for example, other packages (e.g., ball grid array (BGA) packages, dual in-line packages (DIP), quad flat no-lead (QFN) packages, wafer chip scale packages (WCSP), etc.), passive components (e.g., capacitors, resistors, inductors, transformers), active components (e.g., transistors, amplifiers), etc.
• BGA ball grid array
• DIP dual in-line packages
• QFN quad flat no-lead
• WCSP wafer chip scale packages
• passive components e.g., capacitors, resistors, inductors, transformers
• active components e.g., transistors, amplifiers
• any suitable electronic device may be positioned in the cavity 114 and coupled to the conductive terminals 116 to establish power and/or data communication with the semiconductor die 108 via the RDL 110.
• the length of the surface 115 ranges from 0.1 mm to 20 mm
• the width of the surface 115 ranges from 0.1 mm to 20 mm.
• a depth of the cavity 114, as measured from the surface 115 to the horizontal plane of the surface 113, ranges from 0.05 mm to 2 mm.
• the length and/or width of the surface 115 has a limit equivalent to the corresponding length and/or width of the surface 113 minus the sum of 1) 200 microns and 2) the product of 2 * sin(x) * a depth of the cavity 114, where x is the angle between the wall 117 and a vertical plane extending through the wall 117.
• This limit may protect the integrity of the mold compound 112 at a periphery of the semiconductor package 100, while an excessively large cavity that thins the mold compound 112 near the periphery of the semiconductor package 100 may cause the mold compound 112 to crumble.
• the cavity 114 is sufficiently large so that an electronic device positioned inside the cavity 114 and coupled to the conductive terminals 116 fits entirely within the cavity 114, e.g., the electronic device does not extend beyond the horizontal plane of the surface 113.
• the various possible dimensions of the cavity 114 are not mere design choices, but rather have specific advantages and disadvantages associated therewith.
• larger cavities 114 may accommodate additional electronic devices, but associated drawbacks include increased costs and longer manufacturing time, as well as larger package sizes that result in coefficient of thermal expansion (CTE) mismatch problems and problems with alignment between the package and a printed circuit board on which the package is mounted (commonly referred to as coplanarity problems).
• CTE coefficient of thermal expansion
• smaller cavities 114 may mitigate the cost, manufacturing time, CTE, and coplanarity problems mentioned above, but associated drawbacks include reduced space to accommodate additional electronic devices.
• Surfaces 117 are sloping surfaces, but in examples, the surfaces 117 are vertical surfaces.
• the semiconductor package 100 is depicted as being a QFN package.
• a cavity 114 may be formed in a top surface of BGA packages, DIPs, QFN packages, power packages, small outline packages (SOP), etc.
• SOP small outline packages
• the configuration of structures inside the semiconductor package may vary, possibly depending on the type of package used. For example, clips, vias, balls, etc. may be used in lieu of bond wires 126.
• the RDL 110 may be designed as desired and using any suitable pattern to achieve appropriate communications and/or power transfer between the active surface of the semiconductor die 108 and, e.g., the conductive terminals 116, bond wires 126, etc.
• the conductive terminals 116 are depicted as rectangular members and as a pair. In examples, however, each conductive terminal 116 may have any suitable shape, for example, a sphere, a rectangular prism, or an irregular shape. In addition, more or fewer than two conductive terminals 116 may be included. Depending on the metallization pattern of the RDL 110, the conductive terminals 116 may couple to a surface of the RDL 110 (e.g., as shown in FIG. 1A) or may be at least partially positioned inside the RDL (e.g., as shown in FIG. 2 A).
• FIG. IB depicts a top-down view of the semiconductor package 100.
• FIG. 1C depicts a perspective view of the semiconductor package 100.
• FIG. ID shows the semiconductor package 100 positioned on an example printed circuit board (PCB) 150 such that the conductive terminals 104 couple to the PCB 150 via solder joints 152.
• the conductive terminals 104 provide a pathway for the PCB 150 and the semiconductor die 108 within the semiconductor package 100 to exchange signals with each other.
• PCB printed circuit board
• FIG. 2A depicts an example semiconductor package 200.
• the semiconductor package 200 comprises a die pad 202, conductive terminals 204 (e.g., leads), a die attach layer 206 positioned on the die pad 202, and a semiconductor die 208 positioned on the die attach layer 206.
• Seed layers 228 are positioned on portions of an active surface of the semiconductor die 208.
• the seed layers 228 comprise, for example, titanium tungsten or copper.
• Metal layers 220 e.g., copper
• the wirebond balls 224 couple to bond wires 226, which, in turn, couple to conductive terminals 204.
• metal layers 230 provide an electrical communication pathway between the active surface of the semiconductor die 208 and conductive terminals 216.
• the metal layers 220, 230 are depicted herein as being rectangular prisms, the shapes and sizes of the metal layers 220, 230 may be configured as desired to form a metallization layer that couples various areas of the active surface of the semiconductor die 208 to other components (e.g., the wirebond balls 224 and conductive terminals 216) as desired.
• the metal layers 220 are capped by plating layers 222 (e.g., nickel palladium, nickel tungsten).
• a dielectric layer 218 abuts the metal layers 220, 230 and the conductive terminals 216, as shown.
• RDL such as the RDL 110 described with respect to FIG. 1 A above.
• the term RDL does not always include dielectrics, but for purposes of simplicity and clarity of explanation, the RDLs described herein are said to include dielectrics, such as the dielectric layer 218.
• a mold compound 212 covers the die pad 202, conductive terminals 204, die attach layer 206, semiconductor die 208, and the RDL of FIG. 2 A.
• the conductive terminals 216 include metal posts (e.g., copper) 232 that are capped with plating layers 234 (e.g., tin silver).
• the conductive terminals 216 couple to the metal layers 230 and are partially positioned within a cavity 214. Accordingly, the conductive terminals 216 may be said to extend from the RDL, through mold compound 212, and into the cavity 214. In examples, however, the conductive terminals 216 do not extend into the cavity 214 but are exposed to the cavity 214, meaning that the distal ends of the conductive terminals 216 are not covered by the mold compound 212 and thus are accessible from within the cavity 214. In such examples, the distal ends of the conductive terminals 216 may be flush with a bottom surface 215 of the cavity 214 or may be recessed below the bottom surface 215 of the cavity 214.
• the conductive terminals 216 have lengths ranging from 50 microns to 1 mm, widths ranging from 50 microns to 1 mm, and heights ranging from 10 microns to 100 microns.
• the scope of this description is not limited to these specific dimensions.
• the various possible dimensions of the conductive terminals 216 are not mere design choices, but rather have specific advantages and disadvantages associated therewith.
• larger conductive terminals 216 may result in improved electrical and thermal performance due to a larger conductive area, but associated drawbacks include lessened coplanarity during manufacture.
• smaller conductive terminals 216 may improve coplanarity, but associated drawbacks include worsened electrical and thermal performance.
• a greater number of conductive terminals 216 provides the ability to couple more electronic devices and/or greater flexibility in terms of electrical access to the semiconductor die 208, but occupies more space in the cavity 214. Conversely, fewer conductive terminals 216 result in less flexibility and a diminished number of electronic devices that may be coupled, but less space is occupied in the cavity 214.
• FIG. 2B depicts a top-down view of the semiconductor package 200.
• FIG. 2C depicts a perspective view of the semiconductor package 200.
• electronic devices such as those described above, may be coupled to the conductive terminals 216 as desired.
• An example process for fabricating the semiconductor package 200 is described below.
• FIG. 3A depicts a profile cross-sectional view of a semiconductor package 300.
• the semiconductor package 300 is virtually identical to the semiconductor package 200, with like numerals referring to like components (e.g., a die pad 302 in FIG. 3A is identical to the die pad 202 in FIG. 2A; conductive terminals 304 in FIG. 3A are identical to the conductive terminals 204 in FIG.
• the semiconductor package 300 includes conductive terminals 316 that are spherical or semi-spherical.
• the conductive terminals 316 couple to the metal layers 330 and extend through the mold compound 312 and into the cavity 314.
• the conductive terminals 316 are composed of solder.
• the conductive terminals 316 are composed of another metal or metal alloy.
• the diameter of each of the conductive terminals 316 ranges from 100 microns to 500 microns, although other diameters are contemplated and included in the scope of this description.
• FIG. 3B depicts a top-down view of the semiconductor package 300.
• FIG. 3C depicts a perspective view of the semiconductor package 300. An example process for fabricating the semiconductor package 300 is described below.
• FIG. 4A depicts a profile cross-sectional view of a semiconductor package 400.
• the semiconductor package 400 is virtually identical to the semiconductor package 300, with like numerals referring to like components, except that the semiconductor package 400 includes plating layers 440 (e.g., nickel palladium, nickel tungsten) capping the metal layers 430, as shown.
• the plating layers 440 serve as a bond pad finish.
• FIG. 4B depicts a top-down view of the semiconductor package 400.
• FIG. 4C depicts a perspective view of the semiconductor package 400.
• FIG. 5 A is a profile, cross-sectional view of a semiconductor device 501 comprising a semiconductor package 500 and multiple electronic devices 550, 552, 554.
• the semiconductor package 500 is depicted as being a DIP style package with gullwing conductive terminals 504. As is true for the semiconductor packages 100-400, however, the semiconductor package 500 is not limited to implementation as a DIP package and instead may be implemented as any suitable type of package, for example, the package types listed above.
• the semiconductor package 500 includes a die pad 502 and a semiconductor die 508 coupled to the die pad 502 by way of a die attach layer 506.
• An RDL 510 is formed on an active surface of the semiconductor die 508. Example processes for forming the RDLs shown in FIGs.
• RDLs comprising additional structures, for example, the RDL 510 which has six conductive terminals 516 coupled thereto.
• Bond wires 526 couple the RDL 510 to conductive terminals 504 (e.g., gullwing style leads).
• a mold compound 512 covers the die pad 502, die attach layer 506, semiconductor die 508, RDL 510, bond wires 526, and at least portions of the conductive terminals 504.
• the conductive terminals 516 extend from the RDL 510, through the mold compound 512, and into a cavity 514.
• the conductive terminals 516 do not extend into the cavity 514 but are exposed to the cavity 514, meaning that the distal ends of the conductive terminals 516 are not covered by the mold compound 512 and thus are accessible from within the cavity 514.
• FIG. 5D depicts, the distal ends of the conductive terminals 516 are flush with the bottom surface 515 of the cavity 514, and as FIG.
• the distal ends of the conductive terminals 516 are recessed below the bottom surface 515 of the cavity 514. Accessibility to recessed conductive terminals 516 may be improved by using, e.g., reflowed solder connections 599, although such solder bumps may be omitted in some examples.
• conductive terminals 516 are depicted to illustrate the fact that any desired number of conductive terminals may be used in the various examples described herein.
• the shapes and sizes of the conductive terminals 516 may vary and may include, for example, any of the shapes and/or sizes of the various conductive terminals described above.
• the electronic devices 550, 552, 554 may be of any suitable type, such as those described above (e.g., semiconductor packages, active components, passive components).
• the electronic devices 550, 552, 554 are the same type of device, and in other examples, at least one of the electronic devices 550, 552, 554 is different from the remaining electronic devices 550, 552, 554.
• Conductive terminals 516 couple the electronic devices 550, 552, 554 to the RDL 510, as shown.
• optional bond wires 556 couple the electronic devices 550, 552 to each other.
• optional bond wires 558 couple the electronic devices 552, 554 to each other.
• the electronic devices 550, 552, 554 may communicate with the semiconductor die 508 via the conductive terminals 516 and the RDL 510; with each other via the bond wires 556, 558; with each other via the conductive terminals 516 and the RDL 510; with the semiconductor die 508 via bond wires 556, 558, the conductive terminals 516, and the RDL 510; and other devices via the bond wires 556, 558 and/or the conductive terminals 516, the RDL 510, bond wires 526, the conductive terminals 504, and a PCB to which the conductive terminals 504 may couple.
• FIG. 5B is a top-down view of the semiconductor device 501.
• the cavity 514 includes the electronic devices 550, 552, and 554.
• the cavity 514 may also include additional electronic devices 555, 557 that are not visible in the view of FIG. 5A.
• the various electronic devices 550, 552, 554, 555, and 557 may be the same type of electronic device or may include at least one electronic device that is of a different type than the remaining electronic devices.
• FIG. 5C is a perspective view of the semiconductor device 501.
• FIG. 6A is a profile, cross-sectional view of a semiconductor device 601.
• the semiconductor device 601 includes a semiconductor package 600 and an electronic device 660.
• the semiconductor package 600 is similar to the semiconductor package 100, with like numerals referring to like components, except that it has additional conductive terminals, as described below.
• the example electronic device 660 comprises a semiconductor package, for example a DIP with gullwing style conductive terminals. Conductive terminals 662 of the electronic device 660 couple to conductive terminals 616. In this way, the circuitry (e.g., formed on a semiconductor die) within the electronic device 660 is able to communicate with the active surface of a semiconductor die 608 via the conductive terminals 662, 616 and an RDL 610.
• the electronic device 660 may communicate with other devices, for example via the conductive terminals 662, 616, the RDL 610, bond wires 626, and conductive terminals 604, which may couple to a PCB on which such other devices may be mounted.
• FIG. 6B depicts a top-down view of the semiconductor device 601.
• FIG. 6C depicts a perspective view of the semiconductor device 601.
• FIG. 7 is a flow diagram of a method 700 for fabricating a semiconductor device comprising a semiconductor package having a cavity to store an electronic device, in various examples.
• the method 700 may be used, for example, to fabricate the various semiconductor devices and/or packages described above.
• the method 700 begins with providing a leadframe strip (702).
• An inactive surface of a semiconductor die is coupled to a die pad of a leadframe in the leadframe strip using die attach material (704).
• the method 700 comprises forming an RDL on an active surface of the semiconductor die (706).
• FIGs. 8A-8F, 9A-9E2, 10A-10G, and 11A-11G provide example process flows for the fabrication of an RDL and are now described in turn, followed by a description of the remainder of the method 700.
• the structure of FIG. 8A is the result of providing a semiconductor die 800 and positioning (e.g., sputtering) a seed layer 802 (e.g., titanium tungsten or copper) on an active surface of the semiconductor die 800.
• the structure of FIG. 8B is the result of applying a photoresist coat (not expressly shown), exposing the photoresist coat using an appropriately patterned mask, developing the photoresist coat, plating (e.g., electroplating) a metal layer 804 (e.g., a copper layer), plating a plating layer 806 (e.g., nickel palladium, nickel tungsten) on a distal end of the metal layer 804, and stripping the photoresist coat.
• a photoresist coat not expressly shown
• plating e.g., electroplating
• a metal layer 804 e.g., a copper layer
• plating a plating layer 806 e.g., nickel palladium, nickel
• the structure of FIG. 8C is the result of applying a photoresist coat (not expressly shown), exposing the photoresist coat using an appropriately patterned mask, developing the photoresist coat, plating a metal layer 808 (e.g., a copper layer), and stripping the photoresist coat.
• a photoresist coat (not expressly shown)
• exposing the photoresist coat using an appropriately patterned mask developing the photoresist coat
• plating a metal layer 808 e.g., a copper layer
• the structure depicted in FIG. 8D is formed by removing (e.g., etching away) the seed layer 802, except for the portions of the seed layer 802 positioned under the metal layers 804, 808.
• the structure depicted in FIG. 8E is formed by applying a polyimide coat 810, exposing the polyimide coat 810 using a suitably patterned mask, developing the polyimide coat 810 to form orifices 812, 814, performing a post-develop bake (PDB) on the structure, and curing the structure.
• the structure depicted in FIG. 8F is formed by depositing (e.g., sputtering) a seed layer 811 (only a portion of which is shown in FIG.
• the structure depicted in FIG. 8F is further formed by applying a photoresist coat (not expressly shown), exposing the photoresist coat using a suitably patterned mask, developing the photoresist coat, plating a metal post 816 (e.g., copper), plating a plating layer 818 (e.g., tin silver) on a distal end of the metal post 816, and stripping the remaining photoresist coat.
• a photoresist coat not expressly shown
• exposing the photoresist coat using a suitably patterned mask developing the photoresist coat
• plating a metal post 816 e.g., copper
• plating a plating layer 818 e.g., tin silver
• the metal layer 804 may correspond to, e.g., the metal layers 220 (FIG. 2A), 320 (FIG. 3A), and 420 (FIG. 4A) described above, while the metal layer 808 may correspond to, e.g., the metal layers 230 (FIG. 2A), 330 (FIG. 3A), and 430 (FIG. 4A) described above.
• the structure of FIG. 9A is the result of applying (e.g., sputtering) a seed layer 902 to an active surface of a semiconductor die 900, as shown.
• the seed layer 902 comprises titanium tungsten or copper.
• a photoresist coat (not expressly shown) is applied, the photoresist coat is exposed using a suitably patterned mask (not expressly shown), the photoresist coat is developed, and metal layers 904, 908 (e.g., copper) are plated. The photoresist coat is then removed.
• the remaining seed layer 902 is etched away, except for the portions of the seed layer 902 positioned below the metal layers 904, 908.
• a polyimide coat 910 is applied, exposed using a suitably patterned mask (not expressly shown), and developed to produce the shape of the polyimide coat 910 shown, including orifices 912, 914.
• the polyimide coat 910 may also be subjected to a postdevelop baking (PDB) process and a curing process.
• PDB postdevelop baking
• another seed layer 911 is deposited (e.g., sputtered).
• a photoresist coat (not expressly shown) is applied, exposed using a suitably patterned mask (not expressly shown), and developed.
• a plating layer 906 is added using, e.g., a nickel palladium or nickel tungsten electroplating process, and the remaining photoresist coat is then removed.
• another photoresist coat (not expressly shown) is applied, exposed using a suitably patterned mask (not expressly shown), and developed.
• a metal post 916 (e.g., copper) is formed using, e.g., an electroplating process, and the metal post 916 is capped on a distal end with a plating layer 918, which may be formed using a tin silver electroplating process, for example.
• the metal post 916 and the plating layer 918 together form a conductive terminal.
• the remaining seed layer 911 is etched away except for the portions shown remaining under the plating layer 906 and the metal post 916.
• this description assumes the use of polyimide in the polyimide coat 910, in some examples, polybenzoxazole may be used instead of polyimide.
• the plating layer 906 may be shaped and/or sized differently than shown, for example by adjusting the mask pattern used to develop a corresponding photoresist coat.
• the mask may be formed so that the underlying photoresist coat has a narrower opening in which to plate the plating layer 906, producing a narrower plating layer 906.
• the mask may be formed so that the underlying photoresist coat has a wider opening in which to plate the plating layer 906, producing a wider plating layer 906.
• the metal layer 904 may correspond to, e.g., the metal layers 220 (FIG.
• metal layer 908 may correspond to, e.g., the metal layers 230 (FIG. 2A), 330 (FIG. 3A), and 430 (FIG. 4A) described above.
• FIG. 10A-10E The process flow depicted in FIGs. 10A-10E is similar to that depicted in FIGs. 8A-8E, with like numerals referring to like components (e.g., semiconductor die 1000 is similar to semiconductor die 800, seed layer 1002 is similar to seed layer 802, and so on).
• FIG. 10B differs from FIG. 8B in that a metal layer 1008 is shown as being formed prior to a metal layer 1004, while in FIG. 8B, the metal layer 804 is being shown formed before the metal layer 808.
• FIG. 8B and 10B either possibility falls within the scope of this description.
• a conductive terminal 1016 specifically, a metal sphere (e.g., solder ball), is shown being positioned on the metal layer 1008.
• the conductive terminal 1016 is coupled to the metal layer 1008.
• the conductive terminal 1016 may be reflowed to couple the conductive terminal 1016 to the metal layer 1008, and it may be subsequently reflowed again to couple the conductive terminal 1016 to an electronic device as described above.
• the metal layer 1004 may correspond to, e.g., the metal layers 220 (FIG. 2A), 320 (FIG. 3 A), and 420 (FIG. 4A) described above
• the metal layer 1008 may correspond to, e.g., the metal layers 230 (FIG. 2A), 330 (FIG. 3A), and 430 (FIG. 4A) described above.
• a seed layer 1102 (e.g., titanium tungsten, copper) is deposited on a semiconductor die 1100.
• a photoresist coat (not expressly shown) is applied, exposed using a suitably patterned mask (not expressly shown), and developed.
• Metal layers 1104, 1108 e.g., copper layers
• plating layers 1106, 1107 e.g., nickel palladium, nickel tungsten
• portions of the seed layer 1102 are etched away, as shown.
• a polyimide coat 1110 is applied, exposed using a suitably patterned mask (not expressly shown), and developed to form the shape shown, including orifices 1112, 1114.
• a PDB process and a curing process are performed on the polyimide coat 1110.
• a conductive terminal 1116 e.g., a metal sphere, such as a solder ball
• the conductive terminal 1116 is reflowed to couple to the plating layer 1107.
• the conductive terminal 1116 may again be subsequently reflowed to couple to an electronic device, as described above.
• the metal layer 1104 may correspond to, e.g., the metal layers 220 (FIG. 2A), 320 (FIG. 3A), and 420 (FIG. 4A) described above, while the metal layer 1108 may correspond to, e.g., the metal layers 230 (FIG. 2A), 330 (FIG. 3A), and 430 (FIG. 4A) described above.
• the example process flows shown in FIGs. 8A-11G may be used to form, e.g., portions of any of the RDLs mentioned herein (e.g., RDL 110, the RDLs depicted in FIGs. 2A, 3 A, and 4A, RDL 510, RDL 610).
• the metal layers 804, 904, 1004, and 1104 in FIGs. 8F, 9E, 10G, and 1 IF, respectively may correspond to one of the metal layers 220 shown in FIGs. 2A, 3 A, and 4 A.
• the metal layers 808, 908, 1008, and 1108 in FIGs. 8F, 9E, 10G, and 1 IF, respectively may correspond to one of the metal layers 230 shown in FIGs. 2A, 3A, and 4A.
• the scope of description is not limited to the RDL metal layers and patterns depicted herein. A range of metal layers and patterns are contemplated and included in the scope of this description.
• the method 700 comprises coupling a bond wire from a conductive terminal in the RDL to a conductive terminal of the lead frame (708), for instance, using the bond wire 1150 shown in FIG. 11G.
• the method 700 subsequently comprises covering the die pad, semiconductor die, and RDL with mold compound (710); ablating (e.g., using a laser) the mold compound to form a cavity, such as the various cavities described above (712); positioning an electronic device within the cavity as described above (714); and cutting dam bars, tie bars, and conductive terminals of the lead frame, as well as forming a gull wing shape for the conductive terminals of the lead frame (716).
• FIGs. 12A-12C depict profile cross-sectional, top-down, and perspective views of a semiconductor package having a cavity to store a quad flat no lead (QFN) style semiconductor package, in various examples.
• the example structure of FIG. 12A is identical to that of FIG. 6A, except that the electronic device 660 is replaced by an electronic device 1200, which, in examples, is a QFN style semiconductor package.
• the electronic device 1200 includes conductive terminals 1202 that couple to the conductive terminals 616.
• the electronic device 1200 includes a die pad 1204 that is exposed to a bottom surface of the electronic device 1200, thereby providing superior heat dissipation into the empty space 1206.
• FIGs. 12B and 12C show top-down and perspective views of the structure of FIG. 12 A, respectively.
• the examples described herein are advantageous over stacked package configurations for multiple reasons.
• the volume of the resulting structure is the same as, or is not substantially greater than, the volume of the semiconductor package alone.
• the semiconductor device is inexpensive and efficient to manufacture.
• electrical signals are exchanged between the electronic device and the semiconductor package by way of a redistribution layer (RDL) positioned between the electronic device and the semiconductor die of the semiconductor package, thereby mitigating significant increases in distance traveled by the electrical signals and preserving electrical performance.
• RDL redistribution layer
• Open cavity packages may include exposed die pads on which semiconductor dies are mounted and wirebonded to conductive terminals (e.g., leads) that are inside the cavity. After this is done, however, the cavity must be covered by a mold compound to protect the exposed integrated circuit formed on the semiconductor die and the bond wires coupled to the integrated circuit. Modifying such an open cavity package with conductive terminals extending into the cavity from a bottom surface of the cavity is not helpful, as the integrated circuit of the semiconductor die will be facing away from the bottom surface of the cavity and thus will be unable to couple to such conductive terminals.
• the integrated circuit would not be able to couple to both the conductive terminals extending from the bottom surface of the cavity and the conductive terminals (e.g., leads) arranged around the perimeter of the cavity.
• the examples described herein include uncovered cavities. Examples described herein also include cavities that omit conductive terminals (e.g., leads) arranged around a perimeter of the cavity. As such, the cavities of the examples described herein are suitable for packages (as opposed to unpackaged semiconductor dies) and passive components that would be unsuitable for open cavity packages.
• the uncovered cavities described herein provide extra volume that may be occupied by additional electronic devices (e.g., packages, passive components) instead of being occupied by mold compound, which would be needed in a traditional or modified open cavity package. Further still, the uncovered cavities described herein enable additional heat dissipation that would not be possible with open cavity packages, which are subsequently covered to protect the unpackaged semiconductor die mounted inside the cavity.
• additional electronic devices e.g., packages, passive components
• the terms “including” and “comprising” are used in an open-ended fashion, and thus mean “including, but not limited to... .”
• the term “couple” or “couples” means either a direct connection (whether mechanical or electrical) or an indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct mechanical connection, a direct electrical connection, or an indirect electrical connection via other devices and connections. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/- 10 percent of the stated value.

Landscapes

• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=80271040

Family Applications (1)

Country Status (4)

Families Citing this family (4)

Citations (4)

Family Cites Families (25)

• 2020
  • 2020-08-24 US US17/001,429 patent/US11942386B2/en active Active
• 2021
  • 2021-08-23 WO PCT/US2021/047047 patent/WO2022046579A1/en not_active Ceased
  • 2021-08-23 JP JP2023513289A patent/JP2023539243A/ja active Pending
  • 2021-08-23 CN CN202180049887.1A patent/CN116349010A/zh active Pending
• 2024
  • 2024-03-26 US US18/617,517 patent/US12255115B2/en active Active
• 2025
  • 2025-03-18 US US19/083,217 patent/US20250218886A1/en active Pending

Patent Citations (4)

Also Published As

Similar Documents

Legal Events