WO2022042588A1 - Pilote de commutateur et système dac comprenant celui-ci - Google Patents

Pilote de commutateur et système dac comprenant celui-ci Download PDF

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Publication number
WO2022042588A1
WO2022042588A1 PCT/CN2021/114488 CN2021114488W WO2022042588A1 WO 2022042588 A1 WO2022042588 A1 WO 2022042588A1 CN 2021114488 W CN2021114488 W CN 2021114488W WO 2022042588 A1 WO2022042588 A1 WO 2022042588A1
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Prior art keywords
circuits
logic device
circuit
switch driver
group
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PCT/CN2021/114488
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English (en)
Chinese (zh)
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罗豪
常云峰
陈玉虎
朱文涛
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中兴通讯股份有限公司
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Publication of WO2022042588A1 publication Critical patent/WO2022042588A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, the technical field of integrated circuits, and in particular, relate to a switch driver and a DAC system including the switch driver.
  • the current digital-to-analog converter (DAC) system includes a data link (Data Path), a clock link (CLK Path) and a digital-to-analog converter core circuit (DAC Core).
  • the data link includes an interface circuit (Interface), a digital data link (Digital Data Path), a decoder (Decoder), a serializer (Serializer) and a switch driver (Switch Driver), and the clock link includes a clock receiver. (Clock Receiver), delay locked loop (DLL), divider (Divider) and some clock drivers, etc.
  • the switch driver in the data link is the main power consumption module, and the switch driver and the digital-to-analog converter core circuit have the greatest impact on the linearity of the DAC.
  • the input digital signal first receives and processes the data through the interface circuit and the digital data link.
  • the main function of the decoder is to complete the DAC segment encoding (the high bit of the DAC generally uses thermometer code, and the low bit generally uses binary encoding) , in addition, some algorithms can be applied to the data in the decoder. Since the digital data link and the decoder are digital modules, it is impossible to achieve a very high data rate, so in these digital modules, each bit of data of the DAC is generally divided into multi-phase transmission.
  • the main function of the serializer is to convert multiphase data into single phase or less phase data.
  • the main function of the switch driver is to synchronize each bit of data and increase the drive capability. Sometimes the boundaries between switch drivers and serializers are blurred, and some serialization actions can also be done in switch drivers. In addition, different data types can be employed in the switch driver, such as regular data, return-to-zero data, or return-to-one data.
  • FIG. 2 is the first conventional switch driver structure.
  • the switch driver structure uses conventional data types, with data sampling on the rising edge of the clock.
  • the two circuits above do real signaling, and the current they consume on the current source is signal dependent.
  • the next two circuits are additionally added to transmit Dummy data (pseudo data).
  • Dummy data prseudo data
  • the present disclosure provides a switch driver and a DAC system including the switch driver.
  • an embodiment of the present disclosure provides a switch driver, comprising at least two sets of circuits, each set of circuits includes a first circuit, a second circuit and a third logic device, the first circuit and the second circuit
  • the circuits respectively include a first logic device and a second logic device connected to the first logic device, and the third logic device in each group of circuits is respectively connected with the second logic device of the first circuit in the group of circuits and the second logic device in the group of circuits.
  • the second logic devices of the second circuit are connected to each other, and are used to combine and output the output signals of the two second logic devices in this group of circuits; the phases of the input signals of the first circuit and the second circuit in the same group of circuits are different, and each The phases of the input signals of the first circuits in the groups of circuits are the same, and the phases of the input signals of the second circuits in each group of circuits are the same; and the frequency of the clock signal of each of the first logic devices and/or of each of the second logic devices is one-half the clock frequency.
  • the input signal of the second logic device is return-to-zero data or normalized data.
  • the third logic device when the input signal of the second logic device is return-to-zero data, the third logic device adopts OR logic or NOR logic; when the input signal of the second logic device is In the case of normalized data, the third logic device adopts AND logic or NAND logic.
  • the input signal of the first logic device is non-return-to-zero data or non-normalized data
  • the first logic device is a logic device with a return-to-zero or a normalization function; or, the first logic device
  • the input signal of the logic device is return-to-zero data or normalized data.
  • the first logic device and the second logic device are flip-flops or latches.
  • the clock signal frequency of the third logic device is the clock frequency
  • the switch driver further includes the same number of fourth logic devices as the number of circuit groups, wherein each input signal of each fourth logic device is the second logic of the first circuit in different groups of circuits The output signal of the device and the output signal of the second logic device of the second circuit, and the fourth logic devices are configured to combine and output the input signals input to the logic device.
  • an embodiment of the present disclosure also provides a DAC system including a switch driver, including the aforementioned switch driver.
  • the DAC system further includes the same number of digital-to-analog converter DAC core circuits as the switch drivers, wherein each DAC core circuit is respectively connected to each of the switch drivers; and wherein the switches
  • the driver is the switch driver according to claim 3, each of the DAC core circuits includes the same number of dummy loads as the number of the circuit groups, and the output ends of the fourth logic devices of each switch driver are respectively connected to the respective DAC core circuits. connected to each dummy load.
  • each dummy load in each DAC core circuit has the same impedance as the output signal of each group of circuits of the switch driver in this DAC core circuit.
  • Embodiments of the present disclosure provide a switch driver and a DAC system including the switch driver.
  • the switch driver includes at least two groups of circuits, each group of circuits includes a first circuit, a second circuit and a third logic device, and the first circuit and the second circuit respectively include a first logic device and a logic device connected to the first logic device.
  • the frequency of the clock signal in each group of circuits is half the clock frequency.
  • the switches driver of the embodiment of the present disclosure can reduce the clock signal frequency of each group of circuits by half, and correspondingly reduce the frequency of each circuit in the switch driver.
  • the clock signal frequency of each group of circuits is reduced by half, the corresponding data period is doubled, data acquisition is easier, and the timing requirements are correspondingly reduced.
  • 1 is a schematic diagram of the structure of an existing DAC system
  • FIG. 2 is a schematic structural diagram of an existing switch driver
  • FIG. 3 is a schematic structural diagram of a switch driver according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram comparing 1/2 Fclk and Fclk provided in an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of another switch driver provided by an embodiment of the present disclosure.
  • FIG. 7a is a schematic diagram of a signal in a broadband mode according to an embodiment of the present disclosure.
  • FIG. 7b is a schematic diagram of a signal in a frequency mixing mode according to an embodiment of the present disclosure.
  • FIG. 7c is a schematic diagram of a signal in a narrowband low power consumption mode according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a DAC system according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another DAC system provided by an embodiment of the present disclosure.
  • Embodiments described herein may be described with reference to plan and/or cross-sectional views with the aid of idealized schematic representations of the present disclosure. Accordingly, example illustrations may be modified according to manufacturing techniques and/or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Thus, the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
  • an embodiment of the present disclosure provides a switch driver, the switch driver includes at least two groups of circuits, each group of circuits respectively includes a first circuit, a second circuit and a third logic device, the first circuit and the second circuit
  • the circuits respectively include a first logic device and a second logic device connected to the first logic device, and the third logic device in each group of circuits is respectively connected with the second logic device of the first circuit in the group of circuits and the second logic device in the group of circuits.
  • the second logic devices of the circuit are connected, and are used for combining and outputting the output signals of the two second logic devices in this group of circuits.
  • the phases of the input signals of the first circuit and the second circuit in the same group of circuits are different, and the phases of the input signals of the first circuits in each group of circuits are the same, and the phases of the input signals of the second circuits in each group of circuits are the same.
  • the frequency of the clock signal loaded in each group of circuits is one-half the clock frequency Fclk.
  • the first logic device and the second logic device can be implemented by using a flip-flop (Flip-Flop, FF) or a latch (Latch).
  • the third logic device can be implemented by selecting a data selector (multiplexer, MUX).
  • the first logic device in order to reduce the timing requirements of the switch driver for the previous stage, can select a flip-flop, which can omit a delay-locked loop (DLL) in the clock chain, further reduce power consumption, and reduce verification calculations quantity. If the timing requirement for the previous stage is not reduced, the first logic device can also be implemented by using a latch (Latch).
  • DLL delay-locked loop
  • the clock signal frequency of each first logic device and/or each second logic device is one-half the clock frequency.
  • the switch driver includes two sets of circuits, the first logic device is a flip-flop, the second logic device is a latch, and the third logic device is a MUX as an example for description.
  • the two dotted boxes respectively represent the first group of circuits and the second group of circuits, the input signal D1_in corresponds to the first circuit in the first group of circuits, and the input signal D2_in corresponds to the second circuit in the first group of circuits.
  • the third logic device in the first group of circuits is respectively connected to the second logic device of the first circuit in the first group of circuits and the second logic device of the second circuit in the first group of circuits, that is, the first circuit in the first group of circuits
  • the output signal D1 of the second logic device and the output signal D2 of the second logic device of the second circuit in the first group of circuits are respectively input to the third logic device in the first group of circuits, and the third logic device is combined with D1 and D2. , the output signal D.
  • the input signal D1_in (signal A and signal C) of the first circuit in the first group of circuits is different in phase from the input signal D2_in (signal B and signal D) of the second circuit in the first group of circuits.
  • the input signal D1b_in corresponds to the first circuit in the second group of circuits
  • the input signal D2b_in corresponds to the second circuit in the second group of circuits.
  • the third logic device in the second group of circuits is respectively connected to the second logic device of the first circuit in the second group of circuits and the second logic device of the second circuit in the second group of circuits, that is, the first circuit in the second group of circuits
  • the output signal D1b of the second logic device of the second group of circuits and the output signal D2b of the second logic device of the second circuit in the second group of circuits are respectively input to the third logic device in the second group of circuits, and the third logic device is combined with D1b and D2b , the output signal Db.
  • the input signal D1b_in (signal of the first circuit in the second group of circuits and signal ) and the input signal D2b_in (signal of the second circuit in the second group of circuits and signal ) are different in phase.
  • the input signal D1_in of the first circuit in the first group of circuits has the same phase as the input signal D1b_in of the first circuit in the second group of circuits
  • the input signal D2_in of the second circuit in the first group of circuits has the same phase as the second circuit in the second group of circuits.
  • the phase of the input signal D2b_in is the same.
  • the clock signal frequency of each first logic device in the first group of circuits is 1/2Fclk and/or the clock signal frequency of each second logic device in the first group of circuits is 1/2Fclk
  • the frequency of each first logic device in the second group of circuits is 1/2Fclk
  • the frequency of the clock signal is 1/2Fclk and/or the frequency of the clock signal of each second logic device in the second group of circuits is 1/2Fclk.
  • each group of circuits is divided into two circuits, each group of circuits respectively includes a first circuit, a second circuit and a third logic device, and the first circuit and the second circuit respectively include a first logic device device and the second logic device connected to the first logic device, the clock signal frequency in each group of circuits is half the clock frequency; in each group of circuits, the phases of the input signals of the first circuit and the second circuit are different , the phase of the input signal of the first circuit in each group of circuits is the same, the phase of the input signal of the second circuit in each group of circuits is the same, the first circuit and the second circuit are combined and output by the third logic device; Signals of two different phases are respectively input into the first circuit and the second circuit of the same group, so that the frequency of the clock signal of each group of circuits can be reduced by half, correspondingly reducing the data rate of each channel in the switch driver, thereby reducing power consumption; and , the clock signal frequency of each group of
  • the first logic device is the first level
  • the second logic device is the second level
  • the third logic device is the third level.
  • the number of the second logic device may be one or more.
  • the input signal to the second logic device is return-to-zero data or normalized data, that is, the second logic device of the first circuit and the second logic device of the second circuit in the first set of circuits, and
  • the input signals of the second logic device of the first circuit and the second logic device of the second circuit are both return-to-zero data or normalized data. Since the reset-to-zero data and the normalized data themselves are not related to the current consumed by the current source, using the reset-to-zero data or the normalized data as the input signal of the second logic device can reduce the difference between the current consumed on the current source and the signal. The correlation between the two can reduce the power consumption of the second logic device.
  • a clock signal may be loaded to the third logic device, which is beneficial to reduce output data offset and realize data synchronization.
  • the third logic device is used to perform a logic combination operation on each input signal. For example, a clock-triggered third logic device can be selected to complete data combination and synchronization at the same time.
  • the third logic device may use OR logic (OR) or NOR logic (NOR); if the input signal of the second logic device is normalized data, the third logic device can use AND logic (AND) or NAND logic (NAND). It should be noted that, the data merging logic of the third logic device is not limited to the logic relationship exemplified above.
  • the input signal of the second logic device is the return-to-zero data or the return-to-one data, and there are two specific implementation methods.
  • An implementation manner is: the input signal of the first logic device is non-return-to-zero data or non-return-to-normal data.
  • the first logic device is a logic device with a return-to-zero (RZ) or return-to-one (RO) function. That is, the input signals D1_in, D2_in, D1b_in, D2b_in of the four circuits of the switch driver are all non-return-to-zero data or non-return-to-normal data.
  • the four first logic devices of the four circuits are all logic devices having the function of returning to zero or returning to one. That is, the flip-flop in FIG. 3 is an RZ flip-flop, which can convert input non-return-to-zero data into zero-return data, or convert input non-return-to-zero data into normalized data. If the input signal is non-return-to-zero data, the first logic device is a logic device with a return-to-zero function, and if the input signal is non-return-to-zero data, the first logic device is a logic device with a normalization function.
  • the non-return-to-zero input data D1 and D2 of the two phases are respectively converted into return-to-zero data through the flip-flops (RZ FF) of the first stage, and the return-to-zero data of the two phases pass through the second stage respectively.
  • the latches are synchronized, and then merged together by the MUX triggered by the third-stage clock to generate the final output data D.
  • the RZ FF will consume the current related to the signal on the power supply, but the absolute value of the current consumption of the first stage is small, so the impact is relatively small. If signal-related current in the first stage is still a problem, the first stage power supply can be separated from the second stage power supply and the third stage power supply.
  • the input signal of the first logic device is return-to-zero data or normalized data. That is to say, the input signals D1_in, D2_in, D1b_in, D2b_in of the four circuits of the switch driver are all return-to-zero data or return-to-unity data, so that the first logic device may not have a return-to-zero or return-to-unity function.
  • FIG. 4 is another conventional switch driver structure.
  • the switch driver structure is characterized by the compatibility of normal mode and mixer mode. In the mixing mode, the data will change on the rising and falling edges of the clock. The data corresponding to the falling edge is the inversion of the data corresponding to the rising edge, which is equivalent to the mixing effect of the real signal and the clock signal.
  • the output of the DAC system realizes a Band-pass transfer function centered on Fclk (regular mode is low-pass transfer function), which is helpful for lower bandwidth applications at mid-range frequencies.
  • this switch driver has been found to have the following problems:
  • a clock signal whose frequency is the clock frequency Fclk may be loaded into the third logic device. Since the frequency of the clock signal loaded on the first logic device and the second logic device is 1/2 Fclk, the frequency of the clock signal loaded on the third logic device is Fclk. As shown in Figure 5, both the rising edge and the falling edge of 1/2Fclk correspond to the rising edge of Fclk.
  • the duration of high and low levels is only related to the clock period, that is, the duty cycle does not change, so it does not affect the linearity of the DAC system.
  • the third logic device may be used to combine the output signal of the first circuit and the output signal of the second circuit, instead of Loading the clock signal (ie, not tapping) can further reduce power consumption.
  • the switch driver shown in FIG. 2 may also use logic devices in the third stage to transmit Dummy data instead of the Dummy circuit.
  • the switch driver may further include fourth logic devices, the number of the fourth logic devices is the same as the number of circuit groups, and each input signal of each fourth logic device is the second logic of the first circuit in different groups of circuits The output signal of the device and the output signal of the second logic device of the second circuit, and each fourth logic device is used to combine and output various input signals input to the logic device.
  • the fourth logic device can be implemented by selecting a data selector (MUX). As shown in FIG.
  • two MUXs are used to replace the existing Dummy circuit, and the output signal D1 of the second logic device of the first circuit in the first group and the output signal of the second logic device of the second circuit in the second group are combined D2b is used as two input signals of one of the MUXs, and the MUX outputs the signal Dum after combining D1 and D2b.
  • the output signal D2 of the second logic device of the second circuit in the first group and the output signal D1b of the second logic device of the first circuit in the second group are used as two input signals of another MUX, the MUX pair D2 and D1b
  • the combined output signal Dumb The combined output signal Dumb.
  • the embodiment of the present disclosure increases the Two MUXs are created, and the two MUXs are used to generate Dummy data Dum and Dumb respectively to compensate the current consumed by the third logic device on the current source, so that the current consumed by the third logic device on the current source is independent of the signal.
  • the use of MUX instead of Dummy circuit can also reduce power consumption to a large extent.
  • the second logic device also processes return-to-zero data or normalized data.
  • the current drawn on the current source is independent of the signal.
  • the third stage only needs to add two MUXs to achieve that the current consumed on the current source is independent of the signal, and there is no need to set up two additional Dummy circuits, thus saving power consumption.
  • the switch driver provided by the embodiment of the present disclosure can be applied to a wideband mode, a mixing mode, and a narrowband low power consumption mode.
  • the signal processing in the above three modes is described in detail below with reference to FIGS. 7a-7c respectively.
  • the input signals of the first circuit of the first group are A and C
  • the input signals of the second circuit of the first group are B, D
  • the signals B, D and the signals A, C phase is different.
  • the input signal of the first circuit of the second group is
  • the input signal of the second circuit of the second group is Signal with signal The phase of the signal is different, but it is the same as the phase of the signal A and C.
  • the output signal D of the first group of circuits is obtained by combining the signals D1 and D2, which are A, B, C, and D
  • the output signal Db of the second group of circuits is obtained by combining the signals D1b and D2b, as
  • the Dummy signal Dum is obtained by combining the signals D1 and D2b, which are A, C.
  • the Dummy signal Dumb is obtained by combining the signals D2 and D1b, as B. D.
  • the real data and Dummy data change at every beat, the bandwidth reaches the maximum, and the output transfer function of the DAC system is low-pass.
  • the input signals of the first circuit of the first group are A and C
  • the input signals of the second circuit of the first group are Signal Different from the phase of signals A and C.
  • the input signal of the first circuit of the second group is The input signals of the second circuit of the second group are A and C, the signals A and C of the second group of circuits and the signals of the second group of circuits
  • the phase is different, but is different from the signal of the first group of the same phase.
  • the output signal D of the first group of circuits is obtained by combining the signals D1 and D2, which are A, C.
  • the output signal Db of the second group of circuits is obtained by combining the signals D1b and D2b, as A.
  • the Dummy signal Dum is obtained by combining the signals D1 and D2b, which are A, A, C, and C, and the Dummy signal Dumb is obtained by combining the signals D2 and D1b, as Mixing mode can be considered as a special case of regular mode, which changes signal B in wideband mode to signal Change signal D to signal It is equivalent to the mixing effect of the real signal and the clock signal, and finally a band-pass transfer function centered on Fclk is realized at the output of the DAC system.
  • the mixing mode is suitable for high-intermediate frequency applications.
  • the amount of data that needs to be passed in most of the data paths at the front end of the switch driver can be halved (ie, only signals A, C are passed, and It can be obtained by inverting the front-end of the switch driver), thereby greatly reducing the power consumption of the front-end data path of the switch driver.
  • the number of switch drivers is determined according to the number of DAC bits and segmentation (generally, the high bits are thermometer codes, and the low bits are binary codes), and each switch driver is a unit (Slice), Multi-bit data output is performed, and these output data will be connected to the corresponding DAC core circuit and converted into corresponding analog quantities. These analog quantities are added together to form the final DAC output differential voltage Vout.
  • the output data of each switch driver is in the form of A, C. ( A.
  • the corresponding analog quantity is the mixing of the analog signal and the clock signal corresponding to the input of each switch driver
  • the DAC output differential voltage Vout formed by adding these analog quantities together is the mixing of the real input signal and the clock signal.
  • the data distribution method can be random distribution, or distribution according to a specific algorithm, which increases the flexibility of the design and can achieve different output effects.
  • the input signals of the first circuit of the first group are A and C
  • the input signals of the second circuit of the first group are A and C
  • the signal A of the first circuit , C and the signals A, C of the second circuit have different phases.
  • the input signal of the first circuit of the second group is
  • the input signal of the second circuit of the second group is The signal of the second circuit signal with the first circuit The phase is different, but it is the same as the phase of the signals A and C of the first group of the second circuit.
  • the output signal D of the first group of circuits is obtained by combining the signals D1 and D2, which are A, A, C, and C
  • the output signal Db of the second group of circuits is obtained by combining the signals D1b and D2b, as
  • the Dummy signal Dum is obtained by combining the signals D1 and D2b, which are A, C.
  • the Dummy signal Dumb is obtained by combining the signals D2 and D1b, as A. C.
  • the narrow-band low-power mode can also be regarded as a special case of the conventional mode. It changes the signal B in the broadband mode to the signal A, and changes the signal D to the signal C to realize a narrow-band low-pass transfer function.
  • the clock signal frequency of the third logic device of the third stage can also be 1/2Fclk.
  • the narrow-band low-power mode can also halve the amount of data that needs to be passed by most of the data paths in the front-end of the switch driver (ie, only signals A, C, signal It can be obtained by inverting the front-end of the switch driver), thereby greatly reducing the power consumption of the front-end data path of the switch driver.
  • the traditional switch driver shown in Figure 4 has different clock frequencies and poor compatibility in wideband mode, frequency mixing mode and narrowband low power consumption mode.
  • the switch driver provided by the embodiment of the present disclosure has the same clock frequency in the above-mentioned three modes, the compatibility of various modes is better, and the implementation is simple and easy to implement. Therefore, when a large bandwidth (ie, a wideband mode) needs to be implemented, a higher clock frequency signal is not loaded, and power consumption is not increased accordingly.
  • Embodiments of the present disclosure further provide a DAC system, where the DAC system includes a switch driver, and the switch driver can adopt the aforementioned switch driver structure to achieve multi-mode, low power consumption, and high linearity.
  • the DAC system further includes a DAC core circuit, the number of DAC core circuits is the same as the number of switch drivers, and each DAC core circuit is respectively connected to each switch driver.
  • the switch driver is the aforementioned switch driver.
  • Each DAC core circuit includes a Dummy load. The number of the Dummy load is the same as the number of circuits in the corresponding switch driver.
  • the output terminals of the fourth logic devices of each switch driver are respectively connected to Each Dummy load in each DAC core circuit is connected.
  • the number N of DAC core circuits and the number N of switch drivers are determined according to the number of DAC bits and the segmentation situation.
  • One switch driver is a unit (Slice), which performs multi-bit data output, and a DAC core circuit is a unit (Slice). data reception.
  • FIG. 8 and FIG. 9 only exemplarily show two parts of the switch driver and the DAC core circuit, and the other parts of the clock link and the data link are not shown.
  • each Dummy load in each DAC core circuit has the same impedance as the output signals of each group of circuits of the switch driver in the DAC core circuit.
  • Figure 8 shows the structure of the multi-mode resistive DAC circuit.
  • the real data D ⁇ N:0> and Db ⁇ N:0> output by the switch driver are respectively connected to the inverter circuits INV1 and INV1 in the DAC core circuit.
  • the input of INV2, INV1 is used to select the signal D or VDD to the left port of the resistor Ru1, and INV2 is used to select the signal Db or VDD to the left port of the resistor Ru2.
  • the right ports of Ru1 in all DAC core circuits can be connected together and connected to the load resistor RL as the positive end of the differential output, and the right ports of Ru2 in all DAC core circuits are connected together as the negative end of the differential output. a resistor network.
  • the number of Ru1 and Ru2 connected to VDD in the resistor network is different, which realizes the linear conversion relationship between the output differential voltage Vout and the input data.
  • the Dummy data Dum ⁇ N:0> and Dumb ⁇ N:0> output by the switch driver enter the core circuit and then connect to Dummy load 1 and Dummy load 2.
  • Dummy load 1 and Dummy load 2 are approximately the same as the real data D ⁇ N:0 > is consistent with the load of Db ⁇ N:0>, that is, it is approximately the same as the impedance connected to the input terminals of INV1 and INV2.
  • VDD can be replaced with positive and negative reference potentials
  • Ru1 and Ru2 can be set to different resistance values in different DAC core circuits to achieve different weights.
  • Dummy load 1 and Dummy load 2 are added to the DAC core circuit. According to actual needs, Dummy load 1 and Dummy load 2 can also be omitted.
  • the DAC core circuit shown in FIG. 8 is a basic resistive DAC circuit structure, and other resistive DAC circuits may also be used in the embodiments of the present disclosure.
  • FIG. 9 is a circuit structure of a multi-mode current steering DAC.
  • the real data D ⁇ N:0> and Db ⁇ N:0> output by the switch driver are respectively connected to the gates of the switch transistors T1 and T2 in the DAC core circuit to select which lead T1 and T2 are on. Turn on, let the output current of the current source go to the upper port of the load resistor RL1 or RL2 (that is, the positive terminal or the negative terminal of the DAC differential output).
  • the drains of T1 of all DAC core circuits are connected together, and the drains of T2 of all DAC core circuits are connected together.
  • Dummy data Dum ⁇ N:0> and Dumb ⁇ N:0> output by the switch driver enter the core circuit and then connect to Dummy load 1 and Dummy load 2.
  • Dummy load 1 and Dummy load 2 are approximately the same as the real data D ⁇ N:0 > is consistent with the load of Db ⁇ N:0>, that is, it is approximately the same as the impedance connected to the gates of T1 and T2.
  • Dummy load 1 and Dummy load 2 are added to the DAC core circuit. According to actual needs, Dummy load 1 and Dummy load 2 can also be omitted.
  • the DAC core circuit shown in FIG. 9 is a basic current steering type DAC circuit structure, and other current steering type DAC circuits may also be used in the embodiment of the present disclosure.
  • the embodiments of the present disclosure overcome the defects of the traditional switch driver, such as high clock frequency, high power consumption, needing a dummy path, and poor mode compatibility, and provide a multi-mode switch driver with low power consumption and high linearity, and a switch driver using the switch driver.
  • the ADC system is compatible with multiple modes and has the advantages of low power consumption and high linearity.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
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Abstract

Pilote de commutateur et système DAC comportant celui-ci. Le pilote de commutateur comprend au moins deux ensembles de circuits. Chaque ensemble de circuits comprend un premier circuit, un deuxième circuit et un troisième dispositif logique. Le premier circuit et le second circuit comprennent respectivement un premier dispositif logique et un deuxième dispositif logique connecté au premier dispositif logique. La fréquence de signal d'horloge dans chaque ensemble de circuits est la moitié d'une fréquence d'horloge. Dans chaque ensemble de circuits, les phases de signaux d'entrée du premier circuit et du second circuit sont différentes. Les phases de signaux d'entrée des premiers circuits dans les ensembles de circuits sont les mêmes, et les phases de signaux d'entrée des seconds circuits dans les ensembles de circuits sont les mêmes. Les sorties des premiers circuits et des seconds circuits sont combinées au moyen des troisièmes dispositifs logiques. Le pilote de commutateur réduit de moitié la fréquence de signal d'horloge de chaque ensemble de circuits, et par conséquent réduit le débit de données de chaque canal dans le pilote de commutateur, ce qui permet de réduire la consommation d'énergie, de doubler le cycle de données, de rendre l'acquisition de données plus facile, et de réduire les exigences de synchronisation en conséquence.
PCT/CN2021/114488 2020-08-28 2021-08-25 Pilote de commutateur et système dac comprenant celui-ci WO2022042588A1 (fr)

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CN202010883830.9A CN114124052A (zh) 2020-08-28 2020-08-28 开关驱动器和包括开关驱动器的dac系统
CN202010883830.9 2020-08-28

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CN117674774A (zh) * 2022-08-26 2024-03-08 深圳市中兴微电子技术有限公司 一种差分锁存器电路、开关驱动器以及数模转换电路

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US6031410A (en) * 1997-04-11 2000-02-29 Nec Corporation Multiplexor composed of dynamic latches
CN103427838A (zh) * 2012-05-25 2013-12-04 联发科技（新加坡）私人有限公司 开关驱动电路及运用该电路的数模转换器
US10069508B1 (en) * 2017-08-23 2018-09-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Multiplexer circuit for a digital to analog converter
US10644716B1 (en) * 2019-08-26 2020-05-05 Analog Devices International Unlimited Company Multi-path dual-switch digital-to-analog converter
CN111416621A (zh) * 2020-04-10 2020-07-14 中国科学院上海微系统与信息技术研究所 一种用于电流舵dac的功耗降低电路及方法

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EP0221290A2 (fr) * 1985-11-06 1987-05-13 Hewlett-Packard Company Architecture à double bascule pour la réduction de traversée d'horloge dans les convertisseurs numérique-analogique
US6031410A (en) * 1997-04-11 2000-02-29 Nec Corporation Multiplexor composed of dynamic latches
CN103427838A (zh) * 2012-05-25 2013-12-04 联发科技（新加坡）私人有限公司 开关驱动电路及运用该电路的数模转换器
US10069508B1 (en) * 2017-08-23 2018-09-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Multiplexer circuit for a digital to analog converter
US10644716B1 (en) * 2019-08-26 2020-05-05 Analog Devices International Unlimited Company Multi-path dual-switch digital-to-analog converter
CN111416621A (zh) * 2020-04-10 2020-07-14 中国科学院上海微系统与信息技术研究所 一种用于电流舵dac的功耗降低电路及方法

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