WO2022042588A1

WO2022042588A1 - Switch driver and dac system comprising same

Info

Publication number: WO2022042588A1
Application number: PCT/CN2021/114488
Authority: WO
Inventors: 罗豪; 常云峰; 陈玉虎; 朱文涛
Original assignee: 中兴通讯股份有限公司
Priority date: 2020-08-28
Filing date: 2021-08-25
Publication date: 2022-03-03
Also published as: CN114124052A

Abstract

Provided are a switch driver and a DAC system having same. The switch driver comprises at least two sets of circuits. Each set of circuits comprises a first circuit, a second circuit and a third logic device. The first circuit and the second circuit respectively comprise a first logic device and a second logic device connected to the first logic device. The clock signal frequency in each set of circuits is half of a clock frequency. In each set of circuits, the phases of input signals of the first circuit and the second circuit are different. The phases of input signals of the first circuits in the sets of circuits are the same, and the phases of input signals of the second circuits in the sets of circuits are the same. The outputs of the first circuits and the second circuits are combined by means of the third logic devices. The switch driver reduces the clock signal frequency of each set of circuits by half, and accordingly reduces the data rate of each channel in the switch driver, thereby reducing power consumption, doubling data cycle, making data acquisition easier, and reducing the timing requirements accordingly.

Description

Switch driver and DAC system including switch driver

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims the priority of a Chinese patent application with the application number 202010883830.9 and the invention titled "Switch Driver and DAC System Including Switch Driver" filed with the State Intellectual Property Office on August 28, 2020, the entire contents of which are hereby incorporated by reference Incorporated in this disclosure.

technical field

Embodiments of the present disclosure relate to, but are not limited to, the technical field of integrated circuits, and in particular, relate to a switch driver and a DAC system including the switch driver.

Background technique

The current digital-to-analog converter (DAC) system, as shown in Figure 1, includes a data link (Data Path), a clock link (CLK Path) and a digital-to-analog converter core circuit (DAC Core). The data link includes an interface circuit (Interface), a digital data link (Digital Data Path), a decoder (Decoder), a serializer (Serializer) and a switch driver (Switch Driver), and the clock link includes a clock receiver. (Clock Receiver), delay locked loop (DLL), divider (Divider) and some clock drivers, etc. For the DAC system, the switch driver in the data link is the main power consumption module, and the switch driver and the digital-to-analog converter core circuit have the greatest impact on the linearity of the DAC.

In the data link, the input digital signal first receives and processes the data through the interface circuit and the digital data link. The main function of the decoder is to complete the DAC segment encoding (the high bit of the DAC generally uses thermometer code, and the low bit generally uses binary encoding) , in addition, some algorithms can be applied to the data in the decoder. Since the digital data link and the decoder are digital modules, it is impossible to achieve a very high data rate, so in these digital modules, each bit of data of the DAC is generally divided into multi-phase transmission. The main function of the serializer is to convert multiphase data into single phase or less phase data. The main function of the switch driver is to synchronize each bit of data and increase the drive capability. Sometimes the boundaries between switch drivers and serializers are blurred, and some serialization actions can also be done in switch drivers. In addition, different data types can be employed in the switch driver, such as regular data, return-to-zero data, or return-to-one data.

Figure 2 is the first conventional switch driver structure. The switch driver structure uses conventional data types, with data sampling on the rising edge of the clock. The two circuits above do real signaling, and the current they consume on the current source is signal dependent. In order to reduce the influence of the signal-related current on the performance of the DAC system, the next two circuits are additionally added to transmit Dummy data (pseudo data). At each data sampling point, if the real data is not flipped, the Dummy data is flipped; if the real data is flipped, the Dummy data is not flipped. The main disadvantage of this switch driver structure is high power consumption and high timing requirements.

SUMMARY OF THE INVENTION

In view of the above-mentioned deficiencies in the prior art, the present disclosure provides a switch driver and a DAC system including the switch driver.

In a first aspect, an embodiment of the present disclosure provides a switch driver, comprising at least two sets of circuits, each set of circuits includes a first circuit, a second circuit and a third logic device, the first circuit and the second circuit The circuits respectively include a first logic device and a second logic device connected to the first logic device, and the third logic device in each group of circuits is respectively connected with the second logic device of the first circuit in the group of circuits and the second logic device in the group of circuits. The second logic devices of the second circuit are connected to each other, and are used to combine and output the output signals of the two second logic devices in this group of circuits; the phases of the input signals of the first circuit and the second circuit in the same group of circuits are different, and each The phases of the input signals of the first circuits in the groups of circuits are the same, and the phases of the input signals of the second circuits in each group of circuits are the same; and the frequency of the clock signal of each of the first logic devices and/or of each of the second logic devices is one-half the clock frequency.

In some embodiments, the input signal of the second logic device is return-to-zero data or normalized data.

In some embodiments, when the input signal of the second logic device is return-to-zero data, the third logic device adopts OR logic or NOR logic; when the input signal of the second logic device is In the case of normalized data, the third logic device adopts AND logic or NAND logic.

In some embodiments, the input signal of the first logic device is non-return-to-zero data or non-normalized data, and the first logic device is a logic device with a return-to-zero or a normalization function; or, the first logic device The input signal of the logic device is return-to-zero data or normalized data.

In some embodiments, the first logic device and the second logic device are flip-flops or latches.

In some embodiments, the clock signal frequency of the third logic device is the clock frequency.

In some embodiments, the switch driver further includes the same number of fourth logic devices as the number of circuit groups, wherein each input signal of each fourth logic device is the second logic of the first circuit in different groups of circuits The output signal of the device and the output signal of the second logic device of the second circuit, and the fourth logic devices are configured to combine and output the input signals input to the logic device.

In yet another aspect, an embodiment of the present disclosure also provides a DAC system including a switch driver, including the aforementioned switch driver.

In some embodiments, the DAC system further includes the same number of digital-to-analog converter DAC core circuits as the switch drivers, wherein each DAC core circuit is respectively connected to each of the switch drivers; and wherein the switches The driver is the switch driver according to claim 3, each of the DAC core circuits includes the same number of dummy loads as the number of the circuit groups, and the output ends of the fourth logic devices of each switch driver are respectively connected to the respective DAC core circuits. connected to each dummy load.

In some embodiments, each dummy load in each DAC core circuit has the same impedance as the output signal of each group of circuits of the switch driver in this DAC core circuit.

Embodiments of the present disclosure provide a switch driver and a DAC system including the switch driver. The switch driver includes at least two groups of circuits, each group of circuits includes a first circuit, a second circuit and a third logic device, and the first circuit and the second circuit respectively include a first logic device and a logic device connected to the first logic device. For the second logic device, the frequency of the clock signal in each group of circuits is half the clock frequency. In each group of circuits, the phases of the input signals of the first circuit and the second circuit are different, the phases of the input signals of the first circuits in each group of circuits are the same, the phases of the input signals of the second circuits in each group of circuits are the same, the first The circuit and the second circuit are combined and output through the third logic device. By inputting two signals of different phases into the first circuit and the second circuit of the same group, the switch driver of the embodiment of the present disclosure can reduce the clock signal frequency of each group of circuits by half, and correspondingly reduce the frequency of each circuit in the switch driver. In addition, the clock signal frequency of each group of circuits is reduced by half, the corresponding data period is doubled, data acquisition is easier, and the timing requirements are correspondingly reduced.

Description of drawings

1 is a schematic diagram of the structure of an existing DAC system;

2 is a schematic structural diagram of an existing switch driver;

FIG. 3 is a schematic structural diagram of a switch driver according to an embodiment of the present disclosure;

4 is a schematic structural diagram of another existing switch driver;

FIG. 5 is a schematic diagram comparing 1/2 Fclk and Fclk provided in an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of another switch driver provided by an embodiment of the present disclosure;

FIG. 7a is a schematic diagram of a signal in a broadband mode according to an embodiment of the present disclosure;

FIG. 7b is a schematic diagram of a signal in a frequency mixing mode according to an embodiment of the present disclosure;

FIG. 7c is a schematic diagram of a signal in a narrowband low power consumption mode according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a DAC system according to an embodiment of the present disclosure; and

FIG. 9 is a schematic structural diagram of another DAC system provided by an embodiment of the present disclosure.

detailed description

Example embodiments are described more fully hereinafter with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is used to describe particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "made of" are used in this specification, the stated features, integers, steps, operations, elements and/or components are specified to be present, but not precluded or Add one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Embodiments described herein may be described with reference to plan and/or cross-sectional views with the aid of idealized schematic representations of the present disclosure. Accordingly, example illustrations may be modified according to manufacturing techniques and/or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Thus, the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present disclosure, and will not be construed as having idealized or over-formal meanings, unless expressly so limited herein.

It has been found that one of the reasons for the high power consumption of the switch driver shown in Figure 2 is that the clock frequency of the switch driver is equal to the data rate, and the power consumption and timing requirements are high in high data rate applications. Moreover, in order to ensure the timing, it is necessary to increase the delay-locked loop, which will further increase the power consumption.

In order to solve the above technical problem, an embodiment of the present disclosure provides a switch driver, the switch driver includes at least two groups of circuits, each group of circuits respectively includes a first circuit, a second circuit and a third logic device, the first circuit and the second circuit The circuits respectively include a first logic device and a second logic device connected to the first logic device, and the third logic device in each group of circuits is respectively connected with the second logic device of the first circuit in the group of circuits and the second logic device in the group of circuits. The second logic devices of the circuit are connected, and are used for combining and outputting the output signals of the two second logic devices in this group of circuits. The phases of the input signals of the first circuit and the second circuit in the same group of circuits are different, and the phases of the input signals of the first circuits in each group of circuits are the same, and the phases of the input signals of the second circuits in each group of circuits are the same. The frequency of the clock signal loaded in each group of circuits is one-half the clock frequency Fclk.

In some embodiments, the first logic device and the second logic device can be implemented by using a flip-flop (Flip-Flop, FF) or a latch (Latch). The third logic device can be implemented by selecting a data selector (multiplexer, MUX). In some embodiments, in order to reduce the timing requirements of the switch driver for the previous stage, the first logic device can select a flip-flop, which can omit a delay-locked loop (DLL) in the clock chain, further reduce power consumption, and reduce verification calculations quantity. If the timing requirement for the previous stage is not reduced, the first logic device can also be implemented by using a latch (Latch).

In some embodiments, the clock signal frequency of each first logic device and/or each second logic device is one-half the clock frequency.

In the embodiment of the present disclosure, the switch driver includes two sets of circuits, the first logic device is a flip-flop, the second logic device is a latch, and the third logic device is a MUX as an example for description. As shown in FIG. 3 , the two dotted boxes respectively represent the first group of circuits and the second group of circuits, the input signal D1_in corresponds to the first circuit in the first group of circuits, and the input signal D2_in corresponds to the second circuit in the first group of circuits. The third logic device in the first group of circuits is respectively connected to the second logic device of the first circuit in the first group of circuits and the second logic device of the second circuit in the first group of circuits, that is, the first circuit in the first group of circuits The output signal D1 of the second logic device and the output signal D2 of the second logic device of the second circuit in the first group of circuits are respectively input to the third logic device in the first group of circuits, and the third logic device is combined with D1 and D2. , the output signal D. The input signal D1_in (signal A and signal C) of the first circuit in the first group of circuits is different in phase from the input signal D2_in (signal B and signal D) of the second circuit in the first group of circuits. The input signal D1b_in corresponds to the first circuit in the second group of circuits, and the input signal D2b_in corresponds to the second circuit in the second group of circuits. The third logic device in the second group of circuits is respectively connected to the second logic device of the first circuit in the second group of circuits and the second logic device of the second circuit in the second group of circuits, that is, the first circuit in the second group of circuits The output signal D1b of the second logic device of the second group of circuits and the output signal D2b of the second logic device of the second circuit in the second group of circuits are respectively input to the third logic device in the second group of circuits, and the third logic device is combined with D1b and D2b , the output signal Db. The input signal D1b_in (signal of the first circuit in the second group of circuits

and signal

) and the input signal D2b_in (signal of the second circuit in the second group of circuits

and signal

) are different in phase.

The input signal D1_in of the first circuit in the first group of circuits has the same phase as the input signal D1b_in of the first circuit in the second group of circuits, and the input signal D2_in of the second circuit in the first group of circuits has the same phase as the second circuit in the second group of circuits. The phase of the input signal D2b_in is the same. The clock signal frequency of each first logic device in the first group of circuits is 1/2Fclk and/or the clock signal frequency of each second logic device in the first group of circuits is 1/2Fclk, and the frequency of each first logic device in the second group of circuits is 1/2Fclk. The frequency of the clock signal is 1/2Fclk and/or the frequency of the clock signal of each second logic device in the second group of circuits is 1/2Fclk.

In the switch driver and DAC system provided by the embodiments of the present disclosure, each group of circuits is divided into two circuits, each group of circuits respectively includes a first circuit, a second circuit and a third logic device, and the first circuit and the second circuit respectively include a first logic device device and the second logic device connected to the first logic device, the clock signal frequency in each group of circuits is half the clock frequency; in each group of circuits, the phases of the input signals of the first circuit and the second circuit are different , the phase of the input signal of the first circuit in each group of circuits is the same, the phase of the input signal of the second circuit in each group of circuits is the same, the first circuit and the second circuit are combined and output by the third logic device; Signals of two different phases are respectively input into the first circuit and the second circuit of the same group, so that the frequency of the clock signal of each group of circuits can be reduced by half, correspondingly reducing the data rate of each channel in the switch driver, thereby reducing power consumption; and , the clock signal frequency of each group of circuits is reduced by half, the corresponding data period is doubled, data acquisition is easier, and the timing requirements are correspondingly reduced.

In the embodiment of the present disclosure, as shown in FIG. 3 , four circuits are used to transmit real data. In each circuit, the first logic device is the first level, the second logic device is the second level, and the third logic device is the third level. stage, the number of the second logic device may be one or more.

In some embodiments, the input signal to the second logic device is return-to-zero data or normalized data, that is, the second logic device of the first circuit and the second logic device of the second circuit in the first set of circuits, and In the second group of circuits, the input signals of the second logic device of the first circuit and the second logic device of the second circuit are both return-to-zero data or normalized data. Since the reset-to-zero data and the normalized data themselves are not related to the current consumed by the current source, using the reset-to-zero data or the normalized data as the input signal of the second logic device can reduce the difference between the current consumed on the current source and the signal. The correlation between the two can reduce the power consumption of the second logic device.

In some embodiments, as shown in FIG. 3 , in some embodiments, further, a clock signal may be loaded to the third logic device, which is beneficial to reduce output data offset and realize data synchronization. The third logic device is used to perform a logic combination operation on each input signal. For example, a clock-triggered third logic device can be selected to complete data combination and synchronization at the same time.

In some embodiments, if the input signal of the second logic device is return-to-zero data, the third logic device may use OR logic (OR) or NOR logic (NOR); if the input signal of the second logic device is normalized data, the third logic device can use AND logic (AND) or NAND logic (NAND). It should be noted that, the data merging logic of the third logic device is not limited to the logic relationship exemplified above.

It is ensured that the input signal of the second logic device is the return-to-zero data or the return-to-one data, and there are two specific implementation methods. An implementation manner is: the input signal of the first logic device is non-return-to-zero data or non-return-to-normal data. Correspondingly, the first logic device is a logic device with a return-to-zero (RZ) or return-to-one (RO) function. That is, the input signals D1_in, D2_in, D1b_in, D2b_in of the four circuits of the switch driver are all non-return-to-zero data or non-return-to-normal data. Correspondingly, the four first logic devices of the four circuits are all logic devices having the function of returning to zero or returning to one. That is, the flip-flop in FIG. 3 is an RZ flip-flop, which can convert input non-return-to-zero data into zero-return data, or convert input non-return-to-zero data into normalized data. If the input signal is non-return-to-zero data, the first logic device is a logic device with a return-to-zero function, and if the input signal is non-return-to-zero data, the first logic device is a logic device with a normalization function. For example, as shown in Figure 3, the non-return-to-zero input data D1 and D2 of the two phases are respectively converted into return-to-zero data through the flip-flops (RZ FF) of the first stage, and the return-to-zero data of the two phases pass through the second stage respectively. The latches are synchronized, and then merged together by the MUX triggered by the third-stage clock to generate the final output data D.

It should be noted that the RZ FF will consume the current related to the signal on the power supply, but the absolute value of the current consumption of the first stage is small, so the impact is relatively small. If signal-related current in the first stage is still a problem, the first stage power supply can be separated from the second stage power supply and the third stage power supply.

Another implementation manner is: the input signal of the first logic device is return-to-zero data or normalized data. That is to say, the input signals D1_in, D2_in, D1b_in, D2b_in of the four circuits of the switch driver are all return-to-zero data or return-to-unity data, so that the first logic device may not have a return-to-zero or return-to-unity function.

Figure 4 is another conventional switch driver structure. The switch driver structure is characterized by the compatibility of normal mode and mixer mode. In the mixing mode, the data will change on the rising and falling edges of the clock. The data corresponding to the falling edge is the inversion of the data corresponding to the rising edge, which is equivalent to the mixing effect of the real signal and the clock signal. Finally, the output of the DAC system realizes a Band-pass transfer function centered on Fclk (regular mode is low-pass transfer function), which is helpful for lower bandwidth applications at mid-range frequencies. However, this switch driver has been found to have the following problems:

1. If you want to achieve large bandwidth, you still need a relatively high clock frequency and increase power consumption.

2. In the case where the current consumed by the signal-related current source has a great influence on the performance of the DAC system, two additional dummy circuits are required to transmit dummy data to reduce the influence of the signal-related current on the performance of the DAC system. . But even if the dummy circuit is used to transfer dummy data, since the third stage includes latch (Latch), exclusive OR logic (XOR) and multiplexer (MUX), the current consumed on the current source is still related to the clock frequency Fclk , in the mixing mode, the output data rate Fdata is not equal to the clock frequency Fclk, but is equal to 2*Fclk, so it has an impact on the linearity of the DAC system.

3. In the third stage, data changes will occur on both the rising and falling edges of the clock, causing the duty cycle of the clock to change, thus affecting the linearity of the DAC system.

In order to solve the problem of affecting the linearity of the DAC system in the frequency mixing mode, in some embodiments, a clock signal whose frequency is the clock frequency Fclk may be loaded into the third logic device. Since the frequency of the clock signal loaded on the first logic device and the second logic device is 1/2 Fclk, the frequency of the clock signal loaded on the third logic device is Fclk. As shown in Figure 5, both the rising edge and the falling edge of 1/2Fclk correspond to the rising edge of Fclk. In mixing mode, the duration of high and low levels is only related to the clock period, that is, the duty cycle does not change, so it does not affect the linearity of the DAC system.

It should be noted that, in some embodiments, if the deviation of the clock duty cycle has little effect on the performance of the DAC, only the third logic device may be used to combine the output signal of the first circuit and the output signal of the second circuit, instead of Loading the clock signal (ie, not tapping) can further reduce power consumption.

It has also been found that, in the switch driver shown in FIG. 2 , the two-way Dummy data transfer consumes about half of the power consumption, that is, the Dummy circuit is an important factor leading to excessive power consumption. In order to further reduce power consumption, the switch driver provided by the embodiments of the present disclosure may also use logic devices in the third stage to transmit Dummy data instead of the Dummy circuit.

In some embodiments, the switch driver may further include fourth logic devices, the number of the fourth logic devices is the same as the number of circuit groups, and each input signal of each fourth logic device is the second logic of the first circuit in different groups of circuits The output signal of the device and the output signal of the second logic device of the second circuit, and each fourth logic device is used to combine and output various input signals input to the logic device. The fourth logic device can be implemented by selecting a data selector (MUX). As shown in FIG. 6 , two MUXs are used to replace the existing Dummy circuit, and the output signal D1 of the second logic device of the first circuit in the first group and the output signal of the second logic device of the second circuit in the second group are combined D2b is used as two input signals of one of the MUXs, and the MUX outputs the signal Dum after combining D1 and D2b. The output signal D2 of the second logic device of the second circuit in the first group and the output signal D1b of the second logic device of the first circuit in the second group are used as two input signals of another MUX, the MUX pair D2 and D1b The combined output signal Dumb.

Since the data merging is performed at the third stage (ie, the third logic device), the current consumed on the current source is again related to the signal. In order to eliminate the correlation between the current consumed on the current source and the signal, the embodiment of the present disclosure increases the Two MUXs are created, and the two MUXs are used to generate Dummy data Dum and Dumb respectively to compensate the current consumed by the third logic device on the current source, so that the current consumed by the third logic device on the current source is independent of the signal. Moreover, the use of MUX instead of Dummy circuit can also reduce power consumption to a large extent. It should be noted that if the input signal of the first logic device is return-to-zero data or normalized data, correspondingly, the second logic device also processes return-to-zero data or normalized data. The current drawn on the current source is independent of the signal. The third stage only needs to add two MUXs to achieve that the current consumed on the current source is independent of the signal, and there is no need to set up two additional Dummy circuits, thus saving power consumption.

The switch driver provided by the embodiment of the present disclosure can be applied to a wideband mode, a mixing mode, and a narrowband low power consumption mode. The signal processing in the above three modes is described in detail below with reference to FIGS. 7a-7c respectively.

As shown in Fig. 7a, in the broadband mode, the input signals of the first circuit of the first group are A and C, the input signals of the second circuit of the first group are B, D, the signals B, D and the signals A, C phase is different. The input signal of the first circuit of the second group is

The input signal of the second circuit of the second group is

Signal

with signal

The phase of the signal is different, but it is the same as the phase of the signal A and C. The output signal D of the first group of circuits is obtained by combining the signals D1 and D2, which are A, B, C, and D, and the output signal Db of the second group of circuits is obtained by combining the signals D1b and D2b, as

The Dummy signal Dum is obtained by combining the signals D1 and D2b, which are A,

C.

The Dummy signal Dumb is obtained by combining the signals D2 and D1b, as

B.

D. As can be seen from Figure 7a, the real data and Dummy data change at every beat, the bandwidth reaches the maximum, and the output transfer function of the DAC system is low-pass.

As shown in Figure 7b, in the mixing mode, the input signals of the first circuit of the first group are A and C, and the input signals of the second circuit of the first group are

Signal

Different from the phase of signals A and C. The input signal of the first circuit of the second group is

The input signals of the second circuit of the second group are A and C, the signals A and C of the second group of circuits and the signals of the second group of circuits

The phase is different, but is different from the signal of the first group

of the same phase. The output signal D of the first group of circuits is obtained by combining the signals D1 and D2, which are A,

C.

The output signal Db of the second group of circuits is obtained by combining the signals D1b and D2b, as

A.

C, the Dummy signal Dum is obtained by combining the signals D1 and D2b, which are A, A, C, and C, and the Dummy signal Dumb is obtained by combining the signals D2 and D1b, as

Mixing mode can be considered as a special case of regular mode, which changes signal B in wideband mode to signal

Change signal D to signal

It is equivalent to the mixing effect of the real signal and the clock signal, and finally a band-pass transfer function centered on Fclk is realized at the output of the DAC system. The mixing mode is suitable for high-intermediate frequency applications. In mixing mode, the amount of data that needs to be passed in most of the data paths at the front end of the switch driver can be halved (ie, only signals A, C are passed, and

It can be obtained by inverting the front-end of the switch driver), thereby greatly reducing the power consumption of the front-end data path of the switch driver.

It should be noted that, in the entire DAC system, the number of switch drivers is determined according to the number of DAC bits and segmentation (generally, the high bits are thermometer codes, and the low bits are binary codes), and each switch driver is a unit (Slice), Multi-bit data output is performed, and these output data will be connected to the corresponding DAC core circuit and converted into corresponding analog quantities. These analog quantities are added together to form the final DAC output differential voltage Vout. As shown in Figure 7b, in the mixing mode, the output data of each switch driver is in the form of A,

C.

(

A.

C), the corresponding analog quantity is the mixing of the analog signal and the clock signal corresponding to the input of each switch driver, and the DAC output differential voltage Vout formed by adding these analog quantities together is the mixing of the real input signal and the clock signal. In fact, in order to realize the mixing of the real input signal and the clock signal, it is not necessary to present such a data form at the output of each switch driver, as long as the combined effect of all the switch driver outputs is so. Since there are many switch driver units with equivalent weights in the thermometer coding design, A(C) and

Assigned to different switch driver units, as long as their weights are the same, the final effect seen in the DAC output differential voltage Vout is still a mixing effect. The data distribution method can be random distribution, or distribution according to a specific algorithm, which increases the flexibility of the design and can achieve different output effects.

As shown in Figure 7c, in the narrow-band low power consumption mode, the input signals of the first circuit of the first group are A and C, the input signals of the second circuit of the first group are A and C, and the signal A of the first circuit , C and the signals A, C of the second circuit have different phases. The input signal of the first circuit of the second group is

The input signal of the second circuit of the second group is

The signal of the second circuit

signal with the first circuit

The phase is different, but it is the same as the phase of the signals A and C of the first group of the second circuit. The output signal D of the first group of circuits is obtained by combining the signals D1 and D2, which are A, A, C, and C, and the output signal Db of the second group of circuits is obtained by combining the signals D1b and D2b, as

C.

The Dummy signal Dumb is obtained by combining the signals D2 and D1b, as

A.

C. The narrow-band low-power mode can also be regarded as a special case of the conventional mode. It changes the signal B in the broadband mode to the signal A, and changes the signal D to the signal C to realize a narrow-band low-pass transfer function. In narrow-band applications To reduce power consumption, in this case, the clock signal frequency of the third logic device of the third stage can also be 1/2Fclk. Similarly, the narrow-band low-power mode can also halve the amount of data that needs to be passed by most of the data paths in the front-end of the switch driver (ie, only signals A, C, signal

The traditional switch driver shown in Figure 4 has different clock frequencies and poor compatibility in wideband mode, frequency mixing mode and narrowband low power consumption mode. On the other hand, the switch driver provided by the embodiment of the present disclosure has the same clock frequency in the above-mentioned three modes, the compatibility of various modes is better, and the implementation is simple and easy to implement. Therefore, when a large bandwidth (ie, a wideband mode) needs to be implemented, a higher clock frequency signal is not loaded, and power consumption is not increased accordingly.

Embodiments of the present disclosure further provide a DAC system, where the DAC system includes a switch driver, and the switch driver can adopt the aforementioned switch driver structure to achieve multi-mode, low power consumption, and high linearity.

In some embodiments, as shown in FIGS. 8 and 9 , the DAC system further includes a DAC core circuit, the number of DAC core circuits is the same as the number of switch drivers, and each DAC core circuit is respectively connected to each switch driver. The switch driver is the aforementioned switch driver. Each DAC core circuit includes a Dummy load. The number of the Dummy load is the same as the number of circuits in the corresponding switch driver. The output terminals of the fourth logic devices of each switch driver are respectively connected to Each Dummy load in each DAC core circuit is connected.

The number N of DAC core circuits and the number N of switch drivers are determined according to the number of DAC bits and the segmentation situation. One switch driver is a unit (Slice), which performs multi-bit data output, and a DAC core circuit is a unit (Slice). data reception.

It should be noted that, FIG. 8 and FIG. 9 only exemplarily show two parts of the switch driver and the DAC core circuit, and the other parts of the clock link and the data link are not shown.

In some embodiments, each Dummy load in each DAC core circuit has the same impedance as the output signals of each group of circuits of the switch driver in the DAC core circuit. By setting the Dummy load in the DAC core circuit, the compensation current is more accurate, and the effect of reducing the correlation between the current consumed on the current source and the signal is better.

Figure 8 shows the structure of the multi-mode resistive DAC circuit. As shown in Figure 8, the real data D<N:0> and Db<N:0> output by the switch driver are respectively connected to the inverter circuits INV1 and INV1 in the DAC core circuit. The input of INV2, INV1 is used to select the signal D or VDD to the left port of the resistor Ru1, and INV2 is used to select the signal Db or VDD to the left port of the resistor Ru2. The right ports of Ru1 in all DAC core circuits can be connected together and connected to the load resistor RL as the positive end of the differential output, and the right ports of Ru2 in all DAC core circuits are connected together as the negative end of the differential output. a resistor network. According to the different data of D<N:0> and Db<N:0>, the number of Ru1 and Ru2 connected to VDD in the resistor network is different, which realizes the linear conversion relationship between the output differential voltage Vout and the input data. The Dummy data Dum<N:0> and Dumb<N:0> output by the switch driver enter the core circuit and then connect to Dummy load 1 and Dummy load 2. Dummy load 1 and Dummy load 2 are approximately the same as the real data D<N:0 > is consistent with the load of Db<N:0>, that is, it is approximately the same as the impedance connected to the input terminals of INV1 and INV2.

It should be noted that VDD can be replaced with positive and negative reference potentials, and Ru1 and Ru2 can be set to different resistance values in different DAC core circuits to achieve different weights. In order to ensure that the loads of the Dummy data and the real data at the input end of the DAC core circuit are approximately the same, Dummy load 1 and Dummy load 2 are added to the DAC core circuit. According to actual needs, Dummy load 1 and Dummy load 2 can also be omitted. The DAC core circuit shown in FIG. 8 is a basic resistive DAC circuit structure, and other resistive DAC circuits may also be used in the embodiments of the present disclosure.

FIG. 9 is a circuit structure of a multi-mode current steering DAC. As shown in Figure 9, the real data D<N:0> and Db<N:0> output by the switch driver are respectively connected to the gates of the switch transistors T1 and T2 in the DAC core circuit to select which lead T1 and T2 are on. Turn on, let the output current of the current source go to the upper port of the load resistor RL1 or RL2 (that is, the positive terminal or the negative terminal of the DAC differential output). The drains of T1 of all DAC core circuits are connected together, and the drains of T2 of all DAC core circuits are connected together. For the entire DAC core circuit, according to the different data of D<N:0> and Db<N:0>, the total current flowing to RL1 and the total current flowing to RL2 are different, and the corresponding differential output voltage Vout is also different. Finally, the linear conversion relationship between the output differential voltage Vout and the input data is realized. The Dummy data Dum<N:0> and Dumb<N:0> output by the switch driver enter the core circuit and then connect to Dummy load 1 and Dummy load 2. Dummy load 1 and Dummy load 2 are approximately the same as the real data D<N:0 > is consistent with the load of Db<N:0>, that is, it is approximately the same as the impedance connected to the gates of T1 and T2.

It should be noted that, in order to ensure that the loads of the Dummy data and the real data at the input end of the DAC core circuit are approximately the same, Dummy load 1 and Dummy load 2 are added to the DAC core circuit. According to actual needs, Dummy load 1 and Dummy load 2 can also be omitted. . The DAC core circuit shown in FIG. 9 is a basic current steering type DAC circuit structure, and other current steering type DAC circuits may also be used in the embodiment of the present disclosure.

The embodiments of the present disclosure overcome the defects of the traditional switch driver, such as high clock frequency, high power consumption, needing a dummy path, and poor mode compatibility, and provide a multi-mode switch driver with low power consumption and high linearity, and a switch driver using the switch driver. The ADC system is compatible with multiple modes and has the advantages of low power consumption and high linearity.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should only be construed in a general descriptive sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments, unless expressly stated otherwise. Features and/or elements are used in combination. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as set forth in the appended claims.

Claims

A switch driver includes at least two groups of circuits, each group of circuits includes a first circuit, a second circuit and a third logic device, the first circuit and the second circuit respectively include a first logic device and the The second logic device connected to the first logic device, the third logic device in each group of circuits is respectively connected to the second logic device of the first circuit in the group of circuits and the second logic device of the second circuit in the group of circuits, using for combining and outputting the output signals of the two second logic devices in this group of circuits;

The phases of the input signals of the first circuits and the second circuits in the same group of circuits are different, and the phases of the input signals of the first circuits in each group of circuits are the same, and the phases of the input signals of the second circuits in each group of circuits are the same; and

The frequency of the clock signal loaded in each group of circuits is one-half the clock frequency.
The switch driver according to claim 1, wherein a clock signal frequency of each of the first logic devices and/or each of the second logic devices is one-half a clock frequency.
The switch driver of claim 1, wherein the input signal of the second logic device is return-to-zero data or normalized data.
The switch driver according to claim 3, wherein, when the input signal of the second logic device is return-to-zero data, the third logic device adopts OR logic or NOR logic; in the second logic device When the input signal of the logic device is normalized data, the third logic device adopts AND logic or NAND logic.
The switch driver according to claim 3, wherein the input signal of the first logic device is non-return-to-zero data or non-normalization data, and the first logic device is a logic device with a return-to-zero or a return-to-one function; Alternatively, the input signal of the first logic device is return-to-zero data or normalized data.
The switch driver of claim 5, wherein the first logic device and the second logic device are flip-flops or latches.
The switch driver of claim 1, wherein the clock signal frequency of the third logic device is a clock frequency.
The switch driver according to any one of claims 3-7, further comprising the same number of fourth logic devices as the number of circuit groups, wherein each input signal of each fourth logic device is the first one in different groups of circuits The output signal of the second logic device of the circuit and the output signal of the second logic device of the second circuit, and the fourth logic devices are configured to combine and output the input signals input to the logic device.
A DAC system, wherein the DAC system comprises the switch driver of any one of claims 1-8.
The DAC system of claim 9, further comprising the same number of digital-to-analog converter DAC core circuits as the switch drivers, wherein each DAC core circuit is respectively connected to each of the switch drivers; and wherein the switches The driver is the switch driver according to claim 3, each of the DAC core circuits includes the same number of dummy loads as the number of the circuit groups, and the output ends of the fourth logic devices of each switch driver are respectively connected to the respective DAC core circuits. connected to each dummy load.
The DAC system of claim 10 , wherein each pseudo load in each DAC core circuit has the same impedance as the output signal of each group of circuits of the switch driver in the DAC core circuit.