WO2022042021A1 - 一种存储器的制作方法以及存储器 - Google Patents

一种存储器的制作方法以及存储器 Download PDF

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Publication number
WO2022042021A1
WO2022042021A1 PCT/CN2021/103823 CN2021103823W WO2022042021A1 WO 2022042021 A1 WO2022042021 A1 WO 2022042021A1 CN 2021103823 W CN2021103823 W CN 2021103823W WO 2022042021 A1 WO2022042021 A1 WO 2022042021A1
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Prior art keywords
bit line
layer
forming
conductive layer
support layer
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PCT/CN2021/103823
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English (en)
French (fr)
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卢经文
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长鑫存储技术有限公司
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Priority to US17/441,194 priority Critical patent/US11856755B2/en
Publication of WO2022042021A1 publication Critical patent/WO2022042021A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present disclosure relates to, but is not limited to, a method for fabricating a memory and a memory.
  • Memory is a memory component used to store programs and various data information. According to the use type of memory, it can be divided into read-only memory and random access memory.
  • a memory typically includes a capacitor, which is used to store charge representing the stored information, and a transistor connected to the capacitor, which is a switch that controls the flow of charge into and out of the capacitor.
  • the bit line conductive layer and the bit line insulating layer together serve as the bit line structure of the memory.
  • the method for forming the bit line structure is to sequentially deposit the bit line conductive layer and the bit line insulating layer, and then etch the bit line conductive layer and the bit line insulating layer into separate bit line structures.
  • bit line structure when the bit line structure is etched, the depth of the etching needs to be deep, the sidewall of the etched bit line structure is often not vertical enough, and the bit line conductive layer may be over-etched, resulting in the bit line The conductive layer is damaged, affecting the conductivity of the bit line structure.
  • the purpose of the embodiments of the present disclosure is to provide a method for fabricating a memory, which is beneficial to improve the conductivity of the bit line structure.
  • An embodiment of the present disclosure provides a method for fabricating a memory, including: providing a substrate, forming a sacrificial layer on the substrate; patterning the sacrificial layer, forming a plurality of mutually discrete dummy bit line layers on the substrate; forming a support layer, the support layer filling Filling the area between adjacent dummy bit line layers; removing the dummy bit line layer to form a bit line space between adjacent support layers; forming a bit line structure, the bit line structure filling the bit line space, and the bit line structure includes sequentially Stacked bit line conductive layers and bit line insulating layers; removing the support layer to form openings between adjacent bit line structures.
  • An embodiment of the present disclosure provides a memory, and the memory is formed according to the above-mentioned method for fabricating a memory.
  • a patterned sacrificial layer is used to form a dummy bit line layer, so that the position of the bit line structure can be defined; a support layer is filled in the area between the dummy bit line layers to define the bit line structure. The position of the area between the line structures; the dummy bit line layer is removed, the bit line space is formed between the support layers, the bit line conductive layer and the bit line insulating layer are filled in sequence to form the bit line structure, and the support layer is removed.
  • the fabrication method provided by the embodiments of the present disclosure avoids the problem of the morphology defect of the bit line conductive layer that occurs when the bit line structure is formed by etching, and also avoids the over-etching of the bit line conductive layer, thereby improving the performance of the bit line conductive layer. damage, thereby improving the conductivity of the bit line conductive layer and improving the electrical performance of the memory.
  • FIG. 1 is a schematic cross-sectional structure diagram of a step of forming a sacrificial layer on a substrate according to an embodiment of the disclosure
  • FIG. 2 is a schematic cross-sectional structural diagram of a step of forming a dummy bit line layer on a substrate according to an embodiment of the disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of a step of forming a protective layer according to an embodiment of the disclosure
  • FIG. 4 is a schematic cross-sectional structural diagram of a step of forming an initial support layer according to an embodiment of the disclosure
  • FIG. 5 is a schematic cross-sectional structural diagram of a step of forming a support layer according to an embodiment of the disclosure
  • FIG. 6 is a schematic cross-sectional structure diagram of a step of removing a protective layer on top of a dummy bit line layer according to an embodiment of the disclosure
  • FIG. 7 is a schematic cross-sectional structure diagram of a step of removing a dummy bit line layer according to an embodiment of the disclosure.
  • FIG. 8 is a schematic cross-sectional structure diagram of a step of forming a first conductive layer according to an embodiment of the disclosure
  • FIG. 9 is a schematic cross-sectional structural diagram of a step of etching back to remove a partial thickness of the first conductive layer according to an embodiment of the disclosure.
  • FIG. 10 is a schematic cross-sectional structural diagram of a step of forming a diffusion barrier layer according to an embodiment of the disclosure
  • FIG. 11 is a schematic cross-sectional structure diagram of a step of forming a second conductive layer according to an embodiment of the disclosure.
  • FIG. 12 is a schematic cross-sectional structural diagram of a step of etching back to remove a partial thickness of the second conductive layer according to an embodiment of the disclosure
  • FIG. 13 is a schematic cross-sectional structural diagram of a step of etching back the diffusion barrier layer according to an embodiment of the disclosure
  • FIG. 14 is a schematic cross-sectional structural diagram of a step of forming a bit line insulating layer on top of the bit line conductive layer according to an embodiment of the disclosure
  • 15 is a schematic cross-sectional structure diagram of a step of etching back the bit line insulating layer to expose the top of the support layer according to an embodiment of the disclosure
  • 16 is a schematic cross-sectional structural diagram of a step of removing a support layer according to an embodiment of the disclosure
  • 17 is a schematic cross-sectional structure diagram of a step of removing a protective layer on a substrate between adjacent bit line structures according to an embodiment of the disclosure.
  • the memory bit line structure includes a bit line conductive layer and a bit line insulating layer.
  • bit line conductive layer When forming the bit line structure, it is often necessary to etch a deeper depth. Due to the difference in the selectivity ratio of the etchant for different structures, the The sidewall profiles form trenches.
  • further etching is required to remove the bit line contact material remaining between the bit line contact windows, so as to avoid short circuit between multiple adjacent bit line structures. This results in over-etching of the sidewalls on both sides of the bit line contact window. With the progress of the etching, the phenomenon of lateral etching will gradually occur. The etching will cause the problem of morphology defects in the conductive layer of the bit line. At the same time, the conductive layer of the bit line will be over-etched, and the conductive layer of the bit line will be damaged. affect the electrical performance of the memory.
  • the present disclosure provides a method for fabricating a memory.
  • a patterned sacrificial layer is used to form a dummy bit line layer, so that the position of the bit line structure can be defined; a support layer is filled in the area between the dummy bit line layers to define the bit line structure. The position of the area between them is removed; the dummy bit line layer is removed, a bit line space is formed between the support layers, and the bit line structure is filled in sequence, and the support layer is removed.
  • the fabrication method provided by the embodiment of the present disclosure avoids the problem of the morphology defect of the bit line conductive layer that occurs when the bit line structure is formed by etching, and also avoids the over-etching of the bit line conductive layer, thereby improving the bit line conductive layer. damage, thereby improving the conductivity of the bit line conductive layer and improving the electrical performance of the memory.
  • FIG. 1-17 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a memory according to an embodiment of the present disclosure.
  • a substrate 100 is provided on which a sacrificial layer 111 is formed.
  • the substrate 100 has active areas 110 (AA, Active Area), and isolation areas 120 are disposed between the active areas 110 , and the isolation areas 120 are used to isolate adjacent active areas 110 .
  • active areas 110 AA, Active Area
  • isolation areas 120 are disposed between the active areas 110 , and the isolation areas 120 are used to isolate adjacent active areas 110 .
  • the sacrificial layer 111 is a single-layer structure, and in other embodiments, the sacrificial layer may also be a stacked-layer structure.
  • the material of the sacrificial layer 111 is silicon dioxide. When the same material is etched, the anisotropy in each direction is basically the same, so it can effectively avoid over-etching during etching. In other embodiments, the material of the sacrificial layer can also be other materials.
  • the formation process of the sacrificial layer 111 is a chemical vapor deposition process, and the process temperature is 600° C. ⁇ 630° C., such as 605° C., 610° C., 615° C., 620° C. or 625° C., etc.
  • the deposition process may also be physical vapor deposition or atomic layer deposition.
  • the sacrificial layer 111 (refer to FIG. 1 ) is patterned, and a plurality of discrete dummy bit line layers 101 are formed on the substrate 100 .
  • the function of the dummy bit line layer 101 includes defining the position of the bit line structure so as to form the bit line structure subsequently.
  • the dummy bit line layer 101 is located above the active region 110 and at the gap between the isolation regions 120 , and the sidewall profile of the dummy bit line layer 101 is smooth and perpendicular to the substrate 100 .
  • the process steps after forming the dummy bit line layer 101 include: forming a support layer 102 , and the support layer 102 fills the area between adjacent dummy bit line layers 101 .
  • the method for fabricating the memory before forming the support layer 102 , further includes: referring to FIG. 3 , forming a protective layer 105 , the protective layer 105 covers the sidewalls of the dummy bit line layer 101 and is also located on adjacent dummy bits on the substrate 100 between the wire layers 101 .
  • the protective layer 105 can protect the bit line conductive layer in the bit line structure formed in the subsequent process steps, and further improve the insulation between the bit line conductive layer and the capacitor contact window formed later in the memory fabrication process.
  • the process steps of forming the protective layer 105 include: forming a first silicon nitride layer 115 covering the sidewall of the dummy bit line layer 101 and the substrate 100 between adjacent dummy bit line layers 101; A silicon oxide layer 135 is formed on the first silicon nitride layer 115 ; and a second silicon nitride layer 125 is formed on the silicon oxide layer 135 .
  • the process method for forming the first silicon nitride layer 115 and the second silicon nitride layer 125 may be atomic layer deposition, and the reactive gas may be silane, ammonia, or the like.
  • the process method for forming the silicon oxide layer 135 may be atomic layer deposition, and the reaction gas may be dipropylaminosilane.
  • a chemical vapor deposition process or a physical vapor deposition process can also be used to form the protective layer, and the reactive gas can also be selected from other gases.
  • the protective layer may also have a single-layer structure or a double-layer structure.
  • the protective layer may also be formed after the subsequent formation of the bit line structure.
  • an initial support layer 112 is formed between adjacent dummy bit line layers 101 , and the initial support layer 112 is also located on top of the dummy bit line layer 101 .
  • an initial support layer 112 is formed on the surface of the protective layer 105 .
  • the initial support layer 112 (refer to FIG. 4 ) is planarized, and the initial support layer 112 higher than the top of the dummy bit line layer 101 is removed to form the support layer 102 .
  • the process of removing the initial support layer 112 higher than the top of the dummy bit line layer 101 can be dry etching, and the etching gas can be selected from sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, oxygen, argon, etc., or their gas mixture. In other embodiments, other processes may be used to remove the initial support layer above the top of the dummy bit line layer.
  • the material of the support layer 102 is polysilicon
  • the process for forming the support layer 102 is a chemical vapor deposition process
  • the reactive gas can be silane
  • the process temperature is 580°C to 620°C, such as 585°C, 596°C, 600°C or 610°C.
  • the protective layer 105 on top of the dummy bit line layer 101 is removed.
  • the protective layer 105 is also formed before the supporting layer 102 is formed, and the protective layer 105 covers the sidewalls and the top of the dummy bit line layer 101 , the top of the dummy bit line layer 101 can also be protected before the dummy bit line layer 101 is removed.
  • the layer 105 is removed to expose the dummy bit line layer 101 for subsequent removal of the dummy bit line layer 101 .
  • the process of removing the protective layer 105 may be dry etching, and the etching gas may be a mixed gas of sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, oxygen, and argon.
  • the dummy bit line layer 101 is removed to form a bit line space 106 between adjacent support layers 102 .
  • the sidewalls of the bit line space 106 are the protective layer 105 .
  • the process of removing the dummy bit line layer 101 may be wet etching, and the etching liquid for the wet etching is a hydrofluoric acid solution.
  • the process steps after removing the dummy bit line layer 101 include: forming a bit line structure that fills the bit line space 106 , and the bit line structure includes a bit line conductive layer 103 and a bit line insulating layer 104 stacked in sequence.
  • the process steps of forming the bit line structure include: forming a bit line conductive layer 103 in the bit line space 106, and the top of the bit line conductive layer 103 is lower than the top of the supporting layer 102; forming a bit line insulating layer 104 on the top of the bit line conductive layer 103, and The bit line insulating layer 104 exposes the top of the support layer 102 .
  • the formation steps of the bit line structure will be described in detail below with reference to the accompanying drawings.
  • the first conductive layer 113 is formed to fill the bit line space 106 ; referring to FIG. 8 , the first conductive layer 113 is formed to fill the bit line space 106 ; referring to FIG. 8 , the first conductive layer 113 is formed to fill the bit line space 106 ; referring to FIG. 8 , the first conductive layer 113 is formed to fill the bit line space 106 ; referring to FIG. 8 , the first conductive layer 113 is formed to fill the bit line space 106 ; referring to FIG.
  • the bit line conductive layer 103 includes the bit line contact window 133 , and the material of the supporting layer 102 is the same as the material of the bit line contact window 133 , and the process temperature for forming the initial supporting layer 112 is higher than that for forming the bit line contact window. 133 process temperature.
  • the material of the bit line contact window 133 is polysilicon, wherein the material for forming the bit line contact window 133 also has doping ions.
  • the bit line contact window 133 is used to realize electrical connection between the bit line structure and the active region 110 .
  • the process for forming the bit line contact window 133 is a chemical vapor deposition process
  • the reactive gases are silane and phosphine
  • the process temperature is 480°C to 520°C, such as 485°C, 490°C, 500°C, or 510°C. It can be understood that, since the process temperature for forming the support layer 102 is higher than the process temperature for forming the bit line contact window 133 , the etching rate of the support layer 102 is much lower than that of the first conductive layer 113 . Therefore, when the first conductive layer 113 is wet-etched with a nitric acid solution of the same concentration, the supporting layer 102 is hardly affected.
  • the second conductive layer 123 filling the bit line space 106 is formed on the bit line contact window 133 .
  • a diffusion barrier layer 153 may also be formed between the bit line contact window 133 and the bit line conductive pillar 143 , and the material of the diffusion barrier layer 153 may be tantalum nitride or titanium nitride.
  • a partial thickness of the second conductive layer 123 is removed by etching back, and the remaining second conductive layer 123 is used as the bit line conductive pillar 143 .
  • the material of the bit line conductive pillars 143 includes metal conductive materials such as tungsten, gold or silver.
  • the diffusion barrier layer 153 is etched back.
  • the diffusion barrier layer 153 may be etched back.
  • a wet etching process is used to etch back a partial thickness of the first conductive layer 113 .
  • other etching processes can also be used to remove part of the thickness of the first conductive layer 113 to form the bit line contact window 133.
  • the thickness of the removed first conductive layer 113 is determined according to the bit line conductive layer in the bit line structure of the memory.
  • the bit line conductive layer 103 includes the bit line contact windows 133 and the bit line conductive pillars 143 stacked in sequence.
  • bit line insulating layer 104 is formed on top of the bit line conductive layer 103 , and the bit line insulating layer 104 exposes the top of the support layer 102 .
  • the process steps of forming the bit line insulating layer 104 include: referring to FIG. 14 , forming the bit line insulating layer 104 on top of the bit line conductive layer 103 ; referring to FIG. 15 , etching the bit line insulating layer 104 back to expose the top of the support layer 102 .
  • the main function of the bit line insulating layer 104 is to insulate the surface of the bit line structure.
  • the formed bit line structure includes a bit line conductive layer and a bit line insulating layer stacked in sequence, and the formed bit line conductive layer avoids the morphology defect and the bit line of the bit line conductive layer formed by etching the bit line structure in the prior art.
  • the conductive layer is over-etched.
  • the material of the support layer 102 is different from the material of the bit line insulating layer 104 .
  • the material of the bit line insulating layer 104 includes silicon nitride. In other embodiments, the material of the bit line insulating layer may also be silicon oxide, silicon oxynitride or silicon oxycarbonitride.
  • the support layer 102 is removed to form openings between adjacent bit line structures.
  • the process of removing the support layer 102 may be dry etching, and the etching gas may be selected from sulfur hexafluoride, carbon tetrafluoride, chlorine gas, argon gas, etc., or a mixed gas thereof.
  • the protective layer 105 can effectively prevent the bit line conductive layer 103 in the bit line structure from being etched.
  • the process of removing the support layer may also use other processes.
  • the method further includes: removing the protective layer 105 on the substrate 100 between adjacent bit line structures.
  • the protective layer 105 covers the sidewalls of the bit line structures and is also located on the substrate 100 between adjacent bit line structures, so after the support layer 102 is removed, the protection layer 100 between adjacent bit line structures can also be protected The layer 105 is removed, exposing the substrate 100 to form discrete bit line structures on the substrate 100 .
  • a dummy bit line layer without etching defects is first formed, the position of the bit line structure is defined, and then the position of the region between the bit line structures is defined by the supporting layer.
  • a bit line space is formed between the layers, and the bit line conductive layer and the bit line insulating layer are filled in sequence to form a bit line structure, and finally the support layer is removed to form a bit line structure without etching defects.
  • the memory manufacturing method provided by this embodiment avoids the problem of the morphology defect of the bit line conductive layer that occurs when the bit line structure is formed by etching, and also avoids over-etching of the bit line conductive layer, thereby improving the bit line conductive layer. In the damaged condition, the conductivity of the conductive layer of the bit line is improved, and the electrical performance of the memory is further improved.
  • the memory manufacturing method provided by the present disclosure avoids the problem of the morphology defect of the bit line conductive layer that occurs when the bit line structure is formed by etching, and also avoids over-etching of the bit line conductive layer, thereby improving the resistance of the bit line conductive layer. It can improve the conductivity of the bit line conductive layer and further improve the electrical performance of the memory.

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Abstract

本公开提供一种存储器制作方法，包括：提供基底，在基底上形成牺牲层；图形化牺牲层，在基底上形成多个相互分立的伪位线层；形成支撑层，支撑层填充满相邻伪位线层之间的区域；去除伪位线层，形成位于相邻支撑层之间的位线空间；形成位线结构，位线结构填充位线空间，且位线结构包括依次堆叠的位线导电层以及位线绝缘层；去除支撑层，形成位于相邻位线层之间的开口。

Description

一种存储器的制作方法以及存储器
本公开要求在2020年08月31日提交中国专利局、申请号为202010895429.7、发明名称为“一种存储器的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种存储器的制作方法以及存储器。
背景技术
存储器是用来存储程序和各种数据信息的记忆部件，按存储器的使用类型可分为只读存储器和随机存取存储器。存储器通常包括电容器以及与电容器连接的晶体管，电容器用来存储代表存储信息的电荷，晶体管是控制电容器的电荷流入和释放的开关。位线导电层作为存储器的位线结构的一部分，与位线绝缘层共同作为存储器的位线结构。其中，位线结构的形成方法是依次沉积位线导电层以及位线绝缘层，再将位线导电层以及位线绝缘层刻蚀成相互分立的位线结构。
然而，在刻蚀位线结构时，需要刻蚀的深度较深，刻蚀出来的位线结构侧壁往往会出现不够垂直的情况，位线导电层会出现过刻蚀的情况，导致位线导电层受损，影响位线结构的导电性。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例的目的在于提供一种存储器制作方法，有利于提高位线结构的导电性。
本公开实施例提供一种存储器的制作方法，包括：提供基底，在基底上形成牺牲层；图形化牺牲层，在基底上形成多个相互分立的伪位线层；形成支撑层，支撑层填充满相邻伪位线层之间的区域；去除伪位线层，形成位于 相邻支撑层之间的位线空间；形成位线结构，位线结构填充位线空间，且位线结构包括依次堆叠的位线导电层以及位线绝缘层；去除支撑层，形成位于相邻位线结构之间的开口。
本公开实施例提供一种存储器，存储器根据上述存储器的制作方法形成。
本公开实施例提供的一种存储器的制作方法，利用图形化牺牲层形成伪位线层，以便能够定义出位线结构的位置；在伪位线层之间的区域填充支撑层，定义出位线结构之间区域的位置；去除伪位线层，在支撑层之间形成位线空间，并依次填充位线导电层以及位线绝缘层以形成位线结构，去除支撑层。本公开实施例提供的制作方法，避免了在刻蚀形成位线结构出现的位线导电层形貌缺陷问题，同时也可避免位线导电层出现过刻蚀的情况，改善位线导电层的受损情况，从而提高位线导电层的导电能力，改善存储器的电学性能。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制，对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例的在基底上形成牺牲层的步骤的剖面结构示意图；
图2为本公开一实施例的在基底上形成伪位线层的步骤的剖面结构示意图；
图3为本公开一实施例的形成保护层的步骤的剖面结构示意图；
图4为本公开一实施例的形成初始支撑层的步骤的剖面结构示意图；
图5为本公开一实施例的形成支撑层的步骤的剖面结构示意图；
图6为本公开一实施例的去除伪位线层顶部的保护层的步骤的剖面结构示意图；
图7为本公开一实施例的去除伪位线层的步骤的剖面结构示意图；
图8为本公开一实施例的形成第一导电层的步骤的剖面结构示意图；
图9为本公开一实施例的回刻蚀去除部分厚度的第一导电层的步骤的剖面结构示意图；
图10为本公开一实施例的形成扩散阻挡层的步骤的剖面结构示意图；
图11为本公开一实施例的形成第二导电层的步骤的剖面结构示意图；
图12为本公开一实施例的回刻蚀去除部分厚度的第二导电层的步骤的剖面结构示意图；
图13为本公开一实施例的对扩散阻挡层进行回刻蚀的步骤的剖面结构示意图；
图14为本公开一实施例的在位线导电层顶部形成位线绝缘层的步骤的剖面结构示意图；
图15为本公开一实施例的将位线绝缘层回刻蚀至暴露出支撑层顶部的步骤的剖面结构示意图；
图16为本公开一实施例的去除支撑层的步骤的剖面结构示意图；
图17为本公开一实施例的去除位于相邻位线结构之间的基底上的保护层的步骤的剖面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
由背景技术可知，现有技术的存储器的性能有待提高。存储器位线结构包括位线导电层以及位线绝缘层，在形成位线结构时，往往需要刻蚀的深度较深，由于刻蚀剂对不同结构存在可是选择比的差异，使得位线结构的侧壁轮廓形成沟槽。而当通过刻蚀形成位线接触窗后，还需要进一步刻蚀以去除残留在位线接触窗间的位线接触材料，避免多个相邻的位线结构接触发生短路，这一过程同时也导致了位线接触窗的两侧侧壁的过刻蚀现象。随着刻蚀 的进行，会逐渐产生横向刻蚀的现象，刻蚀造成位线导电层出现形貌缺陷问题，同时也会出现位线导电层过刻蚀的情况，位线导电层受损，影响了存储器的电学性能。
本公开实施提供一种存储器的制作方法，利用图形化牺牲层形成伪位线层，以便能够定义出位线结构的位置；在伪位线层之间的区域填充支撑层，定义出位线结构之间区域的位置；去除伪位线层，在支撑层之间形成为位线空间，并依次填充位线结构，去除支撑层。本公开实施例提供的制作方法，避免了在刻蚀形成位线结构出现的位线导电层形貌缺陷问题，同时也可避免位线导电层会出现过刻蚀的情况，改善位线导电层的受损情况，从而提高位线导电层的导电能力，改善存储器的电学性能。
本公开实施例提供的一种存储器的制作方法，以下将结合附图对本实施例提供的存储器的制作方法进行详细说明。图1-图17为本公开实施例提供的存储器的制作方法的各步骤对应的剖面结构示意图。
参考图1，提供基底100，在基底100上形成牺牲层111。
基底100内具有有源区110(AA，Active Area)，有源区110之间设置有隔离区120，隔离区120用于隔离相邻有源区110。
本公开的一些实施例中，牺牲层111为单层结构，在其他实施例中，牺牲层也可以为叠层结构。
牺牲层111的材料为二氧化硅，在对同一种材料进行刻蚀时，对各个方向上的各向异性基本相同，因此能够有效避免刻蚀时产生过刻蚀。在其他实施例中，牺牲层的材料也可以为其他材料。
牺牲层111的形成工艺为化学气相沉积工艺，工艺温度为600℃～630℃，例如605℃、610℃、615℃、620℃或625℃等。在其他实施例中，沉积工艺也可以为物理气相沉积或者原子层沉积。
参考图2，图形化牺牲层111(参考图1)，在基底100上形成多个相互分立的伪位线层101。
伪位线层101的作用包括定义位线结构的位置，以便后续形成位线结构。伪位线层101位于有源区110上方且位于隔离区120之间的间隙处，伪位线层101的侧壁轮廓平滑且垂直于基底100。
形成伪位线层101之后的工艺步骤包括：形成支撑层102，支撑层102 填充满相邻伪位线层101之间的区域。
本公开的一些实施例中，在形成支撑层102之前，存储器的制作方法还包括：参考图3，形成保护层105，保护层105覆盖伪位线层101侧壁，且还位于相邻伪位线层101之间的基底100上。
保护层105能够保护后续工艺步骤中形成的位线结构中的位线导电层，且进一步提高在存储器制作过程中位线导电层与后续形成的电容接触窗的绝缘性。
本公开的一些实施例中，形成保护层105的工艺步骤包括：形成覆盖伪位线层101侧壁、相邻伪位线层101之间的基底100上的第一氮化硅层115；在第一氮化硅层115上形成氧化硅层135；在氧化硅层135上形成第二氮化硅层125。
本公开的一些实施例中，形成第一氮化硅层115以及第二氮化硅层125的工艺方法可以是原子层沉积，反应气体可以是硅烷、氨气等。形成氧化硅层135的工艺方法可以是原子层沉积，反应气体可以是二丙氨基硅烷。在其他实施例中，也可以使用化学气相沉积工艺或者物理气相沉积工艺形成保护层，反应气体也可以选择其他气体。
在其他实施例中，保护层也可以为单层结构或者双层结构。
在其他实施例中，也可以在后续形成位线结构之后再形成保护层。
参考图4，在相邻伪位线层101之间形成初始支撑层112，且初始支撑层112还位于伪位线层101顶部。
本实施例中，在保护层105表面形成初始支撑层112。
参考图5，对初始支撑层112(参考图4)进行平坦化处理，去除高于伪位线层101顶部的初始支撑层112，形成支撑层102。
去除高于伪位线层101顶部的初始支撑层112的工艺可以为干法刻蚀，刻蚀气体可以选择六氟化硫、四氟化碳、三氟甲烷、氧气以及氩气等，或者它们的混合气体。在其他实施例中，去除高于伪位线层顶部的初始支撑层也可以使用别的工艺。
支撑层102的材料为多晶硅，形成支撑层102的工艺为化学气相沉积工艺，反应气体可以为硅烷，工艺温度为580℃～620℃，例如585℃、596℃、600℃或610℃等。
参考图6，去除伪位线层101顶部的保护层105。
由于在形成支撑层102之前，还形成了保护层105，保护层105覆盖伪位线层101侧壁以及顶部，所以在去除伪位线层101之前，还可以对伪位线层101顶部的保护层105去除，将伪位线层101暴露出来，以便后续去除伪位线层101。
去除保护层105的工艺可以为干法刻蚀，刻蚀气体可以选择六氟化硫、四氟化碳、三氟甲烷、氧气以及氩气等的混合气体。
参考图7，去除伪位线层101，形成位于相邻支撑层102之间的位线空间106。
本公开的一些实施例中，位线空间106侧壁为保护层105。
去除伪位线层101的工艺可以为湿法刻蚀，湿法刻蚀的刻蚀液体为氢氟酸溶液。
去除伪位线层101之后的工艺步骤包括：形成位线结构，该位线结构填充位线空间106，且位线结构包括依次堆叠的位线导电层103以及位线绝缘层104。
形成位线结构的工艺步骤包括：在位线空间106形成位线导电层103，且位线导电层103顶部低于支撑层102顶部；在位线导电层103顶部形成位线绝缘层104，且位线绝缘层104暴露出支撑层102顶部。以下将结合附图对位线结构的形成步骤进行详细说明。
参考图8，形成填充满位线空间106的第一导电层113；参考图9，回刻蚀去除部分厚度的第一导电层113，剩余第一导电层113作为位线接触窗133。
本公开的一些实施例中，位线导电层103包括位线接触窗133，且支撑层102的材料与位线接触窗133的材料相同，形成初始支撑层112的工艺温度大于形成位线接触窗133的工艺温度。
本公开的一些实施例中，位线接触窗133的材料为多晶硅，其中，形成位线接触窗133的材料还具有掺杂离子。位线接触窗133用于实现位线结构与有源区110之间的电性连接。
形成位线接触窗133的工艺为化学气相沉积工艺，反应气体为硅烷以及磷化氢，工艺温度为480℃～520℃，例如485℃、490℃、500℃或510℃等。 可以理解的是，由于形成上述支撑层102的工艺温度大于形成位线接触窗133的工艺温度，支撑层102的刻蚀率远远小于第一导电层113的刻蚀率。因此，使用同浓度的硝酸溶液对第一导电层113进行湿法刻蚀时，对支撑层102几乎没有影响。
参考图10以及图11，在位线接触窗133上形成填充满位线空间106的第二导电层123。
本公开的一些实施例中，在位线接触窗133与位线导电柱143之间还可以形成有扩散阻挡层153，扩散阻挡层153的材料可以为氮化钽或者氮化钛。
参考图12，回刻蚀去除部分厚度的第二导电层123，剩余第二导电层123作为位线导电柱143。
位线导电柱143的材料包括钨、金或者银等金属导电材料。
参考图13，对扩散阻挡层153进行回刻蚀。
填充位线绝缘层104之前，可以对扩散阻挡层153进行回刻蚀。
本公开的一些实施例中，采用湿法刻蚀工艺，回刻蚀去除部分厚度的第一导电层113。根据实际需要，还可以采用其他刻蚀工艺去除部分厚度的第一导电层113形成位线接触窗133，去除第一导电层113的厚度是根据存储器的位线结构中位线导电层决定的。
本公开的一些实施例中，位线导电层103包括依次堆叠的位线接触窗133以及位线导电柱143。
参考图14及图15，在位线导电层103顶部形成位线绝缘层104，且位线绝缘层104暴露出支撑层102顶部。
形成位线绝缘层104的工艺步骤包括：参考图14，在位线导电层103顶部形成位线绝缘层104；参考图15，将位线绝缘层104回刻蚀至暴露出支撑层102顶部。位线绝缘层104的主要作用是使位线结构表面绝缘。
形成的位线结构包括依次堆叠的位线导电层以及位线绝缘层，且形成的位线导电层避免了现有技术中位线结构刻蚀形成的位线导电层的形貌缺陷以及位线导电层出现过刻蚀情况。
在本公开的一些实施例中，支撑层102的材料与位线绝缘层104的材料不同。
本公开的一些实施例中，位线绝缘层104的材料包括氮化硅，在其他实施例中，位线绝缘层的材料也可以为氧化硅、氮氧化硅或者碳氮氧化硅。
参考图16，去除支撑层102，形成位于相邻位线结构之间的开口。
去除支撑层102的工艺可以为干法刻蚀，刻蚀气体可以选择六氟化硫、四氟化碳、氯气以及氩气等，或者它们的混合气体。在去除支撑层102期间，保护层105可以有效避免位线结构中的位线导电层103受到刻蚀。
在其他实施例中，去除支撑层的工艺也可以使用其他工艺。
参考图17，去除支撑层102之后，还包括：去除位于相邻位线结构之间的基底100上的保护层105。
保护层105覆盖位线结构的侧壁，且还位于相邻位线结构之间的基底100上，所以在去除支撑层102之后，还可以对相邻位线结构之间的基底100上的保护层105去除，将基底100暴露出来，在基底100上形成分立的位线结构。
本公开的一些实施例中提供的存储器制方法，先形成没有刻蚀缺陷的伪位线层，定义出位线结构的位置，再通过支撑层定义出位线结构之间区域的位置，在支撑层之间形成位线空间，并依次填充位线导电层以及位线绝缘层形成位线结构，最后去除支撑层，形成没有刻蚀缺陷的位线结构。本实施例提供的存储器制造方法，避免了在刻蚀形成位线结构时出现的位线导电层形貌缺陷问题，同时也可避免位线导电层出现过刻蚀情况，改善位线导电层的受损情况，提高位线导电层的导电能力，进一步改善存储器的电学性能。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开提供的存储器制方法，避免了在刻蚀形成位线结构时出现的位线导电层形貌缺陷问题，同时也可避免位线导电层出现过刻蚀情况，改善位线导电层的受损情况，提高位线导电层的导电能力，进一步改善存储器的电学性能。

Claims (11)

  1. 一种存储器的制作方法，包括：
    提供基底，在所述基底上形成牺牲层；
    图形化所述牺牲层，在所述基底上形成多个相互分立的伪位线层；
    形成支撑层，所述支撑层填充满相邻所述伪位线层之间的区域；
    去除所述伪位线层，形成位于相邻所述支撑层之间的位线空间；
    形成位线结构，所述位线结构填充所述位线空间，且所述位线结构包括依次堆叠的位线导电层以及位线绝缘层；
    去除所述支撑层，形成位于相邻所述位线结构之间的开口。
  2. 根据权利要求1所述的存储器的制作方法，其中，形成所述位线结构的工艺步骤包括：在所述位线空间形成所述位线导电层，且所述位线导电层顶部低于所述支撑层顶部；在所述位线导电层顶部形成所述位线绝缘层，且所述位线绝缘层暴露出所述支撑层顶部。
  3. 根据权利要求2所述的存储器的制作方法，其中，所述位线导电层包括依次堆叠的位线接触窗以及位线导电柱；形成所述位线导电层的工艺步骤包括：形成填充满所述位线空间的第一导电层；回刻蚀去除部分厚度的所述第一导电层，剩余所述第一导电层作为所述位线接触窗；在所述位线接触窗上形成填充满所述位线空间的第二导电层；回刻蚀去除部分厚度的所述第二导电层，剩余所述第二导电层作为所述位线导电柱。
  4. 根据权利要求3所述的存储器的制作方法，其中，采用湿法刻蚀工艺，回刻蚀去除部分厚度的所述第一导电层。
  5. 根据权利要求1所述的存储器的制作方法，其中，形成所述支撑层的工艺步骤包括：在相邻所述伪位线层之间形成初始支撑层，且所述初始支撑层还位于所述伪位线层顶部；对所述初始支撑层进行平坦化处理，去除高于所述伪位线层顶部的所述初始支撑层，形成所述支撑层；所述位线导电层包括位线接触窗，且所述支撑层的材料与所述位线接触窗的材料相同，形成所述初始支撑层的工艺温度大于形成所述位线接触窗的工艺温度。
  6. 根据权利要求5所述的存储器的制作方法，其中，所述支撑层与所述位线接触窗的材料为多晶硅，其中，形成所述位线接触窗的材料还具有掺 杂离子；形成所述支撑层的工艺温度为580℃～620℃，形成所述位线接触窗的工艺温度为480℃～520℃。
  7. 根据权利要求1所述的存储器的制作方法，其中，所述支撑层的材料与所述位线绝缘层的材料不同。
  8. 根据权利要求1所述的存储器的制作方法，在形成所述支撑层之前，所述制作方法还包括：形成保护层，所述保护层覆盖所述伪位线层侧壁，且还位于相邻所述伪位线层之间的所述基底上；去除所述支撑层之后，还包括：去除位于相邻所述位线结构之间的所述基底上的所述保护层。
  9. 根据权利要求8所述的存储器的制作方法，其中，形成所述保护层的工艺步骤包括：形成覆盖所述伪位线层侧壁、相邻所述伪位线层之间的所述基底上的第一氮化硅层；在所述第一氮化硅层上形成氧化硅层；在所述氧化硅层上形成第二氮化硅层。
  10. 根据权利要求1所述的存储器的制作方法，其中，所述牺牲层为单层结构。
  11. 一种存储器，其中，所述存储器根据权利要求1所述的方法形成。
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