WO2022037708A1 - Led驱动电路、显示装置与显示系统 - Google Patents

Led驱动电路、显示装置与显示系统 Download PDF

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Publication number
WO2022037708A1
WO2022037708A1 PCT/CN2021/116912 CN2021116912W WO2022037708A1 WO 2022037708 A1 WO2022037708 A1 WO 2022037708A1 CN 2021116912 W CN2021116912 W CN 2021116912W WO 2022037708 A1 WO2022037708 A1 WO 2022037708A1
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Prior art keywords
data
module
input terminal
input
output
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PCT/CN2021/116912
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English (en)
French (fr)
Inventor
张汉儒
黄志正
王景帅
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北京集创北方科技股份有限公司
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Publication of WO2022037708A1 publication Critical patent/WO2022037708A1/zh
Priority to US17/883,315 priority Critical patent/US20220375396A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Definitions

  • the present application relates to the field of LED display, and in particular, to an LED driving circuit, a display device and a display system.
  • SRAM Static Random-Access Memory
  • SRAM static random access memory
  • the existing dynamic energy saving method is to determine whether to perform dynamic energy saving by detecting whether the display data of the next frame is all 0. If the display data is 0, it means that the corresponding LED is off, that is, the corresponding LED is in a black screen state. If the data detection is all 0, it will enter the dynamic energy saving state, that is, the data channel corresponding to the LED in the black screen state will be closed, so as to realize the black screen energy saving.
  • the main purpose of the present application is to provide an LED driving circuit, a display device and a display system to solve the problem that dynamic energy saving cannot be achieved in an LED constant current driving chip without SRAM in the prior art.
  • an LED driving circuit comprising: a driving unit including a plurality of data channels; a control unit, electrically connected to the driving unit, when the control unit is in a predetermined time When it is detected in the segment that the data in all the data channels is 0, all the data channels are controlled to be in an off state, and the predetermined time period is determined according to the duration of the external input signal input to the LED driving circuit of.
  • control unit includes: a detection module, electrically connected to the drive unit, for detecting whether the data in all the data channels is 0; a counter module, electrically connected to the detection module; signal generation The module is electrically connected to the detection module and the counter module respectively, and has an output terminal, and the output terminal outputs a status signal. When the data in all the data channels is 0, the status signal is used for Control all of the data channels to be off.
  • the signal generation module has a first input terminal and a second input terminal
  • the counter module has a first input terminal and an output terminal
  • the output terminal of the detection module is respectively connected with the first input terminal of the signal generation module.
  • the input terminal is electrically connected to the first input terminal of the counter module
  • the output terminal of the counter module is electrically connected to the second input terminal of the signal generating module.
  • the drive unit further includes a reference current generation module and a current output module, and the reference current generation module is electrically connected to the signal generation module and the current output module, respectively, in all the data channels.
  • the state signal controls the reference current generating module to be in an off state.
  • the driving unit further includes: a shift register having a first input terminal, a second input terminal and an output terminal, the first input terminal is used for inputting serial data, and the second input terminal is used for inputting serial data.
  • Input the external clock signal the first inverter, the input terminal of the first inverter is used for inputting the latch enable signal; the second inverter, the input terminal of the second inverter is used for the input channel an enable signal;
  • a data latch having a first input end, a second input end, a third input end and an output end, and the data output by the output end of the data latch is data in a plurality of the data channels , the output end of the data latch is electrically connected to the input end of the detection module and the input end of the current output module, respectively, and the first input end of the data latch is electrically connected to the first inverter
  • the output terminal of the data latch is electrically connected to the output terminal of the shift register, the second input terminal of the data latch is electrically connected to the output terminal of the
  • the driving unit further includes a third inverter
  • the counter module further has a second input terminal
  • the input terminal of the third inverter is electrically connected to the output terminal of the first inverter
  • the output end of the third inverter is electrically connected with the second input end of the counter module.
  • the current output module has a first input terminal, a second input terminal and an output terminal, the first input terminal of the current output module is electrically connected to the output terminal of the data latch, and the current output terminal is electrically connected to the output terminal of the data latch.
  • the second input end of the module is electrically connected with the output end of the second inverter, and the output end of the current output module outputs multiple constant current signals.
  • the driving unit further includes a first in-phase buffer and a second in-phase buffer, an input end of the first in-phase buffer is used to input the serial data, and the first in-phase buffer is used for inputting the serial data.
  • the output terminal of the shift register is electrically connected to the first input terminal of the shift register, the input terminal of the second non-inverting buffer is used to input the external clock signal, and the output terminal of the second non-inverting buffer is connected to the The second input terminal of the shift register is electrically connected.
  • the detection module includes a NOR gate.
  • a display device including an LED driving circuit and an LED display screen, wherein the LED driving circuit is any one of the LED driving circuits described above.
  • a display system including an LED driving circuit, wherein the LED driving circuit is any one of the LED driving circuits described above.
  • the control unit detects that the data in all data channels is 0 within a predetermined period of time, that is, the driven LED is in a black screen state, and controls all the The data channel is closed to reduce the power consumption of the drive unit to achieve dynamic energy saving.
  • the above drive unit is equivalent to the LED constant current driver chip without internal SRAM, that is, the LED drive circuit of this solution has no internal SRAM LED constant current Dynamic energy saving is realized in the driver chip, and the external input signal is a signal other than the LED driver circuit, which does not occupy the resources of the LED driver circuit itself, nor the resources of the driver unit itself.
  • FIG. 1 shows a schematic diagram of an LED driving circuit according to an embodiment of the present application
  • FIG. 2 shows a schematic diagram of another LED driving circuit according to an embodiment of the present application.
  • Fig. 3 shows a schematic diagram of a control unit according to an embodiment of the present application.
  • 01 drive unit; 10, data channel; 11, reference current generation module; 12, current output module; 13, shift register; 14, first inverter; 15, second inverter; 16, data latch 17, the third inverter; 18, the first non-inverting buffer; 19, the second non-inverting buffer; 02, the control unit; 20, the detection module; 21, the counter module; 210, the first D flip-flop; 22.
  • the embodiments of the present application propose an LED driver circuit, a display device and a display device. system.
  • an LED driving circuit is provided.
  • FIG. 1 is a schematic diagram of an LED driving circuit according to an embodiment of the present application. As shown in Figure 1, the LED driver circuit includes:
  • the driving unit 01 includes a plurality of data channels 10, and the data in the data channels is used to drive the LED;
  • the control unit 02 is electrically connected to the above-mentioned driving unit 01, and when the above-mentioned control unit 02 detects that the data in all the above-mentioned data channels 10 is 0 within a predetermined period of time, it controls all the above-mentioned data channels 10 to be in a closed state,
  • the predetermined time period is obtained by counting external input signals, and the predetermined time period is determined according to the duration of the external input signal input to the LED driving circuit.
  • the control unit detects that the data in all data channels is 0 within a predetermined period of time, that is, the driven LED is in a black screen state, and controls all data channels.
  • the above drive unit is equivalent to the LED constant current driver chip without internal SRAM, that is, the LED drive circuit of this solution is in the LED constant current driver chip without internal SRAM. Dynamic energy saving is achieved, and the external input signal is a signal other than the LED driving circuit, which does not occupy the resources of the LED driving circuit itself, nor the resources of the driving unit itself.
  • the above-mentioned external input signal is a signal other than the LED driving circuit, and the external input signal is not on the LED driving circuit, not on the driving unit, that is, not on the LED constant current driving chip without internal SRAM, does not occupy the resources of the chip itself, saves chip resources.
  • the predetermined time period is determined according to the duration of the external input signal input to the LED driving circuit. Specifically, the predetermined time period can be obtained by counting the rising edge, falling edge, high level and low level of the external input signal. part.
  • the above-mentioned predetermined time period includes but is not limited to 5s, 10s, and 15s, and the predetermined time period can be adjusted according to the actual situation.
  • the above-mentioned external input signal may be a latch enable signal, an external input clock signal, a channel enable signal, and the like.
  • the LED constant current driver chip without SRAM in this article refers to a chip without SRAM inside the chip, so it is necessary to add a control unit to achieve dynamic energy saving.
  • the number of the above data channels is one of the following: 8, 16, 32, and 64.
  • the number of data channels can be set according to the actual situation.
  • an LED display screen includes 64 LEDs , the 64 LEDs can be equally divided into 8 parts, each part has 8 LEDs, and 8 drive units are set up, each drive unit includes 8 data channels, and the data in each data channel drives one LED. Drive the entire LED display.
  • the above-mentioned control unit 02 includes a detection module 20 , a counter module 21 and a signal generation module 22 .
  • the detection module 20 is electrically connected to the above-mentioned driving unit 01 for detecting all the above-mentioned Whether the data in the data channel 10 is 0;
  • the counter module 21 is electrically connected to the above-mentioned detection module 20;
  • the signal generation module 22 is electrically connected to the above-mentioned detection module 20 and the above-mentioned counter module 21 respectively, and has an output terminal, and the above-mentioned output terminal outputs the status signal PD_STAT , in the case where the data in all the above-mentioned data channels 10 is 0, the above-mentioned state signal PD_STAT is used to control all the above-mentioned data channels 10 to be in a closed state, and the detection module 20 detects that the data in all the above-mentioned data channels 10 is In the case
  • the signal generating module 22 outputs a status signal PD_STAT, and the status signal PD_STAT is used to control all the above-mentioned data channels 10 to be in an off state to achieve energy saving.
  • the signal generation module 22 has a first input terminal and a second input terminal
  • the counter module 21 has a first input terminal and an output terminal
  • the detection module 20 has a first input terminal and an output terminal.
  • the output terminal is respectively electrically connected with the first input terminal of the above-mentioned signal generation module 22 and the first input terminal of the above-mentioned counter module 21, and the output terminal of the above-mentioned counter module 21 is electrically connected with the second input terminal of the above-mentioned signal generation module 22.
  • the detection module The output signal of the output terminal of 20 is PD_RSLT.
  • the detection module 20 detects that the data in all the above-mentioned data channels 10 is 0, the counter module 21 starts timing, and all the above-mentioned data in the predetermined time period of the counter module 21 timing are counted.
  • the signal generating module 22 outputs the status signal PD_STAT, which controls all the above data.
  • Channel 10 is off for power saving.
  • the above-mentioned driving unit 01 further includes a reference current generation module 11 and a current output module 12 , the above-mentioned reference current generation module 11 is respectively connected with the above-mentioned signal generation module 22 and the above-mentioned current output module
  • the module 12 is electrically connected, and when the data in all the above-mentioned data channels 10 is 0, the above-mentioned state signal PD_STAT controls the above-mentioned reference current generation module 11 to be in an off state, and the detection module 20 detects that all the above-mentioned data channels 10 in the In the case where the data is 0, the counter module 21 starts timing, and in the case where all the data in the above-mentioned data channels 10 are still 0 within the predetermined time period counted by the counter module 21, that is, the data in the data channel 10 within the predetermined time period is: In the idle state, in order to save energy, at this time, the signal generation module 22 output
  • the above-mentioned driving unit 01 further includes a shift register 13 , a first inverter 14 , a second inverter 15 and a data latch 16 .
  • the bit register 13 has a first input terminal, a second input terminal and an output terminal.
  • the first input terminal is used to input the serial data SIN, and the second input terminal is used to input the external clock signal CLK2;
  • the input terminal is used to input the latch enable signal LE;
  • the input terminal of the second inverter 15 is used to input the channel enable signal OE;
  • the data latch 16 has a first input terminal, a second input terminal, a third input terminal and a third input terminal.
  • the data output by the output terminal of the above-mentioned data latch 16 is the data in a plurality of the above-mentioned data channels 10, and the output terminal of the above-mentioned data latch 16 is respectively connected with the input terminal of the above-mentioned detection module 20 and the above-mentioned current.
  • the input terminal of the output module 12 is electrically connected
  • the first input terminal of the above-mentioned data latch 16 is electrically connected to the output terminal of the above-mentioned first inverter 14
  • the second input terminal of the above-mentioned data latch 16 is electrically connected to the above-mentioned shift register.
  • the output terminal of 13 is electrically connected, the third input terminal of the above-mentioned data latch 16 is electrically connected to the output terminal of the above-mentioned second inverter 15, and the serial data SIN input from the first input terminal of the shift register 13 is Under the action of the input external clock signal CLK2, it is input to the data latch 16 after being acted by the shift register 13.
  • the data latch 16 latches the data output by the shift register 13 and outputs it, and the output of the data latch 16
  • the data output from the terminal is the data in a plurality of the above-mentioned data channels 10.
  • the counter module 21 starts timing, and in the case where the data in all the above-mentioned data channels 10 are still 0 within the predetermined time period counted by the counter module 21, that is, the data in the data channel 10 is in an idle state within the predetermined time period, in order to save energy,
  • the signal generating module 22 outputs the status signal PD_STAT, and the status signal PD_STAT controls the reference current generating module 11 and the current outputting module 12 to be in an off state, that is, the current outputting module 12 is controlled not to generate constant current output to achieve dynamic energy saving.
  • the above-mentioned driving unit 01 further includes a third inverter 17
  • the above-mentioned counter module 21 also has a second input terminal, the input terminal of the above-mentioned third inverter 17 It is electrically connected to the output terminal of the first inverter 14, the output terminal of the third inverter 17 is electrically connected to the second input terminal of the counter module 21, and the input terminal of the first inverter 14 is a latch.
  • the enable signal LE outputs the LE_BUF signal after being inverted twice by the first inverter 14 and the third inverter 17 , and the LE_BUF signal is also the clock signal of the counter module 21 .
  • the second input terminal of the counter module is electrically connected to the output terminal of the second inverter, that is, the channel enable signal is used as the clock signal of the counter module.
  • the second input terminal of the counter module is electrically connected to the output terminal of the second non-inverting buffer, that is, the external clock signal is used as the clock signal of the counter module.
  • the detection module 20 includes a NOR gate.
  • the NOR gate in FIG. 3 is a NOR gate with 16 inputs and one output.
  • the detection module 20 can also be For other types of logic gate circuits, it can be a logic gate circuit or a combination of multiple logic gate circuits, as long as the output is 1 when all input signals are 0, and the counter module 21 starts timing when the output is 1.
  • the signal generating module 22 includes a third non-inverting buffer 220 , the output Q1 of the signal generating module 22 is connected to the input terminal of the third non-inverting buffer 220 , and the third The output terminal of the non-inverting buffer 220 outputs the status signal PD_STAT.
  • the counter module 21 is composed of a plurality of first D flip-flops 210 connected in cascade.
  • the first D flip-flops 210 have a clock signal input end CLK, a data terminal D, the first output terminal Q, the second output terminal QN and the reset terminal RN, the second output terminal QN of each of the first D flip-flops 210 is connected to its data terminal D, and the signal input by the signal input terminal CLK is LE_BUF,
  • the signal input terminal CLK is the second input terminal of the counter module 21 in FIG. 2 .
  • the second output terminal QN of the first first D flip-flop 210 is connected to the second input terminal of the second D flip-flop 210 .
  • the clock signal input terminal CLK of the first D flip-flop 210 is connected;
  • the signal generating module 22 includes a second D flip-flop 221, and the second D flip-flop 221 has a clock signal input terminal CLK1, a data terminal D1, and a first output terminal Q1 , the second output terminal QN1 and the reset terminal RN1, the clock signal input terminal CLK1 of the second D flip-flop 221 is connected to the first output terminal Q of the first D flip-flop 210;
  • the output signal of the output terminal of the detection module 20 is PD_RSLT, and the detection
  • the output terminal of the module 20 is respectively connected with the reset terminal RN of the first D flip-flop, the reset terminal RN1 of the second D flip-flop 221 and the data terminal D1 of the signal generating module 22; In the case where the data in one data channel is not
  • the output is 1, that is, as long as the data in the 16 data channels 10 is not 0, the output of the first output terminal Q of the first D flip-flop 210 is 0, and the output of the first output terminal Q of the second D flip-flop 221 is 0. That is, the output status signal PD_STAT of the signal generation module 22 is zero. At this time, the status signal PD_STAT does not work, that is, the reference current generation module 11 and the current output module 12 are in normal working state; When the data is all 0, the output signal of the output terminal of the detection module 20 is PD_RSLT is 1, that is, the input signal of the reset terminal RN is 1.
  • the counter module 21 starts timing, within the predetermined time period of the timing of the counter module 21
  • the status signal PD_STAT is not 0.
  • the status signal PD_STAT controls the reference current generation module 11 and the current
  • the output module 12 is in an off state, that is, the current output module 12 is controlled not to generate a constant current output, so as to achieve dynamic energy saving.
  • the detection module 20 when the detection module 20 detects that the data in the 16 data channels 10 from Data0 to Data15 are all 0, the detection module 20 is triggered to start timing, and LE_BUF is the detection
  • the clock input signal of the module 20 is the input signal of the second input terminal of the counter module 21, the output terminal Q of the counter module 21 is connected to the second input terminal CLK1 of the signal generation module 22, and the output terminal of the detection module 20 is connected to the counter module 21.
  • the first input terminal RN is connected.
  • the current output module 12 has a first input terminal, a second input terminal and an output terminal, and the first input terminal of the current output module 12 is latched with the data
  • the output terminal of the inverter 16 is electrically connected
  • the second input terminal of the above-mentioned current output module 12 is electrically connected to the output terminal of the above-mentioned second inverter 15
  • the output terminal of the above-mentioned current output module 12 outputs a multi-channel constant current signal
  • the multi-channel constant current signals output by 12 are used to drive external LEDs, and when the current output module 12 is in an off state, the external LEDs are not driven to achieve energy saving.
  • the above-mentioned driving unit 01 further includes a first non-inverting buffer 18 and a second in-phase buffer 19, and the input end of the above-mentioned first non-inverting buffer 18 is used for input
  • the output terminal of the first non-inverting buffer 18 is electrically connected to the first input terminal of the shift register 13, and the input terminal of the second non-inverting buffer 19 is used to input the external clock signal CLK2
  • the output terminal of the second non-inverting buffer 19 is electrically connected to the second input terminal of the above-mentioned shift register 13.
  • the first non-inverting buffer 18 buffers the input serial data SIN, and the second non-inverting buffer 19 It acts as a buffer for the input external clock signal CLK2.
  • the above-mentioned channel enable signal OE, latch enable signal LE, serial data SIN and external clock signal CLK2 are all externally input signals, which do not occupy the drive unit 01 itself. resource of.
  • a display device which includes an LED driving circuit and an LED display screen.
  • the LED driving circuit is any of the above-mentioned LED driving circuits.
  • a control unit By arranging a control unit in the LED driving circuit, When the control unit detects that the data in all data channels is 0 within a predetermined period of time, that is, the driven LED is in a black screen state, and controls all data channels to be in a closed state, so as to control some LEDs in the LED display screen. No display (that is, a black screen state) to achieve dynamic energy saving of the LED display.
  • the above drive unit is equivalent to the LED constant current drive chip without SRAM, that is, the LED drive circuit of this solution does not have an internal SRAM LED constant current drive chip Dynamic energy saving is achieved.
  • a display system including an LED driving circuit, the LED driving circuit is any one of the above-mentioned LED driving circuits, and a control unit is provided in the LED driving circuit, and the control unit is in the LED driving circuit.
  • the control unit is in the LED driving circuit.
  • the control unit by setting a control unit in the LED drive circuit, the control unit detects that the data in all data channels is 0 within a predetermined period of time, that is, the driven LED is in a black screen state , control all data channels to be off to reduce the power consumption of the drive unit and achieve dynamic energy saving.
  • the above drive unit is equivalent to the LED constant current drive chip without internal SRAM, that is, the LED drive circuit of this solution has no internal SRAM. Dynamic energy saving is realized in the LED constant current drive chip, and the external input signal is a signal other than the LED drive circuit, which does not occupy the resources of the LED drive circuit itself, nor the resources of the drive unit itself.
  • the control unit by setting the control unit in the LED drive circuit, the control unit detects that the data in all the data channels is 0 within a predetermined period of time, that is, the driven LED is in a black screen state, Control all data channels to be off, so that some LEDs in the LED display screen are not displayed (that is, the black screen state), so as to realize the dynamic energy saving of the LED display screen.
  • the above drive unit is equivalent to the LED constant current drive without internal SRAM
  • the chip that is, the LED drive circuit of this solution realizes dynamic energy saving in the LED constant current drive chip without SRAM inside, and the external input signal is a signal other than the LED drive circuit, which does not occupy the resources of the LED drive circuit itself, nor does it occupy The resources of the drive unit itself.
  • the control unit by setting the control unit in the LED drive circuit, the control unit detects that the data in all data channels is 0 within a predetermined period of time, that is, the driven LED is in a black screen state, Control all data channels to be off to reduce the power consumption of the drive unit to achieve dynamic energy saving.
  • the above drive unit is equivalent to the LED constant current drive chip without internal SRAM, that is, the LED drive circuit of this solution has no internal SRAM LED.
  • the constant current driver chip realizes dynamic energy saving, and the external input signal is a signal other than the LED driver circuit, which does not occupy the resources of the LED driver circuit itself, nor the resources of the driver unit itself.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种LED驱动电路、显示装置与显示系统。该LED驱动电路包括：驱动单元（01），包括多个数据通道（10）；控制单元（02），与驱动单元（01）电连接，控制单元（02）在预定时间段内检测到所有的数据通道（10）中的数据为0的情况下，控制所有的数据通道（10）为关闭状态，预定时间段是根据输入LED驱动电路的外部输入信号的时长确定的。该LED驱动电路可以降低驱动单元的功耗，实现动态节能，驱动单元（01）等同于内部没有SRAM的LED恒流驱动芯片，即LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能。

Description

LED驱动电路、显示装置与显示系统 技术领域
本申请涉及LED显示领域，具体而言，涉及一种LED驱动电路、显示装置与显示系统。
背景技术
目前LED驱动芯片内部有静态随机存取存储器(Static Random-Access Memory，简称SRAM)，可以存储两帧数据，其中一帧是当前显示数据，另一帧是下一帧需要显示的数据，芯片通过接收帧同步信号实现换帧。现有的动态节能方法是通过检测下一帧显示数据是否全为0，显示数据为0表示对应的LED为关闭状态，即对应的LED为黑屏状态，决定是否进行动态节能，如果下一帧显示数据检测全为0，则进入动态节能状态，即将处于黑屏状态的LED对应的数据通道关闭，以实现黑屏节能。
然而，一些现有的LED恒流驱动芯片中，内部却没有SRAM，系统端也没有发送帧同步信号，所以，如何在此类LED恒流驱动芯片中实现动态节能成为一个需要解决的问题。
发明内容
本申请的主要目的在于提供一种LED驱动电路、显示装置与显示系统，以解决现有技术中无法在内部没有SRAM的LED恒流驱动芯片中实现动态节能的问题。
为了实现上述目的，根据本申请的一个方面，提供了一种LED驱动电路，包括：驱动单元，包括多个数据通道；控制单元，与所述驱动单元电连接，在所述控制单元在预定时间段内检测到所有的所述数据通道中的数据为0的情况下，控制所有的所述数据通道为关闭状态，所述预定时间段是根据输入所述LED驱动电路的外部输入信号的时长确定的。
可选地，所述控制单元包括：检测模块，与所述驱动单元电连接，用于检测所有的所述数据通道中的数据是否为0；计数器模块，与所述检测模块电连接；信号产生模块，分别与所述检测模块和所述计数器模块电连接，具有输出端，所述输出端输出状态信号，在所有的所述数据通道中的数据为0的情况下，所述状态信号用于控制所有的所述数据通道为关闭状态。
可选地，所述信号产生模块具有第一输入端和第二输入端，所述计数器模块具有第一输入端和输出端，所述检测模块的输出端分别与所述信号产生模块的第一输入端和所述计数器模块的第一输入端电连接，所述计数器模块的输出端与所述信号产生模块的第二输入端电连接。
可选地，所述驱动单元还包括基准电流产生模块和电流输出模块，所述基准电流产生模块分别与所述信号产生模块和所述电流输出模块电连接，在所有的所述数据通道中的数据为0的情况下，所述状态信号控制所述基准电流产生模块为关闭状态。
可选地，所述驱动单元还包括：移位寄存器，具有第一输入端、第二输入端和输出端，所述第一输入端用于输入串行数据，所述第二输入端用于输入外部时钟信号；第一反相器，所述第一反相器的输入端用于输入锁存使能信号；第二反相器，所述第二反相器的输入端用于输入通道使能信号；数据锁存器，具有第一输入端、第二输入端、第三输入端和输出端，所述数据锁存器的输出端输出的数据为多个所述数据通道中的数据，所述数据锁存器的输出端分别与所述检测模块的输入端和所述电流输出模块的输入端电连接，所述数据锁存器的第一输入端与所述第一反相器的输出端电连接，所述数据锁存器的第二输入端与所述移位寄存器的输出端电连接，所述数据锁存器的第三输入端与所述第二反相器的输出端电连接。
可选地，所述驱动单元还包括第三反相器，所述计数器模块还具有第二输入端，所述第三反相器的输入端与所述第一反相器的输出端电连接，所述第三反相器的输出端与所述计数器模块的第二输入端电连接。
可选地，所述电流输出模块具有第一输入端、第二输入端和输出端，所述电流输出模块的第一输入端与所述数据锁存器的输出端电连接，所述电流输出模块的第二输入端与所述第二反相器的输出端电连接，所述电流输出模块的输出端输出多路恒流信号。
可选地，所述驱动单元还包括第一同相缓冲器和第二同相缓冲器，所述第一同相缓冲器的输入端用于输入所述串行数据，所述第一同相缓冲器的输出端与所述移位寄存器的第一输入端电连接，所述第二同相缓冲器的输入端用于输入所述外部时钟信号，所述第二同相缓冲器的输出端与所述移位寄存器的第二输入端电连接。
可选地，所述检测模块包括或非门。
根据本申请的另一个方面，提供了一种显示装置，包括LED驱动电路和LED显示屏，所述LED驱动电路为任意一种所述的LED驱动电路。
根据本申请的再一个方面，提供了一种显示系统，包括LED驱动电路，所述LED驱动电路为任意一种所述的LED驱动电路。
应用本申请的技术方案，通过在LED驱动电路中设置控制单元，控制单元在预定时间段内检测到所有的数据通道中的数据为0的情况下，即所驱动的LED为黑屏状态，控制所有的数据通道为关闭状态，以降低驱动单元的功耗，以实现动态节能，上述驱动单元等同于内部没有SRAM的LED恒流驱动芯片，即本方案的LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能，且外部输入信号为LED驱动电路以外的信号，不占用LED驱动电路本身的资源，更不会占用驱动单元本身的资源。
附图说明
构成本申请的一部分的说明书附图用来提供对本申请的进一步理解，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1示出了根据本申请的实施例的一种LED驱动电路示意图；
图2示出了根据本申请的实施例的另一种LED驱动电路示意图；以及
图3示出了根据本申请的实施例的一种控制单元示意图。
其中，上述附图包括以下附图标记：
01、驱动单元；10、数据通道；11、基准电流产生模块；12、电流输出模块；13、移位寄存器；14、第一反相器；15、第二反相器；16、数据锁存器；17、第三反相器；18、第一同相缓冲器；19、第二同相缓冲器；02、控制单元；20、检测模块；21、计数器模块；210、第一D触发器；22、信号产生模块；220、第三同相缓冲器；221、第二D触发器。
具体实施方式
应该指出，以下详细说明都是例示性的，旨在对本申请提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本申请所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
正如背景技术所介绍的，现有技术中无法在内部没有SRAM的LED恒流驱动芯片中实现动态节能，为了解决如上技术问题，本申请的实施例提出了一种LED驱动电路、显示装置与显示系统。
根据本申请的实施例，提供了一种LED驱动电路。
图1是根据本申请实施例的一种LED驱动电路示意图。如图1所示，该LED驱动电路包括：
驱动单元01，包括多个数据通道10，数据通道中的数据用于驱动LED；
控制单元02，与上述驱动单元01电连接，在上述控制单元02在预定时间段内检测到所有的上述数据通道10中的数据为0的情况下，控制所有的上述数据通道10为关闭状态，通过对外部输入信号进行计数得到上述预定时间段，上述预定时间段是根据输入上述LED驱动电路的外部输入信号的时长确定的。
上述方案中，通过在LED驱动电路中设置控制单元，控制单元在预定时间段内检测到所有的数据通道中的数据为0的情况下，即所驱动的LED为黑屏状态，控制所有的数据通道为关闭状态，以降低驱动单元的功耗，以实现动态节能，上述驱动单元等同于内部没有SRAM的LED恒流驱动芯片，即本方案的LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能，且外部输入信号为LED驱动电路以外的信号，不占用LED驱动电路本身的资源，更不会占用驱动单元本身的资源。
具体地，上述外部输入信号为LED驱动电路以外的信号，外部输入信号不在LED驱动电路，不在驱动单元上，即不在内部没有SRAM的LED恒流驱动芯片上，不占用芯片本身的资源，节省了芯片的资源。
可选地，根据输入上述LED驱动电路的外部输入信号的时长确定上述预定时间段，具体可以通过对外部输入信号的上升沿、下降沿、高电平以及低电平进行计数，得到上述预定时间段。
具体地，上述预定时间段包括但不限于5s、10s、15s，预定时间段可以根据实际情况进行调整。
具体地，上述外部输入信号可以为锁存使能信号、外部输入时钟信号和通道使能信号等。
需要说明的是，本文中的内部没有SRAM的LED恒流驱动芯片是指，芯片内部没有SRAM的芯片，所以需要增加控制单元，以实现动态节能。
具体地，上述数据通道的个数为以下之一：8个、16个、32个、64个，当然，可以根据实际情况设置数据通道的个数，例如，一个LED显示屏中包括64个LED，可以将64个LED平均分成8份，每一份中有8个LED，设置8个驱动单元，每一个驱动单元中包括8个数据通道，每一个数据通道中的数据驱动一个LED，就实现了对整个LED显示屏的驱动。
本申请的一种实施例中，如图2所示，上述控制单元02包括检测模块20、计数器模块21和信号产生模块22，检测模块20与上述驱动单元01电连接，用于检测所有的上述数据通道10中的数据是否为0；计数器模块21与上述检测模块20电连接；信号产生模块22分别与上述检测模块20和上述计数器模块21电连接，具有输出端，上述输出端输出状态信号PD_STAT，在所有的上述数据通道10中的数据为0的情况下，上述状态信号PD_STAT用于控制所有的上述数据通道10为关闭状态，在检测模块20检测到所有的上述数据通道10中的数据为0的情况下，计数器模块21开始计时，在计数器模块21计 时的预定时间段内所有的上述数据通道10中的数据仍为0的情况下，即在预定时间段内数据通道10数据为闲置状态，为节约能源，此时，信号产生模块22输出状态信号PD_STAT，状态信号PD_STAT用于控制所有的上述数据通道10为关闭状态以实现节能。
本申请的另一种实施例中，如图2所示，上述信号产生模块22具有第一输入端和第二输入端，上述计数器模块21具有第一输入端和输出端，上述检测模块20的输出端分别与上述信号产生模块22的第一输入端和上述计数器模块21的第一输入端电连接，上述计数器模块21的输出端与上述信号产生模块22的第二输入端电连接，检测模块20的输出端的输出信号为PD_RSLT，在检测模块20检测到所有的上述数据通道10中的数据为0的情况下，计数器模块21开始计时，在计数器模块21计时的预定时间段内所有的上述数据通道10中的数据仍为0的情况下，即在预定时间段内数据通道10数据为闲置状态，为节约能源，此时，信号产生模块22输出状态信号PD_STAT，状态信号PD_STAT控制所有的上述数据通道10为关闭状态以实现节能。
本申请的再一种实施例中，如图2所示，上述驱动单元01还包括基准电流产生模块11和电流输出模块12，上述基准电流产生模块11分别与上述信号产生模块22和上述电流输出模块12电连接，在所有的上述数据通道10中的数据为0的情况下，上述状态信号PD_STAT控制上述基准电流产生模块11为关闭状态，在检测模块20检测到所有的上述数据通道10中的数据为0的情况下，计数器模块21开始计时，在计数器模块21计时的预定时间段内所有的上述数据通道10中的数据仍为0的情况下，即在预定时间段内数据通道10数据为闲置状态，为节约能源，此时，信号产生模块22输出状态信号PD_STAT，状态信号PD_STAT控制基准电流产生模块11为关闭状态，即控制基准电流产生模块11不产生基准电流，也就是控制电流输出模块12不产生恒流输出IOUT0～IOUT15，以实现动态节能。
本申请的一种实施例中，如图2和图3所示，上述驱动单元01还包括移位寄存器13、第一反相器14、第二反相器15和数据锁存器16，移位寄存器13具有第一输入端、第二输入端和输出端，上述第一输入端用于输入串行数据SIN，上述第二输入端用于输入外部时钟信号CLK2；第一反相器14的输入端用于输入锁存使能信号LE；上述第二反相器15的输入端用于输入通道使能信号OE；数据锁存器16，具有第一输入端、第二输入端、第三输入端和输出端，上述数据锁存器16的输出端输出的数据为多个上述数据通道10中的数据，上述数据锁存器16的输出端分别与上述检测模块20的输入端和上述电流输出模块12的输入端电连接，上述数据锁存器16的第一输入端与上述第一反相器14的输出端电连接，上述数据锁存器16的第二输入端与上述移位寄存器13的输出端电连接，上述数据锁存器16的第三输入端与上述第二反相器15的输出端电连接，从移位寄存器13的第一输入端输入的串行数据SIN，在输入外部时钟信号CLK2的作用下，经过移位寄存器13作用后输入至数据锁存器16，数据锁存器16将移位寄存器13输出的数据进行锁存后输出，数据锁存器16的输出端输出的数据为多个上述数据通道10中的数据，检测模块20检测到所有的上述数据通道10中的数据为0的情况下，即图3中的 Data0～Data15全部为0的情况下，计数器模块21开始计时，在计数器模块21计时的预定时间段内所有的上述数据通道10中的数据仍为0的情况下，即在预定时间段内数据通道10数据为闲置状态，为节约能源，此时，信号产生模块22输出状态信号PD_STAT，状态信号PD_STAT控制基准电流产生模块11和电流输出模块12为关闭状态，也就是控制电流输出模块12不产生恒流输出，以实现动态节能。
一种更为具体的实施例中，如图2所示，上述驱动单元01还包括第三反相器17，上述计数器模块21还具有第二输入端，上述第三反相器17的输入端与上述第一反相器14的输出端电连接，上述第三反相器17的输出端与上述计数器模块21的第二输入端电连接，第一反相器14的输入端输入的锁存使能信号LE，经过第一反相器14和第三反相器17的两次反相后输出LE_BUF信号，LE_BUF信号也就是计数器模块21的时钟信号。
一种具体的实施例中，计数器模块的第二输入端与第二反相器的输出端电连接，即通道使能信号作为计数器模块的时钟信号。
一种具体的实施例中，计数器模块的第二输入端与第二同相缓冲器的输出端电连接，即外部时钟信号作为计数器模块的时钟信号。
本申请的一种实施例中，如图3所示，上述检测模块20包括或非门，图3中的或非门为16路输入，一路输出的或非门，当然，检测模块20也可以为其他类型的逻辑门电路，可以为一个逻辑门电路或者多个逻辑门电路的组合，只要实现在所有的输入信号为0的情况输出为1即可，输出为1即计数器模块21开始计时。
本申请的一种实施例中，如图3所示，上述信号产生模块22包括第三同相缓冲器220，信号产生模块22的输出端Q1与第三同相缓冲器220的输入端连接，第三同相缓冲器220的的输出端输出状态信号PD_STAT。
本申请的一种具体的实施例中，如图2和图3所示，计数器模块21由多个第一D触发器210级联组成，第一D触发器210具有时钟信号输入端CLK、数据端D、第一输出端Q、第二输出端QN和复位端RN，每一个上述第一D触发器210的第二输出端QN与其数据端D连接，信号输入端CLK输入的信号为LE_BUF，信号输入端CLK即为图2中的计数器模块21的第二输入端，相邻的两个第一D触发器210中，第一个第一D触发器210的第二输出端QN与第二个第一D触发器210的时钟信号输入端CLK连接；信号产生模块22包括一个第二D触发器221，第二D触发器221具有时钟信号输入端CLK1、数据端D1、第一输出端Q1、第二输出端QN1和复位端RN1，第二D触发器221的时钟信号输入端CLK1与第一D触发器210的第一输出端Q连接；检测模块20的输出端的输出信号为PD_RSLT，检测模块20的输出端分别与第一D触发器的复位端RN、第二D触发器221的复位端RN1和信号产生模块22的数据端D1连接；在Data0～Data15共16个数据通道10中至少有一个数据通道中的数据不为0的情况下，检测模块20的输出端的输出信号为PD_RSLT为0，即复位端RN的输入信号为0，第一D触发器210的第一输出端Q输出为0，第二输出端QN的输出为1；同理，复位端RN1的输入信号为0， 此时，第二D触发器221的第一输出端Q输出为0，第二输出端QN的输出为1，即只要16个数据通道10中有数据不为0，第一D触发器210的第一输出端Q输出为0，第二D触发器221的第一输出端Q输出为0，即信号产生模块22输出状态信号PD_STAT为零，此时，状态信号PD_STAT不起作用，即基准电流产生模块11和电流输出模块12为正常工作状态；在Data0～Data15共16个数据通道10中的数据全部为0的情况下，检测模块20的输出端的输出信号为PD_RSLT为1，即复位端RN的输入信号为1，此时，计数器模块21开始计时，在计数器模块21计时的预定时间段内所有的上述数据通道10中的数据仍为0的情况下，在计数器模块21和检测模块20的共同作用下，状态信号PD_STAT不为0，此时，状态信号PD_STAT控制基准电流产生模块11和电流输出模块12为关闭状态，也就是控制电流输出模块12不产生恒流输出，以实现动态节能。
一种更为具体的实施中，如图3所示，检测模块20在检测到Data0～Data15共16个数据通道10中的数据全部为0的情况下，触发检测模块20开始计时，LE_BUF为检测模块20的时钟输入信号，即计数器模块21的第二输入端的输入信号，计数器模块21的输出端Q与信号产生模块22的第二输入端CLK1连接，检测模块20的输出端与计数器模块21的第一输入端RN连接。
本申请的另一种实施例中，如图2所示，上述电流输出模块12具有第一输入端、第二输入端和输出端，上述电流输出模块12的第一输入端与上述数据锁存器16的输出端电连接，上述电流输出模块12的第二输入端与上述第二反相器15的输出端电连接，上述电流输出模块12的输出端输出多路恒流信号，电流输出模块12输出的多路恒流信号用于驱动外部LED，在电流输出模块12处于关闭状态的情况下即不驱动外部LED，实现节能。
一种可选的实施例中，如图2所示，上述驱动单元01还包括第一同相缓冲器18和第二同相缓冲器19，上述第一同相缓冲器18的输入端用于输入上述串行数据SIN，上述第一同相缓冲器18的输出端与上述移位寄存器13的第一输入端电连接，上述第二同相缓冲器19的输入端用于输入上述外部时钟信号CLK2，上述第二同相缓冲器19的输出端与上述移位寄存器13的第二输入端电连接，第一同相缓冲器18对输入的串行数据SIN起到缓存的作用，第二同相缓冲器19对输入的外部时钟信号CLK2起到缓存的作用。
一种优选的实施例中，如图2所示，上述通道使能信号OE、锁存使能信号LE、串行数据SIN和外部时钟信号CLK2均为外部输入的信号，不占用驱动单元01本身的资源。
本申请的一种典型的实施例中，提供了一种显示装置，包括LED驱动电路和LED显示屏，LED驱动电路为任意一种上述的LED驱动电路，通过在LED驱动电路中设置控制单元，控制单元在预定时间段内检测到所有的数据通道中的数据为0的情况下，即所驱动的LED为黑屏状态，控制所有的数据通道为关闭状态，以实现控制LED显示屏中的部分LED不显示(即为黑屏状态)，以实现LED显示屏的动态节能，上述驱动单元 等同于内部没有SRAM的LED恒流驱动芯片，即本方案的LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能。
本申请的另一种典型的实施例中，提供了一种显示系统，包括LED驱动电路，LED驱动电路为任意一种上述的LED驱动电路，通过在LED驱动电路中设置控制单元，控制单元在预定时间段内检测到所有的数据通道中的数据为0的情况下，即所驱动的LED为黑屏状态，控制所有的数据通道为关闭状态，以降低驱动单元的功耗，以实现动态节能，上述驱动单元等同于内部没有SRAM的LED恒流驱动芯片，即本方案的LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能，且外部输入信号为LED驱动电路以外的信号，不占用LED驱动电路本身的资源，更不会占用驱动单元本身的资源。
从以上的描述中，可以看出，本申请上述的实施例实现了如下技术效果：
1)、本申请的LED驱动电路，通过在LED驱动电路中设置控制单元，控制单元在预定时间段内检测到所有的数据通道中的数据为0的情况下，即所驱动的LED为黑屏状态，控制所有的数据通道为关闭状态，以降低驱动单元的功耗，以实现动态节能，上述驱动单元等同于内部没有SRAM的LED恒流驱动芯片，即本方案的LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能，且外部输入信号为LED驱动电路以外的信号，不占用LED驱动电路本身的资源，更不会占用驱动单元本身的资源。
2)、本申请的显示装置，通过在LED驱动电路中设置控制单元，控制单元在预定时间段内检测到所有的数据通道中的数据为0的情况下，即所驱动的LED为黑屏状态，控制所有的数据通道为关闭状态，以实现控制LED显示屏中的部分LED不显示(即为黑屏状态)，以实现LED显示屏的动态节能，上述驱动单元等同于内部没有SRAM的LED恒流驱动芯片，即本方案的LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能，且外部输入信号为LED驱动电路以外的信号，不占用LED驱动电路本身的资源，更不会占用驱动单元本身的资源。
3)、本申请的显示系统，通过在LED驱动电路中设置控制单元，控制单元在预定时间段内检测到所有的数据通道中的数据为0的情况下，即所驱动的LED为黑屏状态，控制所有的数据通道为关闭状态，以降低驱动单元的功耗，以实现动态节能，上述驱动单元等同于内部没有SRAM的LED恒流驱动芯片，即本方案的LED驱动电路在内部没有SRAM的LED恒流驱动芯片中实现了动态节能，且外部输入信号为LED驱动电路以外的信号，不占用LED驱动电路本身的资源，更不会占用驱动单元本身的资源。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (11)

  1. 一种LED驱动电路，其特征在于，包括：
    驱动单元，包括多个数据通道；
    控制单元，与所述驱动单元电连接，在所述控制单元在预定时间段内检测到所有的所述数据通道中的数据为0的情况下，控制所有的所述数据通道为关闭状态，所述预定时间段是根据输入所述LED驱动电路的外部输入信号的时长确定的。
  2. 根据权利要求1所述的LED驱动电路，其特征在于，所述控制单元包括：
    检测模块，与所述驱动单元电连接，用于检测所有的所述数据通道中的数据是否为0；
    计数器模块，与所述检测模块电连接；
    信号产生模块，分别与所述检测模块和所述计数器模块电连接，具有输出端，所述输出端输出状态信号，在所有的所述数据通道中的数据为0的情况下，所述状态信号用于控制所有的所述数据通道为关闭状态。
  3. 根据权利要求2所述的LED驱动电路，其特征在于，所述信号产生模块具有第一输入端和第二输入端，所述计数器模块具有第一输入端和输出端，所述检测模块的输出端分别与所述信号产生模块的第一输入端和所述计数器模块的第一输入端电连接，所述计数器模块的输出端与所述信号产生模块的第二输入端电连接。
  4. 根据权利要求2所述的LED驱动电路，其特征在于，所述驱动单元还包括基准电流产生模块和电流输出模块，所述基准电流产生模块分别与所述信号产生模块和所述电流输出模块电连接，在所有的所述数据通道中的数据为0的情况下，所述状态信号控制所述基准电流产生模块为关闭状态。
  5. 根据权利要求4所述的LED驱动电路，其特征在于，所述驱动单元还包括：
    移位寄存器，具有第一输入端、第二输入端和输出端，所述第一输入端用于输入串行数据，所述第二输入端用于输入外部时钟信号；
    第一反相器，所述第一反相器的输入端用于输入锁存使能信号；
    第二反相器，所述第二反相器的输入端用于输入通道使能信号；
    数据锁存器，具有第一输入端、第二输入端、第三输入端和输出端，所述数据锁存器的输出端输出的数据为多个所述数据通道中的数据，所述数据锁存器的输出端分别与所述检测模块的输入端和所述电流输出模块的输入端电连接，所述数据锁存器的第一输入端与所述第一反相器的输出端电连接，所述数据锁存器的第二输入端与所述移位寄存器的输出端电连接，所述数据锁存器的第三输入端与所述第二反相器的输出端电连接。
  6. 根据权利要求5所述的LED驱动电路，其特征在于，所述驱动单元还包括第三反相器，所述计数器模块还具有第二输入端，所述第三反相器的输入端与所述第一反相器的输出端电连接，所述第三反相器的输出端与所述计数器模块的第二输入端电连接。
  7. 根据权利要求5所述的LED驱动电路，其特征在于，所述电流输出模块具有第一输入端、第二输入端和输出端，所述电流输出模块的第一输入端与所述数据锁存器的输出端电连接，所述电流输出模块的第二输入端与所述第二反相器的输出端电连接，所述电流输出模块的输出端输出多路恒流信号。
  8. 根据权利要求5所述的LED驱动电路，其特征在于，所述驱动单元还包括第一同相缓冲器和第二同相缓冲器，所述第一同相缓冲器的输入端用于输入所述串行数据，所述第一同相缓冲器的输出端与所述移位寄存器的第一输入端电连接，所述第二同相缓冲器的输入端用于输入所述外部时钟信号，所述第二同相缓冲器的输出端与所述移位寄存器的第二输入端电连接。
  9. 根据权利要求2至8中任一项所述的LED驱动电路，其特征在于，所述检测模块包括或非门。
  10. 一种显示装置，其特征在于，包括LED驱动电路，所述LED驱动电路为权利要求1至9中任一项所述的LED驱动电路。
  11. 一种显示系统，其特征在于，包括LED驱动电路和显示屏，所述LED驱动电路为权利要求1至9中任一项所述的LED驱动电路。
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