WO2022034716A1 - Circuit board, electronic device, circuit board manufacturing method, and motherboard for circuit board - Google Patents

Circuit board, electronic device, circuit board manufacturing method, and motherboard for circuit board Download PDF

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Publication number
WO2022034716A1
WO2022034716A1 PCT/JP2021/016645 JP2021016645W WO2022034716A1 WO 2022034716 A1 WO2022034716 A1 WO 2022034716A1 JP 2021016645 W JP2021016645 W JP 2021016645W WO 2022034716 A1 WO2022034716 A1 WO 2022034716A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
conductor layer
mother
insulating layer
insulating
Prior art date
Application number
PCT/JP2021/016645
Other languages
French (fr)
Japanese (ja)
Inventor
光洋 山田
崇宏 栗原
悠史 三田
Original Assignee
株式会社村田製作所
日本カーバイド工業株式会社
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Application filed by 株式会社村田製作所, 日本カーバイド工業株式会社 filed Critical 株式会社村田製作所
Publication of WO2022034716A1 publication Critical patent/WO2022034716A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • the present invention relates to a circuit board, an electronic device, a method for manufacturing a circuit board, and a mother board for a circuit board.
  • Patent Document 1 describes a piezoelectric vibration device in which a piezoelectric vibrator is mounted on the first surface of a base member.
  • the base member of the piezoelectric vibration device is provided with an external electrode continuously formed from the first surface through the side surface to the second surface, and a covering material covering at least a part of the external electrode.
  • the covering material is provided by covering the edge portion of the external electrode, which is composed of the first surface on which the piezoelectric vibrator is mounted and the side surface.
  • solder is provided on the second surface side of the base substrate.
  • the solder may get wet with the external electrodes provided on the sides and crawl up the sides.
  • the surface tension causes the base member to be misaligned, which may reduce the self-alignment property.
  • An object of the present invention is to provide a circuit board, an electronic device, a method for manufacturing a circuit board, and a mother board for a circuit board, which can improve self-alignment during mounting.
  • the circuit board on one side of the present invention is a circuit board on which electronic components are mounted, and has a first surface on which the electronic components are mounted, a second surface opposite to the first surface, and the first surface.
  • a base substrate having a side surface provided between a surface and the second surface, a first conductor layer provided on the first surface, a second conductor layer provided on the second surface, and the above. It is provided on the side surface and covers the side conductor layer that connects the first conductor layer and the second conductor layer, and at least the connection portion that is the connection point between the second conductor layer and the side conductor layer. It has an insulating layer.
  • the electronic device on one aspect of the present invention includes the circuit board, an electronic component mounted on the first surface, and a lid member that covers the electronic component and is joined to the first surface.
  • the self-alignment property can be improved at the time of mounting.
  • FIG. 1 is an exploded perspective view schematically showing a configuration example of an electronic device according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II'of FIG.
  • FIG. 3 is a plan view of the circuit board as viewed from the second surface side.
  • FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG.
  • FIG. 5 is a cross-sectional view for explaining the relationship between the conductor layer, the insulating layer, and the solder when the electronic device is mounted on the mounting substrate.
  • FIG. 6 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the first modification.
  • FIG. 1 is an exploded perspective view schematically showing a configuration example of an electronic device according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II'of FIG.
  • FIG. 3 is a plan view of the circuit board as viewed from the second surface side.
  • FIG. 4 is
  • FIG. 7 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the second modification.
  • FIG. 8 is a flowchart for explaining a method of manufacturing a circuit board included in the electronic device according to the embodiment.
  • FIG. 9 is an explanatory diagram schematically showing a manufacturing apparatus for coating and forming an insulating layer.
  • FIG. 10 is an explanatory diagram for explaining the coating process of the insulating layer.
  • FIG. 11 is a plan view schematically showing a configuration example of a mother board for a circuit board.
  • FIG. 12 is an enlarged plan view showing the area S in FIG. 11.
  • the direction parallel to the first surface 31a of the base board 31 constituting the circuit board 30 and parallel to the long side of the base board 31 is referred to as the first direction Dx.
  • the direction parallel to the first surface 31a and orthogonal to the first direction Dx is defined as the second direction Dy.
  • the direction orthogonal to the first direction Dx and the second direction Dy is defined as the third direction Dz.
  • the third direction Dz is a direction perpendicular to the first surface 31a and the second surface 31b of the base substrate 31.
  • the plan view means an arrangement relationship when viewed from one or the other of the third direction Dz.
  • the circuit board 30 includes a base substrate 31, connection electrodes 37 and 38, a convex portion 39, a conductor layer 50 (see FIG. 4) including a first conductor layer 51, wirings 55 and 56, and an insulating layer 60.
  • the base substrate 31 is a plate-shaped member having a first surface 31a, a second surface 31b opposite to the first surface 31a, and a side surface 31c between the first surface 31a and the second surface 31b.
  • the base substrate 31 has a substantially rectangular shape in a plan view, and each of the four corner portions is provided with a notch portion 31d formed in a cylindrical curved surface shape in which a part of the side surface 31c is curved in a concave shape.
  • the base substrate 31 is, for example, a ceramic substrate made of a ceramic material.
  • the shape of the corner portion of the base substrate 31 is not limited to the cylindrical curved surface shape. For example, it may be a surface (notched side surface) formed by cutting into a rectangular shape or a plane shape, or a corner portion is formed by connecting the two side surfaces 31c without providing the notch portion 31d. May be good.
  • connection electrodes 37, 38 and the convex portion 39 are provided on the first surface 31a of the base substrate 31.
  • the connection electrodes 37, 38 and the convex portion 39 are arranged apart from each other in the first direction Dx.
  • the electronic component 20 is electrically connected to the connection electrodes 37 and 38 via the conductive adhesives 35 and 36.
  • the four first conductor layers 51 are provided near each corner of the first surface 31a.
  • the first conductor layer 51a is connected to the connection electrode 38 via the wiring 55.
  • the first conductor layer 51b located diagonally to the first conductor layer 51a is connected to the connection electrode 37 via the wiring 56. That is, the first conductor layers 51a and 51b function as input / output terminals of the electronic component 20.
  • the first conductor layer 51c located at the corner between the first conductor layer 51a and the first conductor layer 51b is connected to the reference potential. Further, the first conductor layer 51 (not shown in FIG. 1) located diagonally to the first conductor layer 51c is also connected to the reference potential.
  • the reference potential is, for example, the ground potential.
  • the first conductor layer 51c and the diagonally located first conductor layer 51 are reference potential connection terminals, and are electrically connected to the lid member 32, respectively.
  • the insulating layer 60 is provided in a frame shape along the outer edge of the first surface 31a and covers the first conductor layer 51 and the wirings 55 and 56.
  • the connection electrodes 37, 38 and the convex portion 39 are provided in the region surrounded by the insulating layer 60. Further, the insulating layer 60 is also provided so as to cover the cutout portion 31d.
  • the detailed configuration of the conductor layer 50 (see FIG. 4) including the first conductor layer 51 and the insulating layer 60 will be described later.
  • FIG. 2 is a cross-sectional view taken along the line II-II'of FIG.
  • the electronic component 20 is arranged in the internal space 34 surrounded by the circuit board 30 and the lid member 32, and is mounted on the first surface 31a of the base board 31.
  • the electronic component 20 is, for example, a crystal oscillator. However, the electronic component 20 is not limited to the crystal oscillator, and may be another electronic component.
  • the electronic device 10 may be equipped with other components such as a SAW (Surface Acoustic Wave) filter, a piezoelectric vibration element, and a MEMS (Micro Electro Mechanical Systems) vibration element as the electronic component 20.
  • SAW Surface Acoustic Wave
  • MEMS Micro Electro Mechanical Systems
  • the electronic component 20 has a piezoelectric substrate 21, a first excitation electrode 22, and a second excitation electrode 23.
  • the first excitation electrode 22 is provided on one surface of the piezoelectric substrate 21.
  • the second excitation electrode 23 is provided on the other surface of the piezoelectric substrate 21.
  • the first excitation electrode 22 and the second excitation electrode 23 formed on the piezoelectric substrate 21 are arranged as a pair of electrodes so as to overlap each other in a plan view. Further, on one surface of the piezoelectric substrate 21, an extension electrode 22a electrically connected to the first excitation electrode 22 is provided. The extension electrode 22a passes through the side surface of the piezoelectric substrate 21 and is electrically connected to the connection electrode 22b provided on the other surface of the piezoelectric substrate 21. Further, on the other surface of the piezoelectric substrate 21, an extension electrode 23a electrically connected to the second excitation electrode 23 is provided. The extension electrode 23a is provided on the other surface of the piezoelectric substrate 21 and is electrically connected to a connection electrode (not shown in FIG. 2) adjacent to the connection electrode 22b. The two connection electrodes are arranged on the same end side of the piezoelectric substrate 21 and are electrically connected to the connection electrodes 37 and 38 via the conductive adhesives 35 and 36, respectively.
  • the electronic component 20 is supported by the circuit board 30 so that one end on which the connection electrode 22b is arranged becomes a fixed end. Further, the other end of the electronic component 20 is a free end.
  • a convex portion 39 is provided between the other end of the electronic component 20 and the first surface 31a. The convex portion 39 can prevent the other end of the electronic component 20 from coming into direct contact with the first surface 31a.
  • FIG. 3 is a plan view of the circuit board as viewed from the second surface side.
  • FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG.
  • the configuration of the circuit board 30 is shown by omitting the electronic component 20, the lid member 32, and the sealing material 33.
  • the circuit board 30 has a plurality of conductor layers 50a, 50b, 50c, and 50d.
  • the plurality of conductor layers 50a, 50b, 50c, and 50d are provided at positions corresponding to the notched portions 31d of the base substrate 31, respectively.
  • the plurality of conductor layers 50a, 50b, 50c, 50d have a plurality of second conductor layers 52a, 52b, 52c, 52d, respectively.
  • the second conductor layers 52a, 52b, 52c, and 52d are provided on the second surface 31b of the base substrate 31, respectively, and are provided at positions corresponding to the four notched portions 31d.
  • Each of the second conductor layers 52 has a substantially quadrangular shape, and is formed so as to cover from one end to the other end of the notch 31d in the direction along the curved surface of the notch 31d.
  • the conductor layer 50a includes a first conductor layer 51a, a second conductor layer 52a, and a side conductor layer 53a.
  • the first conductor layer 51a is provided on the first surface 31a of the base substrate 31.
  • the second conductor layer 52a is provided on the second surface 31b of the base substrate 31.
  • the first conductor layer 51a is provided at a position overlapping the second conductor layer 52a with the base substrate 31 interposed therebetween.
  • the side conductor layer 53a is provided in the side surface 31c of the base substrate 31, more specifically, the notch portion 31d formed in the corner portion of the side surface 31c of the base substrate 31, and the first conductor layer 51a and the second conductor layer are provided. Connect with 52a.
  • the conductor layer 50b is continuously formed from the first surface 31a of the base substrate 31 to the second surface 31b through the side surface 31c (notch portion 31d). Further, the side conductor layer 53b is provided so as to cover the entire notch portion 31d. However, the present invention is not limited to this, and the side conductor layer 53b may be provided so as to cover a part of the notch portion 31d.
  • the insulating layer 60 has a first insulating layer 61, a protruding portion 62, a side insulating layer 63, and a second insulating layer 67.
  • the first insulating layer 61 is provided on the first surface 31a of the base substrate 31 so as to cover the first conductor layer 51. As described above, the first insulating layer 61 is formed in a frame shape along the outer edge of the first surface 31a of the base substrate 31 (see FIG. 1). However, the present invention is not limited to this, and the first insulating layer 61 may be arranged separately for each of the four conductor layers 50.
  • the protruding portion 62 is provided so as to cover the connecting portion 54, which is a connecting portion between the second conductor layer 52 and the side conductor layer 53.
  • the protrusion 62 is provided so as to cover at least a part of the second conductor layer 52, and is formed so as to project from the surface of the second conductor layer 52 in the third direction Dz. In other words, a step is formed between the protrusion 62 and the second conductor layer 52.
  • the insulating layer 60 is provided in each of the four notches 31d, and the protruding portion 62 is provided so as to cover the connecting portions 54a, 54b, 54c, 54d.
  • the connecting portion 54 is continuously formed from one end to the other along the curved surface of the notch 31d.
  • the protrusion 62 is provided so as to cover the entire connection portion 54, and is continuously formed from one end portion of the connection portion 54 to the other end portion.
  • the connecting portion 54 and the protruding portion 62 are provided in an arc shape along the curved surface of the cutout portion 31d.
  • the connection portion 54 is not limited to the configuration formed in the entire region of the notch portion 31d, and may be provided in a part of the notch portion 31d. Also in this case, the protrusion 62 is provided so as to cover the entire area of the connection portion 54.
  • the side insulating layer 63 is provided so as to cover the side conductor layer 53b, and connects the first insulating layer 61 and the protruding portion 62. That is, each of the insulating layers 60 is continuously formed from the first surface 31a of the base substrate 31 to the second surface 31b through the side surface 31c (notch portion 31d). Further, the side insulating layer 63 is provided so as to cover the entire side conductor layer 53b.
  • the present invention is not limited to this, and the side insulating layer 63 may be provided so as to cover at least the side conductor layer 53b on the second surface 31b side, and the first insulating layer 61, the side insulating layer 63, and the protruding portion 62 may be provided. And may be provided apart from each other.
  • the second insulating layer 67 is provided so as to cover the first insulating layer 61.
  • the second insulating layer 67 may be provided in the same shape as the first insulating layer 61 in a plan view, or may have a different shape from the first insulating layer 61. Further, the second insulating layer 67 may not be provided.
  • the material of the conductor layer 50 is made of a metal such as silver or a silver-palladium alloy, molybdenum, or tungsten.
  • the insulating layer 60 is made of a glass material or a resin material.
  • the glass material for example, low melting point glass (for example, lead boric acid type, tin phosphoric acid type, etc.) and glass that dries at low temperature (for example, alumina, silica, etc.) can be used.
  • the adhesion strength between the insulating layer 60 and the base substrate 31 such as ceramic can be improved.
  • the resin material may be, for example, a thermosetting resin or a material containing an epoxy resin as a main component.
  • FIG. 5 is a cross-sectional view for explaining the relationship between the conductor layer, the insulating layer, and the solder when the electronic device is mounted on the mounting board.
  • the electronic device 10 is mounted on the mounting board 200 by, for example, a reflow process.
  • the second surface 31b of the circuit board 30 is arranged so as to face the mounting board 200.
  • the portion of the second conductor layer 52 where the protrusion 62 is not provided is joined to the mounting electrode 201 of the mounting substrate 200 via the solder 202.
  • the insulating layer 60 made of a glass material or a resin material has a lower wettability of the solder 202 than the conductor layer 50. As a result, it is possible to suppress the creeping up of the solder 202 to the side conductor layer 53. More preferably, in the present embodiment, the projecting portion 62 is provided so as to cover the connecting portion 54, and the projecting portion 62 is provided so as to project from the second conductor layer 52 to form a step. As a result, the movement of the solder 202 is blocked by the protrusion 62, and the solder 202 can be prevented from crawling up to the side conductor layer 53.
  • the movement of the solder 202 is restricted by the protrusion 62, and the solder 202 is in contact with only the second conductor layer 52 provided on the second surface 31b of the conductor layer 50, and is not the side conductor layer 53. It is non-contact.
  • the protruding portion 62 is not formed, and the solder 202 is not provided on the side conductor layer 53 as compared with the case where the solder 202 is provided so as to cover the connecting portion 54 and the side conductor layer 53, so that the surface of the solder 202 is formed.
  • the force acting in the horizontal direction is suppressed by the tension, and the self-alignment property at the time of mounting can be improved.
  • the protruding portion 62 is provided so as to cover the entire connecting portion 54, and the protruding portion 62 is formed in each of the four cutout portions 31d.
  • the protrusions 62 provided on each of the plurality of second conductor layers 52 are formed so as to extend in different directions. That is, each of the plurality of second conductor layers 52 can improve the self-alignment property at the time of mounting such as a reflow process.
  • the conductor layer 50 and the lid member 32 are electrically connected via the solder 202 as compared with the case where the solder 202 creeps up to the first conductor layer 51 side. It can be suppressed. More specifically, it is suppressed that the conductor layers 50a and 50b functioning as input / output terminals of the electronic component 20 are short-circuited to the reference potential (for example, the ground potential) via the solder 202 and the lid member 32.
  • the reference potential for example, the ground potential
  • FIG. 6 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the first modification.
  • the first modification unlike the above-described embodiment, a configuration in which the notch portion 31Ad is formed linearly will be described.
  • the cutout portion 31Ad has a configuration in which a part of the side surface 31Ac is linearly cut at each of the corner portions of the base substrate 31A. It has become.
  • the notch 31Ad connects two adjacent side surfaces 31Ac in a straight line in a plan view.
  • the base substrate 31A has an octagonal shape when viewed from the second surface 31Ab side.
  • the connecting portion 54 is also provided linearly like the notch portion 31Ad, and the protruding portion 62 is provided so as to cover the linear connecting portion 54.
  • the protruding portion 62 is also formed in a straight line along the connecting portion 54.
  • the connecting portion 54 and the protruding portion 62 are formed linearly along each notch portion 31Ad, and the configuration can be simplified as compared with the above-described embodiment. Therefore, the protruding portion 62 can be reliably formed so as to cover the connecting portion 54.
  • FIG. 7 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the second modification.
  • the second modification unlike the above-described embodiment and the first modification, a configuration in which the notch portions 31d and 31Ad are not provided in the base substrate 31B will be described.
  • the base substrate 31B has a rectangular shape in a plan view, and adjacent side surfaces 31Bc are connected to each of the four corner portions. It is formed.
  • the connecting portion 54 is provided along the side surface 31Bc of the long side, and is arranged apart from one end side and the other end side of the side surface 31Bc of the long side. That is, the side conductor layer 53 and the second conductor layer 52 forming the connecting portion 54 are arranged apart from one end side and the other end side of the side surface 31Bc on the long side.
  • the protruding portion 62 of the insulating layer 60 is provided so as to cover the connecting portion 54.
  • the two second conductor layers 52 are arranged between the two protrusions 62 adjacent to each other in the second direction Dy.
  • the electronic device 10B and the circuit board 30B can improve the self-alignment property at least in the second direction Dy at the time of mounting.
  • the step of forming the cutout portions 31d and 31Ad can be omitted, the manufacturing step of the circuit board 30B can be simplified.
  • the second conductor layer 52 is not limited to a substantially quadrangular shape, and may have another shape such as a polygonal shape or a circular shape.
  • the plurality of second conductor layers 52 have similar shapes, but are not limited to these, and may have different shapes.
  • the number of conductor layers 50 provided on one circuit board 30 is not limited to four, and may be three or five or more.
  • the protrusion 62 (insulating layer 60) is preferably provided on all conductor layers 50. However, there may be a plurality of conductor layers in which the protrusion 62 is not formed.
  • the conductor layer 50 and the protruding portion 62 (insulating layer 60) are not limited to the corner portions of the base substrate 31, and may be provided at the central portion of the side surface 31c.
  • the circuit board 30 of the present embodiment is a circuit board 30 on which the electronic component 20 is mounted, and is on the first surface 31a on which the electronic component 20 is mounted and on the side opposite to the first surface 31a.
  • a base substrate 31 having a second surface 31b, a side surface 31c provided between the first surface 31a and the second surface 31b, a first conductor layer 51 provided on the first surface 31a, and a second surface.
  • a second conductor layer 52 provided on 31b, a side conductor layer 53 provided on the side surface 31c and connecting the first conductor layer 51 and the second conductor layer 52, and at least the second conductor layer 52 and the side conductor layer 53.
  • It has an insulating layer 60 provided so as to cover the connection portion 54 which is a connection point with the above.
  • the insulating layer 60 provided so as to cover the connecting portion 54 functions as a stopper for suppressing the creeping up of the solder 202.
  • the solder 202 it is possible to prevent the solder 202 from being provided so as to cover the side conductor layer 53, so that the self-alignment property at the time of mounting can be improved.
  • the insulating layer 60 includes a side insulating layer 63 that covers the side conductor layer 53 and a protruding portion 62 that is provided so as to cover the connecting portion 54, and the protruding portion 62 is a second conductor layer 52. It is provided so as to protrude from.
  • the movement of the solder 202 is restricted by the step formed by the second conductor layer 52 and the protrusion 62, and the creeping up of the solder 202 to the side conductor layer 53 can be effectively suppressed. ..
  • the base substrate 31 has four corners in a plan view from the direction perpendicular to the second surface 31b, and the first conductor layer 51, the second conductor layer 52, the side conductor layer 53, and the like.
  • the insulating layer 60 is provided at each of the four corners.
  • the creeping up of the solder 202 is suppressed at each of the four corners, and the self-alignment property in four directions can be improved.
  • a cutout portion 31d having a part of a cylindrical curved surface curved in a concave shape is provided at a corner portion, and the insulating layer 60 is formed along the cylindrical curved surface of the cutout portion 31d in a plan view. It will be provided.
  • the configuration of the notch portion 31Ad can be simplified.
  • the insulating layer 60 is formed of a glass material or a resin material.
  • the insulating layer 60 made of the glass material or the resin material has a lower wettability of the solder 202 than the conductor layer 50, it is possible to suppress the creeping up of the solder 202 to the side conductor layer 53.
  • the electronic device 10 of the present embodiment includes the circuit board 30, the electronic component 20 mounted on the first surface 31a, the lid member 32 covering the electronic component 20 and joined to the first surface 31a.
  • the electronic component 20 is a crystal oscillator.
  • FIG. 8 is a flowchart for explaining a method of manufacturing a circuit board included in the electronic device according to the embodiment.
  • FIG. 9 is an explanatory diagram schematically showing a manufacturing apparatus for coating and forming an insulating layer.
  • FIG. 10 is an explanatory diagram for explaining the coating process of the insulating layer.
  • FIG. 11 is a plan view schematically showing a configuration example of a mother board for a circuit board.
  • FIG. 12 is an enlarged plan view showing the area S in FIG. 11.
  • a green sheet is coated and formed by, for example, a doctor blade or a lip coater (step ST11).
  • the green sheet contains a ceramic powder containing aluminum oxide (Al 2 O 3 ) as a main component, an organic binder and other additives.
  • a plurality of through holes 82 are formed on the green sheet (step ST12).
  • the plurality of through holes 82 can be formed by punching, drilling, laser machining, or the like. As shown in FIG. 12, the plurality of through holes 82 are arranged in a grid pattern so that the centers are located on the dividing lines L1 and L2.
  • the green sheet is fired at a predetermined temperature (step ST13).
  • the base mother substrate 81 which is the substrate of the mother substrate 80 for the circuit board, is formed.
  • the base mother substrate 81 may be a single-layer ceramic substrate or a laminated ceramic substrate on which a plurality of green sheets are laminated.
  • the order of steps ST12 and ST13 may be reversed. That is, after firing a green sheet that has not been perforated, a plurality of through holes 82 may be formed on the fired ceramic substrate by drilling or laser processing.
  • the conductor layer 50 is formed on the surface of the base mother substrate 81 and the inner wall of the through hole 82 (step ST14).
  • the conductor layer 50 is formed in each of the plurality of circuit regions 83 (see FIGS. 11 and 12). Further, as shown in FIG. 10, the conductor layer 50 is formed over the first surface 81a of the base mother substrate 81 of the circuit board mother substrate 80, the inner wall of the through hole 82, and the second surface 81b of the base mother substrate 81. Will be done. Further, as shown in FIG. 12, connection electrodes 37 and 38 and wirings 55 and 56 (see FIG. 1) are also formed in the same process as the conductor layer 50.
  • connection electrodes 37, 38 and the wirings 55, 56 are formed in each of the plurality of circuit regions 83 on the first surface 81a of the base mother board 81 of the circuit board mother board 80.
  • the conductor layer 50, the connection electrodes 37, 38, and the wirings 55, 56 can be formed by applying a conductive paste containing a conductive material by screen printing.
  • the conductor layer 50 may be formed by vapor deposition, sputtering, plating or the like.
  • a circuit board mother substrate 80 having a plurality of circuit areas 83 and a plurality of through holes 82 shown in FIGS. 11 and 12 can be prepared.
  • the circuit board area 83 is an area to be formed as the circuit board 30 when the circuit board mother board 80 is divided into individual pieces along the division lines L1 and L2.
  • the insulating layer 60 is formed on the base mother substrate 81 on which the conductor layer 50 is formed (step ST15). Specifically, as shown in FIG. 9, the circuit board mother substrate 80 having a plurality of through holes 82 is placed on the printing jig 210.
  • the manufacturing apparatus can use the printing mask 212 and the squeegee 213 to apply and form the insulating paste 85 containing the insulating material on the first surface 81a of the circuit board mother substrate 80 (base mother substrate 81).
  • the printing jig 210 is provided with a space in a region overlapping the plurality of through holes 82, and the suction blower 211 is provided so that the insulating paste 85 can be sucked from the second surface 81b side.
  • the printing apparatus covers the openings on the first surface 81a side of the plurality of through holes 82 and coats and forms the insulating paste 85 (step ST15-1). ..
  • the manufacturing apparatus forms the insulating paste 85 in a grid pattern along the dividing lines L1 and L2 in the same printing process (see FIG. 12).
  • the suction blower 211 sucks the insulating paste 85 formed by covering the opening on the first surface 81a side of the through hole 82 from the second surface 81b side (step ST15-2).
  • the insulating paste 85 is pulled toward the second surface 81b and is provided so as to cover the inner wall of the through hole 82.
  • the insulating paste 85 provided on the inner wall of the through hole 82 is formed thinly at the ends on the first surface 81a side and the second surface 81b side, and is formed thicker at the central portion in the thickness direction.
  • the insulating paste 85 provided on the inner wall of the through hole 82 becomes semi-dry at the ends on the first surface 81a side and the second surface 81b side, and the fluidity is low.
  • the insulating paste 85 maintains a wet state and has higher fluidity than both ends in the thickness direction.
  • the suction blower 211 further sucks the insulating paste 85 from the second surface 81b side of the base mother substrate 81 (step ST15-3).
  • the suction force in the second suction step of step ST15-3 is larger than the suction force in the first suction step, and the suction time in the second suction step is shorter than that in the first suction step.
  • the insulating paste 85 provided on the inner wall of the through hole 82 the portion maintaining the wet state is pulled toward the second surface 81b, and the opening edge portion of the through hole 82 on the second surface 81b side is pulled. cover. That is, the insulating paste 85 is provided so as to cover the connecting portion 54 between the side conductor layer 53 and the second conductor layer 52. Then, the insulating paste 85 is fired or dried to form the insulating layer 60 including the protrusion 62.
  • the protruding portion 62 is formed by a two-step suction step to control the fluidity of the insulating paste 85 and to satisfactorily connect the connecting portion 54.
  • the protrusion 62 can be formed so as to cover it. Further, since the insulating paste 85 can be applied and formed on the first surface 81a and the protruding portion 62 can be formed on the second surface 81b side by the suction step, the step of double-sided printing of the insulating paste 85 can be omitted.
  • the portion 62 can be formed.
  • the mother substrate 80 for a circuit board can be prepared by the above steps.
  • an insulating layer 60 is formed in each of the plurality of circuit areas 83 so as to cover the inner walls of the plurality of through holes 82, and each of the plurality of through holes 82 has an opening on the second surface 81b side.
  • a protruding portion 62 is provided to cover the edge portion.
  • the circuit board mother board 80 of the present embodiment shown in FIGS. 10 to 12 is a circuit board mother board 80 having a plurality of circuit areas 83 and a plurality of through holes 82, and is a plurality of circuit board mother boards 80.
  • the first conductor layer 51 provided on the first surface 81a of the circuit board mother board 80 (base mother board 81) and the second of the circuit board mother board 80 (base mother board 81). It has a second conductor layer 52 provided on the surface 81b, and a side conductor layer 53 provided on the inner wall of the through hole 82 and connecting the first conductor layer 51 and the second conductor layer 52.
  • the mother substrate 80 for a circuit board has at least an insulating layer 60 (projecting portion 62) provided so as to cover the connecting portion 54 which is a connecting portion between the second conductor layer 52 and the side conductor layer 53.
  • each circuit board 30 can be formed by dividing the circuit board mother board 80 into individual pieces along the dividing lines L1 and L2 (step ST16).
  • the dividing lines L1 and L2 are virtual lines indicating positions for dividing the circuit board mother substrate 80 for each circuit area 83, and can be cut along the dividing lines L1 and L2 by a laser device or a dicer. Alternatively, a dividing groove may be provided in advance along the dividing lines L1 and L2.
  • the dividing lines L1 and L2 are formed along a plurality of through holes 82.
  • the circuit board mother substrate 80 is divided along the plurality of through holes 82.
  • a cutout portion 31d having a cylindrical curved surface curved in a concave shape is formed at the corner portion of each circuit board 30.
  • the base mother substrate 81 which is the substrate of the mother substrate 80 for a circuit board, is not limited to the ceramic substrate, and may be a resin substrate.
  • the insulating paste 85 is not limited to screen printing, and may be applied and formed by other methods such as inkjet printing.

Abstract

This circuit board has mounted thereon an electronic component and is provided with: a base board having a first surface on which the electronic component is mounted, a second surface opposite to the first surface, and a side surface provided between the first surface and the second surface; a first conduction layer provided on the first surface; a second conduction layer provided on the second surface; a side-surface conduction layer which is provided on the side surface and through which the first conduction layer and the second conduction layer are interconnected; and an insulation layer provided so as to cover at least a connection section at which the second conduction layer and the side-surface conduction layer are interconnected.

Description

回路基板、電子デバイス、回路基板の製造方法及び回路基板用母基板Manufacturing method of circuit board, electronic device, circuit board and mother board for circuit board
　本発明は、回路基板、電子デバイス、回路基板の製造方法及び回路基板用母基板に関する。 The present invention relates to a circuit board, an electronic device, a method for manufacturing a circuit board, and a mother board for a circuit board.
　特許文献１には、ベース部材の第１面に圧電振動子が搭載された圧電振動デバイスが記載されている。圧電振動デバイスのベース部材には、第１面から側面を通って第２面に亘って連続して形成された外部電極と、外部電極の少なくとも一部を覆う被覆材とが設けられている。被覆材は、外部電極のうち、圧電振動子が搭載される第１面と、側面とによって構成された縁部を被覆して設けられる。 Patent Document 1 describes a piezoelectric vibration device in which a piezoelectric vibrator is mounted on the first surface of a base member. The base member of the piezoelectric vibration device is provided with an external electrode continuously formed from the first surface through the side surface to the second surface, and a covering material covering at least a part of the external electrode. The covering material is provided by covering the edge portion of the external electrode, which is composed of the first surface on which the piezoelectric vibrator is mounted and the side surface.
国際公開第２０１６／１３２７６７号International Publication No. 2016/132767
　特許文献１に記載の圧電振動デバイスを実装する際に、ベース基板の第２面側にはんだが設けられる。はんだは、側面に設けられた外部電極に濡れて側面を這い上がる可能性がある。側面にはんだが這い上がると、表面張力によりベース部材の位置ずれが生じ、セルフアライメント性が低下する可能性がある。 When mounting the piezoelectric vibration device described in Patent Document 1, solder is provided on the second surface side of the base substrate. The solder may get wet with the external electrodes provided on the sides and crawl up the sides. When the solder crawls up to the side surface, the surface tension causes the base member to be misaligned, which may reduce the self-alignment property.
　本発明は、実装の際にセルフアライメント性を向上させることができる回路基板、電子デバイス、回路基板の製造方法及び回路基板用母基板を提供することを目的とする。 An object of the present invention is to provide a circuit board, an electronic device, a method for manufacturing a circuit board, and a mother board for a circuit board, which can improve self-alignment during mounting.
　本発明の一側面の回路基板は、電子部品が搭載される回路基板であって、前記電子部品が搭載される第１面と、前記第１面と反対側の第２面と、前記第１面と前記第２面との間に設けられた側面とを有するベース基板と、前記第１面に設けられた第１導体層と、前記第２面に設けられた第２導体層と、前記側面に設けられ、前記第１導体層と前記第２導体層とを接続する側面導体層と、少なくとも前記第２導体層と前記側面導体層との接続箇所である接続部を覆って設けられた絶縁層と、を有する。 The circuit board on one side of the present invention is a circuit board on which electronic components are mounted, and has a first surface on which the electronic components are mounted, a second surface opposite to the first surface, and the first surface. A base substrate having a side surface provided between a surface and the second surface, a first conductor layer provided on the first surface, a second conductor layer provided on the second surface, and the above. It is provided on the side surface and covers the side conductor layer that connects the first conductor layer and the second conductor layer, and at least the connection portion that is the connection point between the second conductor layer and the side conductor layer. It has an insulating layer.
　本発明の一側面の電子デバイスは、上記の回路基板と、前記第１面に搭載された電子部品と、前記電子部品を覆って前記第１面に接合されたリッド部材と、を有する。 The electronic device on one aspect of the present invention includes the circuit board, an electronic component mounted on the first surface, and a lid member that covers the electronic component and is joined to the first surface.
　本発明の一側面の回路基板の製造方法は、複数の回路領域及び複数のスルーホールを有する回路基板用母基板を準備する工程と、複数の前記回路領域のそれぞれに、前記回路基板用母基板の第１面、前記スルーホールの内壁及び前記回路基板用母基板の第２面に亘って導体層を形成する工程と、絶縁材料を含む絶縁性ペーストを、複数の前記スルーホールの前記第１面側の開口を覆って塗布形成し、前記第１面側の開口を覆う前記絶縁性ペーストを前記回路基板用母基板の前記第２面側から吸引する第１吸引工程と、前記第１吸引工程の後、前記絶縁性ペーストを前記回路基板用母基板の前記第２面側からさらに吸引する第２吸引工程と、を有する。 The method for manufacturing a circuit board on one aspect of the present invention includes a step of preparing a mother board for a circuit board having a plurality of circuit regions and a plurality of through holes, and a mother board for the circuit board in each of the plurality of the circuit areas. The step of forming a conductor layer over the first surface of the through hole, the inner wall of the through hole and the second surface of the mother substrate for a circuit board, and the insulating paste containing an insulating material are applied to the first surface of the plurality of the through holes. The first suction step of covering the opening on the surface side to form the coating and sucking the insulating paste covering the opening on the first surface side from the second surface side of the mother substrate for the circuit board, and the first suction. After the step, there is a second suction step of further sucking the insulating paste from the second surface side of the mother substrate for a circuit board.
　本発明の一側面の回路基板用母基板は、複数の回路領域及び複数のスルーホールを有する回路基板用母基板であって、複数の前記回路領域のそれぞれにおいて、前記回路基板用母基板の第１面に設けられた第１導体層と、前記回路基板用母基板の第２面に設けられた第２導体層と、前記スルーホールの内壁に設けられ、前記第１導体層と前記第２導体層とを接続する側面導体層と、少なくとも前記第２導体層と前記側面導体層との接続箇所である接続部を覆って設けられた絶縁層と、を有する。 The mother board for a circuit board on one side of the present invention is a mother board for a circuit board having a plurality of circuit areas and a plurality of through holes, and in each of the plurality of the circuit areas, the mother board for the circuit board is the first. The first conductor layer provided on one surface, the second conductor layer provided on the second surface of the mother substrate for a circuit board, and the first conductor layer and the second conductor layer provided on the inner wall of the through hole. It has a side conductor layer connecting the conductor layer, and at least an insulating layer provided so as to cover a connecting portion which is a connection point between the second conductor layer and the side conductor layer.
　本発明の回路基板、電子デバイス、回路基板の製造方法及び回路基板用母基板によれば、実装の際にセルフアライメント性を向上させることができる。 According to the circuit board, the electronic device, the method for manufacturing the circuit board, and the mother board for the circuit board of the present invention, the self-alignment property can be improved at the time of mounting.
図１は、実施形態に係る電子デバイスの構成例を模式的に示す分解斜視図である。FIG. 1 is an exploded perspective view schematically showing a configuration example of an electronic device according to an embodiment. 図２は、図１のＩＩ－ＩＩ’断面図である。FIG. 2 is a cross-sectional view taken along the line II-II'of FIG. 図３は、回路基板を第２面側から見た平面図である。FIG. 3 is a plan view of the circuit board as viewed from the second surface side. 図４は、図３のＩＶ－ＩＶ’断面図である。FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG. 図５は、電子デバイスが実装基板に実装された場合の、導体層、絶縁層及びはんだの関係を説明するための断面図である。FIG. 5 is a cross-sectional view for explaining the relationship between the conductor layer, the insulating layer, and the solder when the electronic device is mounted on the mounting substrate. 図６は、第１変形例に係る電子デバイスにおいて、ベース基板を第２面側から見た平面図である。FIG. 6 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the first modification. 図７は、第２変形例に係る電子デバイスにおいて、ベース基板を第２面側から見た平面図である。FIG. 7 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the second modification. 図８は、実施形態に係る電子デバイスが有する回路基板の製造方法を説明するためのフローチャート図である。FIG. 8 is a flowchart for explaining a method of manufacturing a circuit board included in the electronic device according to the embodiment. 図９は、絶縁層を塗布形成するための製造装置を模式的に示す説明図である。FIG. 9 is an explanatory diagram schematically showing a manufacturing apparatus for coating and forming an insulating layer. 図１０は、絶縁層の塗布工程を説明するための説明図である。FIG. 10 is an explanatory diagram for explaining the coating process of the insulating layer. 図１１は、回路基板用母基板の構成例を模式的に示す平面図である。FIG. 11 is a plan view schematically showing a configuration example of a mother board for a circuit board. 図１２は、図１１の領域Ｓを拡大して示す平面図である。FIG. 12 is an enlarged plan view showing the area S in FIG. 11.
　以下に、本発明の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態により本発明が限定されるものではない。各実施の形態は例示であり、異なる実施の形態で示した構成の部分的な置換又は組み合わせが可能であることは言うまでもない。第２実施形態以降では第１実施形態と共通の事柄についての記述を省略し、異なる点についてのみ説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to this embodiment. It is needless to say that each embodiment is an example, and partial replacement or combination of the configurations shown in different embodiments is possible. In the second and subsequent embodiments, the description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same action and effect due to the same configuration will not be mentioned sequentially for each embodiment.
（実施形態）
　図１は、実施形態に係る電子デバイスの構成例を模式的に示す分解斜視図である。図１に示すように、電子デバイス１０は、電子部品２０と、回路基板３０と、リッド部材３２と、を有する。回路基板３０及びリッド部材３２は、電子部品２０を収容するためのケース又はパッケージである。回路基板３０及びリッド部材３２は、平面視で略同じ寸法及び形状を有しており、例えば、略矩形状である。 (Embodiment)
FIG. 1 is an exploded perspective view schematically showing a configuration example of an electronic device according to an embodiment. As shown in FIG. 1, the electronic device 10 includes an electronic component 20, a circuit board 30, and a lid member 32. The circuit board 30 and the lid member 32 are cases or packages for accommodating the electronic components 20. The circuit board 30 and the lid member 32 have substantially the same dimensions and shapes in a plan view, and are, for example, substantially rectangular.
　以下の説明では、回路基板３０を構成するベース基板３１の第１面３１ａに平行な方向であって、ベース基板３１の長辺に平行な方向を第１方向Ｄｘとする。第１面３１ａに平行な方向であって、第１方向Ｄｘと直交する方向を第２方向Ｄｙとする。第１方向Ｄｘ及び第２方向Ｄｙと直交する方向を第３方向Ｄｚとする。第３方向Ｄｚは、ベース基板３１の第１面３１ａ及び第２面３１ｂに垂直な方向である。また、平面視とは、第３方向Ｄｚの一方又は他方から見た場合の配置関係をいう。 In the following description, the direction parallel to the first surface 31a of the base board 31 constituting the circuit board 30 and parallel to the long side of the base board 31 is referred to as the first direction Dx. The direction parallel to the first surface 31a and orthogonal to the first direction Dx is defined as the second direction Dy. The direction orthogonal to the first direction Dx and the second direction Dy is defined as the third direction Dz. The third direction Dz is a direction perpendicular to the first surface 31a and the second surface 31b of the base substrate 31. Further, the plan view means an arrangement relationship when viewed from one or the other of the third direction Dz.
　回路基板３０は、ベース基板３１と、接続電極３７、３８と、凸部３９と、第１導体層５１を含む導体層５０（図４参照）と、配線５５、５６と、絶縁層６０と、を含む。ベース基板３１は、第１面３１ａと、第１面３１ａと反対側の第２面３１ｂと、第１面３１ａと第２面３１ｂとの間の側面３１ｃとを有する板状の部材である。ベース基板３１は、平面視で略矩形状であり、４つのコーナー部のそれぞれは、側面３１ｃの一部が凹状に湾曲する円筒曲面状に形成された切り欠き部３１ｄが設けられる。ベース基板３１は、例えばセラミック材料で形成されたセラミック基板である。なお、ベース基板３１のコーナー部の形状は、円筒曲面状に限定されない。例えば矩形状あるいは平面状に切断して形成された面（切り欠き側面）であってもよいし、あるいは、切り欠き部３１ｄが設けられず２つの側面３１ｃが接続されてコーナー部が形成されてもよい。 The circuit board 30 includes a base substrate 31, connection electrodes 37 and 38, a convex portion 39, a conductor layer 50 (see FIG. 4) including a first conductor layer 51, wirings 55 and 56, and an insulating layer 60. including. The base substrate 31 is a plate-shaped member having a first surface 31a, a second surface 31b opposite to the first surface 31a, and a side surface 31c between the first surface 31a and the second surface 31b. The base substrate 31 has a substantially rectangular shape in a plan view, and each of the four corner portions is provided with a notch portion 31d formed in a cylindrical curved surface shape in which a part of the side surface 31c is curved in a concave shape. The base substrate 31 is, for example, a ceramic substrate made of a ceramic material. The shape of the corner portion of the base substrate 31 is not limited to the cylindrical curved surface shape. For example, it may be a surface (notched side surface) formed by cutting into a rectangular shape or a plane shape, or a corner portion is formed by connecting the two side surfaces 31c without providing the notch portion 31d. May be good.
　接続電極３７、３８及び凸部３９は、ベース基板３１の第１面３１ａに設けられる。接続電極３７、３８と凸部３９とは、第１方向Ｄｘで離れて配置される。電子部品２０は、導電性接着剤３５、３６を介して、接続電極３７、３８と電気的に接続される。 The connection electrodes 37, 38 and the convex portion 39 are provided on the first surface 31a of the base substrate 31. The connection electrodes 37, 38 and the convex portion 39 are arranged apart from each other in the first direction Dx. The electronic component 20 is electrically connected to the connection electrodes 37 and 38 via the conductive adhesives 35 and 36.
　４つの第１導体層５１は、第１面３１ａの各コーナー部近傍に設けられる。第１導体層５１ａは、配線５５を介して接続電極３８と接続される。第１導体層５１ａと対角に位置する第１導体層５１ｂは、配線５６を介して接続電極３７と接続される。すなわち、第１導体層５１ａ、５１ｂは、電子部品２０の入出力端子として機能する。第１導体層５１ａと第１導体層５１ｂとの間のコーナー部に位置する第１導体層５１ｃは、基準電位に接続される。また、第１導体層５１ｃと対角に位置する第１導体層５１（図１では図示されない）も基準電位に接続される。基準電位は、例えばグランド電位である。第１導体層５１ｃ及び対角に位置する第１導体層５１は、基準電位接続端子であり、それぞれリッド部材３２と電気的に接続される。 The four first conductor layers 51 are provided near each corner of the first surface 31a. The first conductor layer 51a is connected to the connection electrode 38 via the wiring 55. The first conductor layer 51b located diagonally to the first conductor layer 51a is connected to the connection electrode 37 via the wiring 56. That is, the first conductor layers 51a and 51b function as input / output terminals of the electronic component 20. The first conductor layer 51c located at the corner between the first conductor layer 51a and the first conductor layer 51b is connected to the reference potential. Further, the first conductor layer 51 (not shown in FIG. 1) located diagonally to the first conductor layer 51c is also connected to the reference potential. The reference potential is, for example, the ground potential. The first conductor layer 51c and the diagonally located first conductor layer 51 are reference potential connection terminals, and are electrically connected to the lid member 32, respectively.
　絶縁層６０は、第１面３１ａの外縁に沿って枠状に設けられ、第１導体層５１及び配線５５、５６を覆う。接続電極３７、３８及び凸部３９は、絶縁層６０で囲まれた領域に設けられる。また、絶縁層６０は、切り欠き部３１ｄも覆って設けられる。なお、第１導体層５１を含む導体層５０（図４参照）及び絶縁層６０の詳細な構成については、後述する。 The insulating layer 60 is provided in a frame shape along the outer edge of the first surface 31a and covers the first conductor layer 51 and the wirings 55 and 56. The connection electrodes 37, 38 and the convex portion 39 are provided in the region surrounded by the insulating layer 60. Further, the insulating layer 60 is also provided so as to cover the cutout portion 31d. The detailed configuration of the conductor layer 50 (see FIG. 4) including the first conductor layer 51 and the insulating layer 60 will be described later.
　リッド部材３２は、凹状の部材であり、ベース基板３１の第１面３１ａに対向するように開口される。リッド部材３２は、電子部品２０を覆って設けられ、リッド部材３２の開口端部は、封止材３３を介してベース基板３１の第１面３１ａに接合される。リッド部材３２は、金属材料で形成される。ただしこれに限定されず、リッド部材３２は、絶縁材料、あるいは、金属材料及び絶縁材料の複合材料で形成されてもよい。 The lid member 32 is a concave member and is opened so as to face the first surface 31a of the base substrate 31. The lid member 32 is provided so as to cover the electronic component 20, and the open end portion of the lid member 32 is joined to the first surface 31a of the base substrate 31 via the sealing material 33. The lid member 32 is made of a metal material. However, the lid member 32 may be formed of an insulating material or a composite material of a metal material and an insulating material.
　図２は、図１のＩＩ－ＩＩ’断面図である。図２に示すように、電子部品２０は、回路基板３０と、リッド部材３２とで囲まれた内部空間３４に配置され、ベース基板３１の第１面３１ａに搭載される。電子部品２０は、例えば水晶振動子である。ただし、電子部品２０は、水晶振動子に限定されず、他の電子部品であってもよい。電子デバイス１０は、電子部品２０として、ＳＡＷ（Surface　Acoustic　Wave）フィルタや、圧電振動素子や、ＭＥＭＳ（Micro　Electro　Mechanical　Systems）振動素子等の他の部品を搭載してもよい。 FIG. 2 is a cross-sectional view taken along the line II-II'of FIG. As shown in FIG. 2, the electronic component 20 is arranged in the internal space 34 surrounded by the circuit board 30 and the lid member 32, and is mounted on the first surface 31a of the base board 31. The electronic component 20 is, for example, a crystal oscillator. However, the electronic component 20 is not limited to the crystal oscillator, and may be another electronic component. The electronic device 10 may be equipped with other components such as a SAW (Surface Acoustic Wave) filter, a piezoelectric vibration element, and a MEMS (Micro Electro Mechanical Systems) vibration element as the electronic component 20.
　電子部品２０は、圧電基板２１と、第１励振電極２２と、第２励振電極２３と、を有する。第１励振電極２２は、圧電基板２１の一方の面に設けられる。第２励振電極２３は、圧電基板２１の他方の面に設けられる。 The electronic component 20 has a piezoelectric substrate 21, a first excitation electrode 22, and a second excitation electrode 23. The first excitation electrode 22 is provided on one surface of the piezoelectric substrate 21. The second excitation electrode 23 is provided on the other surface of the piezoelectric substrate 21.
　圧電基板２１に形成される第１励振電極２２及び第２励振電極２３は、一対の電極として、平面視で重なり合うように配置されている。また、圧電基板２１の一方の面には、第１励振電極２２に電気的に接続された延出電極２２ａが設けられる。延出電極２２ａは圧電基板２１の側面を通って、圧電基板２１の他方の面に設けられた接続電極２２ｂと電気的に接続されている。また、圧電基板２１の他方の面には、第２励振電極２３に電気的に接続された延出電極２３ａが設けられる。延出電極２３ａは、圧電基板２１の他方の面に設けられ、接続電極２２ｂと隣り合う接続電極（図２では図示されない）と電気的に接続されている。２つの接続電極は、圧電基板２１の同じ端部側に配置され、それぞれ導電性接着剤３５、３６を介して、接続電極３７、３８と電気的に接続される。 The first excitation electrode 22 and the second excitation electrode 23 formed on the piezoelectric substrate 21 are arranged as a pair of electrodes so as to overlap each other in a plan view. Further, on one surface of the piezoelectric substrate 21, an extension electrode 22a electrically connected to the first excitation electrode 22 is provided. The extension electrode 22a passes through the side surface of the piezoelectric substrate 21 and is electrically connected to the connection electrode 22b provided on the other surface of the piezoelectric substrate 21. Further, on the other surface of the piezoelectric substrate 21, an extension electrode 23a electrically connected to the second excitation electrode 23 is provided. The extension electrode 23a is provided on the other surface of the piezoelectric substrate 21 and is electrically connected to a connection electrode (not shown in FIG. 2) adjacent to the connection electrode 22b. The two connection electrodes are arranged on the same end side of the piezoelectric substrate 21 and are electrically connected to the connection electrodes 37 and 38 via the conductive adhesives 35 and 36, respectively.
　図２に示す例では、電子部品２０は、接続電極２２ｂが配置された一方の端部が固定端となるように、回路基板３０に支持される。また、電子部品２０の他方の端部は自由端となっている。電子部品２０の他方の端部と第１面３１ａとの間に凸部３９が設けられている。凸部３９により、電子部品２０の他方の端部が、第１面３１ａと直接接触することを抑制することができる。 In the example shown in FIG. 2, the electronic component 20 is supported by the circuit board 30 so that one end on which the connection electrode 22b is arranged becomes a fixed end. Further, the other end of the electronic component 20 is a free end. A convex portion 39 is provided between the other end of the electronic component 20 and the first surface 31a. The convex portion 39 can prevent the other end of the electronic component 20 from coming into direct contact with the first surface 31a.
　次に、図３、４を参照して、導体層５０及び絶縁層６０の詳細な構成について説明する。図３は、回路基板を第２面側から見た平面図である。図４は、図３のＩＶ－ＩＶ’断面図である。なお、図３から図７では、説明を分かりやすくするために、電子部品２０、リッド部材３２及び封止材３３を省略して、回路基板３０の構成を示している。 Next, the detailed configuration of the conductor layer 50 and the insulating layer 60 will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view of the circuit board as viewed from the second surface side. FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG. In addition, in FIGS. 3 to 7, in order to make the explanation easy to understand, the configuration of the circuit board 30 is shown by omitting the electronic component 20, the lid member 32, and the sealing material 33.
　図３に示すように、回路基板３０は、複数の導体層５０ａ、５０ｂ、５０ｃ、５０ｄを有する。複数の導体層５０ａ、５０ｂ、５０ｃ、５０ｄは、それぞれベース基板３１の切り欠き部３１ｄに対応する位置に設けられる。複数の導体層５０ａ、５０ｂ、５０ｃ、５０ｄは、それぞれ、複数の第２導体層５２ａ、５２ｂ、５２ｃ、５２ｄを有する。第２導体層５２ａ、５２ｂ、５２ｃ、５２ｄは、それぞれ、ベース基板３１の第２面３１ｂに設けられ、４つの切り欠き部３１ｄに対応する位置に設けられる。第２導体層５２は、それぞれ略四角形状であり、切り欠き部３１ｄの曲面に沿った方向で、切り欠き部３１ｄの一方の端部から他方の端部まで覆うように形成される。 As shown in FIG. 3, the circuit board 30 has a plurality of conductor layers 50a, 50b, 50c, and 50d. The plurality of conductor layers 50a, 50b, 50c, and 50d are provided at positions corresponding to the notched portions 31d of the base substrate 31, respectively. The plurality of conductor layers 50a, 50b, 50c, 50d have a plurality of second conductor layers 52a, 52b, 52c, 52d, respectively. The second conductor layers 52a, 52b, 52c, and 52d are provided on the second surface 31b of the base substrate 31, respectively, and are provided at positions corresponding to the four notched portions 31d. Each of the second conductor layers 52 has a substantially quadrangular shape, and is formed so as to cover from one end to the other end of the notch 31d in the direction along the curved surface of the notch 31d.
　なお、以下の説明では、導体層５０ａ、５０ｂ、５０ｃ、５０ｄを区別して説明する必要がない場合には、単に導体層５０と表す。また、第２導体層５２ａ、５２ｂ、５２ｃ、５２ｄを区別して説明する必要が無い場合には、単に第２導体層５２と表す。 In the following description, when it is not necessary to distinguish the conductor layers 50a, 50b, 50c, and 50d, they are simply referred to as the conductor layer 50. When it is not necessary to distinguish and explain the second conductor layers 52a, 52b, 52c, and 52d, it is simply referred to as the second conductor layer 52.
　図４に示すように、導体層５０ａは、第１導体層５１ａと、第２導体層５２ａと、側面導体層５３ａと、を含む。第１導体層５１ａは、ベース基板３１の第１面３１ａに設けられる。第２導体層５２ａは、ベース基板３１の第２面３１ｂに設けられる。第１導体層５１ａは、ベース基板３１を挟んで第２導体層５２ａと重なる位置に設けられる。側面導体層５３ａは、ベース基板３１の側面３１ｃ、より具体的には、ベース基板３１の側面３１ｃのコーナー部に形成された切り欠き部３１ｄに設けられ、第１導体層５１ａと第２導体層５２ａとを接続する。つまり、導体層５０ａは、ベース基板３１の第１面３１ａから側面３１ｃ（切り欠き部３１ｄ）を通って第２面３１ｂまで連続して形成される。また、側面導体層５３ａは、切り欠き部３１ｄの全体を覆って設けられる。ただし、これに限定されず、側面導体層５３ａは、切り欠き部３１ｄの一部を覆って設けられていればよい。 As shown in FIG. 4, the conductor layer 50a includes a first conductor layer 51a, a second conductor layer 52a, and a side conductor layer 53a. The first conductor layer 51a is provided on the first surface 31a of the base substrate 31. The second conductor layer 52a is provided on the second surface 31b of the base substrate 31. The first conductor layer 51a is provided at a position overlapping the second conductor layer 52a with the base substrate 31 interposed therebetween. The side conductor layer 53a is provided in the side surface 31c of the base substrate 31, more specifically, the notch portion 31d formed in the corner portion of the side surface 31c of the base substrate 31, and the first conductor layer 51a and the second conductor layer are provided. Connect with 52a. That is, the conductor layer 50a is continuously formed from the first surface 31a of the base substrate 31 to the second surface 31b through the side surface 31c (notch portion 31d). Further, the side conductor layer 53a is provided so as to cover the entire notch portion 31d. However, the present invention is not limited to this, and the side conductor layer 53a may be provided so as to cover a part of the notch portion 31d.
　導体層５０ｂは、第１導体層５１ｂと、第２導体層５２ｂと、側面導体層５３ｂと、を含む。第１導体層５１ｂは、ベース基板３１の第１面３１ａに設けられる。第２導体層５２ｂは、ベース基板３１の第２面３１ｂに設けられる。第１導体層５１ｂは、ベース基板３１を挟んで第２導体層５２ｂと重なる位置に設けられる。側面導体層５３ｂは、ベース基板３１の側面３１ｃ、より具体的には、ベース基板３１の側面３１ｃのコーナー部に形成された切り欠き部３１ｄに設けられ、第１導体層５１ｂと第２導体層５２ｂとを接続する。つまり、導体層５０ｂは、ベース基板３１の第１面３１ａから側面３１ｃ（切り欠き部３１ｄ）を通って第２面３１ｂまで連続して形成される。また、側面導体層５３ｂは、切り欠き部３１ｄの全体を覆って設けられる。ただし、これに限定されず、側面導体層５３ｂは、切り欠き部３１ｄの一部を覆って設けられていればよい。 The conductor layer 50b includes a first conductor layer 51b, a second conductor layer 52b, and a side conductor layer 53b. The first conductor layer 51b is provided on the first surface 31a of the base substrate 31. The second conductor layer 52b is provided on the second surface 31b of the base substrate 31. The first conductor layer 51b is provided at a position overlapping the second conductor layer 52b with the base substrate 31 interposed therebetween. The side conductor layer 53b is provided in the side surface 31c of the base substrate 31, more specifically, the notch portion 31d formed in the corner portion of the side surface 31c of the base substrate 31, and the first conductor layer 51b and the second conductor layer are provided. Connect with 52b. That is, the conductor layer 50b is continuously formed from the first surface 31a of the base substrate 31 to the second surface 31b through the side surface 31c (notch portion 31d). Further, the side conductor layer 53b is provided so as to cover the entire notch portion 31d. However, the present invention is not limited to this, and the side conductor layer 53b may be provided so as to cover a part of the notch portion 31d.
　言い換えると、導体層５０ａ、５０ｂは、それぞれ、ベース基板３１の第１面３１ａから側面３１ｃ（切り欠き部３１ｄ）を通って第２面３１ｂまで連続して形成される。また、図４では、導体層５０ａ、５０ｂの断面構造を示しているが、導体層５０ａ、５０ｂについての説明は、図３の第２導体層５２ｃ、５２ｄをそれぞれ含む導体層５０にも適用できる。 In other words, the conductor layers 50a and 50b are formed continuously from the first surface 31a of the base substrate 31 to the second surface 31b through the side surface 31c (notch portion 31d), respectively. Further, although FIG. 4 shows the cross-sectional structure of the conductor layers 50a and 50b, the description of the conductor layers 50a and 50b can be applied to the conductor layer 50 including the second conductor layers 52c and 52d of FIG. 3, respectively. ..
　絶縁層６０は、第１絶縁層６１と、突出部６２と、側面絶縁層６３と、第２絶縁層６７とを有する。 The insulating layer 60 has a first insulating layer 61, a protruding portion 62, a side insulating layer 63, and a second insulating layer 67.
　第１絶縁層６１は、第１導体層５１を覆ってベース基板３１の第１面３１ａに設けられる。第１絶縁層６１は、上述したように、ベース基板３１の第１面３１ａの外縁に沿って枠状に形成される（図１参照）。ただし、これに限定されず、第１絶縁層６１は、４つの導体層５０ごとに離れて配置されてもよい。 The first insulating layer 61 is provided on the first surface 31a of the base substrate 31 so as to cover the first conductor layer 51. As described above, the first insulating layer 61 is formed in a frame shape along the outer edge of the first surface 31a of the base substrate 31 (see FIG. 1). However, the present invention is not limited to this, and the first insulating layer 61 may be arranged separately for each of the four conductor layers 50.
　突出部６２は、第２導体層５２と、側面導体層５３との接続箇所である接続部５４を覆って設けられる。突出部６２は、第２導体層５２の少なくとも一部を覆って設けられ、第２導体層５２の表面から第３方向Ｄｚに突出して形成される。言い換えると、突出部６２と第２導体層５２とで、段差が形成される。図３に示すように、絶縁層６０は４つの切り欠き部３１ｄのそれぞれに設けられ、突出部６２は、接続部５４ａ、５４ｂ、５４ｃ、５４ｄを覆って設けられる。接続部５４は、切り欠き部３１ｄの曲面に沿って、一方の端部から他方の端部に亘って連続して形成される。突出部６２は、接続部５４の全体を覆って設けられ、接続部５４の一方の端部から他方の端部に亘って連続して形成される。接続部５４及び突出部６２は、切り欠き部３１ｄの曲面に沿って円弧状に設けられる。なお、接続部５４は、切り欠き部３１ｄの全領域に形成される構成に限定されず、切り欠き部３１ｄの一部に設けられていてもよい。この場合にも、突出部６２は、接続部５４の全領域を覆って設けられる。 The protruding portion 62 is provided so as to cover the connecting portion 54, which is a connecting portion between the second conductor layer 52 and the side conductor layer 53. The protrusion 62 is provided so as to cover at least a part of the second conductor layer 52, and is formed so as to project from the surface of the second conductor layer 52 in the third direction Dz. In other words, a step is formed between the protrusion 62 and the second conductor layer 52. As shown in FIG. 3, the insulating layer 60 is provided in each of the four notches 31d, and the protruding portion 62 is provided so as to cover the connecting portions 54a, 54b, 54c, 54d. The connecting portion 54 is continuously formed from one end to the other along the curved surface of the notch 31d. The protrusion 62 is provided so as to cover the entire connection portion 54, and is continuously formed from one end portion of the connection portion 54 to the other end portion. The connecting portion 54 and the protruding portion 62 are provided in an arc shape along the curved surface of the cutout portion 31d. The connection portion 54 is not limited to the configuration formed in the entire region of the notch portion 31d, and may be provided in a part of the notch portion 31d. Also in this case, the protrusion 62 is provided so as to cover the entire area of the connection portion 54.
　図４に戻って、側面絶縁層６３は、側面導体層５３ｂを覆って設けられ、第１絶縁層６１と突出部６２とを接続する。つまり、絶縁層６０は、それぞれ、ベース基板３１の第１面３１ａから側面３１ｃ（切り欠き部３１ｄ）を通って第２面３１ｂまで連続して形成される。また、側面絶縁層６３は、側面導体層５３ｂの全体を覆って設けられる。ただし、これに限定されず、側面絶縁層６３は、少なくとも第２面３１ｂ側の側面導体層５３ｂを覆って設けられていればよく、第１絶縁層６１と、側面絶縁層６３及び突出部６２とが離れて設けられていてもよい。 Returning to FIG. 4, the side insulating layer 63 is provided so as to cover the side conductor layer 53b, and connects the first insulating layer 61 and the protruding portion 62. That is, each of the insulating layers 60 is continuously formed from the first surface 31a of the base substrate 31 to the second surface 31b through the side surface 31c (notch portion 31d). Further, the side insulating layer 63 is provided so as to cover the entire side conductor layer 53b. However, the present invention is not limited to this, and the side insulating layer 63 may be provided so as to cover at least the side conductor layer 53b on the second surface 31b side, and the first insulating layer 61, the side insulating layer 63, and the protruding portion 62 may be provided. And may be provided apart from each other.
　第２絶縁層６７は、第１絶縁層６１を覆って設けられる。第２絶縁層６７は、平面視で第１絶縁層６１と同じ形状で設けられていてもよいし、第１絶縁層６１と異なる形状であってもよい。また、第２絶縁層６７は、設けられていなくてもよい。 The second insulating layer 67 is provided so as to cover the first insulating layer 61. The second insulating layer 67 may be provided in the same shape as the first insulating layer 61 in a plan view, or may have a different shape from the first insulating layer 61. Further, the second insulating layer 67 may not be provided.
　導体層５０の材料は、銀又は銀パラジウム合金、モリブデン、タングステンなどの金属から成る。絶縁層６０は、ガラス材料又は樹脂材料で形成される。ガラス材料として例えば低融点ガラス（例えば鉛ホウ酸系や錫リン酸系等）や、低温で乾燥するガラス（例えばアルミナ、シリカ等）を用いることができる。ガラス材料を用いた場合、絶縁層６０とセラミックなどのベース基板３１との密着強度を向上させることができる。樹脂材料として、例えば、熱硬化性樹脂であってもよく、エポキシ樹脂を主成分とする材料であってもよい。 The material of the conductor layer 50 is made of a metal such as silver or a silver-palladium alloy, molybdenum, or tungsten. The insulating layer 60 is made of a glass material or a resin material. As the glass material, for example, low melting point glass (for example, lead boric acid type, tin phosphoric acid type, etc.) and glass that dries at low temperature (for example, alumina, silica, etc.) can be used. When a glass material is used, the adhesion strength between the insulating layer 60 and the base substrate 31 such as ceramic can be improved. The resin material may be, for example, a thermosetting resin or a material containing an epoxy resin as a main component.
　図５は、電子デバイスが実装基板に実装された場合の、導体層、絶縁層及びはんだの関係を説明するための断面図である。図５に示すように、電子デバイス１０は、例えばリフロー工程により、実装基板２００に実装される。回路基板３０の第２面３１ｂが実装基板２００に対向して配置される。第２導体層５２の、突出部６２が設けられていない部分は、はんだ２０２を介して、実装基板２００の実装電極２０１に接合される。 FIG. 5 is a cross-sectional view for explaining the relationship between the conductor layer, the insulating layer, and the solder when the electronic device is mounted on the mounting board. As shown in FIG. 5, the electronic device 10 is mounted on the mounting board 200 by, for example, a reflow process. The second surface 31b of the circuit board 30 is arranged so as to face the mounting board 200. The portion of the second conductor layer 52 where the protrusion 62 is not provided is joined to the mounting electrode 201 of the mounting substrate 200 via the solder 202.
　ここで、ガラス材料又は樹脂材料で形成された絶縁層６０は、導体層５０に比べてはんだ２０２のぬれ性が低い。これにより、はんだ２０２の側面導体層５３への這い上がりを抑制できる。より好ましくは、本実施形態では、接続部５４を覆って突出部６２が設けられており、第２導体層５２から突出して段差を形成するように突出部６２が設けられる。これにより、はんだ２０２の移動が突出部６２で堰き止められ、はんだ２０２が側面導体層５３に這い上がることを抑制できる。より具体的には、突出部６２によりはんだ２０２の移動が規制され、はんだ２０２は、導体層５０のうち第２面３１ｂに設けられた第２導体層５２のみと接し、側面導体層５３とは非接触である。これにより、突出部６２が形成されず、接続部５４及び側面導体層５３を覆ってはんだ２０２が設けられた場合に比べて、はんだ２０２が側面導体層５３に設けられないので、はんだ２０２の表面張力により水平方向に作用する力が抑制され、実装の際のセルフアライメント性を向上させることができる。 Here, the insulating layer 60 made of a glass material or a resin material has a lower wettability of the solder 202 than the conductor layer 50. As a result, it is possible to suppress the creeping up of the solder 202 to the side conductor layer 53. More preferably, in the present embodiment, the projecting portion 62 is provided so as to cover the connecting portion 54, and the projecting portion 62 is provided so as to project from the second conductor layer 52 to form a step. As a result, the movement of the solder 202 is blocked by the protrusion 62, and the solder 202 can be prevented from crawling up to the side conductor layer 53. More specifically, the movement of the solder 202 is restricted by the protrusion 62, and the solder 202 is in contact with only the second conductor layer 52 provided on the second surface 31b of the conductor layer 50, and is not the side conductor layer 53. It is non-contact. As a result, the protruding portion 62 is not formed, and the solder 202 is not provided on the side conductor layer 53 as compared with the case where the solder 202 is provided so as to cover the connecting portion 54 and the side conductor layer 53, so that the surface of the solder 202 is formed. The force acting in the horizontal direction is suppressed by the tension, and the self-alignment property at the time of mounting can be improved.
　図３に示すように、突出部６２は接続部５４の全体を覆って設けられ、また、４つの切り欠き部３１ｄのそれぞれに突出部６２が形成される。平面視で、複数の第２導体層５２のそれぞれに設けられた突出部６２は、異なる方向に延在して形成される。すなわち、複数の第２導体層５２のそれぞれで、リフロー工程等の実装の際のセルフアライメント性を向上させることができる。 As shown in FIG. 3, the protruding portion 62 is provided so as to cover the entire connecting portion 54, and the protruding portion 62 is formed in each of the four cutout portions 31d. In a plan view, the protrusions 62 provided on each of the plurality of second conductor layers 52 are formed so as to extend in different directions. That is, each of the plurality of second conductor layers 52 can improve the self-alignment property at the time of mounting such as a reflow process.
　また、はんだ２０２の這い上がりを抑制することで、はんだ２０２が第１導体層５１側まで這い上がった場合に比べ、はんだ２０２を介して導体層５０とリッド部材３２とが電気的に接続されることを抑制できる。より具体的には、電子部品２０の入出力端子として機能する導体層５０ａ、５０ｂが、はんだ２０２及びリッド部材３２を介して、基準電位（例えばグランド電位）にショートすることが抑制される。 Further, by suppressing the creeping up of the solder 202, the conductor layer 50 and the lid member 32 are electrically connected via the solder 202 as compared with the case where the solder 202 creeps up to the first conductor layer 51 side. It can be suppressed. More specifically, it is suppressed that the conductor layers 50a and 50b functioning as input / output terminals of the electronic component 20 are short-circuited to the reference potential (for example, the ground potential) via the solder 202 and the lid member 32.
（第１変形例）
　図６は、第１変形例に係る電子デバイスにおいて、ベース基板を第２面側から見た平面図である。第１変形例では、上述した実施形態とは異なり、切り欠き部３１Ａｄが直線状に形成された構成について説明する。 (First modification)
FIG. 6 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the first modification. In the first modification, unlike the above-described embodiment, a configuration in which the notch portion 31Ad is formed linearly will be described.
　図６に示すように、第１変形例の電子デバイス１０Ａ及び回路基板３０Ａでは、切り欠き部３１Ａｄは、ベース基板３１Ａのコーナー部のそれぞれで、側面３１Ａｃの一部が直線状に切断された構成となっている。言い換えると、切り欠き部３１Ａｄは、平面視で、隣り合う２つの側面３１Ａｃを直線状に接続している。ベース基板３１Ａは、第２面３１Ａｂ側から見た平面視で八角形状である。 As shown in FIG. 6, in the electronic device 10A and the circuit board 30A of the first modification, the cutout portion 31Ad has a configuration in which a part of the side surface 31Ac is linearly cut at each of the corner portions of the base substrate 31A. It has become. In other words, the notch 31Ad connects two adjacent side surfaces 31Ac in a straight line in a plan view. The base substrate 31A has an octagonal shape when viewed from the second surface 31Ab side.
　第１変形例では、接続部５４も切り欠き部３１Ａｄと同様に直線状に設けられ、突出部６２は、直線状の接続部５４を覆って設けられる。突出部６２も接続部５４に沿った直線状に形成される。 In the first modification, the connecting portion 54 is also provided linearly like the notch portion 31Ad, and the protruding portion 62 is provided so as to cover the linear connecting portion 54. The protruding portion 62 is also formed in a straight line along the connecting portion 54.
　第１変形例では、接続部５４及び突出部６２が各切り欠き部３１Ａｄに沿って直線状に形成され、上述した実施形態に比べて構成を簡易にできる。このため、突出部６２は、確実に接続部５４を覆って形成できる。 In the first modification, the connecting portion 54 and the protruding portion 62 are formed linearly along each notch portion 31Ad, and the configuration can be simplified as compared with the above-described embodiment. Therefore, the protruding portion 62 can be reliably formed so as to cover the connecting portion 54.
（第２変形例）
　図７は、第２変形例に係る電子デバイスにおいて、ベース基板を第２面側から見た平面図である。第２変形例では、上述した実施形態及び第１変形例とは異なり、ベース基板３１Ｂに切り欠き部３１ｄ、３１Ａｄが設けられていない構成について説明する。 (Second modification)
FIG. 7 is a plan view of the base substrate as viewed from the second surface side in the electronic device according to the second modification. In the second modification, unlike the above-described embodiment and the first modification, a configuration in which the notch portions 31d and 31Ad are not provided in the base substrate 31B will be described.
　図７に示すように、第２変形例の電子デバイス１０Ｂ及び回路基板３０Ｂでは、ベース基板３１Ｂは、平面視で矩形状であり、４つのコーナー部のそれぞれで、隣接する側面３１Ｂｃが接続されて形成される。接続部５４は、長辺の側面３１Ｂｃに沿って設けられ、長辺の側面３１Ｂｃの一方の端部側と、他方の端部側とに離れて配置される。すなわち、接続部５４を形成する側面導体層５３と第２導体層５２とは、長辺の側面３１Ｂｃの一方の端部側と、他方の端部側とに離れて配置される。また、本変形例でも、絶縁層６０の突出部６２は接続部５４を覆って設けられる。 As shown in FIG. 7, in the electronic device 10B and the circuit board 30B of the second modification, the base substrate 31B has a rectangular shape in a plan view, and adjacent side surfaces 31Bc are connected to each of the four corner portions. It is formed. The connecting portion 54 is provided along the side surface 31Bc of the long side, and is arranged apart from one end side and the other end side of the side surface 31Bc of the long side. That is, the side conductor layer 53 and the second conductor layer 52 forming the connecting portion 54 are arranged apart from one end side and the other end side of the side surface 31Bc on the long side. Further, also in this modification, the protruding portion 62 of the insulating layer 60 is provided so as to cover the connecting portion 54.
　本変形例において、第２方向Ｄｙに隣り合う２つの突出部６２の間に２つの第２導体層５２が配置される。これにより、電子デバイス１０Ｂ及び回路基板３０Ｂは、実装の際に少なくとも第２方向Ｄｙでのセルフアライメント性を向上させることができる。また、切り欠き部３１ｄ、３１Ａｄを形成する工程を省略できるので、回路基板３０Ｂの製造工程を簡易にすることができる。 In this modification, the two second conductor layers 52 are arranged between the two protrusions 62 adjacent to each other in the second direction Dy. Thereby, the electronic device 10B and the circuit board 30B can improve the self-alignment property at least in the second direction Dy at the time of mounting. Further, since the step of forming the cutout portions 31d and 31Ad can be omitted, the manufacturing step of the circuit board 30B can be simplified.
　なお、上述した電子デバイス１０、１０Ａ、１０Ｂ及び回路基板３０、３０Ａ、３０Ｂの構成はあくまで一例であり適宜変更することができる。例えば、第２導体層５２は、略四角形状に限定されず、多角形状、円形状等他の形状であってもよい。複数の第２導体層５２は相似形であるが、これに限定されず、異なる形状であってもよい。また、１つの回路基板３０に設けられる導体層５０の数は、４つに限定されず、３つ又は５つ以上であってもよい。突出部６２（絶縁層６０）は、全ての導体層５０に設けられることが好ましい。ただし、複数の導体層のうち突出部６２が形成されないものがあってもよい。導体層５０及び突出部６２（絶縁層６０）は、ベース基板３１のコーナー部に限定されず、側面３１ｃの中央部に設けられていてもよい。 The configurations of the electronic devices 10, 10A and 10B and the circuit boards 30, 30A and 30B described above are merely examples and can be changed as appropriate. For example, the second conductor layer 52 is not limited to a substantially quadrangular shape, and may have another shape such as a polygonal shape or a circular shape. The plurality of second conductor layers 52 have similar shapes, but are not limited to these, and may have different shapes. Further, the number of conductor layers 50 provided on one circuit board 30 is not limited to four, and may be three or five or more. The protrusion 62 (insulating layer 60) is preferably provided on all conductor layers 50. However, there may be a plurality of conductor layers in which the protrusion 62 is not formed. The conductor layer 50 and the protruding portion 62 (insulating layer 60) are not limited to the corner portions of the base substrate 31, and may be provided at the central portion of the side surface 31c.
　以上説明したように、本実施形態の回路基板３０は、電子部品２０が搭載される回路基板３０であって、電子部品２０が搭載される第１面３１ａと、第１面３１ａと反対側の第２面３１ｂと、第１面３１ａと第２面３１ｂとの間に設けられた側面３１ｃとを有するベース基板３１と、第１面３１ａに設けられた第１導体層５１と、第２面３１ｂに設けられた第２導体層５２と、側面３１ｃに設けられ、第１導体層５１と第２導体層５２とを接続する側面導体層５３と、少なくとも第２導体層５２と側面導体層５３との接続箇所である接続部５４を覆って設けられた絶縁層６０と、を有する。 As described above, the circuit board 30 of the present embodiment is a circuit board 30 on which the electronic component 20 is mounted, and is on the first surface 31a on which the electronic component 20 is mounted and on the side opposite to the first surface 31a. A base substrate 31 having a second surface 31b, a side surface 31c provided between the first surface 31a and the second surface 31b, a first conductor layer 51 provided on the first surface 31a, and a second surface. A second conductor layer 52 provided on 31b, a side conductor layer 53 provided on the side surface 31c and connecting the first conductor layer 51 and the second conductor layer 52, and at least the second conductor layer 52 and the side conductor layer 53. It has an insulating layer 60 provided so as to cover the connection portion 54 which is a connection point with the above.
　これによれば、リフロー工程等により回路基板３０を実装基板２００に実装する際に、接続部５４を覆って設けられた絶縁層６０が、はんだ２０２の這い上がりを抑制するストッパとして機能する。これにより、はんだ２０２が側面導体層５３を覆って設けられることを抑制できるので、実装の際のセルフアライメント性を向上させることができる。 According to this, when the circuit board 30 is mounted on the mounting board 200 by a reflow process or the like, the insulating layer 60 provided so as to cover the connecting portion 54 functions as a stopper for suppressing the creeping up of the solder 202. As a result, it is possible to prevent the solder 202 from being provided so as to cover the side conductor layer 53, so that the self-alignment property at the time of mounting can be improved.
　また、回路基板３０において、絶縁層６０は、側面導体層５３を覆う側面絶縁層６３と、接続部５４を覆って設けられた突出部６２とを含み、突出部６２は、第２導体層５２から突出して設けられる。 Further, in the circuit board 30, the insulating layer 60 includes a side insulating layer 63 that covers the side conductor layer 53 and a protruding portion 62 that is provided so as to cover the connecting portion 54, and the protruding portion 62 is a second conductor layer 52. It is provided so as to protrude from.
　これによれば、第２導体層５２と突出部６２とで形成される段差により、はんだ２０２の移動が規制され、はんだ２０２の側面導体層５３への這い上がりを効果的に抑制することができる。 According to this, the movement of the solder 202 is restricted by the step formed by the second conductor layer 52 and the protrusion 62, and the creeping up of the solder 202 to the side conductor layer 53 can be effectively suppressed. ..
　また、回路基板３０において、第２面３１ｂから垂直な方向からの平面視で、ベース基板３１は４つのコーナー部を有し、第１導体層５１、第２導体層５２、側面導体層５３及び絶縁層６０は、４つのコーナー部のそれぞれに設けられる。 Further, in the circuit board 30, the base substrate 31 has four corners in a plan view from the direction perpendicular to the second surface 31b, and the first conductor layer 51, the second conductor layer 52, the side conductor layer 53, and the like. The insulating layer 60 is provided at each of the four corners.
　これによれば、回路基板３０の実装の際に、４つのコーナー部のそれぞれではんだ２０２の這い上がりが抑制され、４方向でのセルフアライメント性を向上させることができる。 According to this, when the circuit board 30 is mounted, the creeping up of the solder 202 is suppressed at each of the four corners, and the self-alignment property in four directions can be improved.
　また、回路基板３０において、コーナー部には、凹状に湾曲する円筒曲面の一部を有する切り欠き部３１ｄが設けられ、絶縁層６０は、平面視で、切り欠き部３１ｄの円筒曲面に沿って設けられる。 Further, in the circuit board 30, a cutout portion 31d having a part of a cylindrical curved surface curved in a concave shape is provided at a corner portion, and the insulating layer 60 is formed along the cylindrical curved surface of the cutout portion 31d in a plan view. It will be provided.
　これによれば、はんだ２０２の側面導体層５３への這い上がりを効果的に抑制することができる。 According to this, it is possible to effectively suppress the creeping up of the solder 202 to the side conductor layer 53.
　また、回路基板３０において、コーナー部には、平面視で、隣り合う２つの側面３１ｃを直線状に接続する切り欠き部３１Ａｄが設けられ、絶縁層６０は、平面視で、切り欠き部３１Ａｄに沿って直線状に設けられる。 Further, in the circuit board 30, the corner portion is provided with a notch portion 31Ad that linearly connects two adjacent side surfaces 31c in a plan view, and the insulating layer 60 is provided in the notch portion 31Ad in a plan view. It is provided linearly along the line.
　これによれば、切り欠き部３１Ａｄの構成を簡易にできる。 According to this, the configuration of the notch portion 31Ad can be simplified.
　また、回路基板３０において、絶縁層６０は、ガラス材料又は樹脂材料で形成される。 Further, in the circuit board 30, the insulating layer 60 is formed of a glass material or a resin material.
　これによれば、ガラス材料又は樹脂材料で形成された絶縁層６０は、導体層５０に比べてはんだ２０２のぬれ性が低いので、はんだ２０２の側面導体層５３への這い上がりを抑制できる。 According to this, since the insulating layer 60 made of the glass material or the resin material has a lower wettability of the solder 202 than the conductor layer 50, it is possible to suppress the creeping up of the solder 202 to the side conductor layer 53.
　また、本実施形態の電子デバイス１０は、上記の回路基板３０と、第１面３１ａに搭載された電子部品２０と、電子部品２０を覆って第１面３１ａに接合されたリッド部材３２と、を有する。また、電子デバイス１０において、電子部品２０は、水晶振動子である。 Further, the electronic device 10 of the present embodiment includes the circuit board 30, the electronic component 20 mounted on the first surface 31a, the lid member 32 covering the electronic component 20 and joined to the first surface 31a. Has. Further, in the electronic device 10, the electronic component 20 is a crystal oscillator.
　これによれば、リフロー等による電子デバイス１０の実装の際にセルフアライメント性を向上させることができる。 According to this, self-alignment can be improved when mounting the electronic device 10 by reflow or the like.
（回路基板の製造方法）
　次に回路基板３０の製造方法について説明する。図８は、実施形態に係る電子デバイスが有する回路基板の製造方法を説明するためのフローチャート図である。図９は、絶縁層を塗布形成するための製造装置を模式的に示す説明図である。図１０は、絶縁層の塗布工程を説明するための説明図である。図１１は、回路基板用母基板の構成例を模式的に示す平面図である。図１２は、図１１の領域Ｓを拡大して示す平面図である。 (Manufacturing method of circuit board)
Next, a method of manufacturing the circuit board 30 will be described. FIG. 8 is a flowchart for explaining a method of manufacturing a circuit board included in the electronic device according to the embodiment. FIG. 9 is an explanatory diagram schematically showing a manufacturing apparatus for coating and forming an insulating layer. FIG. 10 is an explanatory diagram for explaining the coating process of the insulating layer. FIG. 11 is a plan view schematically showing a configuration example of a mother board for a circuit board. FIG. 12 is an enlarged plan view showing the area S in FIG. 11.
　図８に示すように、回路基板３０の製造方法では、グリーンシートを、例えばドクターブレードやリップコータ等により塗布形成する（ステップＳＴ１１）。グリーンシートは、酸化アルミニウム（Ａｌ２Ｏ３）を主成分とするセラミック粉末と、有機バインダ及びその他添加剤を含む。 As shown in FIG. 8, in the method of manufacturing the circuit board 30, a green sheet is coated and formed by, for example, a doctor blade or a lip coater (step ST11). The green sheet contains a ceramic powder containing aluminum oxide (Al 2 O 3 ) as a main component, an organic binder and other additives.
　次に、グリーンシートに複数のスルーホール８２（図１０、図１２参照）を形成する（ステップＳＴ１２）。複数のスルーホール８２は、パンチング、ドリル、レーザ加工等によって形成できる。図１２に示すように、複数のスルーホール８２は、分割ラインＬ１、Ｌ２上に中心が位置するように、格子状に配列される。 Next, a plurality of through holes 82 (see FIGS. 10 and 12) are formed on the green sheet (step ST12). The plurality of through holes 82 can be formed by punching, drilling, laser machining, or the like. As shown in FIG. 12, the plurality of through holes 82 are arranged in a grid pattern so that the centers are located on the dividing lines L1 and L2.
　次に、グリーンシートを所定の温度で焼成する（ステップＳＴ１３）。これにより、回路基板用母基板８０の基体であるベース母基板８１が形成される。ベース母基板８１は、単層のセラミック基板でもよいし、複数のグリーンシートが積層された積層セラミック基板でもよい。なお、ステップＳＴ１２とステップＳＴ１３の順番は逆であってもよい。すなわち、孔開けされていないグリーンシートを焼成した後、焼成後のセラミック基板に、ドリル加工やレーザ加工により複数のスルーホール８２を形成してもよい。 Next, the green sheet is fired at a predetermined temperature (step ST13). As a result, the base mother substrate 81, which is the substrate of the mother substrate 80 for the circuit board, is formed. The base mother substrate 81 may be a single-layer ceramic substrate or a laminated ceramic substrate on which a plurality of green sheets are laminated. The order of steps ST12 and ST13 may be reversed. That is, after firing a green sheet that has not been perforated, a plurality of through holes 82 may be formed on the fired ceramic substrate by drilling or laser processing.
　次に、ベース母基板８１の表面及びスルーホール８２の内壁に導体層５０を形成する（ステップＳＴ１４）。導体層５０は、複数の回路領域８３（図１１、１２参照）のそれぞれに形成される。また、図１０に示すように、導体層５０は、回路基板用母基板８０のベース母基板８１の第１面８１ａ、スルーホール８２の内壁及びベース母基板８１の第２面８１ｂに亘って形成される。また、導体層５０と同じ工程で、図１２に示すように、接続電極３７、３８及び配線５５、５６（図１参照）も形成される。接続電極３７、３８及び配線５５、５６は、回路基板用母基板８０のベース母基板８１の第１面８１ａにおいて、複数の回路領域８３のそれぞれに形成される。導体層５０、接続電極３７、３８及び配線５５、５６は、導電材料を含有する導電性ペーストをスクリーン印刷で塗布形成することができる。あるいは、導体層５０は、蒸着、スパッタ、メッキ等によって形成してもよい。 Next, the conductor layer 50 is formed on the surface of the base mother substrate 81 and the inner wall of the through hole 82 (step ST14). The conductor layer 50 is formed in each of the plurality of circuit regions 83 (see FIGS. 11 and 12). Further, as shown in FIG. 10, the conductor layer 50 is formed over the first surface 81a of the base mother substrate 81 of the circuit board mother substrate 80, the inner wall of the through hole 82, and the second surface 81b of the base mother substrate 81. Will be done. Further, as shown in FIG. 12, connection electrodes 37 and 38 and wirings 55 and 56 (see FIG. 1) are also formed in the same process as the conductor layer 50. The connection electrodes 37, 38 and the wirings 55, 56 are formed in each of the plurality of circuit regions 83 on the first surface 81a of the base mother board 81 of the circuit board mother board 80. The conductor layer 50, the connection electrodes 37, 38, and the wirings 55, 56 can be formed by applying a conductive paste containing a conductive material by screen printing. Alternatively, the conductor layer 50 may be formed by vapor deposition, sputtering, plating or the like.
　以上のステップＳＴ１１からステップＳＴ１４に示す工程で、図１１及び図１２に示す複数の回路領域８３及び複数のスルーホール８２を有する回路基板用母基板８０を準備することができる。なお、回路領域８３は、回路基板用母基板８０が分割ラインＬ１、Ｌ２に沿って各個片に分割された場合に、回路基板３０として形成される予定の領域である。 In the above steps from step ST11 to step ST14, a circuit board mother substrate 80 having a plurality of circuit areas 83 and a plurality of through holes 82 shown in FIGS. 11 and 12 can be prepared. The circuit board area 83 is an area to be formed as the circuit board 30 when the circuit board mother board 80 is divided into individual pieces along the division lines L1 and L2.
　次に、導体層５０が形成されたベース母基板８１に絶縁層６０を形成する（ステップＳＴ１５）。具体的には、図９に示すように、複数のスルーホール８２を有する回路基板用母基板８０を印刷治具２１０上に載置する。製造装置は、印刷マスク２１２及びスキージ２１３を用いて、絶縁材料を含む絶縁性ペースト８５を回路基板用母基板８０（ベース母基板８１）の第１面８１ａに塗布形成することができる。印刷治具２１０には、複数のスルーホール８２と重なる領域に空間が設けられており、吸引ブロア２１１は第２面８１ｂ側から絶縁性ペースト８５を吸引可能に設けられている。 Next, the insulating layer 60 is formed on the base mother substrate 81 on which the conductor layer 50 is formed (step ST15). Specifically, as shown in FIG. 9, the circuit board mother substrate 80 having a plurality of through holes 82 is placed on the printing jig 210. The manufacturing apparatus can use the printing mask 212 and the squeegee 213 to apply and form the insulating paste 85 containing the insulating material on the first surface 81a of the circuit board mother substrate 80 (base mother substrate 81). The printing jig 210 is provided with a space in a region overlapping the plurality of through holes 82, and the suction blower 211 is provided so that the insulating paste 85 can be sucked from the second surface 81b side.
　図１０に示すように、絶縁層６０を形成する工程では、印刷装置は、複数のスルーホール８２の第１面８１ａ側の開口を覆って絶縁性ペースト８５を塗布形成する（ステップＳＴ１５－１）。製造装置は、同じ印刷工程で、絶縁性ペースト８５を分割ラインＬ１、Ｌ２に沿って格子状に形成する（図１２参照）。 As shown in FIG. 10, in the step of forming the insulating layer 60, the printing apparatus covers the openings on the first surface 81a side of the plurality of through holes 82 and coats and forms the insulating paste 85 (step ST15-1). .. The manufacturing apparatus forms the insulating paste 85 in a grid pattern along the dividing lines L1 and L2 in the same printing process (see FIG. 12).
　そして、吸引ブロア２１１は、スルーホール８２の第１面８１ａ側の開口を覆って形成された絶縁性ペースト８５を、第２面８１ｂ側から吸引する（ステップＳＴ１５－２）。これにより、絶縁性ペースト８５は第２面８１ｂ側に引っ張られ、スルーホール８２の内壁を覆って設けられる。ここで、スルーホール８２の内壁に設けられた絶縁性ペースト８５は、第１面８１ａ側及び第２面８１ｂ側の端部で薄く形成され、厚さ方向中央部で厚く形成される。これにより、スルーホール８２の内壁に設けられた絶縁性ペースト８５は、第１面８１ａ側及び第２面８１ｂ側の端部で半乾燥状態となり、流動性が低い。一方、厚さ方向中央部では、絶縁性ペースト８５は湿潤状態を維持しており、厚さ方向の両端部に比べて流動性が高い。 Then, the suction blower 211 sucks the insulating paste 85 formed by covering the opening on the first surface 81a side of the through hole 82 from the second surface 81b side (step ST15-2). As a result, the insulating paste 85 is pulled toward the second surface 81b and is provided so as to cover the inner wall of the through hole 82. Here, the insulating paste 85 provided on the inner wall of the through hole 82 is formed thinly at the ends on the first surface 81a side and the second surface 81b side, and is formed thicker at the central portion in the thickness direction. As a result, the insulating paste 85 provided on the inner wall of the through hole 82 becomes semi-dry at the ends on the first surface 81a side and the second surface 81b side, and the fluidity is low. On the other hand, in the central portion in the thickness direction, the insulating paste 85 maintains a wet state and has higher fluidity than both ends in the thickness direction.
　次に、ステップＳＴ１５－２に示す第１吸引工程の後、吸引ブロア２１１は、ベース母基板８１の第２面８１ｂ側から絶縁性ペースト８５をさらに吸引する（ステップＳＴ１５－３）。ステップＳＴ１５－３の第２吸引工程での吸引力は、第１吸引工程での吸引力よりも大きく、第２吸引工程での吸引時間は、第１吸引工程よりも短時間である。これにより、スルーホール８２の内壁に設けられた絶縁性ペースト８５は、湿潤状態を維持している部分が第２面８１ｂ側に引っ張られ、スルーホール８２の第２面８１ｂ側の開口縁部を覆う。すなわち、絶縁性ペースト８５は、側面導体層５３と第２導体層５２との接続部５４を覆って設けられる。その後、絶縁性ペースト８５を焼成または乾燥することで、突出部６２を含む絶縁層６０が形成される。 Next, after the first suction step shown in step ST15-2, the suction blower 211 further sucks the insulating paste 85 from the second surface 81b side of the base mother substrate 81 (step ST15-3). The suction force in the second suction step of step ST15-3 is larger than the suction force in the first suction step, and the suction time in the second suction step is shorter than that in the first suction step. As a result, in the insulating paste 85 provided on the inner wall of the through hole 82, the portion maintaining the wet state is pulled toward the second surface 81b, and the opening edge portion of the through hole 82 on the second surface 81b side is pulled. cover. That is, the insulating paste 85 is provided so as to cover the connecting portion 54 between the side conductor layer 53 and the second conductor layer 52. Then, the insulating paste 85 is fired or dried to form the insulating layer 60 including the protrusion 62.
　本実施形態において、ステップＳＴ１５－２、ＳＴ１５－３に示すように突出部６２を２段階の吸引工程で形成することにより、絶縁性ペースト８５の流動性を制御して、良好に接続部５４を覆うように突出部６２を形成することができる。また、第１面８１ａへ絶縁性ペースト８５を塗布形成し、吸引工程により第２面８１ｂ側に突出部６２を形成することができるので、絶縁性ペースト８５の両面印刷の工程を省略して突出部６２を形成することができる。 In the present embodiment, as shown in steps ST15-2 and ST15-3, the protruding portion 62 is formed by a two-step suction step to control the fluidity of the insulating paste 85 and to satisfactorily connect the connecting portion 54. The protrusion 62 can be formed so as to cover it. Further, since the insulating paste 85 can be applied and formed on the first surface 81a and the protruding portion 62 can be formed on the second surface 81b side by the suction step, the step of double-sided printing of the insulating paste 85 can be omitted. The portion 62 can be formed.
　以上のような工程で、図１１及び図１２に示すように、回路基板用母基板８０を準備することができる。回路基板用母基板８０において、複数の回路領域８３のそれぞれに、複数のスルーホール８２の内壁を覆って絶縁層６０が形成され、複数のスルーホール８２のそれぞれに、第２面８１ｂ側の開口縁部を覆う突出部６２が設けられる。 As shown in FIGS. 11 and 12, the mother substrate 80 for a circuit board can be prepared by the above steps. In the circuit board mother substrate 80, an insulating layer 60 is formed in each of the plurality of circuit areas 83 so as to cover the inner walls of the plurality of through holes 82, and each of the plurality of through holes 82 has an opening on the second surface 81b side. A protruding portion 62 is provided to cover the edge portion.
　以上説明したように、図１０から図１２に示す本実施形態の回路基板用母基板８０は、複数の回路領域８３及び複数のスルーホール８２を有する回路基板用母基板８０であって、複数の回路領域８３のそれぞれにおいて、回路基板用母基板８０（ベース母基板８１）の第１面８１ａに設けられた第１導体層５１と、回路基板用母基板８０（ベース母基板８１）の第２面８１ｂに設けられた第２導体層５２と、スルーホール８２の内壁に設けられ、第１導体層５１と第２導体層５２とを接続する側面導体層５３と、を有する。さらに、回路基板用母基板８０は、少なくとも第２導体層５２と側面導体層５３との接続箇所である接続部５４を覆って設けられた絶縁層６０（突出部６２）を有する。 As described above, the circuit board mother board 80 of the present embodiment shown in FIGS. 10 to 12 is a circuit board mother board 80 having a plurality of circuit areas 83 and a plurality of through holes 82, and is a plurality of circuit board mother boards 80. In each of the circuit areas 83, the first conductor layer 51 provided on the first surface 81a of the circuit board mother board 80 (base mother board 81) and the second of the circuit board mother board 80 (base mother board 81). It has a second conductor layer 52 provided on the surface 81b, and a side conductor layer 53 provided on the inner wall of the through hole 82 and connecting the first conductor layer 51 and the second conductor layer 52. Further, the mother substrate 80 for a circuit board has at least an insulating layer 60 (projecting portion 62) provided so as to cover the connecting portion 54 which is a connecting portion between the second conductor layer 52 and the side conductor layer 53.
　次に、図８に戻って、回路基板用母基板８０を分割ラインＬ１、Ｌ２に沿って各個片に分割することで、各回路基板３０を形成できる（ステップＳＴ１６）。分割ラインＬ１、Ｌ２は、回路基板用母基板８０を回路領域８３ごとに分割する位置を示す仮想線であり、レーザ装置やダイサーにより分割ラインＬ１、Ｌ２に沿って切断することができる。あるいは、分割ラインＬ１、Ｌ２に沿ってあらかじめ分割溝が設けられていてもよい。分割ラインＬ１、Ｌ２は、図１２に示すように、複数のスルーホール８２に沿って形成されている。言い換えると、ステップＳＴ１６では、回路基板用母基板８０は、複数のスルーホール８２に沿って分割される。これにより、各回路基板３０のコーナー部には、凹状に湾曲する円筒曲面を有する切り欠き部３１ｄが形成される。 Next, returning to FIG. 8, each circuit board 30 can be formed by dividing the circuit board mother board 80 into individual pieces along the dividing lines L1 and L2 (step ST16). The dividing lines L1 and L2 are virtual lines indicating positions for dividing the circuit board mother substrate 80 for each circuit area 83, and can be cut along the dividing lines L1 and L2 by a laser device or a dicer. Alternatively, a dividing groove may be provided in advance along the dividing lines L1 and L2. As shown in FIG. 12, the dividing lines L1 and L2 are formed along a plurality of through holes 82. In other words, in step ST16, the circuit board mother substrate 80 is divided along the plurality of through holes 82. As a result, a cutout portion 31d having a cylindrical curved surface curved in a concave shape is formed at the corner portion of each circuit board 30.
　なお、上述した回路基板３０の製造方法はあくまで一例であり適宜変更することができる。例えば、回路基板用母基板８０の基体であるベース母基板８１は、セラミック基板に限定されず、樹脂基板であってもよい。絶縁性ペースト８５は、スクリーン印刷に限定されず、インクジェット印刷等、他の方法で塗布形成してもよい。 The above-mentioned manufacturing method of the circuit board 30 is just an example and can be changed as appropriate. For example, the base mother substrate 81, which is the substrate of the mother substrate 80 for a circuit board, is not limited to the ceramic substrate, and may be a resin substrate. The insulating paste 85 is not limited to screen printing, and may be applied and formed by other methods such as inkjet printing.
　なお、上記した実施の形態は、本発明の理解を容易にするためのものであり、本発明を限定して解釈するためのものではない。本発明は、その趣旨を逸脱することなく、変更／改良され得るとともに、本発明にはその等価物も含まれる。 It should be noted that the above-described embodiment is for facilitating the understanding of the present invention, and is not for limiting the interpretation of the present invention. The present invention can be modified / improved without departing from the spirit thereof, and the present invention also includes an equivalent thereof.
　１０　電子デバイス
　２０　電子部品
　２１　圧電基板
　３０　回路基板
　３１、３１Ａ、３１Ｂ　ベース基板
　３１ａ　第１面
　３１ｂ　第２面
　３１ｃ　側面
　３１ｄ　切り欠き部
　３２　リッド部材
　３３　封止材
　３４　内部空間
　３５、３６　導電性接着剤
　３９　凸部
　５０、５０ａ、５０ｂ、５０ｃ、５０ｄ　導体層
　５１、５１ａ、５１ｂ、５１ｃ　第１導体層
　５２、５２ａ、５２ｂ、５２ｃ、５２ｄ　第２導体層
　５３、５３ａ、５３ｂ　側面導体層
　５４、５４ａ、５４ｂ、５４ｃ、５４ｄ　接続部
　６０　絶縁層
　６１　第１絶縁層
　６２　突出部
　６３　側面絶縁層
　６７　第２絶縁層
　８０　回路基板用母基板
　８１　ベース母基板
　８２　スルーホール
　８３　回路領域
　８５　絶縁性ペースト
　２００　実装基板
　２０１　実装電極
　２０２　はんだ
　Ｌ１、Ｌ２　分割ライン 10 Electronic devices 20 Electronic components 21 Hydraulic boards 30 Circuit boards 31, 31A, 31B Base boards 31a First side 31b Second side 31c Sides 31d Notches 32 Lid members 33 Encapsulants 34 Internal spaces 35, 36 Conductive adhesives 39 Convex parts 50, 50a, 50b, 50c, 50d Conductor layer 51, 51a, 51b, 51c First conductor layer 52, 52a, 52b, 52c, 52d Second conductor layer 53, 53a, 53b Side conductor layer 54, 54a, 54b, 54c, 54d Connection part 60 Insulation layer 61 First insulation layer 62 Protruding part 63 Side insulation layer 67 Second insulation layer 80 Mother board for circuit board 81 Base mother board 82 Through hole 83 Circuit area 85 Insulation paste 200 Mounting board 201 Mounting electrode 202 Solder L1, L2 dividing line

Claims (13)

  1. 　電子部品が搭載される回路基板であって、
    　前記電子部品が搭載される第１面と、前記第１面と反対側の第２面と、前記第１面と前記第２面との間に設けられた側面とを有するベース基板と、
    　前記第１面に設けられた第１導体層と、
    　前記第２面に設けられた第２導体層と、
    　前記側面に設けられ、前記第１導体層と前記第２導体層とを接続する側面導体層と、
    　少なくとも前記第２導体層と前記側面導体層との接続箇所である接続部を覆って設けられた絶縁層と、を有する
    　回路基板。     A circuit board on which electronic components are mounted.
    A base substrate having a first surface on which the electronic component is mounted, a second surface opposite to the first surface, and a side surface provided between the first surface and the second surface.
    The first conductor layer provided on the first surface and
    The second conductor layer provided on the second surface and
    A side conductor layer provided on the side surface and connecting the first conductor layer and the second conductor layer,
    A circuit board having at least an insulating layer provided so as to cover a connection portion which is a connection portion between the second conductor layer and the side conductor layer.
  2. 　請求項１に記載の回路基板であって、
    　前記絶縁層は、前記側面導体層を覆う側面絶縁層と、前記接続部を覆って設けられた突出部とを含み、前記突出部は、前記第２導体層から突出して設けられる
    　回路基板。     The circuit board according to claim 1.
    The insulating layer includes a side insulating layer that covers the side conductor layer and a protrusion provided that covers the connection portion, and the protrusion is a circuit board that is provided so as to project from the second conductor layer.
  3. 　請求項１又は請求項２に記載の回路基板であって、
    　前記第２面から垂直な方向からの平面視で、前記ベース基板は４つのコーナー部を有し、
    　前記第１導体層、前記第２導体層、前記側面導体層及び前記絶縁層は、前記４つのコーナー部のそれぞれに設けられる
    　回路基板。     The circuit board according to claim 1 or 2.
    In a plan view from the direction perpendicular to the second surface, the base substrate has four corners.
    The first conductor layer, the second conductor layer, the side conductor layer, and the insulating layer are circuit boards provided at each of the four corner portions.
  4. 　請求項３に記載の回路基板であって、
    　前記コーナー部には、凹状に湾曲する円筒曲面の一部を有する切り欠き部が設けられ、
    　前記絶縁層は、前記平面視で、前記切り欠き部の前記円筒曲面に沿って設けられる
    　回路基板。     The circuit board according to claim 3.
    The corner portion is provided with a notch portion having a part of a cylindrical curved surface curved in a concave shape.
    The insulating layer is a circuit board provided along the cylindrical curved surface of the notch portion in the plan view.
  5. 　請求項３に記載の回路基板であって、
    　前記コーナー部には、前記平面視で、隣り合う２つの前記側面を直線状に接続する切り欠き部が設けられ、
    　前記絶縁層は、前記平面視で、前記切り欠き部に沿って直線状に設けられる
    　回路基板。     The circuit board according to claim 3.
    The corner portion is provided with a notch portion that linearly connects two adjacent side surfaces in the plan view.
    The insulating layer is a circuit board provided linearly along the notch in the plan view.
  6. 　請求項１から請求項５のいずれか１項に記載の回路基板であって、
    　前記絶縁層は、ガラス材料又は樹脂材料で形成される
    　回路基板。     The circuit board according to any one of claims 1 to 5.
    The insulating layer is a circuit board made of a glass material or a resin material.
  7. 　請求項１から請求項６のいずれか１項に記載の回路基板と、
    　前記第１面に搭載された電子部品と、
    　前記電子部品を覆って前記第１面に接合されたリッド部材と、を有する
    　電子デバイス。     The circuit board according to any one of claims 1 to 6.
    The electronic components mounted on the first surface and
    An electronic device comprising a lid member that covers the electronic component and is joined to the first surface.
  8. 　請求項７に記載の電子デバイスであって、
    　前記電子部品は、水晶振動子である
    　電子デバイス。     The electronic device according to claim 7.
    The electronic component is an electronic device that is a crystal oscillator.
  9. 　複数の回路領域及び複数のスルーホールを有する回路基板用母基板を準備する工程と、
    　複数の前記回路領域のそれぞれに、前記回路基板用母基板の第１面、前記スルーホールの内壁及び前記回路基板用母基板の第２面に亘って導体層を形成する工程と、
    　絶縁材料を含む絶縁性ペーストを、複数の前記スルーホールの前記第１面側の開口を覆って塗布形成し、前記第１面側の開口を覆う前記絶縁性ペーストを前記回路基板用母基板の前記第２面側から吸引する第１吸引工程と、
    　前記第１吸引工程の後、前記絶縁性ペーストを前記回路基板用母基板の前記第２面側からさらに吸引する第２吸引工程と、を有する
    　回路基板の製造方法。     The process of preparing a mother board for a circuit board having a plurality of circuit areas and a plurality of through holes, and
    A step of forming a conductor layer over the first surface of the circuit board mother board, the inner wall of the through hole, and the second surface of the circuit board mother board in each of the plurality of circuit boards.
    An insulating paste containing an insulating material is applied and formed by covering the openings on the first surface side of the plurality of through holes, and the insulating paste covering the openings on the first surface side is applied to the mother substrate for a circuit board. The first suction step of sucking from the second surface side and
    A method for manufacturing a circuit board, comprising: after the first suction step, a second suction step of further sucking the insulating paste from the second surface side of the circuit board mother substrate.
  10. 　請求項９に記載の回路基板の製造方法であって、
    　前記第２吸引工程での吸引力は、前記第１吸引工程での吸引力よりも大きい
    　回路基板の製造方法。     The method for manufacturing a circuit board according to claim 9.
    A method for manufacturing a circuit board in which the suction force in the second suction step is larger than the suction force in the first suction step.
  11. 　請求項９又は請求項１０に記載の回路基板の製造方法であって、
    　複数の前記スルーホールに沿って、前記回路基板用母基板を分割する工程を有する
    　回路基板の製造方法。     The method for manufacturing a circuit board according to claim 9 or 10.
    A method for manufacturing a circuit board, which comprises a step of dividing a mother board for a circuit board along a plurality of through holes.
  12. 　複数の回路領域及び複数のスルーホールを有する回路基板用母基板であって、
    　複数の前記回路領域のそれぞれにおいて、
    　前記回路基板用母基板の第１面に設けられた第１導体層と、
    　前記回路基板用母基板の第２面に設けられた第２導体層と、
    　前記スルーホールの内壁に設けられ、前記第１導体層と前記第２導体層とを接続する側面導体層と、
    　少なくとも前記第２導体層と前記側面導体層との接続箇所である接続部を覆って設けられた絶縁層と、を有する
    　回路基板用母基板。     A mother board for a circuit board having a plurality of circuit areas and a plurality of through holes.
    In each of the plurality of circuit areas
    A first conductor layer provided on the first surface of the circuit board mother substrate, and
    A second conductor layer provided on the second surface of the circuit board mother substrate, and
    A side conductor layer provided on the inner wall of the through hole and connecting the first conductor layer and the second conductor layer, and
    A mother substrate for a circuit board having at least an insulating layer provided so as to cover a connection portion which is a connection portion between the second conductor layer and the side conductor layer.
  13. 　請求項１２に記載の回路基板用母基板であって、
    　前記絶縁層は、前記スルーホールの前記第２面の開口の縁部を覆って設けられる
    　回路基板用母基板。     The mother board for a circuit board according to claim 12.
    The insulating layer is a mother substrate for a circuit board provided so as to cover the edge of the opening on the second surface of the through hole.
PCT/JP2021/016645 2020-08-12 2021-04-26 Circuit board, electronic device, circuit board manufacturing method, and motherboard for circuit board WO2022034716A1 (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167396A (en) * 1984-02-09 1985-08-30 日立化成工業株式会社 Method of coating paste material on inner wall of through hole
JP2000082762A (en) * 1999-06-28 2000-03-21 Nec Corp Semiconductor device
JP2000312062A (en) * 1999-04-28 2000-11-07 Denso Corp Thick-film circuit substrate and manufacture thereof
JP2009206297A (en) * 2008-02-28 2009-09-10 Panasonic Corp Manufacturing method of printed wiring board
JP2017046341A (en) * 2015-08-25 2017-03-02 株式会社大真空 Piezoelectric device
WO2017126596A1 (en) * 2016-01-22 2017-07-27 京セラ株式会社 Electronic component storage package, multi-piece wiring substrate, electronic device, and electronic module
WO2017208747A1 (en) * 2016-05-31 2017-12-07 株式会社村田製作所 Aggregate substrate for mounting piezoelectric vibration element thereon, manufacturing method therefor, and manufacturing method for piezoelectric vibrator

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167396A (en) * 1984-02-09 1985-08-30 日立化成工業株式会社 Method of coating paste material on inner wall of through hole
JP2000312062A (en) * 1999-04-28 2000-11-07 Denso Corp Thick-film circuit substrate and manufacture thereof
JP2000082762A (en) * 1999-06-28 2000-03-21 Nec Corp Semiconductor device
JP2009206297A (en) * 2008-02-28 2009-09-10 Panasonic Corp Manufacturing method of printed wiring board
JP2017046341A (en) * 2015-08-25 2017-03-02 株式会社大真空 Piezoelectric device
WO2017126596A1 (en) * 2016-01-22 2017-07-27 京セラ株式会社 Electronic component storage package, multi-piece wiring substrate, electronic device, and electronic module
WO2017208747A1 (en) * 2016-05-31 2017-12-07 株式会社村田製作所 Aggregate substrate for mounting piezoelectric vibration element thereon, manufacturing method therefor, and manufacturing method for piezoelectric vibrator

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