WO2022033125A1 - 两端口在片校准件模型和参数确定的方法 - Google Patents

两端口在片校准件模型和参数确定的方法 Download PDF

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WO2022033125A1
WO2022033125A1 PCT/CN2021/096855 CN2021096855W WO2022033125A1 WO 2022033125 A1 WO2022033125 A1 WO 2022033125A1 CN 2021096855 W CN2021096855 W CN 2021096855W WO 2022033125 A1 WO2022033125 A1 WO 2022033125A1
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port
model
chip
chip calibration
calibration
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PCT/CN2021/096855
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English (en)
French (fr)
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王一帮
吴爱华
梁法国
刘晨
霍晔
栾鹏
孙静
李彦丽
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中国电子科技集团公司第十三研究所
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Priority claimed from CN202010820400.2A external-priority patent/CN112098795B/zh
Priority claimed from CN202010819047.6A external-priority patent/CN112098792B/zh
Application filed by 中国电子科技集团公司第十三研究所 filed Critical 中国电子科技集团公司第十三研究所
Priority to US17/550,930 priority Critical patent/US11733298B2/en
Publication of WO2022033125A1 publication Critical patent/WO2022033125A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2837—Characterising or performance testing, e.g. of frequency response
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/28—Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response
    • G01R27/32—Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response in circuits having distributed constants, e.g. having very long conductors or involving high frequencies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references

Definitions

  • the present application relates to the technical field of microwave characteristic measurement of wafer-level semiconductor devices, and in particular, to a method for determining a model and parameters of a two-port on-wafer calibration part.
  • On-chip S-parameter test system is widely used in the microelectronics industry. Before use, the on-chip S-parameter test system needs to be vector calibrated with an on-chip calibration piece. The accuracy of the calibration depends on the accuracy of the definition of the on-chip calibration piece. Different types of calibration parts (such as open-circuit calibration parts, short-circuit calibration parts, load calibration parts and through-calibration parts) have different values of the lumped parameters in the measurement model.
  • the lumped parameters generally include the delay of the bias line, characteristic impedance, series connection Resistance, Inductance, Capacitance and DC Resistance.
  • the measurement model of the traditional commercial on-chip calibrator only characterizes the single-port calibrator model. In the terahertz frequency band, due to the coupling between probes, the traditional single-port calibrator model is used to perform a two-port on-chip test system. When calibrating, errors are generated, resulting in lower calibration and test accuracy.
  • the embodiment of the present application provides a two-port on-chip calibration model and a method for parameter determination, which aims to solve the problem that errors occur when the traditional single-port calibration model is used to perform two-port calibration on an on-chip test system in the prior art. Problems leading to reduced calibration and test accuracy.
  • a first aspect of the embodiments of the present application provides a two-port on-chip calibration model, including: a first intrinsic capacitance, a first parasitic capacitance, and a first parasitic resistance;
  • the first intrinsic capacitance, the first parasitic capacitance, and the first parasitic resistance are respectively connected in parallel to form a first parallel circuit; one end of the first parallel circuit is connected to the first single-port on-chip calibration part model, and the The other end of the first parallel circuit is connected to the second one-port on-chip calibration model.
  • the first single-port on-chip calibration model and the second single-port on-chip calibration model are the same model.
  • the first single-port on-chip calibration model or the second single-port on-chip calibration model includes a crosstalk resistance and a crosstalk capacitance
  • the crosstalk capacitor and the crosstalk resistance are connected in parallel to form a second parallel circuit, and the second parallel circuit is connected in parallel to both ends of the port of the original single-port calibration piece model.
  • one end of the first parallel circuit is connected between the second parallel circuit of the first single-port in-chip calibration piece model and one end of the port of the original single-port calibration piece model, the first parallel circuit is The other end is connected between the second parallel circuit in the second single-port on-chip calibration model and one end of the port of the original single-port calibration model.
  • a second aspect of the embodiments of the present application provides a two-port on-chip calibration model, including: a second intrinsic capacitance, a second parasitic capacitance, and a second parasitic resistance;
  • the second parasitic capacitance and the second parasitic resistance are connected in series to form a first series circuit; the first series circuit and the second intrinsic capacitance are connected in parallel to form a third parallel circuit, and one end of the third parallel circuit is connected to The first single-port on-chip calibration model, and the other end of the third parallel circuit is connected to the second single-port on-chip calibration model.
  • the first single-port on-chip calibration model or the second single-port on-chip calibration model includes a crosstalk resistance R S ' and a crosstalk capacitance C S ';
  • the crosstalk resistance R S ' and the crosstalk capacitance C S ' are connected in series to form a second series circuit, and the second series circuit is connected in parallel at both ends of the port of the original single-port calibration part model; or,
  • the crosstalk resistance RS ' and the crosstalk capacitance CS ' constitute a fourth parallel circuit, and the fourth parallel circuit is connected in parallel to both ends of the port of the original single-port calibration piece model.
  • one end of the third parallel circuit is connected between the second series circuit of the first single-port on-chip calibration piece model and one end of the port of the original single-port calibration piece model, and the third parallel circuit has The other end is connected between the second series circuit in the second single-port on-chip calibration model and one end of the port of the original single-port calibration model; or,
  • One end of the third parallel circuit is connected between the fourth parallel circuit in the first single-port on-chip calibration model and one end of the port of the original single-port calibration model, and the other end of the third parallel circuit is connected Between the fourth parallel circuit in the second one-port on-chip calibrator model and one end of the port of the original single-port calibrator model.
  • a second aspect of the embodiments of the present application provides a method for parameter determination in a two-port on-chip calibration model, based on the two-port on-chip calibration model, the two-port on-chip calibration model
  • the methods of parameter determination include:
  • the intrinsic capacitance value of the two-port on-chip calibration model corresponding to the single-port on-chip calibration model is obtained by calculating according to the first S-parameter;
  • the parasitic capacitance value and the parasitic resistance value of the two-port on-chip calibration component model are obtained by calculation.
  • calculating and obtaining the intrinsic capacitance value of the two-port on-chip calibration part model according to the first S-parameter includes:
  • the first S matrix conversion is performed to obtain Y 21 in the first Y matrix
  • the intrinsic capacitance value of the two-port on-chip calibration model is obtained.
  • the first S matrix conversion is performed according to the first S matrix corresponding to the first S parameter to obtain Y 21 in the first Y matrix, including:
  • Y 21 represents Y 21 in the first Y matrix
  • S 11 , S 21 , S 12 and S 22 represent parameters in the first S matrix, respectively
  • represents the determinant of the first S matrix value.
  • the intrinsic capacitance value of the two-port on-chip calibration part model obtained by calculating according to the Y 21 includes:
  • the intrinsic capacitance value of the two-port on-chip calibration model is obtained by calculation, wherein C i represents the intrinsic capacitance value, j represents an imaginary number, and ⁇ represents the angular frequency corresponding to the first frequency band.
  • the parasitic capacitance value and the parasitic resistance value of the two-port on-chip calibration part model are calculated and obtained, including:
  • the second S matrix conversion is performed to obtain Y 21 ' in the second Y matrix
  • the parasitic capacitance value and the parasitic resistance value of the two-port on-chip calibration part model are obtained by calculation.
  • the parasitic capacitance value and the parasitic resistance value of the two-port on-chip calibration part model are calculated and obtained, including:
  • R C represents the first parasitic capacitance value
  • C C represents the first parasitic resistance value
  • w' represents the angular frequency corresponding to the terahertz frequency band.
  • the parasitic capacitance value and the parasitic resistance value of the two-port on-chip calibration part model are calculated and obtained, including:
  • R C ' represents the second parasitic capacitance value
  • CC ' represents the second parasitic resistance value
  • w' represents the angular frequency corresponding to the terahertz frequency band.
  • the present application provides a two-port on-chip calibration model and a method for determining parameters.
  • the different two-port on-chip calibration models provided by the present application solve the problem of inconsistencies in the standard circuit model in the terahertz frequency band.
  • the calibration and measurement errors brought about by the improvement can improve the test accuracy of on-chip S-parameters in the terahertz frequency band; in addition, the calculation methods of parameters in different two-port on-chip calibration models are given.
  • FIG. 1 is a schematic diagram of a two-port on-chip calibration model provided by an embodiment of the present application
  • FIG. 2(1) is a schematic diagram of a first two-port load calibration model provided by an embodiment of the present application.
  • 2(2) is a schematic diagram of a first two-port open-circuit calibration component model provided by an embodiment of the present application
  • 2(3) is a schematic diagram of a first two-port short-circuit calibration component model provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of a two-port on-chip calibration model provided by another embodiment of the present application.
  • FIG. 4(1) is a schematic diagram of a second two-port load calibration model provided by an embodiment of the present application.
  • 4(2) is a schematic diagram of a second two-port open-circuit calibration component model provided by an embodiment of the present application.
  • 4(3) is a schematic diagram of a second two-port short-circuit calibration component model provided by an embodiment of the present application.
  • 4(4) is a schematic diagram of a third two-port load calibration model provided by an embodiment of the present application.
  • 4(5) is a schematic diagram of a third two-port open-circuit calibration component model provided by an embodiment of the present application.
  • 4(6) is a schematic diagram of a third two-port short-circuit calibration component model provided by an embodiment of the present application.
  • FIG. 5 is an exemplary flowchart of a method for parameter determination in a two-port on-chip calibration model provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a two-port on-chip calibration component model provided by an embodiment of the present application. For convenience of description, only parts related to the embodiment of the present application are shown. As shown in FIG. 1 , it may include: a first intrinsic capacitance C i , a first parasitic capacitance R C and a first parasitic resistance C C ;
  • the first intrinsic capacitance C i , the first parasitic capacitance R C and the first parasitic resistance C C are respectively connected in parallel to form a first parallel circuit; one end of the first parallel circuit is connected to the first single-port on-chip The calibration piece model, the other end of the first parallel circuit is connected to the second single-port on-chip calibration piece model.
  • the first single-port on-chip calibration model and the second single-port on-chip calibration model are the same model.
  • the first single-port on-chip calibration model or the second single-port on-chip calibration model includes a crosstalk resistance R S and a crosstalk capacitance C S ;
  • the crosstalk capacitor R S and the crosstalk resistance C S are connected in parallel to form a second parallel circuit, and the second parallel circuit is connected in parallel to both ends of the port of the original single-port calibration piece model.
  • the original single-port on-chip calibration model can be a load calibration model, an open-circuit calibration model, or a short-circuit calibration model.
  • three types can be formed. There are three models of the single-port on-chip calibration model, that is, the first single-port on-chip calibration model or the second single-port on-chip calibration model.
  • the two-port on-chip calibration model may be: one end of the first parallel circuit is connected between the second parallel circuit in the first single-port on-chip calibration model and the port of the original single-port calibration model. Between one end, the other end of the first parallel circuit is connected between the second parallel circuit in the second single-port on-chip calibration model and one end of the port of the original single-port calibration model.
  • the first single-port on-chip calibrator model or the second single-port on-chip calibrator model plus the crosstalk element between the two ports, the two-port on-chip calibrator model in this embodiment is also three types, As shown in Figure 2(1)- Figure 2(3).
  • 2(1) is the first two-port load calibration model, that is, the first single-port on-chip calibration model includes the first R S , the first CS , the first load calibration inductance L load and the first load
  • the calibration element DC resistance R 1 , the first load calibration element inductance L load and the first load calibration element DC resistance R 1 are connected in series, and the first R S and the first CS are connected in parallel with the first load calibration element inductance L load and the first load calibration element inductance L load respectively.
  • the two ends of the series circuit formed by the DC resistance R of the load calibration piece are loaded, and at the same time, the second single-port on-chip calibration piece model has the same composition as the first single-port calibration piece model.
  • the first parasitic capacitance, the first parasitic resistance and the first intrinsic capacitance are respectively connected in parallel to form a first parallel circuit, and one end of the first parallel circuit is connected between the first R S (or the first C S ) and the first load calibration element inductance L Between loads , the other end of the parallel circuit is connected between the second R S (or the second C S ) and the inductance of the second load calibration element.
  • Figure 2(2) shows the first two-port open-circuit calibration part model.
  • the difference from the first two-port load calibration part model is that the first load-calibrating part inductance and the first load-calibrating part DC resistance are replaced by the open-circuit calibration part capacitance.
  • Figure 2(3) shows the first two-port short-circuit calibration part model. The difference from the first two-port load calibration part model is that the first load calibration part inductance and the first load calibration part DC resistance are replaced by the short-circuit calibration part inductance.
  • the above-mentioned two-port on-chip calibrator model by adding components representing two-port crosstalk between the two single-port on-chip calibrator models, constitutes a new two-port on-chip calibrator model, so that with the on-chip test frequency An increase in , can improve accuracy when calibrating and testing in the terahertz band.
  • FIG. 3 is a schematic diagram of another two-port on-chip calibration component model provided by an embodiment of the present application, which may include: a second intrinsic capacitance C i ', a second parasitic capacitance R C ', and a second parasitic resistance C C ';
  • the second parasitic capacitance R C ' and the second parasitic resistance C C ' are connected in series to form a first series circuit; the first series circuit is connected in parallel with the second intrinsic capacitance C i ' to form a third parallel circuit, One end of the third parallel circuit is connected to the first single-port on-chip calibration model, and the other end of the third parallel circuit is connected to the second single-port on-chip calibration model.
  • the first single-port on-chip calibration model and the second single-port on-chip calibration model are the same model.
  • the first single-port on-chip calibration model or the second single-port on-chip calibration model includes a crosstalk resistance R S ' and a crosstalk capacitance C S ';
  • the crosstalk resistance R S ' and the crosstalk capacitance C S ' are connected in series to form a second series circuit, and the second series circuit is connected in parallel at both ends of the port of the original single-port calibration part model;
  • the crosstalk resistance RS ' and the crosstalk capacitance CS ' are connected in parallel to form a fourth parallel circuit, and the fourth parallel circuit is connected in parallel to both ends of the port of the original single-port calibration piece model.
  • the original single-port on-chip calibration model can be a load calibration model, an open-circuit calibration model or a short-circuit calibration model.
  • six types of single-port calibration can be formed. There are six models in total for the on-chip calibration model, that is, the first single-port on-chip calibration model or the second single-port on-chip calibration model.
  • the two-port on-chip calibration model may be: one end of the third parallel circuit is connected between the second series circuit in the first single-port on-chip calibration model and the port of the original single-port calibration model. between one end, the other end of the third parallel circuit is connected between the second series circuit of the second single-port in-chip calibration piece model and one end of the port of the original single-port calibration piece model; or,
  • One end of the third parallel circuit is connected between the fourth parallel circuit in the first single-port on-chip calibration model and one end of the port of the original single-port calibration model, and the other end of the third parallel circuit is connected Between the fourth parallel circuit in the second one-port on-chip calibrator model and one end of the port of the original single-port calibrator model.
  • Figure 4(1)- Figure 4(3) are the two-port on-chip calibration model composed of crosstalk resistors and crosstalk capacitors in series, wherein Figure 4(1) is the second two-port load calibration model, that is, the first single-port model
  • the on-chip calibration piece model includes a first RS ', a first CS ', a first load calibration piece inductance L load and a first load calibration piece DC resistance R1, the first RS ' and the first CS ' are connected in series, The first load calibration element inductance L load and the first load calibration element DC resistance R 1 are connected in series, and then the two series circuits are connected in parallel.
  • the second single-port on-chip calibration element model has the same structure as the first single-port calibration element model.
  • the second parasitic capacitance and the second parasitic resistance are connected in series with the second intrinsic capacitance.
  • One end of the parallel circuit is connected between the first R S ' and the first load calibration element inductance L load , and the other end of the parallel circuit is connected to between the two R S ' and the second load calibration piece inductance.
  • FIG. 4(2) shows the second two-port open-circuit calibration part model.
  • the difference from the second two-port load calibration part model is that the first load-calibration part inductance and the first load-calibration part DC resistance are replaced by the open-circuit calibration part capacitance.
  • FIG. 4(3) shows the second two-port short-circuit calibration part model. The difference from the second two-port load calibration part model is that the first load calibration part inductance and the first load calibration part DC resistance are replaced by the short-circuit calibration part inductance.
  • Fig. 4(4)-Fig. 4(6) are the two-port on-chip calibration model composed of crosstalk resistors and crosstalk capacitors in parallel.
  • Fig. 4(4) is the third two-port load calibration model.
  • Fig. 4(5) is the third two-port open-circuit calibration part model, and
  • Figure 4(6) is the third two-port short-circuit calibration part model.
  • the above-mentioned two-port on-chip calibrator model by adding components representing two-port crosstalk between the two single-port on-chip calibrator models, constitutes a new two-port on-chip calibrator model, so that with the on-chip test frequency An increase in , can improve accuracy when calibrating and testing in the terahertz band.
  • the parameters in the two-port on-chip calibration model are calculated. As shown in FIG. 5, a method for determining parameters in the two-port on-chip calibration model is described in detail. as follows.
  • Step 501 Measure a single-port on-chip calibration model corresponding to the first frequency band to obtain a first S parameter.
  • the first frequency band is a low frequency band, that is, a frequency band of 40 GHz and below.
  • the obtained first S parameter may be the S parameter of the single-port load calibrator model, the S-parameter of the single-port open-circuit calibrator model, or the S-parameter of the single-port short-circuit calibrator model, and the measurement methods are the same.
  • Step 502 Calculate and obtain the intrinsic capacitance value of the two-port on-chip calibrator model corresponding to the single-port on-chip calibrator model according to the first S parameter.
  • the two-port on-chip calibration model shown in Fig. 2(1) to Fig. 2(3) refer to the two-port on-chip calibration model shown in Fig. 2(1) to Fig. 2(3).
  • the first S parameter is the S parameter of the single-port load calibration model
  • the corresponding The two-port on-chip calibration model is shown in Figure 2(1)
  • the first S-parameter is the S-parameter of the single-port open-circuit calibration model
  • the corresponding two-port on-chip calibration model is shown in Figure 2(2).
  • the S parameter is the S parameter of the single-port short-circuit calibration model
  • the corresponding two-port on-chip calibration model is shown in Figure 2(3).
  • the two-port on-chip calibration model shown in Figure 4(1)-FIG. 4(6) refers to the two-port on-chip calibration model shown in Figure 4(1)-FIG. 4(6).
  • the corresponding The two-port on-chip calibration model is shown in Figure 4(1) or Figure 4(4); when the first S parameter is the S-parameter of the single-port open-circuit calibration model, the corresponding two-port on-chip calibration model is shown in Figure 4( 2) or Fig. 4(5); when the first S-parameter is the S-parameter of the single-port short-circuit calibration model, the corresponding two-port on-chip calibration model is shown in Fig. 4(3) or Fig. 4(6).
  • the intrinsic capacitance value of the two-port on-chip calibrator model corresponding to the single-port on-chip calibrator model is calculated according to the first S parameter, it can be calculated according to the first S parameter.
  • the first S matrix is converted to the first S matrix to obtain Y 21 in the first Y matrix; the intrinsic capacitance value of the two-port on-chip calibration model is obtained by calculating according to the Y 21 .
  • the first S matrix conversion is performed according to the first S matrix corresponding to the first S parameter to obtain Y 21 in the first Y matrix, including:
  • Y 21 represents Y 21 in the first Y matrix
  • S 11 , S 21 , S 12 and S 22 represent parameters in the first S matrix, respectively
  • represents the determinant of the first S matrix value.
  • the obtained first Y matrix is also a 2 ⁇ 2 matrix, including Y 11 , Y 21 , Y 12 and Y 22 .
  • Y 21 is used for subsequent calculations.
  • the calculation to obtain the intrinsic capacitance value of the two-port on-chip calibration model may include:
  • the calculation method of the intrinsic capacitance value C i ' is the same as the calculation method of the intrinsic capacitance value C i .
  • Step 503 Measure the two-port on-chip calibration model corresponding to the terahertz frequency band to obtain a second S parameter.
  • the two-port on-chip calibration model obtained by direct measurement in the terahertz frequency band can obtain the corresponding two-port S-parameters, which are recorded as the second S-parameters.
  • the second S-parameters are also a 2 ⁇ 2 matrix, including S 11 , S 21 , S 12 and S 22 .
  • Step 504 Calculate the parasitic capacitance value and parasitic resistance value of the two-port on-chip calibration component model according to the second S parameter and the intrinsic capacitance value.
  • the second S matrix can be converted according to the second S matrix corresponding to the second S parameter to obtain Y 21 ′ in the second Y matrix ;
  • the characteristic capacitance value is calculated to obtain the parasitic capacitance value and parasitic resistance value of the two-port on-chip calibration part model.
  • the second S matrix conversion is performed to obtain the calculation method of Y 21 ′ in the second Y matrix and the calculation method of the first Y in step 503.
  • the calculation method of Y 21 in the matrix is the same, and details are not repeated here.
  • Figures 2(1)-2(3) can be regarded as a ⁇ -type network composed of three admittances, so we get to get and
  • the methods for determining parameters in the three models included in the two-port on-chip calibration model can be calculated according to the above steps 501 to 504 .
  • Figure 4(1)-4(3) or Figure 4(4)-Figure 4(6) can be regarded as a ⁇ -shaped network composed of three admittances, so we get change the form to get to get and
  • the methods for determining parameters in the six models included in the two-port on-chip calibration model can be calculated according to the above steps 501 to 504 .
  • the first S-parameter is obtained by measuring the single-port on-chip calibration model corresponding to the first frequency band; and the single-port on-chip is calculated according to the first S parameter.
  • the intrinsic capacitance value of the two-port on-chip calibrator model corresponding to the calibration part model measure the two-port on-chip calibration part model corresponding to the terahertz frequency band to obtain a second S parameter; according to the second S parameter and the The intrinsic capacitance value is calculated to obtain the parasitic capacitance value and parasitic resistance value of the two-port on-chip calibration part model.
  • the different two-port on-chip calibration component models provided in this embodiment solve the calibration and measurement errors caused by imperfect circuit models of standard components in the terahertz frequency band, and can improve the accuracy of on-chip S-parameter testing in the terahertz frequency band.
  • the calculation methods of parameters in different two-port on-chip calibration models are presented.

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Abstract

一种两端口在片校准件模型及参数确定的方法，适用于晶圆级半导体器件微波特性测量技术领域，方法包括：通过测量第一频段对应的单端口在片校准件模型，得到第一S参数（501）；根据第一S参数计算得到单端口在片校准件模型对应的两端口在片校准件模型的本征电容值（502）；测量太赫兹频段对应的两端口在片校准件模型，得到第二S参数（503）；根据第二S参数和本征电容值，计算得到两端口在片校准件模型的寄生电容值和寄生电阻值（504）。不同的两端口在片校准件模型解决了在太赫兹频段标准件电路模型不完善带来的校准及测量误差，可以提高太赫兹频段在片S参数测试准确度；另外给出了不同两端口在片校准件模型中参数的计算方法。

Description

两端口在片校准件模型和参数确定的方法
本申请要求于2020年08月14日提交中国专利局、申请号为2020108190476、发明名称为“两端口在片校准件模型和参数确定的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中，以及要求于2020年08月14日提交中国专利局、申请号为2020108204002、发明名称为“两端口在片校准件模型及参数确定的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及晶圆级半导体器件微波特性测量技术领域，尤其涉及一种两端口在片校准件模型和参数确定的方法。
背景技术
“在片S参数测试系统”广泛应用于微电子行业。在使用前，需要用在片校准件对在片S参数测试系统进行矢量校准，校准的准确与否依赖于在片校准件定义的准确程度。不同类型的校准件(例如开路校准件、短路校准件、负载校准件以及直通校准件)测量模型中的集总参数的值不同，集总参数一般包括偏置线的延时、特征阻抗、串联电阻、电感、电容和直流电阻。然而，目前传统商用在片校准件的测量模型仅表征了单端口校准件模型，在太赫兹频段，由于探针之间的耦合使得采用传统的单端口校准件模型对在片测试系统进行两端口校准时，产生误差，导致校准和测试准确度降低。
技术问题
本申请实施例提供了一种两端口在片校准件模型和参数确定的方法，旨在解决现有技术中采用传统的单端口校准件模型对在片测试系统进行两端口校准时，产生误差，导致校准和测试准确度降低的问题。
技术解决方案
为解决上述技术问题，本申请实施例的第一方面提供了一种两端口在片校准件模型，包括：第一本征电容、第一寄生电容和第一寄生电阻；
所述第一本征电容、所述第一寄生电容和所述第一寄生电阻分别并联构成第一并联电路；所述第一并联电路的一端连接第一单端口在片校准件模型，所述第一并联电路的另一端连接第二单端口在片校准件模型。
优选地，所述第一单端口在片校准件模型和所述第二单端口在片校准件模型为相同的模型。
优选地，所述第一单端口在片校准件模型或所述第二单端口在片校准件模型包括串扰电阻和串扰电容；
所述串扰电容和所述串扰电阻并联构成第二并联电路，所述第二并联电路并联在原单端口校准件模型的端口的两端。
优选地，所述第一并联电路的一端连接在所述第一单端口在片校准件模型中的第二并联电路与原单端口校准件模型的端口的一端之间，所述第一并联电路的另一端连接在所述第二单端口在片校准件模型中的第二并联电路与原单端口校准件模型的端口的一端之间。
为解决上述技术问题，本申请实施例的第二方面提供了一种两端口在片校准件模型，包括：第二本征电容、第二寄生电容和第二寄生电阻；
所述第二寄生电容和所述第二寄生电阻串联构成第一串联电路；所述第一串联电路与所述第二本征电容并联构成第三并联电路，所述第三并联电路的一端连接第一单端口在片校准件模型，所述第三并联电路的另一端连接第二单端口在片校准件模型。
优选地，所述第一单端口在片校准件模型或所述第二单端口在片校准件模型包括串扰电阻R S'和串扰电容C S'；
所述串扰电阻R S'和所述串扰电容C S'串联构成第二串联电路，所述第二串联电路并联在原单端口校准件模型的端口的两端；或者，
所述串扰电阻R S'和所述串扰电容C S'构成第四并联电路，所述第四并联电路并联在原单端口校准件模型的端口的两端。
优选地，所述第三并联电路的一端连接在所述第一单端口在片校准件模型中的第二串联电路与原单端口校准件模型的端口的一端之间，所述第三并联电路的另一端连接在所述第二单端口在片校准件模型中的第二串联电路与原单端口校准件模型的端口的一端之间；或者，
所述第三并联电路的一端连接在所述第一单端口在片校准件模型中的第四并联电路与原单端口校准件模型的端口的一端之间，所述第三并联电路的另一端连接在所述第二单端口在片校准件模型中的第四并联电路与原单端口校准件模型的端口的一端之间。
为解决上述技术问题，本申请实施例的第二方面提供了一种两端口在片校准件模型中参数确定的方法，基于两端口在片校准件模型，所述两端口在片校准件模型中参数确定的方法包括：
测量第一频段对应的单端口在片校准件模型，得到第一S参数；
根据所述第一S参数计算得到所述单端口在片校准件模型对应的两端口在片校准件模型的本征电容值；
测量太赫兹频段对应的所述两端口在片校准件模型，得到第二S参数；
根据所述第二S参数和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值。
优选地，所述根据所述第一S参数计算得到两端口在片校准件模型的本征电容值，包括：
根据所述第一S参数对应的第一S矩阵，进行第一S矩阵转换，得到第一Y矩阵中的Y 21；
根据所述Y 21计算得到两端口在片校准件模型的本征电容值。
优选地，所述根据所述第一S参数对应的第一S矩阵，进行第一S矩阵转换，得到第一Y矩阵中的Y 21，包括：
根据
Figure PCTCN2021096855-appb-000001
得到第一Y矩阵中的Y 21；
其中，Y 21表示第一Y矩阵中的Y 21，S 11、S 21、S 12和S 22分别表示所述第一S矩阵中的参数，|S|表示所述第一S矩阵的行列式值。
优选地，所述根据所述Y 21计算得到两端口在片校准件模型的本征电容值，包括：
根据
Figure PCTCN2021096855-appb-000002
计算得到两端口在片校准件模型的本征电容值，其中，C i表示所述本征电容值，j表示虚数，ω表示第一频段对应的角频率。
优选地，所述根据所述第二S参数和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值，包括：
根据所述第二S参数对应的第二S矩阵，进行第二S矩阵转换，得到第二Y矩阵中的Y 21'；
根据所述Y 21'和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值。
优选地，所述根据所述Y 21'和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值，包括：
根据
Figure PCTCN2021096855-appb-000003
计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值；
其中，R C表示第一寄生电容值，C C表示第一寄生电阻值，w'表示太赫兹频段对应的角频率。
优选地，所述根据所述Y 21'和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值，包括：
根据
Figure PCTCN2021096855-appb-000004
计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值；
其中，R C'表示第二寄生电容值，C C'表示第二寄生电阻值，w'表示太赫兹频段对应的角频率。
有益效果
本申请提供了一种两端口在片校准件模型和参数确定的方法，与现有技术相比，本申请提供的不同的两端口在片校准件模型解决了在太赫兹频段标准件电路模型不完善带来的校准及测量误差，可以提高太赫兹频段在片S参数测试准确度；另外给出了不同两端口在片校准件模型中参数的计算方法。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于 本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的两端口在片校准件模型的示意图；
图2(1)是本申请实施例提供的第一两端口负载校准件模型的示意图；
图2(2)是本申请实施例提供的第一两端口开路校准件模型的示意图；
图2(3)是本申请实施例提供的第一两端口短路校准件模型的示意图；
图3是本申请另一实施例提供的两端口在片校准件模型的示意图；
图4(1)是本申请实施例提供的第二两端口负载校准件模型的示意图；
图4(2)是本申请实施例提供的第二两端口开路校准件模型的示意图；
图4(3)是本申请实施例提供的第二两端口短路校准件模型的示意图；
图4(4)是本申请实施例提供的第三两端口负载校准件模型的示意图；
图4(5)是本申请实施例提供的第三两端口开路校准件模型的示意图；
图4(6)是本申请实施例提供的第三两端口短路校准件模型的示意图；
图5是本申请实施例提供的两端口在片校准件模型中参数确定的方法的流程示例图。
本申请的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
为了说明本申请所述的技术方案，下面通过具体实施例来进行说明。
图1是本申请一实施例提供的两端口在片校准件模型的示意图，为了便于说明，仅示出了与本申请实施例相关的部分。如图1所示，可以包括：第一本征电容C i、第一寄生电容R C和第一寄生电阻C C；
所述第一本征电容C i、所述第一寄生电容R C和所述第一寄生电阻C C分别并联构成第一并联电路；所述第一并联电路的一端连接第一单端口在片校准件模型，所述第一并联电路的另一端连接第二单端口在片校准件模型。
可选的，所述第一单端口在片校准件模型和所述第二单端口在片校准件模型为相同的模型。
可选的，所述第一单端口在片校准件模型或所述第二单端口在片校准件模型包括串扰电阻R S和串扰电容C S；
其中，所述串扰电容R S和所述串扰电阻C S并联构成第二并联电路，所述第二并联电路并联在原单端口校准件模型的端口的两端。
原单端口在片校准件模型可以为负载校准件模型、开路校准件模型或者短路校准件模型，这样，在原单端口在片校准件模型中添加串扰电阻和串扰电容的并联电路后，可以构成三种单端口在片校准件模型，即第一单端口在片校准件模型或所述第二单端口在片校准件模型共有三种模型。
可选的，两端口在片校准件模型可以为：所述第一并联电路的一端连接在所述第一单端口在片校准件模型中的第二并联电路与原单端口校准件模型的端口的一端之间，所述第一并联电路的另一端连接在所述第二单端口在片校准件模型中的第二并联电路与原单端口校准件模型的端口的一端之间。
第一单端口在片校准件模型或所述第二单端口在片校准件模型再加上两端口之间的串扰元件，本实施例中的两端口在片校准件模型也就为三种，如图2(1)-图2(3)所示。其中，图2(1)为第一两端口负载校准件模型，即第一单端口在片校准件模型包括第一R S、第一C S、第一负载校准件电感L load和第一负载校准件直流电阻R 1，第一负载校准件电感L load和第一负载校准件直流电阻R 1串联，第一R S和第一C S分别并联在第一负载校准件电感L load和第一负载校准件直流电阻R构成的串联电路的两端，同时，第二单端口在片校准件模型与第一单端口校准件模型的构成相同。第一寄生电容、第一寄生电阻与第一本征电容分别并联构成第一并联电路，第一并联电路的一端连接在第一R S(或第一C S)与第一负载校准件电感L load之间，并联电路的另一端连接在第二R S(或第二C S)与第二负载校准件电感之间。
图2(2)为第一两端口开路校准件模型，与第一两端口负载校准件模型的不同是，第一负载校准件电感和第一负载校准件直流电阻由开路校准件电容代替。图2(3)为第一两端口短路校准件模型，与第一两端口负载校准件模型的不同是，第一负载校准件电感和第一负载校准件直流电阻由短路校准件电感代替。
上述两端口在片校准件模型，通过在两个单端口在片校准件模型件之间增加表征两端口的串扰的元件，构成新的两端口在片校准件模型，使得随着在片测试频率的升高，在太赫兹频段进行校准和测试时，可以提高准确度。
图3为本申请实施例提供的另一种两端口在片校准件模型的示意图，可以包括：第二本征电容C i'、第二寄生电容R C'和第二寄生电阻C C'；
所述第二寄生电容R C'和所述第二寄生电阻C C'串联构成第一串联电路；所述第一串联电路与所述第二本征电容C i'并联构成第三并联电路，所述第三并联电路的一端连接第一单端口在片校准件模型，所述第三并联电路的另一端连接第二单端口在片校准件模型。
可选的，所述第一单端口在片校准件模型和所述第二单端口在片校准件模型为相同的模型。
可选的，所述第一单端口在片校准件模型或所述第二单端口在片校准件模型包括串扰电阻R S'和串扰电容C S'；
其中，所述串扰电阻R S'和所述串扰电容C S'串联构成第二串联电路，所述第二串联电路并联在原单端口校准件模型的端口的两端；或者，
所述串扰电阻R S'和所述串扰电容C S'并联构成第四并联电路，所述第四并联电路并联在原单端口校准件模型的端口的两端。
原单端口在片校准件模型可以为负载校准件模型、开路校准件模型或者短路校准件模型，这样，在原单端口在片校准件模型中添加串扰电阻和串扰电容后，可以构成六种单端口在片校准件模型，即第一单端口在片校准件模型或所述第二单端口在片校准件模型共有六种模型。
可选的，两端口在片校准件模型可以为：所述第三并联电路的一端连接在所述第一单端口在片校准件模型中的第二串联电路与原单端口校准件模型的端口的一端之间，所述第三并联电路的另一端连接在所述第二单端口在片校准件模型中的第二串联电路与原单端口校准件模型的端口的一端之间；或者，
所述第三并联电路的一端连接在所述第一单端口在片校准件模型中的第四并联电路与原单端口校准件模型的端口的一端之间，所述第三并联电路的另一端连接在所述第二单端口在片校准件模型中的第四并联电路与原单端口校准件模型的端口的一端之间。
第一单端口在片校准件模型或所述第二单端口在片校准件模型再加上两端口之间的串扰，本实施例中的两端口在片校准件模型也就为六种，如图4(1)-图4(6)所示。图4(1)-图4(3)为串扰电阻和串扰电容串联构成的两端口在片校准件模型，其中，图4(1)为第二两端口负载校准件模型，即第一单端口在片校准件模型包括第一R S'、第一C S'、第一负载校准件电感L load和第一负载校准件直流电阻R 1，第一R S'和第一C S'串联，第一负载校准件电感L load和第一负载校准件直流电阻R 1串联，然后两个串联电路并联，同时，第二单端 口在片校准件模型与第一单端口校准件模型的构成相同。第二寄生电容和第二寄生电阻串联后与第二本征电容并联，并联电路的一端连接在第一R S'与第一负载校准件电感L load之间，并联电路的另一端连接在第二R S'与第二负载校准件电感之间。
图4(2)为第二两端口开路校准件模型，与第二两端口负载校准件模型的不同是，第一负载校准件电感和第一负载校准件直流电阻由开路校准件电容代替。图4(3)为第二两端口短路校准件模型，与第二两端口负载校准件模型的不同是，第一负载校准件电感和第一负载校准件直流电阻由短路校准件电感代替。
图4(4)-图4(6)为串扰电阻和串扰电容并联构成的两端口在片校准件模型，其中，图4(4)为第三两端口负载校准件模型，图4(5)为第三两端口开路校准件模型，图4(6)为第三两端口短路校准件模型。
上述两端口在片校准件模型，通过在两个单端口在片校准件模型件之间增加表征两端口的串扰的元件，构成新的两端口在片校准件模型，使得随着在片测试频率的升高，在太赫兹频段进行校准和测试时，可以提高准确度。
下面根据上述任一实施例提供的两端口在片校准件模型，计算两端口在片校准件模型中的参数，如图5所示为两端口在片校准件模型中参数确定的方法，详述如下。
步骤501，测量第一频段对应的单端口在片校准件模型，得到第一S参数。
可选的，第一频段为低频段，即40GHz及以下的频段。得到的第一S参数可以为单端口负载校准件模型的S参数、单端口开路校准件模型的S参数或单端口短路校准件模型的S参数，其测量方法相同。
步骤502，根据所述第一S参数计算得到所述单端口在片校准件模型对应的两端口在片校准件模型的本征电容值。
可选的，参见图2(1)-图2(3)所示的两端口在片校准件模型，本步骤中，当第一S参数为单端口负载校准件模型的S参数，则对应的两端口在片校准件模型为图2(1)；当第一S参数为单端口开路校准件模型的S参数，则对应的两端口在片校准件模型为图2(2)；当第一S参数为单端口短路校准件模型的S参数，则对应的两端口在片校准件模型为图2(3)。
可选的，参见图4(1)-图4(6)所示的两端口在片校准件模型，本步骤中，当第一S参数为单端口负载校准件模型的S参数，则对应的两端口在片校准件模型为图4(1)或图4(4)；当第一S参数为单端口开路校准件模型的S参数，则对应的两端口在片校准件模型为图4(2)或图4(5)；当第一S参数为单端口短路校准件模型的S参数，则对应的两端口在片校准件模型为图4(3)或图4(6)。
可选的，本步骤中根据所述第一S参数计算得到所述单端口在片校准件模型对应的两端口在片校准件模型的本征电容值时，可以根据所述第一S参数对应的第一S矩阵，进行第一S矩阵转换，得到第一Y矩阵中的Y 21；根据所述Y 21计算得到两端口在片校准件模型的本征电容值。
可选的，所述根据所述第一S参数对应的第一S矩阵，进行第一S矩阵转换，得到第一Y矩阵中的Y 21，包括：
根据
Figure PCTCN2021096855-appb-000005
得到第一Y矩阵中的Y 21；
其中，Y 21表示第一Y矩阵中的Y 21，S 11、S 21、S 12和S 22分别表示所述第一S矩阵中的参数，|S|表示所述第一S矩阵的行列式值。
可选的，得到的第一Y矩阵也为2×2矩阵，包括Y 11、Y 21、Y 12和Y 22。在本实施例中仅采用其中的Y 21进行后续的计算。
可选的，所述计算得到两端口在片校准件模型的本征电容值，可以包括：
根据
Figure PCTCN2021096855-appb-000006
计算得到两端口在片校准件模型的本征电容值，其中，C i表示所述本征电容值，j表示虚数，ω表示第一频段对应的角频率，其中，ω＝2πf 1，f 1表示第一频段频率。
本征电容值C i'的计算方式与本征电容值C i的计算方式相同。
步骤503，测量太赫兹频段对应的所述两端口在片校准件模型，得到第二S参数。
在太赫兹频段直接测量得到的两端口在片校准件模型，可以得到对应的两端口S参数，记为第二S参数，第二S参数也为2×2矩阵，包括S 11、S 21、S 12和S 22。
步骤504，根据所述第二S参数和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值。
可选的，本步骤可以首先根据所述第二S参数对应的第二S矩阵，进行第二S矩阵转换，得到第二Y矩阵中的Y 21'；根据所述Y 21'和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值。
可选的，在本步骤中根据所述第二S参数对应的第二S矩阵，进行第二S矩阵转换，得到第二Y矩阵中的Y 21'的计算方法与步骤503中计算第一Y矩阵中的Y 21的计算方法相同，在此不再一一赘述。
可选的，图2(1)-2(3)可以看作由三个导纳组成的π型网络，因此得到
Figure PCTCN2021096855-appb-000007
进而得到
Figure PCTCN2021096855-appb-000008
和
Figure PCTCN2021096855-appb-000009
即根据
Figure PCTCN2021096855-appb-000010
计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值；
其中，w'表示太赫兹频段对应的角频率，其中，ω'＝2πf 2，f 2表示太赫兹频段频率，其中，R C表示第一寄生电容值，C C表示第一寄生电阻值。
两端口在片校准件模型包括的三种模型中参数确定的方法均可根据上述步骤501-步骤504计算得到。
可选的，图4(1)-4(3)或图4(4)-图4(6)可以看作由三个导纳组成的π型网络，因此得到
Figure PCTCN2021096855-appb-000011
进行形式变化，得到
Figure PCTCN2021096855-appb-000012
进而得到
Figure PCTCN2021096855-appb-000013
和
Figure PCTCN2021096855-appb-000014
即根据
Figure PCTCN2021096855-appb-000015
计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值；
其中，w'表示太赫兹频段对应的角频率，其中，ω'＝2πf 2，f 2表示太赫兹频段频率，其中，R C'表示第二寄生电容值，C C'表示第二寄生电阻值。
两端口在片校准件模型包括的六种模型中参数确定的方法均可根据上述步骤501-步骤504计算得到。
上述两端口在片校准件模型中参数确定的方法，通过测量第一频段对应的单端口在片校准件模型，得到第一S参数；根据所述第一S参数计算得到所述单端口在片校准件模型对应的两端口在片校准件模型的本征电容值；测量太赫兹频段对应的所述两端口在片校准件模型，得到第二S参数；根据所述第二S参数和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值。本实施例提供的不同的两端口在片校准件模型解决了在太赫兹频段标准件电路模型不完善带来的校准及测量误差，可以提高太赫兹频段在片S参数测试准确度；另外给出了不同两端口在片校准件模型中参数的计算方法。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (14)

  1. 一种两端口在片校准件模型，其特征在于，包括：第一本征电容、第一寄生电容和第一寄生电阻；
    所述第一本征电容、所述第一寄生电容和所述第一寄生电阻分别并联构成第一并联电路；所述第一并联电路的一端连接第一单端口在片校准件模型，所述第一并联电路的另一端连接第二单端口在片校准件模型。
  2. 如权利要求1所述的两端口在片校准件模型，其特征在于，所述第一单端口在片校准件模型和所述第二单端口在片校准件模型为相同的模型。
  3. 如权利要求2所述的两端口在片校准件模型，其特征在于，所述第一单端口在片校准件模型或所述第二单端口在片校准件模型包括串扰电阻R S和串扰电容C S；
    所述串扰电容R S和所述串扰电阻C S并联构成第二并联电路，所述第二并联电路并联在原单端口校准件模型的端口的两端。
  4. 如权利要求3所述的两端口在片校准件模型，其特征在于，所述第一并联电路的一端连接在所述第一单端口在片校准件模型中的第二并联电路与原单端口校准件模型的端口的一端之间，所述第一并联电路的另一端连接在所述第二单端口在片校准件模型中的第二并联电路与原单端口校准件模型的端口的一端之间。
  5. 一种两端口在片校准件模型，其特征在于，包括：第二本征电容、第二寄生电容和第二寄生电阻；
    所述第二寄生电容和所述第二寄生电阻串联构成第一串联电路；所述第一串联电路与所述第二本征电容并联构成第三并联电路，所述第三并联电路的一端连接第一单端口在片校准件模型，所述第三并联电路的另一端连接第二单端口在片校准件模型。
  6. 如权利要求5所述的两端口在片校准件模型，其特征在于，所述第一单端口在片校准件模型或所述第二单端口在片校准件模型包括串扰电阻R S'和串扰电容C S'；
    所述串扰电阻R S'和所述串扰电容C S'串联构成第二串联电路，所述第二串联电路并联在原单端口校准件模型的端口的两端；或者，
    所述串扰电阻R S'和所述串扰电容C S'构成第四并联电路，所述第四并联电路并联在原单端口校准件模型的端口的两端。
  7. 如权利要求6所述的两端口在片校准件模型，其特征在于，所述第三并联电路的一端连接在所述第一单端口在片校准件模型中的第二串联电路与原单端口校准件模型的端口 的一端之间，所述第三并联电路的另一端连接在所述第二单端口在片校准件模型中的第二串联电路与原单端口校准件模型的端口的一端之间；或者，
    所述第三并联电路的一端连接在所述第一单端口在片校准件模型中的第四并联电路与原单端口校准件模型的端口的一端之间，所述第三并联电路的另一端连接在所述第二单端口在片校准件模型中的第四并联电路与原单端口校准件模型的端口的一端之间。
  8. 一种两端口在片校准件模型中参数确定的方法，其特征在于，基于两端口在片校准件模型，所述两端口在片校准件模型中参数确定的方法包括：
    测量第一频段对应的单端口在片校准件模型，得到第一S参数；
    根据所述第一S参数计算得到所述单端口在片校准件模型对应的两端口在片校准件模型的本征电容值；
    测量太赫兹频段对应的所述两端口在片校准件模型，得到第二S参数；
    根据所述第二S参数和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值。
  9. 如权利要求8所述的两端口在片校准件模型中参数确定的方法，其特征在于，所述根据所述第一S参数计算得到两端口在片校准件模型的本征电容值，包括：
    根据所述第一S参数对应的第一S矩阵，进行第一S矩阵转换，得到第一Y矩阵中的Y 21；
    根据所述Y 21计算得到两端口在片校准件模型的本征电容值。
  10. 如权利要求9所述的两端口在片校准件模型中参数确定的方法，其特征在于，所述根据所述第一S参数对应的第一S矩阵，进行第一S矩阵转换，得到第一Y矩阵中的Y 21，包括：
    根据
    Figure PCTCN2021096855-appb-100001
    得到第一Y矩阵中的Y 21；
    其中，Y 21表示第一Y矩阵中的Y 21，S 11、S 21、S 12和S 22分别表示所述第一S矩阵中的参数，|S|表示所述第一S矩阵的行列式值。
  11. 如权利要求10所述的两端口在片校准件模型中参数确定的方法，其特征在于，所述根据所述Y 21计算得到两端口在片校准件模型的本征电容值，包括：
    根据
    Figure PCTCN2021096855-appb-100002
    计算得到两端口在片校准件模型的本征电容值，其中，C i表示所述本征电容值，j表示虚数，ω表示第一频段对应的角频率。
  12. 如权利要求8所述的两端口在片校准件模型中参数确定的方法，其特征在于，所述根据所述第二S参数和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值，包括：
    根据所述第二S参数对应的第二S矩阵，进行第二S矩阵转换，得到第二Y矩阵中的Y 21'；
    根据所述Y 21'和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值。
  13. 如权利要求12所述的两端口在片校准件模型中参数确定的方法，其特征在于，所述根据所述Y 21'和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值，包括：
    根据
    Figure PCTCN2021096855-appb-100003
    计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值；
    其中，R C表示第一寄生电容值，C C表示第一寄生电阻值，w'表示太赫兹频段对应的角频率。
  14. 如权利要求12所述的两端口在片校准件模型中参数确定的方法，其特征在于，所述根据所述Y 21'和所述本征电容值，计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值，包括：
    根据
    Figure PCTCN2021096855-appb-100004
    计算得到所述两端口在片校准件模型的寄生电容值和寄生电阻值；
    其中，R C'表示第二寄生电容值，C C'表示第二寄生电阻值，w'表示太赫兹频段对应的角频率。
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