WO2022030647A2 - 酸化物半導体及び酸化物半導体を含む半導体装置 - Google Patents

酸化物半導体及び酸化物半導体を含む半導体装置 Download PDF

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WO2022030647A2
WO2022030647A2 PCT/JP2021/029574 JP2021029574W WO2022030647A2 WO 2022030647 A2 WO2022030647 A2 WO 2022030647A2 JP 2021029574 W JP2021029574 W JP 2021029574W WO 2022030647 A2 WO2022030647 A2 WO 2022030647A2
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oxide semiconductor
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亮平 菅野
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Flosfia Inc
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
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    • C30B29/10—Inorganic compounds or compositions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
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    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/00—Field-effect transistors [FET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials

Definitions

  • the present invention relates to an oxide semiconductor and relates to an oxide semiconductor having p-type electrical conductivity.
  • the present invention also relates to semiconductor devices and / or systems including oxide semiconductors.
  • the present invention relates to a method for forming an oxide semiconductor having p-type electrical conductivity.
  • gallium oxide Ga 2 O 3
  • the gallium oxide can control the bandgap by mixing indium and aluminum individually or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor. ..
  • Patent Document 2 gallium oxide-based p-type semiconductors have been studied.
  • ⁇ -Ga 2 O 3 -based crystals are obtained by the FZ method using MgO (p-type dopant source). It is described that a substrate exhibiting p-type conductivity can be obtained by forming the substrate.
  • Patent Document 3 describes that a p-type dopant is ion-implanted into an ⁇ - (Al x Ga 1-x ) 2 O 3 single crystal film formed by the MBE method to form a p-type semiconductor. ..
  • Non-Patent Document 1 Non-Patent Document 1
  • a feasible p-type oxide semiconductor and a method for producing the same have been long-awaited.
  • Non-Patent Document 2 and Non-Patent Document 3 it is also considered to use, for example, Rh 2 O 3 or Zn Rh 2 O 4 for a p-type semiconductor, but Rh 2 O 3 is a method.
  • Rh 2 O 3 is a method.
  • the concentration of the raw material becomes particularly thin at the time of film formation, which affects the film formation, and it is difficult to produce a Rh 2 O 3 single crystal even if an organic solvent is used.
  • the Hall effect measurement even if the Hall effect measurement is performed, it is not determined to be p-type, and there is a problem that the measurement itself is not possible.
  • the Hall coefficient is the measurement limit (0.2 cm 3 /). C) There were only the following, and it was not usable at all. Further, since ZnRh 2 O 4 has low mobility and a narrow band gap, there is a problem that it cannot be used for LEDs and power devices, and these are not always satisfactory.
  • Patent Document 4 describes that delafosite, oxycalcogenide, etc. are used as a p-type semiconductor.
  • these semiconductors have a mobility of about 1 cm 2 / V ⁇ s or less, poor electrical characteristics, and a narrow bandgap. Therefore, n-type next-generation oxides such as ⁇ -Ga 2 O 3 are present.
  • pn junctions with semiconductors could not be performed well.
  • Patent Document 5 describes that Ir 2 O 3 is used as an iridium catalyst.
  • Patent Document 6 describes that Ir 2 O 3 is used as a dielectric.
  • Patent Document 7 describes that Ir 2 O 3 is used for the electrode.
  • Patent Documents 8 to 11 Further, regarding the mixed crystal of Ir 2 O 3 and the oxide of Group 13 of the Periodic Table, a sufficiently satisfactory one has not been obtained yet. For example, a mixed crystal of a p-type oxide having a band gap of 3.4 eV or more is obtained. Akira was long-awaited.
  • the present inventors have used a cold wall type solution containing both an organic complex of the 9th metal of the periodic table and an organic complex of the 13th metal of the periodic table. It is a mixed crystal containing two or more metals, which was difficult in the past when the film was formed by the mist CVD device of the above.
  • the mixed crystal containing at least a second metal selected from Group 13 is contained as a main component, and the second metal occupies 40% or more in atomic ratio in all the metals contained in the mixed crystal. It was found that it is possible to form an oxide semiconductor having p-type electrical conductivity, and it was found that such an oxide semiconductor can solve the above-mentioned conventional problems at once. I found it.
  • the present invention relates to the following invention.
  • the second metal occupies 40% or more of the atomic ratio of all the metals contained in the mixed crystal, and has p-type electrical conductivity.
  • the semiconductor device according to any one of [9] to [13], wherein the n-type oxide semiconductor contains an n-type ⁇ -Ga 2 O 3 .
  • the oxide semiconductor of the present invention is industrially useful and has excellent semiconductor characteristics.
  • FIG. 1 It is a schematic block diagram of the film forming apparatus (mist CVD apparatus) used in an Example.
  • the gallium to iridium ratio in the raw material solution in the examples, the gallium ratio (%) and the iridium ratio (%) in the film of the obtained crystalline oxide semiconductor, and the semiconductor type are shown.
  • FIG. 3 The horizontal axis represents the diffraction angle (deg.), And the vertical axis represents the diffraction intensity (cps).
  • SBD Schottky barrier diode
  • HEMT high electron mobility transistor
  • PWM metal oxide film semiconductor field effect transistor
  • JFET junction field effect transistor
  • IGBT insulated gate type bipolar transistor
  • LED light emitting element
  • LED light emitting element
  • PWM metal oxide film semiconductor field effect transistor
  • HBT heterojunction type bipolar transistor
  • PWM metal oxide film semiconductor field effect transistor
  • the oxide semiconductor having p-type electric conductivity is a metal containing two or more metals. Contains mixed crystals of oxides as the main component.
  • the mixed crystal contains at least a first metal selected from Group 9 of the Periodic Table and a second metal selected from Group 13 of the Periodic Table. In all the metals contained in the mixed crystal, the second metal occupies 40% or more in atomic ratio.
  • the oxide semiconductor may have a film shape.
  • "having p-type electrical conductivity" means that the electrical conductive type determined by the Hall effect measurement is p-type.
  • the mixed crystals contained in the oxide semiconductor having p-type electric conductivity are present. It preferably has a corundum structure.
  • the "mixed crystal having a corundum structure” means a crystal of a metal oxide containing at least two kinds of metals, and the crystal structure as the mixed crystal has a corundum structure. Further, in the embodiment of the present invention, it is preferable that the mixed crystal is a single crystal film.
  • Main of the oxide semiconductor having p-type electrical conductivity (hereinafter, also referred to as "p-type oxide semiconductor", “p-type oxide semiconductor film” and / or “p-type oxide semiconductor layer”).
  • p-type oxide semiconductor p-type oxide semiconductor film
  • p-type oxide semiconductor layer p-type oxide semiconductor layer
  • the mixed crystal contained as a component at least one metal selected from Group 9 of the periodic table is used as the first metal, and at least one metal selected from Group 13 of the periodic table is used as the second metal. It is not particularly limited as long as it is a mixed crystal of a metal oxide contained as a metal. In the embodiment of the present invention, it is preferable that the mixed crystal has a corundum structure.
  • the "main component” means that the mixed crystal metal oxide has an atomic ratio of preferably 50% or more, more preferably 70% or more, still more preferably 90, based on all the components of the p-type oxide semiconductor film. It means that it is contained in% or more, and it means that it may be 100%.
  • the oxide semiconductor having p-type electric conductivity is selected from cobalt (Co), rhodium (Rh), and iridium (Ir) as the first metal.
  • the second metal it is preferable to contain a mixed crystal of a metal oxide containing a metal selected from aluminum (Al), gallium (Ga), and indium (In) as a main component.
  • Metal oxide containing iridium and gallium refers to one containing iridium element, gallium element and oxygen, but in the present invention, Ir 1-x Ga x O 3 (0.4 ⁇ X). ⁇ 1) is preferable, and ⁇ -Ir 1-x Ga x O 3 (0.4 ⁇ X ⁇ 1) is more preferable.
  • the second metal is not particularly limited as long as it occupies 40% or more in atomic ratio in all the metals contained in the mixed crystal, but in the embodiment of the present invention, the mixed crystal is used. It is preferable that the second metal (for example, gallium or the like) is in the range of 40% or more and 70% or less in atomic ratio among all the metals contained in. By setting the content of the second metal in such a preferable range, an oxide semiconductor having p-type electrical conductivity and a higher bandgap was obtained. In this case, in all the metals contained in the mixed crystal, the first metal is in the range of 30% or more and 60% or less in atomic ratio.
  • Such mixed crystals are excellent in heat resistance of p-type semiconductor characteristics, they can be applied industrially advantageously to power devices and the like, as well as band gaps such as gallium oxide or mixed crystals thereof. By combining with a large n-type oxide semiconductor, the electrical characteristics and reliability of the semiconductor device can be further improved.
  • Periodic Table means the Periodic Table defined by the International Union of Pure and Applied Chemistry (IUPAC).
  • the “Group 2 metal” may be any Group 2 metal in the periodic table, and examples of the Group 2 metal include beryllium (Be), magnesium (Mg), calcium (Ca), and strontium (C). Sr), barium (Ba) or two or more of these metals and the like can be mentioned.
  • the “Group 9 metal” may be any Group 9 metal in the periodic table, and examples of such Group 9 metal include iridium (Ir), cobalt (Co), rhodium (Rh) or these. Two or more kinds of metals and the like can be mentioned.
  • the “group 13 metal” is not particularly limited as long as it is a group 13 metal in the periodic table, and examples of the group 13 metal include aluminum (Al), gallium (Ga), indium (In), and the like. Talium (Tl) or two or more kinds of metals thereof and the like can be mentioned, but in the present invention, one kind or two or more kinds selected from aluminum (Al), gallium (Ga) and indium (In) are preferable.
  • the p-type oxide semiconductor of the present invention is preferably obtained by the following method, but such a method for producing a p-type oxide semiconductor is also novel and useful, and is included as one of the present inventions.
  • the method for producing a p-type oxide semiconductor is a method for producing a p-type electrically conductive oxide semiconductor containing a mixed crystal of a metal oxide as a main component, for example, FIG. 1.
  • a raw material solution containing iridium and gallium is atomized to suspend droplets to generate atomized droplets (including mist) (atomization step), and carriers are used.
  • the atomized droplets are conveyed to the surface of the substrate by the gas (transportation step), and then the atomized droplets are thermally reacted to form a metal oxide containing iridium and gallium on the surface of the substrate. It is characterized by forming mixed crystals (film forming process).
  • the atomization step atomizes a raw material solution containing at least two metals, iridium and gallium.
  • the raw material solution may further contain other metals if desired.
  • the atomization method is not particularly limited as long as the raw material solution can be atomized, and may be a known method, but in the present invention, the atomization method using ultrasonic waves is preferable.
  • Atomized droplets obtained using ultrasonic waves are preferable because they have a zero initial velocity and float in the air. For example, instead of spraying like a spray, they float in space and are transported as a gas. It is very suitable because it is a possible atomized droplet and is not damaged by collision energy.
  • the size of the atomized droplet is not particularly limited and may be about several mm, but is preferably 50 ⁇ m or less, and more preferably 100 nm to 10 ⁇ m.
  • the raw material solution is not particularly limited as long as it contains iridium and gallium, and may contain an inorganic material or an organic material. Further, the raw material solution may further contain other metals, if desired. When the raw material solution contains iridium and gallium and other metals, the other metals are group 2 metals in the periodic table, group 9 metals other than iridium and / or group 13 metals other than gallium. Is preferable. Further, the raw material solution may contain iridium and gallium, or the raw material solution containing iridium and the raw material solution containing gallium are separately subjected to an atomization step and subjected to a transfer step or a film forming step.
  • the iridium-containing atomized droplets and the gallium-containing atomized droplets obtained from the respective raw material solutions may be merged.
  • iridium and, if desired, other metals dissolved or dispersed in an organic solvent or water in the form of a complex or salt can be suitably used as the raw material solution.
  • the form of the complex include an acetylacetonate complex, a carbonyl complex, an ammine complex, and a hydride complex.
  • the salt form examples include organic metal salts (for example, metal acetate, metal oxalate, metal citrate, etc.), metal sulfide salts, nitrified metal salts, phosphorylated metal salts, and halogenated metal salts (for example, metal chloride). Salts, metal bromide salts, metal iodide salts, etc.) and the like. According to the mist CVD method used in the embodiment of the present invention, a film can be suitably formed even if the raw material concentration is low.
  • the solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solution of an inorganic solvent and an organic solvent.
  • the solvent preferably contains water, and it is also preferable that the solvent is a mixed solvent of water and acid. More specific examples of the water include pure water, ultrapure water, tap water, well water, mineral spring water, mineral water, hot spring water, spring water, fresh water, seawater, and the like. Ultrapure water is preferred.
  • the acid includes organic acids such as acetic acid, propionic acid, and butanoic acid; boron trifluoride, boron trifluoride etherate, boron trichloride, boron tribromide, and trifluoroacetic acid. , Trifluoromethanesulfonic acid, p-toluenesulfonic acid and the like, but in the embodiment of the present invention, acetic acid is preferable.
  • the substrate is not particularly limited as long as it can support the p-type oxide semiconductor.
  • the material of the substrate is not particularly limited as long as it does not impair the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound.
  • the shape of the substrate may be any shape and is effective for any shape, for example, plate-like, fibrous, rod-like, columnar, prismatic, such as a flat plate or a disk. Cylindrical, spiral, spherical, ring-shaped and the like can be mentioned, but in the present invention, a substrate is preferable.
  • the thickness of the substrate is not particularly limited in the present invention. Further, as the substrate, another layer such as a buffer layer may be laminated on the substrate as described later. A semiconductor layer having different electric conductivity may be included and used as a substrate.
  • the substrate is not particularly limited as long as it has a plate shape and serves as a support for the p-type oxide semiconductor. It may be an insulator substrate, a semiconductor substrate, or a conductive substrate, but the substrate is preferably an insulator substrate and has a metal film on the surface. It is also preferable that it is a substrate. Preferred examples of the substrate include a substrate having a corundum structure.
  • the substrate material is not particularly limited and may be known as long as it does not interfere with the object of the present invention.
  • the substrate having the corundum structure examples include a base substrate containing a substrate material having a corundum structure as a main component, and more specifically, for example, a sapphire substrate (preferably a c-plane sapphire substrate) or an ⁇ -type substrate.
  • a gallium oxide substrate examples include a gallium oxide substrate.
  • the "main component” means that the substrate material having the specific crystal structure has an atomic ratio of preferably 50% or more, more preferably 70% or more, still more preferably 90% with respect to all the components of the substrate material. It means that it is contained in% or more, and it means that it may be 100%.
  • the mist is transferred to the substrate by the carrier gas.
  • the type of carrier gas is not particularly limited as long as the object of the present invention is not impaired, and examples thereof include an inert gas such as oxygen, ozone, nitrogen and argon, and a reducing gas such as hydrogen gas and forming gas.
  • the carrier gas in which oxygen is used include air, oxygen gas, ozone gas and the like, but oxygen gas and / or ozone gas is particularly preferable.
  • the type of the carrier gas may be one type, but may be two or more types, and a diluted gas having a changed carrier gas concentration (for example, a 10-fold diluted gas or the like) may be used as the second carrier gas. Further may be used. Further, the carrier gas may be supplied not only at one place but also at two or more places.
  • the carrier gas is preferably provided in the atomization chamber. It is more preferable to provide a supply point for the diluted gas and to provide a supply point for the diluted gas in the supply pipe.
  • the flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, more preferably 1 to 10 L / min.
  • the flow rate of the diluted gas is preferably 0.001 to 2 L / min, more preferably 0.1 to 1 L / min.
  • the mist is reacted in the vicinity of the surface of the substrate to form a film on a part or all of the surface of the substrate.
  • the thermal reaction is not particularly limited as long as it is a thermal reaction in which a film is formed from the atomized droplets, and it may be sufficient if the mist reacts with heat, as long as the reaction conditions and the like do not hinder the object of the present invention. Not particularly limited.
  • the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high or lower. In the present invention, the thermal reaction is preferably carried out at 1200 ° C.
  • the thermal reaction may be carried out under any of vacuum, non-oxygenic atmosphere, reducing gas atmosphere and oxidizing atmosphere as long as the object of the present invention is not impaired, and the thermal reaction may be carried out under atmospheric pressure or pressure. It may be carried out under either reduced pressure or reduced pressure, but in the present invention, it is preferably carried out under an oxidizing atmosphere, preferably under atmospheric pressure, and under an oxidizing atmosphere and under atmospheric pressure. It is more preferable to be carried out in.
  • the "oxidizing atmosphere” is not particularly limited as long as it is an atmosphere in which crystals or mixed crystals of a metal oxide containing iridium can be formed by the thermal reaction.
  • a carrier gas containing oxygen or a mist composed of a raw material solution containing an oxidizing agent may be used to create an oxidizing atmosphere.
  • the film thickness can be set by adjusting the film forming time, and in the present invention, the film thickness is preferably 1 nm to 1 mm, and the semiconductor characteristics are more preferably 1 nm to 100 ⁇ m. It is more preferable because it improves, and most preferably 1 nm to 10 ⁇ m.
  • a film may be formed on the substrate as it is, but a semiconductor layer different from the p-type oxide semiconductor layer (for example, an n-type semiconductor layer or an n + type semiconductor layer) may be formed on the substrate as it is. , N-type semiconductor layer and the like), an insulator layer (including a semi-insulator layer), a buffer layer and the like may be laminated, and then a film may be formed on the substrate via the other layer.
  • the semiconductor layer and the insulator layer include a semiconductor layer and an insulator layer containing the Group 13 metal.
  • a semiconductor layer containing a corundum structure, an insulator layer, a conductor layer, or the like can be mentioned as a suitable example.
  • the semiconductor layer containing the corundum structure include ⁇ -Fe 2 O 3 , ⁇ -Ga 2 O 3 , and ⁇ -Al 2 O 3 .
  • the method for laminating the buffer layer is not particularly limited, and may be the same as the method for forming the p-type oxide semiconductor. In the present invention, it is preferable to form the n-type semiconductor layer before or after the p-type semiconductor layer is formed.
  • the n-type semiconductor layer preferably contains an oxide semiconductor as a main component, and is a group 2 metal (for example, Be, Mg, Ca, Sr, Ba, etc.) and a group 9 metal (for example, Co, Rh) in the periodic table. , Ir, etc.) or an oxide semiconductor containing a Group 13 metal (for example, Al, Ga, In, Tl, etc.) as a main component.
  • a group 2 metal for example, Be, Mg, Ca, Sr, Ba, etc.
  • a group 9 metal for example, Co, Rh
  • the n-type semiconductor layer preferably contains a crystalline oxide semiconductor as a main component, more preferably contains a crystalline oxide semiconductor containing Ga as a main component, has a corundum structure, and contains Ga. Most preferably, the main component is a crystalline oxide semiconductor. Further, in the present invention, the lattice constant difference between the oxide semiconductor which is the main component of the n-type semiconductor and the p-type oxide semiconductor is 1.0% or less, which also forms a good pn junction. It is preferable, and it is more preferably 0.3% or less.
  • the "lattice constant difference” is a value obtained by subtracting the lattice constant of the p-type oxide semiconductor from the lattice constant of the oxide semiconductor which is the main component of the n-type semiconductor of the p-type oxide semiconductor. It is defined as a value (%) obtained by multiplying the absolute value of the value divided by the lattice constant by 100.
  • An example of the case where the lattice constant difference is 1.0% or less is the case where the p-type oxide semiconductor has a corundum structure and the oxide semiconductor which is the main component of the n-type semiconductor also has a corundum structure.
  • the p-type oxide semiconductor is a single crystal or a mixed crystal of Ir 2 O 3
  • the oxide semiconductor which is the main component of the n-type semiconductor is a single Ga 2 O 3 .
  • the case where it is a crystal or a mixed crystal is mentioned.
  • the n-type semiconductor layer before or after the formation of the p-type semiconductor layer. More specifically, in the method for manufacturing the semiconductor device, it is preferable to include at least a step of laminating a p-type semiconductor layer and an n-type semiconductor layer.
  • the method for forming the n-type semiconductor layer is not particularly limited and may be a known method, but in the present invention, the mist CVD method is preferable.
  • the n-type semiconductor layer preferably contains an oxide semiconductor as a main component, and the oxide semiconductor containing a Group 13 metal (for example, Al, Ga, In, Tl, etc.) in the periodic table is the main component. More preferred.
  • the n-type semiconductor layer preferably contains a crystalline oxide semiconductor as a main component, more preferably contains a crystalline oxide semiconductor containing Ga as a main component, has a corundum structure, and contains Ga. Most preferably, the main component is a crystalline oxide semiconductor. Further, in the present invention, the lattice constant difference between the oxide semiconductor which is the main component of the n-type semiconductor and the p-type oxide semiconductor is 1.0% or less, which also forms a good pn junction. It is preferable, and it is more preferably 0.3% or less.
  • the "lattice constant difference” is a value obtained by subtracting the lattice constant of the p-type oxide semiconductor from the lattice constant of the oxide semiconductor which is the main component of the n-type semiconductor of the p-type oxide semiconductor. It is defined as a value (%) obtained by multiplying the absolute value of the value divided by the lattice constant by 100.
  • An example of the case where the lattice constant difference is 1.0% or less is the case where the p-type oxide semiconductor has a corundum structure and the oxide semiconductor which is the main component of the n-type semiconductor also has a corundum structure.
  • the p-type oxide semiconductor is a single crystal or a mixed crystal of Ir 2 O 3
  • the oxide semiconductor which is the main component of the n-type semiconductor is a single Ga 2 O 3 .
  • the "main component” contains the oxide semiconductor in an atomic ratio of preferably 50% or more, more preferably 70% or more, still more preferably 90% or more with respect to all the components of the n-type semiconductor layer. It means that it may be 100%.
  • the p-type oxide semiconductor is preferably a single crystal.
  • the p-type oxide semiconductor film obtained by the above-mentioned suitable forming method is industrially useful and has excellent electrical characteristics. More specifically, the mobility is usually 1.0 cm 2 / V ⁇ s or more.
  • the mobility refers to the mobility obtained by measuring the Hall effect, and in the embodiment of the present invention, the mobility is preferably 3.0 cm 2 / Vs or more.
  • the p-type oxide semiconductor film has a carrier density of 8.0 ⁇ 10 20 / cm 3 or more.
  • the carrier density refers to the carrier density in the semiconductor film obtained by the Hall effect measurement.
  • the lower limit of the carrier density is not particularly limited, but is preferably about 1.0 ⁇ 10 15 / cm 3 or more, and more preferably about 1.0 ⁇ 10 17 / cm 3 or more.
  • the carrier density is 1.0 ⁇ 10 16 / cm 3 to 1.0 ⁇ 10 20 / cm 3 by adjusting the type and amount of the dopant, the mixed crystal material, and the content thereof. It can be easily controlled within the range of.
  • the p-type oxide semiconductor film obtained as described above can be used in a semiconductor device as a p-type semiconductor layer, and is particularly useful for power devices.
  • a semiconductor device By using the p-type oxide semiconductor film in a semiconductor device, roughness scattering can be suppressed and the channel mobility of the semiconductor device can be improved.
  • Semiconductor devices are classified into horizontal elements (horizontal devices) in which electrodes are formed on one side of the semiconductor layer, and vertical elements (vertical devices) in which electrodes are provided on both the front and back sides of the semiconductor layer. In the present invention, it can be suitably used for both horizontal and vertical devices, but it is particularly preferable to use it for vertical devices.
  • Examples of the semiconductor device include a shot key barrier diode (SBD), a junction barrier shot key diode (JBS), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), and a metal oxide film semiconductor field effect transistor. (MOSFET), electrostatic induction transistor (SIT), junction field effect transistor (JFET), isolated gate type bipolar transistor (IGBT), light emitting diode and the like.
  • SBD shot key barrier diode
  • JBS junction barrier shot key diode
  • MESFET metal semiconductor field effect transistor
  • HEMT high electron mobility transistor
  • MOSFET metal oxide film semiconductor field effect transistor
  • MOSFET electrostatic induction transistor
  • JFET junction field effect transistor
  • IGBT isolated gate type bipolar transistor
  • Figures 4 to 10 show examples of using the p-type oxide semiconductor film for the p-type semiconductor layer.
  • the n-type semiconductor may have the same main component as the p-type oxide semiconductor and may contain an n-type dopant, or may be an n-type semiconductor having a different main component and the like from the p-type oxide semiconductor. May be good. Further, the n-type semiconductor is appropriately used as an n-type semiconductor layer, an n + type semiconductor layer, or the like by adjusting the content of the n-type dopant, for example.
  • FIG. 4 shows a semiconductor device as one of the embodiments of the present invention.
  • the semiconductor device in the present embodiment includes a n-type semiconductor layer 101a, an n + type semiconductor layer 101b, a p-type semiconductor layer 102, a metal layer 103, an insulator layer 104, a Schottky electrode 105a, and a Schottky electrode 105b.
  • a suitable example of a barrier diode (SBD) is shown.
  • the SBD of FIG. 4 has a trench 70 having an arc portion, and the p-type semiconductor layer 102 is embedded in the trench 70.
  • An arc portion 70c is provided between the bottom surface 70a and the side surface 70b of the trench 70, the radius of curvature of the arc portion is within the range of 100 nm to 500 nm, the electric field relaxation effect is excellent, and the on-resistance is lowered. Can be done.
  • the depletion layer (not shown) satisfactorily spreads in the n-type semiconductor layer 101a as the crystalline oxide semiconductor layer due to the stress relaxation action of the arc portion of the trench 70. Therefore, the SBD has a high withstand voltage.
  • the ohmic electrode 105b located on the opposite second surface side of the first surface side of the crystalline oxide semiconductor layer is located on the first surface side of the crystalline oxide semiconductor layer. Electrons flow to the shot key electrode 105a.
  • the SBD using the semiconductor structure in this way is excellent for high withstand voltage and large current, has a high switching speed, and is also excellent in withstand voltage and reliability.
  • the metal layer 103 is made of a metal such as Al and covers the Schottky electrode 105a.
  • the p-type semiconductor layer 102 is a mixed crystal containing two or more metals, and is selected from the first metal selected from Group 9 of the Periodic Table and Group 13 of the Periodic Table.
  • the p-type mixed crystal contains the mixed crystal containing at least the second metal to be used as a main component, and the p-type mixed crystal has a corundum structure.
  • the n-type semiconductor layer 101 contains gallium oxide having a corundum structure as a main component
  • the p-type semiconductor layer 102 arranged on the n-type semiconductor layer 101 also has a corundum structure and contains gallium oxide. Since the main component is crystals, a laminated structure of semiconductors with high affinity can be obtained. In addition, the heat resistance of the p-type semiconductor layer is improved.
  • FIG. 5 shows a semiconductor device as one of the embodiments of the present invention.
  • the semiconductor device in this embodiment includes an n-type semiconductor layer 121a with a wide band gap, an n-type semiconductor layer 121b with a narrow band gap, an n + type semiconductor layer 121c, a p-type semiconductor layer 123, a gate electrode 125a, a source electrode 125b, and a drain electrode.
  • HEMT high electron mobility transistor
  • the p-type semiconductor layer 123 contains a mixed crystal containing at least iridium and gallium as a main component, and the mixed crystal has a corundum structure.
  • the p-type semiconductor layer 123 is arranged in contact with the n + type semiconductor layer 121c.
  • the n + type semiconductor layer 121c contains gallium oxide having a corundum structure as a main component
  • the p-type semiconductor layer 123 arranged in contact with the n + type semiconductor layer 121c also has a corundum structure and contains gallium oxide. Since the main component is a crystal, a semiconductor device having a laminated structure of semiconductors having high affinity can be obtained.
  • the material of the Schottky electrode and the ohmic electrode may be a known electrode material, and the electrode material may be, for example, Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, etc.
  • Metals such as Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), oxidation.
  • metal oxide conductive films such as indium tin oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof.
  • the Schottky electrode and the ohmic electrode can be formed by a known method such as a vacuum vapor deposition method or a sputtering method. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are laminated, and the layer made of Mo and the layer made of Al are patterned using a photolithography method. It can be done by.
  • the material of the insulator layer examples include GaO, AlGaO, InAlGaO, AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, Al 2 O 3 , MgO, GdO, SiO 2 or Si 3 N 4 .
  • the insulator layer can be formed by a known method such as a sputtering method, a vacuum vapor deposition method, or a CVD method.
  • FIG. 6 shows a semiconductor device as one of the embodiments of the present invention.
  • the semiconductor device in this embodiment is a trench-type MOSFET, which is an n-type semiconductor layer 131a, a first n + type semiconductor layer 131b, a second n + type semiconductor layer 131c, a p-type semiconductor layer 132, and a p + type semiconductor.
  • MOSFET metal oxide semiconductor field effect transistor
  • a plurality of depths that penetrate the first n + semiconductor layer 131c and reach halfway through the n-type semiconductor layer 131a A groove is formed as the trench 70 of the above.
  • Each of the trenches 70 is provided with the arc portion 70c between the bottom surface 70b and the side surface 70a of the trench 70.
  • a gate electrode 135a is embedded and formed via a gate insulating film 134 having a thickness of 10 nm to 1 ⁇ m.
  • the p + type semiconductor layer 132a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132.
  • the p-type semiconductor layer 132 contains a mixed crystal containing at least iridium and gallium as a main component, and the mixed crystal has a corundum structure.
  • the p + type semiconductor layer 132a may also contain a mixed crystal containing at least iridium and gallium as a main component, and the mixed crystal may have a corundum structure.
  • the p-type semiconductor layer 131c and / or the p + -type semiconductor layer 132a is arranged in contact with the n + -type semiconductor layer 121c and / or the n-type semiconductor layer 131a having a corundum structure.
  • the n + type semiconductor layer 121c and / or the n-type semiconductor layer 131a contains a crystal containing gallium oxide having a corundum structure as a main component
  • the p-type semiconductor layer 131c and the p + type semiconductor layer 132a also have a corundum structure. Since the main component is a mixed crystal containing gallium oxide, a semiconductor device having a laminated structure of semiconductors having high affinity can be obtained.
  • FIG. 7 shows a semiconductor device as one of the embodiments of the present invention.
  • the semiconductor device in this embodiment includes an n-type semiconductor layer 141a, a first n + type semiconductor layer 141b, a second n + type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b and a drain electrode 145c.
  • JFET junction field effect transistor
  • the p-type semiconductor layer 142 contains a mixed crystal containing at least iridium and gallium as a main component, and the mixed crystal has a corundum structure.
  • the p-type semiconductor layer 142 is arranged in contact with the n-type semiconductor layer 141a and the first n + type semiconductor layer 141b.
  • the n-type semiconductor layer 141a and / or the first n + type semiconductor layer 141b contains gallium oxide having a corundum structure as a main component, it comes into contact with the n-type semiconductor layer 141a and the first n + type semiconductor layer 141b. Since the p-type semiconductor layer 123 also includes a corundum structure and contains a mixed crystal containing gallium oxide as a main component, a semiconductor device having a laminated structure of semiconductors having a high affinity can be obtained.
  • FIG. 9 shows an example of the case where the semiconductor device of the present invention is a light emitting diode (LED).
  • the semiconductor light emitting device of FIG. 9 includes an n-type semiconductor layer 161 on the second electrode 165b, and a light emitting layer 163 is laminated on the n-type semiconductor layer 161.
  • a p-type semiconductor layer 162 is laminated on the light emitting layer 163.
  • a translucent electrode 167 that transmits light generated by the light emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is laminated on the translucent electrode 167.
  • the light emitting body used for the light emitting layer may be a known one.
  • the p-type semiconductor layer 162 contains a mixed crystal containing at least iridium and gallium as a main component, and the mixed crystal has a corundum structure.
  • the layer arranged in contact with the p-type semiconductor layer 162 contains a corundum structure and / or gallium oxide as a main component, a semiconductor device having a laminated structure of semiconductors having high affinity can be obtained.
  • the material of the translucent electrode examples include a conductive material of an oxide containing indium (In) or titanium (Ti). More specifically, for example, In 2 O 3 , ZnO, SnO 2 , Ga 2 O 3 , TIO 2 , CeO 2 or a mixed crystal of two or more of these, or those doped with these can be mentioned.
  • a translucent electrode can be formed. Further, after forming the translucent electrode, thermal annealing may be performed for the purpose of making the translucent electrode transparent.
  • the first electrode 165a is used as a positive electrode and the second electrode 165b is used as a negative electrode, and a current is passed through both of them to the p-type semiconductor layer 162, the light emitting layer 163, and the n-type semiconductor layer 161. As a result, the light emitting layer 163 emits light.
  • the materials of the first electrode 165a and the second electrode 165b include, for example, Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, and the like.
  • Metals such as Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys thereof, metal oxides such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) and indium zinc oxide (IZO). Examples thereof include conductive films, organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof.
  • the film forming method of the electrode is not particularly limited, and is a wet method such as a printing method, a spray method, a coating method, a physical method such as a vacuum vapor deposition method, a sputtering method, and an ion plating method, CVD, and plasma CVD. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from chemical methods such as a method.
  • an n-type semiconductor layer 161 is laminated on a substrate 169, and an n-type semiconductor exposed by cutting out a part of a p-type semiconductor layer 162, a light emitting layer 163, and an n-type semiconductor layer 161.
  • the second electrode 165b is laminated on a part of the exposed surface of the semiconductor layer of the layer 161.
  • FIG. 14 shows an example of the case where the semiconductor device of the present invention is a heterojunction bipolar transistor (HBT).
  • the HBT in FIG. 14 can have either an npn structure or a pnp structure.
  • the npn structure will be described in detail, but the same applies to the pnp structure, and the p-type layer having the npn structure can be replaced with the n-type layer having the pnp structure, and vice versa.
  • the substrate 60 may be a semi-insulating substrate and may have a high resistivity ( eg, a resistivity of more than 105 ⁇ cm).
  • the substrate 60 may be n-type.
  • a collector layer 42 is formed above the substrate 60.
  • the collector layer 42 has a thickness of, for example, 200 nm to 100 ⁇ m, more preferably 400 nm to 20 ⁇ m.
  • the collector layer 42 preferably contains an n-type oxide semiconductor having a corundum structure as a main component, and the n-type oxide semiconductor is a Group 2 metal (for example, Be, Mg, Ca, Sr, Ba) in the periodic table. Etc.), Group 9 metals (eg Co, Rh, Ir, etc.) or Group 13 metals (eg Al, Ga, In, Tl, etc.) are more preferably contained as main components, and aluminum, indium, etc.
  • Group 2 metal for example, Be, Mg, Ca, Sr, Ba
  • Etc. Group 9 metals
  • Group 13 metals eg Al, Ga, In, Tl, etc.
  • the concentration of the dopant (for example, tin, germanium, silicon, titanium, etc.) in the n-type oxide semiconductor is usually about 1 ⁇ 10 16 / cm 3 to 1 ⁇ 10 22 / cm. Although it is 3 , for example, it can be made into an n-type semiconductor at a low concentration of about 1 ⁇ 10 17 / cm 3 or less. Further, according to the present invention, it can be contained in a high concentration of about 1 ⁇ 10 20 / cm 3 or more to form an n + type semiconductor.
  • the sub-collector layer 40 may be formed between the collector layer 42 and the substrate 60, particularly when the substrate 60 is semi-insulating.
  • the sub-collector layer 40 preferably contains an n + type oxide semiconductor having a corundum structure as a main component, and the n + type oxide semiconductor is a group 13 metal (for example, Al, Ga, In, Tl, etc.) in the periodic table. ) Is more preferably contained as a main component, and one or more metals selected from aluminum, indium and gallium are more preferably contained, and gallium oxide or a mixed crystal thereof is preferable. Most preferred.
  • the "main component” is the same as the above-mentioned "main component".
  • the thickness of the sub-collector layer 40 is preferably about 0.1 to 100 ⁇ m.
  • a collector electrode 52 is formed on the surface of the sub-collector layer 40.
  • An object of the sub-collector layer 40 is to improve the performance of the ohmic collector electrode 52.
  • the sub-collector layer 40 can be omitted when the substrate 60 is conductive.
  • the base layer 44 is formed on the collector layer 42.
  • the base layer 44 is not particularly limited as long as it contains the p-type oxide semiconductor of the present invention as a main component.
  • the thickness of the base layer 44 is not particularly limited, but is preferably 10 nm to 10 ⁇ m, more preferably 10 nm to 1 ⁇ m. It is also preferable that the base layer 44 is gradually changed from the contact portion of the collector layer to the vicinity of the upper surface of the base layer 44.
  • a superlattice can be deposited on the upper surface of the base layer 44.
  • the emitter layer 46 is formed on the base layer 44.
  • the emitter layer 46 preferably contains an n-type oxide semiconductor having a corundum structure as a main component, and the n-type oxide semiconductor is a group 13 metal (for example, Al, Ga, In, Tl, etc.) in the periodic table. It is more preferable to contain an oxide semiconductor containing, as a main component, and even more preferably to contain one or more metals selected from aluminum, indium and gallium, and gallium oxide or a mixed crystal thereof is the most preferable. preferable.
  • the "main component” is the same as the above-mentioned "main component”.
  • the thickness of the emitter layer 46 is not particularly limited, but is preferably 10 nm to 100 ⁇ m.
  • the emitter layer 46 usually has a wider bandgap than the base layer 44. It is also preferable that the composition of the emitter layer 46 is arbitrarily changed from the contact portion with the base layer 44 to the vicinity of the upper surface of the emitter layer 46.
  • the cap layer 48 is formed on the emitter layer 46.
  • the cap layer 48 is preferably an n + type oxide semiconductor having a corundum structure, more preferably an n + type oxide semiconductor containing one or more metals selected from aluminum, indium and gallium, and more preferably an n + type doped gallium oxide or a gallium thereof. Mixed crystals are most preferred.
  • the thickness is not particularly limited, but is preferably 10 nm to 100 ⁇ m.
  • Each of the collector electrode 52, the base electrode 54, and the emitter electrode 56 is preferably an ohm-based metal electrode.
  • the emitter electrode 56 is deposited on the cap layer 48, and the base electrode 54 is deposited on the base layer 44 exposed by, for example, etching.
  • the collector electrode 52 is deposited on the sub-collector layer 40 as described above.
  • a collector electrode (not shown) is usually provided on the back surface of the substrate 60 on the opposite side of the device structure.
  • each electrode is not particularly limited, and known electrode materials can be used. Suitable compositions for electrodes include known ohmic electrode materials (eg, Ni, Al, Ti, Pt, Au and laminates thereof).
  • the thickness of each electrode m is not particularly limited, but is preferably about 10 to about 100 ⁇ m, and the deposition of each electrode can be realized by electron beam vapor deposition, thermal vapor deposition, sputtering or other techniques.
  • an annealing treatment may be performed in order to achieve ohm contact.
  • the annealing temperature is not particularly limited, but is preferably about 300 to 1000 ° C.
  • the pnp HBT can be formed by substituting the p-type layer of pnp HBT with the n-type layer of npn HBT and vice versa.
  • the p-type oxide semiconductor film in the semiconductor devices (1) to (3) below.
  • the semiconductor device (1) is a semiconductor device including at least a gate electrode and a channel layer on which a channel is formed, either directly on the side wall of the gate electrode or via another layer. Therefore, a part or all of the channel layer is characterized by containing a p-type oxide semiconductor as a main component.
  • the channel layer is not particularly limited as long as it forms a channel, and may be a part or a whole part of the semiconductor layer. It may be formed over other semiconductor layers.
  • the p-type oxide semiconductor film for the p-type semiconductor layer for example, a high-voltage, low-loss n-type semiconductor having a much higher dielectric breakdown electric field strength than SiC (for example,) without ion injection or the like. It can be used in semiconductor devices without impairing the semiconductor characteristics of gallium oxide, etc.).
  • the semiconductor device (1) further incorporates an SBD.
  • SBD SBD-based on-voltage
  • the freewheel current can be easily passed, so that more excellent semiconductor characteristics can be obtained, which is industrially advantageous.
  • the semiconductor device (2) is a semiconductor device including at least an n-type semiconductor layer and a p + -type semiconductor layer, and the n-type semiconductor layer contains a metal of Group 13 of the periodic table. It is characterized in that the contained crystalline oxide semiconductor is contained as a main component, and the p + type semiconductor layer contains the p-type oxide semiconductor film as a main component.
  • the p-type oxide semiconductor film can be suitably used for the p-well layer.
  • the semiconductor device (3) includes an n-type semiconductor layer containing a crystalline oxide semiconductor having a corundum structure as a main component, and a layer directly or another on the n-type semiconductor layer.
  • FIG. 15 shows an example of a semiconductor device including the above (1) to (3).
  • the semiconductor device of FIG. 15 includes a first n + type semiconductor layer 11a, an n ⁇ type semiconductor layer 12, a p-type semiconductor layer 13, a second n + type semiconductor layer 11b, a p + type semiconductor layer 16, a gate electrode 14a, and gate insulation. It includes a film 15, a shot key electrode 14b, and a drain electrode 14c.
  • the p-type is applied in the on state of the semiconductor device of FIG. 15 when a voltage is applied between the source electrode 14b and the drain electrode 14c to give a positive charge to the source electrode 14b to the gate electrode 14a, the p-type is applied.
  • a channel is formed at the interface between the semiconductor layer 13 and the gate insulating film 14a, and turns on.
  • the gate electrode 14a In the off state, by setting the voltage of the gate electrode 14a to 0V, the channel cannot be formed and the gate electrode 14a is turned off. Further, in the semiconductor device of FIG. 15, the p-type semiconductor layer 13 is embedded in the n-type semiconductor layer 12 deeper than the gate electrode 14a. With such a configuration, it is possible to reduce the leakage current in the reverse direction and improve the withstand voltage.
  • the method for forming each layer of the semiconductor device of FIG. 15 is not particularly limited as long as the object of the present invention is not impaired, and may be a known method. For example, a method of forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, various coating techniques, or the like, and then patterning by a photolithography method, or a method of directly patterning by using a printing technique or the like can be mentioned.
  • the second n + type semiconductor layer 11b and the p + type semiconductor layer 16 are connected to each other via the source electrode 14b, but the second n + type semiconductor layer 11b is directly connected without the source electrode 14b.
  • the n + type semiconductor layer 11b and the p + type semiconductor layer 16 may be connected in series.
  • the second n + type semiconductor layer 11b and the p + type semiconductor layer 16 are directly connected to each other, if the p + type semiconductor layer 16 is wider than the second n + type semiconductor layer 11b, hole omission will occur. It has the effect of improving. Further, if the second n + type semiconductor layer 11b is wider than the p + type semiconductor layer 16, the effect of lowering the on-resistance is obtained.
  • the semiconductor device is particularly useful for power devices.
  • the semiconductor device include a diode (such as SBD) or a transistor (for example, MOSFET or JFET), but SBD, MOSFET, IGBT or JFET is more preferable, and MOSFET or JFET is most preferable.
  • the semiconductor device includes an SOI structure or a sapphire substrate having a silicon substrate, an embedded insulating layer formed on the silicon substrate, and an SOS structure having a silicon layer formed on the sapphire substrate. Is also preferable, and operation at a higher temperature can be realized.
  • the semiconductor device of the present invention is suitably used as a power module, an inverter or a converter by using a known method, and further preferably used for a semiconductor system using a power supply device or the like. ..
  • the power supply device can be manufactured by connecting the semiconductor device to a wiring pattern or the like by using a known method.
  • FIG. 11 shows an example of a power supply system.
  • the power supply system 170 is configured by using the plurality of power supply devices 171 and 172 and the control circuit 173.
  • the power supply system 170 can be used in the system apparatus 182 in combination with the electronic circuit 181.
  • An example of the power supply circuit diagram of the power supply device is shown in FIG. FIG.
  • FIG. 13 shows a power supply circuit of a power supply device including a power circuit and a control circuit.
  • the DC voltage is switched at a high frequency by an inverter 19 (composed of MOSFETs A to D), converted to AC, and then insulated and transformed by a transformer 193. After rectifying with a rectifying MOSFET, smoothing with DCL195 (smoothing coils L1 and L2) and a capacitor, and outputting a DC voltage.
  • the voltage comparator 197 compares the output voltage with the reference voltage, and the PWM control circuit 196 controls the inverter 192 and the rectifier MOSFET 194 so as to obtain a desired output voltage.
  • the mist CVD device 1 includes a carrier gas source 2a for supplying a carrier gas, a flow control valve 3a for adjusting the flow rate of the carrier gas sent out from the carrier gas source 2a, and a carrier gas (diluted) for supplying the carrier gas (diluted). Diluted) source 2b, flow control valve 3b for adjusting the flow rate of carrier gas (diluted) sent out from the carrier gas (diluted) source 2b, mist generation source 4 containing the precursor solution 4a, and water 5a.
  • the substrate 10 is installed on the hot plate 8.
  • Iridium acetylacetonate iridium concentration 0.001 mol / L
  • gallium acetylacetonate gallium concentration 0.001 mol / L
  • hydrochloric acid is added to a volume ratio of 1.5%.
  • the aqueous solution was adjusted so as to be, and this was used as a raw material solution.
  • the oxide semiconductor was formed by changing the ratio of gallium (Ga) to iridium (Ir) in the raw material solution.
  • the ultrasonic vibrator was vibrated and the vibration was propagated to the raw material solution 4a through water 5a to atomize the raw material solution 4a and generate atomized droplets.
  • the atomized droplets were conveyed to the film forming chamber 7 by the carrier gas, and the atomized droplets thermally reacted on the surface of the substrate 10 at a temperature of 700 ° C. under atmospheric pressure to form a film on the substrate 10. ..
  • the membrane obtained in the above method was identified using an X-ray diffractometer, the obtained membrane was a mixed crystal oxide semiconductor film, and all the metals contained in the mixed crystal were included. It was found that an iridium gallium oxide film having a corundum structure having p-type electrical conductivity can be obtained when the atomic ratio of gallium is 40% or more.
  • Example 1 The film was formed in the same manner as in 1 to 4 above, with the ratio of Ir to Ga in the raw material solution (Ir / Ga) being 3.
  • the obtained film was ⁇ - (Ir 0.323 , Ga 0.677 ) 2 O 3 , and the Hall effect was measured and it was a p-type semiconductor. It was confirmed.
  • Example 2 The film was formed in the same manner as in 1 to 4 above, with the ratio of Ir to Ga in the raw material solution (Ir / Ga) being 4.
  • the obtained film was ⁇ - (Ir 0.348 , Ga 0.652 ) 2 O 3 , and Hall effect measurement was performed to confirm that it was a p-type semiconductor. Further, the iridium ratio is increased and the gallium ratio is decreased to form a film, and when the gallium is 40% or more and 70% or less in atomic ratio in the mixed crystal metal, the colland structure has p-type electrical conductivity. It was found that an iridium gallium oxide film was obtained.
  • Example 3 The ratio of Ir to Ga in the raw material solution (Ir / Ga) was set to 8, and a film was formed in the same manner as in 1 to 4 above. The obtained film was ⁇ - (Ir 0.517 , Ga 0.483 ) 2 O 3 , and Hall effect measurement was performed to confirm that it was a p-type semiconductor.
  • FIG. 3 shows the XRD measurement results of the oxide semiconductor film obtained in Example 1, and the peaks of 0006 and 0122 were confirmed as in ⁇ -Ga 2 O3 , and the corundum structure was similar to that of gallium oxide having a corundum structure. It was confirmed that it was a mixed crystal oxide semiconductor having. Similarly, peaks 0006 and 00012 were confirmed in Examples 2 and 3, and it was confirmed that the oxide semiconductor was a mixed crystal having a corundum structure.
  • the p-type oxide semiconductor film according to the embodiment of the present invention can be used in all fields such as semiconductors (for example, compound semiconductor electronic devices, etc.), electronic parts / electrical equipment parts, optical / electrophotographic related equipment, industrial parts, and the like. Since it has excellent p-type semiconductor characteristics, it is particularly useful for semiconductor devices and the like.

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WO2024005153A1 (ja) * 2022-06-29 2024-01-04 株式会社Flosfia 半導体装置および半導体装置の製造方法
EP4432332A1 (en) 2023-03-13 2024-09-18 Flosfia Inc. Laminated structure and semiconductor element
WO2024190744A1 (ja) * 2023-03-13 2024-09-19 Jsr株式会社 組成物、組成物の保管方法、および化合物

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JPH09125283A (ja) * 1995-11-01 1997-05-13 Hitachi Ltd 耐食性被覆を有する金属部材とその被覆形成方法
US10943981B2 (en) * 2017-08-24 2021-03-09 Flosfia Inc. Semiconductor device
TWI831755B (zh) * 2017-11-15 2024-02-11 日商Ｆｌｏｓｆｉａ股份有限公司 ｐ型氧化物半導體膜及其形成方法
JPWO2020013244A1 (ja) * 2018-07-12 2021-07-15 株式会社Flosfia 半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024005153A1 (ja) * 2022-06-29 2024-01-04 株式会社Flosfia 半導体装置および半導体装置の製造方法
EP4432332A1 (en) 2023-03-13 2024-09-18 Flosfia Inc. Laminated structure and semiconductor element
WO2024190744A1 (ja) * 2023-03-13 2024-09-19 Jsr株式会社 組成物、組成物の保管方法、および化合物
KR20240139018A (ko) 2023-03-13 2024-09-20 가부시키가이샤 플로스피아 적층 구조체 및 반도체 소자

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