WO2022029532A1 - 半導体装置、及び電子機器 - Google Patents

半導体装置、及び電子機器 Download PDF

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Publication number
WO2022029532A1
WO2022029532A1 PCT/IB2021/056484 IB2021056484W WO2022029532A1 WO 2022029532 A1 WO2022029532 A1 WO 2022029532A1 IB 2021056484 W IB2021056484 W IB 2021056484W WO 2022029532 A1 WO2022029532 A1 WO 2022029532A1
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Prior art keywords
transistor
terminal
circuit
wiring
gate
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Ceased
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PCT/IB2021/056484
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English (en)
French (fr)
Japanese (ja)
Inventor
池田隆之
長塚修平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202180058948.0A priority Critical patent/CN116134442A/zh
Priority to US18/016,888 priority patent/US12149237B2/en
Priority to JP2022541318A priority patent/JP7596386B2/ja
Priority to KR1020237004797A priority patent/KR20230047392A/ko
Publication of WO2022029532A1 publication Critical patent/WO2022029532A1/ja
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor
    • G06G7/14—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for addition or subtraction 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for multiplication or division
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/48—Analogue computers for specific processes, systems or devices, e.g. simulators
    • G06G7/60—Analogue computers for specific processes, systems or devices, e.g. simulators for living beings, e.g. their nervous systems ; for problems in the medical field
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/4824—Neural networks

Definitions

  • One aspect of the present invention relates to a semiconductor device and an electronic device.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of the invention disclosed in the present specification and the like relates to a product, a driving method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, image pickup devices, storage devices, signal processing devices, and processors. , Electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.
  • the mechanism of the brain is incorporated as an electronic circuit, and it has a circuit corresponding to "neurons” and "synapses" of the human brain. Therefore, such integrated circuits are sometimes called “neuromorphic”, “brainmorphic”, “brain-inspired” and the like.
  • the integrated circuit has a non-Von Neumann architecture, and is expected to be able to perform parallel processing with extremely low power consumption as compared with the Von Neumann architecture in which the power consumption increases as the processing speed increases.
  • Non-Patent Document 1 and Non-Patent Document 2 disclose an arithmetic unit in which an artificial neural network is configured by using SRAM (Static Random Access Memory).
  • a calculation is performed by multiplying the synaptic connection strength (sometimes called a weighting factor) that connects two neurons with the signal transmitted between the two neurons.
  • the connection strength of each synapse between the plurality of first neurons in the first layer and one of the second neurons in the second layer, and the plurality of first neurons in the first layer. It is necessary to multiply and add each signal input to one of the second neurons of the second layer from, that is, it is necessary to perform a product-sum operation, for example, depending on the scale of the artificial neural network.
  • the number of bond strengths and the number of parameters indicating the signal are determined.
  • the second neuron performs an operation by the activation function using the result of the product-sum calculation of the synaptic connection strength and the signal output by the first neuron, and uses the calculation result as a signal in the third layer.
  • the calculation performance is generally limited to 10 TOPS (Tera Operations Per Second) / W.
  • TOPS Transmission Operations Per Second
  • an analog arithmetic circuit that performs an arithmetic of an artificial neural network
  • a circuit using a translinear principle and the like can be mentioned.
  • the circuit is composed of a transistor in which silicon is included in a channel forming region (hereinafter, referred to as a Si transistor)
  • Si transistor a transistor in which silicon is included in a channel forming region
  • it is difficult to configure an analog memory with, for example, a Si transistor. Therefore, it is necessary to read the data input to the analog arithmetic circuit from the digital memory and convert it into analog data by the digital-to-analog conversion circuit.
  • the current flowing through the Si transistor needs to be, for example, 10 pA or more, preferably 1 nA or more. On the contrary, at a current lower than these, it is difficult to maintain the exponential characteristics of the subthreshold region in the Si transistor.
  • the voltage input terminal of the circuit may be affected by a voltage drop.
  • the translinear principle including a Si transistor in order to pass the above-mentioned current value through the Si transistor, it is necessary to apply an appropriate voltage to the voltage input terminal of the circuit.
  • the influence of the variation of the threshold voltage of the included transistor may appear in the calculation result. Conversely, the calculation accuracy can be improved by eliminating the variation in the threshold voltage.
  • One aspect of the present invention is to provide a semiconductor device or the like that performs product-sum calculation and / or function calculation.
  • one aspect of the present invention is to provide a semiconductor device for AI (Artificial Integrity) or the like.
  • one aspect of the present invention is to provide a semiconductor device or the like for a DNN (Deep Neural Network).
  • one aspect of the present invention is to provide a semiconductor device having high arithmetic performance.
  • one aspect of the present invention is to provide a semiconductor device or the like having low power consumption.
  • one aspect of the present invention is to provide a semiconductor device or the like that is not easily affected by variations in the threshold voltage of the transistor.
  • one aspect of the present invention is to provide a semiconductor device or the like that is not easily affected by variations in the characteristics of a current source.
  • one aspect of the present invention is to provide a new semiconductor device or the like.
  • the problem of one aspect of the present invention is not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from the description of the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed problems and other problems.
  • One aspect of the present invention is a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. It is a semiconductor device having a tenth transistor and a first capacitance. Further, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor. And each have a metal oxide in the channel forming region. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the gate of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the first capacitance. Is connected.
  • the second terminal of the second transistor is the second terminal of the first capacitance, the first terminal of the fourth transistor, the gate of the fifth transistor, the first terminal of the seventh transistor, and the gate of the eighth transistor. And is electrically connected to. Further, the first terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor and the gate of the seventh transistor, and the first terminal of the eighth transistor is the first terminal of the ninth transistor. And the gate of the 10th transistor are electrically connected to. The amount of current flowing between the source and drain of the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor is determined. The amount of current that flows when the transistor operates in the sub-threshold region.
  • one aspect of the present invention preferably has a configuration having a second capacity in the above (1).
  • the gate of the first transistor is electrically connected to the first terminal of the second capacitance
  • the gate of the second transistor is electrically connected to the second terminal of the second capacitance.
  • one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. It is preferable that at least one of the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor is a transistor having a multi-gate structure.
  • one aspect of the present invention preferably has a configuration having an eleventh transistor and a third capacitance in any one of the above (1) to (3).
  • the first terminal of the eleventh transistor is electrically connected to the first terminal of the third capacitance.
  • the first terminal of the eleventh transistor includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor.
  • the second terminal of the third capacitance is electrically connected to the first terminal of the eleventh transistor when it is electrically connected to the back gate of any one of the ninth transistor and the tenth transistor. It is preferably electrically connected to the source of the transistor having the back gate.
  • one aspect of the present invention is that in any one of (1) to (3) above, the back gate of the first transistor is electrically connected to the back gate of the third transistor and the back gate of the fourth transistor. It is preferable that the configuration is connected to.
  • one aspect of the present invention includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a fourth transistor. It is a semiconductor device having 10 transistors, a twelfth transistor, a thirteenth transistor, and a first capacitance. Further, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the twelfth transistor. And the thirteenth transistor each have a metal oxide in the channel forming region.
  • the first terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the gate of the second transistor is the first terminal of the twelfth transistor, the gate of the thirteenth transistor, and the first capacitance. It is electrically connected to the first terminal, and the second terminal of the twelfth transistor is electrically connected to the first terminal of the thirteenth transistor.
  • the second terminal of the second transistor is the second terminal of the first capacitance, the first terminal of the fourth transistor, the gate of the fifth transistor, the first terminal of the seventh transistor, and the gate of the eighth transistor. And is electrically connected to.
  • the first terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor and the gate of the seventh transistor, and the first terminal of the eighth transistor is connected to the first terminal of the ninth transistor. It is electrically connected to the gate of the tenth transistor. It should be noted that the current flows between the source and drain of the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the thirteenth transistor. The amount of current is the amount of current that flows when the transistor operates in the sub-threshold region.
  • one aspect of the present invention includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. It is preferable that at least one of the ninth transistor, the tenth transistor, the twelfth transistor, and the thirteenth transistor is a transistor having a multi-gate structure.
  • one aspect of the present invention preferably has a configuration having the 11th transistor and the third capacitance in the above (6) or (7).
  • the first terminal of the eleventh transistor is preferably electrically connected to the first terminal of the third capacitance.
  • the first terminal of the eleventh transistor includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor.
  • the second terminal of the third capacitance is connected to the first terminal of the eleventh transistor when it is electrically connected to the back gate of any one of the tenth transistor, the twelfth transistor, and the thirteenth transistor. It is preferable that the configuration is electrically connected to the source of the transistor having the back gate which is electrically connected.
  • the back gate of the first transistor is electrically connected to the back gate of the fourth transistor and the back gate of the twelfth transistor. It is preferable that the configuration is as follows.
  • one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a fourth transistor. It is a semiconductor device having 9 transistors, a 10th transistor, a 14th transistor, a 15th transistor, a first capacitance, and a photodiode. Further, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor. Each of the 14th transistor and the 15th transistor has a metal oxide in the channel forming region.
  • the first terminal of the first transistor is electrically connected to the first terminal of the second transistor
  • the gate of the second transistor is the first terminal of the third transistor and the first terminal of the first capacitance. Is electrically connected to.
  • the second terminal of the second transistor is the second terminal of the first capacitance, the first terminal of the fourth transistor, the gate of the fifth transistor, the first terminal of the seventh transistor, and the gate of the eighth transistor. And is electrically connected to.
  • the first terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor and the gate of the seventh transistor
  • the first terminal of the eighth transistor is the first terminal of the ninth transistor.
  • the gate of the 10th transistor are electrically connected to.
  • the first terminal of the 14th transistor is electrically connected to the input terminal of the photodiode
  • the second terminal of the 14th transistor is the first terminal of the 15th transistor, the gate of the 15th transistor, and the sixth terminal. It is electrically connected to the gate of the transistor. It should be noted that the current flows between the source and drain of the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the fifteenth transistor.
  • the amount of current is the amount of current that flows when the transistor operates in the sub-threshold region.
  • one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. It is preferable that at least one of the eighth transistor, the ninth transistor, the tenth transistor, the fourteenth transistor, and the fifteenth transistor is a transistor having a multi-gate structure.
  • one aspect of the present invention preferably has a configuration having the 11th transistor and the third capacitance in the above (10) or (11). Further, it is preferable that the first terminal of the eleventh transistor is electrically connected to the first terminal of the third capacitance. Further, the first terminal of the eleventh transistor includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. When electrically connected to the back gate of any one of the 9th transistor, the 10th transistor, the 14th transistor, and the 15th transistor, the second terminal of the third capacitance is the 11th transistor. It is preferable that the transistor is electrically connected to the source of the transistor having a back gate which is electrically connected to the first terminal of the above.
  • the back gate of the first transistor is electrically connected to the back gate of the third transistor and the back gate of the fourth transistor. It is preferable that the configuration is as follows.
  • one aspect of the present invention preferably has a configuration having a second capacity in any one of the above (10) to (13).
  • the gate of the first transistor may be electrically connected to the first terminal of the second capacitance
  • the gate of the second transistor may be electrically connected to the second terminal of the second capacitance. preferable.
  • one aspect of the present invention is that the first terminal of the first transistor is a second terminal of the fifth transistor and a second terminal of the eighth transistor. It is preferable that the configuration is electrically connected to the transistor.
  • one aspect of the present invention is an electronic device having the semiconductor device according to any one of (1) to (15) above and a housing, and the product-sum calculation is performed by the semiconductor device.
  • the semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element transistor, diode, photodiode, etc.
  • the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like may be a semiconductor device itself, and may have a semiconductor device.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display
  • One or more devices, light emitting devices, loads, etc. can be connected between X and Y.
  • the switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows.
  • a circuit that enables functional connection between X and Y for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion) Circuits (digital-analog conversion circuit, analog-to-digital conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the potential level of the signal, etc.), voltage source, current source , Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) It is possible to connect one or more to and from. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. do.
  • X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element between X and Y). Or when they are connected by sandwiching another circuit) and when X and Y are directly connected (that is, they are connected without sandwiching another element or another circuit between X and Y). If there is) and.
  • X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and the X, the source (or the second terminal, etc.) of the transistor are connected to each other. (1 terminal, etc.), the drain of the transistor (or the 2nd terminal, etc.), and Y are electrically connected in this order.
  • the source of the transistor (or the first terminal, etc.) is electrically connected to X
  • the drain of the transistor (or the second terminal, etc.) is electrically connected to Y
  • the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
  • X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor.
  • the terminals, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
  • the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. It should be noted that these expression methods are examples, and are not limited to these expression methods.
  • X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • the circuit diagram shows that the independent components are electrically connected to each other, the case where one component has the functions of a plurality of components together.
  • one conductive film has both the function of the wiring and the function of the component of the function of the electrode. Therefore, the electrical connection in the present specification also includes the case where one conductive film has the functions of a plurality of components in combination.
  • the “resistance element” may be, for example, a circuit element having a resistance value higher than 0 ⁇ , wiring higher than 0 ⁇ , or the like. Therefore, in the present specification and the like, the “resistance element” includes wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, and the like. Therefore, the term “resistance element” may be paraphrased into terms such as “resistance”, “load”, and “region having a resistance value”. On the contrary, the terms “resistance”, “load”, and “region having a resistance value” may be paraphrased into terms such as “resistance element”.
  • the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, and further preferably 10 m ⁇ or more and 1 ⁇ or less. Further, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
  • the “capacitance element” means, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value higher than 0F, a parasitic capacitance, and a transistor. It can be the gate capacitance of. Therefore, in the present specification and the like, the “capacitive element” includes a pair of electrodes and a circuit element including a dielectric contained between the electrodes. Further, terms such as “capacitive element”, “parasitic capacitance”, and “gate capacitance” may be paraphrased into terms such as "capacity”.
  • the term “capacity” may be paraphrased into terms such as “capacitive element”, “parasitic capacitance”, and “gate capacitance”.
  • the term “pair of electrodes” of “capacity” can be paraphrased as “pair of conductors", “pair of conductive regions", “pair of regions” and the like.
  • the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be 1 pF or more and 10 ⁇ F or less.
  • the transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • the two terminals that function as sources or drains are the input and output terminals of the transistor.
  • One of the two input / output terminals becomes a source and the other becomes a drain depending on the high and low potentials given to the conductive type (n-channel type and p-channel type) of the transistor and the three terminals of the transistor. Therefore, in the present specification and the like, the terms source and drain may be paraphrased with each other.
  • the transistor when explaining the connection relationship of transistors, "one of the source or drain” (or the first electrode or the first terminal), “the other of the source or drain” (or the second electrode, or the second electrode, or The notation (second terminal) is used.
  • it may have a back gate in addition to the above-mentioned three terminals.
  • one of the gate or the back gate of the transistor may be referred to as a first gate
  • the other of the gate or the back gate of the transistor may be referred to as a second gate.
  • the terms “gate” and “backgate” may be interchangeable.
  • the respective gates When the transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, and the like in the present specification and the like.
  • a transistor having a multi-gate structure having two or more gate electrodes can be used as an example of a transistor.
  • the multi-gate structure since the channel formation regions are connected in series, a structure in which a plurality of transistors are connected in series is obtained. Therefore, the multi-gate structure can reduce the off-current and improve the withstand voltage of the transistor (improve the reliability).
  • the multi-gate structure even if the voltage between the drain and the source changes when operating in the saturated region, the current between the drain and the source does not change much, and the slope is flat. The characteristics can be obtained. By utilizing the voltage / current characteristics with a flat slope, it is possible to realize an ideal current source circuit or an active load having a very high resistance value. As a result, it is possible to realize a differential circuit or a current mirror circuit having good characteristics.
  • the circuit element may have a plurality of circuit elements.
  • one resistance is described on the circuit diagram, it includes the case where two or more resistances are electrically connected in series.
  • one capacity is described on the circuit diagram, it includes a case where two or more capacities are electrically connected in parallel.
  • one transistor is described on the circuit diagram, two or more transistors are electrically connected in series, and the gates of the respective transistors are electrically connected to each other.
  • Shall include.
  • the switch has two or more transistors, and two or more transistors are electrically connected in series or in parallel. It is assumed that the gates of the respective transistors are electrically connected to each other.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration, a device structure, and the like.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • ground potential ground potential
  • the potentials are relative, and when the reference potential changes, the potential given to the wiring, the potential applied to the circuit, the potential output from the circuit, and the like also change.
  • the terms “high level potential” and “low level potential” do not mean a specific potential.
  • the high level potentials provided by both wirings do not have to be equal to each other.
  • the low-level potentials provided by both wirings do not have to be equal to each other. ..
  • the "current” is a charge transfer phenomenon (electrical conduction).
  • the description “electrical conduction of a positively charged body is occurring” means “electrical conduction of a negatively charged body in the opposite direction”. Is happening. " Therefore, in the present specification and the like, “current” refers to a charge transfer phenomenon (electrical conduction) associated with carrier transfer, unless otherwise specified.
  • the carrier here include electrons, holes, anions, cations, complex ions, and the like, and the carriers differ depending on the system in which the current flows (for example, semiconductor, metal, electrolytic solution, vacuum, etc.).
  • the "current direction” in wiring or the like is the direction in which the carrier that becomes a positive charge moves, and is described as a positive current amount.
  • the direction in which the carrier that becomes a negative charge moves is opposite to the direction of the current, and is expressed by the amount of negative current. Therefore, in the present specification and the like, if there is no disclaimer regarding the positive or negative current (or the direction of the current), the description such as “current flows from element A to element B” is described as “current flows from element B to element A”. Can be rephrased as. Further, the description such as “a current is input to the element A” can be rephrased as "a current is output from the element A” or the like.
  • the ordinal numbers “1st”, “2nd”, and “3rd” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, the component referred to in “first” in one of the embodiments of the present specification and the like may be the other embodiment or the component referred to in “second” in the scope of claims. There can also be. Further, for example, the component referred to in "first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the scope of claims.
  • the terms “upper” and “lower” do not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other.
  • the terms “electrode B on the insulating layer A” it is not necessary that the electrode B is formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.
  • words such as “membrane” and “layer” can be interchanged with each other depending on the situation.
  • the terms “insulating layer” and “insulating film” may be changed to the term "insulator”.
  • Electrode may be used as part of a “wiring” and vice versa.
  • the term “electrode” or “wiring” also includes the case where a plurality of “electrodes” and / and “wiring” are integrally formed.
  • a “terminal” may be used as part of a “wiring” or “electrode” and vice versa.
  • the term “terminal” includes a case where a plurality of "electrodes", “wiring”, “terminals” and the like are integrally formed.
  • the "electrode” can be a part of “wiring” or “terminal”, and for example, “terminal” can be a part of “wiring” or “electrode”. Further, terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "area” in some cases.
  • terms such as “wiring”, “signal line”, and “power line” can be interchanged with each other in some cases or depending on the situation.
  • the reverse is also true, and it may be possible to change terms such as “signal line” and “power line” to the term “wiring”.
  • a term such as “power line” may be changed to a term such as "signal line”.
  • a term such as “signal line” may be changed to a term such as “power line”.
  • the term “potential” applied to the wiring may be changed to a term such as “signal” in some cases or depending on the situation.
  • the reverse is also true, and terms such as “signal” may be changed to the term “potential”.
  • the semiconductor impurities refer to, for example, other than the main components constituting the semiconductor layer.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • the inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, group 1 element, group 2 element, group 13 element, group 14 element, group 15 element, and other than the main component.
  • transition metals and the like and in particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements and the like (however, oxygen, Does not contain hydrogen).
  • the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows. Therefore, the switch may have two or three or more terminals through which a current flows, in addition to the control terminals.
  • an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.
  • Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, shotkey diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or logic circuits that combine these.
  • transistors for example, bipolar transistors, MOS transistors, etc.
  • diodes for example, PN diodes, PIN diodes, shotkey diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.
  • the "conduction state" of the transistor is, for example, a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited, and a current is applied between the source electrode and the drain electrode. It refers to the state in
  • the "non-conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically cut off.
  • the polarity (conductive type) of the transistor is not particularly limited.
  • An example of a mechanical switch is a switch that uses MEMS (Micro Electro Mechanical Systems) technology.
  • the switch has an electrode that can be moved mechanically, and by moving the electrode, conduction and non-conduction are controlled and operated.
  • parallel means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of ⁇ 5 ° or more and 5 ° or less is also included.
  • substantially parallel or approximately parallel means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.
  • substantially vertical or “approximately vertical” means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a semiconductor device or the like that performs a product-sum calculation and / or a function calculation.
  • a semiconductor device for AI (Artificial Integrity) or the like can be provided.
  • a semiconductor device or the like for a DNN Deep Neural Network.
  • a semiconductor device having high arithmetic performance can be provided.
  • a semiconductor device or the like that is not easily affected by variations in the threshold voltage of the transistor.
  • a semiconductor device or the like that is not easily affected by variations in the characteristics of the current source.
  • a novel semiconductor device or the like can be provided.
  • the effect of one aspect of the present invention is not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from the description in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.
  • FIG. 1 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device.
  • 2A and 2B are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 3 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device.
  • FIG. 4 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device.
  • FIG. 5 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device.
  • 6A and 6B are block diagrams showing a configuration example of a semiconductor device.
  • 7A to 7C are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • 8A to 8D are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 10 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device.
  • FIG. 11 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 12 is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 13A is a block diagram showing a configuration example of a circuit included in the semiconductor device, and
  • FIG. 13B is a circuit diagram showing a configuration example of the circuit included in the semiconductor device.
  • 14A to 14D are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • 15A and 15B are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 10 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device.
  • FIG. 11 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 12 is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 13A is
  • FIG. 16 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device.
  • FIG. 17 is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 18 is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 19 is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 20 is a block diagram showing a configuration example of a semiconductor device.
  • 21A and 21B are diagrams illustrating a hierarchical neural network.
  • FIG. 22 is a block diagram showing a configuration example of the semiconductor device.
  • FIG. 23 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • 24A to 24C are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 25 is a schematic cross-sectional view showing a configuration example of a semiconductor device.
  • 26A and 26B are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 27 is a schematic cross-sectional view showing a configuration example of a transistor.
  • FIG. 28A is a diagram for explaining the classification of the crystal structure
  • FIG. 28B is a diagram for explaining the XRD spectrum of the crystalline IGZO
  • FIG. 28C is a diagram for explaining the microelectron diffraction pattern of the crystalline IGZO.
  • 29A is a perspective view showing an example of a semiconductor wafer
  • FIG. 29B is a perspective view showing an example of a chip
  • FIGS. 29C and 29D are perspective views showing an example of an electronic component.
  • FIG. 30 is a perspective view showing an example of an electronic device.
  • 31A to 31C are perspective views showing an example of an electronic device.
  • FIG. 32A is a graph showing the relationship between the theoretically expected current output from the semiconductor device and the output current of the semiconductor device obtained by simulation, and
  • FIG. 32B shows the calculation efficiency of the semiconductor device. It is a graph which shows.
  • FIG. 33 is a circuit diagram showing a circuit configuration used in the simulation.
  • FIG. 34 is a graph showing the relationship between the threshold voltage of the transistor and the backgate-source voltage of the transistor obtained by simulation.
  • the synaptic connection strength can be changed by giving existing information to the neural network.
  • the process of giving existing information to the neural network and determining the bond strength may be called "learning”.
  • neural network models include Hopfield type and hierarchical type.
  • a neural network having a multi-layer structure may be referred to as a “deep neural network” (DNN), and machine learning by a deep neural network may be referred to as “deep learning”.
  • DNN deep neural network
  • machine learning by a deep neural network may be referred to as “deep learning”.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is contained in the channel forming region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor. be able to. Further, when the term "OS transistor" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as a metal oxynitride.
  • the configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.
  • the content described in one embodiment (may be a part of the content) is different from the content described in the embodiment (may be a part of the content) and one or more different implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).
  • figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more different figures.
  • the figure (which may be a part) described in the embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more different figures.
  • more figures can be formed.
  • the code is used for identification such as "_1", “[n]”, “[m, n]”. May be added and described. Further, in the drawings and the like, when the reference numerals such as “_1”, “[n]” and “[m, n]” are added to the reference numerals, when it is not necessary to distinguish them in the present specification and the like, when it is not necessary to distinguish them.
  • the identification code may not be described.
  • FIG. 1 shows a configuration example of a multiplication cell, which is a semiconductor device according to one aspect of the present invention.
  • the multiplication cell is configured to perform multiplication using the translinear principle.
  • the multiplication cell has a function of holding the first data as an example, and a function of outputting the product of the first data and the second data by inputting the second data to the multiplication cell. Have.
  • the circuit MC shown in FIG. 1 has transistors M1 to M10, a capacitance C1, and a capacitance CG.
  • the transistor M1 to the transistor M10 can be, for example, an OS transistor.
  • the metal oxide contained in the channel forming region of the OS transistor include indium, an In-M-Zn oxide having element M and zinc (element M is aluminum, gallium, yttrium, tin, copper and vanadium).
  • element M is aluminum, gallium, yttrium, tin, copper and vanadium.
  • transistor other than the OS transistor for example, a transistor in which Ge or the like is included in the channel formation region, or a transistor in which compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, SiGe are included in the channel formation region.
  • Transistors in which carbon nanotubes are contained in the channel forming region, transistors in which organic semiconductors are contained in the channel forming region, and the like can be used.
  • each of the transistor M1, the transistor M3, and the transistor M4 includes, for example, a case where it functions as a switching element. That is, it is assumed that the gate, source, and drain of each of these transistors include a case where a voltage within a range in which these transistors operate as a switching element is appropriately input.
  • one aspect of the present invention is not limited to this.
  • at least one of these transistors can operate in a saturated or linear region when in the on state.
  • at least one of the transistor M1, the transistor M3, and the transistor M4 can operate in the subthreshold region.
  • At least one of the transistor M1, the transistor M3, and the transistor M4 can be operated in a linear region, an operation in a saturation region, and an operation in a subthreshold region.
  • at least one of the transistor M1, the transistor M3, and the transistor M4 can be mixed in the case of operating in the linear region and in the saturated region, or in the case of operating in the saturated region, and the sub.
  • the case of operating in the threshold region and the case of operating in the linear region can be mixed, and the case of operating in the subthreshold region and the case of operating in the subthreshold region can be mixed.
  • the saturation region is a region where the gate-source voltage is larger than the threshold voltage and the difference between the gate-source voltage and the threshold voltage is larger than the source-drain voltage.
  • the saturation region refers to a region in which the drain current of the transistor does not change even if the source-drain voltage is changed.
  • the saturation region refers to a region in which the drain current is proportional to the square of the gate-source voltage.
  • the saturated region shall include a region that can be regarded as the region described above.
  • the linear region is a region in which the gate-source voltage is larger than the threshold voltage and the difference between the gate-source voltage and the threshold voltage is smaller than the source-drain voltage.
  • the linear region refers to a region in which the channel formation region acts as a resistance and the drain current of the transistor behaves as if it changes linearly due to a change in the source-drain voltage.
  • the linear region shall include a region that can be regarded as the region described above.
  • the subthreshold region refers to a region in which the gate voltage is lower than the threshold voltage in the graph showing the gate voltage (Vg) -drain current (Id) characteristics of the transistor.
  • the subthreshold region refers to a region in which a current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that considers only drift current).
  • the subthreshold region is a region in which the drain current increases exponentially with an increase in the gate voltage.
  • the subthreshold region shall include a region that can be regarded as the region described above.
  • the drain current when the transistor operates in the subthreshold region is called the subthreshold current.
  • the subthreshold current increases exponentially with respect to the gate voltage, regardless of the drain voltage. In the circuit operation using the subthreshold current, the influence of the variation of the drain voltage can be reduced.
  • the OS transistor has a drain current per 1 ⁇ m of channel width, such as less than 1 ⁇ 10 -20 A, less than 1 ⁇ 10 -22 A, or less than 1 ⁇ 10 -24 A. Further, the OS transistor drains per 1 ⁇ m of channel width such as 1.0 ⁇ 10 -8 A or less, 1.0 ⁇ 10 -12 A or less, or 1.0 ⁇ 10 -15 A or less at the threshold voltage of the transistor. Current flows. That is, the OS transistor can take a large range of the gate voltage operating in the subthreshold region.
  • the threshold voltage of the OS transistor is Vth
  • the voltage range is Vth -1.0V or more and Vth or less, or Vth -0.5V or more and Vth or less. Circuit operation using the gate voltage can be performed.
  • the off-current is large and the range of the gate voltage operating in the subthreshold region is narrow.
  • the OS transistor can operate in a wider gate voltage range than the Si transistor.
  • the off region of the transistor means a region where the gate-source voltage is lower than the voltage in the subthreshold region. Further, when the gate-source voltage of the transistor is in the off region, the transistor shall be in the off state. Further, in the present specification and the like, the current flowing when the transistor is in the off state is described as an off current or a leak current.
  • each of the transistor M2, the transistor M5 and the transistor M10 shall include the case of operating in the subthreshold region.
  • the first terminal of the transistor M1 is electrically connected to the wiring VDE
  • the second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M2
  • the gate of the transistor M1 is the wiring WWLB and the capacitance CG. It is electrically connected to the first terminal of.
  • the first terminal of the transistor M3 is electrically connected to the wiring WDL
  • the second terminal of the transistor M3 is connected to the gate of the transistor M2, the second terminal of the capacitance CG, and the first terminal of the capacitance C1. It is electrically connected.
  • the second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M4, the second terminal of the capacitance C1, the gate of the transistor M5, the first terminal of the transistor M7, and the gate of the transistor M8. It is connected. Further, the second terminal of the transistor M4 is electrically connected to the wiring VGE, and the gate of the transistor M4 is electrically connected to the gate of the transistor M3 and the wiring WWL. Further, the first terminal of the transistor M5 is electrically connected to the wiring VDE, and the second terminal of the transistor M5 is electrically connected to the first terminal of the transistor M6 and the gate of the transistor M7.
  • the gate of the transistor M6 is electrically connected to the wiring XDL, and the second terminal of the transistor M6 is electrically connected to the wiring VGE. Further, the second terminal of the transistor M7 is electrically connected to the wiring VGE. Further, the first terminal of the transistor M8 is electrically connected to the wiring VDE, and the second terminal of the transistor M8 is electrically connected to the first terminal of the transistor M9 and the gate of the transistor M10. Further, the gate of the transistor M9 is electrically connected to the wiring BDL, and the second terminal of the transistor M9 is electrically connected to the wiring VGE. Further, the first terminal of the transistor M10 is electrically connected to the wiring OL, and the second terminal of the transistor M10 is electrically connected to the wiring VGE.
  • the wiring VDE functions as a wiring that gives a constant voltage as an example.
  • the constant voltage may be, for example, a high power supply voltage.
  • the wiring VGE functions as a wiring that gives a constant voltage as an example.
  • the constant voltage may be, for example, a low power supply voltage, a ground potential, or the like.
  • the wiring WWL functions as a write signal line for writing the first data to the circuit MC as an example.
  • the wiring WWLB functions as a wiring for transmitting an inverted signal with respect to a write signal transmitted to the wiring WWL.
  • the wiring WWLB may be wiring that supplies a variable potential (for example, high level potential, low level potential, etc.) instead of the inverted signal.
  • the wiring WDL functions as a write data line for writing a voltage corresponding to the first data to the circuit MC as an example.
  • the wiring XDL functions as a signal line for inputting a voltage corresponding to the second data to the circuit MC as an example.
  • the transistor M6 having a gate electrically connected to the wiring XDL functions as a current source. Further, as described above, since the transistor M6 includes the case of operating in the subthreshold region, a current in the subthreshold region flows between the first terminal and the second terminal of the transistor M6.
  • the wiring BDL functions as a signal line for inputting a voltage for adjusting the amount of current according to the calculation result of the first data and the second data to the circuit MC.
  • the transistor M9 having a gate electrically connected to the wiring BDL functions as a current source. Further, as described above, since the transistor M9 includes the case of operating in the subthreshold region, a current in the subthreshold region flows between the first terminal and the second terminal of the transistor M9.
  • the amount of current flowing through the transistor M9 can be, for example, a variable or a constant applied to a circuit that performs an operation according to a function system included in the circuit ACTV described later.
  • the wiring OL functions as a wiring for outputting a current according to the product of the first data and the second data, as an example.
  • the potential given by the wiring VDE is a high power supply potential
  • the potential given by the wiring VGE is a ground potential (VGND).
  • a high level potential is input to the wiring WWL.
  • the high level potential is input to the respective gates of the transistor M3 and the transistor M4, so that the transistor M3 and the transistor M4 are turned on.
  • the second terminal of the capacitance C1 (the second terminal of the transistor M2) is in a conductive state via the transistor M4, the second terminal of the capacitance C1 (the second terminal of the transistor M2) is in a conductive state.
  • the potential of the terminal is V GND .
  • the wiring WDL and the first terminal of the capacitance C1 are in a conductive state via the transistor M3.
  • a signal corresponding to the first data hereinafter referred to as voltage V W
  • the first terminal of the capacitance C1 the second terminal of the capacitance CG, the gate of the transistor M2, etc.
  • the voltage V W corresponding to the first data is written in.
  • the inverted signal of the signal transmitted to the wiring WWL is input to the wiring WWLB. Specifically, a low level potential is input to the wiring WWLB. Therefore, the low level potential is applied to the gate of the transistor M1 (the first terminal of the capacitive CG). As a result, the transistor M1 is turned off.
  • the voltage V W is written to the first terminal of the capacitance C1 (the second terminal of the capacitance CG, the gate of the transistor M2, etc.)
  • a low level potential is input to the wiring WWL.
  • the low level potential is input to the respective gates of the transistor M3 and the transistor M4, so that the transistor M3 and the transistor M4 are turned off.
  • the first terminal of the capacitance C1 is in a floating state, so that the voltage VW ⁇ V GND between the first terminal and the second terminal of the capacitance C1 is maintained.
  • the potential given to the gate of the transistor M3 changes from a high level potential to a low level potential, it is written to the first terminal of the capacitance C1 by the parasitic capacitance between the gate of the transistor M3 and the second terminal.
  • the voltage V W may step down.
  • the voltage stepped down from the voltage VW due to the parasitic capacitance between the gate and the second terminal of the transistor M3 is also the voltage corresponding to the first data.
  • the circuit MC of FIG. 1 is provided with a capacitance CG in order to prevent the voltage V W from being stepped down.
  • the wiring WWLB transmits to the wiring WWL. Since the inverted signal of the signal is input, the potential of the wiring WWLB changes from the low level potential to the high level potential. At this time, since the potential of the first terminal of the capacitance CG increases from the low level potential to the high level potential, the potential of the second terminal of the capacitance CG (the first terminal of the capacitance C1, the gate of the transistor M2, etc.) is the capacitance. Capacitive coupling of CG ideally boosts the potential difference between the high-level potential and the low-level potential.
  • the step down of the voltage V W when the transistor M3 is turned off is prevented. be able to.
  • the configuration of the capacitive CG for making the potential difference stepped up by the capacitive coupling of the capacitive CG equal to the potential difference stepped down by the parasitic capacitance between the gate and the second terminal of the transistor M3 will be described later.
  • the transistor M1 may be turned off by supplying the wiring WWLB with a low level potential instead of the inverted signal of the signal transmitted to the wiring WWL.
  • the holding of the first data in the circuit MC and the stop of the supply of the high power supply potential to the first terminal of the transistor M2 can be performed at the same time.
  • the transistor M1 When a high level potential is input to the wiring WWLB, the transistor M1 is turned on. Therefore, a high power supply potential is input to the first terminal of the transistor M2, and a high power potential is input between the first terminal and the second terminal of the transistor M2. In, a current corresponding to the voltage between the gate and the second terminal of the transistor M2 flows. Further, here, the amount of current flowing between the first terminal and the second terminal of the transistor M2 is defined as IW . When the transistor M2 operates in the subthreshold region, IW is a current amount in the current range in the subthreshold region.
  • the current flowing between the first terminal and the second terminal of the transistor M2 flows to the wiring VGE via the transistor M7.
  • the transistor M7 also operates in the subthreshold region, and a current having a current amount of IW flows between the first terminal and the second terminal of the transistor M7.
  • the amount of current I W can be expressed by the following equation.
  • the VM7gs is a voltage between the gate and the second terminal of the transistor M7.
  • I 0 is a current value that flows when VM7gs is 0, and is determined by the threshold voltage, temperature, device structure, and the like of the transistor M7.
  • J is a correction coefficient determined by the temperature, the device structure, and the like.
  • V X is input to the wiring XDL as a voltage corresponding to the second data.
  • the voltage between the gate and the second terminal of the transistor M6 becomes V X -V GND , and a current corresponding to V X -V GND flows between the first terminal and the second terminal of the transistor M6.
  • the amount of current flowing between the first terminal and the second terminal of the transistor M6 is defined as IX .
  • IX is a current amount in the current range in the subthreshold region.
  • the current flowing between the first terminal and the second terminal of the transistor M6 is the current flowing from the wiring VDE to the first terminal of the transistor M6 via the transistor M5.
  • the transistor M5 also operates in the subthreshold region, and a current having a current amount of IX flows between the first terminal and the second terminal of the transistor M5.
  • the amount of current IX can be expressed by the following equation.
  • the VM5gs is a voltage between the gate and the second terminal of the transistor M5.
  • I 0 is a current value that flows when VM5gs is 0, and is determined by the threshold voltage, temperature, device structure, and the like of the transistor M5.
  • J is a correction coefficient determined by the temperature, the device structure, and the like. It should be noted that each of I 0 and J used in the formula (1.2) shall be equal to I 0 and J used in the formula (1.1).
  • V B is input to the wiring BDL as a voltage for adjusting the output current.
  • the voltage between the gate and the second terminal of the transistor M9 becomes V B ⁇ V GND , and a current corresponding to V B ⁇ V GND flows between the first terminal and the second terminal of the transistor M9.
  • IB the amount of current flowing between the first terminal and the second terminal of the transistor M9 is defined as IB.
  • the current flowing between the first terminal and the second terminal of the transistor M9 is the current flowing from the wiring VDE to the first terminal of the transistor M9 via the transistor M8.
  • the transistor M8 also operates in the subthreshold region, and a current having a current amount of IB flows between the first terminal and the second terminal of the transistor M8.
  • the current amount IB can be expressed by the following equation.
  • the VM8gs is a voltage between the gate and the second terminal of the transistor M8.
  • I 0 is a current value that flows when VM8gs is 0. It is determined by the threshold voltage, temperature, device structure, etc. of the transistor M8.
  • J is a correction coefficient determined by the temperature, the device structure, and the like. It should be noted that each of I 0 and J used in the formula (1.3) shall be equal to I 0 and J used in the formula (1.1) and the formula (1.2). ..
  • the current flowing between the first terminal and the second terminal of the transistor M10 is determined according to the voltage between the gate and the second terminal of the transistor M10. Further, when the amount of current flowing between the first terminal and the second terminal of the transistor M10 is YY , the amount of current YY can be expressed by the following equation.
  • the VM10gs is a voltage between the gate and the second terminal of the transistor M10. Further, I 0 is a current value that flows when VM 10gs is 0. It is determined by the threshold voltage, temperature, device structure and the like of the transistor M10. Further, J is a correction coefficient determined by the temperature, the device structure, and the like. It should be noted that each of I 0 and J used in the formula (1.4) shall be equal to I 0 and J used in the formulas (1.1) to (1.3).
  • the wiring VGE the second terminal of the transistor M7, the gate of the transistor M7, the second terminal of the transistor M5, the gate of the transistor M5, the gate of the transistor M8, the second terminal of the transistor M8, the gate of the transistor M10, and the transistor M10.
  • the current I Y flowing between the first terminal and the second terminal of the transistor M10 can be expressed by the product of I W and IX . Therefore, by measuring the amount of current I Y flowing from the wiring OL, it is possible to calculate a value according to the product of I W and IX .
  • the configuration of the multiplication cell included in the semiconductor device of one aspect of the present invention is not limited to the circuit MC shown in FIG.
  • the multiplication cell included in the semiconductor device of one aspect of the present invention may have a configuration in which the circuit MC shown in FIG. 1 is modified depending on the situation.
  • the transistors M1 to M10 shown in FIG. 1 are n-channel transistors having a structure having gates above and below the channel, and the transistors M1 to M10 have a first gate and a second gate, respectively.
  • the first gate is described as a gate (sometimes referred to as a front gate) and the second gate is described as a back gate, but the first gate is described as an example.
  • the second gate can be interchanged with each other. Therefore, in the present specification and the like, the phrase “gate” can be replaced with the phrase “back gate”. Similarly, the phrase “backgate” can be replaced with the phrase "gate”.
  • the connection configuration that "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" is "the back gate is electrically connected to the first wiring". And the gate is electrically connected to the second wiring.
  • the semiconductor device of one aspect of the present invention does not depend on the connection configuration of the back gate of the transistor.
  • a back gate is shown for the transistors M1 to M10 shown in FIG. 1, and the connection configuration of the back gate is not shown.
  • the electrical connection destination of the back gate is at the design stage. You can decide.
  • the gate and the back gate may be electrically connected in order to increase the on-current of the transistor.
  • a wiring electrically connected to an external circuit or the like is provided in order to fluctuate the threshold voltage of the transistor or to reduce the off current of the transistor.
  • the configuration shown in FIG. 1 may have a configuration in which the back gates of the transistor M1, the transistor M3, and the transistor M4 are electrically connected to the wiring BGL, as shown in FIG. 2A.
  • the threshold voltages of the transistor M1, the transistor M3, and the transistor M4 can be increased, so that the transistor M1 can be increased.
  • the off current of each of the transistor M3 and the transistor M4 can be reduced.
  • the connection configuration of the back gate of the above-mentioned transistor not only FIG. 1, but also the transistor described in other parts of the specification or the transistor shown in other drawings is similarly at the design stage. You can decide.
  • the circuit MC of FIG. 1 may be configured to hold the potential of at least one back gate of the transistors M1 to M10.
  • the circuit MC shown in FIG. 3 is a modification of FIG. 1, and has a configuration including a transistor M2 and a circuit HC2 and a circuit HC5 to a circuit HC10 for holding the potentials of the back gates of the transistors M5 to M10. It has become.
  • Each of the circuit HC2 and the circuit HC5 to the circuit HC10 has a transistor BTr and a capacitance BC.
  • the transistor BTr for example, a transistor applicable to a transistor M1, a transistor M3, a transistor M4, or the like can be used. Further, it is assumed that the same voltage as the range in which the transistor M1, the transistor M3, the transistor M4 and the like operate is appropriately input to the gate, the source, and the drain of the transistor BTr.
  • the capacity BC a capacity that can be applied to the capacity C1, the capacity CG, and the like described in the present specification and the like can be used.
  • the first terminal of the transistor BTr is electrically connected to the first terminal of the capacitance BC.
  • the first terminal of the transistor BTr is electrically connected to the back gate of the transistor M2.
  • the second terminal of the capacitance BC is electrically connected to the second terminal of the transistor M2.
  • the gate of the transistor BTr is electrically connected to the wiring BWL2, and the second terminal of the transistor BTr is electrically connected to the wiring BGL2.
  • the first terminal of the transistor BTr of the circuit HC5 to the circuit HC10 is electrically connected to the back gate of the transistor M5 to the transistor M10, respectively.
  • the second terminal of the capacitance BC of the circuit HC5 to the circuit HC10 is electrically connected to the second terminal of the transistor M5 to the transistor M10, respectively.
  • the gate of the transistor BTr of the circuit HC5 to the circuit HC10 is electrically connected to the wiring BWL5 to the wiring BWL10, respectively
  • the second terminal of the transistor BTr of the circuit HC5 to the circuit HC10 is electrically connected to the wiring BGL5 to the wiring BGL10, respectively. It is connected to the.
  • Each of the wiring BGL2 and the wiring BGL5 to the wiring BGL10 functions as a wiring for supplying the correction potential described later to the circuit HC2 and the circuit HC5 to the circuit HC10 as an example.
  • the wiring BWL2 and the wiring BWL5 to the wiring BWL10 function as wiring for controlling switching between the on state and the off state of the transistor BTr included in each of the circuit HC2 and the circuit HC5 to the circuit HC10, for example. ..
  • the circuit HC2 may write a correction potential for adjusting the threshold voltage of the transistor M2 from the wiring BGL2 to the first terminal of the capacitance BC when the transistor BTr is turned on by the wiring BWL2. can. At this time, it is preferable that the second terminal of the transistor M2 is not in a floating state (is in a conductive state with the wiring that applies a constant voltage).
  • the threshold voltage of the transistors M5 to M10 is adjusted by writing the correction potential to the first terminal of the capacitance BC of the circuits HC5 to HC10 in the same manner as described above. Can be done.
  • the circuit MC has a circuit HC2 that holds a correction potential for adjusting the threshold voltage, and a circuit HC5 to a circuit HC10 for each of the transistor M2 and the transistors M5 to M10.
  • the wiring BGL2 and the wiring BGL5 to the wiring BGL10 may be combined as one wiring, for example. Further, at this time, it is preferable that each of the wiring BWL2 and the wiring BWL5 to the wiring BWL10 functions as a selection signal line for selecting one of the circuit HC2 and the circuit HC5 to the circuit HC10 with the correction potential as the writing destination. ..
  • FIG. 3 shows a configuration in which the circuit HC2 and the circuit HC5 to the circuit HC10 are electrically connected to each of the transistor M2 and the transistor M5 to the transistor M10.
  • a circuit that holds a correction potential may be electrically connected to only a part of the transistor M2, the transistor M5, or the transistor M10, not all of them.
  • the transistor M1, the transistor M3, and / or the transistor M4 may be electrically connected to a circuit HC2 and a circuit having the same correction potential as the circuits HC5 to HC10. That is, for example, one or more transistors included in the circuit MC of FIG. 1 may be selected, and a circuit for holding the correction potential may be provided for the selected transistor.
  • any one of the capacitive elements such as the planar type and the trench type can be applied as an example.
  • the capacitance C1 and / or the capacitance CG can be a capacitance element including a transistor.
  • the configuration of the circuit MC when the capacitance CG includes a transistor is shown in FIG. 2B.
  • the capacitive CG has a transistor CT, the gate of the transistor CT is electrically connected to the wiring WWLB and the gate of the transistor M1, and the first terminal and the second terminal of the transistor CT are the first terminal of the transistor M3. It is electrically connected to the two terminals, the gate of the transistor M2, and the first terminal of the capacitance C1. That is, the gate capacitance of the transistor CT is used as the capacitance CG included in the circuit MC of FIG. 2B.
  • the gate capacitance of the transistor CT as the capacitance CG included in the circuit MC, it occurs between the gate and the second terminal of the transistor M3 when the transistor M3 transitions from the on state to the off state.
  • the rising potential difference can be approximately equal.
  • the size of the transistor CT is preferably equal to the size of the transistor M3.
  • the transistor size in the present specification and the like refers to, for example, a channel length, a channel width, a transistor structure, and the like.
  • FIGS. 1 to 3 and FIGS. 4 and 5 described later show a configuration in which the circuit MC has a capacitance CG, but the configuration of the circuit MC according to the semiconductor device of one aspect of the present invention is these. Not limited to.
  • the circuit MC according to the semiconductor device according to one aspect of the present invention may be configured not to have a capacitive CG in FIGS. 1 to 3, 4 and 5 described later.
  • the potential difference is added to the voltage VW corresponding to the first data in consideration of the potential difference stepped down by the parasitic capacitance between the gate and the second terminal of the transistor M3. It is preferable to use a voltage that has been adjusted.
  • the amount of current flowing between the first terminal and the second terminal of the transistor M2 is determined by the voltage between the gate and the second terminal of the transistor M2, but is determined by the first terminal of the transistor M2.
  • Drain-induced barrier lowering may occur in transistor M2 due to the high power potential.
  • DIBL Drain-induced barrier lowering
  • the transistor included in the circuit MC of FIG. 1 may be configured as a transistor in which two or more transistors are connected in series. Such a configuration in which two or more transistors are connected in series may be referred to as a transistor having a multi-gate structure.
  • FIG. 4 shows a configuration example in which each of the transistors M2 to M10 is replaced with a transistor having a multi-gate structure in which two transistors are connected in series in FIG. 2A.
  • the transistor M2 has a transistor M2a and a transistor M2b
  • the transistor M3 has a transistor M3a and a transistor M3b
  • the transistor M4 has a transistor M4a and a transistor M4b.
  • the transistor M5 has a transistor M5a and a transistor M5b
  • the transistor M6 has a transistor M6a and a transistor M6b
  • the transistor M7 has a transistor M7a and a transistor M7b
  • the transistor M8 has a transistor M8a and a transistor M8b
  • the transistor M9 has a transistor M9a and a transistor M9b
  • the transistor M10 has a transistor M10a and a transistor M10b.
  • Each gate of the transistor M2a and the transistor M2b corresponds to the gate of the transistor M2 in FIG. 2A, and each back gate of the transistor M2a and the transistor M2b corresponds to the back gate of the transistor M2 in FIG. 2A.
  • 1st terminal corresponds to the 1st terminal of the transistor M2 in FIG. 2A.
  • the second terminal of the transistor M2a is electrically connected to the first terminal of the transistor M2b. Further, the second terminal of the transistor M2b corresponds to the second terminal of the transistor M2 in FIG. 2A.
  • the description of the connection configuration of the transistor M2a and the transistor M2b is referred to.
  • each of the transistor M3 and the transistor M4 included in the circuit MC into a transistor having a multi-gate structure, the leakage current flowing when each of the transistor M3 and the transistor M4 is in the off state can be generated. Can be lower. Further, when the transistor M3 or the transistor M4 is in the ON state, it is possible to prevent the drain-induced barrier reduction that occurs in the transistor.
  • each of the transistors M2 to M10 is shown as a transistor having a multi-gate structure, but the transistor M2 to the transistor M10 included in the circuit MC according to the semiconductor device of one aspect of the present invention is at least one. May be a transistor having a multi-gate structure.
  • FIG. 4 shows a configuration in which the transistor M1 included in the circuit MC is not replaced with a transistor having a multi-gate structure, the transistor M1 may be replaced with a transistor having a multi-gate structure (not shown). do not do.).
  • the channel length (sometimes referred to as L length) of each of the transistors M1 to M10 is specifically preferably 200 nm, more preferably 300 nm. , 400 nm is more preferable.
  • the channel length of the transistors included in each of the transistors M2 to M10 having a multi-gate structure is specifically preferably 100 nm, more preferably 150 nm, and more preferably 200 nm. Is more preferable.
  • ⁇ Change example 5 In the configuration of the circuit MC of FIG. 1, whether or not the high power supply potential given by the wiring VDE is supplied to the first terminal of the transistor M2 is determined by the on state or the off state of the transistor M1. By the way, since the wiring VDE is also electrically connected to the first terminal of the transistor M5 and the first terminal of the transistor M8, the wiring VDE is also connected to the first terminal of the transistor M5 and the first terminal of the transistor M8. A switching element for controlling the supply of the high power supply potential provided by the device may be provided.
  • the circuit MC shown in FIG. 5 is a modification of the circuit MC of FIG. 1, and has a configuration in which the first terminal of the transistor M5 and the first terminal of the transistor M8 are electrically connected to the second terminal of the transistor M1. It has become.
  • the circuit MC of FIG. 1 since the wiring VDE is electrically connected to the first terminal of the transistor M5 and the first terminal of the transistor M8, the first terminal and the second terminal of each of the transistor M5 and the transistor M8 are constantly connected.
  • the configuration is such that current flows between the terminals.
  • the circuit MC of FIG. 5 has a configuration in which a current flows between the first terminal and the second terminal of each of the transistor M2, the transistor M5, and the transistor M8 when the transistor M1 is turned on. Therefore, the circuit MC can stop the supply of the high power supply potential when the multiplication is not performed, and the power consumption can be reduced.
  • the transistor M2 is turned on by inputting a high level potential to the wiring WDL, the first terminals of the transistor M5 and the transistor M8 are the first terminal to the second terminal of the transistor M2. It becomes conductive with the wiring VGE via the space and between the first terminal and the second terminal of the transistor M4.
  • the constant voltage given by the wiring VGE as the ground potential
  • the ground potential of each of the second terminal of the transistor M2, the second terminal of the transistor M1, the first terminal of the transistor M5, and the first terminal of the transistor M8 is set. Can be.
  • the second terminal of the transistor M2 of the circuit MC Before performing multiplication in the circuit MC of FIG. 5, the second terminal of the transistor M2 of the circuit MC, the second terminal of the transistor M1, the first terminal of the transistor M5, the first terminal of the transistor M8, and the like are grounded in advance. By setting the potential, the circuit MC can stably perform the multiplication operation.
  • the circuit MC according to one aspect of the present invention can be configured by selecting a plurality of the above-mentioned configuration examples and appropriately combining them.
  • FIG. 6A is a circuit diagram showing a configuration example of a semiconductor device to which the circuit MCs of FIGS. 1 and 4 can be applied.
  • the semiconductor device SDV1 shown in FIG. 6A has a circuit WDC, a circuit XDC, a circuit BDC, a circuit WWC, a cell array CA, and a circuit ACTV.
  • the circuit ACTV has a circuit ADR [1] to a circuit ADR [n] as an example.
  • the cell array CA has a plurality of circuits MC as shown in FIGS. 1 and 4. Specifically, in the cell array CA, a plurality of circuits MC are arranged in a matrix of m rows and n columns (m is an integer of 1 or more and n is an integer of 1 or more).
  • the circuit MC [1,1], the circuit MC [m, 1], the circuit MC [1, n], and the circuit MC [m, n] are excerpted as the circuit MC in the cell array CA. And illustrated.
  • the circuit MC [1,1] includes wiring WDL [1], wiring WWL [1], wiring WWLB [1], wiring XDL [1], wiring BDL [1], and wiring OL [1]. Is electrically connected to. Further, the circuit MC [m, 1] includes the wiring WDL [1], the wiring WWL [m], the wiring WWLB [m], the wiring XDL [m], the wiring BDL [m], and the wiring OL [1]. ], And is electrically connected to. Further, the circuit MC [1, n] includes the wiring WDL [n], the wiring WWL [1], the wiring WWLB [1], the wiring XDL [1], the wiring BDL [1], and the wiring OL [n]. ], And is electrically connected to. Further, the circuit MC [m, n] includes wiring WDL [n], wiring WWL [m], wiring WWLB [m], wiring XDL [m], wiring BDL [m], and wiring OL [n]. ], And is electrically connected to. Further, the circuit MC [m,
  • the circuit MC [i, j] (not shown in FIG. 6A) has the wiring WDL [j] and the wiring WWL. It can be said that it is electrically connected to [i], the wiring WWLB [i], the wiring XDL [i], the wiring BDL [i], and the wiring OL [j].
  • the wiring WDL [j] corresponds to the wiring WDL shown in FIG. 1 and the like.
  • the wiring WWL [i] corresponds to the wiring WWL shown in FIG. 1 and the like
  • the wiring WWLB [i] corresponds to the wiring WWLB shown in FIG. 1 and the like.
  • the wiring XDL [i] corresponds to the wiring XDL shown in FIG. 1 and the like
  • the wiring BDL [i] corresponds to the wiring BDL shown in FIG. 1 and the like.
  • the wiring OL [j] corresponds to the wiring OL shown in FIG. 1 and the like.
  • the circuit WDC is electrically connected to the wiring WDL [1] to the wiring WDL [n].
  • the circuit XDC is electrically connected to the wiring XDL [1] to the wiring XDL [m].
  • the circuit BDC is electrically connected to the wiring BDL [1] to the wiring BDL [m].
  • the circuit WWC is electrically connected to the wiring WWL [1] to the wiring WWL [m] and the wiring WWLB [1] to the wiring WWLB [m].
  • each of the circuit ADR [1] to the circuit ADR [n] is electrically connected to the wiring OL [1] to the wiring OL [n] and the wiring ZL [1] to the wiring ZL [n].
  • the circuit WDC functions as a drive circuit that applies a voltage to each of the wiring WDL [1] to the wiring WDL [n] according to the first data for writing to the circuit MC included in the cell array CA.
  • the circuit XDC functions as a drive circuit that applies a voltage to each of the wiring XDL [1] to the wiring XDL [m] according to the second data to be input to the circuit MC included in the cell array CA. ..
  • the circuit BDC adjusts the amount of current flowing through the wiring OL for input to the circuit MC included in the cell array CA for each of the wiring BDL [1] to the wiring BDL [m]. It functions as a drive circuit that gives a voltage to do so.
  • the circuit WWC selects a circuit MC to which the first data is written when writing the first data to the circuit MC of the cell array CA for each of the wiring WWL [1] to the wiring WWL [m].
  • Has a function Specifically, for example, when the first data is written to the circuit MC [i, 1] to the circuit MC [i, n] located in the i-th row of the cell array CA, the circuit WWC is high in the wiring WWL [i].
  • the circuit MC [i, 1] to The circuit MC [i, n] can be selected.
  • the circuit WWC has a function of transmitting an inverted signal of a selection signal transmitted to the wiring WWL [i] to the wiring WWLB [i]. Further, the circuit WWC may transmit a different signal to the wiring WWLB [i] instead of the inverted signal. For example, the circuit WWC may have a function of inputting a low level potential to the wiring WWLB [i] when the low level potential is input to the wiring WWL [i]. As a result, the circuit MC as shown in FIG. 1 can simultaneously hold the first data and stop the supply of the high power supply potential to the first terminal of the transistor M2.
  • the sum of IY output by each of the circuits MC [1, j] to the circuit MC [m, j] flows in the wiring OL as the amount of current.
  • the current flowing through the transistor M2 of the circuit MC [i, j] is defined as I W [i, j]
  • the current flowing through the transistor M6 of the circuit MC [i, j] is defined as IX [i], from the wiring OL.
  • the amount of current flowing in the circuit MC [i, j] be I Y [i, j].
  • the amount of current flowing through each transistor M9 of the circuit MC [1, j] to the circuit MC [m, j] is IB
  • the amount of current IS [j] flowing through the wiring OL is expressed by the following equation. be able to.
  • the circuit ADR [j] has a function of outputting a voltage corresponding to the amount of current flowing from the wiring OL [j] to the circuit ADR [j], and a function system defined in advance using the voltage. It has a function of performing the calculation and a function of outputting the result of the calculation of the function to the wiring ZL [j].
  • the circuit ADR [j] can apply the configuration of the circuit ADR shown in FIG. 7A.
  • the circuit ADR of FIG. 7A has, for example, a transistor M11, a transistor M12, a capacitance C2, and a circuit ACF. Further, the circuit ACF has a terminal IT as an input terminal and a terminal OT as an output terminal.
  • the transistor M11 and the transistor M12 for example, a transistor applicable to a transistor M1, a transistor M3, a transistor M4, or the like can be used. Further, it is assumed that the same voltage as the operating range of the transistor M1, the transistor M3, the transistor M4 and the like is appropriately input to the gate, source, and drain of the transistor M11 or the transistor M12.
  • the first terminal of the transistor M11 is electrically connected to the wiring VDE, and the gate of the transistor M11 is electrically connected to the wiring RSL. Further, the first terminal of the transistor M12 is electrically connected to the wiring OL, and the second terminal of the transistor M12 includes the second terminal of the transistor M11, the first terminal of the capacitance C2, the terminal IT of the circuit ACF, and the like.
  • the gate of the transistor M12 is electrically connected to the wiring TXL. Further, the second terminal of the capacitance C2 is electrically connected to the wiring CVL. Further, the terminal OT of the circuit ACF is electrically connected to the wiring ZL.
  • the wiring OL shown in FIG. 7A corresponds to the wiring OL [j] (not shown) of FIG. 6A.
  • the wiring ZL shown in FIG. 7A corresponds to the wiring ZL [j] (not shown) in FIG. 6A.
  • the wiring CVL functions as a wiring that applies a constant voltage to the second terminal of the capacitance C2 in order to hold the potential between the first terminal and the second terminal of the capacitance C2.
  • the constant voltage can be, for example, a low level potential, a ground potential, a negative potential, or the like.
  • the potential given by the wiring CVL may be equal to the potential given by the wiring VGE, for example.
  • the wiring CVL may be the same wiring as the wiring VGE.
  • the wiring RSL functions as a wiring for transmitting a reset signal for writing an initialization potential to the first terminal of the capacitance C2 in the circuit ADR.
  • a low level potential is input to the wiring TXL to turn off the transistor M12, and a high level potential is applied to the wiring RSL.
  • the transistor M11 is turned on by inputting, and a high power supply potential (potential for initialization) is given from the wiring VDE to the first terminal of the capacitance C2. After that, by inputting a low level potential to the wiring RSL and turning off the transistor M11, the initialization of the potential of the first terminal of the capacitance C2 is completed.
  • the wiring TXL functions as a wiring for transmitting a signal for reading the current flowing through the wiring OL.
  • the potential of the first terminal of the capacitance C2 is used as the initialization potential, and then a high level potential is input to the wiring TXL to input the transistor M12. Is turned on to make the connection between the first terminal of the capacitance C2 and the wiring OL in a conductive state.
  • the wiring OL [j] (not shown) from the circuit ADR [j] to the equation (1.
  • the current of the current amount IS [j] described in 7) flows.
  • the amount of charge held in the first terminal of the capacitance C2 is the time and the amount of current IS [j] when the high level potential is applied to the wiring TXL . It depends on the product. Therefore, the potential of the first terminal of the capacitance C2 is determined by the capacitance value of the capacitance C2 and the amount of the electric charge.
  • the circuit ACF has a function of outputting a voltage corresponding to the potential of the input terminal of the circuit ACF, that is, the potential of the first terminal of the capacitance C2 to the output terminal of the circuit ACF.
  • the specific circuit configuration of the circuit ACF will be described later.
  • the circuit ADR applicable to the semiconductor device SDV1 of FIG. 6A is not limited to the configuration of FIG. 7A.
  • the circuit ADR applicable to the semiconductor device SDV1 may be, for example, the configuration of the circuit ADR shown in FIG. 7B.
  • the circuit ADR of FIG. 7B has a configuration in which the wiring BGLA is electrically connected to the back gates of the transistor M11 and the transistor M12.
  • the threshold voltage of each of the transistor M11 and the transistor M12 can be increased.
  • the off-current of each of the transistors M12 can be reduced.
  • the potential given to the wiring BGLA may be a variable potential instead of a fixed potential, as in the explanation of the wiring BGL of FIG. 2A.
  • each of the transistor M11 and the transistor M12 in the circuit ADR of FIG. 7B may be replaced with a transistor having a multi-gate structure.
  • the transistor M11 has a transistor M11a and a transistor M11b
  • the transistor M12 has a transistor M12a and a transistor M12b.
  • Each gate of the transistor M11a and the transistor M11b corresponds to the gate of the transistor M11 in FIG. 7B, and each back gate of the transistor M11a and the transistor M11b corresponds to the back gate of the transistor M11 in FIG. 7B.
  • the first terminal of the above corresponds to the first terminal of the transistor M11 in FIG. 7B.
  • the second terminal of the transistor M11a is electrically connected to the first terminal of the transistor M11b. Further, the second terminal of the transistor M11b corresponds to the second terminal of the transistor M11 in FIG. 7B.
  • each of the transistor M11 and the transistor M12 included in the circuit ADR a transistor having a multi-gate structure, the leakage current flowing when each of the transistor M11 and the transistor M12 is in the off state is made lower. can do. Further, when the transistor M11 or the transistor M12 is in the ON state, it is possible to prevent the drain-induced barrier reduction that occurs in the transistor.
  • the circuit ACF shown in FIG. 8A includes a transistor M13 and a transistor M14.
  • the transistor M13 and the transistor M14 for example, a transistor applicable to the transistor M2, the transistor M5, the transistor M10, or the like can be used. Further, it is assumed that the same voltage as the range in which the transistor M2, the transistor M5, the transistor M10 and the like operate is appropriately input to the gate, source, and drain of the transistor M13 or the transistor M14.
  • the gate of the transistor M13 is electrically connected to the terminal IT of the circuit ACF, the first terminal of the transistor M13 is electrically connected to the wiring VDE2, and the second terminal of the transistor M13 is connected to the first terminal of the transistor M14. , Is electrically connected to the terminal OT. Further, the second terminal of the transistor M14 is connected to the wiring VGE2, and the gate of the transistor M14 is electrically connected to the wiring BIL.
  • Wiring VDE2 functions as wiring that gives a constant voltage as an example.
  • the constant voltage can be a high power supply potential or the like.
  • the high power potential given by the wiring VDE2 can be equal to the high power potential given by the wiring VDE.
  • the high power potential given by the wiring VDE2 may be different from the high power potential given by the wiring VDE.
  • Wiring VGE2 functions as wiring that gives a constant voltage, for example.
  • the constant voltage can be a low power supply potential or the like.
  • the high power potential given by the wiring VGE2 can be equal to the low power potential given by the wiring VGE.
  • the low power potential given by the wiring VGE2 may be different from the low power potential given by the wiring VGE2.
  • the wiring BIL functions as a wiring for applying a constant voltage to be input to the gate of the transistor M14 as an example.
  • the circuit ACF can output a potential substantially equal to the potential input to the terminal IT of the circuit ACF from the terminal OT.
  • the grounded-emitter circuit shown in FIG. 8B can be applied.
  • the circuit ACF shown in FIG. 8B has, as an example, a transistor M15 and a load LE.
  • the load LE for example, a resistor, a diode, a transistor, or the like can be used.
  • the transistor M15 for example, a transistor applicable to a transistor M2, a transistor M5, a transistor M10, or the like can be used. Further, it is assumed that the same voltage as the range in which the transistor M2, the transistor M5, the transistor M10, and the like operate is appropriately input to the gate, source, and drain of the transistor M15.
  • the gate of the transistor M15 is electrically connected to the terminal IT of the circuit ACF, the first terminal of the transistor M15 is electrically connected to the first terminal of the load LE and the terminal OT of the circuit ACF, and the first terminal of the transistor M15 is connected.
  • the two terminals are electrically connected to the wiring VGE2. Further, the second terminal of the load LE is electrically connected to the wiring VDE2.
  • the circuit ACF can output a potential corresponding to the potential input to the terminal IT of the circuit ACF from the terminal OT.
  • the potential of the first terminal of the capacitance C2 drops significantly from the potential for initialization, so that the current flowing through the first terminal and the second terminal of the transistor M15 becomes small.
  • the voltage output from the terminal OT becomes high (close to the voltage given by the wiring VDE2).
  • the potential of the first terminal of the capacitance C2 has a small voltage drop from the potential for initialization, so that the current flowing through the first terminal and the second terminal of the transistor M15. Becomes larger and the voltage output from the terminal OT becomes lower (closer to the voltage given by the wiring VGE2).
  • a digital circuit can be applied as a specific configuration of the circuit ACF of FIGS. 7A to 7C.
  • a digital circuit for example, the buffer circuit shown in FIG. 8C can be applied.
  • the circuit ACF shown in FIG. 8C has an inverter circuit INV1 and an inverter circuit INV2 as an example.
  • the input terminal of the inverter circuit INV1 is electrically connected to the terminal IT of the circuit ACF
  • the output terminal of the inverter circuit INV1 is electrically connected to the input terminal of the inverter circuit INV2
  • the output terminal of the inverter circuit INV2 is a circuit. It is electrically connected to the terminal OT of the ACF.
  • the circuit ACF terminals either the high level potential or the low level potential according to the potential input to the terminal IT of the circuit ACF. It can be output from the OT.
  • the amount of current IS [j] when the amount of current IS [j] is large, the potential of the first terminal of the capacitance C2 drops significantly from the potential for initialization, so that the potential given to the input terminal of the inverter circuit INV1 becomes small and the terminal OT The voltage output from is a low level potential.
  • the amount of current IS [j] is small , the potential of the first terminal of the capacitance C2 has a small voltage drop from the potential for initialization. At this time, if the potential given to the input terminal of the inverter circuit INV1 does not fall below the threshold voltage of the inverter circuit INV1, the voltage output from the terminal OT becomes a high level potential.
  • the configuration of the buffer circuit applied to the circuit ACF of FIGS. 7A to 7C is not limited to the configuration of FIG. 8C.
  • the configuration of the buffer circuit applied to the circuit ACF of FIGS. 7A to 7C for example, the configuration shown in FIG. 8D may be used.
  • the circuit ACF shown in FIG. 8D includes a NAND circuit ND and an inverter circuit INV3.
  • the first input terminal of the NAND circuit ND is electrically connected to the terminal IT of the circuit ACF
  • the second input terminal of the NAND circuit ND is electrically connected to the wiring PI
  • the output terminal of the NAND circuit ND is an inverter. It is electrically connected to the input terminal of the circuit INV3, and the output terminal of the inverter circuit INV3 is electrically connected to the terminal OT of the circuit ACF.
  • the circuit ACF of FIG. 8D has a high level potential or a high level potential depending on the potential input to the terminal IT of the circuit ACF, similarly to the circuit ACF shown in FIG. 8C, when the low level potential is input to the wiring PI.
  • One of the low level potentials is output from the terminal OT. That is, the circuit ACF of FIG. 8D operates as a buffer circuit by inputting a signal (pulse voltage or the like) to the wiring PI, similarly to the circuit ACF shown in FIG. 8C.
  • NOR circuit may be used instead of the NAND circuit ND.
  • the first input terminal of the NOR circuit is electrically connected to the terminal IT
  • the second input terminal of the NOR circuit is electrically connected to the wiring PI
  • the output terminal of the NOR circuit is electrically connected to the input terminal of the inverter circuit INV3.
  • it operates as a buffer circuit, similar to the circuit ACF shown in FIG. 8C, when a high level potential is input to the wiring PI.
  • the amount of current IB flowing through the first terminal and the second terminal of the transistor M9 included in the circuit MC [1,1] to the circuit MC [m, n] is defined as the current amount IB. It can be treated as variables, constants, etc. of operations performed in the circuit ACF. Specifically, for example, in the circuit ACF of FIGS. 8A and 8B, when the current I Y of the equation (1.7) is input to the terminal IT of the circuit ACF, the circuit ACF is ⁇ I in 1 / IB. It can be regarded as a constant multiplied by W ⁇ IX .
  • the constant may be, for example, a coefficient for normalizing ⁇ I W ⁇ IX in the range of 0 or more and 1 or less.
  • 1 / IB is the activation performed in the circuit ACF. It can be regarded as a variable that changes the threshold value of the function. Specifically, for example, by reducing 1 / IB , YY becomes smaller, so that the threshold value can be relatively increased. Further, for example, since YY is increased by increasing 1 / IB , the threshold value can be relatively lowered.
  • the product-sum calculation of the neural network and the calculation of the activation function can be performed.
  • the calculation circuit of the activation function in the neural network the source ground circuit of FIG. 8B, the buffer circuit of FIG. 8C, or the buffer circuit of FIG. 8D can be applied.
  • the semiconductor device SDV2 shown in FIG. 6B is a modification of the semiconductor device SDV1 shown in FIG. 6A and has a circuit BGC.
  • the circuit BGC is electrically connected to the wiring BGL [1] to the wiring BGL [m].
  • the circuit BGC has a function of inputting a desired constant voltage to each of the wiring BGL [1] to the wiring BGL [m]. That is, the circuit BGC functions as a circuit that supplies a constant voltage to the back gate of each transistor included in the circuit MC [1,1] to the circuit MC [m, n].
  • the circuit applicable to the circuit MC [1,1] to the circuit MC [m, n] of the semiconductor device SDV2 of FIG. 6B is, for example, the circuit MC of FIGS. 2A, 2B, 4 and the like described above. Can be done.
  • FIG. 9A shows, as an example, a configuration in which the structure SIL and the structure OSL are provided above the substrate BSE. That is, the semiconductor device SDV1, the semiconductor device SDV2, and the like can be manufactured, for example, by forming a circuit element or the like on one substrate BSE.
  • various substrates can be used.
  • various substrates include semiconductor substrates (for example, single crystal substrate or silicon substrate), SOI substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, and stainless still foils.
  • glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass.
  • Examples of flexible substrates, laminated films, base films, etc. include the following.
  • plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyether sulfone
  • PTFE polytetrafluoroethylene
  • a synthetic resin such as acrylic.
  • polypropylene polyester, polyvinyl fluoride, polyvinyl chloride and the like.
  • polyamide, polyimide, aramid, epoxy resin, inorganic thin-film film, papers and the like are examples of plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE).
  • acrylic polypropylene
  • polyester polyvinyl fluoride
  • polyvinyl chloride polyvinyl chloride
  • a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to manufacture a transistor having a high current capacity and a small size with little variation in characteristics, size, or shape. ..
  • a circuit is configured with such transistors, it is possible to reduce the power consumption of the circuit or increase the integration of the circuit.
  • a flexible substrate may be used as the substrate BSE, and a transistor may be formed directly on the flexible substrate.
  • a release layer may be provided between the substrate and the transistor. The release layer can be used to separate a part or all of the semiconductor device from the substrate and transfer it to another substrate. At that time, the transistor can be reprinted on a substrate having inferior heat resistance, a flexible substrate, or the like.
  • a structure in which an inorganic film of a tungsten film and a silicon oxide film is laminated, a structure in which an organic resin film such as polyimide is formed on a substrate, or the like can be used.
  • a transistor may be formed using one substrate, then the transistor may be transposed to another substrate, and the transistor may be arranged on another substrate (for example, substrate BSE).
  • substrate BSE a substrate on which the transistor is translocated
  • silk, cotton, linen synthetic fibers
  • nylon, polyurethane, polyester or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, etc.
  • a part of the circuit necessary for realizing the predetermined function is formed on one board, and another part of the circuit necessary for realizing the predetermined function is formed on another board. It is possible. For example, a part of the circuit necessary to realize a predetermined function is formed on a glass substrate, and another part of the circuit necessary to realize a predetermined function is a single crystal substrate (or SOI substrate). Can be formed into. Then, a single crystal substrate (also referred to as an IC chip) on which another part of the circuit necessary for realizing a predetermined function is formed is connected to the glass substrate by COG (Chip On Glass) to be connected to the glass substrate.
  • COG Chip On Glass
  • the IC chip can be placed in the glass.
  • the IC chip can be connected to a glass substrate using a TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), a printed circuit board, or the like.
  • TAB Transmission Automated Bonding
  • COF Chip On Film
  • SMT Surface Mount Technology
  • a printed circuit board or the like.
  • a circuit having a large drive voltage or a circuit having a high drive frequency often consumes a large amount of power. Therefore, such a circuit is formed on a substrate (for example, a single crystal substrate) different from the pixel portion to form an IC chip. By using this IC chip, it is possible to prevent an increase in power consumption.
  • the substrate BSE as a semiconductor substrate, a transistor containing the semiconductor in the channel forming region can be formed on the upper surface of the substrate BSE.
  • the transistor formed on the upper surface of the substrate BSE is included in the structure SIL. That is, it can be said that the structure SIL has a circuit including the transistor.
  • the transistor included in the structure SIL can be a Si transistor. Therefore, it can be said that the structure SIL has a circuit including a Si transistor.
  • the structure OSL is provided above the structure SIL.
  • the structure OSL has, for example, a circuit including an OS transistor. Details will be described in the fifth embodiment, but the OS transistor can be provided above, for example, a flattened insulator, a conductor, or the like. That is, by applying the example of the laminated structure of FIG. 9A to the semiconductor device of one aspect of the present invention, it is possible to use two or more transistors having different semiconductor materials included in the channel forming region in the semiconductor device. can.
  • the substrate BSE as a semiconductor substrate containing silicon and the transistor included in the structure OSL as an OS transistor
  • the example of the laminated structure of FIG. 9A can be applied to the above-mentioned semiconductor device SDV1 and semiconductor device SDV2.
  • OS transistors and Si transistors can be used in circuits and the like included in semiconductor devices.
  • the structure OSL has, for example, a circuit WDC, a circuit XDC, a circuit BDC, a circuit WWC, a circuit MC, a circuit ACTV, and the like, and these circuits can be configured to include an OS transistor.
  • the structure SIL has, for example, a voltage source for supplying a voltage to those circuits, and the voltage source can be configured to include a Si transistor.
  • the structure OSL has, for example, a circuit selected from a circuit WDC, a circuit XDC, a circuit BDC, a circuit WWC, a circuit MC, a circuit ACTV, and the like, and the selected circuit may be configured to include an OS transistor.
  • the structure SIL can have, for example, the remaining circuits that have not been selected, and the remaining circuits can be configured to include Si transistors.
  • the structure OSL has, for example, a circuit WDC, a circuit XDC, a circuit BDC, a circuit WWC, a circuit MC, a circuit ACTV, and the like, and these circuits are configured to include an OS transistor
  • the structure SIL is, for example,. It may have a digital arithmetic circuit or the like, and the digital arithmetic circuit may be configured to include a Si transistor.
  • the operation of the neural network is performed by the semiconductor device
  • the operation of the first layer of the neural network is performed by the structure OSL
  • the operations of the second and subsequent layers of the neural network are performed by the digital calculation circuit included in the structure SIL. It can be carried out.
  • the laminated structure shown in FIG. 9B may be applied.
  • the laminated structure of FIG. 9B is different from the laminated structure of FIG. 9A in that the structure OSL1 is provided above the structure SIL and the structure OSL2 is provided above the structure OSL1.
  • Each of the structure OSL1 and the structure OSL2 can have a circuit including an OS transistor as in the structure OSL of FIG. 9A. That is, a structure having another OS transistor can be laminated on the structure having the OS transistor. Further, FIG.
  • FIG. 9B shows a laminated structure in which two structures, a structure OSL1 and a structure OSL2, are provided above the structure SIL, but a structure having an OS transistor provided above the structure SIL. May be 3 or more.
  • the circuit scale becomes large, the area of the substrate BSE on which the circuit is formed can be reduced by stacking a plurality of structures having OS transistors.
  • the semiconductor device SDV1 and the semiconductor device SDV2 have a structure in which the structure OSL is provided above the substrate BSE as shown in FIG. 9C. Can be done. That is, a structure having an OS transistor may be provided on the substrate BSE. In other words, a circuit including an OS transistor may be manufactured on the substrate BSE.
  • FIGS. 9A to 9C a sensor may be provided above FIGS. 9A to 9C.
  • FIG. 9D shows a laminated structure in which a structure PDL having a sensor is provided above the structure OSL of FIG. 9A.
  • the sensor included in the structure PDL can sense information from the outside world and convert it into a current or a voltage.
  • the sensor may be, for example, an optical sensor (photo diode), a pressure sensor, a gyro sensor, an acceleration sensor, an auditory sensor, a temperature sensor, a humidity sensor, a taste sensor, an odor sensor, or the like.
  • the calculation is performed based on the information obtained by the sensor. be able to.
  • the information obtained by the sensor can be used as input data to infer the input data.
  • a semiconductor device in the case where an optical sensor (photodiode) is applied as a sensor included in the structure PDL is described.
  • the circuit MC shown in any one of FIGS. 1 to 5 the voltage corresponding to the first data can be written to the circuit MC. Further, the circuit MC can output the current YY corresponding to the product of the first data and the second data to the wiring OL. Further, by using the semiconductor device SDV1 of FIG. 6A or the semiconductor device SDV2 of FIG. 6B, the product sum of the plurality of first data and the plurality of second data can be calculated.
  • Each circuit MC described in the first embodiment has a configuration (voltage writing type) in which a current I W is generated in the transistor M2 by writing a voltage corresponding to the first data to the first terminal of the capacitance C2.
  • the semiconductor device according to one aspect of the present invention may be configured to generate a current IW in the transistor M2 by writing a current according to the first data (current writing type).
  • a circuit MC that generates a current I W by writing a current will be described.
  • the circuit MC shown in FIG. 10 is a modification of the circuit MC of FIG. 1, and has a configuration in which it does not have the transistor M3 and the capacitive CG but has the transistor M3A and the transistor M2A.
  • the transistor M3A for example, a transistor applicable to the transistor M3 included in the circuit MC of FIG. 1 can be used. Further, it is assumed that the same voltage as the range in which the transistor M3 operates is appropriately input to the gate, source, and drain of the transistor M3A.
  • the transistor M2A for example, a transistor applicable to the transistor M2 included in the circuit MC of FIG. 1 can be used. Further, it is assumed that the same voltage as the range in which the transistor M2 operates is appropriately input to the gate, source, and drain of the transistor M2A. Further, the size of the transistor M2A is preferably equal to the size of the transistor M2 shown in FIG. In particular, by making the sizes of the transistor M2 and the transistor M2A substantially equal, the transistor M2 and the transistor M2A function as a current mirror circuit by their electrical connection, so that the first terminal of the transistor M2-. The amount of current flowing between the second terminals can be made substantially equal to the amount of current flowing between the first terminal and the second terminal of the transistor M2A.
  • the first terminal of the transistor M3A is electrically connected to the first terminal of the transistor M2A and the wiring WDIL, and the second terminal of the transistor M3A is the gate of the transistor M2, the gate of the transistor M2A, and the capacitance C1. It is electrically connected to the first terminal, and the gate of the transistor M3A is electrically connected to the wiring WWL. Further, the second terminal of the transistor M2A is electrically connected to the wiring VGE.
  • the wiring WDIL functions as a write data line (current line) for passing a current corresponding to the first data to the circuit MC as an example.
  • the amount of current substantially equal to the amount of current according to the first data from the wiring WDIL is set to the first terminal of the transistor M2. It can flow between two terminals.
  • the potential given by the wiring VDE is a high power supply potential
  • the potential given by the wiring VGE is a ground potential (VGND).
  • a high level potential is input to the wiring WWL.
  • the high level potential is input to the respective gates of the transistor M3A and the transistor M4, so that the transistor M3A and the transistor M4 are turned on.
  • the second terminal of the capacitance C1 (the second terminal of the transistor M2) is in a conductive state via the transistor M4, the second terminal of the capacitance C1 (the second terminal of the transistor M2) is in a conductive state.
  • the potential of the terminal is V GND .
  • the wiring WDIL and the first terminal of the capacitance C1 are in a conductive state via the transistor M3A. Therefore, the transistor M2A has a diode connection configuration.
  • a current amount corresponding to the first data flows from the wiring WDIL to the circuit MC, so that the potentials of the first terminal of the transistor M2A and the gate correspond to the current. It becomes the potential (hereinafter referred to as V W ). At this time, the voltage V W is written to the first terminal of the capacitance C1. Further, a current having a current amount of IW flows between the first terminal and the second terminal of the transistor M2A.
  • the inverted signal of the signal transmitted to the wiring WWL is input to the wiring WWLB. Specifically, a low level potential is input to the wiring WWLB. Therefore, the low level potential is applied to the gate of the transistor M1. As a result, the transistor M1 is turned off.
  • the voltage V W is written to the first terminal (gate of the transistor M2) of the capacitance C1
  • a low level potential is input to the wiring WWL.
  • the low level potential is input to the respective gates of the transistor M3A and the transistor M4, so that the transistor M3A and the transistor M4 are turned off.
  • the first terminal of the capacitance C1 is in a floating state, so that the voltage VW ⁇ V GND between the first terminal and the second terminal of the capacitance C1 is maintained. That is, the voltage between the gate and the second terminal of the transistor M2 is substantially equal to the voltage between the gate and the second terminal of the transistor M2A.
  • the inverted signal of the signal transmitted to the wiring WWL is input to the wiring WWLB, a high level potential is input to the wiring WWLB at this time. Therefore, the high level potential is applied to the gate of the transistor M1 and the transistor M1 is turned on. Therefore, the wiring VDE is in a conductive state with the first terminal of the transistor M2, and a high power potential of the wiring VDE is given to the first terminal of the transistor M2.
  • the size of the transistor M2 is equal to the size of the transistor M2A at this time.
  • the current flowing between the first terminal and the second terminal of the transistor M2 is approximately equal to the current amount I W flowing between the first terminal and the second terminal of the transistor M2A.
  • the current amount IW can be written to the circuit MC as the current corresponding to the first data.
  • a transformer having a multi-gate structure may be applied as in the circuit MC of FIG.
  • the circuit MC shown in FIG. 11 shows a configuration example in which the transistor M2, the transistor M2A, the transistor M3A, and the transistors M4 to M10 included in the circuit MC of FIG. 10 are replaced with transistors having a multi-gate structure.
  • the transistor M2 has a configuration having a transistor M2a and a transistor M2b
  • a transistor M2A has a configuration having a transistor M2Aa and a transistor M2Ab
  • a transistor M3A has a configuration having a transistor M3Aa and a transistor M3Ab
  • a transistor M4 has a configuration.
  • the configuration includes the transistor M4a and the transistor M4b, the transistor M5 has the transistor M5a and the transistor M5b, the transistor M6 has the transistor M6a and the transistor M6b, and the transistor M7 has the transistor M7a and the transistor M7b.
  • the transistor M8 has a transistor M8a and a transistor M8b, the transistor M9 has a transistor M9a and a transistor M9b, and the transistor M10 has a transistor M10a and a transistor M10b. As shown in FIG.
  • the transistor M2A, the transistor M3A, and the transistor M4 measures against the drain-induced barrier reduction that occurs in the on state in each transistor and / Alternatively, the leakage current of the transistor in the off state can be reduced.
  • each of the transistor M2, the transistor M2A, the transistor M3A, and the transistors M4 to M10 is shown as a transistor having a multi-gate structure in FIG. 11, it is included in the circuit MC according to the semiconductor device of one aspect of the present invention. At least one of the transistor M2, the transistor M2A, the transistor M3A, and the transistor M4 to the transistor M10 may be a transistor having a multi-gate structure. Further, although FIG. 11 shows a configuration in which the transistor M1 included in the circuit MC is not replaced with a transistor having a multi-gate structure, the transistor M1 may be replaced with a transistor having a multi-gate structure (not shown). do not do.).
  • FIG. 12 is a circuit diagram showing a configuration example of a semiconductor device to which the circuit MC shown in FIG. 10 or 11 can be applied.
  • the semiconductor device SDV3 shown in FIG. 12 is a modification of the semiconductor device SDV1 shown in FIG. 6A, and has a circuit WDIC instead of a circuit WDC. Further, in the semiconductor device SDV3 of FIG. 12, wiring WDIL [1] to wiring WDIL [n] is extended instead of wiring WDL [1] to wiring WDL [n].
  • the semiconductor device SDV3 of FIG. 12 is a modification of the semiconductor device SDV1 of FIG. 6A, the description of the semiconductor device SDV1 will be taken into consideration for the parts common to the semiconductor device SDV1 in the configuration of the semiconductor device SDV3.
  • the circuit WDIC has a function of supplying a current in an amount corresponding to the first data to each of the wiring WDIL [1] to the wiring WDIL [n].
  • the circuit WDIC is electrically connected to each of the wiring WDIL [1] to the wiring WDIL [n].
  • FIG. 13A is a block diagram showing an example of the circuit WDIC. Note that FIG. 13A also shows the wiring WDIL in order to show the electrical connection with the circuit around the circuit WDIC.
  • the circuit WDIC has, for example, as many circuits WDICA as there are wiring WDILs. That is, the circuit WDIC has n circuits WDICA. Therefore, the wiring WDIL shown in FIG. 13A can be any one of the wiring WDIL [1] and the wiring WDIL [n] included in the semiconductor device SDV3 of FIG. Therefore, a separate circuit WDICA is electrically connected to each of the wiring WDIL [1] to the wiring WDIL [n].
  • the circuit WDICA shown in FIG. 13A has a switch SWW as an example.
  • the first terminal of the switch SWW is electrically connected to the wiring WDIL, and the second terminal of the switch SWW is electrically connected to the wiring VINIL1.
  • the wiring VINIL 1 functions as a wiring that gives a potential for initialization to the wiring WDIL, and the potential for initialization can be a negative potential, a ground potential (GND), a low level potential, a high level potential, or the like.
  • the potential for the initialization as an example, the potential when the first data is set to "0" can be used.
  • the switch SWW for example, an analog switch, an electric switch such as a transistor, or the like can be applied.
  • the transistor can be a transistor having the same structure as the transistor M1, the transistor M3, and the transistor M4.
  • a mechanical switch may be applied.
  • the circuit WDICA of FIG. 13A has a plurality of current sources CS as an example.
  • the circuit WDICA has a function of outputting the first data of K bits (2 K value) (K is an integer of 1 or more) as a current amount, and in this case, the circuit WDICA has 2 K -1 pieces.
  • the circuit WDICA has one current source CS that outputs information corresponding to the value of the first bit as a current, and has two current source CSs that output information corresponding to the value of the second bit as a current. It also has 2K-1 current sources CS that output information corresponding to the value of the K-th bit as a current.
  • each current source CS has a terminal T1 and a terminal T2.
  • the terminal T1 of each current source CS is electrically connected to the wiring WDIL.
  • the terminal T2 of one current source CS is electrically connected to the wiring DW [1]
  • each of the terminals T2 of the two current source CS is electrically connected to the wiring DW [2].
  • Each of the terminals T2 of one current source CS is electrically connected to the wiring DW [K].
  • the plurality of current sources CS included in the circuit WDICA each have a function of outputting I Wut from the terminal T1 as the same constant current.
  • the error of the constant current I Wut output from each of the terminals T1 of the plurality of current sources CS is preferably 10% or less, more preferably 5% or less, and even more preferably 1% or less. In this embodiment, it is assumed that there is no error in the constant current I Wut output from the terminals T1 of the plurality of current sources CS included in the circuit WDICA.
  • the wiring DW [1] to the wiring DW [K] functions as wiring for transmitting a control signal for outputting a constant current I Wut from the electrically connected current source CS.
  • the current source CS electrically connected to the wiring DW [1] transmits I Wut to the wiring WDIL as a constant current.
  • the current source CS electrically connected to the wiring DW [1] does not output I Wut .
  • the two current sources CS electrically connected to the wiring DW [2] draw a constant current of a total of 2I Wut in the wiring WDIL .
  • the current source CS electrically connected to the wiring DW [2] does not output a constant current of 2I Wut in total.
  • the total of 2 K- 1 current sources CS electrically connected to the wiring DW [K] is 2 K-1 I.
  • the current flowing by one current source CS electrically connected to the wiring DW [1] corresponds to the value of the first bit
  • the two currents electrically connected to the wiring DW [2] correspond to the value of the first bit
  • the current flowing by the source CS corresponds to the value of the second bit
  • the amount of current flowing by the K current source CS electrically connected to the wiring DW [K] corresponds to the value of the K bit.
  • I Wut flows from the circuit WDICA to the wiring WDIL as a constant current. Further, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is given to the wiring DW [1] and a high level potential is given to the wiring DW [2]. Is given. At this time, 2I Wut flows from the circuit WDICA to the wiring WDIL as a constant current. Further, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high level potential is given to the wiring DW [1] and the wiring DW [2]. At this time, 3I Wut flows from the circuit WDICA to the wiring WDIL as a constant current.
  • FIG. 13A illustrates the circuit WDICA when K is an integer of 3 or more, but when K is 1, the circuit WDICA of FIG. 13A is connected to the wiring DW [2] to the wiring DW [K].
  • the configuration may be such that the current source CS electrically connected to is not provided.
  • the circuit WDICA in FIG. 13A may be configured so as not to provide the current source CS electrically connected to the wiring DW [3] (not shown) to the wiring DW [K]. good.
  • the current source CS1 shown in FIG. 14A is a circuit applicable to the current source CS included in the circuit WDICA of FIG. 13A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. It is connected.
  • the second terminal of the transistor Tr2 is electrically connected to the terminal T1, and the gate of the transistor Tr2 is electrically connected to the terminal T2. Further, the terminal T2 is electrically connected to the wiring DW.
  • the wiring DW is any one of the wiring DW [1] to the wiring DW [K] in FIG. 13A.
  • Wiring VDDL functions as wiring that gives a constant voltage.
  • the constant voltage can be, for example, a high level potential.
  • the constant voltage given by the wiring VDDL is set to a high level potential
  • a high level potential is input to the first terminal of the transistor Tr1.
  • the potential of the second terminal of the transistor Tr1 is set to a potential lower than the high level potential.
  • the first terminal of the transistor Tr1 functions as a drain
  • the second terminal of the transistor Tr1 functions as a source.
  • the gate-source voltage of the transistor Tr1 is 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the current range of the subthreshold region flows between the first terminal and the second terminal of the transistor Tr1.
  • the transistor Tr2 functions as a switching element.
  • the first terminal of the transistor Tr2 functions as a drain and the second terminal of the transistor Tr2 functions as a source.
  • the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, the voltage between the back gate and the source is 0V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on by inputting a high level potential to the gate of the transistor Tr2, and the gate of the transistor Tr2 is low. When the level potential is input, the transistor Tr2 is turned off.
  • the current in the current range of the subthreshold region described above flows from the second terminal of the transistor Tr1 to the terminal T1, and when the transistor Tr2 is in the off state, the current is the transistor Tr1. It is assumed that the current does not flow from the second terminal to the terminal T1.
  • the circuit applicable to the current source CS included in the circuit WDICA of FIG. 13A is not limited to the current source CS1 of FIG. 14A.
  • the current source CS1 has a configuration in which the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, but the back gate of the transistor Tr2 is electrically connected to another wiring. It may be configured as such.
  • An example of such a configuration is shown in FIG. 14B.
  • the current source CS2 shown in FIG. 14B has a configuration in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL.
  • the threshold voltage of the transistor Tr2 can be changed. In particular, by increasing the threshold voltage of the transistor Tr2, the off-current of the transistor Tr2 can be reduced.
  • the current source CS1 of FIG. 14A has a configuration in which the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected.
  • the back gate of the transistor Tr2 and the second terminal It may be configured to hold the voltage depending on the capacity during the period.
  • FIG. 14C An example of such a configuration is shown in FIG. 14C.
  • the current source CS3 shown in FIG. 14C has a transistor Tr3 and a capacitance C6 in addition to the transistor Tr1 and the transistor Tr2.
  • the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are electrically connected via the capacitance C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are electrically connected.
  • the current source CS3 has a configuration in which the second terminal of the transistor Tr3 is electrically connected to the wiring VTL, and the gate of the transistor Tr3 is electrically connected to the wiring VWL.
  • the current source CS3 can make the wiring VTL and the back gate of the transistor Tr1 conductive by applying a high level potential to the wiring VWL to turn on the transistor Tr3.
  • a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1.
  • the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be maintained by the capacitance C6. That is, the threshold voltage of the transistor Tr1 can be changed by determining the voltage applied to the back gate of the transistor Tr1 by the wiring VTL, and the threshold voltage of the transistor Tr1 is fixed by the transistor Tr3 and the capacitance C6. can do.
  • the circuit applicable to the current source CS included in the circuit WDICA of FIG. 13A may be the current source CS4 shown in FIG. 14D.
  • the current source CS4 has a configuration in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL instead of the second terminal of the transistor Tr2 in the current source CS3 of FIG. 14C. That is, the current source CS4 can change the threshold voltage of the transistor Tr2 according to the potential given by the wiring VTHL, similarly to the current source CS2 of FIG. 14B.
  • the current source CS4 when a large current flows between the first terminal and the second terminal of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to allow the current to flow from the terminal T1 to the outside of the current source CS4. ..
  • the current source CS4 applies a high level potential to the wiring VTHL, lowers the threshold voltage of the transistor Tr2, and raises the on-current of the transistor Tr2, so that the first terminal of the transistor Tr1 ⁇ 2nd. A large current flowing between the terminals can be passed from the terminal T1 to the outside of the current source CS4.
  • the circuit WDICA By applying the current sources CS1 to CS4 shown in FIGS. 14A to 14D as the current source CS included in the circuit WDICA of FIG. 13A, the circuit WDICA outputs a current corresponding to the first data of the K bit. can do. Further, the amount of the current can be, for example, the amount of current flowing between the first terminal and the second terminal within the range in which the transistor M2A operates in the subthreshold region.
  • the circuit WDICA of FIG. 13A has a configuration in which one current source CS1 of FIG. 14A is connected to each of the wiring DW [1] to the wiring DW [K]. Further, when the channel width of the transistor Tr1 [1] is w [1], the channel width of the transistor Tr1 [2] is w [2], and the channel width of the transistor Tr1 [K] is w [K], each channel is used.
  • the circuit WDICA shown in FIG. 13B corresponds to the first data of K bits like the circuit WDICA of FIG. 13A. It can output current.
  • the transistor Tr1 (including the transistor Tr1 [1] to the transistor Tr2 [K]), the transistor Tr2 (including the transistor Tr2 [1] to the transistor Tr2 [K]), and the transistor Tr3 are, for example, the transistor M1 to the transistor M10.
  • Transistors applicable to the above can be used.
  • an OS transistor may be used as the transistor Tr1 (including the transistor Tr1 [1] to the transistor Tr1 [K]), the transistor Tr2 (including the transistor Tr2 [1] to the transistor Tr2 [K]), and the transistor Tr3. preferable.
  • the current corresponding to the first data can be written to the circuit MC. Further, by making the sizes of the transistor M2 and the transistor M2A substantially equal to each other, the amount of current substantially equal to the amount of current according to the first data from the wiring WDIL can be reduced to the first terminal-2nd of the transistor M2. It can flow between terminals. As a result, the circuit MC can output the current YY corresponding to the product of the first data and the second data to the wiring OL.
  • FIG. 15A is a circuit diagram showing a configuration example of a circuit MC and a circuit ISC included in the semiconductor device described in the present embodiment.
  • the circuit MC of FIG. 15A takes into account the description of the circuit MC shown in FIG.
  • the circuit ISC of FIG. 15A is an example of a pixel circuit including an image pickup device, and has a photodiode PD and a circuit PE.
  • the circuit PE has a transistor M6A and a transistor M16.
  • the transistor M6A for example, a transistor applicable to the transistor M6 included in the circuit MC of FIG. 1 can be used. Further, it is assumed that the same voltage as the range in which the transistor M6 operates is appropriately input to the gate, source, and drain of the transistor M6A. Further, the size of the transistor M6A is preferably equal to the size of the transistor M6. In particular, by making the sizes of the transistor M6 and the transistor M6A substantially equal, the transistor M6 and the transistor M6A function as a current mirror circuit by their electrical connection, so that the first terminal of the transistor M6-. The amount of current flowing between the second terminals can be made substantially equal to the amount of current flowing between the first terminal and the second terminal of the transistor M6A.
  • the transistor M16 for example, a transistor applicable to the transistor M1, the transistor M3, the transistor M4, etc. included in the circuit MC of FIG. 1 can be used. Further, it is assumed that the same voltage as the range in which the transistor M1, the transistor M3, the transistor M4 and the like operate is appropriately input to the gate, the source, and the drain of the transistor M16.
  • the first terminal of the transistor M6A is electrically connected to the gate of the transistor M6A and the first terminal of the transistor M16, and the second terminal of the transistor M6A is electrically connected to the wiring VGE3. Further, the first terminal and the gate of the transistor M6A are electrically connected to the wiring XDL.
  • the second terminal of the transistor M16 is electrically connected to the input terminal (anode) of the photodiode PD, and the output terminal (cathode) of the photodiode PD is electrically connected to the wiring VDE3. Further, the gate of the transistor M16 is electrically connected to the wiring IML.
  • Wiring VDE3 functions as wiring that gives a constant voltage, for example.
  • the constant voltage may be, for example, a high power supply voltage.
  • the wiring VGE3 functions as a wiring that applies a constant voltage as an example.
  • the constant voltage may be, for example, a low power supply voltage, a ground potential, or the like. Further, when the constant voltage given by each of the wiring VGE3 and the wiring VGE is equal, the wiring VGE3 may be treated as the wiring VGE.
  • the wiring IML functions as a wiring for transmitting a signal for passing a current generated by the photodiode PD between the first terminal and the second terminal of the transistor M6A.
  • a current generated by the photodiode PD is passed between the first terminal and the second terminal of the transistor M6A, a high level potential is input to the wiring IML to turn on the transistor M16. Make a conduction state between the input terminal of the photodiode PD and the first terminal of the transistor M6A.
  • the photodiode PD is irradiated with light, the current generated by the photodiode PD flows between the first terminal and the second terminal of the transistor M6A.
  • the constant voltage given by the wiring VDE3 is a high power supply potential or the like. Therefore, when the photodiode PD is irradiated with light, a positive current flows from the output terminal of the photodiode PD toward the input terminal. Therefore, when the photodiode PD is irradiated with light, a current flows from the wiring VDE3 to the input terminal via the output terminal of the photodiode PD.
  • the input terminal and the output terminal of the photodiode PD may be interchanged (not shown).
  • the input terminal (anode) of the photodiode PD is electrically connected to the wiring VDE3 (high power potential side)
  • the output terminal (cathode) of the photodiode PD is the wiring VGE3 (low power potential side).
  • the circuit ISC may be able to operate by making it electrically connected to the circuit ISC. Further, in this case, if necessary, one or more of the transistors included in the circuit ISC and the circuit MC may be changed from the n-channel type transistor to the p-channel type transistor.
  • the potential given by the wiring VDE and the wiring VDE3 is a high power supply potential
  • the potential given by the wiring VGE and the wiring VGE3 is a ground potential (VGND).
  • a high level potential is input to the wiring IML.
  • the high level potential is input to the gate of the transistor M16, so that the transistor M16 is turned on.
  • the first terminal of the transistor M6A and the input terminal of the photodiode PD are in a conductive state via the transistor M16.
  • the photodiode PD when the photodiode PD is irradiated with light, the photodiode PD generates a current amount (hereinafter referred to as IX ) corresponding to the second data (light intensity).
  • IX a current amount
  • a current of the amount IX flows from the input terminal of the photodiode PD to the first terminal of the transistor M6A via the transistor M16, so that the potentials of the first terminal of the transistor M6A and the gate correspond to the current. (Hereinafter, it is referred to as V X. ).
  • V W is written to the first terminal of the capacitance C1.
  • a current having a current amount of IW flows between the first terminal and the second terminal of the transistor M6A.
  • the voltage between the gate and the second terminal of the transistor M6 is V X -V GND
  • the voltage between the gate and the second terminal of the transistor M6A is V X -V GND . That is, the voltage between the gate and the second terminal of the transistor M6 is substantially equal to the voltage between the gate and the second terminal of the transistor M6A.
  • the size of the transistor M6 is equal to the size of the transistor M6A at this time.
  • the current flowing between the first terminal and the second terminal of the transistor M6 is approximately equal to the current amount IX flowing between the first terminal and the second terminal of the transistor M6A.
  • the current amount IX can be input to the circuit MC as the current corresponding to the second data.
  • the circuit MC is provided with a capacity for holding the voltage between the gate of the transistor M6 and the second terminal, and the gate of the transistor M6 is floated. May be provided to hold the potential (V X ) of the gate of the transistor M6.
  • FIG. 15B The configuration of the circuit ISC and the circuit MC in this case is shown in FIG. 15B.
  • the circuit ISC and the circuit MC of FIG. 15B are modifications of the circuit ISC and the circuit MC of FIG. 15A, and the circuit MC has a transistor M6A, a transistor M17, and a capacitance C3. Further, the circuit ISC of FIG. 15B does not have the transistor M6A, unlike the circuit ISC of FIG. 15A.
  • the transistor M17 for example, a transistor applicable to the transistor M1, the transistor M3, the transistor M4, etc. included in the circuit MC of FIG. 1 can be used. Further, it is assumed that the same voltage as the range in which the transistor M1, the transistor M3, the transistor M4 and the like operate is appropriately input to the gate, the source, and the drain of the transistor M17.
  • the capacity C3 for example, a capacity that can be applied to the capacity C1, the capacity CG, and the like described in the present specification and the like can be used.
  • the first terminal of the transistor M17 is electrically connected to the first terminal of the transistor M6A, and the second terminal of the transistor M17 is electrically connected to the gate of the transistor M6A and the gate of the transistor M6.
  • the gate is electrically connected to the wiring XWL.
  • the first terminal of the capacitance C3 is electrically connected to the gate of the transistor M6A and the gate of the transistor M6, and the second terminal of the capacitance C3 is electrically connected to the wiring VGE.
  • the wiring XWL functions as a wiring that controls switching between the on state and the off state of the transistor M17, as an example. Specifically, for example, the wiring XWL functions as a selection signal line for selecting a circuit MC in which a current corresponding to the second data is written.
  • the circuit MC and the circuit ISC shown in FIG. 16 show a configuration example in which the transistor M6 and the transistor M6A included in the circuit MC of FIG. 15A are replaced with a transistor having a multi-gate structure.
  • measures against the drain-induced barrier reduction that occurs in the on state and / or the leakage current of the transistor in the off state are taken in each transistor. Can be reduced.
  • the transistor M6 has a transistor M6a and a transistor M6b
  • the transistor M6A has a transistor M6Aa and a transistor M6Ab.
  • each gate of the transistor M6a and the transistor M6b corresponds to the gate of the transistor M6 in FIG. 15A
  • the first terminal of the transistor M6a corresponds to the first terminal of the transistor M6 in FIG. 15A.
  • the second terminal of the transistor M6a is electrically connected to the first terminal of the transistor M6b.
  • the second terminal of the transistor M6b corresponds to the second terminal of the transistor M6 in FIG. 15A.
  • each gate of the transistor M6Aa and the transistor M6Ab corresponds to the gate of the transistor M6A in FIG. 15A
  • the first terminal of the transistor M6Aa corresponds to the first terminal of the transistor M6A in FIG. 15A.
  • the second terminal of the transistor M6Aa is electrically connected to the first terminal of the transistor M6Ab.
  • the second terminal of the transistor M6b corresponds to the second terminal of the transistor M6 in FIG. 15A.
  • each of the transistor M6 and the transistor M6A is shown as a transistor having a multi-gate structure in FIG. 16, the transistor M1 to the transistor M10, the transistor M6A, and the transistor M16 according to the semiconductor device of one aspect of the present invention are at least.
  • One may be a transistor having a multi-gate structure.
  • at least one of the transistors M1 to M10, the transistor M6A, the transistor M16, and the transistor M17 may be a transistor having a multi-gate structure.
  • FIG. 17 shows a configuration example of a semiconductor device including the circuit MC of FIGS. 15A and 16 and the circuit ISC.
  • the semiconductor device SDV4 shown in FIG. 17 has, as an example, a circuit PDA, a circuit PEA, and a cell array CA.
  • the circuit PEA is located above the cell array CA as an example. Further, the circuit PDA is located above the circuit PEA as an example.
  • the transistor included in the circuit PEA has the same structure as the transistor included in the cell array CA, the circuit PEA and the cell array CA are simultaneously manufactured in the same layer by the same process. Can be (not shown).
  • the circuit PDA has a photodiode PD [1] to a photodiode PD [m] (where m is an integer of 1 or more). Further, in the circuit PDA, the photodiode PD [1] to the photodiode PD [m] are arranged in a matrix of m / h rows and h columns (h is an integer of 1 or more and is a divisor of m). Has been done. Any one of the photodiode PD [1] to the photodiode PD [m] corresponds to the photodiode PD included in the circuit ISC shown in FIGS. 15A and 16.
  • the circuit PEA has a circuit PE [1] to a circuit PE [m]. Further, in the circuit PEA, the circuit PE [1] to the circuit PE [m] are arranged in a matrix of m / h rows and columns, similarly to the circuit PDA. Further, any one of the circuit PE [1] to the circuit PE [m] corresponds to the circuit PE included in the circuit ISC shown in FIGS. 15A and 16.
  • the cell array CA has a circuit MC [1] to a circuit MC [m]. Further, in the cell array CA, the circuits MC [1] to the circuits MC [m] are arranged in a matrix of m rows and 1 column. Further, any one of the circuit MC [1] to the circuit MC [m] corresponds to the circuit MC shown in FIGS. 15A and 16.
  • the circuit WDC and the circuit BDC similar to the semiconductor device SDV1 of FIG. 6A, the semiconductor device SDV2 of FIG. 6B, or the semiconductor device SDV3 of FIG.
  • a circuit WWC, a circuit ACTV, or the like may be provided.
  • the photodiode PD [1] is electrically connected to the circuit MC [1] via the circuit PE [1] and the wiring XDL [1]. Further, the photodiode PD [h] is electrically connected to the circuit MC [h] via the circuit PE [h] and the wiring XDL [h].
  • the photodiode PD [m-h + 1] is electrically connected to the circuit MC [m-h + 1] via the circuit PE [m-h + 1] and the wiring XDL [m-h + 1]. Further, the photodiode PD [m] is electrically connected to the circuit MC [m] via the circuit PE [m] and the wiring XDL [m].
  • image data can be captured as a plurality of second data by the photodiode PD [1] to the photodiode PD [m] included in the circuit PDA. Further, a plurality of first data are written in advance in the circuit MC [1] to the circuit MC [m] of the cell array CA, and then each of the plurality of second data is transferred to the circuit MC [1] to the circuit MC [m]. By transmitting, the product-sum operation of the first data and the second data can be executed. Further, the function may be calculated using the result of the product-sum operation.
  • the above product-sum calculation can be performed by the photodiode PD [1].
  • To the image data captured by the photodiode PD [m] can be regarded as a convolution process. Further, when the convolution process is performed, for example, the ReLU function can be used as the operation of the above-mentioned function.
  • the cell array CA of the semiconductor device SDV4 in FIG. 17 can perform operations on the first layer of the convolutional neural network (CNN). Further, by configuring the semiconductor device SDV4 as a laminated structure as shown in FIG. 9D and providing a digital arithmetic circuit in the structure SIL, the arithmetic in the second and subsequent layers of the convolutional neural network can be performed, for example, by the digital arithmetic circuit. It can be done by using.
  • CNN convolutional neural network
  • the semiconductor device SDV4 of FIG. 17 is configured to acquire image data by a circuit PDA in which photodiodes PD are arranged in a matrix of m / h rows and h columns, and one aspect of the present invention is this. Not limited to.
  • one aspect of the present invention may be a configuration in which a plurality of semiconductor devices SDV4 are provided in a matrix so that the circuit PDA is on the upper surface.
  • an imaging region IMA is provided at the upper portion, and the imaging region IMA has a plurality of circuit PDAs.
  • the plurality of photodiode PDs included in the imaging region IMA are divided by the plurality of circuit PDAs.
  • the image data acquired in the entire imaging region IMA is divided and acquired by the plurality of circuit PDAs. ..
  • Each of the divided image data can be subjected to a product-sum calculation of the first data (weight coefficient, filter value, etc.) and the divided image data by each semiconductor device SDV4.
  • one aspect of the present invention is also a configuration in which the imaging region is divided into a plurality of regions and the product-sum operation is performed using the image data acquired in each region, as in the semiconductor device of FIG. good.
  • the semiconductor device SDV5 shown in FIG. 19 is a circuit configuration example to which the circuit MC and the circuit ISC of FIG. 15B are applied.
  • the semiconductor device SDV5 of FIG. 19 is different from the semiconductor device SDV4 of FIG. 17 in that a plurality of circuits MC can be provided in the cell array CA and that the semiconductor device SDV5 has a circuit XWC.
  • FIG. 20 shows an example of a circuit configuration including a peripheral circuit of the cell array CA of the semiconductor device SDV5 of FIG. That is, it is assumed that the cell array CA of the semiconductor device SDV5 of FIG. 19 has a circuit WDC, a circuit WWC, a circuit BDC, and a circuit ACTV in addition to the circuit XWC. Regarding the circuit WDC, the circuit WWC, the circuit BDC, and the circuit ACTV, the description of the circuit configuration of the semiconductor device SDV1 of FIG. 6A will be taken into consideration.
  • the circuit PDA and the circuit PEA are provided so as to be located above the cell array CA as shown in FIG. 19, but in FIG. 20, the circuit PDA and the circuit PEA are conveniently placed on the same plane of the cell array CA. It is shown in the figure.
  • circuit MCs [1,1] arranged in a matrix of m rows and n columns (where n is an integer of 1 or more).
  • circuit MC [m, n] To the circuit MC [m, n].
  • the circuits MC [1, j] to the circuits MC [m, j] located in the jth column of the cell array CA are electrically connected to the wiring XWL [j]. Is connected.
  • the circuits MC [1,1] to the circuits MC [m, 1] located in the first row of the cell array CA are electrically connected to the wiring XWL [1], and for example, the cell array.
  • the circuits MC [1, n] to the circuits MC [m, n] located in the nth row of the CA are electrically connected to the wiring XWL [n].
  • the wiring XWL [1] to the wiring XWL [n] are electrically connected to the circuit XWC.
  • the circuit XWC selects the circuit MC to which the second data is written when the second data is written to the circuit MC of the cell array CA in each of the wiring XWL [1] to the wiring XWL [m].
  • the circuit MC [1, j] to The circuit MC [m, j] can be selected.
  • the circuit MC and the circuit ISC shown in FIG. 15B can hold the voltage (V X ) corresponding to the current input as the second data, and the circuit MC and the circuit shown in FIG. 15A. It is different from ISC. Therefore, when each of the photodiode PD [1] to the photodiode PD [m] is irradiated with light and a current is generated in each of the photodiode PD [1] to the photodiode PD [m], the transistor M16 is used. By turning it on and selecting the circuit MC for each row of the cell array CA by the circuit XWC, the voltage corresponding to the current input as the second data can be written to the plurality of circuit MCs in each row. By the above-mentioned operation, the same second data is written in each of the plurality of circuits MC in each column of the cell array CA.
  • the semiconductor device SDV5 performs image processing in the same manner as the semiconductor device SDV4. Since the circuit MCs of the cell array CA of the semiconductor device SDV5 are arranged in n rows, n filters can be assigned to each column of the cell array CA of the semiconductor device SDV5. Further, one filter shall have m filter values. Therefore, m filter values can be held as the first data in each of the m circuits MC arranged in a row of the cell array CA.
  • the filter values included in the n filters in the circuit MC of the cell array CA can be obtained.
  • the product can be calculated for each filter.
  • the circuits MC [1,1] to the circuits MC [m, 1] arranged in the first row of the cell array CA hold m filter values included in the first filter, and the cell array CA
  • the m filter values included in the nth filter are held in the circuits MC [1, n] to the circuits MC [m, n] arranged in the nth column of the semiconductor device SDV5.
  • the product-sum calculation of the m filter values included in the first filter and the image data is performed, and the current corresponding to the calculation result is transferred to the circuit ADR [1]. Entered. Further, in the nth column of the cell array CA, a product-sum calculation is performed between the m filter values included in the nth filter and the image data, and the current corresponding to the calculation result is transmitted to the circuit ADR [n]. Entered. As a result, the image data input to the cell array CA is subjected to convolution processing by a plurality of filters, and the results are output from the circuit ACTV to the wiring ZL [1] to the wiring ZL [n].
  • the photodiode PD is formed by configuring the semiconductor device SDV4 of FIG. 17, the semiconductor device SDV5 of FIG. 19, and the like by using the circuit MC and the circuit ISC shown in FIGS. 15A, 15B, 16 and the like.
  • the acquired image data as the second data, it is possible to perform a product-sum operation with the first data (weight coefficient, filter value, etc.).
  • a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers.
  • the hierarchical neural network 100 shown in FIG. 21A shows an example thereof, and the neural network 100 has a first layer to an R layer (R here can be an integer of 4 or more). ing.
  • R can be an integer of 4 or more
  • the first layer corresponds to the input layer
  • the R layer corresponds to the output layer
  • the other layers correspond to the intermediate layer.
  • FIG. 21A illustrates the (k-1) th layer and the kth layer (here, k is an integer of 3 or more and R-1 or less) as the intermediate layer, and the other intermediate layers. Is not shown.
  • Each layer of the neural network 100 has one or more neurons.
  • the first layer has neurons N 1 (1) to neurons N p (1) (where p is an integer of 1 or more), and the layer (k-1) has neurons N 1 .
  • the kth layer is neuron N 1 (k) to neuron N n (k) (
  • n is an integer of 1 or more
  • the layer R has neurons N 1 (R) to neurons N q (R) (where q is an integer of 1 or more).
  • FIG. 21B shows the neuron N j (k) in the k-th layer, the signal input to the neuron N j ( k) , and the signal output from the neuron N j (k).
  • the degree of signal transmission is determined by the strength of synaptic connections (hereinafter referred to as weighting factors) that connect these neurons.
  • weighting factors the strength of synaptic connections that connect these neurons.
  • the signal output from the neurons in the previous layer is multiplied by the corresponding weighting factor and input to the neurons in the next layer.
  • i be an integer of 1 or more and m or less, and set the weight coefficient of the synapse between the neuron N i (k-1) in the (k-1) layer and the neuron N j (k) in the kth layer as wi ( k ).
  • j (k) When j (k) is set, the signal input to the neuron Nj (k) in the kth layer can be expressed by the equation (4.1).
  • the result of the sum of products may be biased as a bias.
  • the bias is b
  • the equation (4.2) can be rewritten as the following equation.
  • the neuron N j (k) produces an output signal z j (k ) in response to u j (k) .
  • the output signal z j ( k) from the neuron N j (k) is defined by the following equation.
  • the function f (u j (k) ) is an activation function in a hierarchical neural network, and a sigmoid function, a tanh function, a softmax function, a ReLU function (ramp function), a threshold function, and the like can be used. ..
  • the same function can be applied to all neurons, or different functions can be applied.
  • the same function can be applied for each layer, or different functions can be applied.
  • the signal output by the neurons in each layer, the weighting factor w, or the bias b can be an analog value or a digital value.
  • the digital value may be, for example, a value having two values or a value having a number of bits of three or more values. A value with a larger number of bits may be used.
  • an analog value for example, a linear ramp function, a sigmoid function, or the like may be used as the activation function.
  • binary digital values for example, a step function with an output of -1 or 1 or 0 or 1 may be used.
  • the signal output by the neurons in each layer can have three or more values, and in this case, the activation function has three values, for example, a step function having an output of -1, 0, or 1, or 0, 1, or.
  • a step function or the like set to 2 may be used.
  • a step function of -2, -1, 0, 1, or 2 may be used.
  • the neural network 100 By inputting an input signal to the first layer (input layer), the neural network 100 is sequentially input from the front layer in each layer from the first layer (input layer) to the last layer (output layer). Based on the signal, an output signal is generated using the equation (4.1), the equation (4.2) (or the equation (4.3)), and the equation (4.4), and the output signal is transferred to the next layer. Perform the operation to output to. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.
  • the weighting coefficients w s [k-1] (k-1) s [k] (k) (s [k-1] are An integer of 1 or more and m or less, and s [k] is an integer of 1 or more and n or less) is used as the first data, and the voltage corresponding to the first data is held in the first terminal of the capacitance C1 of the circuit MC.
  • the output signal z s [k-1] (k-1) from the neurons N s [k-1] (k-1) in the first layer (k-1) is used as the second data, and the current corresponding to the second data is used.
  • the sum of products of the first data and the second data can be obtained from the current amount YY flowing in the circuit ADR.
  • the value of the activation function is used as a signal to output the neurons N s [k] (k) in the k-th layer. It can be a signal z s [k] (k) .
  • the weighting coefficients w s [R-1] (R-1) s [R] (R) (s [R-1]. ] Is an integer of 1 or more, and s [R] is an integer of 1 or more and q or less) as the first data, and the voltage corresponding to the first data is held in the first terminal of the capacitance C1 of the circuit MC.
  • the output signal z s [R-1] (R-1) from the neurons N s [R-1] (R-1) in the first layer (R-1) is used as the second data, and the current corresponding to the second data is used.
  • the sum of products of the first data and the second data can be obtained from the current amount YY flowing in the circuit ADR.
  • the value of the activation function is used as a signal to output the neurons N s [R] (R) in the R layer.
  • the signal z s [R] (R) can be used.
  • the input layer described in the present embodiment may function as a buffer circuit that outputs an input signal to the second layer.
  • the weighting coefficient w s [k-1] (k-1) s [k] (k) is used as the first data.
  • the voltage corresponding to the first data is stored in the circuit MC [1,1] to the circuit MC [m, n] from the neurons N s [k-1] (k- 1) in the layer (k-1).
  • the output signal z s [k-1] (k-1) of the above is used as the second data, and the voltage corresponding to the second data is input from the circuit XDC to the wiring XDL [1] to the wiring XDL [m].
  • the value of the activation function according to the sum of products of the first data and the second data can be calculated from the current amount IS [j] input to the circuit ADR. That is, the value can be used as a signal to be the output signal z s [k] (k) of the neurons N s [k] (k) in the k-th layer. Further, for example, when the circuit ADR is configured to output a voltage corresponding to the value, the neurons N s [k] (k) of the k-th layer are input to a plurality of neurons of the (k + 1) layer.
  • the output signal z s [k] (k) can be the voltage.
  • the output signal z s [k] (k) can be the voltage output from the circuit ADR of the semiconductor device SDV1 in the hidden layer of the k-th layer without being generated by the circuit XDC.
  • the semiconductor device of FIG. 22 includes a semiconductor device SDV1-1 having the same configuration as the semiconductor device SDV1 of FIG. 6A, and a semiconductor device SDV1-2 having a configuration in which the circuit XDC is not provided in the semiconductor device SDV1 of FIG. 6A.
  • the cell array CA of the semiconductor device SDV1-1 has circuits MC [1,1] to circuits MC [m, n].
  • the cell array CA of the semiconductor device SDV1-2 has circuits MC [1,1] to circuits MC [n, t] (t is an integer of 1 or more).
  • each of the wiring ZL [1] to the wiring ZL [n] of the semiconductor device SDV1-1 is electrically connected to the wiring XDL [1] to the wiring XDL [n] of the semiconductor device SDV1-2.
  • the circuit MC [1,1] to the circuit MC [1] uses the weighting coefficient between the neurons of the layer (k-1) and the neurons of the kth layer as the first data. It is held in m, n], and the output signal z s [k-1] ( k-1) from the neurons N s [k-1] (k-1) in the (k-1) layer is used as the second data.
  • the output signal z s [k-1] ( k-1) from the neurons N s [k-1] (k-1) in the (k-1) layer is used as the second data.
  • the output signals z 1 (k) to z n (k) of (k ) to the neuron N n (k) can be output.
  • the respective values of the output signals z 1 (k) to z n (k) can be expressed as the voltage output from the circuit ADR.
  • the circuit MC [1,1] to the circuit MC [n] uses the weighting coefficient between the neurons of the kth layer and the neurons of the (k + 1) layer as the first data. , T] and the voltage input to the wiring XDL [1] to the wiring XDL [n], that is, the output signal z 1 (k) of the neurons N 1 (k) to the neurons N n (k) in the k-th layer.
  • the wiring ZL [s [k + 1]] here, s [k + 1] is an integer of 1 or more and t or less
  • the output signal z s [k + 1] ( k + 1 ) of s [k + 1] (k + 1) can be output.
  • the value (voltage) of the output signal of the neuron output by the semiconductor apparatus SDV1-1 is directly transferred to the semiconductor apparatus SDV1-2. Since it can be input, the operation of the hierarchical neural network can be continuously performed from the first layer as an example. Further, since it is not necessary to temporarily store the output signal output from the wiring ZL [1] to the wiring ZL [n] of the semiconductor device SDV1-1 by an external circuit or the like, a storage device required for temporary storage is separately provided. It does not have to be provided. That is, by configuring the semiconductor device of FIG. 22, the circuit area can be reduced, and the power required for data transmission for temporary storage can be reduced.
  • FIG. 23 is, as an example, the semiconductor device described in the above embodiment, in which the semiconductor device includes a transistor 300, a transistor 500, and a capacitive element 600. Further, FIG. 24A shows a cross-sectional view of the transistor 500 in the channel length direction, FIG. 24B shows a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 24C shows a cross-sectional view of the transistor 300 in the channel width direction. There is.
  • the transistor 500 is a transistor (OS transistor) having a metal oxide in the channel forming region.
  • the transistor 500 has a characteristic that the off-current is small and the field effect mobility does not easily change even at a high temperature.
  • a transistor included in a semiconductor device for example, the semiconductor device SDV1, the semiconductor device SDV2, the semiconductor device SDV3, the semiconductor device SDV4, the semiconductor device SDV5, etc. described in the above embodiment, the operation capability even at a high temperature is possible. It is possible to realize a semiconductor device that does not easily decrease.
  • the transistor 500 to, for example, the transistor M3 by utilizing the characteristic that the off-current is small, the potential written to the first terminal of the capacitance C1 of the circuit MC can be held for a long time.
  • the transistor 500 is provided above the transistor 300, for example, and the capacitive element 600 is provided above the transistor 300 and the transistor 500, for example.
  • the capacitive element 600 may be a capacitance included in the semiconductor device SDV1, the semiconductor device SDV2, the semiconductor device SDV3, the semiconductor device SDV4, the semiconductor device SDV5, or the like described in the above embodiment. Depending on the circuit configuration, the capacitive element 600 shown in FIG. 23 may not necessarily be provided.
  • the transistor 300 is provided on the substrate 310, and has an element separation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 310, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314a. It has a resistance region 314b.
  • the transistor 300 can be applied to, for example, a transistor included in the semiconductor device SDV1, the semiconductor device SDV2, the semiconductor device SDV3, the semiconductor device SDV4, the semiconductor device SDV5, etc. described in the above embodiment. Specifically, for example, it may be a transistor included in an inverter circuit, a NAND circuit, or the like included in the circuit ACF shown in FIGS. 8A and 8B.
  • FIG. 23 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 via a pair of electrodes of the capacitive element 600.
  • the semiconductor device SDV3 the semiconductor device SDV4, the semiconductor device SDV5, etc.
  • one of the source or drain of the transistor 300 is one of the source or drain of the transistor 500 via the pair of electrodes of the capacitive element 600.
  • One of the source or drain of the transistor 300 is electrically connected to the gate of the transistor 500 via a pair of electrodes of the capacitive element 600.
  • each terminal of the transistor 300 can be configured not to be electrically connected to each terminal of the transistor 500 and each terminal of the capacitive element 600.
  • a semiconductor substrate for example, a single crystal substrate or a silicon substrate
  • the substrate 310 it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 310.
  • the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315.
  • the on characteristic of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • It preferably contains crystalline silicon.
  • it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.
  • n-type conductivity such as arsenic and phosphorus, or p-type conductivity such as boron are imparted.
  • the conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the element separation layer 312 is provided to separate a plurality of transistors formed on the substrate 310.
  • the element separation layer can be formed by using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa separation method, or the like.
  • LOCOS Local Oxidation of Silicon
  • STI Shallow Trench Isolation
  • the transistor 300 shown in FIG. 23 is an example, and the transistor 300 is not limited to its structure, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like.
  • the transistor 300 may have a planar type structure instead of the FIN type shown in FIG. 24C.
  • the transistor 300 may be configured in the same manner as the transistor 500 using an oxide semiconductor, as shown in FIG. 25. The details of the transistor 500 will be described later.
  • the unipolar circuit means a circuit including a transistor having only one polarity of an n-channel transistor or a p-channel transistor.
  • the transistor 300 is provided on the substrate 310A.
  • a semiconductor substrate may be used in the same manner as the substrate 310 of the semiconductor device of FIG. 23.
  • the substrate 310A includes, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel still foil, a tungsten substrate, and a tungsten foil.
  • a substrate, a flexible substrate, a laminated film, a paper containing a fibrous material, a base film, or the like can be used.
  • glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass.
  • flexible substrates, laminated films, base films, etc. include the following.
  • plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyether sulfone
  • PTFE polytetrafluoroethylene
  • synthetic resin such as acrylic.
  • polypropylene polyester, polyvinyl fluoride, polyvinyl chloride and the like.
  • polyamide, polyimide, aramid epoxy resin, inorganic thin-film film, papers and the like.
  • the transistor 300 shown in FIG. 23 is provided with an insulator 320, an insulator 322, an insulator 324, and an insulator 326 stacked in this order from the substrate 310 side.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.
  • silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition refers to a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen
  • aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.
  • the insulator 322 may have a function as a flattening film for flattening a step generated by the insulator 320 and the transistor 300 covered with the insulator 322.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property so that hydrogen, impurities, etc. do not diffuse in the region where the transistor 500 is provided from the substrate 310, the transistor 300, or the like.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by the CVD method can be used.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS).
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is such that the amount desorbed in terms of hydrogen atoms is converted per area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C. to 500 ° C. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 has a lower dielectric constant than the insulator 324.
  • the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitive element 600, a conductor 328 connected to the transistor 500, a conductor 330, and the like.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • a plurality of structures may be collectively given the same reference numeral.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are provided in order above the insulator 326 and the conductor 330.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 350 it is preferable to use an insulator having a barrier property against impurities such as hydrogen and water, similarly to the insulator 324.
  • the insulator 352 and the insulator 354 it is preferable to use an insulator having a relatively low relative permittivity in order to reduce the parasitic capacitance generated between the wirings, similarly to the insulator 326.
  • the conductor 356 preferably contains a conductor having a barrier property against impurities such as hydrogen and water.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in order on the insulator 354 and the conductor 356.
  • the insulator 360 it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324 and the like. Therefore, as the insulator 360, for example, a material applicable to the insulator 324 or the like can be used.
  • the insulator 362 and the insulator 364 have a function as an interlayer insulating film and a flattening film. Further, as the insulator 362 and the insulator 364, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324. Therefore, as the insulator 362 and / or the insulator 364, a material applicable to the insulator 324 can be used.
  • an opening is formed in a region of each of the insulator 360, the insulator 362, and the insulator 364 that overlaps with a part of the conductor 356, and the conductor 366 is provided so as to fill the opening.
  • the conductor 366 is also formed on the insulator 362.
  • the conductor 366 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are laminated in this order on the insulator 364 and the conductor 366.
  • any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 it is preferable to use a substance having a barrier property against oxygen and hydrogen.
  • the insulator 510 and the insulator 514 have a barrier property such that hydrogen and impurities do not diffuse from the region where the substrate 310 or the transistor 300 is provided to the region where the transistor 500 is provided. It is preferable to use. Therefore, the same material as the insulator 324 can be used.
  • Silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 512 and the insulator 516.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 include a conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 24A and 24B) and the like. It is embedded.
  • the conductor 518 has a function as a plug or wiring for connecting to the capacitive element 600 or the transistor 300.
  • the conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 has an insulator 516 on the insulator 514 and a conductor 503 (conductor 503a, and conductivity) arranged to be embedded in the insulator 514 or the insulator 516.
  • Body 503b insulator 522 on insulator 516, and insulator 503, insulator 524 on insulator 522, oxide 530a on insulator 524, and oxide 530b on oxide 530a.
  • the insulator 552 includes the upper surface of the insulator 522, the side surface of the insulator 524, the side surface of the oxide 530a, the side surface and the upper surface of the oxide 530b, and the side surface of the conductor 542.
  • the upper surface of the conductor 560 is arranged so as to substantially coincide in height with the upper part of the insulator 554, the upper part of the insulator 550, the upper part of the insulator 552, and the upper surface of the insulator 580.
  • the insulator 574 is in contact with at least a part of the upper surface of the conductor 560, the upper part of the insulator 552, the upper part of the insulator 550, the upper part of the insulator 554, and the upper surface of the insulator 580.
  • the insulator 580 and the insulator 544 are provided with an opening reaching the oxide 530b.
  • Insulator 552, insulator 550, insulator 554, and conductor 560 are arranged in the opening. Further, in the channel length direction of the transistor 500, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are placed between the insulator 571a and the conductor 542a and the insulator 571b and the conductor 542b. It is provided.
  • the insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.
  • the oxide 530 preferably has an oxide 530a arranged on the insulator 524 and an oxide 530b arranged on the oxide 530a.
  • the oxide 530a By having the oxide 530a under the oxide 530b, it is possible to suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b.
  • the transistor 500 shows a configuration in which the oxide 530 is laminated with two layers of the oxide 530a and the oxide 530b
  • the present invention is not limited to this.
  • the transistor 500 can be configured to have a single layer of oxide 530b or a laminated structure of three or more layers.
  • each of the oxide 530a and the oxide 530b may have a laminated structure.
  • the conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode.
  • the insulator 552, the insulator 550, and the insulator 554 function as the first gate insulator, and the insulator 522 and the insulator 524 function as the second gate insulator.
  • the gate insulator may be referred to as a gate insulating layer or a gate insulating film.
  • the conductor 542a functions as one of the source or the drain, and the conductor 542b functions as the other of the source or the drain. Further, at least a part of the region overlapping with the conductor 560 of the oxide 530 functions as a channel forming region.
  • FIG. 26A an enlarged view of the vicinity of the channel formation region in FIG. 24A is shown in FIG. 26A.
  • the oxide 530b is provided with a region 530 bc that functions as a channel forming region of the transistor 500, and a region 530 ba and a region 530 bb that are provided so as to sandwich the region 530 bc and function as a source region or a drain region.
  • Have At least a part of the region 530bc overlaps with the conductor 560.
  • the region 530bc is provided in the region between the conductor 542a and the conductor 542b.
  • the region 530ba is provided so as to be superimposed on the conductor 542a
  • the region 530bb is provided so as to be superimposed on the conductor 542b.
  • the region 530bc that functions as a channel forming region has more oxygen deficiency than the regions 530ba and 530bb (in the present specification and the like, the oxygen deficiency in the metal oxide may be referred to as VO (oxygen vacancy)). It is a high resistance region with a low carrier concentration because it is low or the impurity concentration is low. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.
  • Transistors using metal oxides are likely to fluctuate in electrical characteristics and may be unreliable if impurities or oxygen deficiencies (VOs) are present in the regions where channels are formed in the metal oxides. Further, hydrogen in the vicinity of the oxygen deficiency (VO) forms a defect in which hydrogen is contained in the oxygen deficiency (VO) (hereinafter, may be referred to as VOH ) to generate electrons as carriers. In some cases. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics). Therefore, it is preferable that impurities, oxygen deficiency, and VOH are reduced as much as possible in the region where channels are formed in the oxide semiconductor.
  • the region 530ba and the region 530bab that function as a source region or a drain region have a large amount of oxygen deficiency (VO) or a high concentration of impurities such as hydrogen, nitrogen, and metal elements, so that the carrier concentration increases and the resistance is low. It is an area that has become. That is, the region 530ba and the region 530bb are n-type regions having a high carrier concentration and low resistance as compared with the region 530bc.
  • VO oxygen deficiency
  • impurities such as hydrogen, nitrogen, and metal elements
  • the carrier concentration of the region 530 bc that functions as a channel forming region is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3 , and 1 ⁇ 10 16 cm. It is more preferably less than -3 , still more preferably less than 1 ⁇ 10 13 cm -3 , and even more preferably less than 1 ⁇ 10 12 cm -3 .
  • the lower limit of the carrier concentration of the region 530 bc that functions as the channel forming region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
  • the carrier concentration between the region 530 bc and the region 530 ba or the region 530 bb is equal to or lower than the carrier concentration of the region 530 ba and the region 530 bb, and equal to or higher than the carrier concentration of the region 530 bc.
  • Regions may be formed. That is, the region functions as a junction region between the region 530 bc and the region 530 ba or the region 530 bb.
  • the hydrogen concentration may be equal to or lower than the hydrogen concentration in the regions 530ba and 530bb, and may be equal to or higher than the hydrogen concentration in the region 530bc.
  • the junction region may have an oxygen deficiency equal to or less than that of the regions 530ba and 530bb, and may be equal to or greater than that of the region 530bc.
  • FIG. 26A shows an example in which the region 530ba, the region 530bb, and the region 530bc are formed on the oxide 530b, but the present invention is not limited thereto.
  • each of the above regions may be formed not only with the oxide 530b but also with the oxide 530a.
  • the concentrations of the metal elements detected in each region and the impurity elements such as hydrogen and nitrogen are not limited to the stepwise changes in each region, but may be continuously changed in each region. That is, the closer the region is to the channel formation region, the lower the concentration of the metal element and the impurity elements such as hydrogen and nitrogen is sufficient.
  • a metal oxide hereinafter, also referred to as an oxide semiconductor that functions as a semiconductor for the oxide 530 (oxide 530a and oxide 530b) containing a channel forming region.
  • the metal oxide that functions as a semiconductor it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • an In-M-Zn oxide having indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium).
  • Zinc, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used.
  • an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used as the oxide 530.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 530b is larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the oxide 530a under the oxide 530b By arranging the oxide 530a under the oxide 530b in this way, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a to the oxide 530b. ..
  • the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Since the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered, the influence of the interfacial scattering on the carrier conduction is small, and a high on-current can be obtained.
  • the oxide 530b preferably has crystallinity.
  • CAAC-OS c-axis aligned crystalline semiconductor semiconductor
  • CAAC-OS is a metal oxide having a highly crystalline and dense structure and having few impurities and defects (for example, oxygen deficiency (VO, etc.).
  • the metal By heat-treating at a temperature at which the oxide does not polycrystallize (for example, 400 ° C. or higher and 600 ° C. or lower), CAAC-OS can be made into a more crystalline and dense structure.
  • a temperature at which the oxide does not polycrystallize for example, 400 ° C. or higher and 600 ° C. or lower
  • CAAC-OS By increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.
  • the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
  • a transistor using an oxide semiconductor if impurities and oxygen deficiencies are present in the region where a channel is formed in the oxide semiconductor, the electrical characteristics are liable to fluctuate and the reliability may be deteriorated. Further, hydrogen in the vicinity of the oxygen deficiency may form a defect in which hydrogen is contained in the oxygen deficiency (hereinafter, may be referred to as VOH) to generate an electron as a carrier. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics).
  • the region in which the channel is formed in the oxide semiconductor is preferably i-type (intrinsic) or substantially i-type with a reduced carrier concentration.
  • excess oxygen an insulator containing oxygen desorbed by heating
  • the oxide semiconductor is removed from the insulator.
  • the on-current of the transistor 500 may decrease or the field effect mobility may decrease.
  • the oxygen supplied to the source region or the drain region varies in the surface of the substrate, so that the characteristics of the semiconductor device having the transistor vary.
  • the region 530bc that functions as a channel forming region is preferably i-type or substantially i-type because the carrier concentration is reduced, but the region 530ba that functions as a source region or a drain region and
  • the region 530bb has a high carrier concentration and is preferably n-type. That is, it is preferable to reduce oxygen deficiency and VOH in the region 530 bc of the oxide semiconductor so that an excessive amount of oxygen is not supplied to the region 530 ba and the region 530 bb.
  • microwave treatment is performed in an atmosphere containing oxygen to reduce oxygen deficiency and VOH in the region 530bc .
  • the microwave processing refers to processing using, for example, a device having a power source for generating high-density plasma using microwaves.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma by using a high frequency such as microwave or RF, and the oxygen plasma can be allowed to act. At this time, it is also possible to irradiate the region 530bc with a high frequency such as microwave or RF.
  • a high frequency such as microwave or RF.
  • the VO H in the region 530 bc can be divided, the hydrogen H can be removed from the region 530 bc, and the oxygen -deficient VO can be supplemented with oxygen. That is, in the region 530 bc, the reaction “VO H ⁇ H + VO” occurs, and the hydrogen concentration in the region 530 bc can be reduced. Therefore, oxygen deficiency and VOH in the region 530bc can be reduced, and the carrier concentration can be lowered.
  • the action of microwaves, high frequencies such as RF, oxygen plasma, etc. is shielded by the conductors 542a and 542b and does not reach the regions 530ba and 530bb. .. Further, the action of the oxygen plasma can be reduced by the insulator 571 and the insulator 580 provided overlying the oxide 530b and the conductor 542. As a result, during microwave treatment, the reduction of VOH and the supply of an excessive amount of oxygen do not occur in the regions 530ba and 530bab , so that the reduction of the carrier concentration can be prevented.
  • microwave treatment in an atmosphere containing oxygen after the film formation of the insulating film to be the insulator 552 or the film formation of the insulating film to be the insulator 550.
  • microwave treatment in an atmosphere containing oxygen through the insulator 552 or the insulator 550 in this way, oxygen can be efficiently injected into the region 530 bc.
  • the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, the injection of more oxygen than necessary into the region 530bc is suppressed, and the oxidation of the side surface of the conductor 542 is suppressed. be able to. Further, it is possible to suppress the oxidation of the side surface of the conductor 542 when the insulating film to be the insulator 550 is formed.
  • the oxygen injected into the region 530bc has various forms such as an oxygen atom, an oxygen molecule, and an oxygen radical (also called an O radical, an atom or molecule having an unpaired electron, or an ion).
  • the oxygen injected into the region 530bc is preferably one or more of the above-mentioned forms, and is particularly preferable to be an oxygen radical. Further, since the film quality of the insulator 552 and the insulator 550 can be improved, the reliability of the transistor 500 is improved.
  • oxygen deficiency and VOH can be selectively removed in the region 530bc of the oxide semiconductor to make the region 530bc i-type or substantially i-type. Further, it is possible to suppress the supply of excess oxygen to the region 530ba and the region 530bb that function as the source region or the drain region, and maintain the n-type. As a result, it is possible to suppress fluctuations in the electrical characteristics of the transistor 500 and reduce variations in the electrical characteristics of the transistor 500 within the substrate surface.
  • a curved surface may be provided between the side surface of the oxide 530b and the upper surface of the oxide 530b in a cross-sectional view of the transistor 500 in the channel width direction. That is, the end portion of the side surface and the end portion of the upper surface may be curved (hereinafter, also referred to as a round shape).
  • the radius of curvature on the curved surface is preferably larger than 0 nm, smaller than the film thickness of the oxide 530b in the region overlapping the conductor 542, or smaller than half the length of the region having no curved surface.
  • the radius of curvature on the curved surface is larger than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less.
  • the oxide 530 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions.
  • the atomic number ratio of the element M to the metal element as the main component is the ratio of the element M to the metal element as the main component in the metal oxide used for the oxide 530b. It is preferably larger than the atomic number ratio.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the oxide 530b is preferably an oxide having crystallinity such as CAAC-OS.
  • Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 530b by the source electrode or the drain electrode. As a result, oxygen can be reduced from being extracted from the oxide 530b even if heat treatment is performed, so that the transistor 500 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
  • the lower end of the conduction band changes gently.
  • the lower end of the conduction band at the junction between the oxide 530a and the oxide 530b is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.
  • the oxide 530a and the oxide 530b have a common element other than oxygen as a main component, so that a mixed layer having a low defect level density can be formed.
  • the oxide 530b is an In-M-Zn oxide
  • the oxide 530a is an In-M-Zn oxide, an M-Zn oxide, an element M oxide, an In-Zn oxide, or an indium oxide. Etc. may be used.
  • a metal oxide having a composition in the vicinity thereof may be used.
  • a metal oxide having a composition may be used.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic number ratio. Further, it is preferable to use gallium as the element M.
  • the above-mentioned atomic number ratio is not limited to the atomic number ratio of the formed metal oxide, but is the atomic number ratio of the sputtering target used for forming the metal oxide. May be.
  • the interface between the oxide 530 and the insulator 552 and its vicinity thereof can be provided.
  • Indium contained in the oxide 530 may be unevenly distributed.
  • the vicinity of the surface of the oxide 530 has an atomic number ratio close to that of the indium oxide or an atomic number ratio close to that of the In—Zn oxide.
  • the atomic number ratio of indium in the vicinity of the surface of the oxide 530, particularly the oxide 530b, is increased, so that the field effect mobility of the transistor 500 can be improved.
  • the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a large on-current and high frequency characteristics.
  • At least one of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 has impurities such as water and hydrogen from the substrate side or the transistor 500. It is preferable to function as a barrier insulating film that suppresses diffusion from above to the transistor 500.
  • insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, It is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as nitrogen oxide molecules ( N2O, NO, NO2, etc.) and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule) (the above-mentioned oxygen is difficult to permeate).
  • the barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property is a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability).
  • the corresponding substance has the function of capturing and fixing (also referred to as gettering).
  • the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 are insulators having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.
  • impurities such as water and hydrogen, and oxygen.
  • silicon nitride it is preferable to use silicon nitride having a higher hydrogen barrier property.
  • the insulator 514, the insulator 571, the insulator 574, and the insulator 581 it is preferable to use aluminum oxide or magnesium oxide having a high function of capturing hydrogen and fixing hydrogen. This makes it possible to prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 500 side via the insulator 512 and the insulator 514. Alternatively, it is possible to prevent impurities such as water and hydrogen from diffusing to the transistor 500 side from the interlayer insulating film or the like arranged outside the insulator 581. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 524 or the like to the substrate side via the insulator 512 and the insulator 514.
  • the transistor 500 has an insulator 512, an insulator 514, an insulator 571, an insulator 544, an insulator 574, an insulator 576, and an insulator 512 having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. It is preferable to have a structure surrounded by an insulator 581.
  • an oxide having an amorphous structure as the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581.
  • a metal oxide such as AlO x (x is an arbitrary number larger than 0) or MgO y (y is an arbitrary number larger than 0).
  • an oxygen atom has a dangling bond, and the dangling bond may have a property of capturing or fixing hydrogen.
  • a metal oxide having such an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen existing around the transistor 500 is captured or fixed. be able to. In particular, it is preferable to capture or fix hydrogen contained in the channel forming region of the transistor 500.
  • a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, it is possible to manufacture the transistor 500 having good characteristics and high reliability, and a semiconductor device.
  • the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 preferably have an amorphous structure, but a region of a polycrystal structure is partially formed. It may be formed. Further, the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 are multi-layered in which a layer having an amorphous structure and a layer having a polycrystalline structure are laminated. It may be a structure. For example, a laminated structure in which a layer having a polycrystalline structure is formed on a layer having an amorphous structure may be used.
  • the film formation of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 may be performed by using, for example, a sputtering method. Since the sputtering method does not require the use of molecules containing hydrogen in the film forming gas, the hydrogen concentrations of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581. Can be reduced.
  • the film forming method is not limited to the sputtering method, but is limited to a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, and a pulsed laser deposition (PLD) method.
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • atomic layer deposition ALD: Atomic Layer Deposition
  • the resistivity of the insulator 512, the insulator 544, and the insulator 576 it may be preferable to reduce the resistivity of the insulator 512, the insulator 544, and the insulator 576.
  • the resistivity of the insulator 512, the insulator 544, and the insulator 576 is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 516, the insulator 574, the insulator 580, and the insulator 581 have a lower dielectric constant than the insulator 514.
  • the insulator 516, the insulator 580, and the insulator 581 include silicon oxide, silicon oxide nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and holes. Silicon oxide or the like may be used as appropriate.
  • the insulator 581 is preferably an insulator that functions as an interlayer film, a flattening film, or the like.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560.
  • the conductor 503 is embedded in the opening formed in the insulator 516.
  • a part of the conductor 503 may be embedded in the insulator 514.
  • the conductor 503 has a conductor 503a and a conductor 503b.
  • the conductor 503a is provided in contact with the bottom surface and the side wall of the opening.
  • the conductor 503b is provided so as to be embedded in the recess formed in the conductor 503a.
  • the height of the upper part of the conductor 503b roughly coincides with the height of the upper part of the conductor 503a and the height of the upper part of the insulator 516.
  • the conductor 503a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a conductive material having. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule).
  • the conductor 503a By using a conductive material having a function of reducing the diffusion of hydrogen in the conductor 503a, impurities such as hydrogen contained in the conductor 503b can be prevented from diffusing into the oxide 530 via the insulator 524 or the like. Can be prevented. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the conductor 503a, the above-mentioned conductive material may be a single layer or a laminated material. For example, titanium nitride may be used for the conductor 503a.
  • the conductor 503b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • tungsten may be used for the conductor 503b.
  • the conductor 503 may function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 500 can be controlled by independently changing the potential applied to the conductor 503 without interlocking with the potential applied to the conductor 560.
  • Vth threshold voltage
  • the electrical resistivity of the conductor 503 is designed in consideration of the potential applied to the above-mentioned conductor 503, and the film thickness of the conductor 503 is set according to the electrical resistivity.
  • the film thickness of the insulator 516 is substantially the same as that of the conductor 503.
  • the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, so that the impurities can be reduced from diffusing into the oxide 530. ..
  • the conductor 503 is provided larger than the size of the region that does not overlap with the conductor 542a and the conductor 542b of the oxide 530 when viewed from the upper surface.
  • the conductor 503 is also stretched in a region outside the ends of the oxides 530a and 530b in the channel width direction. That is, it is preferable that the conductor 503 and the conductor 560 are superimposed on each other via the insulator on the outside of the side surface of the oxide 530 in the channel width direction.
  • the channel forming region of the oxide 530 is electrically surrounded by the electric field of the conductor 560 that functions as the first gate electrode and the electric field of the conductor 503 that functions as the second gate electrode. Can be done.
  • the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate and the second gate is called a curved channel (S-channel) structure.
  • the transistor having an S-channel structure represents the structure of a transistor that electrically surrounds the channel formation region by the electric fields of one and the other of the pair of gate electrodes.
  • the S-channel structure disclosed in the present specification and the like is different from the Fin type structure and the planar type structure.
  • the conductor 503 is stretched to function as wiring.
  • the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 503. Further, it is not always necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by a plurality of transistors.
  • the conductor 503 shows a configuration in which the conductor 503a and the conductor 503b are laminated, but the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • the insulator 522 and the insulator 524 function as a gate insulator.
  • the insulator 522 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.
  • the insulator 522 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 releases oxygen from the oxide 530 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 500 to the oxide 530. It functions as a suppressing layer.
  • the insulator 522 impurities such as hydrogen can be suppressed from diffusing into the inside of the transistor 500, and the generation of oxygen deficiency in the oxide 530 can be suppressed. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 and the oxide 530.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • the insulator 522 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
  • an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide may be used in a single layer or in a laminated state.
  • a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide
  • problems such as leakage current may occur due to the thinning of the gate insulator.
  • a high-k material for an insulator that functions as a gate insulator it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • insulator 522 a substance having a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr) TiO 3 (BST) may be used.
  • PZT lead zirconate titanate
  • strontium titanate SrTiO 3
  • Ba, Sr Ba TiO 3
  • silicon oxide, silicon nitride nitride, or the like may be appropriately used.
  • the heat treatment in a state where the surface of the oxide 530 is exposed.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 600 ° C. or lower, more preferably 350 ° C. or higher and 550 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more, and then continuously heat-treated in an atmosphere of nitrogen gas or an inert gas.
  • the oxygen deficiency in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "VO + O ⁇ null" can be promoted. .. Further, the oxygen supplied to the hydrogen remaining in the oxide 530 reacts with the hydrogen, so that the hydrogen can be removed (dehydrated) as H2O . As a result, it is possible to suppress the hydrogen remaining in the oxide 530 from recombination with the oxygen deficiency to form VOH.
  • the insulator 522 and the insulator 524 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the insulator 524 may be formed in an island shape by superimposing on the oxide 530a. In this case, the insulator 544 is in contact with the side surface of the insulator 524 and the upper surface of the insulator 522.
  • the conductor 542a and the conductor 542b are provided in contact with the upper surface of the oxide 530b.
  • the conductor 542a and the conductor 542b each function as a source electrode or a drain electrode of the transistor 500.
  • Examples of the conductor 542 include a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, and the like. It is preferable to use a nitride containing titanium and aluminum. In one aspect of the invention, a nitride containing tantalum is particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
  • hydrogen contained in the oxide 530b or the like may diffuse into the conductor 542a or the conductor 542b.
  • hydrogen contained in the oxide 530b or the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen is the conductor. It may bind to the nitrogen contained in the 542a or the conductor 542b. That is, hydrogen contained in the oxide 530b or the like may be absorbed by the conductor 542a or the conductor 542b.
  • the conductor 542 it is preferable that no curved surface is formed between the side surface of the conductor 542 and the upper surface of the conductor 542.
  • the conductor 542 on which the curved surface is not formed the cross-sectional area of the conductor 542 in the cross section in the channel width direction can be increased.
  • the conductivity of the conductor 542 can be increased and the on-current of the transistor 500 can be increased.
  • the insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b.
  • the insulator 571 preferably functions as a barrier insulating film against at least oxygen. Therefore, it is preferable that the insulator 571 has a function of suppressing the diffusion of oxygen.
  • the insulator 571 preferably has a function of suppressing the diffusion of oxygen more than the insulator 580.
  • a nitride containing silicon such as silicon nitride may be used.
  • the insulator 571 preferably has a function of capturing impurities such as hydrogen.
  • a metal oxide having an amorphous structure for example, an insulator such as aluminum oxide or magnesium oxide may be used.
  • an insulator such as aluminum oxide or magnesium oxide
  • the insulator 544 is provided so as to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. It is preferable that the insulator 544 has a function of capturing hydrogen and fixing hydrogen. In that case, the insulator 544 preferably contains an insulator such as silicon nitride or a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide. Further, for example, as the insulator 544, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used.
  • the conductor 542 can be wrapped with the insulator having a barrier property against oxygen. That is, it is possible to prevent oxygen contained in the insulator 524 and the insulator 580 from diffusing into the conductor 542. As a result, the conductor 542 is directly oxidized by the oxygen contained in the insulator 524 and the insulator 580 to increase the resistivity and suppress the decrease in the on-current.
  • the insulator 552 functions as a part of the gate insulator.
  • an insulator that can be used for the above-mentioned insulator 574 may be used.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be used.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate) and the like can be used.
  • aluminum oxide is used as the insulator 552.
  • the insulator 552 is an insulator having at least oxygen and aluminum.
  • the insulator 552 is provided in contact with the upper surface and the side surface of the oxide 530b, the side surface of the oxide 530a, the side surface of the insulator 524, and the upper surface of the insulator 522. That is, the region of the oxide 530a, the oxide 530b, and the insulator 524 overlapping with the conductor 560 is covered with the insulator 552 in the cross section in the channel width direction. As a result, it is possible to block the desorption of oxygen by the oxides 530a and 530b by the insulator 552 having a barrier property against oxygen when heat treatment or the like is performed.
  • the insulator 580 and the insulator 550 contain an excessive amount of oxygen, it is possible to suppress the excessive supply of the oxygen to the oxide 530a and the oxide 530b. Therefore, it is possible to prevent the region 530ba and the region 530bb from being excessively oxidized via the region 530bc to cause a decrease in the on-current of the transistor 500 or a decrease in the field effect mobility.
  • the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580, respectively. Therefore, it is possible to reduce the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. As a result, it is possible to suppress a decrease in the on-current of the transistor 500 or a decrease in the field effect mobility.
  • the insulator 552 needs to be provided in the opening formed in the insulator 580 or the like together with the insulator 554, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, it is preferable that the thickness of the insulator 552 is thin.
  • the film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. ..
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 552 may have a region having the above-mentioned film thickness at least in a part thereof. Further, the film thickness of the insulator 552 is preferably thinner than the film thickness of the insulator 550. In this case, the insulator 552 may have a region having a film thickness thinner than that of the insulator 550, at least in part.
  • the insulator 552 In order to form the insulator 552 with a thin film thickness as described above, it is preferable to form the insulator by using the ALD method.
  • the ALD method include a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, and a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor.
  • a thermal ALD Thermal ALD
  • PEALD Laser ALD
  • the ALD method utilizes the characteristics of atoms, which are self-regulating properties, and can deposit atoms layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, pinholes, etc. It has the effects of being able to form a film with few defects, being able to form a film with excellent coverage, and being able to form a film at a low temperature. Therefore, the insulator 552 can be formed on the side surface of the opening formed in the insulator 580 or the like with good coverage and with a thin film thickness as described above.
  • the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
  • the quantification of impurities can be performed by using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the insulator 550 functions as a part of the gate insulator.
  • the insulator 550 is preferably arranged in contact with the upper surface of the insulator 552.
  • the insulator 550 includes silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, and the like. Can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are heat-stable.
  • the insulator 550 is an insulator having at least oxygen and silicon.
  • the insulator 550 has a reduced concentration of impurities such as water and hydrogen in the insulator 550.
  • the film thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15.0 nm or less, or 20 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 550 may have a region having the above-mentioned film thickness at least in a part thereof.
  • FIGS. 24A and 24B show a configuration in which the insulator 550 is a single layer
  • the present invention is not limited to this, and a laminated structure of two or more layers may be used.
  • the insulator 550 may have a two-layer laminated structure of the insulator 550a and the insulator 550b on the insulator 550a.
  • the lower insulator 550a is formed by using an insulator that easily permeates oxygen
  • the upper insulator 550b is a diffusion of oxygen. It is preferable to use an insulator having a function of suppressing the above. With such a configuration, oxygen contained in the insulator 550a can be suppressed from diffusing into the conductor 560. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 530. Further, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a.
  • the insulator 550a may be provided by using a material that can be used for the above-mentioned insulator 550, and the insulator 550b may be an insulator containing an oxide of one or both of aluminum and hafnium.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate) and the like can be used.
  • hafnium oxide is used as the insulator 550b.
  • the insulator 550b is an insulator having at least oxygen and hafnium.
  • the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 550b may have, at least in part, a region having the above-mentioned film thickness.
  • an insulating material which is a high-k material having a high relative permittivity may be used for the insulator 550b.
  • the gate insulator By forming the gate insulator into a laminated structure of the insulator 550a and the insulator 550b, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Therefore, the withstand voltage of the insulator 550 can be increased.
  • EOT equivalent oxide film thickness
  • the insulator 554 functions as a part of the gate insulator.
  • silicon nitride formed by the PEALD method may be used as the insulator 554.
  • the insulator 554 is an insulator having at least nitrogen and silicon.
  • the insulator 554 may further have a barrier property against oxygen. As a result, oxygen contained in the insulator 550 can be suppressed from diffusing into the conductor 560.
  • the insulator 554 needs to be provided in the opening formed in the insulator 580 or the like together with the insulator 552, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, it is preferable that the thickness of the insulator 554 is thin.
  • the film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 554 may have a region having the above-mentioned film thickness at least in a part thereof.
  • the film thickness of the insulator 554 is preferably thinner than the film thickness of the insulator 550.
  • the insulator 554 may have a region having a film thickness thinner than that of the insulator 550, at least in part.
  • the conductor 560 functions as the first gate electrode of the transistor 500.
  • the conductor 560 preferably has a conductor 560a and a conductor 560b arranged on the conductor 560a.
  • the conductor 560a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 560b.
  • the position of the upper part of the conductor 560 substantially coincides with the position of the upper part of the insulator 550. In FIGS.
  • the conductor 560 is shown as a two-layer structure of the conductor 560a and the conductor 560b, but the conductor 560 has a single-layer structure or a three-layer structure other than the two-layer structure. It can be a laminated structure with more than one layer.
  • a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one such as an oxygen atom and an oxygen molecule.
  • the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductor 560 also functions as wiring, it is preferable to use a conductor having high conductivity.
  • a conductor having high conductivity for example, as the conductor 560b, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 560b can have a laminated structure. Specifically, for example, the conductor 560b may have a laminated structure of titanium or titanium nitride and the conductive material.
  • the conductor 560 is self-aligned so as to fill the opening formed in the insulator 580 or the like.
  • the conductor 560 can be reliably arranged in the region between the conductor 542a and the conductor 542b without aligning the conductor 560.
  • the height is preferably lower than the height of the bottom surface of the oxide 530b.
  • the conductor 560 functioning as a gate electrode covers the side surface and the upper surface of the channel forming region of the oxide 530b via an insulator 550 or the like, so that the electric field of the conductor 560 can be applied to the channel forming region of the oxide 530b. It becomes easier to act on the whole. Therefore, the on-current of the transistor 500 can be increased and the frequency characteristics can be improved.
  • the difference is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and preferably 20 nm or less, 50 nm or less, or 100 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 580 is provided on the insulator 544, and an opening is formed in the region where the insulator 550 and the conductor 560 are provided. Further, the upper surface of the insulator 580 may be flattened.
  • the insulator 580 that functions as an interlayer film preferably has a low dielectric constant.
  • a material having a low dielectric constant As an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the insulator 580 is provided, for example, by using the same material as the insulator 516.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen desorbed by heating.
  • the insulator 580 has a reduced concentration of impurities such as water and hydrogen in the insulator 580.
  • the insulator 580 may appropriately use an oxide containing silicon such as silicon oxide and silicon nitride nitride.
  • the insulator 574 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 580 from above, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen.
  • a metal oxide having an amorphous structure for example, an insulator such as aluminum oxide may be used. In this case, the insulator 574 is an insulator having at least oxygen and aluminum.
  • the insulator 574 which has a function of capturing impurities such as hydrogen in contact with the insulator 580, hydrogen contained in the insulator 580 and the like can be provided. Impurities can be captured and the amount of hydrogen in the region can be kept constant.
  • the insulator 576 functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 580 from above. Insulator 576 is placed on top of insulator 574.
  • a nitride containing silicon such as silicon nitride or silicon nitride oxide.
  • silicon nitride formed by a sputtering method may be used as the insulator 576.
  • a silicon nitride film having a high density can be formed.
  • silicon nitride formed by the PEALD method or the CVD method may be further laminated on the silicon nitride formed by the sputtering method.
  • one of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540a functioning as a plug, and the other of the first terminal or the second terminal of the transistor 500 is connected to the conductor 540b. It is electrically connected.
  • the conductor 540a and the conductor 540b are collectively referred to as a conductor 540.
  • the conductor 540a is provided in a region overlapping with the conductor 542a. Specifically, in the region overlapping with the conductor 542a, the insulator 571, the insulator 544, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 shown in FIG. 24A, and the insulator further shown in FIG. 23. An opening is formed in the 582 and the insulator 586, and the conductor 540a is provided inside the opening. Further, the conductor 540b is provided, for example, in a region overlapping with the conductor 542b.
  • An opening is formed in the 582 and the insulator 586, and the conductor 540b is provided inside the opening.
  • the insulator 582 and the insulator 586 will be described later.
  • an insulator 541a may be provided as an insulator having a barrier property against impurities between the side surface of the opening of the region overlapping with the conductor 542a and the conductor 540a. ..
  • an insulator 541b may be provided as an insulator having a barrier property against impurities between the side surface of the opening of the region overlapping with the conductor 542b and the conductor 540b.
  • the insulator 541a and the insulator 541b are collectively referred to as an insulator 541.
  • the conductor 540a and the conductor 540b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 540a and the conductor 540b may have a laminated structure.
  • the conductor 540 has a laminated structure
  • the insulator 574, the insulator 576, the insulator 581, the insulator 580, the insulator 544, and the first conductor arranged in the vicinity of the insulator 571 are included in the first conductor.
  • a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated manner. Further, it is possible to prevent impurities such as water and hydrogen contained in the layer above the insulator 576 from being mixed into the oxide 530 through the conductor 540a and the conductor 540b.
  • a barrier insulating film that can be used for the insulator 544 or the like may be used.
  • insulators such as silicon nitride, aluminum oxide, and silicon nitride may be used. Since the insulator 541a and the insulator 541b are provided in contact with the insulator 574, the insulator 576, and the insulator 571, impurities such as water and hydrogen contained in the insulator 580 and the like are contained in the conductor 540a and the conductor 540b. It is possible to prevent the oxide from being mixed with the oxide 530. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 580 from being absorbed by the conductor 540a and the conductor 540b.
  • the first insulator in contact with the inner wall of the opening such as the insulator 580 and the second insulator inside the insulator are against oxygen. It is preferable to use a barrier insulating film in combination with a barrier insulating film against hydrogen.
  • aluminum oxide formed by the ALD method may be used as the first insulator, and silicon nitride formed by the PEALD method may be used as the second insulator.
  • silicon nitride formed by the PEALD method may be used as the second insulator.
  • the transistor 500 shows a configuration in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are laminated
  • the present invention is not limited to this.
  • the insulator 541 may be provided as a single layer or a laminated structure having three or more layers.
  • the configuration in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are laminated is shown, but the present invention is not limited to this.
  • the conductor 540 may be provided as a single layer or a laminated structure having three or more layers.
  • a conductor 610, a conductor 612, or the like which is in contact with the upper part of the conductor 540a and the upper part of the conductor 540b and functions as wiring may be arranged.
  • the conductor 610 and the conductor 612 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor may also have a laminated structure.
  • the conductor may be titanium or a laminate of titanium nitride and the conductive material.
  • the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • the structure of the transistor included in the semiconductor device of the present invention is not limited to the transistor 500 shown in FIGS. 23, 24A, 24B, and 25.
  • the structure of the transistor included in the semiconductor device of the present invention may be changed depending on the situation.
  • the transistor 500 shown in FIGS. 23, 24A, 24B, and 25 may have the configuration shown in FIG. 27.
  • the transistor of FIG. 27 differs from the transistor 500 shown in FIGS. 23, 24A, 24B, and 25 in that it has an oxide of 543a and an oxide of 543b.
  • the oxide 543a and the oxide 543b are collectively referred to as an oxide 543.
  • the cross section of the transistor in FIG. 27 in the channel width direction can be the same as the cross section of the transistor 500 shown in FIG. 24B.
  • the oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b.
  • the oxide 543a is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a.
  • the oxide 543b is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.
  • the oxide 543 preferably has a function of suppressing the permeation of oxygen.
  • the oxide 543 having a function of suppressing the permeation of oxygen between the conductor 542 functioning as the source electrode and the drain electrode and the oxide 530b, electricity between the conductor 542 and the oxide 530b can be obtained. It is preferable because the resistance is reduced. With such a configuration, the electrical characteristics, field effect mobility, and reliability of the transistor 500 may be improved.
  • a metal oxide having an element M may be used.
  • the element M aluminum, gallium, yttrium, or tin may be used.
  • the oxide 543 preferably has a higher concentration of the element M than the oxide 530b.
  • gallium oxide may be used as the oxide 543.
  • a metal oxide such as In—M—Zn oxide may be used.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the film thickness of the oxide 543 is preferably 0.5 nm or more, or 1 nm or more, and preferably 2 nm or less, 3 nm or less, or 5 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the oxide 543 preferably has crystallinity. When the oxide 543 has crystallinity, the release of oxygen in the oxide 530 can be suitably suppressed. For example, as the oxide 543, if it has a crystal structure such as a hexagonal crystal, it may be possible to suppress the release of oxygen in the oxide 530.
  • An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • FIGS. 23 and 25 The wiring or plug around the capacitive element 600 and its surroundings will be described.
  • a capacitive element 600, wiring, and / or a plug are provided above the transistor 500 shown in FIGS. 23 and 25.
  • the capacitive element 600 has, for example, a conductor 610, a conductor 620, and an insulator 630.
  • a conductor 610 is provided on one of the conductors 540a or 540b, the conductor 546, and the insulator 586.
  • the conductor 610 has a function as one of a pair of electrodes of the capacitive element 600.
  • the conductor 612 is provided on the other of the conductor 540a or the conductor 540b and on the insulator 586.
  • the conductor 612 has a function as a plug, wiring, terminal, or the like for electrically connecting the transistor 500 and a circuit element, wiring, or the like arranged above.
  • the conductor 612 can be a wiring WDL in the semiconductor device SDV1 described in the first embodiment.
  • the conductor 612 and the conductor 610 may be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components.
  • a metal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film and the like can be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 612 and the conductor 610 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.
  • An insulator 630 is provided on the insulator 586 and the conductor 610.
  • the insulator 630 functions as a dielectric sandwiched between a pair of electrodes of the capacitive element 600.
  • Examples of the insulator 630 include silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum oxide, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, and hafnium nitride. Zylon oxide or the like can be used. Further, the insulator 630 can be provided as a laminated or a single layer by using the above-mentioned material.
  • the capacitive element 600 can secure a sufficient capacitance by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacitance is improved. It is possible to suppress electrostatic breakdown of the element 600.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • the insulator 630 may include, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST). Insulators containing high-k material may be used in single layers or in layers. Further, as the insulator 630, a compound containing hafnium and zirconium may be used. As semiconductor devices become finer and more integrated, problems such as leakage currents in transistors and capacitive elements may occur due to the thinning of the gate insulator and the dielectric used in the capacitive element.
  • the gate insulator and the insulator that functions as a dielectric used for the capacitive element By using a high-k material for the gate insulator and the insulator that functions as a dielectric used for the capacitive element, it is possible to reduce the gate potential during transistor operation and secure the capacitance of the capacitive element while maintaining the physical film thickness. It will be possible.
  • the conductor 620 is provided so as to be superimposed on the conductor 610 via the insulator 630.
  • the conductor 610 has a function as one of a pair of electrodes of the capacitive element 600. Further, for example, the conductor 620 can be the wiring WWLB in the semiconductor device SDV1 described in the first embodiment.
  • a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when it is formed at the same time as another structure such as a conductor, Cu (copper), Al (aluminum) or the like, which are low resistance metal materials, may be used. Further, for example, as the conductor 620, a material applicable to the conductor 610 can be used. Further, the conductor 620 may have a laminated structure of two or more layers instead of a single layer structure.
  • An insulator 640 is provided on the conductor 620 and the insulator 630.
  • the insulator 640 for example, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 500 is provided. Therefore, the same material as the insulator 324 can be used.
  • An insulator 650 is provided on the insulator 640.
  • the insulator 650 can be provided by using the same material as the insulator 320. Further, the insulator 650 may function as a flattening film that covers the uneven shape below the insulator 650. Therefore, the insulator 650 can be, for example, a material applicable to the insulator 324.
  • the capacitive element 600 shown in FIGS. 23 and 25 is of a planar type, but the shape of the capacitive element is not limited to this.
  • the capacitive element 600 may be, for example, a cylinder type instead of the planar type.
  • a wiring layer may be provided above the capacitive element 600.
  • the insulator 411, the insulator 412, the insulator 413, and the insulator 414 are provided in order above the insulator 650.
  • the insulator 411, the insulator 412, and the insulator 413 are provided with a conductor 416 that functions as a plug or wiring.
  • the conductor 416 can be provided in a region superposed on the conductor 660, which will be described later.
  • the insulator 630, the insulator 640, and the insulator 650 are provided with an opening in a region overlapping with the conductor 612, and the conductor 660 is provided so as to fill the opening.
  • the conductor 660 functions as a plug and wiring that are electrically connected to the conductor 416 included in the wiring layer described above.
  • the insulator 411 and the insulator 414 for example, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324 and the like. Therefore, as the insulator 411 and the insulator 414, for example, a material applicable to the insulator 324 and the like can be used.
  • the insulator 412 and the insulator 413 for example, like the insulator 326, it is preferable to use an insulator having a relatively low relative permittivity in order to reduce the parasitic capacitance generated between the wirings.
  • the conductor 612 and the conductor 416 can be provided, for example, by using the same materials as the conductor 328 and the conductor 330.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like. ..
  • FIG. 28A is a diagram illustrating the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).
  • IGZO a metal oxide containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes “completable amorphous”.
  • Crystalline includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-AlignedComposite) (excluding single crystal).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 28A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • FIG. 28B the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 28B (horizontal axis is 2 ⁇ [deg.], And vertical axis is intensity. (Intensity) is represented by an arbitrary unit (a.u.)).
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 28B is simply referred to as an XRD spectrum.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or the substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 28C.
  • FIG. 28C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 28A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystal oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: atomous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a grid image, for example, in a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to the replacement of metal atoms, and the like. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be deteriorated due to the mixing of impurities, the generation of defects, etc., CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method. For example, when structural analysis is performed on an nc-OS film using an XRD device, a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan. Further, when electron beam diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter larger than that of nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron beam diffraction also referred to as selected area electron diffraction
  • nanocrystals for example, 50 nm or more
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic shape or a patch shape.
  • the CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). It is said.). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) are unevenly distributed and have a mixed structure.
  • the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function).
  • the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on -current (Ion), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more preferably 1 ⁇ 10 -9 cm -3 or more.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor are determined. 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • This embodiment shows an example of a semiconductor wafer on which the semiconductor device and the like shown in the above embodiment are formed, and an electronic component in which the semiconductor device is incorporated.
  • the semiconductor wafer 4800 shown in FIG. 29A has a wafer 4801 and a plurality of circuit units 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is a dicing region.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by the previous process. Further, after that, the opposite surface on which the plurality of circuit portions 4802 of the wafer 4801 are formed may be ground to reduce the thickness of the wafer 4801. By this step, the warp of the wafer 4801 can be reduced and the size of the wafer can be reduced.
  • a dicing process is performed. Dicing is performed along the scribe line SCL1 and the scribe line SCL2 (sometimes referred to as a dicing line or a cutting line) indicated by a alternate long and short dash line.
  • the spacing 4803 is provided so that the plurality of scribe lines SCL1 are parallel to each other and the plurality of scribe lines SCL2 are parallel to each other in order to facilitate the dicing process. It is preferable to provide it so that it is vertical.
  • the chip 4800a as shown in FIG. 29B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a has a wafer 4801a, a circuit unit 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit portions 4802 may be substantially the same as the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.
  • the shape of the element substrate of one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 29A.
  • the shape of the element substrate can be appropriately changed depending on the process of manufacturing the device and the device for manufacturing the device.
  • FIG. 29C shows a perspective view of a board (mounting board 4704) on which the electronic component 4700 and the electronic component 4700 are mounted.
  • the electronic component 4700 shown in FIG. 29C has a chip 4800a in the mold 4711. As shown in FIG. 29C, the chip 4800a may have a configuration in which circuit units 4802 are laminated. In FIG. 29C, a part is omitted in order to show the inside of the electronic component 4700.
  • the electronic component 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714.
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board 4702 to complete the mounting board 4704.
  • FIG. 29D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • the electronic component 4730 is provided with an interposer 4731 on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • the electronic component 4730 has a semiconductor device 4710.
  • the semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, a wideband memory (HBM: High Bandwidth Memory), or the like.
  • HBM High Bandwidth Memory
  • an integrated circuit semiconductor device such as a CPU, GPU, FPGA, or storage device can be used.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. Multiple wirings are provided in a single layer or multiple layers. Further, the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732. For these reasons, the interposer may be referred to as a "rewiring board" or an "intermediate board”. Further, a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode. Further, in the silicon interposer, a TSV (Through Silicon Via) can be used as a through electrode.
  • TSV Three Silicon Via
  • interposer 4731 It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as an interposer for mounting HBM.
  • the reliability is unlikely to decrease due to the difference in expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided on top of the electronic component 4730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 4731 are the same.
  • the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.
  • an electrode 4733 may be provided on the bottom of the package substrate 4732.
  • FIG. 29D shows an example in which the electrode 4733 is formed of a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 4733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 4730 can be mounted on another board by using various mounting methods, not limited to BGA and PGA.
  • BGA Base-Chip
  • PGA Stepgered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFN
  • FIG. 30 illustrates how each electronic device includes an electronic component 4700 having the semiconductor device.
  • the information terminal 5500 shown in FIG. 30 is a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and a button is provided in the housing 5510.
  • the information terminal 5500 can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5511. Examples thereof include an application displayed on the display unit 5511 and an application for performing biometric authentication such as fingerprints and voice prints.
  • FIG. 30 shows a wristwatch-type information terminal 5900 as an example of a wearable terminal.
  • the information terminal 5900 has a housing 5901, a display unit 5902, an operation button 5903, an operator 5904, a band 5905, and the like.
  • the wearable terminal can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • applications using artificial intelligence include an application that manages the health condition of a person wearing a wearable terminal, a navigation system that selects and guides the optimum route by inputting a destination, and the like.
  • FIG. 30 shows a desktop type information terminal 5300.
  • the desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like. Further, by using the desktop type information terminal 5300, it is possible to develop a new artificial intelligence.
  • a smartphone, a desktop information terminal, and a wearable terminal are taken as examples of electronic devices, respectively, which are shown in FIG. 30, but information terminals other than smartphones, desktop information terminals, and wearable terminals can be applied.
  • information terminals other than smartphones, desktop information terminals, and wearable terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.
  • FIG. 30 shows an electric freezer / refrigerator 5800 as an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric refrigerator / freezer 5800 having artificial intelligence can be realized.
  • the electric freezer / refrigerator 5800 has a function to automatically generate a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800, the expiration date of the foodstuffs, etc., and the foodstuffs stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the above.
  • an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a washing machine, a microwave oven, an electric oven, a rice cooker, a water heater, an IH (Induction Heating) cooker, a water server, and air.
  • electric appliances include, for example, a washing machine, a microwave oven, an electric oven, a rice cooker, a water heater, an IH (Induction Heating) cooker, a water server, and air.
  • heating and cooling appliances including conditioners, washing machines, dryers, and audiovisual equipment.
  • FIG. 30 illustrates a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 has a housing 5201, a display unit 5202, a button 5203, and the like.
  • FIG. 30 shows a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can be provided with a display unit for displaying a game image, a touch panel as an input interface other than buttons, a stick, a rotary knob, a slide knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 30, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a controller having a shape imitating a gun can be used by using a trigger as a button.
  • a controller having a shape imitating a musical instrument, a music device, or the like can be used.
  • the stationary game machine may be provided with a camera, a depth sensor, a microphone, or the like instead of using a controller, and may be operated by a game player's gesture and / or voice.
  • the video of the above-mentioned game machine can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • the semiconductor device described in the above embodiment By applying the semiconductor device described in the above embodiment to the portable game machine 5200, it is possible to realize the portable game machine 5200 with low power consumption. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5200 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the program that the game has, but by applying artificial intelligence to the portable game machine 5200, .
  • Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
  • the game player can be constructed in an anthropomorphic manner by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one person can play the game. You can play games.
  • FIG. 30 illustrates a portable game machine as an example of a game machine, but the electronic device of one aspect of the present invention is not limited to this.
  • Examples of the electronic device of one aspect of the present invention include a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a pitching machine for batting practice installed in a sports facility. Machines and the like.
  • the semiconductor device described in the above embodiment can be applied to an automobile which is a mobile body and around the driver's seat of the automobile.
  • FIG. 30 illustrates an automobile 5700, which is an example of a moving body.
  • an instrument panel that can display speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. Further, a display device showing such information may be provided around the driver's seat.
  • the semiconductor device described in the above embodiment can be applied as a component of artificial intelligence
  • the semiconductor device can be used, for example, in an automatic driving system of an automobile 5700. Further, the semiconductor device can be used in a system for performing road guidance, danger prediction, and the like.
  • the display device may be configured to display information such as road guidance and danger prediction.
  • the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the semiconductor device of one aspect of the present invention is applied to these moving objects. Then, a system using artificial intelligence can be provided.
  • FIG. 30 illustrates a digital camera 6240, which is an example of an image pickup device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, a shutter button 6244, and the like, and a removable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured so that a strobe device, a viewfinder, or the like can be separately attached.
  • a low power consumption digital camera 6240 can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the digital camera 6240 having artificial intelligence can be realized.
  • the digital camera 6240 has a function to automatically recognize a subject such as a face or an object, a function to adjust the focus according to the subject, a function to automatically fire a flash according to the environment, and an captured image. Can have a function of toning.
  • Video camera The semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 30 illustrates a video camera 6300, which is an example of an image pickup device.
  • the video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation key 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation key 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by the connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connection unit 6306.
  • the video camera 6300 can perform pattern recognition by artificial intelligence at the time of encoding. By this pattern recognition, it is possible to calculate the difference data of people, animals, objects, etc. included in the continuous captured image data and compress the data.
  • the semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • FIG. 31A shows, as an example of the expansion device, an expansion device 6100 externally attached to a PC, which is equipped with a portable chip capable of arithmetic processing.
  • the expansion device 6100 can perform arithmetic processing by the chip by connecting to a PC by, for example, USB (Universal Serial Bus) or the like.
  • USB Universal Serial Bus
  • FIG. 31A illustrates a portable expansion device 6100, but the expansion device according to one aspect of the present invention is not limited to this, and is relatively equipped with, for example, a cooling fan. It may be a large form of expansion device.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104.
  • the substrate 6104 is housed in the housing 6101.
  • the substrate 6104 is provided with a circuit for driving the semiconductor device or the like described in the above embodiment.
  • a chip 6105 for example, a semiconductor device, an electronic component 4700, a memory chip, etc. described in the above embodiment
  • a controller chip 6106 are attached to the substrate 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • the expansion device 6100 such as a PC
  • the arithmetic processing capacity of the PC can be increased.
  • even a PC with insufficient processing capacity can perform operations such as artificial intelligence and moving image processing.
  • FIG. 31B schematically shows data transmission in a broadcasting system. Specifically, FIG. 31B shows a route for a radio wave (broadcast signal) transmitted from a broadcasting station 5680 to reach a television receiving device (TV) 5600 in each home.
  • the TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.
  • the antenna 5650 illustrates a UHF (Ultra High Frequency) antenna, but as the antenna 5650, a BS / 110 ° CS antenna, a CS antenna, or the like can also be applied.
  • UHF Ultra High Frequency
  • the radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio waves 5675A and transmits the radio waves 5675B.
  • the terrestrial broadcasting can be watched on the TV 5600.
  • the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 31B, and may be satellite broadcasting using an artificial satellite, data broadcasting by an optical line, or the like.
  • the above-mentioned broadcasting system may be a broadcasting system using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • the broadcasting data is transmitted from the broadcasting station 5680 to the TV 5600 of each household, the broadcasting data is compressed by the encoder, and when the antenna 5650 receives the broadcasting data, the decoder of the receiving device included in the TV 5600 compresses the broadcasting data. Restoration is done.
  • artificial intelligence for example, in motion compensation prediction, which is one of the compression methods of an encoder, it is possible to recognize a display pattern included in a display image. In-frame prediction using artificial intelligence can also be performed. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, it is possible to perform image interpolation processing such as up-conversion in the restoration of the broadcast data by the decoder.
  • the above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.
  • UHDTV ultra-high definition television
  • a recording device having artificial intelligence may be provided on the TV5600.
  • a recording device having artificial intelligence may be provided on the TV5600.
  • FIG. 31C shows a palm print authentication device, which has a housing 6431, a display unit 6432, a palm print reading unit 6433, and wiring 6434.
  • FIG. 31C shows how the palm print authentication device acquires the palm print of the hand 6435.
  • the acquired palm print is processed for pattern recognition using artificial intelligence, and it is possible to determine whether or not the palm print belongs to the person himself / herself. This makes it possible to construct a system that performs highly secure authentication.
  • the authentication system according to one aspect of the present invention is not limited to the palm print authentication device, but is a device that acquires biometric information such as fingerprints, veins, faces, irises, voice prints, genes, and physiques to perform biometric authentication. May be good.
  • the configuration of the circuit MC shown in FIG. 4 is input to the circuit simulator, the current IW flowing between the first terminal and the second terminal of the transistor M2, and the current IW between the first terminal and the second terminal of the transistor M6.
  • the output current flowing between the first terminal and the second terminal (wiring OL) of the transistor M10 was calculated.
  • the capacitance CG included in the circuit MC of FIG. 5 input to the simulation is omitted, and the power gating (operation of supplying or stopping the high power supply potential) by the transistor M1 shown in FIG. 5 is performed.
  • the voltage held at the gate of the transistor M2 is a potential in the voltage range from 0.25V to 0.32V in increments of 0.01V.
  • the potential input to the wiring XDL that is, the potential input to the gate of the transistor M6 is, as an example, a potential in the voltage range from 0.2V to 0.34V in 0.02V increments.
  • the potential input to the wiring BDL that is, the potential input to the gate of the transistor M9 is always set to 0.34 V as an example.
  • FIG. 32A shows a graph of the output current obtained by the simulation under the above-mentioned voltage input conditions.
  • the horizontal axis of FIG. 32A shows the magnitude of the theoretically expected output current
  • the vertical axis shows the magnitude of the output current calculated by the simulation. From the results of the graph of FIG. 32A, it was confirmed that the magnitude of the output current calculated by the simulation was almost the same as the magnitude of the theoretically expected output current.
  • FIG. 32B the calculation efficiency of the circuit used in the above simulation is shown in FIG. 32B.
  • the horizontal axis of FIG. 32B shows the magnitude of the output current calculated by the simulation, and the vertical axis of FIG. 32B shows the calculation efficiency.
  • the calculation efficiency differs for each output current, but it was confirmed that the calculation efficiency was 100 TOPS / W or more at all output currents.
  • FIG. 33 is a circuit configuration used in the simulation, and has a transistor MS, a transistor BTr, and a capacitance BC.
  • the transistor for adjusting the threshold voltage is a transistor MS
  • the transistor MS corresponds to, for example, the transistor M2, the transistor M5 to the transistor M10 in the circuit MC of FIG.
  • the transistor BTr and the capacitance BC are included in the circuit HC
  • the circuit HC is, for example, the circuit HC2, the circuit HC5, the circuit HC6, the circuit HC7, the circuit HC8, and the circuit HC9 in the circuit MC of FIG.
  • the voltage V bs between the back gate and the source (terminal ST1) of the transistor MS can be held by the capacitance BC.
  • the first terminal of the transistor MS is under the condition that the voltage between the gate (terminal GT) and the source (terminal ST1) is 0 V.
  • a current of 1.0 ⁇ 10-14 A is passed between the second terminals.
  • the voltage between the gate (terminal GT) and the source (terminal ST1) is increased by controlling V bs in the voltage range from 0V to 2.5V.
  • a current of approximately 1.0 ⁇ 10-14 A could flow between the first terminal and the second terminal of the transistor MS under the condition of 0 V.
  • the relationship between the threshold voltage V sh of the transistor MS and the voltage V bs between the back gate and the source (terminal ST1) of the transistor MS is as shown in FIG. 34.
  • the circuit HC shown in FIG. 33 (corresponding to the circuit HC2, the circuit HC5 to the circuit HC10 in FIG. 3) is a transistor MS (transistor M2, transistor M5 to) for controlling the threshold voltage. It was confirmed that the threshold voltage of the transistor MS can be appropriately controlled by electrically connecting to the back gate of the transistor M10).
  • SDV1 Semiconductor device
  • SDV1-1 Semiconductor device
  • SDV1-2 Transistor device
  • SDV2 Semiconductor device
  • SDV3 Semiconductor device
  • SDV4 Semiconductor device
  • SDV5 Transistor device
  • CA Transistor
  • MC Circuit, MC [1 , 1]: circuit, MC [1, n]: circuit, MC [h, 1]: circuit, MC [h, n]: circuit, MC [m-h + 1,1]: circuit, MC [m-h + 1, n]: circuit, MC [m, 1]: circuit, MC [m, n]: circuit, MC [1]: circuit, MC [h]: circuit, MC [m-h + 1]: circuit, MC [m]: Circuit, WDC: Circuit, WDIC: Circuit, WDICA: Circuit, XDC: Circuit, BDC: Circuit, WWC: Circuit, XWC: Circuit, BGC: Circuit, ACTV: Circuit,

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