WO2022028088A1 - 用于系统级芯片设计的标准单元及应用其的数据处理单元、运算芯片和计算设备 - Google Patents

用于系统级芯片设计的标准单元及应用其的数据处理单元、运算芯片和计算设备 Download PDF

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WO2022028088A1
WO2022028088A1 PCT/CN2021/098910 CN2021098910W WO2022028088A1 WO 2022028088 A1 WO2022028088 A1 WO 2022028088A1 CN 2021098910 W CN2021098910 W CN 2021098910W WO 2022028088 A1 WO2022028088 A1 WO 2022028088A1
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type
threshold
transistor
standard cell
chip
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PCT/CN2021/098910
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English (en)
French (fr)
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孔维新
杨作兴
田文博
于东
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深圳比特微电子科技有限公司
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Priority to US17/997,319 priority Critical patent/US11768988B2/en
Priority to CA3177015A priority patent/CA3177015C/en
Publication of WO2022028088A1 publication Critical patent/WO2022028088A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Definitions

  • the present disclosure generally relates to standard cells for system-on-chip design and data processing units, arithmetic chips and computing devices using the same, and more particularly, to standard cells using hybrid threshold technology and data processing using the same Units, computing chips and computing devices.
  • multi-threshold voltage design is gradually becoming an important design method in the physical design of digital circuits.
  • existing multi-threshold designs are usually performed at the cell level, that is, devices within a cell use the same threshold.
  • the device threshold that is, the standard cells used in a standard cell library belong to the same threshold type, for example, each standard cell in the RVT (common threshold) library All use only RVT threshold type devices, and each standard cell in the LVT (low threshold) library only uses LVT threshold type devices.
  • a standard cell for a system-on-chip design comprising a plurality of semiconductor devices and implementing basic logic functions, wherein the plurality of semiconductor devices comprises: a first threshold type a transistor; and a second transistor of a second threshold type; wherein a threshold range of the first threshold type is different from a threshold range of the second threshold type.
  • the rise delay time and the fall delay time of the standard cells are balanced.
  • the plurality of semiconductor devices further include: a third transistor of a third threshold type, wherein the threshold range of the third threshold type is different from the threshold ranges of the first threshold type and the second threshold type, and wherein, By selecting the first threshold type, the second threshold type and the third threshold type, the rise delay time and the fall delay time of the standard cells are balanced.
  • the first threshold type, the second threshold type or the third threshold type are selected from the following: common threshold RVT type, low threshold LVT type, ultra-low threshold SLVT type, and high threshold HVT type.
  • the first transistor is an n-type transistor and the second transistor is a p-type transistor; or wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor.
  • the first transistor and the second transistor are both n-type transistors or p-type transistors.
  • the standard cell is an inverter
  • the first transistor is a low-threshold LVT type p-type transistor
  • the second transistor is an ultra-low threshold SLVT type n-type transistor
  • the first transistor and the gate of the second transistor is connected to the input terminal of the standard cell
  • the drain of the first transistor and the second transistor is connected to the output terminal of the standard cell.
  • a data processing unit comprising at least one standard unit as previously described.
  • an arithmetic chip including at least one data processing unit as described above.
  • a computing device for executing an algorithm for mining virtual digital currency, and comprising: at least one computing chip as described above; a control chip; a power module; a heat sink; Wherein, the control chip is coupled to the at least one operation chip and is used to control the operation of the at least one operation chip, wherein the power supply module is used to supply the power to the at least one operation chip, the control chip and/or the at least one operation chip.
  • the heat sink provides power, and wherein the heat sink is used to dissipate heat to the at least one computing chip, the control chip and/or the power module.
  • FIG. 1 exemplarily shows a schematic diagram of a standard cell according to an embodiment of the present disclosure
  • FIG. 2 exemplarily shows a schematic diagram of a standard cell used as an inverter according to a specific embodiment of the present disclosure
  • FIG. 3 exemplarily shows a schematic diagram of a standard cell used as a dynamic edge-triggered register according to a specific embodiment of the present disclosure.
  • FIG. 4 exemplarily shows a schematic diagram of a data processing unit, an arithmetic chip, and a computing device according to an embodiment of the present disclosure.
  • Standard cell is the basis of modern system-on-chip (SOC) design. It can design some basic logic functions into splicable cells according to some principles such as equal height and variable width, so as to facilitate subsequent implementation by design automation (EDA) tools complex system.
  • EDA design automation
  • the balance between the rise delay time and the fall delay time of the standard cell is an important indicator to measure the performance of the standard cell, which plays an important role in optimizing the clock network and reducing glitch power consumption. In many cases, balancing the rise and fall delay times may mean making the rise and fall delay times substantially the same.
  • the channel length of each transistor is usually set to the minimum feature size to obtain the best performance.
  • CMOS Complementary Metal-Oxide-Semiconductor
  • PMOS P-type Metal-Oxide-Semiconductor
  • NMOS N-type Metal-Oxide-Semiconductor
  • the adjustable parameter is the number of Fins (fins) of the transistor, so there are usually only a few fixed integer values to choose from.
  • the number of Fins is completely fixed and cannot be adjusted, which makes it very difficult to optimize the balance between the rise delay time and the fall delay time.
  • the present invention proposes a digital standard cell adopting a hybrid threshold technology, wherein transistors of different threshold types can be used, so that the balance of the rise delay time and the fall delay time of the standard cell can be realized in various situations. adjust.
  • the existing standard cell library is the most basic one of the reusable IP libraries, which can be provided by Foundry (semiconductor manufacturers) or third-party IP suppliers. Foundry or third-party IP suppliers generally only provide primary standard cell libraries for specific processes.
  • the standard cells in this primary standard cell library are designed for the general needs of many customers and use a single threshold type. On this basis, customers can design or improve standard cells by themselves, as a supplement to the primary standard cell library.
  • the standard cell using the hybrid threshold technology proposed by the present invention can be designed by the user and produced by Foundry. Since in the primary standard cell library provided by Foundry, generally only one threshold type device is used in the standard cell in a library, so it can be distinguished between ordinary threshold RVT library, low threshold LVT library, ultra-low threshold SVLT library, etc. Different from this, the standard cell using the hybrid threshold technology proposed in the present invention uses devices of different threshold types in one standard cell, so it does not belong to the existing library distinguished by the threshold type, but can be classified into two types according to other standards. The corresponding standard cell library.
  • NMOS and PMOS transistors will use ultra-low threshold SLVT type devices in this process, but the present invention proposes that the NMOS transistors can use ultra-low threshold SLVT type devices , and use a low-threshold LVT type device for the PMOS transistor, so as to achieve a balance between the rise delay time and the fall delay time. Specific embodiments according to the present disclosure will be described in detail below.
  • the plurality of semiconductor devices of the standard cell 100 include a first transistor 110 of a first threshold type and a second transistor 120 of a second threshold type.
  • the threshold range of the first threshold type is different from the threshold range of the second threshold type.
  • different threshold types may be implemented by different channel doping concentrations.
  • the channel of the transistor 110 of the first threshold type may have a first doping concentration
  • the channel of the transistor 120 of the second threshold type may have a second doping concentration different from the first doping concentration concentration.
  • the channel doping concentration is a decisive factor for the transistor threshold.
  • Different threshold types realized by different channel doping concentrations may include, for example, ordinary threshold RVT (Regular Vt) type, low threshold LVT (Low Vt) type, Super low threshold SLVT (Super low Vt) type and/or high threshold HVT (High Vt) type, etc.
  • the first threshold type or the second threshold type may be selected from a normal threshold RVT type, a low threshold LVT type, an ultra-low threshold SLVT type, and/or a high threshold HVT type, among others.
  • a normal threshold RVT type a low threshold LVT type
  • an ultra-low threshold SLVT type a high threshold HVT type
  • Those skilled in the art will understand that although some existing threshold types are described above, embodiments according to the present disclosure are not limited thereto, and more threshold types may be used, as long as the use of the threshold type is helpful It is sufficient to achieve a balance between the rise delay time and the fall delay time of the standard cell.
  • the first transistor 110 and the second transistor 120 may be any type of transistors fabricated by any process, including but not limited to MOS transistors, and may preferably be FinFET transistors.
  • the rise delay time and the fall delay time of the standard cell 100 are balanced.
  • the rise delay time refers to the delay time required for the signal at the output end of the standard cell to change to its specified upper limit after the signal at the input end of the standard cell is stabilized. Therefore, the rise delay time may include the path delay time from the input terminal to the output terminal of the standard cell and the time for the signal at the output terminal to transition from low to high.
  • the fall delay time refers to the delay time required for the signal at the output of the standard cell to change to its specified lower limit after the signal at the input of the standard cell stabilizes. Therefore, the fall delay time may include the path delay time from the input terminal to the output terminal of the standard cell and the time for the signal at the output terminal to transition from high to low.
  • the first transistor 110 in the standard cell 100 shown in FIG. 1 is a p-type transistor, and the second transistor 120 is an n-type transistor; in still others according to the present disclosure
  • the first transistor 110 in the standard cell 100 shown in FIG. 1 is an n-type transistor, and the second transistor 120 is a p-type transistor; in other embodiments according to the present disclosure, the standard cell 100 shown in FIG.
  • the first transistor 110 and the second transistor 120 in the cell 100 are both p-type transistors; and, in further embodiments according to the present disclosure, the first transistor 110 and the second transistor in the standard cell 100 shown in FIG. 1 120 are all n-type transistors.
  • NMOS transistors are usually used for signal pull-down, that is, when the output signal is flipped from high to low, NMOS transistors work; and PMOS transistors are usually used for signal pull-up ( pull up), that is, when the output signal flips from low to high, the PMOS transistor works.
  • the semiconductor process and/or the structure of the standard cell determine that the NMOS transistor and the PMOS transistor use the same threshold type, the NMOS transistor path is slower and the PMOS transistor has a slower path.
  • the CMOS standard cell may use a lower threshold NMOS transistor in combination with a higher threshold PMOS transistor, so that the NMOS path becomes faster and the PMOS path becomes slower, thereby realizing the NMOS transistor path and The speed of the PMOS transistor path is balanced to achieve a balance between the rising delay time and the falling delay time.
  • the semiconductor process or the structure of the standard cell determines that the NMOS transistor path is faster and the PMOS transistor path is slower when the NMOS transistor and PMOS transistor use the same threshold type, the higher threshold NMOS transistor can be used with the lower threshold.
  • Threshold PMOS transistors are used in combination, making the NMOS path slower and the PMOS path faster, so as to achieve a balance between the rise delay time and the fall delay time.
  • the standard cell 100 may be an inverter, wherein the gates of the first transistor 110 and the second transistor 120 are connected to the input of the standard cell 100, and the first transistor 110 and the second transistor 120 are connected to the input of the standard cell 100.
  • the drains of the two transistors 120 are connected to the output terminals of the standard cell 100 .
  • the first One transistor 110 uses an ultra-low threshold SLVT type p-type transistor
  • the second transistor 120 uses a low threshold LVT type n-type transistor, that is, a combination of a lower threshold PMOS transistor and a higher threshold NMOS transistor is realized, so that the PMOS transistor The path becomes faster and the NMOS path becomes slower, thereby balancing the rise and fall delay times of the standard cell 100 .
  • the standard cell 100 may further include: a third transistor of a third threshold type.
  • the threshold range of the third threshold type is different from the threshold ranges of the first threshold type and the second threshold type.
  • the rise delay time and the fall delay time of the standard cell 100 can be balanced by selecting the first threshold type, the second threshold type and the third threshold type.
  • different threshold types may be implemented by different channel doping concentrations of the transistors, for example, the channel of the transistor of the first threshold type has the first doping concentration, the channel of the transistor of the second threshold type has the first doping concentration The channel has a second doping concentration, the channel of the transistor of the third threshold type has a third doping concentration, and the first doping concentration, the second doping concentration, and the third doping concentration are different.
  • Different threshold types implemented by different channel doping concentrations may include, for example, a normal threshold RVT (Regular Vt) type, a low threshold LVT (Low Vt) type, an ultra-low threshold SLVT (Super low Vt) type and/or a high threshold HVT (High Vt) type and so on.
  • the first threshold type, the second threshold type or the third threshold type may be selected from a normal threshold RVT type, a low threshold LVT type, an ultra-low threshold SLVT type and/or a high threshold HVT type, among others.
  • a normal threshold RVT type a low threshold LVT type
  • an ultra-low threshold SLVT type a high threshold HVT type
  • Those skilled in the art will understand that although some existing threshold types are described above, embodiments according to the present disclosure are not limited thereto, and more threshold types may be used, as long as the use of the threshold type is helpful It is sufficient to achieve a balance between the rise delay time and the fall delay time of the standard cell.
  • a cell may include any number of transistors of any number of different threshold types.
  • FIG. 2 exemplarily shows a circuit diagram of a standard cell 200 used as an inverter according to a specific embodiment of the present disclosure.
  • the standard cell 200 is a specific example of the standard cell 100 shown in FIG.
  • the description of the standard cell 100 may also apply, at least in part, here.
  • a standard cell 200 serving as an inverter may include a first transistor M1 of a first threshold type, and a second transistor M2 of a second threshold type.
  • the gates of the first transistor M1 and the second transistor M2 are connected to the input terminal I of the standard cell 200, and the drains of the first transistor M1 and the second transistor M2 are connected to the output terminal O of the standard cell 200 , the source of the first transistor M1 is connected to the power supply VDD, and the source of the second transistor M2 is connected to the ground GND.
  • the first transistor M1 adopts a low-threshold LVT p-type transistor; the second transistor M2 adopts an ultra-low threshold SLVT-type n-type transistor, so that the rising delay time and falling delay time of the inverter are balanced.
  • the same threshold type is usually selected for both transistors of the inverter, i.e. a single threshold type design, but this results in an unbalanced rise delay time and fall delay time .
  • the threshold of the PMOS transistor used for pull-up of the signal is lower than the threshold of the NMOS transistor used for the pull-down of the signal.
  • the rise delay time of the inverter will be significantly smaller than the fall delay time, resulting in a poor balance between the rise delay time and the fall delay time of the standard cell.
  • the faster PMOS path does not bring performance improvement, but it brings the cost of increased dynamic power consumption and leakage.
  • the first transistor M1 used for signal pull-up selects a low-threshold LVT type p-type transistor
  • the first transistor M1 used for signal pull-down is a low-threshold LVT type transistor
  • the second transistor M2 is an n-type transistor with an ultra-low threshold value SLVT type, so that the rise delay time and fall delay time of the standard cell 200 used as an inverter tend to be balanced without increasing the number or size of devices, and can reduce Dynamic power consumption and leakage. That is, the standard cell using the hybrid threshold technology according to the embodiment of the present disclosure can achieve a balance between the rising delay time and the falling delay time without increasing the size and number of devices, and reduce dynamic power consumption and leakage, thereby improving performance A more superior standard unit.
  • FIG. 3 exemplarily shows a circuit diagram of a standard cell 300 used as a dynamic edge-triggered register according to a specific embodiment of the present disclosure.
  • the standard cell 300 is a specific example of the standard cell 100 shown in FIG. 1 , so The foregoing description of the standard cell 100 may also apply, at least in part, here. 3, the standard cell 300 serves as a dynamic edge-triggered register, which includes a transmission gate 302, an inverter 304, a transmission gate 306, and an inverter 308 connected in series between the input terminal D and the output terminal Q in sequence.
  • first transistors M1 ′ and M1 ′′ of a first threshold type wherein the first threshold type is selected as a low threshold LVT type
  • second transistor of the second threshold type M2' and M2" wherein the second threshold type is selected as an ultra-low threshold SLVT type
  • third transistors M3, M4, M3' and M4' of the third threshold type wherein the third threshold type is selected as a normal threshold RVT type .
  • the gate of the p-type third transistor M3 is connected to the clock signal CLKP, and the gate of the n-type third transistor M4 is connected to the clock signal CLKN; in contrast, in the transmission gate 306, the p-type The gate of the third transistor M3' is connected to the clock signal CLKN, and the gate of the n-type third transistor M4' is connected to the clock signal CLKP, wherein the clock signals CLKN and CLKP are mutually inverse clock signals.
  • the inverters 304 and 308 adopt the structure of the inverters shown in FIG. 2, that is, the first transistor M1 for pull-up of the signal ' and M1" select p-type transistors of low-threshold LVT type, and the second transistors M2' and M2" for signal pull-down select n-type transistors of ultra-low threshold SLVT type, so that the respective rises of the inverters 304 and 308 are The delay time is balanced with the fall delay time.
  • the p-type transistors and n-type transistors in the transmission gates can be of the same threshold type.
  • the transmission gate 302 is composed of a p-type third transistor M3 and an n-type third transistor M4 of the common threshold RVT type
  • the transmission gate 306 is composed of a common threshold value
  • the p-type third transistor M3 ′ of the RVT type is composed of an n-type third transistor M4 ′.
  • the drive capability of transmission gates 302 and 306 can be enhanced without affecting the balance of delay times.
  • the standard cell 300 used as a dynamic edge-triggered register according to the embodiment of the present disclosure, by reasonably adopting the mixed threshold design, it is possible to realize the difference between the rise delay time and the fall delay time without increasing the size and number of devices. Balance, reduce dynamic power consumption and leakage, and enhance drive capability to provide standard cells with better performance.
  • FIG. 4 exemplarily shows a schematic diagram of a data processing unit, an arithmetic chip, and a computing device according to an embodiment of the present disclosure.
  • a data processing unit 402 is also provided.
  • the data processing unit 402 includes at least one standard unit 100 as described above.
  • the data processing unit 402 may include both a standard unit 100 using a hybrid threshold technique as shown in FIG. 1 of the present application and a conventional standard unit using a single threshold type.
  • the data processing unit 402 can be used to implement relatively simple data processing functions, for example, it can be an adder, a multiplier, and the like.
  • the data processing unit 402 shown in FIG. 4 is part of the computing device 400, the data processing unit 402 may also be used alone as a separate component.
  • an arithmetic chip 404 is also provided.
  • the computing chip 404 includes at least one data processing unit 402 as described above.
  • the computing chip 404 can be used to implement relatively complex computing functions, for example, a certain algorithm (such as a hash algorithm) can be implemented.
  • a certain algorithm such as a hash algorithm
  • the computing chip 404 shown in FIG. 4 is part of the computing device 400, the computing chip 404 may also be used alone as a separate component.
  • the computing device 400 may include: at least one computing chip 404 as described above; a control chip 406 ; a power module 408 ; and a heat sink 410 .
  • the control chip 406 is coupled to at least one computing chip 404; the power module 408 can be used to provide power to at least one computing chip 404, the control chip 406 and/or the heat sink 410; the heat sink 410 can be used to supply power to the at least one computing chip 404,
  • the control chip 406 and/or the power module 408 dissipate heat.
  • computing device 400 may be used, for example, to perform a hashing algorithm for mining Bitcoin.
  • the word "exemplary” means “serving as an example, instance, or illustration” rather than as a “model” to be exactly reproduced. Any implementation illustratively described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be bound by any expressed or implied theory presented in the technical field, background, brief summary or detailed description.
  • the word “substantially” is meant to encompass any minor variation due to design or manufacturing imperfections, tolerances of devices or elements, environmental influences, and/or other factors.
  • the word “substantially” also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in an actual implementation.
  • connection means that one element/node/feature is electrically, mechanically, logically or otherwise directly connected to another element/node/feature (or direct communication).
  • coupled means that one element/node/feature can be mechanically, electrically, logically or otherwise linked, directly or indirectly, with another element/node/feature to allow interaction, even though the two features may not be directly connected. That is, “coupled” is intended to encompass both direct and indirect connections of elements or other features, including connections utilizing one or more intervening elements.
  • first,” “second,” and the like may also be used herein for reference purposes only, and are thus not intended to be limiting.
  • the terms “first,” “second,” and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly dictates otherwise.
  • providing is used broadly to encompass all ways of obtaining an object, thus “providing something” includes, but is not limited to, “purchasing,” “preparing/manufacturing,” “arranging/arranging,” “installing/ Assembly”, and/or “Order” objects, etc.

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Abstract

一种用于系统级芯片设计的标准单元（100），包括多个半导体器件并且用于实现基础逻辑功能。所述标准单元（100）包括：第一阈值类型的第一晶体管（110）；以及第二阈值类型的第二晶体管（120），所述第二阈值类型与所述第一阈值类型不同；其中，第一阈值类型的阈值范围与第二阈值类型的阈值范围不同。

Description

用于系统级芯片设计的标准单元及应用其的数据处理单元、运算芯片和计算设备
相关申请的交叉引用
本申请要求于2020年8月4日提交的、标题为“用于系统级芯片设计的标准单元及应用其的数据处理单元、运算芯片和计算设备”的中国专利申请第202010773501.9的优先权，该申请的公开内容通过引用被全部合并于此。
技术领域
本公开总体而言涉及用于系统级芯片设计的标准单元及应用其的数据处理单元、运算芯片和计算设备，更具体而言，涉及用于采用混合阈值技术的标准单元及应用其的数据处理单元、运算芯片和计算设备。
背景技术
当前，多阈值电压设计正逐渐成为数字电路物理设计中重要的设计手段。但是，现有的多阈值设计通常是在单元级别进行，即，一个单元内部的器件采用同一阈值。以常用的标准单元库为例，其通常是以器件阈值来分类，即，在一个标准单元库内用到的标准单元都属于同一阈值类型，例如，RVT(普通阈值)库中的各个标准单元都只采用RVT阈值类型的器件，LVT(低阈值)库中的各个标准单元都只采用LVT阈值类型的器件。
因此，存在对于改进的标准单元的需求。
发明内容
根据本公开的第一方面，提供有一种用于系统级芯片设计的标准单元，包括多个半导体器件并且用于实现基础逻辑功能，其中，所述多个半导体器件包括：第一阈值类型的第一晶体管；以及第二阈值类型的第二晶体管；其中，第一阈值类型的阈值范围与第二阈值类型的阈值范围不同。
优选地，其中，通过选择第一阈值类型和第二阈值类型，使得所述标准单元的上升延迟时间和下降延迟时间平衡。
优选地，所述多个半导体器件还包括：第三阈值类型的第三晶体管，其中，第三阈值 类型的阈值范围与第一阈值类型和第二阈值类型的阈值范围均不相同，以及其中，通过选择第一阈值类型、第二阈值类型和第三阈值类型，使得所述标准单元的上升延迟时间和下降延迟时间平衡。
优选地，其中，第一阈值类型、第二阈值类型或第三阈值类型选自以下：普通阈值RVT类型，低阈值LVT类型，超低阈值SLVT类型，高阈值HVT类型。
优选地，其中，第一晶体管是n型晶体管，并且第二晶体管是p型晶体管；或者其中，第一晶体管是p型晶体管，并且第二晶体管是n型晶体管。
优选地，其中，第一晶体管和第二晶体管都是n型晶体管或者都是p型晶体管。
优选地，其中，所述标准单元是反相器，所述第一晶体管是低阈值LVT类型的p型晶体管，所述第二晶体管是超低阈值SLVT类型的n型晶体管，所述第一晶体管和所述第二晶体管的栅极连接到所述标准单元的输入端，所述第一晶体管和所述第二晶体管的漏极连接到所述标准单元的输出端。
根据本公开的第二方面，提供有一种数据处理单元，其包括至少一个如前所述的标准单元。
根据本公开的第三方面，提供有一种运算芯片，其包括至少一个如前所述的数据处理单元。
根据本公开的第四方面，提供有一种计算设备，所述计算设备用于执行挖掘虚拟数字货币的算法，并且包括：至少一个如前所述的运算芯片；控制芯片；电源模块；散热器；其中，所述控制芯片与所述至少一个运算芯片耦接并用于控制所述至少一个运算芯片的操作，其中，所述电源模块用于向所述至少一个运算芯片、所述控制芯片和/或所述散热器提供电力，以及其中，所述散热器用于给所述至少一个运算芯片、所述控制芯片和/或所述电源模块散热。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1示例性地示出了根据本公开的实施例的标准单元的示意图；
图2示例性地示出了根据本公开的一个具体实施例的用作反相器的标准单元的示意图；
图3示例性地示出了根据本公开的一个具体实施例的用作动态边沿触发寄存器的标准单元的示意图；以及
图4示例性地示出了根据本公开的实施例的数据处理单元、运算芯片和计算设备的示意图。
注意，在以下说明的实施方式中，有时在不同的附图之间共同使用同一附图标记来表示相同部分或具有相同功能的部分，而省略其重复说明。在本说明书中，使用相似的标号和字母表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
为了便于理解，在附图等中所示的各结构的位置、尺寸及范围等有时不表示实际的位置、尺寸及范围等。因此，所公开的发明并不限于附图等所公开的位置、尺寸及范围等。此外，附图不必按比例绘制，一些特征可能被放大以示出具体组件的细节。
具体实施方式
下面将参照附图来详细描述本公开的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本公开的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。也就是说，本文中的结构及方法是以示例性的方式示出，来说明本公开中的结构和方法的不同实施例。然而，本领域技术人员将会理解，它们仅仅说明可以用来实施的本公开的示例性方式，而不是穷尽的方式。此外，附图不必按比例绘制，一些特征可能被放大以示出具体组件的细节。
另外，对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
标准单元是现代系统级芯片(SOC)设计的基础，它可以把一些基础逻辑功能按照例如高度相等、宽度可变等一些原则设计成可拼接的单元，以方便后续通过设计自动化(EDA)工具实现复杂的系统。标准单元的上升延迟时间与下降延迟时间的平衡是衡量标准单元的性能的一项重要指标，其对于时钟网络优化以及减少毛刺(glitch) 功耗都起着重要作用。在很多情况下，实现上升延迟时间与下降延迟时间的平衡可以意味着使得上升延迟时间与下降延迟时间基本相同。
在标准单元的电路设计中，通常都会将各个晶体管的沟道长度设置为最小特征尺寸，以获得最好的性能。以传统的平面CMOS(互补金属氧化物半导体，Complementary Metal-Oxide-Semiconductor)工艺为例，在沟道长度固定的前提下，为了获得上升延迟时间与下降延迟时间的较好的平衡，一般是通过调节PMOS(P型金属氧化物半导体，P-type Metal-Oxide-Semiconductor)晶体管与NMOS(N型金属氧化物半导体，N-type Metal-Oxide-Semiconductor)晶体管的沟道宽度来实现。但是，对沟道宽度的这种调整会导致晶体管的尺寸和功耗增加，从而导致标准单元的尺寸和功耗增加。此外，对沟道宽度的调整在很多情况下并不适用。例如，在FinFET(鳍式场效应晶体管，Fin Field-Effect Transistor)工艺中，可调节的参数是晶体管的Fin(鳍)的个数，因此通常只有几个固定的整数值可选。特别是在一些高密度的标准单元库中，Fin的个数完全固定不可调整，这使得上升延迟时间与下降延迟时间的平衡的优化非常困难。
为了解决上述问题，本发明提出了采用混合阈值技术的数字标准单元，其中可以采用不同阈值类型的晶体管，从而使得能够在各种情况下实现对标准单元的上升延迟时间与下降延迟时间的平衡的调节。现有的标准单元库是可复用IP库中最基本的一种，其可以由Foundry(半导体制造厂家)或第三方IP供应商提供。Foundry或第三方IP供应商一般只提供针对特定工艺的初级标准单元库，这种初级标准单元库中的标准单元针对众多客户的通用需求而设计，采用单一阈值类型。在此基础上，客户可以自行设计或改进标准单元，作为对初级标准单元库的补充，只要客户自行设计或改进的标准单元符合Foundry的设计规则，就可由Foundry来生产。基于此，本发明提出的采用混合阈值技术的标准单元可以由用户自行设计并通过Foundry来生产。由于在Foundry提供的初级标准单元库中，一般一个库内的标准单元只用到一种阈值类型的器件，因此可以区分普通阈值RVT库、低阈值LVT库、超低阈值SVLT库等。与此不同，本发明提出的采用混合阈值技术的标准单元会在一个标准单元中采用不同阈值类型的器件，因此并不属于现有的以阈值类型区分的库，而是可以根据其它标准分类成相应的标准单元库。
以现有的某一FinFET工艺的标准单元设计为例，其中提供普通阈值RVT类型、低阈值LVT类型、超低阈值SVLT类型等不同阈值类型的器件。由于设计规则的限制，高密度的标准单元设计中器件的Fin的个数固定为2。在通常的标准单元设计中，对于简单的反相器电路，NMOS和PMOS晶体管会同时使用此工艺中的超低阈值SLVT类型 的器件，而本发明提出，可对NMOS晶体管用超低阈值SLVT类型的器件，而对PMOS晶体管采用低阈值LVT类型的器件，从而实现上升延迟时间与下降延迟时间的平衡。以下将详细描述根据本公开的具体实施例。
图1示例性地示出了根据本公开的实施例的用于系统级芯片设计的标准单元100的示意图，该标准单元100包括多个半导体器件并且用于实现基础逻辑功能。如图1所示，标准单元100的多个半导体器件包括：第一阈值类型的第一晶体管110以及第二阈值类型的第二晶体管120。其中，第一阈值类型的阈值范围与第二阈值类型的阈值范围不同。
在根据本公开的实施例中，不同的阈值类型可以由不同的沟道掺杂浓度来实现。例如，在标准单元100中，第一阈值类型的晶体管110的沟道可以具有第一掺杂浓度，第二阈值类型的晶体管120的沟道可以具有与第一掺杂浓度不同的第二掺杂浓度。沟道掺杂浓度对于晶体管阈值而言是决定性的因素，由不同的沟道掺杂浓度实现的不同的阈值类型例如可以包括普通阈值RVT(Regular Vt)类型、低阈值LVT(Low Vt)类型、超低阈值SLVT(Super low Vt)类型和/或高阈值HVT(High Vt)类型等等。在标准单元100中，第一阈值类型或第二阈值类型可以选自普通阈值RVT类型、低阈值LVT类型、超低阈值SLVT类型和/或高阈值HVT类型等等。本领域技术人员将理解，虽然在上文中描述了某几种现有的阈值类型，但根据本公开的实施例不限于此，而是可以采用更多的阈值类型，只要采用该阈值类型有助于实现标准单元的上升延迟时间与下降延迟时间的平衡即可。
在根据本公开的实施例中，第一晶体管110和第二晶体管120可以是以任意工艺制造的任意类型的晶体管，包括但不限于MOS晶体管，并且优选地可以是FinFET晶体管。
在根据本公开的实施例的标准单元100中，通过选择第一阈值类型和第二阈值类型，使得标准单元100的上升延迟时间和下降延迟时间平衡。
在根据本公开的实施例中，上升延迟时间是指，在标准单元的输入端的信号稳定之后，标准单元的输出端的信号变化至其规定上限所需的延迟时间。因此，上升延迟时间可以包括从标准单元的输入端到输出端的路径延迟时间和输出端的信号由低翻转至高的时间。类似地，在根据本公开的实施例中，下降延迟时间是指，在标准单元的输入端的信号稳定之后，标准单元的输出端的信号变化至其规定下限所需的延迟时间。因此，下降延迟时间可以包括从标准单元的输入端到输出端的路径延迟时间和输出端的信号由高翻转至低的时间。
在根据本公开的实施例的标准单元100中，针对不同的半导体工艺以及不同的标准单元电路类型，可以采用不同的阈值类型组合。例如，可以对不同掺杂类型的晶体 管采用不同的阈值类型，也可以对相同掺杂类型的晶体管采用不同的阈值类型。具体而言，在根据本公开的一些实施例中，图1所示的标准单元100中的第一晶体管110是p型晶体管，而第二晶体管120是n型晶体管；在根据本公开的又一些实施例中，图1所示的标准单元100中的第一晶体管110是n型晶体管，而第二晶体管120是p型晶体管；在根据本公开的另一些实施例中，图1所示的标准单元100中的第一晶体管110和第二晶体管120都是p型晶体管；以及，在根据本公开的再一些实施例中，图1所示的标准单元100中的第一晶体管110和第二晶体管120都是n型晶体管。
在采用CMOS工艺的标准单元中，NMOS晶体管通常用于信号的下拉(pull down)，即，当输出信号由高翻转至低时，NMOS晶体管起作用；而PMOS晶体管通常用于信号的上拉(pull up)，即，当输出信号由低翻转至高时，PMOS晶体管起作用。为了实现CMOS标准单元的上升延迟时间与下降延迟时间的平衡，如果半导体工艺和/或标准单元的结构决定了在NMOS晶体管和PMOS晶体管采用同一阈值类型的情况下，NMOS晶体管路径较慢而PMOS晶体管路径较快，则根据本公开的实施例的CMOS标准单元可以将较低阈值的NMOS晶体管与较高阈值的PMOS晶体管组合使用，使得NMOS路径变快并且PMOS路径变慢，从而实现NMOS晶体管路径和PMOS晶体管路径的速度的平衡，进行实现上升延迟时间与下降延迟时间的平衡。反之，如果半导体工艺或标准单元的结构决定了在NMOS晶体管和PMOS晶体管采用同一阈值类型的情况下，NMOS晶体管路径较快而PMOS晶体管路径较慢，则可以将较高阈值的NMOS晶体管与较低阈值的PMOS晶体管组合使用，使得NMOS路径变慢并且PMOS路径变快，从而实现上升延迟时间与下降延迟时间的平衡。
例如，在根据本公开的一些实施例中，标准单元100可以是反相器，其中第一晶体管110和第二晶体管120的栅极连接到标准单元100的输入端，并且第一晶体管110和第二晶体管120的漏极连接到标准单元100的输出端。假设该反相器采用的半导体工艺和标准单元结构决定了在NMOS晶体管和PMOS晶体管采用同一阈值类型的情况下，NMOS晶体管路径较快而PMOS晶体管路径较慢，则在该反相器中，第一晶体管110采用超低阈值SLVT类型的p型晶体管，第二晶体管120采用低阈值LVT类型的n型晶体管，即，实现了较低阈值的PMOS晶体管与较高阈值的NMOS晶体管的组合，使得PMOS路径变快并且NMOS路径变慢，从而实现了标准单元100的上升延迟时间与下降延迟时间的平衡。
在根据本公开的实施例中，标准单元100还可以包括：第三阈值类型的第三晶体管。第三阈值类型的阈值范围与第一阈值类型和第二阈值类型的阈值范围均不相同。在优选的实施例中，可以通过选择第一阈值类型、第二阈值类型和第三阈值类型，使得标准单元100的上升延迟时间和下降延迟时间平衡。在一些实施例中，不同的阈值类型可以通过晶体管 的不同的沟道掺杂浓度来实现，例如，第一阈值类型的晶体管的沟道具有第一掺杂浓度，第二阈值类型的晶体管的沟道具有第二掺杂浓度，第三阈值类型的晶体管的沟道具有第三掺杂浓度，并且第一掺杂浓度、第二掺杂浓度和第三掺杂浓度各不相同。由不同的沟道掺杂浓度实现的不同的阈值类型例如可以包括普通阈值RVT(Regular Vt)类型、低阈值LVT(Low Vt)类型、超低阈值SLVT(Super low Vt)类型和/或高阈值HVT(High Vt)类型等等。在标准单元100中，第一阈值类型、第二阈值类型或第三阈值类型可以选自普通阈值RVT类型、低阈值LVT类型、超低阈值SLVT类型和/或高阈值HVT类型等等。本领域技术人员将理解，虽然在上文中描述了某几种现有的阈值类型，但根据本公开的实施例不限于此，而是可以采用更多的阈值类型，只要采用该阈值类型有助于实现标准单元的上升延迟时间与下降延迟时间的平衡即可。
注意，虽然根据本公开的实施例仅示出了包括两种不同阈值类型的晶体管和包括三种不同阈值类型的晶体管的标准单元，但本领域技术人员将理解，根据本公开的实施例的标准单元可以包括任意多种不同阈值类型的任意多个晶体管。
图2示例性地示出了根据本公开的一个具体实施例的用作反相器的标准单元200的电路图，该标准单元200是图1所示的标准单元100的一个具体示例，因此前述关于标准单元100的描述也可以至少部分地适用于此。参考图2，用作反相器的标准单元200可以包括：第一阈值类型的第一晶体管M1，以及第二阈值类型的第二晶体管M2。在该反相器中，第一晶体管M1和第二晶体管M2的栅极连接到标准单元200的输入端I，第一晶体管M1和第二晶体管M2的漏极连接到标准单元200的输出端O，第一晶体管M1的源极连接到电源VDD，并且第二晶体管M2的源极连接到地GND。其中，第一晶体管M1采用低阈值LVT类型的p型晶体管；第二晶体管M2采用超低阈值SLVT类型的n型晶体管，以使得该反相器的上升延迟时间和下降延迟时间达到平衡。
在现有的用作反相器的标准单元中，通常会为反相器的两个晶体管选择相同的阈值类型，即单一阈值类型设计，但是这会导致上升延迟时间和下降延迟时间的不平衡。原因在于，就超低阈值SLVT类型的器件而言，用于信号的上拉的PMOS晶体管的阈值比用于信号的下拉的NMOS晶体管的阈值要低。如果采用通常的单一阈值类型设计，会使得反相器的上升延迟时间明显小于下降延迟时间，造成标准单元的上升延迟时间与下降延迟时间的平衡较差。同时，由于标准单元的最高运行速度是由最慢路径决定的，较快的PMOS路径并未带来性能的提升，但却带来了动态功耗与漏电增加的代价。
与此不同，在根据本公开的实施例的用作反相器的标准单元200中，用于信号的上拉的第一晶体管M1选用低阈值LVT类型的p型晶体管，用于信号的下拉的第二晶体管 M2选用超低阈值SLVT类型的n型晶体管，从而使得用作反相器的标准单元200的上升延迟时间与下降延迟时间趋于平衡，同时不增加器件个数或尺寸，并且可以降低动态功耗与漏电。即，根据本公开的实施例的采用混合阈值技术的标准单元能够在不增加器件尺寸和个数的前提下实现上升延迟时间与下降延迟时间的平衡，并降低动态功耗和漏电，从而提供性能更为优越的标准单元。
图3示例性地示出了作为根据本公开的一个具体实施例的用作动态边沿触发寄存器的标准单元300的电路图，该标准单元300是图1所示的标准单元100的一个具体示例，因此前述关于标准单元100的描述也可以至少部分地适用于此。参考图3，该标准单元300用作动态边沿触发寄存器，其包括依次串联连接在输入端D和输出端Q之间的传输门302、反相器304、传输门306和反相器308。在用作动态边沿触发寄存器的该标准单元300中，包括：第一阈值类型的第一晶体管M1’和M1”，其中第一阈值类型选择为低阈值LVT类型；第二阈值类型的第二晶体管M2’和M2”，其中第二阈值类型选择为超低阈值SLVT类型；以及，第三阈值类型的第三晶体管M3、M4、M3’和M4’，其中第三阈值类型选择为普通阈值RVT类型。在传输门302中，p型的第三晶体管M3的栅极连接到时钟信号CLKP，n型的第三晶体管M4的栅极连接到时钟信号CLKN；与此相反，在传输门306中，p型的第三晶体管M3’的栅极连接到时钟信号CLKN，n型的第三晶体管M4’的栅极连接到时钟信号CLKP，其中，时钟信号CLKN和CLKP是互为反相的时钟信号。
参考图3，在用作动态边沿触发寄存器的该标准单元300中，反相器304和308采用图2中所示的反相器的结构，即，用于信号的上拉的第一晶体管M1’和M1”选用低阈值LVT类型的p型晶体管，用于信号的下拉的第二晶体管M2’和M2”选用超低阈值SLVT类型的n型晶体管，从而使得反相器304和308各自的上升延迟时间与下降延迟时间达到平衡。
继续参考图3，由于传输门302和306并不涉及信号的上拉或下拉，因此在传输门中的p型晶体管和n型晶体管可以采用同一阈值类型。具体而言，在用作动态边沿触发寄存器的该标准单元300中，传输门302由普通阈值RVT类型的p型的第三晶体管M3和n型的第三晶体管M4组成，传输门306由普通阈值RVT类型的p型的第三晶体管M3’和n型的第三晶体管M4’组成。并且，通过为传输门302和306中的p型晶体管和n型晶体管都选择普通阈值RVT类型，能够在不影响延迟时间的平衡的同时增强传输门302和306的驱动能力。
在根据本公开的实施例的用作动态边沿触发寄存器的标准单元300中，通过合理地 采用混合阈值设计，能够在不增加器件尺寸和个数的前提下，实现上升延迟时间与下降延迟时间的平衡、降低动态功耗和漏电并增强驱动能力，从而提供性能更为优越的标准单元。
图4示例性地示出了根据本公开的实施例的数据处理单元、运算芯片和计算设备的示意图。
根据本公开的实施例，还提供一种数据处理单元402。参考图4，该数据处理单元402包括至少一个如前文中所述的标准单元100。在一些实施例中，该数据处理单元402可以同时包括如本申请的图1中所示的采用混合阈值技术的标准单元100和传统的采用单一阈值类型的标准单元。数据处理单元402可以用于实现较为简单的数据处理功能，例如其可以是加法器、乘法器等等。本领域技术人员将理解，虽然图4中所示的数据处理单元402是计算设备400的一部分，但该数据处理单元402也可以作为独立的部件单独使用。
根据本公开的实施例，还提供一种运算芯片404。参考图4，该运算芯片404包括至少一个如前文中所述的数据处理单元402。运算芯片404可以用于实现较为复杂的运算功能，例如可以实现某种算法(诸如散列算法)。本领域技术人员将理解，虽然图4中所示的运算芯片404是计算设备400的一部分，但运算芯片404也可以作为独立的部件单独使用。
根据本公开的实施例，还提供一种计算设备400，其可以用于执行挖掘虚拟数字货币的算法。参考图4，该计算设备400可以包括：至少一个如前文中所述的运算芯片404；控制芯片406；电源模块408；以及散热器410。其中，控制芯片406与至少一个运算芯片404耦接；电源模块408可用于向至少一个运算芯片404、控制芯片406和/或散热器410提供电力；散热器410可用于给至少一个运算芯片404、控制芯片406和/或电源模块408散热。在优选的实施例中，计算设备400例如可以用于执行挖掘比特币的散列算法。
在说明书及权利要求中的词语“前”、“后”、“顶”、“底”、“之上”、“之下”等，如果存在的话，用于描述性的目的而并不一定用于描述不变的相对位置。应当理解，这样使用的词语在适当的情况下是可互换的，使得在此所描述的本公开的实施例，例如，能够在与在此所示出的或另外描述的那些取向不同的其它取向上操作。
如在此所使用的，词语“示例性的”意指“用作示例、实例或说明”，而不是作为将被精确复制的“模型”。在此示例性描述的任意实现方式并不一定要被解释为比其它实现方式优选的或有利的。而且，本公开不受在技术领域、背景技术、发明内容 或具体实施方式中所给出的任何所表述的或所暗示的理论所限定。
如在此所使用的，词语“基本”意指包含由设计或制造的缺陷、器件或元件的容差、环境影响和/或其它因素所致的任意微小的变化。词语“基本”还允许由寄生效应、噪声以及可能存在于实际的实现方式中的其它实际考虑因素所致的与完美的或理想的情形之间的差异。
另外，本文的描述可能提及了被“连接”或“耦接”在一起的元件或节点或特征。如在此所使用的，除非另外明确说明，“连接”意指一个元件/节点/特征与另一种元件/节点/特征在电学上、机械上、逻辑上或以其它方式直接地连接(或者直接通信)。类似地，除非另外明确说明，“耦接”意指一个元件/节点/特征可以与另一元件/节点/特征以直接的或间接的方式在机械上、电学上、逻辑上或以其它方式连结以允许相互作用，即使这两个特征可能并没有直接连接也是如此。也就是说，“耦接”意图包含元件或其它特征的直接连结和间接连结，包括利用一个或多个中间元件的连接。
另外，仅仅为了参考的目的，还可以在本文中使用“第一”、“第二”等类似术语，并且因而并非意图限定。例如，除非上下文明确指出，否则涉及结构或元件的词语“第一”、“第二”和其它此类数字词语并没有暗示顺序或次序。
还应理解，“包括/包含”一词在本文中使用时，说明存在所指出的特征、整体、步骤、操作、单元和/或组件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元和/或组件以及/或者它们的组合。
在本公开中，术语“提供”从广义上用于涵盖获得对象的所有方式，因此“提供某对象”包括但不限于“购买”、“制备/制造”、“布置/设置”、“安装/装配”、和/或“订购”对象等。
本领域技术人员应当意识到，在上述操作之间的边界仅仅是说明性的。多个操作可以结合成单个操作，单个操作可以分布于附加的操作中，并且操作可以在时间上至少部分重叠地执行。而且，另选的实施例可以包括特定操作的多个实例，并且在其它各种实施例中可以改变操作顺序。但是，其它的修改、变化和替换同样是可能的。因此，本说明书和附图应当被看作是说明性的，而非限制性的。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。在此公开的各实施例可以任意组合，而不脱离本公开的精神和范围。本领域的技术人员还 应理解，可以对实施例进行多种修改而不脱离本公开的范围和精神。本公开的范围由所附权利要求来限定。

Claims (10)

  1. 一种用于系统级芯片设计的标准单元，包括多个半导体器件并且用于实现基础逻辑功能，其中，所述多个半导体器件包括：
    第一阈值类型的第一晶体管；以及
    第二阈值类型的第二晶体管；
    其中，第一阈值类型的阈值范围与第二阈值类型的阈值范围不同。
  2. 根据权利要求1所述的标准单元，其中，其中，通过选择第一阈值类型和第二阈值类型，使得所述标准单元的上升延迟时间和下降延迟时间平衡。
  3. 根据权利要求1所述的标准单元，其中，所述多个半导体器件还包括：
    第三阈值类型的第三晶体管，
    其中，第三阈值类型的阈值范围与第一阈值类型和第二阈值类型的阈值范围均不相同，以及
    其中，通过选择第一阈值类型、第二阈值类型和第三阈值类型，使得所述标准单元的上升延迟时间和下降延迟时间平衡。
  4. 根据权利要求1或3所述的标准单元，其中，其中，第一阈值类型、第二阈值类型或第三阈值类型选自以下：普通阈值RVT类型，低阈值LVT类型，超低阈值SLVT类型，高阈值HVT类型。
  5. 根据权利要求1所述的标准单元，其中，
    其中，第一晶体管是n型晶体管，并且第二晶体管是p型晶体管；或者
    其中，第一晶体管是p型晶体管，并且第二晶体管是n型晶体管。
  6. 根据权利要求1所述的标准单元，其中，其中，第一晶体管和第二晶体管都是n型晶体管或者都是p型晶体管。
  7. 根据权利要求1所述的标准单元，其中，其中，所述标准单元是反相器，所述第 一晶体管是低阈值LVT类型的p型晶体管，所述第二晶体管是超低阈值SLVT类型的n型晶体管，所述第一晶体管和所述第二晶体管的栅极连接到所述标准单元的输入端，所述第一晶体管和所述第二晶体管的漏极连接到所述标准单元的输出端。
  8. 一种数据处理单元，其中，包括至少一个根据权利要求1至7中任意一项所述的标准单元。
  9. 一种运算芯片，其中，包括至少一个根据权利要求7所述的数据处理单元。
  10. 一种计算设备，其中，所述计算设备用于执行挖掘虚拟数字货币的算法，并且包括：
    至少一个根据权利要求9所述的运算芯片；
    控制芯片；
    电源模块；
    散热器；
    其中，所述控制芯片与所述至少一个运算芯片耦接并用于控制所述至少一个运算芯片的操作，
    其中，所述电源模块用于向所述至少一个运算芯片、所述控制芯片和/或所述散热器提供电力，以及
    其中，所述散热器用于给所述至少一个运算芯片、所述控制芯片和/或所述电源模块散热。
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