WO2022022017A1 - 半导体器件的制备方法及半导体器件 - Google Patents

半导体器件的制备方法及半导体器件 Download PDF

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Publication number
WO2022022017A1
WO2022022017A1 PCT/CN2021/094445 CN2021094445W WO2022022017A1 WO 2022022017 A1 WO2022022017 A1 WO 2022022017A1 CN 2021094445 W CN2021094445 W CN 2021094445W WO 2022022017 A1 WO2022022017 A1 WO 2022022017A1
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Prior art keywords
layer
shallow trench
active region
etch stop
semiconductor device
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PCT/CN2021/094445
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English (en)
French (fr)
Inventor
张魁
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/599,782 priority Critical patent/US11915967B2/en
Publication of WO2022022017A1 publication Critical patent/WO2022022017A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method for fabricating a semiconductor device and a semiconductor device.
  • STI shallow trench isolation
  • LOCOS Local Oxidation of Silicon
  • a shallow trench is formed in the semiconductor substrate between the active area of the semiconductor (Active Area, which can be used to form, for example, the gate electrode and the source/drain electrode), and the MOSFETs are electrically isolated from each other.
  • Shallow trenches are filled with insulating material, such as silicon oxide, to provide electrical isolation.
  • the depth of the WL trench formed in the active region and the STI is different, so that the metal gate of the formed WL is deposited.
  • the depth of the bottom of the WL trench is different, which causes the metal gate in the STI to be easily coupled with the active region and the adjacent gate to form parasitic capacitance, which in turn leads to the occurrence of leakage current.
  • the bottom depth of the metal gate is different, which also elongates the effective length of the wire and increases the wire resistance.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a preparation method of a semiconductor device and a semiconductor device.
  • An embodiment of the present disclosure provides a method for fabricating a semiconductor device, the method comprising: providing a semiconductor substrate, the semiconductor substrate including a shallow trench and an active region isolated from the shallow trench; An oxygen-containing layer is formed on the exposed outer surface of the trench and the active region; a first sacrificial layer with a set height is filled in the shallow trench whose surface includes the oxygen-containing layer, and the set height is lower than the set height height of the active area; forming an etch stop layer on the upper surface of the first sacrificial layer; removing the first sacrificial layer under the etch stop layer to form an air space; in the shallow trench An isolation layer is filled on the etch stop layer to form a shallow trench isolation structure including the air space; the active region and the shallow trench isolation structure are etched to form a word line trench, wherein The bottom of the word line trench in the shallow trench isolation structure is higher than the set height.
  • the thickness of the etch stop layer is in the range of 2 nm to 10 nm.
  • the bottoms of the wordline trenches in the shallow trench isolation structure and the bottoms of the wordline trenches in the active region are both connected to the bottom of the etch stop layer.
  • the top surface is flush.
  • forming an etch stop layer on the upper surface of the first sacrificial layer includes: forming an etch stop layer on the upper surface of the first sacrificial layer and the surface corresponding to the active region The exposed outer surface of the oxygen-containing layer forms an etch stop layer.
  • removing the first sacrificial layer under the etch stop layer to form an air space includes: forming an etch hole in the shallow trench, and the etching An etching hole penetrates the etching stop layer; an etching solution is poured into the first sacrificial layer through the etching hole, and the first sacrificial layer below the etching stop layer is wet-etched.
  • forming an etch hole in the shallow trench includes: filling a second sacrificial layer on the etch stop layer in the shallow trench, the first The upper surfaces of the two sacrificial layers are flush with the upper surface of the active region; a patterned mask layer is formed over the second sacrificial layer and the active region, and the mask layer is on the semiconductor A through hole exposing the second sacrificial layer is formed in the edge region of the substrate; using the mask layer as a mask, etching the second sacrificial layer to form an etching hole connecting the through hole, and the etching A hole penetrates the etch stop layer; the mask layer is removed.
  • the oxygen-containing layer includes a linear oxide layer, an oxide layer and a nitride layer stack structure, and at least one of an oxide layer, a nitride layer, and an oxide layer stack structure .
  • the material of the first sacrificial layer includes oxide, ethyl orthosilicate, spin-coated organic carbon, amorphous carbon, photoresist, and silicon-containing polymer materials. at least one.
  • the isolation layer includes an oxide layer, a stacked structure of oxide layers and nitride layers, and at least one of an oxide layer, a nitride layer, and a stacked structure of oxide layers.
  • the method further includes forming a word line structure within the word line trench, the word line structure including a gate oxide layer, a barrier layer, a conductive layer, and a word line Protective cover.
  • the material of the etch stop layer includes at least one of silicon nitride, silicon carbonitride, and silicon oxycarbonitride.
  • Embodiments of the present disclosure provide a semiconductor device, the semiconductor device comprising: a semiconductor substrate including: a shallow trench; and an active region isolated by the shallow trench; wherein, at the bottom of the shallow trench and the surface of the active region includes an oxygen-containing layer; an etch stop layer is provided above the set height of the shallow trench, the etch stop layer and the shallow trench form an air space, the set height A certain height is lower than the height of the active region; in the shallow trench there is a shallow trench isolation structure including the air space above the etch stop layer, and the shallow trench isolation structure is filled with an isolation layer A word line trench is included in the shallow trench isolation structure and the active region, and the bottom of the word line trench in the shallow trench isolation structure is higher than the set height.
  • the thickness of the etch stop layer is in the range of 2 nm to 10 nm.
  • the bottoms of the wordline trenches in the shallow trench isolation structure and the bottoms of the wordline trenches in the active region are both connected to the bottom of the etch stop layer.
  • the top surface is flush.
  • a surface of the oxygen-containing layer corresponding to the active region includes the etch stop layer.
  • an edge region of the semiconductor substrate includes an etch hole penetrating the etch stop layer, and the etch hole fills the isolation layer.
  • an etch stop layer is provided at a set height of the first sacrificial layer in the shallow trench, so that the formation of the semiconductor device is formed during subsequent etching.
  • the etching stop layer can prevent the WL trench from continuing to etch in the STI, so that a WL trench whose depth is approximately the same as that of the WL trench in the active region can be formed in the STI structure.
  • the depth of the formed WL trench in the active region and the STI structure is approximately the same, the depth of the bottom of the metal gate of the WL word line subsequently formed in the active region and the STI structure can be approximated in the semiconductor substrate Similarly, a nearly straight straight line can be formed, so that the parasitic capacitance formed between the WL in the STI structure and the active region and the adjacent WL can be improved, and the occurrence of leakage current can be reduced.
  • the length of WL can also be shortened and the conduction resistance can be reduced.
  • an air gap air gap
  • FIG. 1 schematically shows a flow chart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure
  • 2-28 are schematic flowcharts of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • FIG. 1 schematically shows a flow chart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.
  • the method provided by the embodiment of the present disclosure may include the following steps.
  • step S110 a semiconductor substrate is provided, and the semiconductor substrate includes a shallow trench and an active region isolated from the shallow trench.
  • Embodiments of the present disclosure provide a semiconductor substrate, which can be used to provide an operating platform for subsequent processes.
  • the semiconductor substrate can be any substrate used to carry the components of the semiconductor integrated circuit, which can be a bare chip or a wafer processed by an epitaxial growth process.
  • the semiconductor substrate may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate Or a combination of any one or more of germanium-on-insulator substrates and the like.
  • the active region (active region) is used to establish the position of the transistor body, on which the source, drain and gate are formed, and the two active regions are separated by STI.
  • step S120 an oxygen-containing layer is formed on the exposed outer surface of the shallow trench and the active region.
  • the oxygen-containing layer may include a liner oxide, an oxide layer and a nitride layer stack structure (oxide/nitride), an oxide layer, a nitride layer and an oxide layer stack structure (ONO structure) and the like at least one.
  • the linear oxide layer may be, for example, an oxide layer formed in a high-temperature furnace tube.
  • the oxide layer and nitride layer stack structure refers to stacking a nitride layer on top of an oxide layer, and another oxide layer can be stacked on top of this nitride layer, and so on.
  • the structure is formed by stacking layers and nitride layers layer by layer, and the present disclosure does not limit parameters such as the number of layers of oxide layers and nitride layers, layer thicknesses, and the like.
  • the oxide layer, the nitride layer and the oxide layer stack structure refer to a structure comprising at least one stacked oxide layer, a nitride layer and an oxide layer, each oxide layer, nitride layer and oxide layer structure including a stack of sequentially oxide layer, nitride layer and oxide layer.
  • step S130 a first sacrificial layer with a set height is filled in the shallow trench whose surface includes the oxygen-containing layer, and the set height is lower than the height of the active region.
  • the material of the first sacrificial layer may include oxide (oxide), Tetraethyl orthosilicate (TEOS), spin-on organic carbon, amorphous carbon, photoresist, and silicon-containing At least one of polymer materials and the like.
  • oxide oxide
  • TEOS Tetraethyl orthosilicate
  • spin-on organic carbon amorphous carbon
  • photoresist and silicon-containing At least one of polymer materials and the like.
  • the method may further include: setting the set height according to the depth of the word line trench in the active region.
  • the value range of the set height may be, for example, 100-160 nm, but the present disclosure is not limited to this, and the setting of the set height depends on the active region
  • the depth of the word lines formed in the active region depends on the depth of the word line trenches in the active region.
  • step S140 an etch stop layer is formed on the upper surface of the first sacrificial layer.
  • the thickness of the etch stop layer may be in the range of 2 nm to 10 nm.
  • the thickness of the etch stop layer can be set to be any one of 2 nm, 4 nm, 5 nm, 8 nm, 9 nm, or 10 nm.
  • the present disclosure is not limited to this, and can be selected according to actual needs.
  • forming an etch stop layer on the upper surface of the first sacrificial layer may include: exposing the oxygen-containing layer on the upper surface of the first sacrificial layer and corresponding to the active region The outer surface of the etch stop layer is formed.
  • the material of the etch stop layer may include at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiCON), and the like.
  • the etch stop layer may also be referred to as an etch stop layer.
  • step S150 the first sacrificial layer under the etch stop layer is removed to form an air space.
  • removing the first sacrificial layer under the etch stop layer to form an air space may include: forming an etch hole in the shallow trench, the etch hole passing through the The etch stop layer is poured into the first sacrificial layer through the etching hole, and the first sacrificial layer below the etch stop layer is wet-etched.
  • forming an etch hole in the shallow trench may include: filling a second sacrificial layer on the etch stop layer in the shallow trench, and the second sacrificial layer is the upper surface is flush with the upper surface of the active region; a patterned mask layer is formed over the second sacrificial layer and the active region, and the mask layer is at the edge of the semiconductor substrate A through hole exposing the second sacrificial layer is formed in the area; using the mask layer as a mask, etching the second sacrificial layer to form an etching hole connecting the through hole, and the etching hole penetrates the Etch stop layer; remove the mask layer.
  • the material of the second sacrificial layer may include oxide, Tetraethyl orthosilicate (TEOS), spin-on organic carbon, amorphous carbon, photoresist, and silicon-containing At least one of polymer materials and the like.
  • TEOS Tetraethyl orthosilicate
  • spin-on organic carbon amorphous carbon
  • photoresist amorphous carbon
  • silicon-containing At least one of polymer materials and the like.
  • step S160 an isolation layer is filled on the etch stop layer in the shallow trench to form a shallow trench isolation structure including the air space.
  • the second sacrificial layer and the first sacrificial layer can be filled above and below the etch stop layer in the shallow trench, respectively, and then a small amount of etch holes can be etched at the edge of the active region to pass through the etch.
  • the etch stop layer through wet etching, removes the first sacrificial layer under the etch stop layer in the STI structure to form an air gap, and simultaneously removes the second sacrificial layer filled above the etch stop layer in the shallow trench, and then An isolation layer can be filled over the etch stop layer containing the air gap to form the STI structure containing the air gap.
  • the isolation layer may include an oxide layer (oxide), an oxide layer and a nitride layer stack structure (oxide/nitride), an oxide layer, a nitride layer and an oxide layer stack structure (ONO structure) and so on.
  • step S170 the active region and the shallow trench isolation structure are etched to form a word line trench, wherein the bottom of the word line trench in the shallow trench isolation structure is higher than the setting high.
  • the method may further include forming a wordline structure within the wordline trench, the wordline structure including a gate oxide layer, a barrier layer, a conductive layer, and a wordline capping layer.
  • the bottoms of the wordline trenches within the shallow trench isolation structure and the bottoms of the wordline trenches within the active region may both be flush with the upper surface of the etch stop layer .
  • photomask etching can be used to form WL trenches in the active region and the STI structure, respectively, because the depth of the word line in the active region was used as a reference to set the set height of the first sacrificial layer before. , and then an etch stop layer is formed on the first sacrificial layer of the set height. Therefore, it can prevent the problem that the depth of the word line trench in the STI structure is too deep due to the etch selection ratio, so that the The depths of the word line trenches in the active region and the STI structure are similar.
  • the depths of the word line trenches in the active region and the STI structure can be made the same, that is, the bottom of the word line trench in the active region and the bottom of the word line trench in the STI structure are the same as the etched depth.
  • the upper surface of the stop layer is flush, so that in subsequent processes, the depth of the word lines in the active region and the STI structure is the same.
  • an etch stop layer is provided at the set height of the first sacrificial layer in the shallow trench, so that the WL is formed in the subsequent etching.
  • the etch stop layer can prevent the WL trench from continuing to etch in the STI, so that a WL trench whose depth is approximately the same as the depth of the WL trench in the active region can be formed in the STI structure.
  • the depth of the formed WL trench in the active region and the STI structure is approximately the same, the depth of the bottom of the metal gate of the WL word line subsequently formed in the active region and the STI structure can be approximated in the semiconductor substrate Similarly, a nearly straight straight line can be formed, so that the parasitic capacitance formed between the WL in the STI structure and the active region and the adjacent WL can be improved, and the occurrence of leakage current can be reduced.
  • the length of WL can also be shortened and the conduction resistance can be reduced.
  • an air gap air gap
  • the semiconductor substrate includes a shallow trench 1 and an active region 2 isolated from the shallow trench.
  • a vertical direction ie, the extension direction of AA in the top view in FIG. 2
  • a lateral direction not shown, that is, along the direction from the top view in FIG. Left to right horizontal direction
  • the vertical direction can be defined as the extension direction of the word line (not shown) or the bit line.
  • the extension direction (such as the extension direction of BB in FIG. 2 in the top view) is a direction at a certain angle, and the transverse direction is the direction perpendicular to the longitudinal direction.
  • the longitudinal direction may also be defined as the same direction as the extension direction of the word lines or the extension direction of the bit lines, and the direction in which the transverse direction and the longitudinal direction intersect vertically.
  • Fig. 3 is a cross-sectional view taken along the AA direction of Fig. 2
  • Fig. 4 is a cross-sectional view taken along the BB direction of Fig. 2.
  • the BB direction intersects with the AA direction, which may be the extension direction of the active region.
  • an oxygen-containing layer 3 such as a liner oxide, oxide/nitride or ONO structure, is formed on the exposed outer surfaces of the shallow trench 1 and the active region 2 .
  • 5 is a plan view
  • FIG. 6 is a cross-sectional view along the AA direction of FIG. 5
  • FIG. 7 is a cross-sectional view along the BB direction of FIG. 5 .
  • a first sacrificial layer 4 with a predetermined height is filled in the shallow trench 1 including the oxygen-containing layer 3 on the surface.
  • the first sacrificial layer 4 can be made of oxide, TEOS, spin-coated organic carbon, It is made of any one or more of shaped carbon, photoresist and silicon-containing polymer materials.
  • 8 is a plan view
  • FIG. 9 is a cross-sectional view along the AA direction of FIG. 8
  • FIG. 10 is a cross-sectional view along the BB direction of FIG. 8 .
  • an etch stop layer 5 is formed on the upper surface of the first sacrificial layer 4 and the exposed outer surface of the oxygen-containing layer 3 corresponding to the active region 2 .
  • the etch stop layer 5 can be made of, for example, any one or more materials of SiN, SiCN, SiCON and the like.
  • 11 is a plan view
  • FIG. 12 is a cross-sectional view along the AA direction of FIG. 11
  • FIG. 13 is a cross-sectional view along the BB direction of FIG. 11 .
  • a second sacrificial layer 6 is deposited on the etch stop layer 5 in the shallow trench, and the upper surface of the second sacrificial layer 6 is flush with the upper surface of the active region 2 .
  • the second sacrificial layer 6 can be made of, for example, any one or more materials selected from oxide, TEOS, spin-coated organic carbon, amorphous carbon, photoresist, and silicon-containing polymer materials.
  • 14 is a top view
  • FIG. 15 is a cross-sectional view along the AA direction of FIG. 14
  • FIG. 16 is a cross-sectional view along the BB direction of FIG. 14 .
  • the mask layer is formed with through-holes exposing the second sacrificial layer 6 in the edge region of the semiconductor substrate.
  • FIG. 17 is a plan view
  • FIG. 18 is a cross-sectional view along the AA direction of FIG. 17
  • FIG. 19 is a cross-sectional view along the BB direction of FIG. 17 .
  • the size of the etching hole 7 is wider than the width of the active region 2 and smaller than the distance between adjacent active regions 2 .
  • the etching holes 7 can be arranged at the edge of the memory cell array region formed by the active region 2 .
  • an isolation layer 9 is filled on the etch stop layer 5 in the shallow trench 1 to form an STI structure including an air spacer 8, and the etch hole 7 at the edge of the active region 2 is also isolated Layer 9 fill.
  • the isolation layer 9 can be formed, for example, by depositing oxide or an oxide/nitride or ONO structure.
  • 20 is a top view
  • FIG. 21 is a cross-sectional view of FIG. 20 along the AA direction
  • FIG. 22 is a cross-sectional view of FIG. 20 along the BB direction.
  • the mask etches the active region 2 and the shallow trench isolation structure including the air spacers 8 to form word line trenches 10 in the active region and the STI structure, respectively, since the bottom of the STI structure There is an etch stop layer 5, so that the bottom of the word line trench 10 in the shallow trench isolation structure is higher than the above-mentioned set height, that is, when the word line trench 10 in the STI structure is formed by etching, due to the etch stop layer 5
  • the existence of so that the depth of the word line trench 10 in the STI structure does not exceed the etch stop layer 5 , so that the depth of the word line trench in the STI structure and the active region is approximately the same.
  • FIG. 23 is a plan view
  • FIG. 24 is a cross-sectional view along the AA direction of FIG. 23
  • FIG. 25 is a cross-sectional view along the BB direction of FIG. 23 .
  • the gate oxide layer 11 and the barrier layer 13 can be formed in the active region and the word line trench in the STI structure (for example, it can be made of tin, but the present disclosure is not limited to Herein), a conductive layer 14 (for example, can be made of metal tungsten W material, but the present disclosure is not limited to this) and a word line protection cap layer 12 (for example, a nitride can be used) for forming the active area and The WL structure within the STI structure.
  • 26 is a plan view
  • FIG. 27 is a cross-sectional view along the AA direction of FIG. 26
  • FIG. 28 is a cross-sectional view along the BB direction of FIG. 26 .
  • an etch stop layer is provided at the set height of the first sacrificial layer in the shallow trench, so that the WL is formed in the subsequent etching.
  • the etch stop layer can prevent the WL trench from continuing to etch in the STI, so that a WL trench whose depth is approximately the same as the depth of the WL trench in the active region can be formed in the STI structure.
  • the depth of the formed WL trench in the active region and the STI structure is approximately the same, the depth of the bottom of the metal gate of the WL word line subsequently formed in the active region and the STI structure can be approximated in the semiconductor substrate Similarly, a nearly straight straight line can be formed, so that the parasitic capacitance formed between the WL in the STI structure and the active region and the adjacent WL can be improved, and the occurrence of leakage current can be reduced.
  • the length of WL can also be shortened and the conduction resistance can be reduced.
  • an air gap air gap
  • the semiconductor device may be a Dynamic Random Access Memory (DRAM), which is a semiconductor memory device composed of many repeated memory cells, each memory cell usually including a capacitor and a transistor, and the gate of the transistor is It is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or through the bit line Write data information into the capacitor for storage.
  • DRAM Dynamic Random Access Memory
  • inventions of the present disclosure also provide a semiconductor device, and the semiconductor device may include a semiconductor substrate.
  • the semiconductor substrate may further include a shallow trench and an active region isolated from the shallow trench.
  • the bottom of the shallow trench and the surface of the active region may include an oxygen-containing layer.
  • An etch stop layer is provided above a set height of the shallow trench, the etch stop layer and the shallow trench form an air space, and the set height is lower than the height of the active region.
  • the shallow trench there is a shallow trench isolation structure including the air space above the etch stop layer, and the shallow trench isolation structure is filled with an isolation layer.
  • the shallow trench isolation structure and the active region include word line trenches, and the bottom of the word line trench in the shallow trench isolation structure is higher than the set height.
  • an etch stop layer is provided at the set height of the first sacrificial layer in the shallow trench, so that when the WL trench is formed by subsequent etching
  • the etching stop layer can prevent the WL trench from continuing to etch in the STI, so that a WL trench whose depth is approximately the same as the depth of the WL trench in the active region can be formed in the STI structure.
  • the depth of the formed WL trench in the active region and the STI structure is approximately the same, the depth of the bottom of the metal gate of the WL word line subsequently formed in the active region and the STI structure can be approximated in the semiconductor substrate Similarly, a nearly straight straight line can be formed, so that the parasitic capacitance formed between the WL in the STI structure and the active region and the adjacent WL can be improved, and the occurrence of leakage current can be reduced.
  • the length of WL can also be shortened and the conduction resistance can be reduced.
  • an air gap air gap
  • the thickness of the etch stop layer may be in the range of 2 nm to 10 nm.
  • the bottoms of the wordline trenches within the shallow trench isolation structure and the bottoms of the wordline trenches within the active region may both be flush with the upper surface of the etch stop layer .
  • a surface of the oxygen-containing layer corresponding to the active region may include the etch stop layer.
  • the edge region of the semiconductor substrate may include an etch hole through the etch stop layer, the etch hole filling the isolation layer.
  • the material of the first sacrificial layer may include at least one of oxide, ethyl orthosilicate, spin-coated organic carbon, amorphous carbon, photoresist, and silicon-containing polymer material, etc. .
  • a word line structure may be included within the word line trench, and the word line structure may include a gate oxide layer, a barrier layer, a conductive layer, a word line capping layer, and the like.
  • the material of the etch stop layer may include at least one of silicon nitride, silicon carbonitride, silicon oxycarbonitride, and the like.

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Abstract

本公开是关于一种半导体器件的制备方法及半导体器件，涉及半导体技术领域。该方法包括：提供半导体衬底，所述半导体衬底包括浅沟槽及所述浅沟槽隔离出的有源区；在所述浅沟槽及所述有源区暴露的外表面形成含氧层；在表面包括所述含氧层的所述浅沟槽内填充设定高度的第一牺牲层，所述设定高度低于所述有源区的高度；在所述第一牺牲层的上表面形成刻蚀停止层；去除所述刻蚀停止层下方的所述第一牺牲层，以形成空气间隔；在所述浅沟槽中所述刻蚀停止层之上填充隔离层，以形成包含所述空气间隔的浅沟槽隔离结构；刻蚀所述有源区和所述浅沟槽隔离结构，以形成字线沟槽，其中所述浅沟槽隔离结构内的字线沟槽的底部高于所述设定高度。

Description

半导体器件的制备方法及半导体器件
相关申请的交叉引用
本申请要求于2020年07月27日提交的申请号为202010733747.3、名称为“半导体器件的制备方法及半导体器件”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体器件的制备方法及半导体器件。
背景技术
在亚微米技术中，浅沟槽隔离(shallow trench isolation，STI)结构已取代了其它半导体器件隔离方法，例如需要更多宝贵面积的硅局部氧化隔离(Local Oxidation of Silicon，LOCOS)技术。
在浅沟槽隔离工艺中，在半导体有源区(Active Area，例如可以用于形成栅极和源极/漏极)之间的半导体衬底中形成浅沟槽，并使MOSFET彼此电隔离。浅沟槽填充有绝缘材料，例如氧化硅，以提供电绝缘。
相关技术中，在形成WL(wordline，字线)沟槽时，由于刻蚀选择比，导致在有源区与STI中形成的WL沟槽的深度不同，从而使得沉积形成的WL的金属栅极在WL沟槽的底部的深度不同，导致STI中的金属栅极容易与有源区以及邻近的栅极发生耦合作用，形成寄生电容，进而导致漏电流现象的发生。
此外，金属栅极的底部深度不同，同样拉长了导线的有效长度，增加了导线电阻。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种半导体器件的制备方法及半导体器件。
本公开实施例提供一种半导体器件的制备方法，所述方法包括：提供半导体衬底，所述半导体衬底包括浅沟槽及所述浅沟槽隔离出的有源区；在所述浅沟槽及所述有源区暴露的外表面形成含氧层；在表面包括所述含氧层的所述浅沟槽内填充设定高度的第一牺牲层，所述设定高度低于所述有源区的高度；在所述第一牺牲层的上表面形成刻蚀停止层；去除所述刻蚀停止层下方的所述第一牺牲层，以形成空气间隔；在所述浅沟槽中所述刻蚀停止层之上填充隔离层，以形成包含所述空气间隔的浅沟槽隔离结构；刻蚀所述有源区和所述 浅沟槽隔离结构，以形成字线沟槽，其中所述浅沟槽隔离结构内的字线沟槽的底部高于所述设定高度。
在本公开的一种示例性实施例中，所述刻蚀停止层的厚度处于2nm至10nm的范围之内。
在本公开的一种示例性实施例中，所述浅沟槽隔离结构内的字线沟槽的底部和所述有源区内的字线沟槽的底部均与所述刻蚀停止层的上表面齐平。
在本公开的一种示例性实施例中，在所述第一牺牲层的上表面形成刻蚀停止层，包括：在所述第一牺牲层的上表面和对应所述有源区的所述含氧层暴露的外表面，形成刻蚀停止层。
在本公开的一种示例性实施例中，去除所述刻蚀停止层下方的所述第一牺牲层，以形成空气间隔，包括：在所述浅沟槽中形成刻蚀孔，所述刻蚀孔贯穿所述刻蚀停止层；通过所述刻蚀孔灌入刻蚀液至所述第一牺牲层内，湿法刻蚀所述刻蚀停止层下方的所述第一牺牲层。
在本公开的一种示例性实施例中，在所述浅沟槽中形成刻蚀孔，包括：在所述浅沟槽内所述刻蚀停止层之上填充第二牺牲层，所述第二牺牲层的上表面和所述有源区的上表面齐平；在所述第二牺牲层和所述有源区的上方形成图案化的掩膜层，所述掩膜层在所述半导体衬底的边缘区域形成有暴露第二牺牲层的通孔；以所述掩膜层为掩膜，刻蚀所述第二牺牲层形成连通所述通孔的刻蚀孔，且所述刻蚀孔贯穿所述刻蚀停止层；去除所述掩膜层。
在本公开的一种示例性实施例中，所述含氧层包括线形氧化层，氧化物层和氮化物层堆叠结构，氧化物层、氮化物层和氧化物层堆叠结构中的至少一种。
在本公开的一种示例性实施例中，所述第一牺牲层的材料包括氧化物、正硅酸乙酯、旋涂有机碳、不定型碳、光刻胶以及含硅高分子材料中的至少一种。
在本公开的一种示例性实施例中，所述隔离层包括氧化物层，氧化物层和氮化物层堆叠结构，氧化物层、氮化物层和氧化物层堆叠结构中的至少一种。
在本公开的一种示例性实施例中，所述方法还包括：在所述字线沟槽内形成字线结构，所述字线结构包括栅氧化物层、阻挡层、导电层和字线保护盖层。
在本公开的一种示例性实施例中，所述刻蚀停止层的材料包括氮化硅、碳氮化硅和碳氮氧化硅中的至少一种。
本公开实施例提供一种半导体器件，所述半导体器件包括：半导体衬底，其包括：浅沟槽；以及所述浅沟槽隔离出的有源区；其中，在所述浅沟槽的底部和所述有源区的表面包括含氧层；在所述浅沟槽的设定高度之上具有刻蚀停止层，所述刻蚀停止层和所述浅沟槽形成空气间隔，所述设定高度低于所述有源区的高度；所述浅沟槽中所述刻蚀停止层之上具有包含所述空气间隔的浅沟槽隔离结构，所述浅沟槽隔离结构由隔离层填充而成；所述浅沟槽隔离结构和所述有源区内包括字线沟槽，所述浅沟槽隔离结构内的字线沟槽的底部高于所述设定高度。
在本公开的一种示例性实施例中，所述刻蚀停止层的厚度处于2nm至10nm的范围之内。
在本公开的一种示例性实施例中，所述浅沟槽隔离结构内的字线沟槽的底部和所述有源区内的字线沟槽的底部均与所述刻蚀停止层的上表面齐平。
在本公开的一种示例性实施例中，对应所述有源区的所述含氧层的表面包括所述刻蚀停止层。
在本公开的一种示例性实施例中，所述半导体衬底的边缘区域包括贯穿所述刻蚀停止层的刻蚀孔，所述刻蚀孔填充所述隔离层。
本公开一些实施例提供的半导体器件的制备方法，一方面，通过在形成STI过程中，在浅沟槽内的第一牺牲层的设定高度处设置一刻蚀停止层，使得在后续刻蚀形成WL沟槽时，通过该刻蚀停止层可以阻止WL沟槽在STI中继续刻蚀，从而使得能够在STI结构内形成一与有源区的WL沟槽深度接近一致的WL沟槽。由于形成的WL沟槽在有源区与STI结构中的深度近似相同，进而可以使得后续在有源区和STI结构内形成的WL字线的金属栅极的底部在半导体衬底内的深度近似相同，可以形成一条接近平直的直线，从而可以改善STI结构中的WL与有源区及邻近的WL之间形成的寄生电容，减小漏电流发生。同时，也可以缩短WL的长度，减小导电电阻。另一方面，通过在STI结构的下部形成空气间隔(air gap)，可以使得隔离效果更好，可以进一步起到减小寄生电容的作用。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出了根据本公开的一实施例的半导体器件的制备方法的流程图；
图2-28示意性示出了根据本公开的一实施例的半导体器件的制备方法的流程示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”仅作为标记使用，不是对其对象的数量限制。
图1示意性示出了根据本公开的一实施例的半导体器件的制备方法的流程图。
如图1所示，本公开实施例提供的方法可以包括以下步骤。
在步骤S110中，提供半导体衬底，所述半导体衬底包括浅沟槽及所述浅沟槽隔离出的有源区。
本公开实施例，提供一半导体衬底，可以用于为后续工艺提供操作平台。半导体衬底可以采用任何用以承载半导体集成电路组成元件的底材，可以是裸片，也可以是经过外延生长工艺处理后的晶圆。半导体衬底例如可以是绝缘体上硅(silicon-on-insulator，SOI)基底、体硅(bulk silicon)基底、锗基底、锗硅基底、磷化铟(InP)基底、砷化镓(GaAs)基底或者绝缘体上锗基底等中的任意一种或者多种的组合。
其中，有源区(有源区)是用来建立晶体管主体的位置所在，在其上形成源、漏和栅极，两个有源区之间以STI来做隔离。
在步骤S120中，在所述浅沟槽及所述有源区暴露的外表面形成含氧层。
在示例性实施例中，所述含氧层可以包括线形氧化层(liner oxide)，氧化物层和氮化物层堆叠结构(oxide/nitride)，氧化物层、氮化物层和氧化物层堆叠结构(ONO结构)等中的至少一种。
其中，线形氧化层例如可以为在高温炉管中形成的氧化层。氧化物层和氮化物层堆叠结构是指在一层氧化物层之上堆叠一层氮化物层，在该层氮化物层之上可以再堆叠另一层氧化物层，以此类推，氧化物层和氮化物层层层堆叠而成的结构，本公开不对氧化物层、氮化物层的层数量、层厚度等参数进行限定。氧化物层、氮化物层和氧化物层堆叠结构是指包括至少一个堆叠的氧化物层、氮化物层和氧化物层结构，每个氧化物层、氮化物层和氧化物层结构包括依次堆叠的氧化物层、氮化物层和氧化物层。
在步骤S130中，在表面包括所述含氧层的所述浅沟槽内填充设定高度的第一牺牲层，所述设定高度低于所述有源区的高度。
在示例性实施例中，所述第一牺牲层的材料可以包括氧化物(oxide)、正硅酸乙酯 (Tetraethyl orthosilicate，TEOS)、旋涂有机碳、不定型碳、光刻胶以及含硅高分子材料等中的至少一种。
在示例性实施例中，所述方法还可以包括：根据所述有源区内的字线沟槽的深度设置所述设定高度。
本公开实施例中，从浅沟槽底部起，所述设定高度的取值范围例如可以是100-160nm，但本公开并不限定于此，设定高度的设置取决于要在有源区内形成的字线的深度，有源区内字线的深度又取决于有源区内的字线沟槽的深度。
在步骤S140中，在所述第一牺牲层的上表面形成刻蚀停止层。
在示例性实施例中，所述刻蚀停止层的厚度可以处于2nm至10nm的范围之内。例如，可以设置刻蚀停止层的厚度为2nm，4nm，5nm，8nm，9nm或者10nm等中的任意一个。但本公开并不限定于此，可以根据实际需求进行选择。
在示例性实施例中，在所述第一牺牲层的上表面形成刻蚀停止层，可以包括：在所述第一牺牲层的上表面和对应所述有源区的所述含氧层暴露的外表面，形成刻蚀停止层。
在示例性实施例中，所述刻蚀停止层的材料可以包括氮化硅(SiN)、碳氮化硅(SiCN)和碳氮氧化硅(SiCON)等中的至少一种。刻蚀停止层也可以称之为刻蚀终止层。
在步骤S150中，去除所述刻蚀停止层下方的所述第一牺牲层，以形成空气间隔。
在示例性实施例中，去除所述刻蚀停止层下方的所述第一牺牲层，以形成空气间隔，可以包括：在所述浅沟槽中形成刻蚀孔，所述刻蚀孔贯穿所述刻蚀停止层；通过所述刻蚀孔灌入刻蚀液至所述第一牺牲层内，湿法刻蚀所述刻蚀停止层下方的所述第一牺牲层。
在示例性实施例中，在所述浅沟槽中形成刻蚀孔，可以包括：在所述浅沟槽内所述刻蚀停止层之上填充第二牺牲层，所述第二牺牲层的上表面和所述有源区的上表面齐平；在所述第二牺牲层和所述有源区的上方形成图案化的掩膜层，所述掩膜层在所述半导体衬底的边缘区域形成有暴露第二牺牲层的通孔；以所述掩膜层为掩膜，刻蚀所述第二牺牲层形成连通所述通孔的刻蚀孔，且所述刻蚀孔贯穿所述刻蚀停止层；去除所述掩膜层。
在示例性实施例中，所述第二牺牲层的材料可以包括氧化物(oxide)、正硅酸乙酯(Tetraethyl orthosilicate，TEOS)、旋涂有机碳、不定型碳、光刻胶以及含硅高分子材料等中的至少一种。
在步骤S160中，在所述浅沟槽中所述刻蚀停止层之上填充隔离层，以形成包含所述空气间隔的浅沟槽隔离结构。
具体地，可以先在浅沟槽内的刻蚀停止层的上方和下方分别填充满第二牺牲层和第一牺牲层后，再在有源区的边缘部位刻蚀少量刻蚀孔穿过刻蚀停止层，通过湿法刻蚀，去除STI结构内刻蚀停止层下方的第一牺牲层，形成air gap，同时去除浅沟槽内的刻蚀停止层的上方填充的第二牺牲层，之后可以再在包含air gap的刻蚀停止层之上填充隔离层，用于形成包含air gap的STI结构。
在示例性实施例中，所述隔离层可以包括氧化物层(oxide)，氧化物层和氮化物层堆 叠结构(oxide/nitride)，氧化物层、氮化物层和氧化物层堆叠结构(ONO结构)等中的至少一种。
在步骤S170中，刻蚀所述有源区和所述浅沟槽隔离结构，以形成字线沟槽，其中所述浅沟槽隔离结构内的字线沟槽的底部高于所述设定高度。
在示例性实施例中，所述方法还可以包括：在所述字线沟槽内形成字线结构，所述字线结构包括栅氧化物层、阻挡层、导电层和字线保护盖层。
在示例性实施例中，所述浅沟槽隔离结构内的字线沟槽的底部和所述有源区内的字线沟槽的底部可以均与所述刻蚀停止层的上表面齐平。
本公开实施例中，可以采用光罩刻蚀分别在有源区和STI结构内形成WL沟槽，由于之前是以字线在有源区的深度为参考来设置第一牺牲层的设定高度的，然后在该设定高度的第一牺牲层之上形成刻蚀停止层，因此，就能够防止因为刻蚀选择比导致在STI结构内的字线沟槽的深度过深的问题，从而使得在有源区内和STI结构内的字线沟槽的深度接近。理想情况下，可以使得有源区内和STI结构内的字线沟槽的深度相同，即有源区内的字线沟槽的底部、STI结构内的字线沟槽的底部均与刻蚀停止层的上表面齐平，从而使得后续工艺中，在有源区内和STI结构内的字线的深度相同。
本公开实施方式提供的半导体器件的制备方法，一方面，通过在形成STI过程中，在浅沟槽内的第一牺牲层的设定高度处设置一刻蚀停止层，使得在后续刻蚀形成WL沟槽时，通过该刻蚀停止层可以阻止WL沟槽在STI中继续刻蚀，从而使得能够在STI结构内形成一与有源区的WL沟槽深度接近一致的WL沟槽。由于形成的WL沟槽在有源区与STI结构中的深度近似相同，进而可以使得后续在有源区和STI结构内形成的WL字线的金属栅极的底部在半导体衬底内的深度近似相同，可以形成一条接近平直的直线，从而可以改善STI结构中的WL与有源区及邻近的WL之间形成的寄生电容，减小漏电流发生。同时，也可以缩短WL的长度，减小导电电阻。另一方面，通过在STI结构的下部形成空气间隔(air gap)，可以使得隔离效果更好，可以进一步起到减小寄生电容的作用。
下面结合图2-28对上述实施例提供的半导体器件的制备方法进行举例说明。
如图2-4所示，半导体衬底包括浅沟槽1以及浅沟槽隔离出的有源区2。
在图2实施例中，在半导体衬底表面所在的平面内，可以预先定义有相互垂直的纵向(即俯视图图2中的AA延伸方向)及横向(未图示，即沿俯视图图2中从左至右的水平方向)，例如当浅沟槽隔离结构用于定义存储阵列中的存储单元对应的有源区时，可以定义纵向是与字线的延伸方向(未图示)或位线的延伸方向(如俯视图图2中的BB延伸方向)呈一定夹角的方向，横向是和纵向垂直相交的方向。当然，在本公开的其他实施例中，也可以定义纵向是与字线的延伸方向或位线的延伸方向相同的方向，横向和纵向垂直相交的方向。图3为图2沿AA方向的剖面图，图4为图2沿BB方向的剖面图，BB方向与 AA方向相交，可以是有源区的延伸方向。
如图5-7所示，在浅沟槽1及有源区2暴露的外表面形成含氧层3，例如liner oxide、oxide/nitride或ONO结构。其中，图5为俯视图，图6为图5沿AA方向的剖面图，图7为图5沿BB方向的剖面图。
如图8-10所示，在表面包括含氧层3的浅沟槽1内填充设定高度的第一牺牲层4，第一牺牲层4例如可以采用oxide、TEOS、旋涂有机碳、不定型碳、光刻胶及含硅高分子材料等中的任意一种或者多种材料制成。其中，图8为俯视图，图9为图8沿AA方向的剖面图，图10为图8沿BB方向的剖面图。
如图11-13所示，在第一牺牲层4的上表面和对应有源区2的含氧层3暴露的外表面，形成刻蚀停止层5。刻蚀停止层5例如可以采用SiN、SiCN、SiCON等中的任意一种或者多种材料制成。其中，图11为俯视图，图12为图11沿AA方向的剖面图，图13为图11沿BB方向的剖面图。
如图14-16所示，在浅沟槽内的刻蚀停止层5之上沉积第二牺牲层6，第二牺牲层6的上表面和有源区2的上表面齐平。第二牺牲层6例如可以采用oxide、TEOS、旋涂有机碳、不定型碳、光刻胶及含硅高分子材料等中的任意一种或者多种材料制成。其中，图14为俯视图，图15为图14沿AA方向的剖面图，图16为图14沿BB方向的剖面图。
如图17-19所示，通过在第二牺牲层6和有源区2的上方形成图案化的掩膜层，掩膜层在半导体衬底的边缘区域形成有暴露第二牺牲层6的通孔(图中未示出)，以该掩膜层为掩膜，刻蚀第二牺牲层6形成连通该通孔的刻蚀孔7，且该刻蚀孔7贯穿刻蚀停止层5，之后可以去除该掩膜层，从而可以利用该刻蚀孔7灌入刻蚀液至第一牺牲层4内，湿法刻蚀去除浅沟槽1内的刻蚀停止层5之下的第一牺牲层4和浅沟槽1内的刻蚀停止层5之上的第二牺牲层6，形成空气间隔8。其中，图17为俯视图，图18为图17沿AA方向的剖面图，图19为图17沿BB方向的剖面图。
图17-19实施例中，刻蚀孔7的尺寸比有源区2的宽度宽，且比相邻有源区2的间距小。刻蚀孔7例如可以布局在有源区2构成的存储单元阵列区的边缘。
如图20-22所示，在浅沟槽1中刻蚀停止层5之上填充隔离层9，以形成包含空气间隔8的STI结构，有源区2边缘的刻蚀孔7也会被隔离层9填充。隔离层9例如可以通过沉积oxide或者oxide/nitride或ONO结构形成。其中，图20为俯视图，图21为图20沿AA方向的剖面图，图22为图20沿BB方向的剖面图。
如图23-25所示，光罩刻蚀有源区2和包含空气间隔8的浅沟槽隔离结构，以分别在有源区和STI结构内形成字线沟槽10，由于STI结构的底部存在刻蚀停止层5，从而使得浅沟槽隔离结构内的字线沟槽10的底部高于上述设定高度，即刻蚀形成STI结构内的字线沟槽10时，由于刻蚀停止层5的存在，使得STI结构内的字线沟槽10的深度不会超过刻蚀停止层5，使得字线沟槽在STI结构内和有源区内的深度近似相同。同时，由于STI结构下部包含空气间隔8，因此可以进一步减小寄生电容。其中，图23为俯视图，图24 为图23沿AA方向的剖面图，图25为图23沿BB方向的剖面图。
如图26-28所示，可以在有源区内和STI结构内的字线沟槽内，形成栅氧化层11、阻挡层13(例如可以采用锡Tin材料制成，但本公开并不限定于此)、导电层14(例如可以采用金属钨W材料制成，但本公开并不限定于此)和字线保护盖层12(例如可以采用nitride)，以用于形成有源区内和STI结构内的WL结构。其中，图26为俯视图，图27为图26沿AA方向的剖面图，图28为图26沿BB方向的剖面图。
可以理解的是，本公开对如何在字线沟槽内形成字线沟槽的工艺、组成结构等均不做限定。
本公开实施方式提供的半导体器件的制备方法，一方面，通过在形成STI过程中，在浅沟槽内的第一牺牲层的设定高度处设置一刻蚀停止层，使得在后续刻蚀形成WL沟槽时，通过该刻蚀停止层可以阻止WL沟槽在STI中继续刻蚀，从而使得能够在STI结构内形成一与有源区的WL沟槽深度接近一致的WL沟槽。由于形成的WL沟槽在有源区与STI结构中的深度近似相同，进而可以使得后续在有源区和STI结构内形成的WL字线的金属栅极的底部在半导体衬底内的深度近似相同，可以形成一条接近平直的直线，从而可以改善STI结构中的WL与有源区及邻近的WL之间形成的寄生电容，减小漏电流发生。同时，也可以缩短WL的长度，减小导电电阻。另一方面，通过在STI结构的下部形成空气间隔(air gap)，可以使得隔离效果更好，可以进一步起到减小寄生电容的作用。
本公开实施例提供的半导体器件的制备方法可以应用于具有埋入式的栅极结构的半导体器件的制备。例如，所述半导体器件可以是动态随机存储器(Dynamic Random Access Memory，DRAM)，DRAM是一种半导体存储器件，由许多重复的存储单元组成，每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
进一步地，本公开实施方式还提供了一种半导体器件，该半导体器件可以包括半导体衬底。该半导体衬底可以进一步包括浅沟槽以及所述浅沟槽隔离出的有源区。
其中，在所述浅沟槽的底部和所述有源区的表面可以包括含氧层。在所述浅沟槽的设定高度之上具有刻蚀停止层，所述刻蚀停止层和所述浅沟槽形成空气间隔，所述设定高度低于所述有源区的高度。所述浅沟槽中所述刻蚀停止层之上具有包含所述空气间隔的浅沟槽隔离结构，所述浅沟槽隔离结构由隔离层填充而成。所述浅沟槽隔离结构和所述有源区内包括字线沟槽，所述浅沟槽隔离结构内的字线沟槽的底部高于所述设定高度。
本公开实施方式提供的半导体器件，一方面，通过在形成STI过程中，在浅沟槽内的第一牺牲层的设定高度处设置一刻蚀停止层，使得在后续刻蚀形成WL沟槽时，通过该刻蚀停止层可以阻止WL沟槽在STI中继续刻蚀，从而使得能够在STI结构内形成一与 有源区的WL沟槽深度接近一致的WL沟槽。由于形成的WL沟槽在有源区与STI结构中的深度近似相同，进而可以使得后续在有源区和STI结构内形成的WL字线的金属栅极的底部在半导体衬底内的深度近似相同，可以形成一条接近平直的直线，从而可以改善STI结构中的WL与有源区及邻近的WL之间形成的寄生电容，减小漏电流发生。同时，也可以缩短WL的长度，减小导电电阻。另一方面，通过在STI结构的下部形成空气间隔(air gap)，可以使得隔离效果更好，可以进一步起到减小寄生电容的作用。
在示例性实施例中，所述刻蚀停止层的厚度可以处于2nm至10nm的范围之内。
在示例性实施例中，所述浅沟槽隔离结构内的字线沟槽的底部和所述有源区内的字线沟槽的底部可以均与所述刻蚀停止层的上表面齐平。
在示例性实施例中，对应所述有源区的所述含氧层的表面可以包括所述刻蚀停止层。
在示例性实施例中，所述半导体衬底的边缘区域可以包括贯穿所述刻蚀停止层的刻蚀孔，所述刻蚀孔填充所述隔离层。
在示例性实施例中，所述第一牺牲层的材料可以包括氧化物、正硅酸乙酯、旋涂有机碳、不定型碳、光刻胶以及含硅高分子材料等中的至少一种。
在示例性实施例中，在所述字线沟槽内可以包括字线结构，所述字线结构可以包括栅氧化物层、阻挡层、导电层和字线保护盖层等。
在示例性实施例中，所述刻蚀停止层的材料可以包括氮化硅、碳氮化硅和碳氮氧化硅等中的至少一种。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种半导体器件的制备方法，其特征在于，包括：
    提供半导体衬底，所述半导体衬底包括浅沟槽及所述浅沟槽隔离出的有源区；
    在所述浅沟槽及所述有源区暴露的外表面形成含氧层；
    在表面包括所述含氧层的所述浅沟槽内填充设定高度的第一牺牲层，所述设定高度低于所述有源区的高度；
    在所述第一牺牲层的上表面形成刻蚀停止层；
    去除所述刻蚀停止层下方的所述第一牺牲层，以形成空气间隔；
    在所述浅沟槽中所述刻蚀停止层之上填充隔离层，以形成包含所述空气间隔的浅沟槽隔离结构；
    刻蚀所述有源区和所述浅沟槽隔离结构，以形成字线沟槽，其中所述浅沟槽隔离结构内的字线沟槽的底部高于所述设定高度。
  2. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述刻蚀停止层的厚度处于2nm至10nm的范围之内。
  3. 根据权利要求1或2所述的半导体器件的制备方法，其特征在于，所述浅沟槽隔离结构内的字线沟槽的底部和所述有源区内的字线沟槽的底部均与所述刻蚀停止层的上表面齐平。
  4. 根据权利要求1所述的半导体器件的制备方法，其特征在于，在所述第一牺牲层的上表面形成刻蚀停止层，包括：
    在所述第一牺牲层的上表面和对应所述有源区的所述含氧层暴露的外表面，形成刻蚀停止层。
  5. 根据权利要求4所述的半导体器件的制备方法，其特征在于，去除所述刻蚀停止层下方的所述第一牺牲层，以形成空气间隔，包括：
    在所述浅沟槽中形成刻蚀孔，所述刻蚀孔贯穿所述刻蚀停止层；
    通过所述刻蚀孔灌入刻蚀液至所述第一牺牲层内，湿法刻蚀所述刻蚀停止层下方的所述第一牺牲层。
  6. 根据权利要求5所述的半导体器件的制备方法，其特征在于，在所述浅沟槽中形成刻蚀孔，包括：
    在所述浅沟槽内所述刻蚀停止层之上填充第二牺牲层，所述第二牺牲层的上表面和所述有源区的上表面齐平；
    在所述第二牺牲层和所述有源区的上方形成图案化的掩膜层，所述掩膜层在所述半导体衬底的边缘区域形成有暴露第二牺牲层的通孔；
    以所述掩膜层为掩膜，刻蚀所述第二牺牲层形成连通所述通孔的刻蚀孔，且所述刻蚀孔贯穿所述刻蚀停止层；
    去除所述掩膜层。
  7. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述含氧层包括线形氧化层，氧化物层和氮化物层堆叠结构，氧化物层、氮化物层和氧化物层堆叠结构中的至少一种。
  8. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述第一牺牲层的材料包括氧化物、正硅酸乙酯、旋涂有机碳、不定型碳、光刻胶以及含硅高分子材料中的至少一种。
  9. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述隔离层包括氧化物层，氧化物层和氮化物层堆叠结构，氧化物层、氮化物层和氧化物层堆叠结构中的至少一种。
  10. 根据权利要求1所述的半导体器件的制备方法，其特征在于，还包括：
    在所述字线沟槽内形成字线结构，所述字线结构包括栅氧化物层、阻挡层、导电层和字线保护盖层。
  11. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述刻蚀停止层的材料包括氮化硅、碳氮化硅和碳氮氧化硅中的至少一种。
  12. 一种半导体器件，其特征在于，包括：
    半导体衬底，其包括：
    浅沟槽；以及
    所述浅沟槽隔离出的有源区；其中，
    在所述浅沟槽的底部和所述有源区的表面包括含氧层；
    在所述浅沟槽的设定高度之上具有刻蚀停止层，所述刻蚀停止层和所述浅沟槽形成空气间隔，所述设定高度低于所述有源区的高度；
    所述浅沟槽中所述刻蚀停止层之上具有包含所述空气间隔的浅沟槽隔离结构，所述浅沟槽隔离结构由隔离层填充而成；
    所述浅沟槽隔离结构和所述有源区内包括字线沟槽，所述浅沟槽隔离结构内的字线沟槽的底部高于所述设定高度。
  13. 根据权利要求12所述的半导体器件，其特征在于，所述刻蚀停止层的厚度处于2nm至10nm的范围之内。
  14. 根据权利要求12或13所述的半导体器件，其特征在于，所述浅沟槽隔离结构内的字线沟槽的底部和所述有源区内的字线沟槽的底部均与所述刻蚀停止层的上表面齐平。
  15. 根据权利要求12所述的半导体器件，其特征在于，对应所述有源区的所述含氧层的表面包括所述刻蚀停止层。
  16. 根据权利要求12所述的半导体器件，其特征在于，所述半导体衬底的边缘区域包括贯穿所述刻蚀停止层的刻蚀孔，所述刻蚀孔填充所述隔离层。
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