WO2022021837A1 - 一种记忆板件智能测试系统及方法 - Google Patents
一种记忆板件智能测试系统及方法 Download PDFInfo
- Publication number
- WO2022021837A1 WO2022021837A1 PCT/CN2021/076108 CN2021076108W WO2022021837A1 WO 2022021837 A1 WO2022021837 A1 WO 2022021837A1 CN 2021076108 W CN2021076108 W CN 2021076108W WO 2022021837 A1 WO2022021837 A1 WO 2022021837A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- array switch
- board
- unit
- detection signal
- reference signal
- Prior art date
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 146
- 238000000034 method Methods 0.000 title abstract description 24
- 238000001514 detection method Methods 0.000 claims abstract description 217
- 238000004891 communication Methods 0.000 claims abstract description 17
- 230000001960 triggered effect Effects 0.000 claims abstract description 12
- 238000010998 test method Methods 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 abstract description 18
- 230000008859 change Effects 0.000 description 11
- 230000003750 conditioning effect Effects 0.000 description 7
- 238000005259 measurement Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to the technical field of panel testing, and more particularly, to an intelligent testing system and method for panels.
- the technical problem to be solved by the present invention is to provide an intelligent testing system and method for a memory board in view of the above-mentioned part of the technical defects of the prior art.
- the technical scheme adopted by the present invention to solve the technical problem is: constructing a memory board intelligent testing system, including: a power supply unit, a reference signal output unit, an output detection unit, and a board socket that can be pluggably installed with the board to be tested , connect the first array switch of the first attribute pin of the board socket, connect the second attribute pin of the board socket with the second array switch of the power supply unit, connect the first array switch of the board socket.
- the three attribute pins and the third array switch of the reference signal output unit are connected to the fourth attribute pin of the board socket and the fourth array switch of the output detection unit, and are respectively connected to the first array switch,
- the control units of the second array switch, the third array switch and the fourth array switch are respectively connected to the reference signal output unit, the output detection unit and the communication unit of the control unit, and are connected to the A display unit of a communication unit;
- the display unit displays virtual nodes corresponding to the connection nodes of the first array switch, the second array switch, the third array switch and the fourth array switch respectively, and the display unit is in the When the virtual node is triggered, the connection between the virtual nodes is generated or cleared, and the control unit triggers the first array switch, the second array switch, the third array switch when the virtual node is triggered The switch and/or the corresponding connection node in the fourth array switch is connected or disconnected;
- the display unit is further configured to control the reference signal output unit to output a reference signal and obtain a detection signal corresponding to the reference signal through the output detection unit, so as to obtain the test of the board to be tested according to the detection signal result.
- the power supply unit includes a first power supply unit for providing a first power supply voltage and a second power supply unit for providing a second power supply voltage, the first power supply unit and the second power supply unit are respectively connected to the second power supply unit different connection nodes of the array switch; and/or
- the output detection unit includes an output voltage detection unit for acquiring the voltage detection signal of the board to be tested and an output current detection unit for acquiring the current detection signal of the board to be tested, the output voltage detection unit and the output current detection unit are respectively connected to different connection nodes of the fourth array switch.
- the reference signal output unit includes a first reference signal output unit for generating a first reference voltage, a second reference signal output unit for outputting a second reference voltage, and a third reference signal output unit for generating a third reference voltage unit;
- the first reference signal output unit, the second reference signal output unit and the third reference signal output unit are respectively connected to different connection nodes of the third array switch.
- the display unit controls the first reference voltage generated by the first reference signal output unit to be a first fixed value
- the display unit controls the second reference voltage generated by the second reference signal output unit to be a second fixed value
- the display unit controls the third reference voltage generated by the third reference signal output unit to satisfy a preset function.
- the present invention also constructs a memory board intelligent test method, which is applied to the memory board intelligent test system as described above, including:
- the first array switch, the second array switch, the third array switch, and the fourth array switch on the display interface of the display unit, generate a connection with the first array switch, the third array switch, and the fourth array switch. virtual nodes corresponding to the connection nodes of the second array switch, the third array switch and the fourth array switch respectively;
- S2 Trigger the virtual node to generate a trigger instruction, so as to generate or clear the connection between the virtual nodes on the display interface, and control the first array switch and the second array switch according to the trigger instruction , the third array switch and/or the corresponding connection node in the fourth array switch is connected or disconnected;
- a memory board intelligent testing method of the present invention further comprises:
- A1 Trigger the virtual node corresponding to the second array switch, so that the connection node connected to the power supply unit in the second array switch is connected to the twentieth pin and the fourth tube of the board socket respectively.
- the connection node of the pin is turned on, and the connection nodes connected to the fifteenth pin and the sixteenth pin of the board socket are grounded respectively;
- A2 Trigger the virtual node corresponding to the fourth array switch, so that the connection node of the fourth array switch connected to the twenty-fourth pin of the board socket is connected to the output voltage detection unit The node is turned on, and the connection node connected to the eighteenth pin of the board socket is turned on with the connection node connected to the output current detection unit;
- A3. Trigger the virtual node corresponding to the third array switch, so that the connection node of the third array switch connected to the twenty-second pin of the board socket is connected to the reference signal output unit The node is turned on;
- A4 Adjust the reference signal to obtain the corresponding voltage detection signal and the current detection signal, and confirm whether the voltage detection signal and the current detection signal meet the first preset condition, if so, determine the The test result of the board to be tested is qualified, if not, it is determined that the test result of the board to be tested is unqualified.
- a memory board intelligent testing method of the present invention further comprises:
- A5. Trigger the virtual node corresponding to the second array switch, so that the connection node connected to the power supply unit in the second array switch and the connection node connected to the first pin of the board socket are instantly connected ;
- A6 Adjust the reference signal to obtain the corresponding voltage detection signal and the current detection signal, and confirm whether the voltage detection signal and the current detection signal meet the second preset condition, and if so, determine the The test result of the board to be tested is qualified, if not, it is determined that the test result of the board to be tested is unqualified.
- a memory board intelligent testing method of the present invention further comprises:
- B5. Trigger the virtual node corresponding to the second array switch, so that the connection node connected to the power supply unit in the second array switch is connected to the connection node of the tenth pin of the board socket to conduct;
- a memory board intelligent testing method of the present invention further comprises:
- C5. Trigger the virtual node corresponding to the second array switch, so that the connection node connected to the power supply unit in the second array switch is connected to the connection node connected to the twelfth pin of the board socket. ;
- a memory board intelligent testing method of the present invention further comprises:
- D5. Trigger the virtual node corresponding to the second array switch, so as to disconnect the connection node connected to the power supply unit in the second array switch from the connection node connected to the fourth pin of the board socket;
- the implementation of an intelligent testing system and method for boards of the present invention has the following beneficial effects: easy to operate, can greatly reduce the workload of the memory board testing process, and ensure the reliability of memory board testing.
- FIG. 1 is a logical block diagram of an embodiment of a memory board intelligent testing system of the present invention
- FIG. 2 is a logical block diagram of another embodiment of a memory board intelligent testing system of the present invention.
- FIG. 3 is a schematic diagram of an embodiment of a display interface of a display unit of the present invention.
- FIG. 4 is a flowchart of an embodiment of an intelligent testing method for a memory board according to the present invention.
- FIG. 5 is a flowchart of an embodiment of an intelligent testing method for a memory board according to the present invention.
- FIG. 6 is a flow chart of another embodiment of a memory board intelligent testing method of the present invention.
- Fig. 7 is a flow chart of another embodiment of a memory board intelligent testing method of the present invention.
- FIG. 8 is a flowchart of another embodiment of an intelligent testing method for a memory board according to the present invention.
- a memory board intelligent test system of the present invention includes: a power supply unit 121 , a reference signal output unit 122 , an output detection unit 123 , and a pluggable installation with the board to be tested.
- the third attribute pin of 110 and the third array switch 133 of the reference signal output unit 122 are connected to the fourth attribute pin of the board socket 110 and the fourth array switch 134 of the output detection unit 123, respectively connected to the first array switch 131 , the control unit 140 of the second array switch 132 , the third array switch 133 and the fourth array switch 134 are respectively connected to the reference signal output unit 122 , the output detection unit 123 and the communication unit 140 of the control unit 140 , and are connected to the display of the communication unit 140 unit 160; wherein the display unit 160 displays the virtual nodes 161 corresponding to the connection nodes of the first array switch 131, the second array switch 132, the third array switch 133 and the fourth array switch 134 respectively, and the display unit 160 is at the virtual node When the virtual node 161 is triggered
- the corresponding connection node in 134 is connected or disconnected; the display unit 160 is also used to control the reference signal output unit 122 to output the reference signal and obtain the detection signal corresponding to the reference signal through the output detection unit 123, so as to obtain the board to be tested according to the detection signal 's test results.
- the board to be tested is matched with the board socket 110 and is pluggable and installed with the board socket 110 .
- the board to be tested is placed on the board socket 110 To form the test circuit of the board to be tested.
- the test circuit of the board to be tested includes a power supply unit 121 , a reference signal output unit 122 , and an output detection unit 123 .
- the power supply unit 121 is used to provide power supply to the board to be tested and other circuits during the test of the board to be tested, the reference signal output unit 122 is used to provide the reference signal required for the test of the board to be tested, and the output detection unit 123 is used to During the testing of the board under test, the corresponding output signal is obtained when the reference signal is input.
- the power supply unit 121 is connected to the power supply pin of the board socket 110 through the second array switch 132 , that is, the second attribute pin. It can be understood that the power supply unit 121 controls the on or off of the board under test through the second array switch 132 .
- the reference signal output unit 122 is connected to the reference signal input pin of the board socket 110 through the third array switch 123, that is, the third attribute pin.
- the output detection unit 123 is connected to the test signal output pin of the board socket 110 through the fourth array switch 134, that is, the fourth attribute pin. It can also be understood that the output detection unit 123 controls it and the board to be tested through the fourth array switch 134. turn-on or turn-off. At the same time, during the test process of the board under test, some of its pins need to be connected to each other, that is, the pins of the board under test that need to be connected to each other are controlled by the first array switch 131 to be turned on or off, that is, the first array switch 131 An array switch 131 is connected to the first attribute pin of the board socket 110 .
- the pin properties of the board socket 110 are determined by the circuit properties of the board under test to be connected.
- the control unit 140 can control the first array switch 131 , the second array switch 132 , the third array switch 133 and the fourth array switch 134 to act as required, and the display unit 160 controls the reference signal output unit through the communication unit 150 122 outputs the required reference signal, and at the same time, the display unit 160 receives the detection signal obtained by the output detection unit 123 through the communication unit 150 and confirms the test result of the board under test. It can form different electrical connection relationships of the board under test through the setting of on and off of each switch node in each array switch.
- the control unit 140 is connected to the display unit 160 through the communication unit 150 .
- the display unit 160 displays a virtual node 161 , and the virtual node 161 is in a one-to-one correspondence with the connection nodes of each array switch.
- the connection node of the array switch is understood as the connection node used by the array switch to connect external circuits.
- the power supply unit 121 When it is necessary to set a certain connection relationship between the endpoints of the board socket 110, the power supply unit 121, the reference signal output unit 123 and the output detection unit 123, it can trigger the virtual node 161 corresponding to the connection node of the array switch corresponding to the endpoint, For example, if two virtual nodes 161 are clicked in sequence, when the two virtual nodes 161 are in a disconnected state, a connection between the two virtual nodes 161 will be generated on the display unit 160 . At the same time, when the virtual node 161 is triggered, and when the two virtual nodes 161 are in a disconnected state, the control unit 140 triggers the connection of the switch node corresponding to the connection node in the array switch 130, thus forming a connection with the display unit.
- the electrical connection relationship in the actual test circuit corresponding to the virtual node 161 connection on 160 can be triggered in sequence, for example, in sequence Click on the two virtual nodes 161 , when the two virtual nodes 161 are in a connected state, the connection between the two virtual nodes 161 will be cleared on the display unit 160 .
- the control unit 140 triggers the switch node corresponding to the connection node in the corresponding array switch to disconnect, thus disconnecting The electrical connection relationship in the actual test circuit corresponding to the connection of the virtual node 161 on the display unit 160 .
- the control unit 140 and the display unit 160 receive the trigger instruction that the virtual node 161 is triggered, they can both judge whether there is a connection between the current virtual nodes 161, and respectively trigger the actual connection according to the judgment result.
- the array switching action and the action of generating or clearing the connection on the display unit 160 realize the consistency between the display state of the display unit 160 and the electrical connection relationship in the actual test system.
- the power supply unit 121 supplies power to the board under test, triggers the virtual node 161 corresponding to the third array switch 133, and inputs the board under test.
- the reference signal by triggering the virtual node 161 corresponding to the fourth array switch 134, causes the output detection unit 123 to obtain the output signal of the board to be tested, and determines the output signal of the board to be tested by testing the output signal or the relationship between the test output signal and the reference signal. Performance.
- each array switch and the virtual node 161 corresponds to the connection node of the array switch as described above.
- the first array switch 131 , the second array switch 132 , the third array switch 133 and the fourth array switch 134 can be selectively set as required.
- the power supply unit 121 includes a first power supply unit 1211 for providing a first power supply voltage and a second power supply unit 1212 for providing a second power supply voltage.
- the first power supply unit 1211 and the second power supply unit 1212 are respectively connected to different connection nodes of the second array switch 132; specifically, the power supply unit 121 includes different unit modules that provide different voltage outputs, and the first power supply unit 1211 provides a voltage output of about 30V, that is, the first power supply voltage, the second power supply unit 1212 provides a voltage output of about 48V, that is, the second power supply voltage.
- the first power supply unit 1211 and the second power supply unit 1212 do not affect each other, and they can correspond to different connection nodes of the second array switch 132.
- the unit 160 corresponds to different virtual nodes 161 , for example, corresponding to the virtual node P1 and the virtual node P2 respectively, which are controlled by the second array switch 132 respectively.
- the first power supply unit 1211 and the second power supply unit 1212 may use power frequency transformers.
- the power supply unit is provided with a current limiting protection function.
- the output detection unit 123 includes an output voltage detection unit 1231 for acquiring the voltage detection signal of the board under test and an output current detection unit 1232 for acquiring the current detection signal of the board under test.
- the output voltage detection unit 1231 and the output current detection unit 1231 are respectively connected to different connection nodes of the fourth array switch 134 . That is, in the process of testing the board under test, it can detect the voltage detection signal and the current detection signal respectively, so as to analyze the performance of the board under test.
- the corresponding voltage detection signal can be obtained through the output voltage detection unit 1231 and the corresponding current detection signal can be obtained through the output current detection unit 1232 .
- the output voltage detection unit 1231 and the output current detection unit 1232 respectively correspond to different connection nodes of the fourth array switch 134, which correspond to different virtual nodes in the display unit, for example, corresponding to the virtual node C1 and the virtual node C2 respectively, which are composed of the fourth array switch 134.
- the switches 134 are controlled separately.
- the output voltage detection unit 1231 adopts a highly stable reference and a 24-bit high-precision analog-to-digital conversion chip to protect the measurement signal against high-voltage mis-entry, and the maximum allowable 60VDC, the voltage detection signal enters the signal conditioning circuit, conditioning The circuit adjusts the voltage detection signal to a voltage suitable for the ADC measurement chip through high-performance operational amplifiers and metal foil resistors, and then directly measures it by the ADC.
- the measurement rate can be set, and the maximum acquisition rate is 100 points/second.
- the output voltage detection unit is provided with a single-chip microcomputer to control the acquisition process of the voltage detection signal. In order to prevent signal crosstalk, an optoelectronic isolation chip is also used for data communication between the output voltage detection unit 1231 and the communication unit 150 .
- the output current detection unit 1232 adopts a highly stable reference and a 24-bit high-precision analog-to-digital conversion chip, and firstly performs current limiting protection on the measured signal current signal, that is, the maximum current does not exceed ⁇ 30mA, to prevent the large current from affecting the subsequent damage to the circuit.
- the current is converted into a voltage through a 250 ohm resistor before entering the signal conditioning circuit.
- the conditioning circuit uses high-performance op amps and metal foil resistors to adjust the input signal to a voltage suitable for the ADC measurement chip, and then directly measure it by the ADC.
- the measurement rate can be set, and the maximum acquisition rate is 100 points/second.
- a single-chip microcomputer is set in the output current detection unit to control the current detection signal acquisition process.
- an optoelectronic isolation chip is also used for data communication between the output current detection unit 1232 and the communication unit 150 .
- the reference signal output unit 122 includes a first reference signal output unit 1221 for generating a first reference voltage, a second reference signal output unit 1222 for outputting a second reference voltage, and a second reference signal output unit 1222 for generating a third reference voltage.
- the third reference signal output unit 1223 ; the first reference signal output unit 1221 , the second reference signal output unit 1222 and the third reference signal output unit 1223 are respectively connected to different connection nodes of the third array switch 133 . That is, the reference signal output unit 122 includes a first reference signal output unit 1221, a second reference signal output unit 1222 and a third reference signal output unit 1223 using independent power supplies, which are respectively used to provide three different reference voltage outputs.
- a reference signal output unit is equipped with output short-circuit protection function. It uses a voltage reference with high stability and low temperature drift and a 16-bit high-precision digital-to-analog conversion chip to perform signal conditioning on the output signal of the digital-to-analog chip.
- the conditioning circuit adopts high-performance operation. Discharge and metal foil resistors, after conditioning, the output voltage is output after current limiting protection, and the allowable output current does not exceed 10mA. It can obtain the reference voltage output by the output port of each reference signal output unit.
- Each reference signal output unit is provided with a single-chip microcomputer to control the output process of each reference voltage.
- each reference signal output unit and the communication unit 150 use an optoelectronic isolation chip for data communication.
- the first reference signal output unit 1221 , the second reference signal output unit 1222 and the third reference signal output unit 1223 respectively correspond to different connection nodes of the third array switch 133 , which correspond to different virtual nodes 161 in the display unit 160 , for example, respectively
- the virtual node I1 , the virtual node I2 and the virtual node I3 are controlled by the third array switch 134 respectively.
- the display unit 160 controls the first reference voltage generated by the first reference signal output unit 1221 to be a first fixed value; the display unit 160 controls the second reference voltage generated by the second reference signal output unit 1222 to be a second fixed value; The display unit 160 controls the third reference voltage generated by the third reference signal output unit 1223 to satisfy a predetermined function.
- the first reference voltage and the second reference voltage may be fixed values, and their value ranges are 0-6V.
- the third reference voltage is a function voltage, that is, the third reference signal output unit 1231 can implement ramp voltage output under the control of the display unit 160, with a maximum output rate of 100 points/second.
- a memory board intelligent test method of the present invention is applied to the above memory board intelligent test system, including:
- S2 Trigger the virtual node to generate a trigger instruction to generate or clear the connection between the virtual nodes on the display interface, so as to trigger the corresponding one of the first array switch, the second array switch, the third array switch and/or the fourth array switch Connecting nodes are connected or disconnected;
- the intelligent test system for memory boards forms a connection relationship between virtual nodes by triggering virtual nodes, and generates corresponding connections. Action to form the connection relationship between the corresponding connection nodes, and form the final connection circuit connection relationship.
- the reference signal output unit is controlled to output the reference signal and the detection signal corresponding to the reference signal is obtained through the output detection unit; the test result of the board to be tested is obtained according to the detection signal, and the test of the board to be tested is completed.
- it also performs various operations according to the board intelligent testing system to test different boards to be tested.
- a memory board intelligent testing method of the present invention further includes:
- A1 Trigger the virtual node corresponding to the second array switch, so that the connection node connected to the power supply unit in the second array switch is turned on and connected to the connection node of the twentieth pin and the fourth pin of the board socket respectively.
- the connection nodes of the fifteenth pin and the sixteenth pin of the board socket are grounded respectively;
- A2 Trigger the virtual node corresponding to the fourth array switch, so that the connection node of the fourth array switch connected to the twenty-fourth pin of the board socket is connected to the connection node of the output voltage detection unit and connected to the board socket.
- the connection node of the eighteenth pin is conductive with the connection node connected to the output current detection unit;
- A3. Trigger the virtual node corresponding to the third array switch, so that the connection node connecting the twenty-second pin of the board socket in the third array switch is connected to the connection node connecting the reference signal output unit;
- A4. Adjust the reference signal to obtain the corresponding voltage detection signal and current detection signal, and confirm whether the voltage detection signal and the current detection signal meet the first preset condition. If yes, determine that the test result of the board to be tested is qualified, if not , the test result of the panel to be tested is determined to be unqualified.
- an automatic state test can be performed on the ME board through the following process.
- the pins T20 and T4 of the ME board can be connected to the power supply unit to realize the +28V voltage input.
- T15 and pin T16 are grounded, the pin T22 of the ME board and the reference signal output unit receive the input of the reference signal, and the output voltage detection unit is conductively connected to the pin T24 of the ME board to obtain the voltage detection signal, and output the current detection
- the unit is conductively connected to the pin T18 of the ME board to obtain the current detection signal.
- the reference signal is a 1 ⁇ 5V voltage signal
- the current detection signal and the voltage detection signal are 1 ⁇ 5V voltage and 4 ⁇ 20mA current signal respectively.
- the accuracy of the voltage detection signal is required to have a deviation of no more than 0.5%
- the accuracy of the current detection signal is required to have a deviation of no more than 3%.
- a memory board intelligent testing method of the present invention further includes:
- A5. Trigger the virtual node corresponding to the second array switch, so that the connection node connecting the power supply unit in the second array switch and the connection node connecting the first pin of the board socket are instantly conductive;
- A6 Adjust the reference signal to obtain the corresponding voltage detection signal and current detection signal, and confirm whether the voltage detection signal and the current detection signal meet the second preset condition. If yes, then determine that the test result of the board to be tested is qualified. , the test result of the panel to be tested is determined to be unqualified.
- the ME board is switched to the manual state test through the following process, and the pin T20 and pin T4 of the ME board realized by triggering the virtual node are connected to the power supply unit to realize the +28V voltage input.
- the pins T15 and T16 of the ME board are grounded, the pin T22 of the ME board and the reference signal output unit receive the input of the reference signal, and the output voltage detection unit is connected to the pin T24 of the ME board to realize voltage detection.
- the output current detection unit is conductively connected to the pin T18 of the ME board to realize the acquisition of the current detection signal.
- the pin T1 of the ME board is instantly turned on with the power supply unit, and the instantaneous turn-on can also be understood as instantaneous turn-on, that is, the power supply is disconnected after the pin T1 of the ME board is quickly powered on.
- adjust the reference signal output unit to make the reference signal change according to certain rules, and obtain the corresponding current detection signal and voltage detection signal, and confirm whether the output of the ME board meets the requirements through the current detection signal and voltage detection signal, that is, voltage detection Whether the signal and the current detection signal satisfy the second preset condition.
- the current detection signal and the voltage detection signal should not change with the change of the reference signal, and are fixed values.
- test result of the board to be tested is judged to be qualified, and if there is a change, the test result of the board to be tested is judged to be unqualified.
- a memory board intelligent testing method of the present invention further includes:
- B5. Trigger the virtual node corresponding to the second array switch, so that the connection node connecting the power supply unit in the second array switch is connected to the connection node connecting the tenth pin of the board socket;
- the ME board is switched to the automatic increase state test through the following process, and the pin T20 and pin T4 of the ME board realized by triggering the virtual node are connected to the power supply unit to realize the +28V voltage Input, the pins T15 and T16 of the ME board are grounded, the pin T22 of the ME board and the reference signal output unit receive the input of the reference signal, and the output voltage detection unit is connected to the pin T24 of the ME board to realize the voltage For the acquisition of the detection signal, the output current detection unit is electrically connected to the pin T18 of the ME board to realize the acquisition of the current detection signal.
- the pin T10 of the ME board is connected to the power supply unit to realize the +28V voltage input.
- the reference signal output unit makes the reference signal a fixed input, and obtains the corresponding current detection signal and voltage
- the current detection signal and the voltage detection signal are used to confirm whether the output of the ME board meets the requirements, that is, whether the voltage detection signal and the current detection signal meet the third preset condition.
- the current detection signal and voltage detection signal at this time should automatically increase. That is, when the current detection signal and the voltage detection signal should increase automatically, the test result of the board under test is judged to be qualified; if it does not increase automatically, the test result of the board to be tested is judged to be unqualified.
- a memory board intelligent testing method of the present invention further includes:
- the ME board is switched to the automatic reduction state test through the following process.
- the reference signal output unit receives the input of the reference signal, the output voltage detection unit is connected to the pin T24 of the ME board to realize the acquisition of the voltage detection signal, and the output current detection unit is connected to the pin T18 of the ME board to realize the current Detection signal acquisition.
- the pin T12 of the ME board is connected to the power supply unit to realize the +28V voltage input.
- the reference signal output unit makes the reference signal a fixed input, and obtains the corresponding current detection signal and voltage
- the current detection signal and the voltage detection signal are used to confirm whether the output of the ME board meets the requirements, that is, whether the voltage detection signal and the current detection signal meet the fourth preset condition.
- the current detection signal and the voltage detection signal should automatically decrease. That is, when the current detection signal and the voltage detection signal should be automatically reduced, the test result of the board to be tested is judged to be qualified; if it does not automatically decrease, the test result of the board to be tested is judged to be unqualified.
- a memory board intelligent testing method of the present invention further includes:
- D6 Adjust the reference signal to obtain the corresponding voltage detection signal and current detection signal, and confirm whether the voltage detection signal and the current detection signal meet the fifth preset condition. If yes, then determine that the test result of the board under test is qualified, if not , the test result of the panel to be tested is determined to be unqualified.
- the ME board is switched to the automatic and manual state switching test through the following process.
- Keep the pin T20 of the ME board connected to the power supply unit by triggering the virtual node to realize the connection of +28V voltage input the pins T15 and T16 of the ME board are grounded, and the pin T22 of the ME board is connected to the reference
- the signal output unit receives the input of the reference signal
- the output voltage detection unit is connected to the pin T24 of the ME board to realize the acquisition of the voltage detection signal
- the output current detection unit is connected to the pin T18 of the ME board to realize the current detection signal.
- acquisition By triggering the virtual node, the pin T4 of the ME board is connected to the power supply unit to realize the disconnection of the +28V voltage input.
- the reference signal output unit makes the reference signal change, and obtains the corresponding current detection signal and voltage detection signal, and confirms whether the output of the ME board meets the requirements through the current detection signal and the voltage detection signal, that is, the voltage detection signal and current Whether the detection signal satisfies the fifth preset condition.
- the current detection signal and the voltage detection signal should not change. That is, when the current detection signal and the voltage detection signal do not change, the test result of the board to be tested is determined to be qualified; if there is a change, the test result of the board to be tested is determined to be unqualified.
- test result of the board to be tested is judged to be qualified or unqualified, which is the judgment of the specific test item. If the test result is qualified, the test is qualified for the test item. When the test is unqualified, it is also understood. The test result for this test item is unqualified.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
一种记忆板件智能测试系统及方法，该测试系统包括：供电单元（121），基准信号输出单元（122），输出检测单元（123），板件插座（110），连接板件插座（110）的第一、第二、第三和第四阵列开关（131-134），连接各阵列开关（131-134）的控制单元（140），连接基准信号输出单元（122）、输出检测单元（123）和控制单元（140）的通信单元（150），连接通信单元（150）的显示单元（160）；其中，显示单元（160）显示与各阵列开关（131-134）分别对应的虚拟节点，且显示单元（160）在虚拟节点被触发时生成或清除虚拟节点之间的连线，控制单元（140）在虚拟节点被触发时触发各阵列开关（131-134）对应的连接节点连接或断开；显示单元（160）控制基准信号输出单元（122）输出基准信号并获取检测信号以得到待测板件的测试结果。实施本系统操作方便，能够大大减少记忆板件测试过程的工作量，保证记忆板件测试可靠。
Description
本发明涉及板件测试技术领域，更具体地说，涉及一种板件智能测试系统及方法。
大亚湾、岭澳核电站每轮次大修校验板件的数量庞大，其中使用的记忆板件（ME板件）有35个针脚，在测试过程中，需要针对不同的性能测试，对其管脚进行不同的连线。繁琐的接线，不仅不直观和凌乱，同时还增加接线错误概率，尤其是在变更接线的过程中，其出错概率也会激增，测试结果不能保证为正确连线的测试结果，影响ME板件的最终测试结果的可靠性。
本发明要解决的技术问题在于，针对现有技术的上述部分技术缺陷，提供一种记忆板件智能测试系统及方法。
本发明解决其技术问题所采用的技术方案是：构造一种记忆板件智能测试系统，包括：供电单元，基准信号输出单元，输出检测单元，与待测板件可插拔安装的板件插座，连接所述板件插座的第一属性管脚的第一阵列开关，连接所述板件插座的第二属性管脚与所述供电单元的第二阵列开关，连接所述板件插座的第三属性管脚与所述基准信号输出单元的第三阵列开关，连接所述板件插座的第四属性管脚与所述输出检测单元的第四阵列开关，分别连接所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关的控制单元，分别连接所述基准信号输出单元、所述输出检测单元和所述控制单元的通信单元，连接所述通信单元的显示单元；其中，
所述显示单元显示与所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关的连接节点分别对应的虚拟节点，且所述显示单元在所述虚拟节点被触发时生成或清除所述虚拟节点之间的连线，所述控制单元在所述虚拟节点被触发时触发所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和/或所述第四阵列开关中对应的连接节点连接或断开；
所述显示单元还用于控制所述基准信号输出单元输出基准信号并通过所述输出检测单元获取与所述基准信号对应的检测信号，以根据所述检测信号得到所述待测板件的测试结果。
优选地，
所述供电单元包括用于提供第一供电电压的第一供电单元和用于提供第二供电电压的第二供电单元，所述第一供电单元和所述第二供电单元分别连接所述第二阵列开关的不同连接节点；和/或
所述输出检测单元包括用于获取所述待测板件的电压检测信号的输出电压检测单元和用于获取所述待测板件的电流检测信号的输出电流检测单元，所述输出电压检测单元和所述输出电流检测单元分别连接所述第四阵列开关的不同连接节点。
优选地，
所述基准信号输出单元包括用于生成第一基准电压的第一基准信号输出单元，用于输出第二基准电压生成第二基准信号输出单元和用于生成第三基准电压的第三基准信号输出单元；
所述第一基准信号输出单元、所述第二基准信号输出单元和所述第三基准信号输出单元分别连接所述第三阵列开关的不同连接节点。
优选地，
所述显示单元控制所述第一基准信号输出单元生成的所述第一基准电压为第一固定值；
所述显示单元控制所述第二基准信号输出单元生成的所述第二基准电压为第二固定值；
所述显示单元控制所述第三基准信号输出单元生成的所述第三基准电压满足一预设函数。
本发明还构造一种记忆板件智能测试方法，应用于如上面所述的记忆板件智能测试系统，包括：
S1、根据所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关在所述显示单元的显示界面生成与所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关的连接节点分别对应的虚拟节点；
S2、触发所述虚拟节点生成触发指令，以在所述显示界面生成或清除所述虚拟节点之间的连线，并根据所述触发指令控制所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和/或所述第四阵列开关中对应的连接节点连接或断开；
S3、控制所述基准信号输出单元输出基准信号并通过所述输出检测单元获取与所述基准信号对应的检测信号；
S4、根据所述检测信号得到所述待测板件的测试结果。
优选地，本发明的一种记忆板件智能测试方法还包括：
A1、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点分别与连接所述板件插座的第二十管脚和第四管脚的连接节点导通、连接所述板件插座的第十五管脚和第十六管脚的连接节点分别接地；
A2、触发与所述第四阵列开关对应的虚拟节点，以使所述第四阵列开关中连接所述板件插座的第二十四管脚的连接节点与连接所述输出电压检测单元的连接节点导通、连接所述板件插座的第十八管脚的连接节点与连接所述输出电流检测单元的连接节点导通；
A3、触发与所述第三阵列开关对应的虚拟节点，以使所述第三阵列开关中连接所述板件插座的第二十二管脚的连接节点与连接所述基准信号输出单元的连接节点导通；
A4、调整所述基准信号以获取对应的所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第一预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
优选地，本发明的一种记忆板件智能测试方法还包括：
A5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第一管脚的连接节点瞬间导通；
A6、调整所述基准信号以获取对应的所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第二预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
优选地，本发明的一种记忆板件智能测试方法还包括：
B5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第十管脚的连接节点导通；
B6、获取所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第三预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
优选地，本发明的一种记忆板件智能测试方法还包括：
C5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第十二管脚的连接节点导通；
C6、获取所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第四预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
优选地，本发明的一种记忆板件智能测试方法还包括：
D5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第四管脚的连接节点断开；
D6、调整所述基准信号以获取对应的所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第五预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
实施本发明的一种板件智能测试系统及方法，具有以下有益效果：操作方便，能够大大减少记忆板件测试过程的工作量，保证记忆板件测试可靠。
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是本发明一种记忆板件智能测试系统一实施例的逻辑框图；
图2是本发明一种记忆板件智能测试系统另一实施例的逻辑框图；
图3是本发明显示单元显示界面一实施例的示意图；
图4是本发明一种记忆板件智能测试方法一实施例的流程图；
图5是本发明一种记忆板件智能测试方法一实施例的流程图；
图6是本发明一种记忆板件智能测试方法另一实施例的流程图；
图7是本发明一种记忆板件智能测试方法另一实施例的流程图；
图8是本发明一种记忆板件智能测试方法另一实施例的流程图。
为了对本发明的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本发明的具体实施方式。
如图1所示，在本发明的一种记忆板件智能测试系统第一实施例中，包括：供电单元121，基准信号输出单元122，输出检测单元123，与待测板件可插拔安装的板件插座110，连接板件插座110的第一属性管脚的第一阵列开关131，连接板件插座110的第二属性管脚与供电单元121的第二阵列开关132，连接板件插座110的第三属性管脚与基准信号输出单元122的第三阵列开关133，连接板件插座110的第四属性管脚与输出检测单元123的第四阵列开关134，分别连接第一阵列开关131、第二阵列开关132、第三阵列开关133和第四阵列开关134的控制单元140，分别连接基准信号输出单元122、输出检测单元123和控制单元140的通信单元140，连接通信单元140的显示单元160；其中，显示单元160显示与第一阵列开关131、第二阵列开关132、第三阵列开关133和第四阵列开关134的连接节点分别对应的虚拟节点161，且显示单元160在虚拟节点161被触发时生成或清除虚拟节点之间的连线，控制单元140在虚拟节点161被触发时触发第一阵列开关131、第二阵列开关132、第三阵列开关133和/或第四阵列开关134中对应的连接节点连接或断开；显示单元160还用于控制基准信号输出单元122输出基准信号并通过输出检测单元123获取与基准信号对应的检测信号，以根据检测信号得到待测板件的测试结果。具体的，在测试系统中，待测板件与板件插座110配合并与板件插座110可插拔安装，在对待测板件进行测试时，将待测板件置于板件插座110上以构成待测板件的测试电路。待测板件的测试电路包括供电单元121、基准信号输出单元122、输出检测单元123。其中供电单元121用于在待测板件测试时给待测板件及其他电路提供供电电源，基准信号输出单元122用来提供待测板件测试时需要的基准信号，输出检测单元123用于在待测板件测试过程中，基准信号输入时获取对应的输出信号。供电单元121通过第二阵列开关132连接板件插座110的供电管脚即第二属性管脚，其可以理解供电单元121通过第二阵列开关132控制其与待测板件的导通或关断。基准信号输出单元122通过第三阵列开关123连接板件插座110的基准信号输入管脚也即第三属性管脚，其可以理解为基准信号输出单元122通过第三阵列开关133控制其与待测板件的导通或关断。输出检测单元123通过第四阵列开关134连接板件插座110的测试信号输出管脚也即第四属性管脚，也可以理解为输出检测单元123通过第四阵列开关134控制其与待测板件的导通或关断。同时，在待测板件测试过程中，其部分管脚需要相互连接，即待测板件这些需要互相连接的管脚通过第一阵列开关131控制其之间的导通或关断，即第一阵列开关131连接板件插座110的第一属性管脚。由于板件插座110与待测板件之间关系是一一对应的，因此板件插座110的管脚属性由待测板件的需要连接的电路属性决定。在测试过程中，可以通过控制单元140控制第一阵列开关131、第二阵列开关132、第三阵列开关133和第四阵列开关134按照需要动作，显示单元160通过通信单元150控制基准信号输出单元122输出需要的基准信号，同时显示单元160通过通信单元150接收输出检测单元123获取的检测信号并对待测板件的测试结果进行确认。其可以通过各个阵列开关的中各开关节点的导通与关断的设置，形成待测板件的不同的电性连接关系。不同的电性连接关系对应待测板件的不同功能或指标的测试。控制单元140通过通信单元150连接显示单元160，显示单元160上显示有虚拟节点161，虚拟节点161与各个阵列开关的连接节点为一一对应的关系。阵列开关的连接节点理解为阵列开关用来外接电路的连接节点。当需要设置板件插座110、供电单元121、基准信号输出单元123和输出检测单元123的端点之间的某一连接关系时，其可以触发端点对应的阵列开关的连接节点对应的虚拟节点161，例如依次点击两个虚拟节点161，当该两个虚拟节点161之间为未连线状态时，则会在显示单元160上生成该两个虚拟节点161之间的连线。同时控制单元140在该虚拟节点161被触发时，并当该两个虚拟节点161之间为未连线状态时，触发阵列开关130中与连接节点对应的开关节点连接，这样就形成与显示单元160上虚拟节点161连线对应的实际的测试电路中的电性连接关系。当需要断开板件插座110、供电单元121、基准信号输出单元122和输出检测单元123端点之间的某一连接关系时，其可以依次触发端点对应的连接节点对应的虚拟节点161，例如依次点击两个虚拟节点161，当该两个虚拟节点161之间为已连线状态时，则会在显示单元160上清除该两个虚拟节点161之间的连线。同时控制单元140在该虚拟节点161被触发时，并当该两个虚拟节点161之间为已连线状态时，触发对应阵列开关中与连接节点对应的开关节点断开，这样就断开了与显示单元160上虚拟节点161连线对应的实际的测试电路中的电性连接关系。其可以理解，控制单元140和显示单元160在接收到虚拟节点161被触发的触发指令时，其均可以对当前的虚拟节点161之间是否已有连线进行判断，并根据判断结果分别触发实际阵列开关动作和在显示单元160上进行生成或者清除连线的动作，实现显示单元160的显示状态与实际的测试系统中电性连接关系的一致性。待测板件测试过程中，通过触发与第二阵列开关132对应的虚拟节点161，使得供电单元121对待测板件供电，触发与第三阵列开关133对应的虚拟节点161，对待测板件输入基准信号，通过触发与第四阵列开关134对应的虚拟节点161，使得输出检测单元123获取待测板件的输出信号，通过测试输出信号或者测试输出信号与基准信号的关系判定待测板件的性能指标。触发与第一阵列开关131对应的虚拟节点161，即可以实现待测板件内部工作管脚之间的连接或断开关系。各阵列开关与虚拟节点161的对应关系为上文描述虚拟节点161与阵列开关的连接节点对应。第一阵列开关131、第二阵列开关132、第三阵列开关133和第四阵列开关134可以根据需要进行选择性设置。
可选的，如图2和图3所示，供电单元121包括用于提供第一供电电压的第一供电单元1211和用于提供第二供电电压的第二供电单元1212，第一供电单元1211和第二供电单元1212分别连接第二阵列开关132的不同连接节点；具体的，供电单元121包括提供不同电压输出的不同单元模块，其第一供电单元1211提供30V左右的电压输出即第一供电电压，第二供电单元1212提供48V左右的电压输出即第二供电电压，第一供电单元1211和第二供电单元1212相互不影响，其可以对应第二阵列开关132不同的连接节点，其在显示单元160中对应不同虚拟节点161，例如分别对应虚拟节点P1和虚拟节点P2，由第二阵列开关132分别控制。同时为降低电源噪声，防止相互串扰，第一供电单元1211和第二供电单元1212可以采用工频变压器。另外，为了保障待测板件和供电单元121的安全，其供电单元均设有限流保护功能。
可选的，输出检测单元123包括用于获取待测板件的电压检测信号的输出电压检测单元1231和用于获取待测板件的电流检测信号的输出电流检测单元1232，输出电压检测单元1231和输出电流检测单元1231分别连接第四阵列开关134的不同连接节点。即，在待测板件测试过程中，其可以分别对电压检测信号和电流检测信号进行检测，以对待测板件的性能进行分析。可通过输出电压检测单元1231获取对应的电压检测信号和通过输出电流检测单元1232获取对应的电流检测信号。输出电压检测单元1231和输出电流检测单元1232分别对应第四阵列开关134的不同连接节点，其在显示单元中对应不同虚拟节点，例如对应分别对应虚拟节点C1和虚拟节点C2，其由第四阵列开关134分别控制。
在一实施例中，输出电压检测单元1231采用高稳定的基准和24位高精度模数转换芯片，对测量信号进行防高压误入保护，其最高允许60VDC，电压检测信号进入信号调理电路，调理电路通过高性能运放和金属箔电阻将电压检测信号调理到适合ADC测量芯片适合的电压后，再由ADC直接测量。测量速率可设置，最高采集速率100点/秒。输出电压检测单元内设有单片机控制电压检测信号获取过程。为了防止信号串扰，输出电压检测单元1231同通信单元150间也采用了光电隔离芯片进行数据通信。
在一实施例中，输出电流检测单元1232采用高稳定的基准和24 位高精度模数转换芯片，对测量信电流信号先进行限流保护，即最大电流不超过<30mA，防止大电流对后继电路的破坏。同时通过250欧姆电阻将电流转换成电压后再后进入信号调理电路，调理电路采用高性能运放和金属箔电阻，将输入信号调理到适合ADC测量芯片适合的电压后，再由ADC直接测量。测量速率可设置，最高采集速率100点/秒。输出电流检测单元内设置单片机控制电流检测信号获取过程，为了防止信号串扰，输出电流检测单元1232同通信单元150间也采用了光电隔离芯片进行数据通信。
可选的，基准信号输出单元122包括用于生成第一基准电压的第一基准信号输出单元1221，用于输出第二基准电压生成第二基准信号输出单元1222和用于生成第三基准电压的第三基准信号输出单元1223；第一基准信号输出单元1221、第二基准信号输出单元1222和第三基准信号输出单元1223分别连接第三阵列开关133的不同连接节点。即，基准信号输出单元122包括采用独立供电的第一基准信号输出单元1221、第二基准信号输出单元1222和第三基准信号输出单元1223，分别用来提供三路不同的基准电压输出，对每一基准信号输出单元均设有输出短路保护功能，其内部采用高稳定、低温漂的电压基准和16位高精度数模转换芯片，将数模芯片输出信号进行信号调理，调理电路采用高性能运放和金属箔电阻，调理后输出电压再进行限流保护后输出，其允许输出电流不超过10mA。其可以通过各基准信号输出单元的输出端口获取其输出的基准电压。各基准信号输出单元内设有单片机控制各基准电压的输出过程，同时为了防止信号串扰，各基准信号输出单元同通信单元150间采用了光电隔离芯片进行数据通信。第一基准信号输出单元1221、第二基准信号输出单元1222和第三基准信号输出单元1223分别对应第三阵列开关133的不同连接节点，其在显示单元160中对应不同虚拟节点161，例如分别对应虚拟节点I1、虚拟节点I2和虚拟节点I3，其由第三阵列开关134分别控制。
可选的，显示单元160控制第一基准信号输出单元1221生成的第一基准电压为第一固定值；显示单元160控制第二基准信号输出单元1222生成的第二基准电压为第二固定值；显示单元160控制第三基准信号输出单元1223生成的第三基准电压满足一预设函数。其中第一基准电压和第二基准电压可以为固定值，其取值范围为0-6V。第三基准电压为函数电压，即第三基准信号输出单元1231可以在显示单元160的控制下实现斜坡电压输出，最高输出速率100点/秒。
另，如图4所示，本发明的一种记忆板件智能测试方法，应用于如上面的记忆板件智能测试系统，包括：
S1、根据第一阵列开关、第二阵列开关、第三阵列开关和第四阵列开关在显示单元的显示界面生成与第一阵列开关、第二阵列开关、第三阵列开关和第四阵列开关的连接节点分别对应的虚拟节点；
S2、触发虚拟节点生成触发指令，以在显示界面生成或清除虚拟节点之间的连线，以触发第一阵列开关、第二阵列开关、第三阵列开关和/或第四阵列开关中对应的连接节点连接或断开；
S3、控制基准信号输出单元输出基准信号并通过输出检测单元获取与基准信号对应的检测信号；
S4、根据检测信号得到待测板件的测试结果。
具体的，通过上面描述的记忆板件智能测试系统，其通过触发虚拟节点形成虚拟节点之间的连接关系，并生成对应的连线，同时与虚拟节点对应的各个阵列开关根据虚拟节点的触发指令动作，形成对应的连接节点之间的连接关系，形成最终的连接电路连接关系。在该电路连接关系下，控制基准信号输出单元输出基准信号并通过输出检测单元获取与基准信号对应的检测信号；根据检测信号得到待测板件的测试结果，完成对待测板件的测试。其具体还根据板件智能测试系统进行各种操作，以实现对不同的待测板件的测试。
可选的，如图5所示，本发明的一种记忆板件智能测试方法还包括：
A1、触发与第二阵列开关对应的虚拟节点，以使第二阵列开关中连接供电单元的连接节点分别与连接板件插座的第二十管脚和第四管脚的连接节点导通、连接板件插座的第十五管脚和第十六管脚的连接节点分别接地；
A2、触发与第四阵列开关对应的虚拟节点，以使第四阵列开关中连接板件插座的第二十四管脚的连接节点与连接输出电压检测单元的连接节点导通、连接板件插座的第十八管脚的连接节点与连接输出电流检测单元的连接节点导通；
A3、触发与第三阵列开关对应的虚拟节点，以使第三阵列开关中连接板件插座的第二十二管脚的连接节点与连接基准信号输出单元的连接节点导通；
A4、调整基准信号以获取对应的电压检测信号和电流检测信号，并确认电压检测信号和电流检测信号是否满足第一预设条件，若是，则判定待测板件的测试结果为合格，若否，则判定待测板件的测试结果为不合格。
具体的，可以通过以下过程对ME板件进行自动状态测试，通过触发虚拟节点实现ME板件的管脚T20和管脚T4与供电单元导通连接实现+28V电压输入，ME板件的管脚T15和管脚T16接地，ME板件的管脚T22与基准信号输出单元接收基准信号的输入，输出电压检测单元与ME板件的管脚T24导通连接实现电压检测信号的获取，输出电流检测单元与ME板件的管脚T18导通连接实现电流检测信号的获取。在测试过程中，调整基准信号输出单元使得基准信号按照一定规则变化，并获取对应的电流检测信号和电压检测信号，通过电流检测信号和电压检测信号确认ME板件的输出精度是否满足要求即电压检测信号和电流检测信号是否满足第一预设条件。当基准信号为为1~5V电压信号，电流检测信号和电压检测信号分别为1~5V电压和4~20mA电流信号。电压检测信号的精度要求为其偏差不超过为0.5%，电流检测信号的精度为其偏差不超过3%。具体的可以参照下表：
可选的，如图6所示，本发明的一种记忆板件智能测试方法还包括：
A5、触发与第二阵列开关对应的虚拟节点，以使第二阵列开关中连接供电单元的连接节点与连接板件插座的第一管脚的连接节点瞬间导通；
A6、调整基准信号以获取对应的电压检测信号和电流检测信号，并确认电压检测信号和电流检测信号是否满足第二预设条件，若是，则判定待测板件的测试结果为合格，若否，则判定待测板件的测试结果为不合格。
具体的，在上面的基础上通过以下过程对ME板件切换为手动状态测试，保持通过触发虚拟节点实现的ME板件的管脚T20和管脚T4与供电单元导通连接实现+28V电压输入，ME板件的管脚T15和管脚T16接地，ME板件的管脚T22与基准信号输出单元接收基准信号的输入，输出电压检测单元与ME板件的管脚T24导通连接实现电压检测信号的获取，输出电流检测单元与ME板件的管脚T18导通连接实现电流检测信号的获取。通过触发虚拟节点触发ME板件的管脚T1与供电单元进行瞬间导通，瞬间导通也可以理解为瞬时导通，即对ME板件的管脚T1进行快速上电触发后断开供电。在测试过程中，调整基准信号输出单元使得基准信号按照一定规则变化，并获取对应的电流检测信号和电压检测信号，通过电流检测信号和电压检测信号确认ME板件的输出是否满足要求即电压检测信号和电流检测信号是否满足第二预设条件。此时的电流检测信号和电压检测信应当不随基准信号的变化而变化，其为固定值。即当电流检测信号和电压检测信应当不随基准信号的变化而变化时，判定待测板件的测试结果为合格，若发生变化，则判定待测板件的测试结果为不合格。
可选的，如图6所示，本发明的一种记忆板件智能测试方法还包括：
B5、触发与第二阵列开关对应的虚拟节点，以使第二阵列开关中连接供电单元的连接节点与连接板件插座的第十管脚的连接节点导通；
B6、获取电压检测信号和电流检测信号，并确认电压检测信号和电流检测信号是否满足第三预设条件，若是，则判定待测板件的测试结果为合格，若否，则判定待测板件的测试结果为不合格。
具体的，在上面的基础上通过以下过程对ME板件切换为自动增加状态测试，保持通过触发虚拟节点实现的ME板件的管脚T20和管脚T4与供电单元导通连接实现+28V电压输入，ME板件的管脚T15和管脚T16接地，ME板件的管脚T22与基准信号输出单元接收基准信号的输入，输出电压检测单元与ME板件的管脚T24导通连接实现电压检测信号的获取，输出电流检测单元与ME板件的管脚T18导通连接实现电流检测信号的获取。通过触发虚拟节点实现ME板件的管脚T10与供电单元导通连接实现+28V电压输入，在测试过程中，基准信号输出单元使得基准信号为一固定输入，并获取对应的电流检测信号和电压检测信号，通过电流检测信号和电压检测信号确认ME板件的输出是否满足要求即电压检测信号和电流检测信号是否满足第三预设条件。此时的电流检测信号和电压检测信应当自动增加。即当电流检测信号和电压检测信应当自动增加时，判定待测板件的测试结果为合格，若不自动增加，则判定待测板件的测试结果为不合格。
可选的，如图7所示，本发明的一种记忆板件智能测试方法还包括：
C5、触发与第二阵列开关对应的虚拟节点，以使第二阵列开关中连接供电单元的连接节点与连接板件插座的第十二管脚的连接节点导通；
C6、获取电压检测信号和电流检测信号，并确认电压检测信号和电流检测信号是否满足第四预设条件，若是，则判定待测板件的测试结果为合格，若否，则判定待测板件的测试结果为不合格。
具体的，在上面的基础上通过以下过程对ME板件切换为自动减少状态测试。保持通过触发虚拟节点实现的ME板件的管脚T20和管脚T4与供电单元导通连接实现+28V电压输入，ME板件的管脚T15和管脚T16接地，ME板件的管脚T22与基准信号输出单元接收基准信号的输入，输出电压检测单元与ME板件的管脚T24导通连接实现电压检测信号的获取，输出电流检测单元与ME板件的管脚T18导通连接实现电流检测信号的获取。通过触发虚拟节点实现ME板件的管脚T12与供电单元导通连接实现+28V电压输入，在测试过程中，基准信号输出单元使得基准信号为一固定输入，并获取对应的电流检测信号和电压检测信号，通过电流检测信号和电压检测信号确认ME板件的输出是否满足要求即电压检测信号和电流检测信号是否满足第四预设条件。此时的电流检测信号和电压检测信应当自动减少。即当电流检测信号和电压检测信应当自动减少时，判定待测板件的测试结果为合格，若不自动减少，则判定待测板件的测试结果为不合格。
可选的，如图8所示，本发明的一种记忆板件智能测试方法还包括：
D5、触发与第二阵列开关对应的虚拟节点，以使第二阵列开关中连接供电单元的连接节点与连接板件插座的第四管脚的连接节点断开；
D6、调整基准信号以获取对应的电压检测信号和电流检测信号，并确认电压检测信号和电流检测信号是否满足第五预设条件，若是，则判定待测板件的测试结果为合格，若否，则判定待测板件的测试结果为不合格。
具体的，在上面的基础上通过以下过程对ME板件切换为自动与手动的状态切换测试。保持通过触发虚拟节点实现的ME板件的管脚T20与供电单元导通连接实现+28V电压输入的连接， ME板件的管脚T15和管脚T16接地，ME板件的管脚T22与基准信号输出单元接收基准信号的输入，输出电压检测单元与ME板件的管脚T24导通连接实现电压检测信号的获取，输出电流检测单元与ME板件的管脚T18导通连接实现电流检测信号的获取。通过触发虚拟节点实现ME板件的管脚T4与供电单元导通连接实现+28V电压输入的断开。在测试过程中，基准信号输出单元使得基准信号变化时，并获取对应的电流检测信号和电压检测信号，通过电流检测信号和电压检测信号确认ME板件的输出是否满足要求即电压检测信号和电流检测信号是否满足第五预设条件。此时的电流检测信号和电压检测信应当不发生变化。即当电流检测信号和电压检测信不发生变化时，判定待测板件的测试结果为合格，若发生变化时，则判定待测板件的测试结果为不合格。
还可以理解，在测试过程中对待测板件的测试结果判定为合格或不合格是对具体的测试项目的判断，其测试结果合格，为该项测试项目测试合格，当测试不合格，也理解为该测试项的测试结果不合格。
可以理解的，以上实施例仅表达了本发明的优选实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制；应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，可以对上述技术特点进行自由组合，还可以做出若干变形和改进，这些都属于本发明的保护范围；因此，凡跟本发明权利要求范围所做的等同变换与修饰，均应属于本发明权利要求的涵盖范围。
Claims (10)
- 一种记忆板件智能测试系统，其特征在于，包括：供电单元，基准信号输出单元，输出检测单元，与待测板件可插拔安装的板件插座，连接所述板件插座的第一属性管脚的第一阵列开关，连接所述板件插座的第二属性管脚与所述供电单元的第二阵列开关，连接所述板件插座的第三属性管脚与所述基准信号输出单元的第三阵列开关，连接所述板件插座的第四属性管脚与所述输出检测单元的第四阵列开关，分别连接所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关的控制单元，分别连接所述基准信号输出单元、所述输出检测单元和所述控制单元的通信单元，连接所述通信单元的显示单元；其中，所述显示单元显示与所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关的连接节点分别对应的虚拟节点，且所述显示单元在所述虚拟节点被触发时生成或清除所述虚拟节点之间的连线，所述控制单元在所述虚拟节点被触发时触发所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和/或所述第四阵列开关中对应的连接节点连接或断开；所述显示单元还用于控制所述基准信号输出单元输出基准信号并通过所述输出检测单元获取与所述基准信号对应的检测信号，以根据所述检测信号得到所述待测板件的测试结果。
- 根据权利要求1所述的记忆板件智能测试系统，其特征在于，所述供电单元包括用于提供第一供电电压的第一供电单元和用于提供第二供电电压的第二供电单元，所述第一供电单元和所述第二供电单元分别连接所述第二阵列开关的不同连接节点；和/或所述输出检测单元包括用于获取所述待测板件的电压检测信号的输出电压检测单元和用于获取所述待测板件的电流检测信号的输出电流检测单元，所述输出电压检测单元和所述输出电流检测单元分别连接所述第四阵列开关的不同连接节点。
- 根据权利要求1所述的记忆板件智能测试系统，其特征在于，所述基准信号输出单元包括用于生成第一基准电压的第一基准信号输出单元，用于输出第二基准电压生成第二基准信号输出单元和用于生成第三基准电压的第三基准信号输出单元；所述第一基准信号输出单元、所述第二基准信号输出单元和所述第三基准信号输出单元分别连接所述第三阵列开关的不同连接节点。
- 根据权利要求3所述的记忆板件智能测试系统，其特征在于，所述显示单元控制所述第一基准信号输出单元生成的所述第一基准电压为第一固定值；所述显示单元控制所述第二基准信号输出单元生成的所述第二基准电压为第二固定值；所述显示单元控制所述第三基准信号输出单元生成的所述第三基准电压满足一预设函数。
- 一种记忆板件智能测试方法，其特征在于，应用于如权利要求1-4任意一项所述的记忆板件智能测试系统，包括：S1、根据所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关在所述显示单元的显示界面生成与所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和所述第四阵列开关的连接节点分别对应的虚拟节点；S2、触发所述虚拟节点生成触发指令，以在所述显示界面生成或清除所述虚拟节点之间的连线，并根据所述触发指令控制所述第一阵列开关、所述第二阵列开关、所述第三阵列开关和/或所述第四阵列开关中对应的连接节点连接或断开；S3、控制所述基准信号输出单元输出基准信号并通过所述输出检测单元获取与所述基准信号对应的检测信号；S4、根据所述检测信号得到所述待测板件的测试结果。
- 根据权利要求5所述的记忆板件智能测试方法，其特征在于，所述测试方法还包括：A1、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点分别与连接所述板件插座的第二十管脚和第四管脚的连接节点导通、连接所述板件插座的第十五管脚和第十六管脚的连接节点分别接地；A2、触发与所述第四阵列开关对应的虚拟节点，以使所述第四阵列开关中连接所述板件插座的第二十四管脚的连接节点与连接所述输出电压检测单元的连接节点导通、连接所述板件插座的第十八管脚的连接节点与连接所述输出电流检测单元的连接节点导通；A3、触发与所述第三阵列开关对应的虚拟节点，以使所述第三阵列开关中连接所述板件插座的第二十二管脚的连接节点与连接所述基准信号输出单元的连接节点导通；A4、调整所述基准信号以获取对应的所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第一预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
- 根据权利要求6所述的记忆板件智能测试方法，其特征在于，所述测试方法还包括：A5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第一管脚的连接节点瞬间导通；A6、调整所述基准信号以获取对应的所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第二预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
- 根据权利要求6所述的记忆板件智能测试方法，其特征在于，所述测试方法还包括：B5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第十管脚的连接节点导通；B6、获取所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第三预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
- 根据权利要求6所述的记忆板件智能测试方法，其特征在于，所述测试方法还包括：C5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第十二管脚的连接节点导通；C6、获取所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第四预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
- 根据权利要求6所述的记忆板件智能测试方法，其特征在于，所述测试方法还包括：D5、触发与所述第二阵列开关对应的虚拟节点，以使所述第二阵列开关中连接所述供电单元的连接节点与连接所述板件插座的第四管脚的连接节点断开；D6、调整所述基准信号以获取对应的所述电压检测信号和所述电流检测信号，并确认所述电压检测信号和所述电流检测信号是否满足第五预设条件，若是，则判定所述待测板件的测试结果为合格，若否，则判定所述待测板件的测试结果为不合格。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP21848780.9A EP4184186A4 (en) | 2020-07-29 | 2021-02-08 | INTELLIGENT TESTING SYSTEM AND METHOD FOR DATA PANEL |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010745358.2A CN112083309B (zh) | 2020-07-29 | 2020-07-29 | 一种记忆板件智能测试系统及方法 |
| CN202010745358.2 | 2020-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2022021837A1 true WO2022021837A1 (zh) | 2022-02-03 |
Family
ID=73735619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2021/076108 WO2022021837A1 (zh) | 2020-07-29 | 2021-02-08 | 一种记忆板件智能测试系统及方法 |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP4184186A4 (zh) |
| CN (1) | CN112083309B (zh) |
| WO (1) | WO2022021837A1 (zh) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112083310A (zh) * | 2020-07-29 | 2020-12-15 | 中广核核电运营有限公司 | 一种板件智能测试系统 |
| CN112083309B (zh) * | 2020-07-29 | 2023-11-17 | 中广核核电运营有限公司 | 一种记忆板件智能测试系统及方法 |
| CN112067970B (zh) * | 2020-07-29 | 2023-11-17 | 中广核核电运营有限公司 | 一种带校验功能的板件智能测试系统 |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4724379A (en) * | 1984-03-14 | 1988-02-09 | Teradyne, Inc. | Relay multiplexing for circuit testers |
| FR2561480B1 (fr) * | 1984-03-14 | 1994-05-20 | Teradyne Inc | Procede et circuit de multiplexage a relais pour un appareil de test de circuits |
| US5898703A (en) * | 1997-06-05 | 1999-04-27 | Mitsubishi Denki Kabushiki Kaisha | Device and method for testing integrated circuit including bi-directional test pin for receiving control data and outputting observation data |
| US20130342236A1 (en) * | 2012-06-26 | 2013-12-26 | Samsung Electronics Co., Ltd. | Test interface boards and test systems |
| CN105510763A (zh) * | 2016-02-25 | 2016-04-20 | 珠海全志科技股份有限公司 | 集成电路管脚测试装置 |
| CN106950489A (zh) * | 2017-04-06 | 2017-07-14 | 芯海科技（深圳）股份有限公司 | 一种电量检测及失效判定系统及方法 |
| CN108226751A (zh) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | 一种多处理器协同芯片性能评估系统及方法 |
| CN112067970A (zh) * | 2020-07-29 | 2020-12-11 | 中广核核电运营有限公司 | 一种带校验功能的板件智能测试系统 |
| CN112083310A (zh) * | 2020-07-29 | 2020-12-15 | 中广核核电运营有限公司 | 一种板件智能测试系统 |
| CN112083309A (zh) * | 2020-07-29 | 2020-12-15 | 中广核核电运营有限公司 | 一种记忆板件智能测试系统及方法 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5861743A (en) * | 1995-12-21 | 1999-01-19 | Genrad, Inc. | Hybrid scanner for use in an improved MDA tester |
| US7552024B2 (en) * | 2004-03-08 | 2009-06-23 | Kelbon Richard G | Circuit board diagnostic operating center |
| JP2006153793A (ja) * | 2004-12-01 | 2006-06-15 | Agilent Technol Inc | 半導体特性測定装置用スイッチングマトリックス |
| TWI439711B (zh) * | 2011-10-03 | 2014-06-01 | Star Techn Inc | 切換矩陣器及其半導體元件特性之測試系統 |
| KR102294127B1 (ko) * | 2014-07-15 | 2021-08-26 | 삼성전자주식회사 | 누설 전류 감지 장치 및 이를 포함하는 비휘발성 메모리 장치 |
| CN104345262B (zh) * | 2014-10-27 | 2017-06-27 | 华南农业大学 | 一种通用电路板测试系统 |
| CN104965165A (zh) * | 2015-07-13 | 2015-10-07 | 江苏杰进微电子科技有限公司 | 一种小微型集成电路可靠性测试仪及测试方法 |
| CN107238788B (zh) * | 2016-03-29 | 2019-12-27 | 深圳市汇顶科技股份有限公司 | 基于矩阵电容板的触控芯片测试系统及其测试方法 |
| CN110047555B (zh) * | 2018-01-15 | 2021-05-07 | 长鑫存储技术有限公司 | 确定虚拟信号传输线数量的测试装置、方法及半导体存储器 |
| CN208736976U (zh) * | 2018-09-11 | 2019-04-12 | 深圳创维－Rgb电子有限公司 | 电路板的测试电路及测试仪器 |
| CN109256748B (zh) * | 2018-10-16 | 2023-12-05 | 深圳圣诺医疗设备股份有限公司 | 有记忆功能的过温保护电路 |
| CN209927976U (zh) * | 2019-03-27 | 2020-01-10 | 珠海格莱克斯自动化设备有限公司 | 一种电路板检测系统 |
-
2020
- 2020-07-29 CN CN202010745358.2A patent/CN112083309B/zh active Active
-
2021
- 2021-02-08 WO PCT/CN2021/076108 patent/WO2022021837A1/zh unknown
- 2021-02-08 EP EP21848780.9A patent/EP4184186A4/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4724379A (en) * | 1984-03-14 | 1988-02-09 | Teradyne, Inc. | Relay multiplexing for circuit testers |
| FR2561480B1 (fr) * | 1984-03-14 | 1994-05-20 | Teradyne Inc | Procede et circuit de multiplexage a relais pour un appareil de test de circuits |
| US5898703A (en) * | 1997-06-05 | 1999-04-27 | Mitsubishi Denki Kabushiki Kaisha | Device and method for testing integrated circuit including bi-directional test pin for receiving control data and outputting observation data |
| US20130342236A1 (en) * | 2012-06-26 | 2013-12-26 | Samsung Electronics Co., Ltd. | Test interface boards and test systems |
| CN105510763A (zh) * | 2016-02-25 | 2016-04-20 | 珠海全志科技股份有限公司 | 集成电路管脚测试装置 |
| CN106950489A (zh) * | 2017-04-06 | 2017-07-14 | 芯海科技（深圳）股份有限公司 | 一种电量检测及失效判定系统及方法 |
| CN108226751A (zh) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | 一种多处理器协同芯片性能评估系统及方法 |
| CN112067970A (zh) * | 2020-07-29 | 2020-12-11 | 中广核核电运营有限公司 | 一种带校验功能的板件智能测试系统 |
| CN112083310A (zh) * | 2020-07-29 | 2020-12-15 | 中广核核电运营有限公司 | 一种板件智能测试系统 |
| CN112083309A (zh) * | 2020-07-29 | 2020-12-15 | 中广核核电运营有限公司 | 一种记忆板件智能测试系统及方法 |
Non-Patent Citations (1)
| Title |
|---|
| See also references of EP4184186A4 * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP4184186A4 (en) | 2024-01-24 |
| CN112083309A (zh) | 2020-12-15 |
| CN112083309B (zh) | 2023-11-17 |
| EP4184186A1 (en) | 2023-05-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2022021837A1 (zh) | 一种记忆板件智能测试系统及方法 | |
| TWI418978B (zh) | 測試裝置 | |
| WO2022021839A1 (zh) | 一种带校验功能的板件智能测试系统 | |
| WO2016127558A1 (zh) | 连接检测方法、装置及射频连接器 | |
| US8724474B2 (en) | Telecommunication port testing apparatus | |
| CN103546114A (zh) | 根据从设备的上拉电压调整总线上拉电压的电路及其方法 | |
| CN106708231A (zh) | 算力芯片电压稳定控制装置和算力板系统电压稳定控制装置 | |
| CN115420942A (zh) | 一种电能测量装置以及供电系统 | |
| CN210573652U (zh) | 一种服务器断电装置 | |
| CN207910201U (zh) | 一种用于仪器设备航空插座测试连接的辅助装置 | |
| TWI729631B (zh) | 阻抗量測方法 | |
| CN209624707U (zh) | 一种ict测试仪系统 | |
| CN209979709U (zh) | 一种基于pxie架构的电源卡 | |
| WO2018133005A1 (zh) | 一种can信号线对地短路测试装置 | |
| CN108152593B (zh) | 便携式全自动电接口直流电阻测试系统及测试方法 | |
| CN110542825A (zh) | 一种产品布线完好性的测试设备和测试方法 | |
| CN219657674U (zh) | 一种便于航空插头校线、绝缘测试装置 | |
| CN111312000A (zh) | 一种电能计量装置的校验培训装置 | |
| CN111693754A (zh) | 通信模组pin脚电压检测装置、设备及方法 | |
| CN113009223A (zh) | 阻抗量测方法 | |
| CN109101376A (zh) | 一种usb测速装置及系统 | |
| CN111596115B (zh) | 电阻补偿测量输出电流的方法及其转换电路 | |
| CN221148900U (zh) | 机车信号设备线缆快速检测装置 | |
| CN221224897U (zh) | 一种航天器电气系统功能检测装置 | |
| CN216411947U (zh) | 一种自动刹车控制组件测试台 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21848780 Country of ref document: EP Kind code of ref document: A1 |
|
| ENP | Entry into the national phase |
Ref document number: 2021848780 Country of ref document: EP Effective date: 20230214 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |