WO2022017079A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022017079A1
WO2022017079A1 PCT/CN2021/100217 CN2021100217W WO2022017079A1 WO 2022017079 A1 WO2022017079 A1 WO 2022017079A1 CN 2021100217 W CN2021100217 W CN 2021100217W WO 2022017079 A1 WO2022017079 A1 WO 2022017079A1
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Prior art keywords
wafer
conductive
layer
groove
orthographic projection
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English (en)
French (fr)
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吴秉桓
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/398,127 priority Critical patent/US12009324B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure and a method for forming the same.
  • the backside area of the wafer is often used to lay out the conductive layer.
  • the current process chooses to form additional layers such as a dielectric layer on the backside surface of the wafer, and then in the additionally formed film layer or The conductive layer is prepared on the side away from the crystal back, so as to realize the isolation of the conductive layer and the wafer.
  • Some embodiments of the present application provide a semiconductor structure and a method for forming the same, which are beneficial to reduce the overall thickness and overall package height of the semiconductor structure, and reduce the deformation stress borne by the wafer.
  • some embodiments of the present application provide a method for forming a semiconductor structure, including: providing a wafer, the wafer has a front surface and a back surface opposite to the front surface; patterning the back surface of the wafer to form A groove extending from the back to the front; a dielectric layer is formed on the bottom and sidewalls of the groove; a conductive layer filling the groove is formed on the dielectric layer.
  • the dielectric layer is coplanar with the back surface of the wafer.
  • the process steps of forming the dielectric layer include: forming a first dielectric film filling the groove and covering the backside of the wafer; performing a planarization process to remove the first dielectric film covering the backside of the wafer A dielectric film is formed to form a second dielectric film; and an etching process is performed on the second dielectric film to form the dielectric layer.
  • the method further includes: forming a blocking layer on the back of the wafer, the blocking layer is used for blocking metal ions from migrating into the wafer. .
  • the blocking layer is coplanar with the conductive layer.
  • the wafer has conductive plugs extending from the front surface to the back surface, and the bottom surface of the conductive plugs is located in the wafer; the forming the grooves includes: forming and exposing the conductive plugs A groove in at least part of the surface of the plug.
  • the wafer in a direction perpendicular to the back surface of the wafer, has a plurality of the conductive plugs with different bottom surface heights; the forming the groove includes: forming and exposing each of the conductive plugs at least Grooves on part of the surface.
  • the dielectric layer exposes at least part of the surface of the conductive plug.
  • the orthographic projection of the bottom surface of the conductive plug is located in the orthographic projection of the top surface of the conductive layer, or, the orthographic projection of the bottom surface of the conductive plug is the same as that of the conductive plug.
  • the orthographic projection of the top surface of the layer partially overlaps, or the orthographic projection of the bottom surface of the conductive plug does not overlap with the orthographic projection of the top surface of the conductive layer.
  • some embodiments of the present application further provide a semiconductor structure, including: a wafer, the wafer has a front surface and a back surface opposite to the front surface; a groove, the groove is located in the wafer, the the groove extends from the back to the front; a dielectric layer, the dielectric layer covers the bottom and sidewalls of the groove; a conductive layer, the conductive layer is located on the side of the dielectric layer away from the wafer and fill the groove.
  • the semiconductor structure further includes: a blocking layer covering the back of the wafer, and the blocking layer is used for blocking metal ions from migrating into the wafer.
  • the wafer has conductive plugs extending from the front surface to the back surface, and the bottom surface of the conductive plugs is located in the wafer; the conductive layer is connected to the conductive plugs, and is vertically In the direction of the back of the wafer, the orthographic projection of the bottom surface of the conductive plug is located within the orthographic projection of the top surface of the conductive layer, or the orthographic projection of the bottom surface of the conductive plug is the same as the top surface of the conductive layer.
  • the orthographic projections partially overlap, or, the orthographic projections of the bottom surface of the conductive plug and the orthographic projection of the top surface of the conductive layer do not overlap.
  • the wafer has a plurality of conductive plugs with different bottom heights, and each of the conductive plugs is connected to one of the conductive layers.
  • the patterned crystal back is selected to form a groove, and a conductive layer is filled in the groove.
  • the setting of the conductive layer will not increase the overall thickness of the wafer, and there is no need to form an additional film on the surface of the crystal back, which is beneficial to
  • the overall package height of the semiconductor structure is reduced, and the deformation stress on the backside of the wafer is reduced, so that the wafer has better structural stability.
  • the conductive layer can function as a redistribution layer or pad, thereby adjusting the position and shape of the solder joints on the back of the wafer to meet higher requirements. Packaging process requirements.
  • 1 to 3 are schematic structural diagrams of a semiconductor structure
  • 4 to 7 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application
  • FIGS. 8 to 11 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to another embodiment of the present application.
  • the conductive layer 12 is formed on the back surface 101 of the wafer 10 , and there is at least one dielectric layer 11 between the conductive layer 12 and the wafer 10 .
  • the materials and functions of different dielectric layers 11 are different.
  • the above arrangement of the conductive layer 12 has the following problems: the dielectric layer 11 and the conductive layer 12 stacked on the back surface 101 will increase the overall thickness of the semiconductor structure, thereby increasing the overall package size; in addition, the stacked film layers will exert stress on the wafer 10 , thereby causing the wafer 10 to undergo stress deformation.
  • the stress applied to the wafer 10 by the film layer stacked on the back surface 101 mainly comes from the internal stress of the stacked film layer itself, and the internal stress of the stacked film layer.
  • Thermal stress and thermal stress between stacked layers and wafer 10 mainly comes from the difference in thermal expansion coefficients of adjacent films.
  • the embodiments of the present application provide a semiconductor structure and a method for forming the same.
  • a groove is formed by patterning a crystal back, and a conductive layer is filled in the groove, so that the configuration of the conductive layer does not increase the overall thickness of the semiconductor structure.
  • no additional film layers are stacked on the backside of the wafer, which is beneficial to reduce the overall package size of the semiconductor structure and reduce the stress on the wafer.
  • 4 to 11 are schematic structural diagrams corresponding to each step of the method for fabricating the semiconductor structure provided by the embodiments of the present application.
  • a wafer 20 is provided, the wafer 20 has a front side 202 and a back side 201 opposite the front side 202; the back side 201 of the wafer 20 is patterned to form grooves 21 extending from the back side 201 to the front side 202.
  • the backside 201 is further thinned to reduce the overall thickness of the wafer 20 and increase the flexibility of the wafer 20, thereby reducing the overall package size of the semiconductor structure , and enables the wafer 20 to withstand greater stress deformation.
  • the thinned wafer 20 is more prone to stress deformation while being able to withstand greater stress and deformation.
  • the deformation stress enables the wafer 20 and the semiconductor structure including the wafer 20 to have high structural stability.
  • the structural features of the grooves 21 define the structural features of the conductive layer subsequently formed in the grooves 21 to a certain extent, when the grooves 21 are formed, the structural characteristics of the grooves 21 need to be subject to the actual packaging process requirements of the conductive layers. limited.
  • the actual packaging process of the conductive layers is related to the specific components to be packaged, and the actual packaging process requirements include the relationship between the distance between adjacent conductive layers and the minimum distance between solder balls and the arrangement of multiple conductive layers.
  • the groove 21 is filled with dielectric material to form a second dielectric film 22 ;
  • the process steps of the second dielectric film 22 include: forming a first dielectric film that fills the groove 21 and covers the back surface 201 ; performing a planarization process on the first dielectric film to remove the first dielectric film covering the back surface 201 to form a second dielectric film membrane 22.
  • the dielectric material is used to coat the subsequently formed conductive layer, so as to prevent the leakage of the conductive layer from negatively affecting the wafer 20 . Since the subsequently formed conductive layer is filled in the groove 21 , the first dielectric film on the back surface 201 does not have the function of preventing leakage, and is a redundant material. Removing the first dielectric film covering the back surface 201 is beneficial to avoid stress applied to the wafer 20 by the redundant first dielectric film, so that the wafer 20 receives less stress and the wafer 20 has higher structural stability .
  • the blocking layer 23 is provided not only for blocking the metal material deposited on the backside 201 during the formation of the conductive layer, but also for blocking other metal materials in contact with the backside 201 after packaging.
  • an etching process is performed on the second dielectric film 22 (refer to FIG. 5 ) to form a dielectric layer 24 .
  • An etching process is performed on the second dielectric film 22 and the blocking layer 23 to form a dielectric layer 24 covering the bottom and sidewalls of the groove 21 .
  • the thickness of the dielectric layer 24 in different directions perpendicular to the surface of the groove 21 may be the same or different. Since the conductive layer filling the groove 21 is to be formed on the dielectric layer 24 later, the structural features of the conductive layer can be adjusted by controlling the thickness of the dielectric layer 24 in different directions, including the position, shape, and vertical direction to the back surface. Orthographic projection area in the 201 direction.
  • the dielectric layer 24 is coplanar with the back surface 201 of the wafer 20 , that is, the top surface of the dielectric layer 24 and the back surface 201 are on the same plane, and the dielectric layer 24 is completely located in the wafer 20 . In this way, it is beneficial to prevent the dielectric layer 24 from exerting additional deformation stress on the back surface 201 , so as to ensure that the wafer 20 has better structural stability.
  • a conductive layer 26 filling the grooves 21 is formed on the dielectric layer 24 .
  • a first barrier layer 25 and a conductive layer 26 are sequentially formed on the dielectric layer 24, and the first barrier layer 25 is used to block the migration of metal ions in the conductive layer 26 into the wafer 20; in other embodiments Among them, a film layer for relieving the stress of the conductive layer or adhering the conductive layer can also be arranged between the conductive layer and the dielectric layer.
  • the conductive layer 26 and the blocking layer 23 are coplanar, that is, the top surface of the conductive layer 26 and the top surface of the blocking layer 23 are on the same plane, and the conductive layer 26 is completely located in the stack formed by the blocking layer 23 and the wafer 20 In the structure, in this way, the conductive layer 26 will not apply deformation stress to the back surface 201 through the blocking layer 23 or directly, so as to ensure that the wafer 20 has high structural stability.
  • the backside of the wafer is patterned to form a groove, and a conductive layer is filled in the groove.
  • the arrangement of the conductive layer will not increase the overall thickness of the semiconductor structure, and there is no need to install a leakage-preventing device on the backside of the wafer.
  • the dielectric layer is beneficial to reduce the overall thickness of the semiconductor structure and reduce the stress on the backside of the wafer, so that the packaged semiconductor structure has a smaller package size and better structural stability.
  • FIGS. 8 to 11 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to another embodiment of the present application. For the same or corresponding forming steps as in the previous embodiment, reference may be made to the corresponding description of the previous method embodiment, which will not be repeated below.
  • a wafer 30 is provided, the wafer 30 has a front surface 302 and a back surface 301 opposite to the front surface 302; the wafer 30 has conductive plugs 31 extending from the front surface 302 to the back surface 301, and the bottom surface of the conductive plugs 31 is located in the wafer 30. Inside the circle 30.
  • the bottom surface of the conductive plug 31 is located in the wafer 30 .
  • the position of the solder joint on the back surface 301 of the wafer can be changed by adjusting the position of the conductive layer connected to the conductive plug 31 in the future, so that the semiconductor structure can be soldered.
  • the point distribution meets the actual packaging process requirements.
  • the surface of the conductive plug 31 is covered with a second barrier layer 311 and a first dielectric layer 312.
  • the second barrier layer 311 is used to block the metal ions in the conductive plug 31 from migrating into the wafer 30.
  • the first dielectric layer 312 is used for In order to prevent the leakage of the conductive plugs 31 from negatively affecting the wafer 30 .
  • the material of the second barrier layer 311 is a conductive material, such as tantalum; in other embodiments, the material of the second barrier layer is a dielectric material, such as silicon carbonitride.
  • the back surface 301 is patterned to form grooves 32 exposing the conductive plugs 31 .
  • the back surface 301 is patterned, and part of the first dielectric layer 312 covering the conductive plug 31 is removed to form a groove 32 exposing the second barrier layer 311 . Since the material of the second barrier layer 311 is a conductive material, the retention of the second barrier layer 311 will not affect the electrical connection between the conductive plug 31 and the subsequently formed conductive layer.
  • whether to remove the second barrier layer 311 is mainly considered based on the following two points: first, the conductivity of the second barrier layer 311 , the conductivity of the second barrier layer 311 is higher than that of the conductive plug 31 .
  • the second barrier layer 311 may not be removed; secondly, the second barrier layer 311
  • the removal process is time-consuming.
  • the removal process time includes changing the etchant, changing the reaction chamber, etching time, and cleaning time before etching, etc.
  • the groove 32 exposes the bottom surface and part of the sidewall of the second barrier layer 311 ; in other embodiments, the groove only exposes the bottom surface of the blocking layer.
  • Exposing part of the sidewall of the second barrier layer 311 is beneficial to increase the contactable area between the barrier layer 311 and the conductive layer.
  • the increase of the contact area can reduce the resistance between the conductive plug 31 and the conductive layer, increase the maximum current flow between the conductive plug 31 and the conductive layer, and ensure that the power device connected to the solder joint can work effectively;
  • the increase of the contact area is beneficial to expand the position selection range of the conductive layer, that is, the conductive layer can be connected to the sidewall of the second barrier layer 311 instead of the bottom surface.
  • the orthographic projection of the conductive layer It can no longer overlap with the orthographic projection of the second barrier layer 311 , and the conductive layer can have a smaller orthographic projection area, so as to better meet the packaging process requirements.
  • the wafer 30 has a plurality of conductive plugs 31.
  • the bottom surfaces of the plurality of conductive plugs 31 have the same height; in other embodiments, the bottom surfaces of the plurality of conductive plugs have the same height.
  • the heights are different, and when the grooves are formed, the grooves expose at least part of the surface of each conductive plug.
  • a conductive layer 34 filling the grooves 32 is formed on the second dielectric layer 33 .
  • the conductive layer 34 can be used as both a redistribution layer (RDL) and a pad (PAD).
  • the redistribution layer is used to change the position of the solder joints, so as to realize the rearrangement of the solder joints, so that the The arrangement meets the requirements of the actual packaging process.
  • the orthographic projection of the second barrier layer 311 is located within the orthographic projection of the top surface of the conductive layer 34 , or, the orthographic projection of the second barrier layer 311 and the top surface of the conductive layer 34
  • the orthographic projection of the second barrier layer 311 partially overlaps, or the orthographic projection of the second barrier layer 311 does not overlap with the orthographic projection of the top surface of the conductive layer 34 .
  • the orthographic projection of the second barrier layer 311 can either overlap with the orthographic projection of the top surface of the conductive layer 34, or it can be The orthographic projections of the top surface of the conductive layer 34 do not overlap, which depends on the structure of the second dielectric layer 33 .
  • the partial overlap includes two cases of area overlap and boundary overlap.
  • the conductive layer 34 serving as the redistribution layer is not located on the side of the blocking layer 35 away from the wafer 30, the setting of the conductive layer 34 will not apply deformation stress to the back surface 301 through the blocking layer 35 or directly;
  • the conductive layer 34 as the redistribution layer is located inside the stacked structure composed of the barrier layer 35 and the wafer 30, the barrier layer or the stress buffer layer for isolating the wafer 30 and the conductive layer 34 are also It is located inside the stacked structure, that is, the arrangement of the barrier layer or stress buffer layer will not increase the package height of the semiconductor structure, nor will it impose additional deformation stress on the wafer 30; in addition, due to the conductive layer 34 and the barrier layer 35 are coplanar, and the conductive layer 34 itself exists as a solder joint, so there is no need to provide an additional planarization layer to protect the conductive layer 34 and define the position of the new solder joint, which is conducive to further reducing the package height of the semiconductor structure. Deformation stress on
  • the conductive layer is connected to the conductive plug located in the wafer, the conductive layer can be used as a pad or a redistribution layer, the pad can change the size and shape of the solder joint, and the redistribution layer can change the position of the solder joint , so that the arrangement and distribution of the solder joints on the back of the wafer and the shape and size meet the actual packaging process requirements.
  • the embodiments of the present application further provide a semiconductor structure, which can be fabricated by using the above-mentioned method for forming the semiconductor structure.
  • the semiconductor structure includes: a wafer 30 having a front side 302 and a back side 301 opposite to the front side 302; a groove 32, the groove 32 being located in the wafer 30, the groove 32 extending from the back side 301 to the front side 302
  • the dielectric layer 33, the dielectric layer 33 covers the bottom and sidewalls of the groove 32; the conductive layer 34, the conductive layer 34 is located on the side of the dielectric layer 33 away from the wafer 30 and fills the groove 32.
  • the semiconductor structure further includes a blocking layer 35 .
  • the blocking layer 35 covers the back surface 301 of the wafer.
  • the blocking layer 35 is used to block metal ions from migrating into the wafer 30 .
  • the wafer 30 has conductive plugs 31 extending from the front surface 302 to the back surface 301, and the bottom surface of the conductive plugs 31 is located in the wafer 30; the conductive layer 34 is connected to the conductive plugs 31, and is perpendicular to the wafer.
  • the orthographic projection of the bottom surface of the conductive plug 31 is located within the orthographic projection of the top surface of the conductive layer 34, or, the orthographic projection of the bottom surface of the conductive plug 31 overlaps with the orthographic projection of the top surface of the conductive layer 34, or, the conductive
  • the orthographic projection of the bottom surface of the plug 31 does not coincide with the orthographic projection of the top surface of the conductive layer 34 .
  • the wafer 30 has a plurality of conductive plugs 31, the bottom surfaces of the plurality of conductive plugs 31 have the same height, and each conductive plug 31 is connected to a conductive layer 34; in other embodiments, a plurality of conductive plugs 31 The height of the bottom surface of the plug is different.
  • the conductive layer is located in the wafer, and there is no need to provide an additional dielectric layer on the backside of the wafer to prevent leakage of the conductive layer.
  • the film layer exerts greater deformation stress on the backside of the wafer, so that the semiconductor structure has a smaller package size and higher structural stability.

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Abstract

本申请实施例提供一种半导体结构及其形成方法，半导体结构及其形成方法包括：提供晶圆，晶圆具有正面和与正面相对的背面；图形化晶圆的背面，形成自背面向正面延伸的凹槽；在凹槽底部和侧壁形成介质层；在介质层上形成填充凹槽的导电层。

Description

半导体结构及其形成方法
交叉引用
本申请要求于2020年7月21日递交的名称为“半导体结构及其形成方法”、申请号为2020107074529的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体结构及其形成方法。
背景技术
目前，在芯片结构的3D封装上，常会利用晶圆的晶背区域来布局导电层。而为了降低导电层漏电以及导电层内的金属离子迁移等负面情况对晶圆背面区域的影响，当前工艺选择在晶背表面额外形成介质层等膜层，然后再在额外形成的膜层内或者在其远离晶背的一侧制备导电层，从而实现导电层和晶圆的隔离。
发明内容
本申请部分实施例提供一种半导体结构及其形成方法，有利于减小半导体结构的整体厚度和整体封装高度，以及减小晶圆所承受的变形应力。
为解决上述问题，本申请部分实施例提供一种半导体结构的形成方法，包括：提供晶圆，所述晶圆具有正面和与所述正面相对的背面；图形化所述晶圆的背面，形成自所述背面向所述正面延伸的凹槽；在所述凹槽底部和侧壁形成介质层；在所述介质层上形成填充所述凹槽的导电层。
另外，所述介质层与所述晶圆背面共面。
另外，形成所述介质层的工艺步骤，包括：形成填充满所述凹槽且覆盖所述晶圆背面的第一介质膜；进行平坦化工艺，去除覆盖所述晶圆背面的所述第一介质膜，形成第二介质膜；对所述第二介质膜进行刻蚀工艺，形成所述介质层。
另外，在进行所述平坦化工艺之后，且在进行所述刻蚀工艺之前，还包 括：在所述晶圆背面形成阻拦层，所述阻拦层用于阻拦金属离子迁移至所述晶圆内。
另外，所述阻拦层与所述导电层共面。
另外，所述晶圆内具有自所述正面向所述背面延伸的导电插塞，所述导电插塞的底面位于所述晶圆内；所述形成凹槽，包括：形成暴露所述导电插塞至少部分表面的凹槽。
另外，在垂直于所述晶圆背面的方向上，所述晶圆内具有底面高度不同的多个所述导电插塞；所述形成凹槽，包括：形成暴露每一所述导电插塞至少部分表面的凹槽。
另外，所述介质层暴露出所述导电插塞至少部分表面。
另外，在垂直于所述晶圆背面的方向上，所述导电插塞底面的正投影位于所述导电层顶面的正投影内，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影部分重合，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影不重合。
相应地，本申请部分实施例还提供一种半导体结构，包括：晶圆，所述晶圆具有正面和与所述正面相对的背面；凹槽，所述凹槽位于所述晶圆内，所述凹槽自所述背面向所述正面延伸；介质层，所述介质层覆盖所述凹槽底部和侧壁；导电层，所述导电层位于所述介质层远离所述晶圆的一侧且填充所述凹槽。
另外，所述半导体结构还包括：阻拦层，所述阻拦层覆盖所述晶圆背面，所述阻拦层用于阻拦金属离子迁移至所述晶圆内。
另外，所述晶圆内具有自所述正面向所述背面延伸的导电插塞，所述导电插塞的底面位于所述晶圆内；所述导电层与所述导电插塞连接，在垂直于所述晶圆背面的方向上，所述导电插塞底面的正投影位于所述导电层顶面的正投影内，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影部分重合，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影不重合。
另外，所述晶圆内具有底部高度不同的多个导电插塞，每一所述导电插塞与一所述导电层连接。
与现有技术相比，本申请部分实施例提供的技术方案具有以下优点：
上述技术方案中，选择图形化晶背以形成凹槽，并在凹槽内填充导电层，导电层的设置不会增加晶圆的整体厚度，且晶背表面无需形成额外的膜层，有利于减小半导体结构的整体封装高度，以及减小晶圆背面所承受的变形应力，使得晶圆具有较好的结构稳定性。
另外，通过控制导电插塞底面和导电层顶面的正投影关系，可使导电层起到重布线层或者焊盘的作用，从而调整晶圆背面焊点的位置和形状，进而满足更高的封装工艺要求。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至图3为半导体结构的结构示意图；
图4至图7为本申请一实施例提供的半导体结构的形成方法各步骤对应的结构示意图；
图8至图11为本申请另一实施例提供的半导体结构的形成方法各步骤对应的结构示意图。
具体实施方式
参考图1至图3，导电层12形成于晶圆10背面101上，且在导电层12和晶圆10之间具有至少一层介质层11。当具有多层介质层11时，不同介质层11的材料和功能不同。
上述导电层12的设置存在以下问题：堆叠在背面101上的介质层11和导电层12会增加半导体结构的整体厚度，进而增加整体封装尺寸；此外，堆叠的膜层会对晶圆10施加应力，进而使得晶圆10发生应力变形。
堆叠在背面101上的膜层(以下简称堆叠膜层，堆叠膜层包括介质层11和导电层12)对晶圆10施加的应力主要来源于堆叠膜层自身的内应力、堆叠膜层内部的热应力以及堆叠膜层和晶圆10之间的热应力。其中，内应力大多是在膜层生长过程中产生的，例如晶体失配、杂质接入、晶格重构以及相变等，而 热应力主要来源于相邻膜层的热膨胀系数差异。
为解决上问题，本申请实施例提供一种半导体结构及其形成方法，通过图案化晶背形成凹槽，且在凹槽内填充导电层，使得导电层的设置不会增加半导体结构的整体厚度，也不会在晶圆背面额外堆叠膜层，有利于减小半导体结构的整体封装尺寸以及减小晶圆受到的应力。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图4至图11为本申请实施例提供的半导体结构的制作方法各步骤对应的结构示意图。
参考图4，提供晶圆20，晶圆20具有正面202和与正面202相对的背面201；图形化晶圆20的背面201，形成自背面201向正面202延伸的凹槽21。
本实施例中，在对背面201进行图形化之前，还对背面201进行减薄处理，以减小晶圆20的整体厚度以及增加晶圆20的柔韧性，进而减小半导体结构的整体封装尺寸，以及使得晶圆20能够承受更大的应力变形。
需要说明的是，减薄后的晶圆20在能够承受更大的应力变形的同时，也更容易发生应力变形，因此，在减薄晶圆20的基础上，减小晶圆20所承受的变形应力，才能使得晶圆20以及包含晶圆20的半导体结构具有较高的结构稳定性。
由于凹槽21的结构特征一定程度上限定了后续形成于凹槽21内的导电层的结构特征，因此在形成凹槽21时，凹槽21的结构特征需要受到导电层的实际封装工艺要求的限定。其中，导电层的实际封装工艺与进行封装的具体部件有关，实际封装工艺要求包括相邻导电层之间的间距与焊料球最小间距的关系以及多个导电层的排列方式。
参考图5，在凹槽21内填充满介质材料，形成第二介质膜22；在背面201形成阻拦层23，阻拦层23用于阻拦金属离子迁移至晶圆20内。
第二介质膜22的工艺步骤包括：形成填充满凹槽21且覆盖背面201的第一介质膜；对第一介质膜进行平坦化工艺，去除覆盖背面201的第一介质膜，形成第二介质膜22。
介质材料用于包覆后续形成的导电层，以避免导电层漏电对晶圆20造成负面影响。由于后续形成的导电层填充于凹槽21内，因此位于背面201上的第一介质膜不具备防漏电的作用，属于多余材料。去除覆盖背面201的第一介电膜，有利于避免多余的第一介质膜对晶圆20施加应力，从而使得晶圆20受到的应力较小，以及使得晶圆20具有较高的结构稳定性。
本实施例中，阻拦层23的设置不仅用于阻拦导电层形成过程中沉积于背面201上的金属材料，还用于阻拦在进行封装后与背面201接触的其他金属材料。
参考图6，对第二介质膜22(参考图5)进行刻蚀工艺，形成介质层24。
对第二介质膜22和阻拦层23进行刻蚀工艺，形成覆盖凹槽21底部和侧壁的介质层24。
需要说明的是，介质层24在垂直于凹槽21表面的不同方向上的厚度可以相同也可以不同。由于后续要在介质层24上形成填充凹槽21的导电层，因此，可以通过控制介质层24在不同方向上的厚度，调整导电层的结构特征，结构特征包括位置、形状和在垂直于背面201方向上的正投影面积。
本实施例中，介质层24与晶圆20背面201共面，也就是说，介质层24顶面与背面201处于同一平面，介质层24完全位于晶圆20内。如此，有利于避免介质层24对背面201施加额外的变形应力，保证晶圆20具有较好的结构稳定性。
参考图7，在介质层24上形成填充凹槽21的导电层26。
本实施例中，在介质层24上依次形成第一阻障层25和导电层26，第一阻障层25用于阻拦导电层26中的金属离子向晶圆20内迁移；在其他实施例中，还可以在导电层和介质层之间设置用于缓解导电层的应力，或者，粘附导电层的膜层。
本实施例中，导电层26与阻拦层23共面，也就是说，导电层26顶面与 阻拦层23顶面处于同一平面，导电层26完全位于阻拦层23和晶圆20构成的叠层结构内，如此，导电层26不会通过阻拦层23或直接对背面201施加变形应力，保证晶圆20具有较高的结构稳定性。
本实施例中，图案化晶圆背面以形成凹槽，并在凹槽内填充导电层，导电层的设置不会增加半导体结构的整体厚度，，且无需在晶圆背面设置起防漏电作用的介质层，有利于减小半导体结构的整体厚度，以及减小晶圆背面所承受的应力，使得封装后的半导体结构具有较小的封装尺寸和较好的结构稳定性。
本申请另一实施例还提供一种半导体结构的形成方法，与前一实施例不同的是，本实施例中，晶圆内具有自正面向背面延伸的导电插塞，且导电插塞的底面位于晶圆内。以下将结合图8至图11进行详细说明，图8至图11为本申请另一实施例提供的半导体结构的形成方法各步骤对应的结构示意图。与上一实施例相同或者相应的形成步骤，可以参考上一方法实施例的相应说明，以下不做赘述。
参考图8，提供晶圆30，晶圆30具有正面302和与正面302相对的背面301；晶圆30内具有自正面302向背面301延伸的导电插塞31，导电插塞31的底面位于晶圆30内。
本实施例中，导电插塞31的底面位于晶圆30内，如此，后续可以通过调整与导电插塞31连接的导电层的位置，改变晶圆背面301的焊点位置，使得半导体结构的焊点分布满足实际封装工艺要求。
导电插塞31表面覆盖有第二阻障层311和第一介质层312，第二阻障层311用于阻拦导电插塞31内的金属离子向晶圆30内迁移，第一介质层312用于防止导电插塞31漏电对晶圆30造成负面影响。
本实施例中，第二阻障层311的材料为导电材料，例如钽；在其他实施例中，第二阻障层的材料为介质材料，例如碳氮化硅。
参考图9，对背面301进行图案化处理，形成暴露导电插塞31的凹槽32。
对背面301进行图案化处理，并去除包覆导电插塞31的部分第一介质层312形成暴露出第二阻障层311的凹槽32。由于第二阻障层311的材料为导电材料，因此第二阻障层311的保留不会影响导电插塞31与后续形成的导电层的 电连接。
在实际工艺过程中，主要基于以下两点考虑是否去除第二阻障层311：第一，第二阻障层311的电导率，第二阻障层311的电导率高于导电插塞31的电导率、或者高于后续形成的导电层的电导率、或者满足导电层和导电插塞31之间的电连接要求时，可不去除第二阻障层311；第二，第二阻障层311的去除工艺耗时，去除工艺时间包括更换刻蚀剂、更换反应腔室、刻蚀时间以及刻蚀前的清洗时间等，第二阻障层311的去除工艺耗时较长时，可根据当前的工艺周期要求以及其他标准要求确定是否去除阻拦层。
本实施例中，凹槽32暴露出第二阻障层311底面和部分侧壁；在其他实施例中，凹槽仅暴露出阻拦层底面。
暴露出第二阻障层311部分侧壁有利于增大阻拦层311和导电层的可接触区域。接触区域的增大可以减小导电插塞31与导电层之间电阻，增大导电插塞31与导电层之间的最大电流流量，保证与焊点连接的功率器件能够有效工作；此外，可接触区域的增加有利于扩大导电层的位置选择范围，即导电层可以与第二阻障层311侧壁连接而非与底面连接，如此，在垂直于背面301的方向上，导电层的正投影可以不再与第二阻障层311的正投影重合，导电层可以具有更小的正投影面积，从而更好地满足封装工艺要求。
本实施例中，晶圆30内具有多个导电插塞31，在垂直于背面301的方向上，多个导电插塞31的底面高度相同；在其他实施例中，多个导电插塞的底面高度不同，在形成凹槽时，凹槽暴露每一导电插塞的至少部分表面。
参考图10和图11，在第二介质层33上形成填充凹槽32的导电层34。
本实施例中，导电层34既可以作为重布线层(RDL)，也可以作为焊盘(PAD)，重布线层用于改变焊点位置，从而实现焊点的重新布局，以使焊点的排列满足实际封装工艺的要求。
具体来说，在垂直于背面301的方向上，第二阻障层311的正投影位于导电层34顶面的正投影内，或者，第二阻障层311的正投影与导电层34顶面的正投影部分重合，或者，第二阻障层311的正投影与导电层34顶面的正投影不重合。
需要说明的是，当导电层34作为重布线层与第二阻障层311电连接时，第二阻障层311的正投影既可以与导电层34顶面的正投影部分重合，也可以与导电层34顶面的正投影不重合，这取决于第二介质层33的结构。其中，部分重合包括区域重合和边界重合两种情况。
本实施例中，由于作为重布线层的导电层34并不位于阻拦层35背离晶圆30的一侧，因此导电层34的设置不会通过阻拦层35或者直接对背面301施加变形应力；此外，由于作为重布线层的导电层34位于阻拦层35和晶圆30构成的叠层结构内部，因此，用于隔离晶圆30和导电层34的阻障层或应力缓冲层等膜层也都位于叠层结构内部，即阻障层或应力缓冲层等膜层的设置不会增加半导体结构的封装高度，也不会对晶圆30施加额外的变形应力；此外，由于导电层34与阻拦层35共面，且导电层34本身就是作为焊点存在，因此不需要设置额外的平坦化层来保护导电层34和定义新焊点的位置，如此，有利于进一步减小半导体结构的封装高度和减小晶圆30背面受到的变形应力。
本实施例中，导电层与位于晶圆内的导电插塞连接，导电层可作为焊盘或者重布线层使用，焊盘可以改变焊点的大小和形状，重布线层能够改变焊点的位置，从而使得晶圆背面的焊点排列分布以及形状大小满足实际封装工艺要求。
相应地，本申请实施例还提供一种半导体结构，可采用上述半导体结构的形成方法制成。
参考图10，半导体结构包括：晶圆30，晶圆30具有正面302和与正面302相对的背面301；凹槽32，凹槽32位于晶圆30内，凹槽32自背面301向正面302延伸；介质层33，介质层33覆盖凹槽32底部和侧壁；导电层34，导电层34位于介质层33远离晶圆30的一侧且填充凹槽32。
本实施例中，半导体结构还包括阻拦层35，阻拦层35覆盖晶圆背面301，阻拦层35用于阻拦金属离子迁移至晶圆30内。
本实施例中，晶圆30内具有自正面302向背面301延伸的导电插塞31，导电插塞31的底面位于晶圆30内；导电层34与导电插塞31连接，在垂直于晶圆背面301的方向上，导电插塞31底面的正投影位于导电层34顶面的正投影内，或者，导电插塞31底面的正投影与导电层34顶面的正投影部分重合， 或者，导电插塞31底面的正投影与导电层34顶面的正投影不重合。
本实施例中，晶圆30内具有多个导电插塞31，多个导电插塞31的底面高度相同，每一导电插塞31与一导电层34连接；在其他实施例中，多个导电插塞的底面高度不同。
本实施例中，导电层位于晶圆内，晶圆背面无需设置额外的介质层以防止导电层漏电，如此，有利于避免介质层和导电层在背面堆叠而增加半导体结构整体厚度，以及避免堆叠的膜层对晶圆背面施加较大的形变应力，从而使得半导体结构具有较小的封装尺寸以及较高的结构稳定性。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (13)

  1. 一种半导体结构的形成方法，包括：
    提供晶圆，所述晶圆具有正面和与所述正面相对的背面；
    图形化所述晶圆的背面，形成自所述背面向所述正面延伸的凹槽；
    在所述凹槽底部和侧壁形成介质层；
    在所述介质层上形成填充所述凹槽的导电层。
  2. 根据权利要求1所述的形成方法，其中，所述介质层与所述晶圆背面共面。
  3. 根据权利要求1所述的形成方法，其中，形成所述介质层的工艺步骤，包括：形成填充满所述凹槽且覆盖所述晶圆背面的第一介质膜；进行平坦化工艺，去除覆盖所述晶圆背面的所述第一介质膜，形成第二介质膜；对所述第二介质膜进行刻蚀工艺，形成所述介质层。
  4. 根据权利要求3所述的形成方法，其中，在进行所述平坦化工艺之后，且在进行所述刻蚀工艺之前，还包括：在所述晶圆背面形成阻拦层，所述阻拦层用于阻拦金属离子迁移至所述晶圆内。
  5. 根据权利要求4所述的形成方法，其中，所述阻挡层与所述导电层共面。
  6. 根据权利要求1所述的形成方法，其中，所述晶圆内具有自所述正面向所述背面延伸的导电插塞，所述导电插塞的底面位于所述晶圆内；所述形成凹槽，包括：形成暴露所述导电插塞至少部分表面的凹槽。
  7. 根据权利要求6所述的形成方法，其中，在垂直于所述晶圆背面的方向上，所述晶圆内具有底面高度不同的多个所述导电插塞；所述形成凹槽，包括：形成暴露每一所述导电插塞至少部分表面的凹槽。
  8. 根据权利要求6所述的形成方法，其中，所述介质层暴露出所述导电插塞至少部分表面。
  9. 根据权利要求8所述的形成方法，其中，在垂直于所述晶圆背面的方向上，所述导电插塞底面的正投影位于所述导电层顶面的正投影内，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影部分重合，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影不重合。
  10. 一种半导体结构，包括：
    晶圆，所述晶圆具有正面和与所述正面相对的背面；
    凹槽，所述凹槽位于所述晶圆内，所述凹槽自所述背面向所述正面延伸；
    介质层，所述介质层覆盖所述凹槽底部和侧壁；
    导电层，所述导电层位于所述介质层远离所述晶圆的一侧且填充所述凹槽。
  11. 根据权利要求10所述的半导体结构，其中，还包括：阻拦层，所述阻拦层覆盖所述晶圆背面，所述阻拦层用于阻拦金属离子迁移至所述晶圆内。
  12. 根据权利要求10所述的半导体结构，其中，所述晶圆内具有自所述正面向所述背面延伸的导电插塞，所述导电插塞的底面位于所述晶圆内；所述导电层与所述导电插塞连接，在垂直于所述晶圆背面的方向上，所述导电插塞底面的正投影位于所述导电层顶面的正投影内，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影部分重合，或者，所述导电插塞底面的正投影与所述导电层顶面的正投影不重合。
  13. 根据权利要求12所述的半导体结构，其中，所述晶圆内具有底部高度不同的多个导电插塞，每一所述导电插塞与一所述导电层连接。
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