WO2022013677A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2022013677A1
WO2022013677A1 PCT/IB2021/055989 IB2021055989W WO2022013677A1 WO 2022013677 A1 WO2022013677 A1 WO 2022013677A1 IB 2021055989 W IB2021055989 W IB 2021055989W WO 2022013677 A1 WO2022013677 A1 WO 2022013677A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
transistor
arithmetic
wiring
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2021/055989
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
岡本佑樹
伊藤港
上妻宗広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US18/013,916 priority Critical patent/US20230297339A1/en
Priority to KR1020237004297A priority patent/KR20230038731A/ko
Priority to CN202180046426.9A priority patent/CN115735208A/zh
Priority to JP2022535980A priority patent/JP7583046B2/ja
Publication of WO2022013677A1 publication Critical patent/WO2022013677A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024192009A priority patent/JP7723821B2/ja
Priority to JP2025129610A priority patent/JP2025169289A/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/48—Analogue computers for specific processes, systems or devices, e.g. simulators
    • G06G7/60—Analogue computers for specific processes, systems or devices, e.g. simulators for living beings, e.g. their nervous systems ; for problems in the medical field
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • one aspect of the present invention is not limited to the above technical fields.
  • the technical fields of one aspect of the present invention disclosed in the present specification and the like include semiconductor devices, image pickup devices, display devices, light emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, and input / output devices.
  • Devices, their driving methods, or their manufacturing methods can be mentioned as an example.
  • SoC System on Chip
  • Typical architectures include Binary Neural Network (BNN) and Ternary Neural Network (TNN), which are particularly effective for circuit scale reduction and power consumption reduction (see, for example, Patent Document 1).
  • BNN Binary Neural Network
  • TNN Ternary Neural Network
  • AI technology is required to speed up arithmetic processing.
  • Integrating circuits is effective for speeding up arithmetic processing.
  • weight data also called weight parameters, filters, etc.
  • a storage circuit that stores weight data
  • necessary data such as weight data is read from the storage circuit to the arithmetic circuit via wiring such as bit wires.
  • the frequency of reading data such as weight data increases. Therefore, the charge / discharge energy of the bit line may increase, and the power consumption may increase.
  • the arithmetic circuit and the storage circuit are arranged alternately side by side, the area of the peripheral circuit may be significantly increased.
  • One aspect of the present invention is to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention is to provide a semiconductor device with improved arithmetic processing speed. Alternatively, one aspect of the present invention is to provide a miniaturized semiconductor device. Alternatively, one of the issues is to provide a semiconductor device having a new configuration.
  • one aspect of the present invention does not necessarily have to solve all of the above problems, as long as it can solve at least one problem. Moreover, the description of the above-mentioned problem does not prevent the existence of other problems. Issues other than these are self-evident from the description of the description, claims, drawings, etc., and the issues other than these should be extracted from the description of the specification, claims, drawings, etc. Is possible.
  • One aspect of the present invention is a first calculation block having a first storage circuit unit, a first calculation circuit unit, and a second calculation block having a second storage circuit unit and a second calculation circuit unit.
  • the first storage circuit unit has a first storage circuit that holds a plurality of first weight data
  • the second storage circuit unit has a plurality of second storage circuits. It has a second storage circuit that holds weight data
  • the first arithmetic circuit unit has a first arithmetic circuit, a first switching circuit, and a third switching circuit
  • the second arithmetic circuit unit has a second arithmetic circuit unit.
  • the first switching circuit has a function of giving any one of a plurality of first weight data to the first wiring, and a second.
  • the switching circuit has a function of giving any one of a plurality of second weight data to the second wiring, and the third switching circuit is given to the first weight data given to the first wiring or the second wiring.
  • It has a function of giving any one of the second weight data to the first arithmetic circuit, and the fourth switching circuit has the first weight data given to the first wiring or the second given to the second wiring.
  • It is a semiconductor device having a function of giving any one of weight data to the second arithmetic circuit.
  • One aspect of the present invention is a first calculation block having a first storage circuit unit, a first calculation circuit unit, and a second calculation block having a second storage circuit unit and a second calculation circuit unit.
  • the first storage circuit unit has a first storage circuit that holds a plurality of first weight data
  • the second storage circuit unit has a plurality of second storage circuits. It has a second storage circuit that holds weight data
  • the first arithmetic circuit unit has a first arithmetic circuit, a first switching circuit, and a third switching circuit
  • the second arithmetic circuit unit has a second arithmetic circuit unit.
  • the first switching circuit has a function of giving any one of a plurality of first weight data to the first wiring, and a second.
  • the switching circuit has a function of giving any one of a plurality of second weight data to the second wiring, and the operation of giving any one of the plurality of first weight data to the first wiring is a plurality of second weight data. It is performed in a period different from the operation of giving any one of the above to the second wiring, and the third switching circuit is of the first weight data given to the first wiring or the second weight data given to the second wiring.
  • the fourth switching circuit has either the first weight data given to the first wiring or the second weight data given to the second wiring.
  • the operation of giving the first weight data given to the first wiring to the first calculation circuit has a function of giving the second weight data given to the second wiring to the second calculation circuit. It is a semiconductor device that is performed in a period different from the given operation.
  • the first storage circuit unit is provided on a layer laminated on the layer having the first arithmetic circuit unit, and the second storage circuit unit is laminated on the layer having the second arithmetic circuit unit.
  • a semiconductor device provided in the layer to be formed is preferable.
  • the first arithmetic circuit and the second arithmetic circuit are preferably semiconductor devices that independently perform a product-sum calculation process.
  • the semiconductor device comprises a first storage circuit unit and a second storage circuit unit, each of which has a first transistor, and the first transistor has a semiconductor layer having a metal oxide in a channel forming region. preferable.
  • a semiconductor device containing In, Ga, and Zn as the metal oxide is preferable.
  • a semiconductor device in which the first arithmetic circuit unit and the second arithmetic circuit unit each have a second transistor, and the second transistor has a semiconductor layer having silicon in a channel forming region.
  • One aspect of the present invention can provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention can provide a semiconductor device with improved arithmetic processing speed. Alternatively, one aspect of the present invention can provide a miniaturized semiconductor device. Alternatively, it is possible to provide a semiconductor device having a new configuration.
  • 1A, 1B and 1C are diagrams illustrating a configuration example of a semiconductor device.
  • 2A, 2B, 2C and 2D are diagrams illustrating a configuration example of a semiconductor device.
  • 3A, 3B, and 3C are diagrams illustrating a configuration example of a semiconductor device.
  • 4A and 4B are diagrams illustrating a configuration example of a semiconductor device.
  • 5A and 5B are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 6 is a diagram illustrating a configuration example of a semiconductor device.
  • 7A and 7B are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 8 is a diagram illustrating a configuration example of a semiconductor device.
  • FIG. 9 is a diagram illustrating a configuration example of a semiconductor device.
  • FIGS. 10A and 10B are diagrams illustrating a configuration example of a semiconductor device.
  • 11A and 11B are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 12 is a diagram illustrating a configuration example of a semiconductor device.
  • FIG. 13 is a timing chart illustrating an operation example of the semiconductor device.
  • FIG. 14 is a diagram illustrating a configuration example of a semiconductor device.
  • FIG. 15 is a diagram illustrating a configuration example of a semiconductor device.
  • 16A and 16B are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 17 is a diagram illustrating a configuration example of an arithmetic processing system.
  • FIG. 18 is a diagram illustrating a configuration example of a CPU.
  • FIG. 19A and 19B are diagrams illustrating a configuration example of a CPU.
  • FIG. 20 is a timing chart showing an operation example of the CPU.
  • FIG. 21 is a diagram showing a configuration example of a transistor.
  • 22A and 22B are diagrams showing a configuration example of a transistor.
  • 23A and 23B are diagrams illustrating a configuration example of an integrated circuit.
  • 24A and 24B are diagrams illustrating application examples of integrated circuits.
  • 25A and 25B are diagrams illustrating an application example of an integrated circuit.
  • 26A, 26B and 26C are diagrams illustrating application examples of integrated circuits.
  • FIG. 27 is a diagram illustrating an application example of an integrated circuit.
  • the ordinal numbers "1st”, “2nd”, and “3rd” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like is regarded as another embodiment or the component referred to in “second” in the scope of claims. It is possible. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like may be omitted in other embodiments or in the scope of claims.
  • the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (eg, signals, voltages, circuits, elements, electrodes, wiring, etc.).
  • the code is used for identification such as "_1”, “_2”, “[n]", “[m, n]”. May be added and described.
  • the second wiring GL is described as wiring GL [2].
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • a semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of a semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optic device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.
  • FIG. 1A is a diagram for explaining the semiconductor device 10 which is one aspect of the present invention. Further, FIGS. 1B and 1C are diagrams for explaining a configuration example of a calculation block included in the semiconductor device 10.
  • the semiconductor device 10 has a function as an accelerator that executes a program (also called a kernel or a kernel program) called from a host program.
  • the semiconductor device 10 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in a neural network, parallel processing of floating-point operations in science and technology calculations, and the like.
  • the semiconductor device 10 has a plurality of calculation blocks 21.
  • the calculation block 21 has a storage circuit unit 30 (also referred to as a memory cell array) and a calculation circuit unit 40.
  • the storage circuit unit 30 and the arithmetic circuit unit 40 are provided in different layers in a direction substantially perpendicular to the xy plane in the figure (in the z direction in FIG. 1A). That is, the storage circuit unit 30 and the arithmetic circuit unit 40 are provided in a stacked manner.
  • approximately vertical means a state in which they are arranged at an angle of 85 degrees or more and 95 degrees or less.
  • the X direction, the Y direction, and the Z direction shown in FIGS. 1A and the like are directions orthogonal to or intersecting each other. Further, the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.
  • the plurality of arithmetic blocks shown in FIG. 1A are roughly classified into two or more blocks having different operations and connection relationships.
  • a plurality of arithmetic blocks will be described as an odd-numbered arithmetic block unit 20_O and an even-numbered arithmetic block unit 20_E, but the configuration may be divided into three or more blocks.
  • the arithmetic block in the arithmetic block unit 20_O may be referred to as an arithmetic block 21_O.
  • the arithmetic block in the arithmetic block unit 20_E may be referred to as an arithmetic block 21_E.
  • the arithmetic block 21_O and the arithmetic block 21_E have a storage circuit unit 30 and an arithmetic circuit unit 40, respectively, as shown in FIGS. 1B and 1C.
  • the explanations of each other can be appropriately used for the parts common to each other.
  • the storage circuit unit 30 has a plurality of storage circuits 31.
  • the storage circuit unit 30 may be a memory cell array, and the storage circuit 31 may be a memory cell.
  • Writing and reading of data to the storage circuit 31 is controlled by the drive circuit 12 and the drive circuit 13.
  • the drive circuit 12 and the drive circuit 13 are also referred to as a data control circuit.
  • the storage circuit 31 included in the storage circuit unit 30 has a transistor (OS transistor) having an oxide semiconductor in the channel forming region.
  • the data stored (retained) by the storage circuit 31 is data (weight data) corresponding to the weight parameter used in the product-sum operation processing of the neural network.
  • weight data may be analog data.
  • the weight data may be configured to perform arithmetic processing using 1-bit data (that is, ‘1’ or ‘0’ data), or may be configured to perform arithmetic processing using multi-bit data.
  • the weight data may be supplied by using a number of wires corresponding to the number of bits.
  • the storage circuit 31 included in the storage circuit unit 30 can have a NOSRAM circuit configuration.
  • NOSRAM registered trademark
  • NOSRAM refers to a memory in which the memory cell is a 2-transistor type (2T) or 3-transistor type (3T) gain cell and the access transistor is an OS transistor.
  • the OS transistor has an extremely small leakage current, that is, the current flowing between the source and drain in the off state.
  • the NOSRAM can be used as a non-volatile memory by holding a charge corresponding to the data in the storage circuit using the characteristic that the leakage current is extremely small.
  • NOSRAM can read the held data without destroying it (non-destructive reading), it is suitable for parallel processing of the product-sum operation of the neural network in which the data reading operation is repeated many times.
  • a memory having an OS transistor such as NOSRAM or DOSRAM (hereinafter, also referred to as OS memory) is suitable. Since the bandgap of the metal oxide that functions as an oxide semiconductor is 2.5 eV or more, the OS transistor has a minimum off current. As an example, voltage 3.5V between the source and the drain, at at room temperature (25 °C), 1 ⁇ less than 10 -20 A state current per channel width 1 [mu] m, less than 1 ⁇ 10 -22 A, or 1 ⁇ 10 It can be less than -24A. Therefore, the OS memory has an extremely small amount of charge leaked from the holding node via the OS transistor. Therefore, since the OS memory can function as a non-volatile storage circuit, power gating of the semiconductor device 10 becomes possible.
  • OS memory can function as a non-volatile storage circuit, power gating of the semiconductor device 10 becomes possible.
  • Semiconductor devices with high density and integrated transistors may generate heat due to the drive of the circuit. Due to this heat generation, the temperature of the transistor rises, which may change the characteristics of the transistor, resulting in a change in field effect mobility and a decrease in operating frequency. Since the OS transistor has higher thermal resistance than the Si transistor, the field effect mobility does not easily change due to the temperature change, and the operating frequency does not easily decrease. Further, the OS transistor tends to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage even when the temperature rises. Therefore, by using the OS transistor, stable operation can be performed in a high temperature environment.
  • the metal oxides applied to the OS transistor are Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is: Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) and the like.
  • M is: Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf
  • oxides containing indium and zinc include aluminum, gallium, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. , Magnesium, etc. may be included, or a plurality of species may be contained.
  • the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystal portion such as CAAC-OS, CAC-OS, and nc-OS.
  • CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor ductor.
  • CAC-OS is an abbreviation for Cloud-Aligned Composite oxide semiconductor ductor.
  • nc-OS is an abbreviation for nanocrystalline oxide semiconductor ductor.
  • CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain.
  • the strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.
  • the CAC-OS has a function of flowing electrons (or holes) as carriers and a function of not flowing electrons as carriers. By separating the function of flowing electrons and the function of not flowing electrons, both functions can be maximized. That is, by using CAC-OS in the channel formation region of the OS transistor, both a high on current and an extremely low off current can be realized.
  • OS transistors Since metal oxides have a large bandgap, electrons are not easily excited, and the effective mass of holes is large, OS transistors may be less prone to avalanche collapse than general Si transistors. .. Therefore, for example, deterioration of hot carriers due to avalanche breakdown can be suppressed. By suppressing hot carrier deterioration, it is possible to drive an OS transistor with a high drain voltage.
  • the OS transistor is a storage type transistor that has a large number of electrons as carriers. Therefore, the influence of DIBL (Drain-Induced Barrier Lowering), which is one of the short-channel effects, is smaller than that of an inverting transistor (typically, a Si transistor) having a pn junction. That is, the OS transistor has a higher resistance to the short channel effect than the Si transistor.
  • DIBL Drain-Induced Barrier Lowering
  • the OS transistor Since the OS transistor has high resistance to the short channel effect, the channel length can be reduced without deteriorating the reliability of the OS transistor, so that the degree of integration of the circuit can be increased by using the OS transistor. As the channel length becomes finer, the drain electric field becomes stronger, but as mentioned above, the OS transistor is less likely to undergo avalanche breakdown than the Si transistor.
  • the OS transistor has high resistance to the short channel effect, it is possible to make the gate insulating film thicker than the Si transistor. For example, even in a fine transistor having a channel length and a channel width of 50 nm or less, it may be possible to provide a thick gate insulating film of about 10 nm. By thickening the gate insulating film, the parasitic capacitance can be reduced, so that the operating speed of the circuit can be improved. Further, by making the gate insulating film thicker, the leakage current through the gate insulating film is reduced, which leads to a reduction in static current consumption.
  • the semiconductor device 10 has the storage circuit 31 which is the OS memory, so that the data can be held even if the supply of the power supply voltage is stopped. Therefore, power gating of the semiconductor device 10 becomes possible, and power consumption can be significantly reduced.
  • the storage circuit unit 30 of the calculation block 21_O may be referred to as a first storage circuit unit. Further, the storage circuit unit 30 of the calculation block 21_E may be referred to as a second storage circuit unit. Further, the storage circuit 31 of the storage circuit unit 30 of the calculation block 21_O may be referred to as a first storage circuit. Further, the storage circuit 31 of the storage circuit unit 30 of the calculation block 21_E may be referred to as a second storage circuit. Further, the weight data stored in the storage circuit 31 of the storage circuit unit 30 of the calculation block 21_O may be referred to as the first weight data. Further, the weight data stored in the storage circuit 31 of the storage circuit unit 30 of the calculation block 21_E may be referred to as a second weight data. The first weight data is weight data different from the second weight data.
  • the layer having the arithmetic circuit unit 40 has a latch circuit 41, a switching circuit 42, a buffer circuit 43_O (43_E), a switching circuit 44, and an arithmetic circuit 45.
  • Control and processing such as data input / output in the arithmetic circuit unit 40 are controlled by the control circuit 14 and the processing circuit 15.
  • the control circuit 14 and the processing circuit 15 are also referred to as an arithmetic control circuit, an arithmetic processing circuit, or an arithmetic circuit.
  • Each circuit of the latch circuit 41, the switching circuit 42, the buffer circuit 43_O (43_E), the switching circuit 44, and the arithmetic circuit 45 is preferably composed of a transistor (Si transistor) having silicon in the channel forming region. With this configuration, it is possible to switch the connection state at high speed and perform arithmetic processing.
  • each circuit of the latch circuit 41, the switching circuit 42, the buffer circuit 43_O (43_E), the switching circuit 44, and the arithmetic circuit 45 can be provided by stacking with the OS transistor by using a Si transistor. That is, the storage circuit unit 30 composed of the OS transistor can be provided so as to be stacked with the arithmetic circuit unit 40 that can be configured with the Si transistor. Therefore, the area where the storage circuit unit 30 can be arranged can be increased without increasing the circuit area. By setting the area where the storage circuit unit 30 is provided on the substrate on which the arithmetic circuit unit 40 is provided, as an accelerator, as compared with the case where the storage circuit unit 30 and the arithmetic circuit unit 40 are arranged on the same layer.
  • the storage capacity required for arithmetic processing in the functioning semiconductor device 10 can be increased. By increasing the storage capacity, it is possible to reduce the number of times of data transfer required for arithmetic processing from the external storage device to the semiconductor device, so that power consumption can be reduced.
  • the latch circuit 41 has a function of holding a plurality of weight data read via wiring (also referred to as a local bit line or a read bit line) connected to the storage circuit 31 of the storage circuit unit 30.
  • the latch circuit 41 can be omitted if necessary.
  • the wiring connected to the storage circuit 31 of the storage circuit unit 30 is preferably shortened in order to read the weight data from the storage circuit unit 30 to the latch circuit 41 at high speed. Further, the wiring connected to the storage circuit 31 of the storage circuit unit 30 is preferably shortened in order to reduce the energy consumption associated with charging and discharging.
  • the wiring distance can be shortened by stacking, the parasitic capacitance generated in the signal line can be reduced. Therefore, it is possible to reduce the power consumption.
  • the switching circuit 42 selects one from a plurality of weight data held in the latch circuit 41 and outputs it to the buffer circuit 43_O (43_E).
  • the switching circuit 42 has a function of a multiplexer.
  • the switching circuit 42 has a function of selecting one from a plurality of input signals.
  • the control signal lsel that controls the switching circuit 42 is the control signal lsel_O in the arithmetic circuit unit 40 of the arithmetic block 21_O, and the control signal lsel_E in the arithmetic circuit unit 40 of the arithmetic block 21_E, and can be controlled separately.
  • the switching circuit 42 of the arithmetic circuit unit 40 of the arithmetic block 21_O may be referred to as a first switching circuit. Further, the switching circuit 42 of the arithmetic circuit unit 40 of the arithmetic block 21_E may be referred to as a third switching circuit.
  • the buffer circuit 43_O transmits the weight data selected by the switching circuit 42 to the wiring WOL in the calculation circuit unit 40 of the calculation block 21_O.
  • the buffer circuit 43_E transmits the weight data selected by the switching circuit 42 to the wiring WEL in the calculation circuit unit 40 of the calculation block 21_E.
  • the buffer circuits 43_O and 43_E have the function of a tri-state buffer circuit.
  • the buffer circuits 43_O and 43_E are controlled by the control signals gsel_O and gsel_E, respectively.
  • Wire WOL has a function of transmitting the weight data stored in the storage circuit section 30 in the operation block 21_O computing block unit 20_O (W O).
  • the wiring WEL has a function of transmitting the weight data stored in the storage circuit section 30 in the operation block 21_E computing block unit 20_E (W E).
  • the weight data transmitted via the wiring WOL and the wiring WEL is transmitted to the arithmetic circuit 45 of each of the arithmetic block 21_O and the arithmetic block 21_E via the switching circuit 44.
  • the wiring WOL may be referred to as the first wiring. Further, the wiring WEL may be referred to as a second wiring.
  • the wiring WOL and WEL are wirings arranged according to the number of blocks of a plurality of calculation block units, and may be three or more wirings.
  • the switching circuit 44 selects either one of the weight data transmitted to the wiring WOL or the wiring WEL and outputs it to the arithmetic circuit 45.
  • the switching circuit 44 has a function of a multiplexer.
  • the control signal wsel that controls the switching circuit 44 can perform the same control by the arithmetic circuit unit 40 of the arithmetic block 21_O and the arithmetic circuit unit 40 of the arithmetic block 21_E.
  • the switching circuit 44 of the arithmetic circuit unit 40 of the arithmetic block 21_O may be referred to as a second switching circuit.
  • the switching circuit 44 of the arithmetic circuit unit 40 of the arithmetic block 21_E may be referred to as a fourth switching circuit.
  • the arithmetic circuit 45 has a function of executing arithmetic processing such as a product-sum operation.
  • the calculation circuit 45 performs a product-sum calculation process of the input data input from the control circuit 14 and the weight data given by the switching circuit 44.
  • Digital data is preferable as the input data and the weight data. Digital data is less susceptible to noise. Therefore, the arithmetic circuit 45 is suitable for performing arithmetic processing that requires highly accurate arithmetic results.
  • the arithmetic circuit 45 of the arithmetic circuit unit 40 of the arithmetic block 21_O may be referred to as a first arithmetic circuit.
  • the arithmetic circuit 45 of the arithmetic circuit unit 40 of the arithmetic block 21_E may be referred to as a second arithmetic circuit.
  • the arithmetic circuit 45 may be configured to perform an activation function operation, a quantization operation, a pooling operation, and the like.
  • 2A is calculation block 21_O, in the structure of the applicable calculation block 21 to 21_E, weight data are read from the memory circuit 31 (weight data W O or W E, shown as reference numeral W O / W E) is ,
  • the state given to the arithmetic circuit 45 via the buffer circuit 43 applicable to the buffer circuit 43_O or 43_E, the wiring WOL, WEL, and the switching circuit 44 is schematically shown by a broken line arrow.
  • Arithmetic circuit 45 outputs the input data A, and the weight data W O / W E, the output by product-sum operation processing, the output data MAC.
  • the weight data represented by W O (O represents an odd number), W O 1 and the like in the figure correspond to the above-mentioned first weight data.
  • the weight data representing figure W E (E is an even number), and the like W E1 corresponds to a second weight data described above.
  • the arithmetic circuit unit 40 in the arithmetic block 21_O of the arithmetic block unit 20_O can be schematically represented according to the appearance of the weight data shown in FIG. 2A, and can be abbreviated as shown in FIG. 2B.
  • the weight data W O was read out from the memory circuit section 30 (not shown) illustrates how a given wiring WOL via the buffer circuit 43_O.
  • the weight data W O given to the wiring WOL, and the weight data W E given to the wiring WEL, one of the weight data (figure W O / W E) is in the switching circuit 44 It is illustrated how it is selected and given to the arithmetic circuit 45 (not shown).
  • the arithmetic circuit unit 40 in the arithmetic block 21_E of the arithmetic block unit 20_E can be abbreviated as shown in FIG. 2C.
  • the weight data W E is shown how the given interconnection WEL via the buffer circuit 43_E.
  • the weight data W O given to the wiring WOL, and the weight data W E given to the wiring WEL, one of the weight data (figure W O / W E) is in the switching circuit 44 It is illustrated how it is selected and given to the arithmetic circuit 45 (not shown).
  • FIG. 2D shows a schematic diagram in which the arithmetic circuit unit 40 of the arithmetic block unit 20_O shown in FIGS. 2B and 2C and the arithmetic circuit unit 40 of the arithmetic block unit 20_E are combined.
  • the weight data W O1 to W ON (N is a natural number) read from the storage circuit unit 30 (not shown) in the operation circuit unit 40 of each operation block unit 20_O are shown.
  • the arithmetic circuit 40 of each of the operation block portion 20_E, the storage circuit section 30 are shown the weight data W E1 to W EN was read from (not shown).
  • Calculation block portion 20_O and operation block portion 20_E has, in the storage circuit section 30 corresponding to the calculating circuit section 40 (not shown), different weight data held, weight data is selected (in the drawing W O / W E ) Is output to the arithmetic circuit 45 (not shown).
  • FIG. 2B the switching circuit 44 in FIG. 2C, but shows the configuration which switches and outputs the weight data W O / W E, or in other configurations.
  • FIG. 3A the arithmetic circuit 40 (operation block 21_O, operation block 21_E) illustrated in FIG. 3B as shown in, without passing through the buffer circuit 43_E (buffer circuit 43_O), the weight data W FC to the switching circuit 44 It may be configured to output.
  • Figure 3A In the structure of FIG. 3B, the switching circuit 44 be configured to output the weight data is selected (in the drawing W O / W E / W FC ) to the arithmetic circuit 45 (not shown) Can be done.
  • Weight data W FC is the weight data used in all join operation in the neural network for convolution operation. In the fully coupled operation, the operation is performed using different weight data for each operation circuit. Different when weight data W FC the weight data W fc_1 to weight data W FC_N (N is a natural number of 2 or more) and, as shown in FIG. 3C, different weight data W for each operation circuit section 40 fc_1 to weight data W FC_N Can be selected by the switching circuit 44 and output to the arithmetic circuit 45 (not shown).
  • the weight data W O / W or sharing E at a plurality of arithmetic circuits, or by using the weight data W FC different for each calculation circuit 40 calculating circuit by the switching circuit 44 You can switch between performing operations with. Therefore, the weight data required for the convolution operation and the fully connected operation in the neural network that performs the convolution operation can be read out near the required arithmetic circuit.
  • FIG. 4A shows a state in which the memory circuit portion corresponding to the arithmetic circuit unit 40_O1 belonging to the odd-numbered arithmetic module unit 20_O selects and reads the weight data W O1, charging and discharging the wiring WOL in potential corresponding to the weight data W O1 Is schematically shown by a broken line arrow.
  • FIG. 4A corresponds to the initial operation before starting the calculation, and at this point, the connection between the wiring WOL and the calculation circuit 45 is cut off by the switching circuit 44. Therefore, the charging / discharging operation of the wiring WOL does not become the operation rate-determining of the operation in the calculation circuit 45. It is preferable that the output of the switching circuit 44 does not become an indefinite state by connecting the wiring WEL and the arithmetic circuit 45 or supplying another fixed potential (H potential or L potential).
  • FIG. 4B shows that in the switching circuit 44 in the arithmetic circuit unit 40 of the odd-numbered arithmetic block unit 20_O and the even-numbered arithmetic block unit 20_E, the connection between the wiring WOL and the arithmetic circuit 45 is made conductive.
  • the weight data W O1 is supplied to the circuit 45. Since the buffer circuit 43_O included in the arithmetic circuit unit 40_O1 has completed charging of the wiring WOL in the immediately preceding operation, even if the charge supply capacity of the buffer circuit 43_O is small, the operation rate-determining of the arithmetic in the arithmetic circuit 45 is not achieved.
  • FIG. 5A shows that the switching circuit 44 in the arithmetic circuit unit 40 of the odd-numbered arithmetic block unit 20_O and the even-numbered arithmetic block unit 20_E is calculated by making the connection between the wiring WEL and the arithmetic circuit 45 conductive.
  • the weight data WE1 is supplied to the circuit 45. Since the buffer circuit 43_E included in the arithmetic circuit unit 40_E1 has completed charging of the wiring WEL in the immediately preceding operation, even if the charge supply capacity of the buffer circuit 43_E is small, the operation rate-determining of the arithmetic of the arithmetic circuit 45 is not achieved.
  • FIG. 5B shows that in the switching circuit 44 in the arithmetic circuit unit 40 of the odd-numbered arithmetic block unit 20_O and the even-numbered arithmetic block unit 20_E, the connection between the wiring WOL and the arithmetic circuit 45 is made conductive.
  • the weight data W O2 is supplied to the circuit 45. Since the buffer circuit 43_O included in the arithmetic circuit unit 40_O2 has completed charging of the wiring WOL in the immediately preceding operation, even if the charge supply capacity of the buffer circuit 43_O is small, the operation rate-determining of the arithmetic of the arithmetic circuit 45 is not achieved.
  • the odd-numbered arithmetic block unit 20_O and the even-numbered arithmetic block unit 20_E are used to charge and discharge the wiring WOL or WEL, and the wiring WOL or The weight data charged and discharged to the WEL is supplied to the arithmetic circuit 45 alternately.
  • the charging / discharging operation of the wiring WOL and WEL does not become the operation speed limiting of the operation of the calculation circuit 45, and the operation speed of the calculation can be improved.
  • wiring is performed at high speed even when the charge supply capacity of the buffer circuit is restricted, such as when the buffer circuit is designed in a limited area. Can be configured to charge.
  • the weight data W is supplied to the arithmetic circuit 45 via the wiring WL without switching the operation from the buffer circuit 43 of the arithmetic circuit unit 40 as shown in FIG. 6, it corresponds to the weight data in the wiring WL. It takes time to change the potential, and the calculation processing speed may not be sufficient.
  • the semiconductor device in which the charging speed in the wiring WOL or WEL is increased, the semiconductor device can be obtained in which the arithmetic processing speed is improved.
  • FIG. 7A shows a schematic diagram in the case where the storage circuit unit 30 and the calculation circuit unit 40 are stacked in the calculation block 21_O shown in FIG. 1B.
  • the storage circuit unit 30 and the arithmetic circuit unit 40 are connected via the wiring LBL.
  • the area of the storage circuit unit can be increased without increasing the circuit area.
  • a huge amount of weight data can be held in the storage circuit unit, and the number of times the weight data is transferred from the external memory can be reduced, so that power consumption can be reduced.
  • the size of the semiconductor device can be reduced.
  • FIG. 7B is a diagram for explaining a transistor suitable for the storage circuit unit 30 and the calculation circuit unit 40 in the calculation block 21_O shown in FIG. 7A. It can also be applied to the calculation block 21_E.
  • the storage circuit unit 30 has a storage circuit 31.
  • the storage circuit 31 has a transistor 51.
  • an oxide semiconductor (metal oxide) for the semiconductor layer 52 included in the transistor 51 the storage circuit 31 composed of the OS transistor described above can be used.
  • the arithmetic circuit unit 40 includes a latch circuit 41, a switching circuit 42, a buffer circuit 43_O, a switching circuit 44, and an arithmetic circuit 45.
  • Each circuit included in the arithmetic circuit unit 40 has a transistor 53.
  • silicon As the semiconductor layer 54 of the transistor 53, each circuit of the arithmetic circuit unit 40 composed of the Si transistor described above can be used.
  • the storage circuit unit 30 By setting the area where the storage circuit unit 30 is provided on the substrate on which the arithmetic circuit unit 40 is provided, as an accelerator, as compared with the case where the storage circuit unit 30 and the arithmetic circuit unit 40 are arranged on the same layer.
  • the storage capacity required for arithmetic processing in the functioning semiconductor device 10, that is, the number of storage circuits can be increased.
  • By increasing the storage capacity it is possible to reduce the number of times of data transfer required for arithmetic processing from the external storage device to the semiconductor device, so that power consumption can be reduced.
  • the bus width is limited according to the number of pins on the chip.
  • the number of parallel data required for arithmetic processing can be increased according to the opening in which the wiring LBL is provided. Therefore, it is possible to perform efficient arithmetic processing.
  • the calculation blocks 21_O and 21_E are provided along the wiring WOL and WEL as shown in FIG. With this configuration, the distance between the wiring WOL and WEL and the calculation blocks 21_O and 21_E can be shortened, so that the semiconductor device can be miniaturized and the power consumption can be reduced.
  • FIG. 9 a block diagram showing the entire arithmetic processing system 100 including the semiconductor device 10 functioning as an AI accelerator will be described.
  • FIG. 9 illustrates the CPU 110 and the bus 120 in addition to the accelerator unit 130 having a plurality of semiconductor devices 10 described with reference to FIG. 1A.
  • the CPU 110 has a CPU core 200 and a backup circuit 222.
  • the accelerator unit 130 includes a plurality of semiconductor devices 10 and a control unit 131 for controlling data input / output between the semiconductor devices 10.
  • the CPU 110 has a function of performing general-purpose processing such as execution of an operating system, control of data, execution of various operations and programs.
  • the CPU 110 has a CPU core 200.
  • the CPU core 200 corresponds to one or more CPU cores.
  • the CPU 110 has a backup circuit 222 that can hold the data in the CPU core 200 even if the supply of the power supply voltage is stopped.
  • the supply of the power supply voltage can be controlled by electrical disconnection from the power supply domain (power domain) by a power switch or the like.
  • the power supply voltage may be referred to as a drive voltage.
  • As the backup circuit 222 for example, an OS memory having an OS transistor is suitable.
  • the backup circuit 222 composed of the OS transistor can be provided so as to be laminated with the CPU core 200 that can be configured with the Si transistor. Since the area of the backup circuit 222 is smaller than the area of the CPU core 200, the backup circuit 222 can be arranged on the CPU core 200 without increasing the circuit area.
  • the backup circuit 222 has a function of holding the register data of the CPU core 200.
  • the backup circuit 222 is also referred to as a data holding circuit. The details of the configuration of the CPU core 200 including the backup circuit 222 including the OS transistor will be described in the third embodiment.
  • the control unit 131 has a storage circuit such as an SRAM inside.
  • the control unit 131 holds the output data MACs obtained by the plurality of semiconductor devices 10 in the storage circuit. Then, the output data MAC held in the storage circuit is output to a plurality of semiconductor devices. With this configuration, it is possible to perform parallel calculation with an increased number of parallels using a plurality of semiconductor devices.
  • the bus 120 electrically connects the CPU 110 and the accelerator unit 130. That is, the CPU 110 and the semiconductor device 10 can transmit data via the bus 120.
  • FIG. 10A is a diagram illustrating an example of a circuit configuration applicable to the storage circuit unit 30 in the semiconductor device 10 of the present invention.
  • writing word lines WWL_1 to WWL_M writing word lines RWL_1 to RWL_M, and writing bit lines WBL_1 WBL_N arranged side by side in the matrix direction of M rows and N columns (M and N are natural numbers of 2 or more).
  • M and N are natural numbers of 2 or more.
  • LBL_1 to LBL_N are illustrated.
  • the storage circuit 31 connected to each word line and bit line is illustrated.
  • FIG. 10B is a diagram illustrating a circuit configuration example applicable to the storage circuit 31.
  • the storage circuit 31 includes a transistor 61, a transistor 62, a transistor 63, and a capacitive element 64 (also referred to as a capacitor).
  • One of the source and drain of the transistor 61 is connected to the writing bit line WBL.
  • the gate of the transistor 61 is connected to the writing word line WWL.
  • the other of the source or drain of the transistor 61 is connected to one electrode of the capacitive element 64 and the gate of the transistor 62.
  • One of the source or drain of the transistor 62 and the other electrode of the capacitive element 64 are connected to a wire that provides a fixed potential, eg, a ground potential.
  • the other of the source or drain of the transistor 62 is connected to one of the source or drain of the transistor 63.
  • the gate of the transistor 63 is connected to the read word line RWL.
  • the other of the source or drain of the transistor 63 is connected to the wiring LBL.
  • the wiring LBL is connected to the latch circuit 41 (not shown) of the arithmetic circuit unit 40 via wiring provided so as to extend in a direction substantially perpendicular to the substrate surface on which the Si transistor of the arithmetic circuit unit 40 is provided. Will be done.
  • the circuit configuration of the storage circuit 31 shown in FIG. 10B corresponds to the NOSRAM of the 3-transistor type (3T) gain cell.
  • the transistor 61 to the transistor 63 are OS transistors.
  • the OS transistor has an extremely small leakage current, that is, a current flowing between the source and the drain in the off state.
  • the NOSRAM can be used as a non-volatile memory by holding a charge corresponding to the data in the storage circuit using the characteristic that the leakage current is extremely small.
  • the circuit configuration applicable to the storage circuit 31 of FIG. 10A is not limited to the 3T type NOSRAM of FIG. 10B.
  • it may be a circuit corresponding to the 2T type NOSRAM shown in FIG. 11A.
  • FIG. 11A illustrates a storage circuit 31A having a transistor 61B, a transistor 62B, and a capacitive element 64B.
  • the transistor 61B and the transistor 62B are OS transistors.
  • the transistor 61B and the transistor 62B may be an OS transistor in which a semiconductor layer is arranged in different layers, or an OS transistor in which a semiconductor layer is arranged in the same layer.
  • FIG. 31A An example in which the storage circuit 31A is connected to a write bit line WBL, a wiring LBL functioning as a read bit line, a write word line WWL, a read word line RWL, a source line SL, and a back gate line BGL is shown in the figure. Shows.
  • the circuit configuration applicable to the storage circuit 31 of FIG. 10A may be a circuit in which the 3T type NOSRAM shown in FIG. 11B is combined.
  • FIG. 11B illustrates a storage circuit 31B having a storage circuit 31_P capable of holding data having different logics and a storage circuit 31_N.
  • FIG. 11B illustrates a storage circuit 31_P having a transistor 61_P, a transistor 62_P, a transistor 63_P and a capacitive element 64_P, and a storage circuit 31_N having a transistor 61_N, a transistor 62_N, a transistor 63_N and a capacitive element 64_N.
  • Each transistor included in the storage circuit 31_P and the storage circuit 31_N is an OS transistor.
  • Each transistor included in the storage circuit 31_P and the storage circuit 31_N may be an OS transistor in which a semiconductor layer is arranged in different layers, or an OS transistor in which a semiconductor layer is arranged in the same layer.
  • the storage circuit 31B illustrates an example of being connected to a writing bit line WBL_P, a wiring LBL_P, a writing bit line WBL_N, a wiring LBL_N, a writing word line WWL, and a reading word line RWL.
  • the storage circuit 31B holds data having different logics, and can read the data having different logics to the wiring LBL_P and the wiring LBL_N.
  • FIG. 12 is a diagram illustrating the operation of the switching circuit 42, the buffer circuit 43 (43_O, 43_E), and the switching circuit 44.
  • the storage circuit units 30_1 to 30_1 and the calculation circuit units 40_1 to 40_1 are illustrated as the configurations of the four calculation blocks.
  • the combination of the storage circuit unit 30_1 and the arithmetic circuit unit 40_1, and the combination of the storage circuit unit 30_3 and the arithmetic circuit unit 40_1 correspond to the configuration of the odd-numbered arithmetic block unit.
  • the combination of the storage circuit unit 30_2 and the arithmetic circuit unit 40_2, and the combination of the storage circuit unit 30_4 and the arithmetic circuit unit 40_4 correspond to the configuration of the even-numbered arithmetic block unit.
  • the storage circuit unit 30_1 has a storage circuit 31 connected to the wirings LBL_111 to LBL_1N.
  • the storage circuit unit 30_1 holds the weight data W 11 to W 1N .
  • the storage circuit unit 30_2 has a storage circuit 31 connected to the wirings LBL_21 to LBL_2N.
  • the storage circuit unit 30_2 holds the weight data W 21 to W 2N .
  • the storage circuit unit 30_3 has a storage circuit 31 connected to the wirings LBL_31 to LBL_3N.
  • the storage circuit unit 30_3 holds the weight data W 31 to W 3N .
  • the storage circuit unit 30_4 has a storage circuit 31 connected to the wirings LBL_41 to LBL_4N.
  • the storage circuit unit 30_4 holds the weight data W 41 to W 4N .
  • the wiring LBL P shown by the wiring LBL_11 to LBL_1N, the wiring LBL_21 to LBL_2N, the wiring LBL_31 to LBL_3N, and the wiring LBL_41 to LBL_4N is in the vertical direction connecting the storage circuit unit in the upper layer and the arithmetic circuit unit in the lower layer. Corresponds to the wiring extending to.
  • the wiring LBL P is shorter than the wiring extending in the horizontal direction.
  • the parasitic capacitance of the wiring LBL_11 to LBL_1N, the wiring LBL_21 to LBL_2N, the wiring LBL_31 to LBL_3N, and the wiring LBL_41 to LBL_4N can be reduced, the charge required for charging and discharging the wiring can be reduced, the power consumption can be reduced, and the calculation efficiency can be improved. Can be planned. Further, the weight data can be read out from the storage circuit 31 to the latch circuit at high speed.
  • the arithmetic circuit unit 40_1 includes a latch circuit 41_1, a switching circuit 42_1, a buffer circuit 43_1, a switching circuit 44_1, and an arithmetic circuit 45_1.
  • the latch circuit 41_1 holds the weight data W 11 to W 1N read from the storage circuit 31 possessed by the storage circuit unit 30_1 via the wirings LBL_1 to LBL_1N.
  • the switching circuit 42_1 is controlled by the control signal lsel_O.
  • the buffer circuit 43_1 is controlled by the control signal gsel_O1.
  • the switching circuit 44_1 is controlled by the control signal wsel.
  • Arithmetic circuit 45_1 includes an input data A 1, performs the weight data selected by the switching circuit 44_1, the arithmetic processing by the sum of products, and outputs the output data MAC1.
  • the arithmetic circuit unit 40_2 includes a latch circuit 41_2, a switching circuit 42_2, a buffer circuit 43_2, a switching circuit 44_2, and an arithmetic circuit 45_2.
  • the latch circuit 41_2 holds the weight data W 21 to W 2N read from the storage circuit 31 possessed by the storage circuit unit 30_2 via the wirings LBL_21 to LBL_2N.
  • the switching circuit 42_2 is controlled by the control signal lsel_E.
  • the buffer circuit 43_2 is controlled by the control signal gsel_E1.
  • the switching circuit 44_2 is controlled by the control signal wsel.
  • Arithmetic circuit 45_2 includes an input data A 2, performs the weight data selected by the switching circuit 44_2, the arithmetic processing by the sum of products, and outputs the output data MAC2.
  • the arithmetic circuit unit 40_3 includes a latch circuit 41_3, a switching circuit 42_3, a buffer circuit 43_3, a switching circuit 44_3, and an arithmetic circuit 45_3.
  • the latch circuit 41_3 holds the weight data W 31 to W 3N read from the storage circuit 31 of the storage circuit unit 30_3 via the wirings LBL_31 to LBL_3N.
  • the switching circuit 42_3 is controlled by the control signal lsel_O.
  • the buffer circuit 43_3 is controlled by the control signal gsel_O2.
  • the switching circuit 44_3 is controlled by the control signal wsel.
  • Arithmetic circuit 45_3 includes an input data A 3, performs the weight data selected by the switching circuit 44_3, the arithmetic processing by the sum of products, and outputs the output data MAC3.
  • the calculation circuit unit 40_4 includes a latch circuit 41_4, a switching circuit 42_4, a buffer circuit 43_4, a switching circuit 44_4, and a calculation circuit 45_4.
  • the latch circuit 41_4 holds the weight data W 41 to W 4N read from the storage circuit 31 of the storage circuit unit 30_4 via the wirings LBL_41 to LBL_4N.
  • the switching circuit 42_4 is controlled by the control signal lsel_E.
  • the buffer circuit 43_4 is controlled by the control signal gsel_E2.
  • the switching circuit 44_4 is controlled by the control signal wsel.
  • Arithmetic circuit 45_4 includes an input data A 4, performs the weight data selected by the switching circuit 44_4, the arithmetic processing by the sum of products, and outputs the output data MAC 4.
  • FIG. 13 shows a timing chart for explaining the operation of each configuration described with reference to FIG. Arithmetic circuit 45, weight data is given in response to the toggle operation of the clock signal CLK (for example, time T0 to T6), performs arithmetic processing of the input data A 1 to A 4. By increasing the frequency of the clock signal CLK, it is possible to speed up the arithmetic processing.
  • 41 to W 4N are held by the latch circuits 41_1 to 41_4.
  • the reading of the weight data W 11 to W 1N , the weight data W 21 to W 2N , the weight data W 31 to W 3N , and the weight data W 41 to W 4N which are performed from the time T0, may be performed simultaneously in each storage circuit unit. You may go in order.
  • the weight data W 11 and the weight data W 31 are selected from the latch circuits 41_1 and 41_3 by the control signal lsel_O.
  • the control signal gsel_O1 as the H level, the wiring WOL is charged with the potential corresponding to the weight data W 11 selected by the switching circuit 42_1. At this time, the wiring WOL can be charged at high speed as described above.
  • the weight data W 21 and the weight data W 41 are selected from the latch circuits 41_2 and 41_4 by the control signal lsel_E.
  • the control signal gsel_E1 as the H level
  • the wiring WEL is charged with the potential corresponding to the weight data W 21 selected by the switching circuit 42_2.
  • the wiring WEL at this time can be charged at high speed as described above.
  • the potential corresponding to the weight data W 11 of the wiring WOL charged at the previous time T1 is switched by the control signal wsel given to the switching circuits 44_1 to 44_1, and is given to the arithmetic circuits 45_1 to 45_1.
  • the calculation circuits 45_1 to 45_1 the product-sum calculation process according to the same weight data W 11 is performed, and the output data MAC1 to MAC4 are calculated.
  • the control signal gsel_O2 is set as the H level, and the potential corresponding to the weight data W 31 selected by the switching circuit 42_3 is charged to the wiring WOL.
  • the wiring WOL can be charged at high speed as described above.
  • the potential corresponding to the weight data W 21 of the wiring WEL charged at the previous time T2 is switched by the control signal wsel given to the switching circuits 44_1 to 44_1, and is given to the arithmetic circuits 45_1 to 45_1.
  • the calculation circuits 45_1 to 45_1 the product-sum calculation process according to the same weight data W 21 is performed, and the output data MAC1 to MAC4 are calculated.
  • the control signal gsel_E2 is set as the H level, and the potential corresponding to the weight data W 41 selected by the switching circuit 42_4 is charged to the wiring WEL.
  • the wiring WEL at this time can be charged at high speed as described above.
  • the potential corresponding to the weight data W 31 of the wiring WOL charged at the previous time T3 is switched by the control signal wsel given to the switching circuits 44_1 to 44_1, and is given to the arithmetic circuits 45_1 to 45_1.
  • the calculation circuits 45_1 to 45_1 the product-sum calculation process according to the same weight data W 31 is performed, and the output data MAC1 to MAC4 are calculated.
  • the weight data W 12 and the weight data W 32 are selected from the latch circuits 41_1 and 41_3 by the control signal lsel_O.
  • the wiring WOL can be charged at high speed as described above.
  • the potential corresponding to the weight data W 41 of the wiring WEL charged at the previous time T4 is switched by the control signal wsel given to the switching circuits 44_1 to 44_1, and is given to the arithmetic circuits 45_1 to 45_1.
  • the calculation circuits 45_1 to 45_1 the product-sum calculation process according to the same weight data W 41 is performed, and the output data MAC1 to MAC4 are calculated.
  • the weight data W 22 and the weight data W 42 are selected from the latch circuits 41_2 and 41_4 by the control signal lsel_E.
  • the control signal gsel_E1 as the H level
  • the wiring WEL is charged with the potential corresponding to the weight data W 22 selected by the switching circuit 42_2.
  • the wiring WEL at this time can be charged at high speed as described above.
  • switch control signal wsel for applying a potential corresponding to the weight data W 12 of the wiring WOL charged in the preceding time T5 to the switching circuit 44_1 to 44_4 and gives the arithmetic circuit 45_1 to 45_4.
  • the calculation circuits 45_1 to 45_1 the product-sum calculation process according to the same weight data W 12 is performed, and the output data MAC1 to MAC4 are calculated.
  • the product-sum calculation can be performed by the calculation circuits 45_1 to 45_1 while switching the weight data at high speed, and the output data MAC1 to MAC4 can be calculated.
  • FIG. 14 shows a specific configuration example of the arithmetic circuit 45.
  • Figure 14 illustrates the weight data W (the above-mentioned W O, corresponding to W E) and, the configuration example of the arithmetic circuit 45 can perform the product-sum operation processing of the input data A.
  • the multiplication circuit 71, the addition circuit 72, and the register 73 are illustrated.
  • the data multiplied by the multiplication circuit 71 is input to the addition circuit 72.
  • the output of the adder circuit 72 is held in the register 73, and the data multiplied by the multiplication circuit 71 is added to each other by the adder circuit 72 to perform the multiply-accumulate operation process.
  • the register 73 is controlled by the clock signal CLK and the reset signal reset_B. With this configuration, an output data MAC corresponding to the product-sum operation of the weight data W and the input data A can be obtained.
  • FIG. 15 illustrates a configuration example of a storage circuit unit 30 stacked on the arithmetic circuit unit 40 and a peripheral circuit thereof described with reference to FIG. 1A. Specifically, FIG. 15 illustrates a drive circuit 12, a drive circuit 13, a control circuit 14, a processing circuit 15, a storage circuit 31, a switching circuit 42, a switching circuit 44, and an arithmetic circuit 45.
  • each circuit in FIG. 15 has a configuration in which control signals, input data, and output data for controlling each circuit are input / output to and from an external circuit. Become.
  • FIG. 16A is a diagram in which a block for controlling the storage circuit unit 30 is extracted for each configuration shown in FIG. In FIG. 16A, in addition to the storage circuit 31 in the storage circuit unit 30, the drive circuit 12 and the drive circuit 13 are extracted and shown.
  • the drive circuit 12 and the drive circuit 13 process an input signal from the outside to generate a signal for writing weight data to the storage circuit 31 and a signal for reading weight data from the storage circuit 31.
  • the generated signal is given to the storage circuit via wiring.
  • FIG. 16B is a diagram in which a block that controls the arithmetic circuit unit 40 is extracted for each configuration shown in FIG.
  • the control circuit 14 in addition to the switching circuit 42, the switching circuit 44, and the arithmetic circuit 45 included in the arithmetic circuit unit 40, the control circuit 14, the processing circuit 15, the wiring WOL, and the WEL are illustrated.
  • the latch circuit 41, the buffer circuit 43, and the like are not shown.
  • the control circuit 14 generates the input data A and outputs it to the arithmetic circuit 45.
  • the switching circuit 42 selects weight data read from the storage circuit 31 and feeds it to the wiring WOL or WEL via a buffer circuit (not shown).
  • Switching circuit 44 selects the wire WOL or WEL, outputs weight data W (the above-mentioned W O, corresponding to W E) to the arithmetic circuit 45.
  • the calculation circuit 45 performs a product-sum calculation of the weight data W and the input data A, and outputs the output data MAC to the processing circuit 15.
  • the processing circuit 15 performs post-processing of the output data MAC and outputs it to the control circuit 14.
  • the input data A is re-input to the arithmetic circuit unit 40.
  • the data processed by the control circuit 14 can be output again as input data to the calculation circuit unit 40. Therefore, the calculation process can be executed without reading the data in the middle of the calculation to the main memory or the like outside the semiconductor device 10. Further, in the semiconductor device 10, since the electrical connection between the storage circuit unit and the arithmetic circuit unit can be made via the wiring of the opening provided in the insulating film or the like, the number of wirings can be increased in parallel. It is possible to increase the number. Therefore, in the semiconductor device 10, parallel calculation of the number of bits equal to or larger than the data bus width of the CPU becomes possible. Further, since the arithmetic circuit unit is provided so as to be stacked on the storage circuit unit, the area in which the storage circuit can be arranged can be increased. As a result, a huge amount of weight data can be held in the storage circuit unit, and the number of times the weight data is transferred from the external memory can be reduced, so that power consumption can be reduced.
  • one aspect of the present invention can provide a semiconductor device that functions as an accelerator and is miniaturized.
  • one aspect of the present invention can provide a semiconductor device that functions as an accelerator with low power consumption.
  • FIG. 17 is a diagram illustrating an example of operation when a part of the operation of the program executed by the CPU is executed by the accelerator.
  • the host program is executed on the CPU (host program execution; step S1).
  • step S2 When the CPU confirms an instruction to allocate a data area required for performing an operation using the accelerator in the storage circuit unit (memory allocation instruction; step S2), the CPU allocates the data area to the storage circuit. It is secured in the unit (memory allocation; step S3).
  • the CPU transmits weight data, which is input data, from the main memory or the external storage device to the storage circuit unit (data transmission; step S4).
  • the storage circuit unit receives the weight data and stores the weight data in the area secured in step S2 (data reception; step S5).
  • step S6 When the CPU confirms the instruction to start the kernel program (starting the kernel program; step S6), the accelerator starts executing the kernel program (starting calculation; step S7).
  • the CPU may be switched from the state of performing calculation to the PG (power gating) state (PG state transition; step S8).
  • PG state transition PG state transition
  • the CPU is switched from the PG state to the state in which the calculation is performed (PG state stop; step S9).
  • step S10 When the accelerator finishes executing the kernel program, the output data is stored in the storage unit that holds the calculation result in the accelerator (completion of calculation; step S10).
  • step S11 After the execution of the kernel program is completed, when the CPU confirms the instruction to transmit the output data stored in the storage unit to the main memory or the external storage device (data transmission request; step S11), the above output data is output. It is transmitted to the main memory or the external storage device and stored in the main memory or the external storage device (data transmission; step S12).
  • the semiconductor device of one aspect of the present invention has a non-Von Neumann architecture, and can perform arithmetic processing with extremely low power consumption as compared with the von Neumann architecture in which the power consumption increases as the processing speed increases. ..
  • FIG. 18 shows a configuration example of the CPU 110.
  • the CPU 110 includes a CPU core (CPU Core) 200, an L1 (level 1) cache memory device (L1 cache) 202, an L2 cache memory device (L2 cache) 203, a bus interface unit (Bus I / F) 205, and a power switch 210 to. It has 212, a level shifter (LS) 214.
  • the CPU core 200 has a flip-flop 220.
  • the CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203 are connected to each other by the bus interface unit 205.
  • the PMU193 generates a clock signal GCLK1 and various PG (power gating) control signals (PG control signals) in response to signals such as interrupt signals (Interrupts) input from the outside and signal SLEEP1 issued by the CPU 110.
  • the clock signals GCLK1 and PG control signals are input to the CPU 110.
  • the PG control signal controls the power switches 210 to 212 and the flip-flop 220.
  • the power switches 210 and 211 control the supply of the voltages VDDD and VDD1 to the virtual power supply line V_ VDD (hereinafter referred to as V_ VDD line), respectively.
  • the power switch 212 controls the supply of the voltage VDDH to the level shifter (LS) 214.
  • the voltage VSSS is input to the CPU 110 and the PMU 193 without going through the power switch.
  • the voltage VDDD is input to the PMU 193 without going through the power switch.
  • Voltages VDDD and VDD1 are drive voltages for CMOS circuits.
  • the voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state.
  • the voltage VDDH is the drive voltage for the OS transistor and is higher than the voltage VDDD.
  • Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain capable of power gating.
  • a power domain capable of power gating is provided with one or more power switches. These power switches are controlled by PG control signals.
  • the flip-flop 220 is used as a register.
  • the flip-flop 220 is provided with a backup circuit. Hereinafter, the flip-flop 220 will be described.
  • FIG. 19 shows an example of a circuit configuration of a flip-flop 220 (Flip-flop).
  • the flip-flop 220 has a scan flip-flop (Scan Flip-flop) 221 and a backup circuit (Backup Circuit) 222.
  • the scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.
  • Node D1 is a data (data) input node
  • node Q1 is a data output node
  • node SD is a scan test data input node.
  • the node SE is an input node of the signal SCE.
  • the node CK is an input node for the clock signal GCLK1.
  • the clock signal GCLK1 is input to the clock buffer circuit 221A.
  • the analog switch of the scan flip-flop 221 is connected to the nodes CK1 and CKB1 of the clock buffer circuit 221A.
  • the node RT is an input node for a reset signal.
  • the signal SCE is a scan enable signal and is generated by PMU193.
  • PMU193 generates signals BK and RC.
  • the level shifter 214 level-shifts the signals BK and RC to generate the signals BKH and RCH.
  • the signal BK is a backup signal
  • the signal RC is a recovery signal.
  • the circuit configuration of the scan flip-flop 221 is not limited to FIG. Flip-flops provided in standard circuit libraries can be applied.
  • the backup circuit 222 has a node SD_IN, SN11, transistors M11 to M13, and a capacitive element C11.
  • the node SD_IN is an input node for scan test data and is connected to node Q1 of the scan flip-flop 221.
  • the node SN11 is a holding node of the backup circuit 222.
  • the capacitance element C11 is a holding capacitance for holding the voltage of the node SN11.
  • the transistor M11 controls the conduction state between the node Q1 and the node SN11.
  • the transistor M12 controls the conduction state between the node SN11 and the node SD.
  • the transistor M13 controls the conduction state between the node SD_IN and the node SD.
  • the on / off of the transistors M11 and M13 is controlled by the signal BKH, and the on / off of the transistors M12 is controlled by the signal RH.
  • the transistors M11 to M13 are OS transistors like the transistors 61 to 63 of the storage circuit 31 described above.
  • the transistors M11 to M13 show a configuration having a back gate.
  • the back gates of the transistors M11 to M13 are connected to a power line that supplies the voltage VBG1.
  • the backup circuit 222 has a non-volatile characteristic because the off current is extremely small, the voltage drop of the node SN11 can be suppressed, and almost no power is consumed to hold the data. Since the data is rewritten by charging / discharging the capacitive element C11, the backup circuit 222 is not limited in the number of rewritings in principle, and data can be written and read with low energy.
  • the backup circuit 222 can be laminated on the scan flip-flop 221 composed of the silicon CMOS circuit.
  • the backup circuit 222 Since the backup circuit 222 has a very small number of elements as compared with the scan flip-flop 221, it is not necessary to change the circuit configuration and layout of the scan flip-flop 221 in order to stack the backup circuit 222. That is, the backup circuit 222 is a very versatile backup circuit. Further, since the backup circuit 222 can be provided in the region where the scan flip-flop 221 is formed, the area overhead of the flip-flop 220 can be reduced to zero even if the backup circuit 222 is incorporated. Therefore, by providing the backup circuit 222 on the flip-flop 220, power gating of the CPU core 200 becomes possible. Since the energy required for power gating is small, it is possible to power gate the CPU core 200 with high efficiency.
  • the backup circuit 222 By providing the backup circuit 222, the parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is smaller than the parasitic capacitance due to the logic circuit connected to the node Q1, the scan flip-flop 221 operates. There is no effect. That is, even if the backup circuit 222 is provided, the performance of the flip-flop 220 is not substantially deteriorated.
  • the low power consumption state of the CPU core 200 for example, a clock gating state, a power gating state, and a hibernation state can be set.
  • the PMU193 selects the low power consumption mode of the CPU core 200 based on the interrupt signal, the signal SLEEP1, and the like. For example, when shifting from the normal operating state to the clock gating state, the PMU 193 stops the generation of the clock signal GCLK1.
  • the PMU193 when shifting from the normal operating state to the hibernation state, the PMU193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 in order to input the voltage VDD1 to the CPU core 200.
  • the voltage VDD1 is a voltage that does not cause the data of the scan flip-flop 221 to be lost.
  • PMU193 lowers the frequency of the clock signal GCLK1.
  • FIG. 20 shows an example of the power gating sequence of the CPU core 200.
  • t1 to t7 represent the time.
  • the signals PSE0 to PSE2 are control signals of the power switches 210 to 212 and are generated by the PMU193. When the signal PSE0 is “H” / “L”, the power switch 210 is on / off. The same applies to the signals PSE1 and PSE2.
  • the power switch 210 Before the time t1, it is in the normal operating state (Normal Operation).
  • the power switch 210 is on, and the voltage VDDD is input to the CPU core 200.
  • the scan flip-flop 221 operates normally.
  • the power switch 212 since the level shifter 214 does not need to be operated, the power switch 212 is off, and the signals SCE, BK, and RC are “L”. Since the node SE is “L”, the scan flip-flop 221 stores the data of the node D1. In the example of FIG. 20, at time t1, the node SN11 of the backup circuit 222 is “L”.
  • the PMU193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to “H”.
  • the level shifter 214 becomes active and outputs the “H” signal BKH to the backup circuit 222.
  • the transistor M11 of the backup circuit 222 is turned on, and the data of the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is "L”, the node SN11 remains “L”, and if the node Q1 is "H”, the node SN11 becomes "H”.
  • the PMU193 sets the signals PSE2 and BK to “L” at time t2 and sets the signal PSE0 to “L” at time t3. At time t3, the state of the CPU core 200 shifts to the power gating state.
  • the signal PSE0 may be turned off at the timing of lowering.
  • PMU193 sets the signal PSE0 to “H” to shift from the power gating state to the recovery state.
  • the PMU193 sets the signals PSE2, RC, and SCE to "H” in a state where the charging of the V_ldap line is started and the voltage of the V_ldap line becomes VDDD (time t5).
  • the transistor M12 is turned on, and the charge of the capacitive element C11 is distributed to the node SN11 and the node SD. If the node SN11 is "H”, the voltage of the node SD rises. Since the node SE is “H”, the data of the node SD is written to the input side latch circuit of the scan flip-flop 221. When the clock signal GCLK1 is input to the node CK at time t6, the data of the input side latch circuit is written to the node Q1. That is, the data of the node SN11 is written to the node Q1.
  • PMU193 sets the signals PSE2, SCE, and RC to “L”, and the recovery operation ends.
  • the backup circuit 222 using the OS transistor is very suitable for normal-off computing because both dynamic and static low power consumption are small.
  • the CPU 110 including the CPU core 200 having a backup circuit 222 using an OS transistor can be referred to as a Noff CPU (registered trademark).
  • the Noff CPU has a non-volatile memory and can stop the power supply when the operation is not required. Even if the flip-flop 220 is mounted, it is possible to hardly cause a decrease in the performance of the CPU core 200 and an increase in dynamic power.
  • the CPU core 200 may have a plurality of power domains capable of power gating.
  • the plurality of power domains are provided with one or more power switches for controlling the voltage input.
  • the CPU core 200 may have one or a plurality of power domains in which power gating is not performed.
  • a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212 may be provided in the power domain where power gating is not performed.
  • the application of the flip-flop 220 is not limited to the CPU 110.
  • the flip-flop 220 can be applied to a register provided in a power domain capable of power gating.
  • FIG. 21 shows a part of the cross-sectional structure of the semiconductor device.
  • the semiconductor device shown in FIG. 21 includes a transistor 550, a transistor 500, and a capacitive element 600.
  • 22A is a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 22B is a cross-sectional view of the transistor 500 in the channel width direction.
  • the transistor 500 corresponds to an OS transistor included in the storage circuit 31 shown in the above embodiment, that is, a transistor having an oxide semiconductor in a channel forming region.
  • the transistor 550 corresponds to a Si transistor included in the arithmetic circuit unit 40 shown in the above embodiment, that is, a transistor having silicon in the channel forming region.
  • the capacitive element 600 corresponds to the capacitive element of the storage circuit 31.
  • the transistor 500 is an OS transistor.
  • the OS transistor has an extremely small off current. Therefore, it is possible to hold the data voltage or charge written to the storage node via the transistor 500 for a long period of time. That is, the frequency of refreshing operations of the storage node is reduced, or the refreshing operation is not required, so that the power consumption of the semiconductor device can be reduced.
  • the transistor 500 is provided above the transistor 550, and the capacitive element 600 is provided above the transistor 550 and the transistor 500.
  • the transistor 550 is provided on the substrate 311.
  • the substrate 311 is, for example, a p-type silicon substrate.
  • the substrate 311 may be an n-type silicon substrate.
  • the oxide layer 314 is preferably an insulating layer (also referred to as a BOX layer) formed in a substrate 311 by embedded oxidation (Blured oxide), for example, silicon oxide.
  • the transistor 550 is provided on a single crystal silicon, a so-called SOI (Silicon On Insulator) substrate, which is provided on the substrate 311 via an oxide layer 314.
  • SOI Silicon On Insulator
  • the substrate 311 in the SOI substrate is provided with an insulator 313 that functions as an element separation layer.
  • the substrate 311 also has a well region 312.
  • the well region 312 is a region to which n-type or p-type conductivity is imparted depending on the conductive type of the transistor 550.
  • the single crystal silicon in the SOI substrate is provided with a semiconductor region 315, a low resistance region 316a that functions as a source region or a drain region, and a low resistance region 316b. Further, a low resistance region 316c is provided on the well region 312.
  • the transistor 550 can be provided so as to be superimposed on the well region 312 to which the impurity element that imparts conductivity is added.
  • the well region 312 can function as a bottom gate electrode of the transistor 550 by independently changing the potential via the low resistance region 316c. Therefore, the threshold voltage of the transistor 550 can be controlled.
  • the threshold voltage of the transistor 550 can be controlled.
  • the threshold voltage of the transistor 550 can be made larger and the off-current can be reduced. Therefore, by applying a negative potential to the well region 312, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be reduced.
  • the power consumption based on the through current and the like in the arithmetic circuit unit 40 having the transistor 550 can be reduced, and the arithmetic efficiency can be improved.
  • the transistor 550 is preferably of a so-called Fin type in which the upper surface of the semiconductor layer and the side surface in the channel width direction are covered with the conductor 318 via the insulator 317.
  • the on characteristic of the transistor 550 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 550 can be improved.
  • the transistor 550 may be either a p-channel type transistor or an n-channel type transistor.
  • the conductor 318 may function as a first gate (also referred to as a top gate) electrode. Further, the well region 312 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the potential applied to the well region 312 can be controlled via the low resistance region 316c.
  • the low resistance region 316a which is the region where the channel of the semiconductor region 315 is formed, the region in the vicinity thereof, the source region, or the drain region, and the low resistance region 316b, which is connected to the electrode controlling the potential of the well region 312.
  • the region 316c or the like preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 550 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • the low resistance region 316a, the low resistance region 316b, and the low resistance region 316c are elements that impart n-type conductivity such as arsenic and phosphorus, or boron. It contains elements that impart p-type conductivity such as.
  • the conductor 318 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • a silicide such as nickel silicide may be used as the conductor 318.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the low resistance region 316a, the low resistance region 316b, and the low resistance region 316c may be configured to be provided by laminating another conductor, for example, a silicide such as nickel silicide. With this configuration, the conductivity of the region that functions as an electrode can be enhanced. At this time, an insulator that functions as a side wall spacer (also referred to as a side wall insulating layer) may be provided on the side surface of the conductor 318 that functions as the gate electrode and the side surface of the insulator that functions as the gate insulating film. .. With this configuration, it is possible to prevent the conductor 318 and the low resistance region 316a and the low resistance region 316b from being in a conductive state.
  • a silicide such as nickel silicide
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are laminated in this order so as to cover the transistor 550.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.
  • silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition refers to a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen
  • aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.
  • the insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 550 or the like provided below the insulator 322.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 500 is provided from the substrate 311 or the transistor 550.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by the CVD method can be used.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS).
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is such that the amount desorbed in terms of hydrogen atoms is converted per area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C. to 500 ° C. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 has a lower dielectric constant than the insulator 324.
  • the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324.
  • a conductor 328 connected to the capacitive element 600 or the transistor 500, a conductor 330, and the like are embedded.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • the conductor having a function as a plug or a wiring may collectively give the same reference numeral to a plurality of configurations.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 550.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 350 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 356 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 550 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 354 and the conductor 356.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in this order.
  • a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 has a function as a plug or wiring.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 360 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 366 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 364 and the conductor 366.
  • the insulator 370, the insulator 372, and the insulator 374 are laminated in this order.
  • a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 has a function as a plug or wiring.
  • the conductor 376 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 370 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 376 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 374 and the conductor 376.
  • the insulator 380, the insulator 382, and the insulator 384 are laminated in this order.
  • a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 has a function as a plug or wiring.
  • the conductor 386 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 380 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 386 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen.
  • the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment has been described. It is not limited to this.
  • the number of wiring layers similar to the wiring layer including the conductor 356 may be 3 or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be 5 or more.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are laminated in this order.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 it is preferable to use a substance having a barrier property against oxygen and hydrogen.
  • the insulator 510 and the insulator 514 it is preferable to use a film having a barrier property against hydrogen and impurities in the region where the transistor 500 is provided from the region where the substrate 311 or the transistor 550 is provided. Therefore, the same material as the insulator 324 can be used.
  • Silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 512 and the insulator 516.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are embedded with a conductor 518, a conductor (for example, a conductor 503) constituting the transistor 500, and the like.
  • the conductor 518 has a function as a plug or wiring for connecting to the capacitive element 600 or the transistor 550.
  • the conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, and an insulator 522 arranged on the insulator 516 and the insulator 503. And an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, and each other on the oxide 530b. Insulator 580 and an opening which are arranged on the conductor 542a and the conductor 542b and which are arranged apart from each other and have an opening formed by superimposing between the conductor 542a and the conductor 542b. It has an insulator 545 arranged on the bottom surface and side surfaces of the insulator 545, and a conductor 560 arranged on the forming surface of the insulator 545.
  • the insulator 544 is arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580.
  • the conductor 560 includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable to have.
  • the insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 545.
  • the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.
  • the transistor 500 shows a configuration in which two layers of oxide 530a and oxide 530b are laminated in a region where a channel is formed and in the vicinity thereof, but the present invention is not limited to this.
  • a single layer of the oxide 530b or a laminated structure of three or more layers may be provided.
  • the conductor 560 is shown as a laminated structure of two layers, but the present invention is not limited to this.
  • the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.
  • the transistor 500 shown in FIGS. 21, 22A, and 22B is an example, and the transistor 500 is not limited to the configuration thereof, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.
  • the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved and high frequency characteristics can be provided.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, it is possible to increase the threshold voltage of the transistor 500 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done.
  • the configuration of a transistor that electrically surrounds a channel forming region by an electric field of a pair of gate electrodes is referred to as a curved channel (S-channel) configuration.
  • S-channel configuration disclosed in the present specification and the like is different from the Fin type configuration and the planar type configuration.
  • the conductor 503 has the same configuration as the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
  • the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • a conductive material for the conductor 503a which has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one such as an oxygen atom and an oxygen molecule
  • the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
  • the conductor 503 also has a wiring function
  • the conductor 503 is shown by laminating the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer structure.
  • the insulator 522 and the insulator 524 have a function as a second gate insulating film.
  • the insulator 524 in contact with the oxide 530 it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition.
  • the oxygen is easily released from the membrane by heating.
  • oxygen released by heating may be referred to as "excess oxygen”. That is, it is preferable that the insulator 524 is formed with a region containing excess oxygen (also referred to as “excess oxygen region”).
  • the defective Functions as a donor, sometimes electrons serving as carriers are generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in an oxide semiconductor is easily moved by stress such as heat and electric field, if a large amount of hydrogen is contained in the oxide semiconductor, the reliability of the transistor may be deteriorated.
  • the highly purified intrinsic or substantially highly purified intrinsic it is preferable that the highly purified intrinsic or substantially highly purified intrinsic.
  • the V O H to obtain a sufficiently reduced oxide semiconductor (referred to as “dewatering” or “dehydrogenation process” also.) Water in the oxide semiconductor, to remove impurities such as hydrogen It is important to supply oxygen to the oxide semiconductor to compensate for the oxygen deficiency (also referred to as “dehydrogenation treatment").
  • the V O H oxide semiconductor impurity is sufficiently reduced such by using a channel formation region of the transistor, it is possible to have stable electrical characteristics.
  • an oxide material in which a part of oxygen is desorbed by heating is those whose oxygen desorption amount in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment.
  • heat treatment microwave treatment, or RF treatment.
  • water or hydrogen in the oxide 530 can be removed.
  • reactions occur which bonds VoH is disconnected, when other words happening reaction of "V O H ⁇ Vo + H", it can be dehydrogenated.
  • the hydrogen generated as oxygen combines with H 2 O, it may be removed from the oxide 530 or oxide 530 near the insulator. Further, a part of hydrogen may be gettered to the conductor 542.
  • the microwave processing for example, it is preferable to use a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side.
  • a device having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is better to do it at% or less.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO ).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more, and then continuously heat-treated in an atmosphere of nitrogen gas or an inert gas.
  • the oxygen deficiency in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo + O ⁇ null" can be promoted. Further, since the oxygen supplied to the hydrogen remaining in the oxide 530 is reacted to remove the hydrogen as H 2 O (to dehydration) can. Thus, the hydrogen remained in the oxide 530 can be prevented from recombine V O H is formed by oxygen vacancies.
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
  • oxygen for example, oxygen atom, oxygen molecule, etc.
  • the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, the oxygen contained in the oxide 530 does not diffuse to the conductor 503 side, which is preferable. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 and the oxide 530.
  • the insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) in a single layer or in a laminated manner. As the transistor becomes finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for an insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a so-called high-k material such as (Ba, Sr) TiO 3 (BST)
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials having a function of suppressing diffusion of impurities and oxygen (which oxygen is difficult to permeate).
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 is formed using such a material, the insulator 522 suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.
  • the insulator 522 and the insulator 524 are shown as the second gate insulating film having a laminated structure of two layers, but the second gate insulating film is It may have a single layer, three layers, or a laminated structure of four or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium). , Hafnium, tantalum, tungsten, or one or more selected from gallium, etc.) and the like.
  • the metal oxide that functions as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method.
  • the oxide 530 can suppress the diffusion of impurities from the composition formed below the oxide 530a to the oxide 530b.
  • the oxide 530 has a laminated structure of a plurality of oxide layers having different atomic number ratios of each metal atom.
  • the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 530b.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the energy at the lower end of the conduction band of the oxide 530a is higher than the energy at the lower end of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxides 530a and 530b can be said to be continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.
  • the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, so that a mixed layer having a low defect level density can be formed.
  • the oxide 530b is an In-Ga-Zn oxide
  • the main path of the carrier is oxide 530b.
  • the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.
  • a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b.
  • the conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.
  • Iridium, strontium, a metal element selected from lanthanum, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like is preferably used.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
  • the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used.
  • a tantalum nitride film and a tungsten film may be laminated.
  • the titanium film and the aluminum film may be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may be a two-layer structure in which copper films are laminated.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a region 543a and a region 543b may be formed as a low resistance region at the interface of the oxide 530 with the conductor 542a (conductor 542b) and its vicinity thereof.
  • the region 543a functions as one of the source region or the drain region
  • the region 543b functions as the other of the source region or the drain region.
  • a channel forming region is formed in a region sandwiched between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier density of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
  • the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and come into contact with the insulator 524.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.
  • the insulator 544 it is preferable to use aluminum or an oxide containing one or both oxides of hafnium, such as aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate). ..
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step.
  • the conductors 542a and 542b are materials having oxidation resistance or materials whose conductivity does not decrease even if oxygen is absorbed, the insulator 544 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.
  • the insulator 544 By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. Further, it is possible to suppress the oxidation of the conductor 542 due to the excess oxygen contained in the insulator 580.
  • the insulator 545 functions as a first gate insulating film. Like the above-mentioned insulator 524, the insulator 545 is preferably formed by using an insulator that contains excessive oxygen and releases oxygen by heating.
  • silicon oxide with excess oxygen silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, carbon, silicon oxide with nitrogen, and pores.
  • Silicon oxide having can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are heat-stable.
  • the insulator 545 By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel forming region of the oxide 530b. Further, as with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 545 is reduced.
  • the film thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. Further, the above-mentioned microwave treatment may be performed before and / or after the formation of the insulator 545.
  • a metal oxide may be provided between the insulator 545 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 545 may have a laminated structure as in the case of the second gate insulating film.
  • an insulator that functions as a gate insulating film is made of a high-k material and heat.
  • the conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 22A and 22B, it may have a single-layer structure or a laminated structure of three or more layers.
  • Conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), conductive having a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 545 to reduce the conductivity.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 560b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon, resin, or the like silicon oxide and silicon nitride nitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 in which oxygen is released by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.
  • the opening of the insulator 580 is formed so as to overlap the region between the conductor 542a and the conductor 542b.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the conductor 560 may have a shape having a high aspect ratio.
  • the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.
  • the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545.
  • an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • the insulator 574 use one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Can be done.
  • aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.
  • an insulator 581 that functions as an interlayer film on the insulator 574. It is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the membrane, similarly to the insulator 524 and the like.
  • the conductor 540a and the conductor 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544.
  • the conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween.
  • the conductor 540a and the conductor 540b have the same configuration as the conductor 546 and the conductor 548 described later.
  • An insulator 582 is provided on the insulator 581.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582.
  • a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • a conductor 546, a conductor 548, etc. are embedded in the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586. There is.
  • the conductor 546 and the conductor 548 have a function as a plug or wiring for connecting to the capacitive element 600, the transistor 500, or the transistor 550.
  • the conductor 546 and the conductor 548 can be provided by using the same materials as the conductor 328 and the conductor 330.
  • an opening may be formed so as to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening.
  • an insulator having a high barrier property against hydrogen or water By wrapping the transistor 500 with the above-mentioned insulator having a high barrier property, it is possible to prevent moisture and hydrogen from invading from the outside.
  • a plurality of transistors 500 may be bundled together and wrapped with an insulator having a high barrier property against hydrogen or water.
  • an opening is formed so as to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the above-mentioned insulator having a high barrier property is provided so as to be in contact with the insulator 522 or the insulator 514.
  • the insulator having a high barrier property to hydrogen or water for example, the same material as the insulator 522 or the insulator 514 may be used.
  • the capacitive element 600 has a conductor 610, a conductor 620, and an insulator 630.
  • the conductor 612 may be provided on the conductor 546 and the conductor 548.
  • the conductor 612 has a function as a plug or wiring for connecting to the transistor 500.
  • the conductor 610 has a function as an electrode of the capacitive element 600.
  • the conductor 612 and the conductor 610 can be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components.
  • a metal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film can be used.
  • the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the configuration is not limited to this, and a laminated configuration of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having the barrier property and the conductor having a high conductivity.
  • the conductor 620 is provided so as to be superimposed on the conductor 610 via the insulator 630.
  • a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as other configurations such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.
  • An insulator 640 is provided on the conductor 620 and the insulator 630.
  • the insulator 640 can be provided by using the same material as the insulator 320. Further, the insulator 640 may function as a flattening film that covers the uneven shape below the insulator 640.
  • FIG. 23A is an example of a schematic diagram for explaining an integrated circuit including each configuration of the arithmetic processing system 100.
  • the integrated circuit 390 illustrated in FIG. 23A can be made into one integrated circuit in which each circuit is integrated by forming a part of the circuit included in the CPU 110 and the accelerator described as the semiconductor device 10 with an OS transistor.
  • the CPU 110 may be configured to provide the backup circuit 222 on the layer having the OS transistor on the upper layer of the CPU core 200.
  • the storage circuit unit 30 is provided on the layer having the OS transistor on the upper layer of the layer having the Si transistor constituting the arithmetic circuit unit 40. be able to.
  • an OS memory 300N or the like may be provided on the layer having the OS transistor.
  • a DOSRAM can be applied in addition to the NOSRAM described in the above embodiment.
  • the memory density can be improved by stacking the layer having the OS transistor on the drive circuit provided in the layer having the Si transistor.
  • FIG. 23B shows an example of a semiconductor chip incorporating an integrated circuit 390.
  • the semiconductor chip 391 shown in FIG. 23B has a lead 392 and an integrated circuit 390.
  • various circuits shown in the above embodiment are provided on one die.
  • the integrated circuit 390 has a laminated structure and is roughly classified into a layer having a Si transistor (Si transistor layer 393), a wiring layer 394, and a layer having an OS transistor (OS transistor layer 395). Since the OS transistor layer 395 can be laminated on the Si transistor layer 393, the semiconductor chip 391 can be easily miniaturized.
  • QFP Quad Flat Package
  • Other configuration examples include insert-mounted DIP (Dual In-line Package), PGA (Pin Grid Array), surface-mounted SOP (Small Outline Package), SSOP (Shrink Small Outline Package), and TS. Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-readed package), BGA (Ball Grid Array), FBGA (Pin Grid Array), FBGA (Fine Grid) TP Structures such as Package) and QTP (Quad Tape-carrier Package) can be appropriately used.
  • the arithmetic circuit and switching circuit having a Si transistor and the storage circuit having an OS transistor can all be formed in the Si transistor layer 393, the wiring layer 394, and the OS transistor layer 395. That is, the elements constituting the semiconductor device can be formed by the same manufacturing process. Therefore, in the IC shown in FIG. 23B, it is not necessary to increase the manufacturing process even if the number of constituent elements increases, and the semiconductor device can be incorporated at low cost.
  • a novel semiconductor device and an electronic device can be provided.
  • FIG. 24A illustrates an external view of an automobile as an example of a moving body.
  • FIG. 24B is a diagram that simplifies the exchange of data in the automobile.
  • the automobile 590 has a plurality of cameras 591 and the like. Further, the automobile 590 is equipped with various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.
  • the integrated circuit 390 (or the semiconductor chip 391 incorporating the integrated circuit 390) can be used in the camera 591 or the like.
  • the camera 591 processes a plurality of images obtained in a plurality of imaging directions 592 by the integrated circuit 390 described in the above embodiment, and the plurality of images are collected by the host controller 594 or the like via the bus 593 or the like. By analyzing this, it is possible to determine the surrounding traffic conditions such as the presence or absence of guardrails and pedestrians, and perform automatic driving. It can also be used in systems for road guidance, danger prediction, and the like.
  • the obtained image data is subjected to arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • Etc. image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, reduction of reflection reflection, etc. can be performed.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc.
  • computer of one aspect of the present invention is applied to these moving objects. Therefore, it is possible to provide a system using artificial intelligence.
  • FIG. 25A is an external view showing an example of a portable electronic device.
  • FIG. 25B is a diagram simplifying the exchange of data in a portable electronic device.
  • the portable electronic device 595 includes a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.
  • the integrated circuit 390 can be provided on the printed wiring board 596.
  • the portable electronic device 595 improves user convenience by processing and analyzing a plurality of data obtained by the speaker 597, the camera 598, the microphone 599, etc. by using the integrated circuit 390 described in the above embodiment. be able to. It can also be used in systems that perform voice guidance, image search, and the like.
  • the obtained image data is subjected to arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • Etc. image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, reduction of reflection reflection, etc. can be performed.
  • the portable game machine 1100 shown in FIG. 26A has a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, an operation key 1107, and the like.
  • the housing 1101, the housing 1102 and the housing 1103 can be removed.
  • the connection unit 1105 provided in the housing 1101 to the housing 1108 the video output to the display unit 1104 can be output to another video device.
  • the housing 1102 and the housing 1103 are integrated and function as an operation unit.
  • the integrated circuit 390 shown in the previous embodiment can be incorporated into the chips and the like provided on the boards of the housing 1102 and the housing 1103.
  • FIG. 26B is a USB connection type stick-type electronic device 1120.
  • the electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a substrate 1124.
  • the board 1124 is housed in the housing 1121.
  • a memory chip 1125 and a controller chip 1126 are attached to the substrate 1124.
  • the integrated circuit 390 shown in the previous embodiment can be incorporated in the controller chip 1126 or the like of the substrate 1124.
  • FIG. 26C is a humanoid robot 1130.
  • the robot 1130 has sensors 2101 to 2106 and a control circuit 2110.
  • the integrated circuit 390 shown in the previous embodiment can be incorporated in the control circuit 2110.
  • the integrated circuit 390 described in the above embodiment can be used as a server that communicates with the electronic device instead of being built in the electronic device.
  • the arithmetic system is composed of the electronic device and the server.
  • FIG. 27 shows a configuration example of the system 3000.
  • the system 3000 is composed of an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via the Internet line 3003.
  • the server 3002 has a plurality of racks 3004.
  • a plurality of boards 3005 are provided in the plurality of racks, and the integrated circuit 390 described in the above embodiment can be mounted on the board 3005.
  • a neural network is configured on the server 3002.
  • the server 3002 can perform the operation of the neural network by using the data input from the electronic device 3001 via the Internet line 3003.
  • the result of the calculation by the server 3002 can be transmitted to the electronic device 3001 via the Internet line 3003, if necessary. This makes it possible to reduce the burden of calculation in the electronic device 3001.
  • each embodiment can be made into one aspect of the present invention by appropriately combining with other embodiments or configurations shown in Examples. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.
  • the content described in one embodiment is another content (may be a part of the content) described in the embodiment, and / or one or more. It can be applied, combined, or replaced with respect to the content described in another embodiment (may be a part of the content).
  • figure (which may be a part) described in one embodiment is another part of the figure, another figure (which may be a part) described in the embodiment, and / or one or more.
  • figures (which may be a part) described in another embodiment of the above more figures can be formed.
  • the components are classified by function and shown as blocks independent of each other.
  • it is difficult to separate the components for each function and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved in a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately paraphrased according to the situation.
  • the size, the thickness of the layer, or the area is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.
  • electrode and “wiring” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wiring” are integrally formed.
  • voltage and potential can be paraphrased as appropriate.
  • the voltage is a potential difference from a reference potential.
  • the reference potential is a ground voltage (ground voltage)
  • the voltage can be paraphrased as a potential.
  • the ground potential does not always mean 0V.
  • the potential is relative, and the potential given to the wiring or the like may be changed depending on the reference potential.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration, a device structure, and the like.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • a and B are connected means that A and B are electrically connected.
  • the fact that A and B are electrically connected refers to an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) between A and B. ) Is present, it means a connection capable of transmitting an electric signal between A and B.
  • the case where A and B are electrically connected includes the case where A and B are directly connected.
  • the fact that A and B are directly connected means that the electric signal between A and B is transmitted between A and B via wiring (or an electrode) or the like without going through the object.
  • a possible connection is a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.
  • a switch is a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows.
  • the channel length means, for example, in the top view of a transistor, a region or a channel where a semiconductor (or a part where a current flows in the semiconductor when the transistor is on) and a gate overlap is formed.
  • the distance between the source and the drain in the area means, for example, in the top view of a transistor, a region or a channel where a semiconductor (or a part where a current flows in the semiconductor when the transistor is on) and a gate overlap is formed. The distance between the source and the drain in the area.
  • the channel width is a source in, for example, a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap, or a region where a channel is formed.
  • WEL Wiring
  • WOL Wiring
  • 10 Semiconductor device
  • 12 Drive circuit
  • 14 Control circuit
  • 20_E Arithmetic block unit
  • 20_O Arithmetic block unit
  • 21_E Arithmetic block
  • 21_O Calculation block
  • 43_E Buffer circuit
  • 43_O Buffer circuit
  • 44 Switching Circuit, 45: Arithmetic circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Mathematical Physics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • General Health & Medical Sciences (AREA)
  • Neurology (AREA)
  • Biophysics (AREA)
  • Molecular Biology (AREA)
  • Software Systems (AREA)
  • Computational Linguistics (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Databases & Information Systems (AREA)
  • Physiology (AREA)
  • Neurosurgery (AREA)
  • Algebra (AREA)
  • Semiconductor Memories (AREA)
  • Memory System (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Complex Calculations (AREA)
  • Non-Volatile Memory (AREA)
PCT/IB2021/055989 2020-07-17 2021-07-05 半導体装置 Ceased WO2022013677A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US18/013,916 US20230297339A1 (en) 2020-07-17 2021-07-05 Semiconductor device
KR1020237004297A KR20230038731A (ko) 2020-07-17 2021-07-05 반도체 장치
CN202180046426.9A CN115735208A (zh) 2020-07-17 2021-07-05 半导体装置
JP2022535980A JP7583046B2 (ja) 2020-07-17 2021-07-05 半導体装置
JP2024192009A JP7723821B2 (ja) 2020-07-17 2024-10-31 半導体装置
JP2025129610A JP2025169289A (ja) 2020-07-17 2025-08-01 半導体装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2020-122483 2020-07-17
JP2020122483 2020-07-17
JP2020-200722 2020-12-03
JP2020200722 2020-12-03

Publications (1)

Publication Number Publication Date
WO2022013677A1 true WO2022013677A1 (ja) 2022-01-20

Family

ID=79554311

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2021/055989 Ceased WO2022013677A1 (ja) 2020-07-17 2021-07-05 半導体装置

Country Status (5)

Country Link
US (1) US20230297339A1 (https=)
JP (3) JP7583046B2 (https=)
KR (1) KR20230038731A (https=)
CN (1) CN115735208A (https=)
WO (1) WO2022013677A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017228295A (ja) * 2016-06-20 2017-12-28 東芝メモリ株式会社 演算装置
JP2019046375A (ja) * 2017-09-06 2019-03-22 株式会社半導体エネルギー研究所 半導体装置、電子部品、及び電子機器
JP2020057306A (ja) * 2018-10-04 2020-04-09 富士通株式会社 最適化装置及び最適化装置の制御方法
JP2020068048A (ja) * 2018-10-18 2020-04-30 株式会社デンソー 人工ニューラルネットワーク回路及び人工ニューラルネットワーク回路における学習値切替方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6623947B2 (ja) 2016-06-17 2019-12-25 富士通株式会社 情報処理装置、イジング装置及び情報処理装置の制御方法
US20190122104A1 (en) 2017-10-19 2019-04-25 General Electric Company Building a binary neural network architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017228295A (ja) * 2016-06-20 2017-12-28 東芝メモリ株式会社 演算装置
JP2019046375A (ja) * 2017-09-06 2019-03-22 株式会社半導体エネルギー研究所 半導体装置、電子部品、及び電子機器
JP2020057306A (ja) * 2018-10-04 2020-04-09 富士通株式会社 最適化装置及び最適化装置の制御方法
JP2020068048A (ja) * 2018-10-18 2020-04-30 株式会社デンソー 人工ニューラルネットワーク回路及び人工ニューラルネットワーク回路における学習値切替方法

Also Published As

Publication number Publication date
JPWO2022013677A1 (https=) 2022-01-20
JP2025169289A (ja) 2025-11-12
CN115735208A (zh) 2023-03-03
JP7583046B2 (ja) 2024-11-13
JP2025013424A (ja) 2025-01-24
US20230297339A1 (en) 2023-09-21
JP7723821B2 (ja) 2025-08-14
KR20230038731A (ko) 2023-03-21

Similar Documents

Publication Publication Date Title
JP7684946B2 (ja) 半導体装置
JP7560469B2 (ja) 半導体装置
WO2022029541A1 (ja) 半導体装置
JP2025065240A (ja) 半導体装置
CN110506325A (zh) 半导体装置及半导体装置的制造方法
JP7829754B2 (ja) 半導体装置
WO2022013677A1 (ja) 半導体装置
JP7651555B2 (ja) 半導体装置
WO2021130591A1 (ja) 半導体装置
JP7624980B2 (ja) 半導体装置
TW202331707A (zh) 半導體裝置、顯示裝置、資料處理系統以及半導體裝置的控制系統
WO2024013604A1 (ja) 半導体装置
CN118401927A (zh) 半导体装置、显示装置、数据处理系统以及半导体装置的控制系统

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21842508

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022535980

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20237004297

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21842508

Country of ref document: EP

Kind code of ref document: A1