WO2022012227A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022012227A1
WO2022012227A1 PCT/CN2021/098966 CN2021098966W WO2022012227A1 WO 2022012227 A1 WO2022012227 A1 WO 2022012227A1 CN 2021098966 W CN2021098966 W CN 2021098966W WO 2022012227 A1 WO2022012227 A1 WO 2022012227A1
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WIPO (PCT)
Prior art keywords
substrate
orthographic projection
data line
electrode
spacer
Prior art date
Application number
PCT/CN2021/098966
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English (en)
French (fr)
Inventor
张春旭
张云天
姜晓婷
杨海鹏
戴珂
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/772,674 priority Critical patent/US11740523B2/en
Publication of WO2022012227A1 publication Critical patent/WO2022012227A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device including the same.
  • the liquid crystal display includes a liquid crystal display panel, the liquid crystal display panel includes an array substrate and a cell alignment substrate arranged for cell alignment, and a liquid crystal layer located between the array substrate and the cell alignment substrate, and the array substrate and the cell alignment substrate are sealed by a frame sealant.
  • a spacer with elastic restoring force is usually arranged between the array substrate and the cell-to-cell substrate. material (referred to as PS).
  • PS material
  • the spacer is in a compressed state and functions to support the liquid crystal cell, thereby keeping the cell thickness of the liquid crystal display panel stable and uniform.
  • a display panel comprising:
  • a first substrate, the first substrate includes:
  • each of the gate lines disposed in a row direction, and each of the data lines disposed in a column direction;
  • each Each sub-pixel includes a light-transmitting area
  • the plurality of spacers include at least one first spacer, the plurality of data lines include at least a first data line, the plurality of sub-pixels include a first sub-pixel, and the first data line is adjacent to all the first sub-pixel setting;
  • the orthographic projection of the first spacer on the second substrate is adjacent to the orthographic projection of the light-transmitting region of the first sub-pixel on the second substrate, where the first spacer is located.
  • the orthographic projection on the second substrate and the orthographic projection of the first data line on the second substrate are arranged at intervals;
  • the first data line has a main body portion and a bent portion, the projection of the bent portion in the column direction at least partially overlaps with the projection of the first spacer in the column direction, and the bent portion at least partially overlaps.
  • the orthographic projection of the body portion on the second substrate relative to the orthographic projection of the body portion on the second substrate is directed away from the orthographic projection of the first spacer on the second substrate Bent direction.
  • the bent portion includes a bent main body portion and two bent connection portions, and the orientation of the bent main body portion and the main body portion of the first data line is parallel to each other, the One end of the bent main body portion is connected to a section of the main body portion of the first data line through one bent connection portion, and the other end of the bent main body portion is connected to the first data line through another bent connection portion another section of the main body.
  • the plurality of data lines further include a second data line disposed adjacent to the first sub-pixel; the first data line is on the second substrate
  • the orthographic projection of the second data line and the orthographic projection of the second data line on the second substrate are respectively located on both sides of the orthographic projection of the first spacer on the second substrate in the row direction, The distance along the row direction between the orthographic projection of the second data line on the second substrate and the orthographic projection of the first spacer on the second substrate is greater than the first The distance along the row direction between the orthographic projection of the data line on the second substrate and the orthographic projection of the first spacer on the second substrate.
  • the second data line has a main body portion and a bent portion
  • the projection of the bent portion of the second data line in the column direction is the same as that of the first spacer in the
  • the projections in the column direction at least partially overlap, and the orthographic projection of the bent portion of the second data line on the second substrate is relative to the projection of the main portion of the second data line on the second substrate.
  • the orthographic projection is bent away from the orthographic projection of the first spacer on the second substrate.
  • the bent portion of the second data line includes a bent main body portion and two bent connection portions, and the bent main portion of the second data line and the bent main portion of the second data line
  • the arrangement directions of the main body parts are parallel to each other, one end of the bent main body part of the second data line is connected to a section of the main body part of the second data line through a bending connection part of the second data line, and the second data line is connected to a section of the main body part of the second data line.
  • the other end of the bent main body portion of the data line is connected to another section of the main body portion of the second data line through another bent connection portion of the second data line.
  • the plurality of gate lines include a first gate line disposed adjacent to the first sub-pixel, and an orthographic projection of the first spacer on the second substrate falls within the The first grid line is in the orthographic projection of the second substrate.
  • the first gate line includes a first widened portion and a second widened portion, and the first widened portion and the second widened portion are on the second substrate is located between the orthographic projection of the first data line on the second substrate and the orthographic projection of the second data line on the second substrate; the first widened portion and The dimension of each of the second widened portions along the column direction is larger than the dimension of other portions of the first gate lines along the column direction, and the first spacer is in the second substrate The orthographic projection on falls within the orthographic projection of the first widened portion of the first grid line on the second substrate.
  • the second substrate further includes a plurality of thin film transistors disposed on the second substrate, the plurality of thin film transistors including at least one first sub-pixel disposed adjacent to the first sub-pixel A thin film transistor; the orthographic projection of the first thin film transistor on the second substrate falls within the orthographic projection of the second widened portion of the first gate line on the second substrate.
  • the orthographic projection of the first thin film transistor on the second substrate is located between the orthographic projection of the first spacer on the second substrate and the second data
  • the bends of the lines are between orthographic projections on the second substrate.
  • the first grid line further includes a plurality of inclined portions, and the setting direction of the orthographic projection of each inclined portion on the second substrate forms an included angle with an acute angle with the row direction;
  • the orthographic projection of the bent portion of the first data line on the second substrate at least partially overlaps with the orthographic projection of an inclined portion of the first gate line on the second substrate, and the The orthographic projection of the bent portion of the second data line on the second substrate at least partially overlaps the orthographic projection of the other inclined portion of the first gate line on the second substrate.
  • the plurality of sub-pixels further includes a second sub-pixel adjacent to the first sub-pixel
  • the plurality of data lines further includes a third data line
  • the first data line and The third data lines are respectively located on both sides of the second sub-pixels
  • the third data lines include bending parts, and the projection of the bending parts of the third data lines in the column direction is the same as the first
  • the projection of each of the bent portion of the data line and the bent portion of the second data line in the column direction at least partially overlaps, and the bending direction of the bent portion of the third data line is the same as that of the third data line.
  • the bending direction of one of the bending portion of the first data line and the bending portion of the second data line is the same.
  • the second substrate further includes a plurality of common electrode lines disposed on the second substrate, and each of the common electrode lines is disposed along the row direction; the plurality of common electrode lines
  • the electrode line includes a first common electrode line, the orthographic projection of the first common electrode line on the second substrate is adjacent to the orthographic projection of the first grid line on the second substrate, the
  • the first common electrode line has a main body portion and a bent portion, and the projection of the bent portion of the first common electrode line in the row direction at least partially overlaps the projection of the first widened portion in the row direction , the orthographic projection of the bent portion of the first common electrode line on the second substrate faces away from the orthographic projection of the main portion of the first common electrode line on the second substrate
  • the first widened portion is bent in the direction of the orthographic projection of the second substrate.
  • the first widened portion protrudes toward the first common electrode line with respect to each of the second widened portion and the inclined portion.
  • an interval along the column direction between the first widened portion and the bent portion of the first common electrode line is equal to the distance between the second widened portion and the first common electrode line.
  • the spacing distance between the main parts of the common electrode lines along the column direction is equal to the distance between the second widened portion and the first common electrode line.
  • the size of the bent portion of the first common electrode line along the column direction is larger than the size of the main portion of the first common electrode line along the column direction.
  • the first thin film transistor includes an active layer, a gate electrode, a first electrode and a second electrode
  • the second substrate further includes a pixel electrode disposed on the second substrate;
  • the first electrode is electrically connected to the second data line
  • the second electrode is electrically connected to the pixel electrode;
  • the first electrode has a first part and a second part, and the first part of the first electrode directly Extending from the second data line along the row direction, the orthographic projection of the second portion of the first electrode on the second substrate falls into the second widened portion on the second substrate In the orthographic projection on the second electrode;
  • the second electrode has a first part and a second part, and the orthographic projection of the first part of the second electrode on the second substrate is the same as that of the pixel electrode on the second substrate orthographic projections on the second substrate at least partially overlap, and the orthographic projection of the second portion of the second electrode on the second substrate falls within the orthographic projection of the second widening portion on the second substrate ; the size of the first part of the first
  • the second portion of the first electrode is parallel to the second portion of the second electrode, and the second portion of the second electrode is closer than the second portion of the first electrode the first widened portion.
  • the orthographic projection of the first spacer on the second substrate is the difference between the orthographic projection of the second portion of the second electrode on the second substrate and spaced apart along the row direction by a second distance, the first distance being equal to the second distance.
  • the first distance is greater than or equal to 10 microns.
  • the second substrate includes a first raised structure and a second raised structure on the second substrate, the first raised structure and the second raised structure are located on both sides of the first spacer along the row direction; the orthographic projection of the first protruding structure on the second substrate and the bent portion of the first data line are on the second The orthographic projections on the two substrates at least partially overlap, and the orthographic projection of the second raised structure on the second substrate and the orthographic projection of the first thin film transistor on the second substrate at least partially overlap overlap.
  • the second substrate further includes third and fourth raised structures on the second substrate, the third and fourth raised structures
  • the structures are located on both sides of the first spacer along the column direction; the orthographic projection of the third protruding structure on the second substrate and the bent portion of the first common electrode line are located at the same location.
  • the orthographic projection on the second substrate at least partially overlaps, and the orthographic projection of the fourth protruding structure on the second substrate and the pixel electrode of the first sub-pixel on the second substrate The orthographic projections of , at least partially overlap.
  • the second substrate includes a first conductive layer and a second conductive layer disposed on the second substrate, and the second conductive layer is disposed away from the first conductive layer.
  • the gate line and the common electrode line are located in the first conductive layer
  • the data line and the first electrode and the second electrode of the thin film transistor are located in the second conductive layer Floor.
  • the third protrusion structure includes a first protrusion in the second conductive layer, the orthographic projection of the first protrusion on the second substrate falls within the The bent portion of the first common electrode line is in the orthographic projection of the second substrate.
  • the fourth protrusion structure includes a second protrusion and a third protrusion, the second protrusion is located on the first conductive layer, and the third protrusion is located on the first conductive layer. Two conductive layers, the orthographic projection of the third boss on the second substrate falls within the orthographic projection of the second boss on the second substrate.
  • the orthographic projection of each of the first spacer and the first widening on the second substrate has an octagonal shape, the first spacer The area of the orthographic projection of the object on the second substrate is smaller than the area of the orthographic projection of the first widened portion on the second substrate.
  • each of the first data line, the second data line and the third data line includes a plurality of bent portions; the same data line includes a plurality of bent portions
  • the bending directions of the parts are the same as each other, or the bending directions of at least two bending parts among the plurality of bending parts included in the same data line are different from each other.
  • the first substrate further includes a black matrix disposed on the first substrate, the gate lines, the data lines, the common electrode lines and the thin film transistors Each orthographic projection on the first substrate falls within the orthographic projection of the black matrix on the first substrate.
  • the first sub-pixel is a red sub-pixel.
  • the second substrate includes a first electrode layer and a second electrode layer disposed on the second substrate, and the second electrode layer is disposed away from the first electrode layer.
  • the second substrate further includes a common electrode disposed on the second substrate, and the pixel electrode is disposed in one of the first electrode layer and the second electrode layer , the common electrode is disposed in the other of the first electrode layer and the second electrode layer.
  • a display device comprising the display panel as described above.
  • FIG. 1 is a schematic cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure
  • FIG. 2 is a schematic plan view schematically illustrating the distribution of spacers on a display panel according to an embodiment of the present disclosure
  • FIG. 3 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, wherein a planar structure between two adjacent sub-pixels located in the same column is schematically shown;
  • FIG. 4 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which columns of sub-pixels are schematically shown;
  • FIG. 5 is a plan view of a first conductive layer included in the display panel of FIG. 3;
  • FIG. 6 is a plan view of a second conductive layer included in the display panel of FIG. 3;
  • Figure 7 is a cross-sectional view taken along line AA' in Figure 3;
  • Figure 8 is a cross-sectional view taken along line BB' in Figure 3;
  • Figure 9 is a cross-sectional view taken along line CC' in Figure 3;
  • FIG. 10 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, wherein the relative positional relationship between the black matrix on the first substrate and the film layer structure on the second substrate is schematically shown;
  • FIGS. 11A and 11B are partial plan views, respectively, of a display panel according to some exemplary embodiments of the present disclosure, in which rows of sub-pixels and data lines extending in the rows of sub-pixels are schematically shown;
  • FIG. 12 is a schematic diagram of a display device according to some exemplary embodiments of the present disclosure.
  • the X axis, the Y axis and the Z axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a broader sense.
  • the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as X only, Y only, Z only, or Any combination of two or more of X, Y and Z such as XYZ, XYY, YZ and ZZ.
  • the term "and/or" includes any and all combinations of one or more of the associated listed items.
  • first the terms “first”, “second”, etc. may be used herein to describe various components, components, elements, regions, layers and/or sections, these components, components, elements, regions, layers and/or parts shall not be limited by these terms. Rather, these terms are used to distinguish one element, member, element, region, layer and/or section from another. Thus, for example, a first part, first member, first element, first region, first layer and/or first section discussed below could be termed a second part, second member, second element, second region , the second layer and/or the second portion without departing from the teachings of the present disclosure.
  • spatially relational terms eg, "upper,” “lower,” “left,” “right,” etc. may be used herein to describe one element or feature relative to another element or feature as shown in the figures relation. It should be understood that the spatially relational terms are intended to encompass other different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the expression “height” or “thickness” refers to a dimension along a surface perpendicular to a display panel (eg, a color filter substrate or an array substrate) on which the respective film layers are disposed , that is, the size along the light-emitting direction of the display panel, or the size along the Z direction in the drawings.
  • expressions such as “projection in the row direction”, “projection in the X direction” and other similar expressions mean the following: in the plane formed by the row direction and the column direction, that is, in the XY plane, the layers of the plane, The projection of an element, part, structure or device onto the row or X direction; if considered in terms of a three-dimensional structure, the expression means: a three-dimensional layer, element, part, structure or device is projected onto a plane perpendicular to the column direction Or a projection in a plane perpendicular to the Y direction.
  • expressions such as “projection in the column direction”, “projection in the Y direction” and other similar expressions mean the following: in the plane formed by the column direction and the column direction, that is, in the XY plane, the plane layers, elements , component, structure or device is projected onto the column direction or Y direction; if considered from the three-dimensional structure, the expression means: the three-dimensional layer, element, component, structure or device is projected onto a plane perpendicular to the row direction or A projection into a plane perpendicular to the X direction.
  • Embodiments of the present disclosure provide a display panel and a display device.
  • the display panel may include: a first substrate including: a first substrate; and a plurality of spacers disposed on the first substrate; and a plurality of spacers disposed opposite to the first substrate
  • a second substrate, the second substrate includes: a second substrate; a plurality of gate lines and a plurality of data lines arranged on the second substrate, each of the gate lines is arranged along the row direction, and each of the gate lines is arranged along the row direction.
  • the data lines are arranged in a column direction; and a plurality of sub-pixels are arranged on the second substrate in an array along the row direction and the column direction, the plurality of gate lines and the plurality of data lines surround forming the plurality of sub-pixels, each of which includes a light-transmitting area, wherein the plurality of spacers includes at least one first spacer, the plurality of data lines includes at least a first data line, and the The plurality of sub-pixels includes a first sub-pixel, the first data line is disposed adjacent to the first sub-pixel; the orthographic projection of the first spacer on the second substrate is adjacent to the first sub-pixel The orthographic projection of the light-transmitting area on the second substrate, the orthographic projection of the first spacer on the second substrate and the orthographic projection of the first data line on the second substrate The projections are arranged at intervals; the first data line has a main body portion and a bent portion, and the projection of the bent portion in the column direction at least partially overlaps with the projection
  • FIG. 1 is a schematic cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure.
  • the display panel may be a liquid crystal display panel.
  • the liquid crystal display panel includes a first substrate 1 , a second substrate 2 arranged in a cell-to-cell manner with the first substrate 1 , and a liquid crystal molecular layer 3 arranged between the first substrate 1 and the second substrate 2 .
  • the liquid crystal display panel at least further includes an alignment film 4 disposed on the side of the second substrate 2 facing the first substrate 1 and a spacer 5 disposed on the first substrate 1 or the second substrate 2 . It should be understood that an alignment film is also provided on the side of the first substrate 1 facing the second substrate 2 .
  • spacers 5 may be provided on the first substrate 1 .
  • the alignment film 4 can induce alignment of the liquid crystal molecules in the liquid crystal molecular layer 3 ; for example, an alignment channel can be formed on the surface of the alignment film 4 through a rubbing process, thereby inducing alignment of the liquid crystal molecules in the liquid crystal molecular layer 3 .
  • an alignment channel can be formed on the surface of the alignment film 4 through a rubbing process, thereby inducing alignment of the liquid crystal molecules in the liquid crystal molecular layer 3 .
  • the liquid crystal display panel displays a dark state, the liquid crystal molecules in the liquid crystal molecule layer 3 are not deflected, and light cannot pass through the liquid crystal display panel.
  • the liquid crystal display panel displays a bright state, the liquid crystal molecules in the liquid crystal molecule layer 3 are deflected under the action of an electric field, and light can pass through the liquid crystal display panel.
  • the liquid crystal display panel can also display light having a color corresponding to the color filter pattern through the function of the color filter pattern disposed
  • the spacers in the liquid crystal display panel play a role in maintaining and ensuring the uniformity of the cell thickness of the liquid crystal cell at each position, thereby maintaining the stability and uniformity of the cell thickness of the liquid crystal display panel.
  • the first substrate 1 is provided with a black matrix 12 and a color filter layer, and the orthographic projection of the spacer 5 on the first substrate 1 falls within the orthographic projection of the black matrix 12 on the first substrate 1 . That is, on the one hand, the size of the spacer 5 cannot be set too small.
  • the size here may refer to the diameter of the circle; when the orthographic projection of the spacer 5 on the first substrate 1 is a rectangle , the dimensions here may refer to the length and width of the rectangle. In this way, it can be ensured that the supporting area of the spacer 5 is large enough, which is beneficial to provide sufficient supporting force.
  • the spacer 5 since the spacer 5 needs to fall within the range of the black matrix 12, the spacer also restricts the aperture ratio of the liquid crystal display panel to some extent. That is to say, the size of the spacer 5 cannot be set too large, otherwise the aperture ratio of the display panel will be reduced.
  • the orthographic projection of the spacer 5 on the first substrate 1 may have a circular shape, and the diameter of the spacer 5 is in the range of 15-30 ⁇ m, for example is about 20 microns.
  • FIG. 2 is a schematic plan view schematically illustrating the distribution of spacers on a display panel according to an embodiment of the present disclosure.
  • the plurality of spacers 5 may include a plurality of main spacers (may be Main PS in English) 51 and a plurality of secondary spacers (sub PS in English) 52 .
  • the spacers 5 (including the main spacer 51 and the cut spacer 52 ) are represented by a “hexagon”, which does not mean that the main spacer and the The shape of the sub-spacer is limited, and the main and sub-spacers can adopt various shapes of spacers known in the art, which will not be repeated here.
  • the shape of the spacer 5 in the schematic plan view of FIG. 2 may be a circle, an ellipse, a rectangle, a rounded rectangle, or the like.
  • the height of the primary spacer 51 is greater than the height of the secondary spacer 52 .
  • the height of the secondary spacer 52 may be 70% to 95% of the height of the main spacer 51 .
  • the main spacer 51 plays a supporting role.
  • the auxiliary spacer 52 can also play a supporting role. Support to improve pressure resistance, and, when crushing is eliminated, the restoring force can be provided by the primary and secondary spacers.
  • FIG. 3 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which a planar structure between two adjacent sub-pixels located in the same column is schematically shown.
  • 4 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which columns of sub-pixels are schematically shown. It should be noted that, in the plan views of FIGS. 3 and 4 , in order to clearly show the relative positional relationship between the spacers on the first substrate and the film layer structure on the second substrate, the first substrate is omitted. Some layer structures formed (eg black matrix).
  • FIG. 5 is a plan view of a first conductive layer included in the display panel of FIG. 3 .
  • FIG. 5 is a plan view of a first conductive layer included in the display panel of FIG. 3 .
  • FIG. 6 is a plan view of a second conductive layer included in the display panel of FIG. 3 .
  • Fig. 7 is a cross-sectional view taken along line AA' in Fig. 3 .
  • Fig. 8 is a cross-sectional view taken along line BB' in Fig. 3 .
  • Fig. 9 is a cross-sectional view taken along line CC' in Fig. 3 .
  • 10 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which the relative positional relationship of the black matrix on the first substrate and the film layer structure on the second substrate is schematically shown.
  • the display panel may include a plurality of sub-pixels SP arranged in an array, that is, the plurality of sub-pixels SP along a row direction (X direction in the drawings) and a column direction ( Y direction in the figure) arrangement.
  • the plurality of sub-pixels SP may include at least a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3, for example, the first sub-pixel, the second sub-pixel and the third sub-pixel may be red sub-pixels, green sub-pixels, respectively. pixel and blue subpixel.
  • the first sub-pixel, the second sub-pixel and the third sub-pixel may constitute one pixel.
  • 7680*4320 pixels are set.
  • embodiments of the present disclosure are not limited thereto, and the first sub-pixel, the second sub-pixel and the third sub-pixel may be sub-pixels of other colors.
  • the plurality of spacers 5 are respectively provided in the plurality of sub-pixels SP. For example, at most one spacer 5 (one of the main spacer 51 and the sub-spacer 52 ) is provided in each sub-pixel SP.
  • the display panel includes a plurality of main spacers 51 and a plurality of secondary spacers 52 .
  • the number of primary spacers 51 may be smaller than the number of secondary spacers 52 .
  • 8 rows and 24 columns (ie, 192) of sub-pixels SP are shown, wherein 64 spacers 5 are provided, specifically 4 main spacers 51 are provided, 60 subspacers 52. With this arrangement, it can be ensured that the spacer has a better supporting effect on the liquid crystal cell.
  • each sub-pixel is provided with a spacer, but some sub-pixels are provided with the spacer.
  • the embodiments of the present disclosure are not limited to Therefore, in other embodiments, according to the actual needs of the distribution density, a plurality of spacers may also be provided in one sub-pixel, or one spacer may be provided in each sub-pixel.
  • no spacer is provided in a sub-pixel adjacent to the sub-pixel where each main spacer 51 is located.
  • the display panel according to the embodiment of the present disclosure is particularly suitable for the ADS (ADvanced Super Dimension Switch, advanced super-dimensional field switching technology) mode, and the embodiments described herein are also described by taking the ADS mode display panel as an example.
  • the embodiment of the present disclosure is not limited to this, and it can also be applied to display devices of various other modes, such as TN (Twisted Nematic, twisted nematic) mode, VA (Vertical Alignment, vertical alignment) mode and other modes.
  • the display panel may be a touch display panel.
  • the first substrate 1 may be a color filter substrate
  • the second substrate 2 may be an array substrate.
  • the first substrate 1 may include a first substrate 10 and a black matrix 12 disposed on the first substrate 10 .
  • the respective spacers 5 are located on the first substrate 10 , and their orthographic projections on the first substrate 10 all fall into the black matrix 12 in the first substrate 10 . In an orthographic projection on a substrate 10 .
  • the second substrate 2 may include a second substrate 20 , gate lines GL, common electrode lines CL and data lines DL disposed on the second substrate 20 .
  • the gate lines GL and the common electrode lines CL are arranged in the row X direction, and the data lines DL are arranged in the column Y direction.
  • the intersection of the gate line GL and the data line DL defines a plurality of sub-pixels SP.
  • Each sub-pixel SP includes a light-transmitting area TA, from which light can exit the display panel, thereby realizing a display function. It should be understood that the orthographic projection of the light transmission area TA of each sub-pixel SP on the second substrate 20 does not overlap with the orthographic projection of the black matrix 12 on the second substrate 20 .
  • Orthographic projections of each spacer 5 various data lines including gate line GL, common electrode line CL and data line DL, and various thin film transistors for driving each sub-pixel on the second substrate 20 all fall into The black matrix 12 is in an orthographic projection on the second substrate 20 .
  • FIG. 3 and FIG. 4 it schematically shows a partial plane structure of pixels located in two adjacent rows and the opaque area between these two rows of adjacent pixels, wherein, FIG. 3 only shows one column of sub-pixels. pixel.
  • the two adjacent rows of pixels may be respectively referred to as first row pixels (upper row of pixels in FIG. 4 ) P1 and second row pixels (lower row of pixels in FIG. 4 ) P2 .
  • each row of pixels may respectively include a plurality of pixels arranged along the row X direction, and each pixel may include a first subpixel SP1 , a second subpixel SP2 and a third subpixel SP3 sequentially arranged along the row X direction.
  • the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 may be a red sub-pixel, a green sub-pixel and a blue sub-pixel, respectively.
  • each of the first subpixel SP1, the second subpixel SP2 and the third subpixel SP3 includes a light transmission area TA.
  • a grid line GL and a common electrode line CL are both arranged along the row X direction, and the grid The line GL and the common electrode line CL are arranged at intervals along the column Y direction.
  • the gate line GL is used for supplying gate scan signals to each sub-pixel SP in the first row of pixels P1.
  • the common electrode line CL is electrically connected to the common electrodes of the sub-pixels in the first row and the sub-pixels in the second row.
  • the common electrode line CL may include a plurality of portions extending toward the first row of sub-pixels, and the orthographic projection of the plurality of portions on the second substrate may be at the same level as the common electrodes of the respective sub-pixels in the first row of sub-pixels.
  • the orthographic projections on the two substrates overlap at least in part, so that the plurality of parts can be electrically connected to the common electrodes of the respective sub-pixels in the first row of sub-pixels through via holes.
  • data lines DL are respectively provided on both sides of the first sub-pixel SP1 along the X direction.
  • the data line on the right side of the first subpixel SP1 is called the first data line DLA
  • the data line on the left side of the first subpixel SP1 is called the second data line DLB.
  • a gate line GL and a common electrode line CL are arranged in sequence.
  • the gate line GL that supplies the gate scan signal to the first sub-pixel SP1 is referred to as the first sub-pixel SP1.
  • first common electrode line CL a common electrode line disposed adjacent to the first gate line GL.
  • first common electrode line CL a common electrode line disposed adjacent to the first gate line GL.
  • a spacer 5 in a light-tight area between the first row of pixels P1 and the second row of pixels P2 is schematically shown. It should be noted that the spacer 5 may be the main spacer 51 or the secondary spacer 52 . It can also be said that in the embodiment of FIG. 3 , the spacer 5 is arranged in the first sub-pixel SP1 .
  • the expression "a spacer is arranged in a sub-pixel” or "a sub-pixel where the spacer is located” means: the orthographic projection of the spacer on the substrate and the sub-pixel on the substrate The orthographic projection of the sub-pixel overlaps or falls within the orthographic projection of the sub-pixel on the substrate, or in other words, the orthographic projection of the spacer on the substrate and the non-transmissive area adjacent to the sub-pixel's light-transmitting area Orthographic projections of regions on the substrate at least partially overlap.
  • the spacer 5 is disposed in one of the first sub-pixels SP1 in the first row of pixels P1, which means that the spacer 5 is disposed in the second row close to the first sub-pixel SP1 in the first row of pixels P1.
  • the orthographic projection of the spacer 5 on the substrate at least partially overlaps the orthographic projection of the non-light-transmitting region of the first sub-pixel SP1 on the substrate.
  • the first gate line GL may include a first widened part GL1 and a second widened part GL2 .
  • the size of the first widened portion GL1 and the size of the second widened portion GL2 are larger, and larger than the first gate line GL except the The size of the portion other than the first widened portion GL1 and the second widened portion GL2.
  • the orthographic projection of the first widened portion GL1 on the second substrate 20 may have an approximate polygonal shape (eg, an octagon or a regular octagon), and the normal projection of the second widened portion GL2 on the second substrate 20
  • the projection can have an approximately rectangular shape (eg, a rounded rectangle). It should be understood that these shapes are not limitations to the embodiments of the present disclosure, and the first widened part GL1 and the second widened part GL2 may also have other suitable shapes.
  • the orthographic projection of the spacer 5 on the second substrate 20 may have an approximate polygonal shape (eg, an octagon or a regular octagon). It should be understood that these shapes are not limitations to the embodiments of the present disclosure, and the spacer 5 may also have other suitable shapes.
  • the spacer includes an upper surface facing the first substrate and a lower surface away from the first substrate, and the area of the upper surface of the spacer may be larger than the area of the lower surface, that is, the The cross section of the spacer has a trapezoidal shape.
  • the orthographic projection of the spacer on the first substrate or the second substrate may refer to the upper surface (ie, the surface with a larger area) of the spacer on the first substrate or the second substrate. Orthographic projection on the substrate.
  • the orthographic projection of a spacer 5 (herein, for convenience of description, may be referred to as a first spacer) on the second substrate 20 falls into the first gate line GL at the In the orthographic projection on the two substrates 20 .
  • the orthographic projection of the first spacer 5 on the second substrate 20 falls within the orthographic projection of the first widened portion GL1 of the first gate line GL on the second substrate 20 .
  • the second substrate 2 may further include thin film transistors 6 disposed on the second substrate 20 .
  • the thin film transistor 6 may include an active layer ACT, a gate electrode 6G, a first electrode 6S (eg, one of the source and drain electrodes) and a second electrode 6D (eg, the other of the source and drain electrodes).
  • the thin film transistor 6 may also be referred to as a first transistor.
  • the orthographic projection of the thin film transistor 6 on the second substrate 20 at least partially overlaps the orthographic projection of the first gate line GL on the second substrate 20 .
  • the orthographic projection of the thin film transistor 6 on the second substrate 20 at least partially overlaps the orthographic projection of the second widened portion GL2 of the first gate line GL on the second substrate 20 .
  • a portion of the first gate line GL forms the gate electrode 6G of the thin film transistor 6 .
  • the orthographic projection of a portion of the first gate line GL on the second substrate 20 coincides with the orthographic projection of the active layer ACT of the thin film transistor 6 on the second substrate 20 , for example, the second widening of the first gate line GL
  • the orthographic projection of a portion of the portion GL2 on the second substrate 20 coincides with the orthographic projection of the active layer ACT of the thin film transistor 6 on the second substrate 20 .
  • the portion of the gate line GL forms the gate electrode 6G of the thin film transistor 6 .
  • the layer where the gate lines GL are located is referred to as the first conductive layer
  • the layer where the data lines DL are located is referred to as the second conductive layer.
  • the first conductive layer and the second conductive layer are different layers.
  • the second conductive layer is disposed on a side of the first conductive layer away from the second substrate 20 .
  • the common electrode line CL may be located on the first conductive layer.
  • the first electrode 6S and the second electrode 6D of the thin film transistor may be located on the second conductive layer.
  • the first electrode 6S of the thin film transistor 6 may be electrically connected to the left data line DL (ie, the second data line DLB), and the second electrode 6D may be electrically connected to the pixel electrode 7 (described in detail below).
  • the data signal supplied by the data line DL (eg, the second data line) can be transmitted to the pixel electrode 7, thereby generating a signal for controlling the liquid crystal Molecular electric field.
  • the orthographic projection of the first spacer 5 on the second substrate 20 is located in the orthographic projection of the thin film transistor 6 on the second substrate 20 and the data line DL located on the right side in the first between the orthographic projections on the two substrates 20 . That is, the orthographic projection of the first widened portion GL1 on the second substrate 20 is located on the orthographic projection of the second widened portion GL2 on the second substrate 20 and the data line DL on the right side is on the second substrate 20 between the orthographic projections.
  • the data line DL on the right side (ie, the first data line DLA) has a bent portion DL1. That is, the first data line DLA does not extend straight along the Y direction, but has a bent portion DL1 at a position corresponding to the spacer 5 . Specifically, the projection of the spacer 5 in the Y direction falls within the projection of the bent portion DL1 in the Y direction.
  • the projection of the first widened portion GL1 in the Y direction and the projection of the bent portion DL1 in the Y direction at least partially overlap.
  • the first data line DLA has a main body portion DL2 and a bent portion DL1.
  • the bent portion DL1 is further away from the first spacer 5 or the first widened portion GL1 than the main body portion DL2.
  • the orthographic projection of the bent portion DL1 on the second substrate 20 is farther from the first spacer 5 or the orthographic projection of the main body portion DL2 on the second substrate 20
  • An orthographic projection of the first widened portion GL1 on the second substrate 20 That is, in the plan view shown in FIG.
  • the distance along the X direction is greater than the distance between the orthographic projection of the main body portion DL2 on the second substrate 20 and the orthographic projection of the first spacer 5 or the first widening portion GL1 on the second substrate 20 along the distance in the X direction.
  • the bent portion DL1 also has a bent main body portion DL11 and two bent connection portions DL12.
  • the bent main body portion DL11 extends straight in the Y direction.
  • the two bending connection parts DL12 are respectively located at both ends of the bending main body part DL11, one bending connection part DL12 at one end is connected to a section of the main body part DL2, and one bending connection part DL12 at the other end is connected to the other part of the main body part DL2.
  • the data line DL is described with different parts (eg, the main body part DL2, the bent part DL1, the bent main body part DL11, the bent connection part DL12), it should be understood that these parts (eg, the main body part DL2, the bending part DL1, the bending main body part DL11, the bent connection part DL12) are integral structures extending continuously, that is to say, a data line DL is a structure extending continuously, rather than being arranged in sections .
  • the included angle between the disposition direction of each bending connection portion DL12 and the X direction or the Y direction may be about 45 degrees. It should be understood that the embodiments of the present disclosure are not limited thereto, and the included angle may also adopt other angles, such as 30 degrees, 60 degrees, and the like.
  • the data line DL (ie, the first data line DLA) close to the first spacer 5 is designed to be bent at the position corresponding to the first spacer 5, so that the first spacer 5 can be provided with a bending design.
  • the pad 5 provides enough space for setting or sliding.
  • the spacer 5 is arranged on the first substrate 1 . When the first substrate 1 and the second substrate 2 are assembled, due to the limitation of the accuracy of the assembly, there may be a gap between the first substrate 1 and the second substrate 2 .
  • the cell alignment deviation through the bending design, even if the cell alignment deviation occurs, the spacer 5 can still be prevented from abutting on the data line, so as to ensure that the spacer 5 provides a good supply to the second substrate ground support.
  • a certain relative displacement may be generated between the first substrate 1 and the second substrate 2.
  • the heights of the positions on the second substrate where the data lines, the source electrodes and the drain electrodes of the thin film transistors are disposed are higher than other places, that is, protrusions will be formed at these positions , through the bending design, the spacer can be kept away from the protrusion as far as possible, so that the display panel can be prevented from being thicker at the position of the data line than the box at other positions. In this way, the risk of generating dark state unevenness can be reduced.
  • the size of the spacer 5 can be set relatively large, which increases the contact area between the spacer 5 and the second substrate 2 and can provide a good supporting force for the second substrate 2 . , and reduce the risk of black gap.
  • a bending design is also performed on the data line DL (ie, the second data line DLB) on the left side of the first sub-pixel SP1.
  • the second data line DLB is located on the side of the thin film transistor 6 away from the spacer 5 .
  • the orthographic projection of the second data line DLB on the second substrate 20 is located at a distance from the orthographic projection of the thin film transistor 6 on the second substrate 20 away from the spacer 5 on the second substrate 20 side of the orthographic projection.
  • the distance between the orthographic projection of the second data line DLB on the second substrate 20 and the orthographic projection of the spacer 5 on the second substrate 20 is greater than that of the thin film transistor 6 on the second substrate The distance between the orthographic projection on the bottom 20 and the orthographic projection of the spacer 5 on the second substrate 20 .
  • the distance between the orthographic projection of the second data line DLB on the second substrate 20 and the orthographic projection of the first spacer 5 on the second substrate 20 is greater than that of the first data line
  • the distance between the orthographic projection of the DLA on the second substrate 20 and the orthographic projection of the first spacer 5 on the second substrate 20 is greater than that of the first data line
  • the second data line DLB has a bent portion DL6. That is, the second data line DLB does not extend straight along the Y direction, but has a bent portion DL6 at a position corresponding to the first spacer 5 . Specifically, the projection of the first spacer 5 in the Y direction falls within the projection of the bent portion DL6 in the Y direction. The projection of the first widened portion GL1 in the Y direction and the projection of the bent portion DL6 in the Y direction at least partially overlap. The projection of the second widening portion GL2 in the Y direction and the projection of the bent portion DL6 in the Y direction at least partially overlap.
  • the second data line DLB has a main body portion DL7 and a bent portion DL6.
  • the bent portion DL6 is further away from the first spacer 5, the first widened portion GL1 or the second widened portion GL2 than the main body portion DL7.
  • the orthographic projection of the bent portion DL6 on the second substrate 20 is farther from the first spacer 5 or the orthographic projection of the main body portion DL7 on the second substrate 20
  • An orthographic projection of the first widened portion GL1 on the second substrate 20 That is, in the plan view shown in FIG.
  • the distance along the X direction is greater than the distance between the orthographic projection of the main body portion DL7 on the second substrate 20 and the orthographic projection of the first spacer 5 or the first widening portion GL1 on the second substrate 20 along the distance in the X direction.
  • the bent portion DL6 also has a bent main body portion DL61 and two bent connection portions DL62.
  • the bent main body portion DL61 extends straight in the Y direction.
  • the two bending connection parts DL62 are respectively located at both ends of the bending main body part DL61, one bending connection part DL62 at one end is connected to a section of the main body part DL7, and one bending connection part DL62 at the other end is connected to the other part of the main body part DL7.
  • the data line DL is described with different parts (eg, the main body part DL7, the bent part DL6, the bent main body part DL61, the bent connection part DL62), it should be understood that these parts (eg, the main body part DL7, the bending part DL6, the bending main body part DL61, the bending connection part DL62) are integral structures that extend continuously, that is to say, a data line DL is a structure extending continuously, rather than being arranged in sections .
  • the included angle between the disposition direction of each bending connection portion DL62 and the X direction or the Y direction may be about 45 degrees. It should be understood that the embodiments of the present disclosure are not limited thereto, and the included angle may also adopt other angles, such as 30 degrees, 60 degrees, and the like.
  • the thin film transistor 6 is located between the second data line DLB and the spacer 5 .
  • the orthographic projection of the thin film transistor 6 on the second substrate 20 is located at the second data line DLB on the second substrate 20 .
  • the orthographic projection of the spacer 5 on the second substrate 20 is substantially Invariably, it is beneficial to fabricate data lines and thin film transistors on the second substrate 20 .
  • the thin film transistor 6 is also shifted to the left direction (ie, the direction away from the spacer 5 ) correspondingly at the position corresponding to the spacer 5 .
  • the distance between the thin film transistor 6 and the spacer 5 is increased, thereby increasing the space for the spacer 5 to slide to the left.
  • the data lines located on both sides of the first sub-pixel SP1 are respectively bent in a direction away from the spacer 5 at the position corresponding to the spacer 5 , thereby increasing the spacing The space in which the pad 5 slides toward both sides (eg, left and right in FIG. 3 ). In this way, it is beneficial to reduce or even avoid defects caused by the inaccuracy of the two substrates to the cell or the slippage of the spacer.
  • FIG. 4 schematically shows a plurality of data lines located on both sides of a plurality of columns of sub-pixels.
  • spacers may not be provided in some sub-pixels.
  • spacers 5 are not provided in the second sub-pixel SP2 and the third sub-pixel SP3 .
  • the plurality of data lines may include a third data line DLC adjacent to the first data line DLA.
  • the third data line DLC can also be designed to be bent.
  • the third data line DLC has a main body portion DLC2 and a bent portion DLC1. That is, the third data line DLC does not extend straight along the Y direction, and has a bent portion DLC1 at a position corresponding to the first spacer 5 . Specifically, the projection of the first spacer 5 in the Y direction falls within the projection of the bent portion DLC1 in the Y direction. The projection of the first widened portion GL1 in the Y direction and the projection of the bent portion DLC1 in the Y direction at least partially overlap.
  • the bending direction of the third data line DLC may be the same as the bending direction of the second data line DLB.
  • the bent portion DL6 of the second data line DLB is bent to the left, and the bent portion DLC1 of the third data line DLC is also bent to the left.
  • the bending direction of the third data line DLC may be the same as the bending direction of the first data line DLA. That is, the bent portion DL1 of the first data line DLB is bent to the right, and the bent portion DLC1 of the third data line DLC is also bent to the right.
  • the first sub-pixel SP1 , the second sub-pixel SP2 and the third sub-pixel SP3 are sequentially arranged along the X direction to form a pixel.
  • a plurality of pixels are arranged in an array along the X direction and the Y direction.
  • the data lines on both sides of the first sub-pixel SP1 are the second data line DLB and the first data line DLA
  • the data lines on both sides of the second sub-pixel SP2 are the first data line DLA and the third data line DLC
  • the third sub-pixel The data lines on both sides of SP3 are the third data line DLC and the second data line DLB.
  • the second data line DLB, the first data line DLA and the third data line DLC are sequentially arranged in the X direction. It should be understood that the embodiments of the present disclosure are not limited to such an arrangement of pixels, and accordingly, when the arrangement of pixels is changed, the arrangement of data lines, gate lines, and common electrode lines can also be changed accordingly.
  • FIGS. 11A and 11B are partial plan views, respectively, of a display panel according to some exemplary embodiments of the present disclosure, in which rows of sub-pixels and data lines extending in the rows of sub-pixels are schematically shown. It should be noted that some specific structures of gate lines, common electrode lines, pixel electrodes, thin film transistors and other components are omitted in FIGS. 11A and 11B to emphasize the structure of data lines arranged along the Y direction.
  • each spacer 5 may be located in the same position of the first data line DLA
  • each spacer 5 may be located in the first sub-pixel, that is, located on the left side of the first data line DLA.
  • the bent portions DL1 of the first data lines DLA are all bent in a direction away from the spacers 5 (right direction in the figure). That is, a plurality of bending portions are provided on the same data line, and the bending directions of the plurality of bending portions are the same.
  • a plurality of spacers 5 are provided, and the plurality of spacers 5 may be located at different positions of the first data line DLA
  • a part of the spacer 5 may be located in the first sub-pixel, that is, to the left of the first data line DLA
  • another part of the spacer may be located in the second sub-pixel, that is, to the right of the first data line DLA side.
  • the bending directions of the plurality of bending parts DL1 of the first data line DLA are different, for example, some bending parts are bent toward the left direction, and other bending parts Bend to the right. That is, a plurality of bending portions are provided on the same data line, and the bending directions of the plurality of bending portions are different.
  • the data lines on both sides of the sub-pixels provided with the spacers have bent portions, and one data line may have a plurality of bent portions. Due to the plurality of bent portions, the lengths of the data lines on both sides of the sub-pixels provided with the spacers are increased. In the embodiment of the present disclosure, the same bending design is also performed on the data lines on both sides of the sub-pixels that are not provided with the spacers, even if they also have a plurality of bending parts, so that each The lengths of the data lines are all basically the same.
  • projections of the first widened portion GL1 and the second widened portion GL2 of the first gate line GL in the Y direction at least partially overlap each other.
  • the orthographic projection of the first spacer 5 on the second substrate 20 falls within the orthographic projection of the first widening portion GL1 on the second substrate 20
  • the orthographic projection of the first spacer 5 on the second substrate 20 is
  • the area of the orthographic projection is smaller than the area of the orthographic projection of the first widening portion GL1 on the second substrate 20 .
  • the orthographic projection of the active layer ACT of the thin film transistor 6 on the second substrate 20 falls within the orthographic projection of the second widening portion GL2 on the second substrate 20, and the active layer ACT of the thin film transistor 6 is on the second substrate 20.
  • the area of the orthographic projection on the bottom 20 is smaller than the area of the orthographic projection of the second widening portion GL2 on the second substrate 20 .
  • the first electrode 6S of the thin film transistor 6 has a first portion 6S1 and a second portion 6S2, and the first portion 6S1 is in direct contact with the data line DL (specifically, the second data line DLB), or in other words, the first portion 6S1 Extending directly from the second data line DLB in the X direction, the orthographic projection of the first portion 6S1 on the second substrate 20 at least partially overlaps the orthographic projection of the second data line DLB on the second substrate 20 .
  • the orthographic projection of the second portion 6S2 on the second substrate 20 at least partially overlaps the orthographic projection of the second widening GL2 on the second substrate 20 , eg, the projection of the second portion 6S2 on the second substrate 20
  • the orthographic projection falls within the orthographic projection of the second widening portion GL2 on the second substrate 20 .
  • the width (eg, the dimension in the Y direction) of the first portion 6S1 is greater than the width (eg, the dimension in the X direction) of the second portion 6S2.
  • the first electrode 6S of the thin film transistor 6 may further include a third portion 6S3.
  • the third portion 6S3 is disposed obliquely with respect to both the X direction and the Y direction, and the third portion 6S3 is disposed between the first portion 6S1 and the second portion 6S2 for connecting the first portion 6S1 and the second portion 6S2.
  • the second electrode 6D of the thin film transistor 6 has a first part 6D1 and a second part 6D2, the first part 6D1 partially overlaps with the pixel electrode 7, or in other words, the orthographic projection of the first part 6D1 on the second substrate 20 is in the pixel electrode 7.
  • the orthographic projections on the second substrate 20 at least partially overlap. In this way, the first portion 6D1 can be in electrical contact with the pixel electrode 7 through the via hole VH1.
  • the orthographic projection of the second portion 6D2 on the second substrate 20 at least partially overlaps the orthographic projection of the second widening GL2 on the second substrate 20 , eg, the projection of the second portion 6D2 on the second substrate 20
  • the orthographic projection falls within the orthographic projection of the second widening portion GL2 on the second substrate 20 .
  • the width (eg, dimension along the X direction) of the first portion 6D1 is greater than the width (eg, dimension along the X direction) of the second portion 6D2.
  • This arrangement can make the electrical contact area of the second electrode 6D and the pixel electrode larger, which is beneficial to improve the electrical contact capability of the two, and at the same time, the overlapping area of the second electrode 6D and the gate electrode 6G can be made as small as possible.
  • the second electrode 6D of the thin film transistor 6 may further include a third portion 6D3, and the third portion 6D3 may directly extend from the first portion 6D1 toward the pixel electrode 7, that is, the orthographic projection of the third portion 6D3 on the second substrate 20 is the same as that of the pixel.
  • the orthographic projections of the electrodes 7 on the second substrate 20 at least partially overlap.
  • the width of the third portion 6D3 (eg, the dimension in the X-direction) is greater than the width (eg, the dimension in the X-direction) of the first portion 6D1 .
  • the second portion 6S2 of the first electrode 6S is substantially parallel to the second portion 6D2 of the second electrode 6D, and they are arranged substantially in the Y direction.
  • the projections of the second portion 6S2 of the first electrode 6S and the second portion 6D2 of the second electrode 6D in the Y direction substantially coincide.
  • the second portion 6D2 of the second electrode 6D is closer to the first widened portion GL1 than the second portion 6S2 of the first electrode 6S.
  • the orthographic projection of the first spacer 5 on the second substrate 20 and the orthographic projection of the bent portion DL1 of the first data line DLA on the second substrate 20 along the X direction The distance may be referred to as the first distance d1, along the X direction between the orthographic projection of the first spacer 5 on the second substrate 20 and the orthographic projection of the second portion 6D2 of the second electrode 6D on the second substrate 20
  • the distance can be referred to as the second distance d2.
  • the orthographic projection of the first spacer 5 on the second substrate 20 may have a shape such as a regular polygon or a circle, and the regular polygon or circle may have a center 50, and the bent portion DL1 of the first data line DLA Having an edge portion DL3 close to the first spacer 5 , the second portion 6D2 of the second electrode 6D has an edge portion 6D21 close to the first spacer 5 .
  • the first distance d1 can be represented by the distance from the center 50 to the edge portion DL3 along the X direction, or can be represented by the distance between the first spacer 5 and the bent portion DL1 along the X direction.
  • the second distance d2 can be represented by the distance from the center 50 to the edge portion 6D21 along the X direction, or can be represented by the distance between the first spacer 5 and the second portion 6D2 along the X direction. Interval distance representation.
  • the first distance d1 may be substantially equal to the second distance d2. That is, the spacer 5 has substantially equal slip distances toward the left and toward the right in the X-direction.
  • each of the bent connection parts DL12 of the first data line DLA may have an edge part DL13 close to the spacer 5 .
  • the distance from the center 50 to the edge portion DL13 may be represented by a third distance d3.
  • the third distance d3 may be substantially equal to the first distance d1.
  • the first distance d1 , the second distance d2 and the third distance d3 may be greater than 10 micrometers, for example, within a range of 10 to 50 micrometers.
  • the projection of the pad 5 is located between the data line and the thin film transistor.
  • the projection of the first data line DLA (eg, its main body portion DL2 and the bending connection portion DL12 ) in the X direction and the projection of the first widening portion GL1 in the X direction are at least Partially overlapping.
  • the embodiments of the present disclosure are not limited thereto.
  • the projection of the first data line DLA (eg, its main body portion DL2 and the bending connection portion DL12 ) in the X direction is the same as the projection of the first widening portion GL1 in the X direction
  • the projections can be non-overlapping, that is, they can be set at intervals.
  • the first widened portion GL1 of the gate line GL protrudes toward the common electrode line CL with respect to other portions of the gate line GL (eg, the second widened portion GL2 ).
  • the common electrode line CL has a bent portion CL1.
  • the projection of the bent portion CL1 in the X direction at least partially overlaps with the projection of the first widened portion GL1 in the X direction, for example, the projection of the bent portion CL1 in the X direction is substantially the same as the projection of the first widened portion GL1 in the X direction coincide.
  • the common electrode line CL has a main body portion CL2 and a bent portion CL1.
  • the bent portion CL1 is further away from the first widened portion GL1 than the main body portion CL2.
  • the distance in the direction is greater than the distance in the Y direction between the orthographic projection of the main body portion CL2 on the second substrate 20 and the orthographic projection of the first widening portion GL1 on the second substrate 20 .
  • the bent portion CL1 also has a bent main body portion CL11 and two bent connection portions CL12.
  • the main body portion CL2 and the bent main body portion CL11 extend straight in the X direction.
  • the two bending connection parts CL12 are respectively located at both ends of the bending main body part CL11, one bending connection part CL12 at one end is connected to a section of the main body part CL2, and one bending connection part CL12 at the other end is connected to the other part of the main body part CL2. a paragraph.
  • the common electrode line CL is described with different parts (eg, the main body part CL2 , the bent part CL1 , the bent main body part CL11 , the bent connection part CL12 ), it should be understood that these parts (For example, the main body portion CL2, the bent portion CL1, the bent main body portion CL11, and the bent connection portion CL12) are a continuously extending integral structure, that is, a common electrode line CL is a continuously extending structure, not a segmented structure set.
  • the distance between the common electrode line CL and the first widened portion GL1 can be substantially equal to the distance between the common electrode line CL and the second widened portion GL2, avoiding the common electrode
  • the gap between the line CL and the first widened portion GL1 is too small.
  • the gate line GL has an inclined portion GL3 whose orthographic projection on the second substrate 20 at least partially overlaps with the orthographic projection of the data line DL on the second substrate 20 .
  • the orthographic projection of the inclined portion GL3 on the second substrate 20 at least partially overlaps with the orthographic projection of the bent portion DL1 of the data line DL on the second substrate 20 .
  • the gate lines GL are substantially disposed along the X direction.
  • the included angle may be in the range of 10-50 degrees.
  • the data line DL is located above the gate line GL, that is, the data line DL needs to climb across the gate line GL.
  • the gate line GL is described in different parts (eg, the first widened part GL1 , the second widened part GL2 and the inclined part GL3 ) herein, it should be understood that these parts (eg, the first widened part GL2 , and the inclined part GL3 )
  • the widened portion GL1 , the second widened portion GL2 and the inclined portion GL3 ) are a continuously extending integral structure, that is, one gate line GL is a continuously extending structure instead of being arranged in sections.
  • the second substrate 2 may include a first electrode layer 201 , a first conductive layer (where the gate line GL, the gate electrode 6G and the common electrode line CL are located on the second substrate 20 in sequence) layer), the gate insulating layer 202, the active layer ACT, the interlayer dielectric layer 207, the second conductive layer (the layer where the first electrode 6S, the second electrode 6D, the data line DL, etc. are located), the passivation layer 204 and The second electrode layer 205 .
  • the first electrode layer 201 and the second electrode layer 205 may be ITO electrode layers.
  • the common electrode 8 may be located on the first electrode layer 201 , and the pixel electrode 7 may be located on the second electrode layer 205 .
  • the common electrode 8 may be electrically connected to the common electrode line CL, and the pixel electrode 7 may be electrically connected to the second electrode 6D of the thin film transistor 6 .
  • the second substrate 2 may further include a planarization layer 208 disposed on the side of the passivation layer 204 away from the second substrate 20 .
  • two protruding structures are formed on both sides of the spacer 5 along the X direction, namely the first protruding structure 21 and the second protruding structure 22 shown in FIG. 7 .
  • the orthographic projection of the first raised structure 21 on the second substrate 20 at least partially overlaps with the orthographic projection of the first data line DLA on the second substrate 20
  • the second raised structure 22 is on the second substrate 20
  • the orthographic projection of at least partially overlaps with the orthographic projection of the thin film transistor 6 on the second substrate 20 .
  • Disposing the first data line DLA and the source and drain electrodes of the thin film transistor 6 on the second substrate 20 causes the heights at corresponding positions on the second substrate 20 to be higher than those at other positions, thereby forming two protrusions Build structures 21 and 22.
  • the "protruding structure” included in the second substrate refers to a structure as follows: a protruding structure formed by a plurality of stacked film layers that is higher than an adjacent portion, specifically, the protruding structure
  • the distance from the upper surface of the alignment film 4 (that is, the surface away from the second substrate 20 ) from the upper surface of the second substrate 20 is greater than that of the upper surface of the alignment film 4 at other locations (eg, the light-transmitting area TA ) (that is, away from the second substrate). 20) from the upper surface of the second substrate 20.
  • the first protruding structure 21 and the second protruding structure 22 can stop the spacer 5 and limit the movement range of the spacer 5 in the X direction within the range defined by the two protruding structures .
  • each of the third protruding structure 23 and the fourth protruding structure 24 includes a structure higher than an adjacent portion formed by a plurality of stacked film layers.
  • the orthographic projection of the third raised structure 23 on the second substrate 20 at least partially overlaps with the orthographic projection of the common electrode line CL on the second substrate 20 .
  • the orthographic projection on the substrate 20 at least partially overlaps the orthographic projection of the bent portion CL1 of the common electrode line CL on the second substrate 20 .
  • the third protrusion structure 23 further includes a first protrusion 231 in the second conductive layer.
  • the orthographic projection of the first boss 231 on the second substrate 20 falls within the orthographic projection of the bent portion CL1 of the common electrode line CL on the second substrate 20 .
  • the bent portion CL1 of the common electrode line CL is widened.
  • the size (ie, the width) of the bent main portion CL11 of the bent portion CL1 of the common electrode line CL in the X direction is larger than the size (ie, the width) of the main portion CL2 of the common electrode line CL in the X direction.
  • the orthographic projection of the third raised structure 23 on the second substrate 20 at least partially overlaps the orthographic projection of the pixel electrode 7 or the common electrode 8 on the second substrate 20 .
  • the pixel electrode 7 or the common electrode 8 is the pixel electrode or the common electrode of the sub-pixel adjacent to the sub-pixel provided with the spacer 5 along the column Y direction.
  • the third protruding structure 23 is formed by using the bent portion CL1 of the common electrode line CL and disposing a separate first boss 231 in the second conductive layer.
  • the fourth protrusion structure 24 includes a second protrusion 241 and a third protrusion 242, the second protrusion 241 is located on the first conductive layer, and the third protrusion 242 is located on the second conductive layer.
  • the orthographic projection of the third boss 242 on the second substrate 20 falls within the orthographic projection of the second boss 241 on the second substrate 20 .
  • the orthographic projection of the fourth raised structure 24 on the second substrate 20 at least partially overlaps the orthographic projection of the pixel electrode 7 or the common electrode 8 on the second substrate 20 .
  • the pixel electrode 7 or the common electrode 8 here is the pixel electrode or the common electrode of the sub-pixel provided with the spacer 5 .
  • the third protruding structure 23 and the fourth protruding structure 24 are respectively located on both sides of the spacer 5 or the first widening portion GL1 along the Y direction.
  • the orthographic projection of the third protruding structure 23 on the second substrate 20 and the orthographic projection of the fourth protruding structure 24 on the second substrate 20 are located on the spacer 5 or the first widening along the Y direction, respectively.
  • the portion GL1 is on both sides of the orthographic projection on the second substrate 20 . In this way, the third protruding structure 23 and the fourth protruding structure 24 can stop the spacer 5 and limit the movement range of the spacer 5 in the Y direction within the range defined by the two protruding structures .
  • the third protruding structure 23 has an edge portion 235 close to the spacer 5
  • the third protruding structure 24 has an edge portion 245 close to the spacer 5
  • the distance along the Y direction between the orthographic projection of the spacer 5 on the second substrate 20 and the orthographic projection of the third raised structure 23 on the second substrate 20 may be referred to as a fourth distance d4.
  • the spacer 5 The distance along the Y direction between the orthographic projection of the fourth raised structure 24 on the second substrate 20 and the orthographic projection of the fourth raised structure 24 on the second substrate 20 may be referred to as a fifth distance d5.
  • the fourth distance d4 may be represented by the distance from the center 50 to the edge portion 235 in the Y direction
  • the fifth distance d5 may be represented by the distance from the center 50 to the edge portion 245 in the Y direction Express.
  • the fourth distance d4 may be substantially equal to the fifth distance d5. That is, the spacer 5 has substantially equal slip distances toward the upper side and toward the lower side in the Y direction.
  • the fourth distance d4 may be greater than or equal to the first distance d1.
  • the spacer 5 has sufficient sliding space, and can prevent the spacer 5 from sliding into the light-transmitting area, and can prevent the spacer from scratching the alignment film located in the light-transmitting area.
  • the spacer 5 is only provided in the first sub-pixel SP1, and the spacer 5 is not provided in the second sub-pixel SP2 and the third sub-pixel SP3.
  • the portion of the gate line GL located in the second sub-pixel SP2 does not have the first widened portion GL1 but only has the second widened portion GL2, and accordingly, the common electrode line CL is located in the second sub-pixel
  • the portion in SP2 also does not have the widened portion CL1.
  • the portion of the gate line GL located in the third sub-pixel SP3 does not have the first widened portion GL1, but only has the second widened portion GL2.
  • the portion of the common electrode line CL located in the third sub-pixel SP3 also has There is no widened portion CL1.
  • the first sub-pixel SP1 is a red sub-pixel
  • the second sub-pixel SP2 is a green sub-pixel
  • the third sub-pixel SP3 is a blue sub-pixel.
  • the spacer 5 is arranged in the red sub-pixel SP1, so that it can be avoided that the setting of the spacer 5 has an influence on the display color temperature and the display color.
  • the embodiment of the present disclosure is not limited thereto, and the spacer 5 may be disposed in at least one of the first subpixel SP1 , the second subpixel SP2 and the third subpixel SP3 .
  • the pixel electrode 7 may be a slit electrode, that is, the pixel electrode 7 has a plurality of slits 71 .
  • the common electrode 8 may be a planar electrode, and the common electrode line CL may be electrically connected to the common electrode 8 .
  • the orthographic projection of the pixel electrode 7 on the second substrate 20 at least partially overlaps the orthographic projection of the common electrode 8 on the second substrate 20 .
  • the display panel according to some exemplary embodiments of the present disclosure can be applied to liquid crystal display devices of AD-SDS (Advanced-Super Dimensional Switching, ADS for short) type, IPS type and the like.
  • ADS Advanced-Super Dimensional Switching
  • a multi-dimensional electric field is formed by the parallel electric field generated at the edge of the pixel electrode in the same plane and the longitudinal electric field generated between the pixel electrode layer and the common electrode layer. All of the liquid crystal molecules can produce rotational conversion, thereby improving the working efficiency of the plane alignment system liquid crystal and increasing the light transmission efficiency.
  • the electrodes located in the first electrode layer may be pixel electrodes, and the electrodes located in the second electrode layer may be common electrodes .
  • the orthographic projections of each of the spacers 5 , the gate lines GL, the data lines DL, the common electrode lines CL and the thin film transistors 6 on the second substrate 20 fall into the black matrix 12 on the second substrate 20 in the orthographic projection on. That is to say, they are all arranged within the coverage area of the black matrix 12, that is, they are all located in the opaque area.
  • FIG. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 12 , the display device includes the display panel provided according to any of the above embodiments. Therefore, the display device also has technical effects corresponding to the beneficial effects of the display panel included in the display device, and details can be referred to the above description.
  • the display device may be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a smart phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

提供一种显示面板和显示装置。该显示面板包括相对设置的第一基板和第二基板。第一基板包括多个隔垫物。第二基板包括：第二衬底；设置在第二衬底上的多条栅线和多条数据线，栅线沿行方向设置，数据线沿列方向设置；和多个子像素，多条栅线和多条数据线包围形成多个子像素，每一个子像素包括透光区。隔垫物在第二衬底上的正投影邻近子像素的透光区在第二衬底上的正投影，隔垫物在第二衬底上的正投影与数据线在第二衬底上的正投影间隔设置；数据线具有主体部和弯折部，弯折部在第二衬底上的正投影相对于主体部在第二衬底上的正投影朝远离隔垫物在第二衬底上的正投影的方向弯折。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，并且具体地涉及一种显示面板和包括该显示面板的显示装置。
背景技术
液晶显示器包括液晶显示面板，液晶显示面板包括对盒设置的阵列基板和对盒基板、以及位于阵列基板和对盒基板之间的液晶层，阵列基板和对盒基板通过封框胶密封。在液晶显示面板的液晶盒内，为保持保证液晶盒的盒厚(英文表述为Cell Gap)在各个位置的均一性，通常在阵列基板和对盒基板之间设置有具有弹性回复力的隔垫物(简称为PS)。隔垫物处于压缩状态并起到支撑液晶盒的作用，从而保持液晶显示面板的盒厚稳定与均一。随着显示技术的不断发展，显示装置的分辨率不断提高，相应地，每一个像素的尺寸不断减小，这样，如何在小尺寸的像素中设置隔垫物，逐渐成为研发人员关注的课题。
在本部分中公开的以上信息仅用于对本公开的发明构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示面板，包括：
第一基板，所述第一基板包括：
第一衬底；和
设置在所述第一衬底上的多个隔垫物；和
与所述第一基板相对设置的第二基板，所述第二基板包括：
第二衬底；
设置在所述第二衬底上的多条栅线和多条数据线，每一条所述栅线沿行方向设置，每一条所述数据线沿列方向设置；和
沿所述行方向和所述列方向成阵列地布置在所述第二衬底上的多个子像素， 所述多条栅线和所述多条数据线包围形成所述多个子像素，每一个子像素均包括透光区，
其中，所述多个隔垫物包括至少一个第一隔垫物，所述多条数据线至少包括第一数据线，所述多个子像素包括第一子像素，所述第一数据线邻近所述第一子像素设置；
所述第一隔垫物在所述第二衬底上的正投影邻近所述第一子像素的透光区在所述第二衬底上的正投影，所述第一隔垫物在所述第二衬底上的正投影与所述第一数据线在所述第二衬底上的正投影间隔设置；
所述第一数据线具有主体部和弯折部，所述弯折部在所述列方向的投影与所述第一隔垫物在所述列方向的投影至少部分交叠，所述弯折部在所述第二衬底上的正投影相对于所述主体部在所述第二衬底上的正投影朝远离所述第一隔垫物在所述第二衬底上的正投影的方向弯折。
根据一些示例性的实施例，所述弯折部包括弯折主体部和两个弯折连接部，所述弯折主体部和所述第一数据线的主体部的设置方向彼此平行，所述弯折主体部的一端通过一个弯折连接部连接至所述第一数据线的主体部的一段，所述弯折主体部的另一端通过另一个弯折连接部连接至所述第一数据线的主体部的另一段。
根据一些示例性的实施例，所述多条数据线还包括第二数据线，所述第二数据线邻近所述第一子像素设置；所述第一数据线在所述第二衬底上的正投影和所述第二数据线在所述第二衬底上的正投影在所述行方向上分别位于所述第一隔垫物在所述第二衬底上的正投影的两侧，所述第二数据线在所述第二衬底上的正投影与所述第一隔垫物在所述第二衬底上的正投影之间沿所述行方向的距离大于所述第一数据线在所述第二衬底上的正投影与所述第一隔垫物在所述第二衬底上的正投影之间沿所述行方向的距离。
根据一些示例性的实施例，所述第二数据线具有主体部和弯折部，所述第二数据线的弯折部在所述列方向的投影与所述第一隔垫物在所述列方向的投影至少部分交叠，所述第二数据线的弯折部在所述第二衬底上的正投影相对于所述第二数据线的主体部在所述第二衬底上的正投影朝远离所述第一隔垫物在所述第二衬底上的正投影的方向弯折。
根据一些示例性的实施例，所述第二数据线的弯折部包括弯折主体部和两个弯折连接部，所述第二数据线的弯折主体部和所述第二数据线的主体部的设置方向彼此平 行，所述第二数据线的弯折主体部的一端通过一个第二数据线的弯折连接部连接至所述第二数据线的主体部的一段，所述第二数据线的弯折主体部的另一端通过第二数据线的另一个弯折连接部连接至所述第二数据线的主体部的另一段。
根据一些示例性的实施例，所述多条栅线包括邻近所述第一子像素设置的第一栅线，所述第一隔垫物在所述第二衬底上的正投影落入所述第一栅线在所述第二衬底上的正投影内。
根据一些示例性的实施例，所述第一栅线包括第一加宽部和第二加宽部，所述第一加宽部和所述第二加宽部在所述第二衬底上的正投影位于所述第一数据线在所述第二衬底上的正投影与所述第二数据线在所述第二衬底上的正投影之间；所述第一加宽部和所述第二加宽部中的每一个沿所述列方向的尺寸大于所述第一栅线的其它部分沿所述列方向的尺寸，所述第一隔垫物在所述第二衬底上的正投影落入所述第一栅线的第一加宽部在所述第二衬底上的正投影内。
根据一些示例性的实施例，所述第二基板还包括设置在所述第二衬底上的多个薄膜晶体管，所述多个薄膜晶体管包括邻近所述第一子像素设置的至少一个第一薄膜晶体管；所述第一薄膜晶体管在所述第二衬底上的正投影落入所述第一栅线的第二加宽部在所述第二衬底上的正投影内。
根据一些示例性的实施例，所述第一薄膜晶体管在所述第二衬底上的正投影位于所述第一隔垫物在所述第二衬底上的正投影与所述第二数据线的弯折部在所述第二衬底上的正投影之间。
根据一些示例性的实施例，所述第一栅线还包括多个倾斜部，每一个倾斜部在所述第二衬底上的正投影的设置方向与所述行方向成锐角的夹角；所述第一数据线的弯折部在所述第二衬底上的正投影与所述第一栅线的一个倾斜部在所述第二衬底上的正投影至少部分交叠，所述第二数据线的弯折部在所述第二衬底上的正投影与所述第一栅线的另一个倾斜部在所述第二衬底上的正投影至少部分交叠。
根据一些示例性的实施例，所述多个子像素还包括与所述第一子像素相邻的第二子像素，所述多条数据线还包括第三数据线，所述第一数据线和所述第三数据线分别位于所述第二子像素两侧；所述第三数据线包括弯折部，所述第三数据线的弯折部在所述列方向的投影与所述第一数据线的弯折部和所述第二数据线的弯折部中的每一个在所述列方向的投影至少部分交叠，所述第三数据线的弯折部的弯折方向与所述第一 数据线的弯折部和所述第二数据线的弯折部中的一个的弯折方向相同。
根据一些示例性的实施例，所述第二基板还包括设置在所述第二衬底上的多条公共电极线，每一条所述公共电极线沿所述行方向设置；所述多条公共电极线包括第一公共电极线，所述第一公共电极线在所述第二衬底上的正投影与所述第一栅线在所述第二衬底上的正投影相邻，所述第一公共电极线具有主体部和弯折部，所述第一公共电极线的弯折部在所述行方向的投影与所述第一加宽部在所述行方向的投影至少部分交叠，所述第一公共电极线的弯折部在所述第二衬底上的正投影相对于所述第一公共电极线的主体部在所述第二衬底上的正投影朝远离所述第一加宽部在所述第二衬底上的正投影的方向弯折。
根据一些示例性的实施例，所述第一加宽部相对于所述第二加宽部和所述倾斜部中的每一个朝向所述第一公共电极线突出。
根据一些示例性的实施例，所述第一加宽部与所述第一公共电极线的弯折部之间沿所述列方向的间隔距离等于所述第二加宽部与所述第一公共电极线的主体部之间沿所述列方向的间隔距离。
根据一些示例性的实施例，所述第一公共电极线的弯折部沿所述列方向的尺寸大于所述第一公共电极线的主体部沿所述列方向的尺寸。
根据一些示例性的实施例，所述第一薄膜晶体管包括有源层、栅极、第一电极和第二电极，所述第二基板还包括设置在所述第二衬底上的像素电极；所述第一电极与所述第二数据线电连接，所述第二电极与所述像素电极电连接；所述第一电极具有第一部分和第二部分，所述第一电极的第一部分直接自所述第二数据线沿所述行方向延伸，所述第一电极的第二部分在所述第二衬底上的正投影落入所述第二加宽部在所述第二衬底上的正投影内；所述第二电极具有第一部分和第二部分，所述第二电极的第一部分在所述第二衬底上的正投影与所述像素电极在所述第二衬底上的正投影至少部分交叠，所述第二电极的第二部分在所述第二衬底上的正投影落入所述第二加宽部在所述第二衬底上的正投影内；所述第一电极的第一部分沿所述列方向的尺寸大于所述第一电极的第二部分沿所述行方向的尺寸，所述第二电极的第一部分沿所述行方向的尺寸大于所述第二电极的第二部分沿所述行方向的尺寸。
根据一些示例性的实施例，所述第一电极的第二部分与所述第二电极的第二部分平行，所述第二电极的第二部分比所述第一电极的第二部分更靠近所述第一加宽部。
根据一些示例性的实施例，所述第一隔垫物在所述第二衬底上的正投影与所述第一数据线的弯折部在所述第二衬底上的正投影之间沿所述行方向间隔第一距离，所述第一隔垫物在所述第二衬底上的正投影与所述第二电极的第二部分在所述第二衬底上的正投影之间沿所述行方向间隔第二距离，所述第一距离等于所述第二距离。
根据一些示例性的实施例，所述第一距离大于等于10微米。
根据一些示例性的实施例，所述第二基板包括位于所述第二衬底上的第一凸起结构和第二凸起结构，所述第一凸起结构和所述第二凸起结构沿所述行方向位于所述第一隔垫物的两侧；所述第一凸起结构在所述第二衬底上的正投影与所述第一数据线的弯折部在所述第二衬底上的正投影至少部分交叠，所述第二凸起结构在所述第二衬底上的正投影与所述第一薄膜晶体管在所述第二衬底上的正投影至少部分交叠。
根据一些示例性的实施例，所述第二基板还包括位于所述第二衬底上的第三凸起结构和第四凸起结构，所述第三凸起结构和所述第四凸起结构沿所述列方向位于所述第一隔垫物的两侧；所述第三凸起结构在所述第二衬底上的正投影与所述第一公共电极线的弯折部在所述第二衬底上的正投影至少部分交叠，所述第四凸起结构在所述第二衬底上的正投影与所述第一子像素的像素电极在所述第二衬底上的正投影至少部分交叠。
根据一些示例性的实施例，所述第二基板包括设置在所述第二衬底上的第一导电层和第二导电层，所述第二导电层设置在所述第一导电层远离所述第二衬底的一侧；所述栅线和所述公共电极线位于所述第一导电层，所述数据线以及所述薄膜晶体管的第一电极和第二电极位于所述第二导电层。
根据一些示例性的实施例，所述第三凸起结构包括位于所述第二导电层中的第一凸台，所述第一凸台在所述第二衬底上的正投影落入所述第一公共电极线的弯折部在所述第二衬底上的正投影内。
根据一些示例性的实施例，所述第四凸起结构包括第二凸台和第三凸台，所述第二凸台位于所述第一导电层，所述第三凸台位于所述第二导电层，所述第三凸台在所述第二衬底上的正投影落入所述第二凸台在所述第二衬底上的正投影内。
根据一些示例性的实施例，所述第一隔垫物和所述第一加宽部中的每一个在所述第二衬底上的正投影具有八边形形状，所述第一隔垫物在所述第二衬底上的正投影的面积小于所述第一加宽部在所述第二衬底上的正投影的面积。
根据一些示例性的实施例，所述第一数据线、所述第二数据线和所述第三数据线中的每一个都包括多个弯折部；同一条数据线包括的多个弯折部的弯折方向彼此相同，或者，同一条数据线包括的多个弯折部中的至少两个弯折部的弯折方向彼此不同。
根据一些示例性的实施例，所述第一基板还包括设置在所述第一衬底上的黑矩阵，所述栅线、所述数据线、所述公共电极线和所述薄膜晶体管中的每一个在所述第一衬底上的正投影落入所述黑矩阵在所述第一衬底上的正投影内。
根据一些示例性的实施例，所述第一子像素为红色子像素。
根据一些示例性的实施例，所述第二基板包括设置在所述第二衬底上的第一电极层和第二电极层，所述第二电极层设置在所述第一电极层远离所述第二衬底的一侧；所述第二基板还包括设置在所述第二衬底上的公共电极，所述像素电极设置在所述第一电极层和第二电极层中的一个中，所述公共电极设置在所述第一电极层和第二电极层中的另一个中。
在又一方面，提供一种显示装置，包括如上所述的显示面板。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加明显。
图1为根据本公开的一些示例性实施例的显示面板的剖面示意图；
图2是示意性示出根据本公开实施例的显示面板上的隔垫物的分布的平面示意图；
图3是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了位于同一列的两个相邻子像素之间的平面结构；
图4是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了多列子像素；
图5是图3中的显示面板包括的第一导电层的平面图；
图6是图3中的显示面板包括的第二导电层的平面图；
图7是沿图3中的线AA’截取的截面图；
图8是沿图3中的线BB’截取的截面图；
图9是沿图3中的线CC’截取的截面图；
图10是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了位于第一基板上的黑矩阵与位于第二基板上的膜层结构的相对位置关系；
图11A和图11B分别是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了多行子像素以及在多行子像素中延伸的数据线；以及
图12是根据本公开的一些示例性实施例的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到 这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
本领域技术人员应该理解，在本文中，除非另有说明，表述“高度”或“厚度”指的是沿垂直于显示面板(例如彩膜基板或阵列基板)设置有各个膜层的表面的尺寸，即沿显示面板的出光方向的尺寸，或沿附图中Z方向的尺寸。
在本文中，除非另有说明，“位于同一层”、“设置在同一层”或“同层设置”等类似表述表示所指的多个层、元件、部件、结构或器件由相同的材料构成，并且它们通过同一构图工艺形成。
在本文中，表述“在行方向的投影”、“在X方向的投影”等类似表述方式，表示如下意思：在行方向和列方向形成的平面内，即在XY平面内，平面的层、元件、部件、结构或器件投影到行方向或X方向上形成的投影；如果从三维结构考虑，该表述表示的是：立体的层、元件、部件、结构或器件投影到与列方向垂直的平面或与Y方向垂直的平面内的投影。类似地，表述“在列方向的投影”、“在Y方向的投影”等类似表述方式，表示如下意思：在列方向和列方向形成的平面内，即在XY平面内，平面的层、元件、部件、结构或器件投影到列方向或Y方向上形成的投影；如果从三维结构考虑，该表述表示的是：立体的层、元件、部件、结构或器件投影到与行方向垂直的平面或与X方向垂直的平面内的投影。
本公开实施例提供一种显示面板和显示装置。所述显示面板可以包括：第一基板，所述第一基板包括：第一衬底；和设置在所述第一衬底上的多个隔垫物；和与所述第一基板相对设置的第二基板，所述第二基板包括：第二衬底；设置在所述第二衬底上的多条栅线和多条数据线，每一条所述栅线沿行方向设置，每一条所述数据线沿列方向设置；和沿所述行方向和所述列方向成阵列地布置在所述第二衬底上的多个子像素， 所述多条栅线和所述多条数据线包围形成所述多个子像素，每一个子像素均包括透光区，其中，所述多个隔垫物包括至少一个第一隔垫物，所述多条数据线至少包括第一数据线，所述多个子像素包括第一子像素，所述第一数据线邻近所述第一子像素设置；所述第一隔垫物在所述第二衬底上的正投影邻近所述第一子像素的透光区在所述第二衬底上的正投影，所述第一隔垫物在所述第二衬底上的正投影与所述第一数据线在所述第二衬底上的正投影间隔设置；所述第一数据线具有主体部和弯折部，所述弯折部在所述列方向的投影与所述第一隔垫物在所述列方向的投影至少部分交叠，所述弯折部在所述第二衬底上的正投影相对于所述主体部在所述第二衬底上的正投影朝远离所述第一隔垫物在所述第二衬底上的正投影的方向弯折。在本公开的实施例中，靠近隔垫物的数据线在对应第一隔垫物的位置处进行了弯折设计，从而能够给隔垫物提供足够的设置空间或滑移空间。
图1为一种根据本公开的一些示例性实施例的显示面板的剖面示意图。例如，该显示面板可以是液晶显示面板。如图1所示，该液晶显示面板包括第一基板1、与第一基板1对盒设置的第二基板2以及设置在第一基板1和第二基板2之间的液晶分子层3。该液晶显示面板至少还包括设置在第二基板2面向第一基板1的一侧的取向膜4以及设置在第一基板1或第二基板2上的隔垫物5。应该理解，在第一基板1面向第二基板2的一侧也设置有取向膜。例如，如图1所示，隔垫物5可设置在第一基板1上。取向膜4可诱导液晶分子层3中的液晶分子进行定向排列；例如，可通过摩擦工艺在取向膜4的表面形成定向沟道，从而诱导液晶分子层3中的液晶分子进行定向排列。当该液晶显示面板显示暗态时，液晶分子层3中的液晶分子不发生偏转，光无法透过液晶显示面板。当液晶显示面板显示亮态时，液晶分子层3中的液晶分子在电场的作用下发生偏转，光可以透过液晶显示面板。并且，该液晶显示面板还可通过设置在第一基板或第二基板上的彩色滤光图案的作用，使得该液晶显示面板显示具有与该彩色滤光图案对应颜色的光。
需要说明的是，所述隔垫物在液晶显示面板中起着保持保证液晶盒的盒厚(Cell Gap)在各个位置的均一性的作用，从而保持液晶显示面板的盒厚稳定与均一。
还需要说明的是，第一基板1上设置有黑矩阵12和彩膜层，隔垫物5在第一基板1上的正投影落入黑矩阵12在第一基板1上的正投影内。也就是说，一方面，隔垫物5的尺寸不能设置得过小。例如，当隔垫物5在第一基板1上的正投影为圆形时，此 处的尺寸可以指所述圆形的直径；当隔垫物5在第一基板1上的正投影为矩形时，此处的尺寸可以指所述矩形的长和宽。这样，可以确保隔垫物5的支撑面积足够大，有利于提供足够的支撑力。另一方面，由于隔垫物5需要落入黑矩阵12的范围内，所以，隔垫物也在某种程度上也制约着液晶显示面板的开口率。也就是说，隔垫物5的尺寸不能设置得太大，否则会降低显示面板的开口率。示例性地，在分辨率为8K的显示面板中，隔垫物5在第一基板1上的正投影可以具有圆形形状，并且隔垫物5的直径在15～30微米的范围内，例如为约20微米。
在下面的附图中，为了清楚地示出显示面板包括的各个膜层的相对位置关系，上述取向膜、彩膜层和黑矩阵可能被省略，但是，这并不能理解为对本公开实施例的限制。
图2是示意性示出根据本公开实施例的显示面板上的隔垫物的分布的平面示意图。
结合参照图1和图2，所述多个隔垫物5可以包括多个主隔垫物(英文表述可以为Main PS)51和多个副隔垫物(英文表述可以为Sub PS)52。需要说明的是，在图2的平面示意图中，隔垫物5(包括主隔垫物51和剐隔垫物52)用“六边形”表示，这并不意味着对主隔垫物和副隔垫物的形状的限制，主、副隔垫物可以采用本领域中已知的隔垫物的各种形状，在此不再赘述。例如，隔垫物5在图2的平面示意图中的形状可以为圆形、椭圆形、矩形、圆角矩形等形状。
例如，主隔垫物51的高度大于副隔垫物52的高度。例如，副隔垫物52的高度可以是主隔垫物51高度的70％～95％。在第一基板1和第二基板2正常对盒的状态下，起支撑作用的是主隔垫物51，当显示面板受到较大的外力挤压作用时，副隔垫物52也可以起到支撑作用，以提高耐压力，并且，在挤压消除时，可以由主隔垫物和副隔垫物提供回复力。通过设置高度不同的主隔垫物和副隔垫物，可以提高隔垫物的支撑能力，并且防止各种Mura或者不良的发生。
图3是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了位于同一列的两个相邻子像素之间的平面结构。图4是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了多列子像素。需要说明的是，在图3和图4的平面图中，为了清楚地示出位于第一基板上的隔垫物与位于第二基板上的膜层结构的相对位置关系，省略了第一基板上形成的一些膜层结构(例如黑矩阵)。 图5是图3中的显示面板包括的第一导电层的平面图。图6是图3中的显示面板包括的第二导电层的平面图。图7是沿图3中的线AA’截取的截面图。图8是沿图3中的线BB’截取的截面图。图9是沿图3中的线CC’截取的截面图。图10是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了位于第一基板上的黑矩阵与位于第二基板上的膜层结构的相对位置关系。
参照图2、图3和图4，所述显示面板可以包括多个子像素SP，多个子像素SP成阵列地布置，即，多个子像素SP沿行方向(图中的X方向)和列方向(图中的Y方向)布置。多个子像素SP可以至少包括第一子像素SP1、第二子像素SP2和第三子像素SP3，例如，第一子像素、第二子像素和第三子像素可以分别为红色子像素、绿色子像素和蓝色子像素。例如，第一子像素、第二子像素和第三子像素可以组成一个像素。例如，在8K分辨率的显示面板中，设置有7680*4320个像素。但是，本公开的实施例不局限于此，第一子像素、第二子像素和第三子像素可以是其他颜色的子像素。
多个隔垫物5分别设置在多个子像素SP中。例如，每一个子像素SP中设置有至多一个隔垫物5(主隔垫物51和副隔垫物52中的一个)。
例如，所述显示面板包括多个主隔垫物51和多个副隔垫物52。主隔垫物51的数量可以小于副隔垫物52的数量。例如，在图2所示的示例中，示出了8行24列(即192个)子像素SP，其中，设置有64个隔垫物5，具体地设置有4个主隔垫物51，60个副隔垫物52。通过这样的设置，可以确保隔垫物对液晶盒的支撑效果较佳。
需要说明的是，在图2的实施例中，并不是每一个子像素中设置有一个隔垫物，而是部分子像素中设置有所述隔垫物，但是，本公开的实施例不限于此，在其它实施例中，根据分布密度的实际需要，也可以在一个子像素中设置多个隔垫物，或者，也可以在每一个子像素中均设置一个隔垫物。再例如，在一些示例性的实施例中，在每一个主隔垫物51所在的子像素邻近的一个子像素中不设置任何隔垫物。
还需要说明的是，根据本公开实施例的显示面板特别适用于ADS(ADvanced Super Dimension Switch，高级超维场转换技术)模式，本文中描述的实施例也以ADS模式显示面板为例进行说明。但是，本公开的实施例并不限于此，它还可以适用于各种其他模式的显示装置，例如TN(Twisted Nematic，扭曲向列)模式、VA(Vertical Alignment，垂直取向)模式等模式。另外，所述显示面板可以是触控显示面板。
可选地，第一基板1可以是彩膜基板，第二基板2可以是阵列基板。
结合参照图3至图10，第一基板1可以包括第一衬底10和设置于第一衬底10上的黑矩阵12。各个隔垫物5(主隔垫物51和副隔垫物52中的每一个)位于第一衬底10上，且它们在第一衬底10上的正投影均落入黑矩阵12在第一衬底10上的正投影内。
第二基板2可以包括第二衬底20、设置于第二衬底20上的栅线GL、公共电极线CL和数据线DL。栅线GL和公共电极线CL沿行X方向设置，数据线DL沿列Y方向设置。栅线GL和数据线DL交叉限定出多个子像素SP。每一个子像素SP包括透光区TA，光可以从该透光区TA射出所述显示面板，从而实现显示功能。应该理解，各个子像素SP的透光区TA在第二衬底20上的正投影与所述黑矩阵12在第二衬底20上的正投影不交叠。各个隔垫物5、包括栅线GL、公共电极线CL和数据线DL的各种数据线、以及用于驱动各个子像素的各种薄膜晶体管在第二衬底20上的正投影均落入所述黑矩阵12在第二衬底20上的正投影内。
参照图3和图4，示意性示出了位于2个相邻行的像素以及这2行相邻的像素之间的不透光区的部分平面结构，其中，图3仅示出了一列子像素。为了方便描述，所述2行相邻的像素可以分别称为第一行像素(图4中位于上侧的一行像素)P1和第二行像素(图4中位于下侧的一行像素)P2。示例性地，每一行像素可以分别包括沿行X方向排列的多个像素，每一个像素可以包括沿行X方向依次排列的第一子像素SP1、第二子像素SP2和第三子像素SP3。例如，第一子像素SP1、第二子像素SP2和第三子像素SP3可以分别为红色子像素、绿色子像素和蓝色子像素。同样地，第一子像素SP1、第二子像素SP2和第三子像素SP3中的每一个都包括一个透光区TA。
在第一行像素P1与第二行像素P2之间的不透光区(即被黑矩阵12遮挡的区域)中，一条栅线GL和一条公共电极线CL均沿行X方向设置，并且栅线GL和公共电极线CL沿列Y方向间隔设置。所述栅线GL用于给第一行像素P1中的各个子像素SP供给栅极扫描信号。所述公共电极线CL电连接第一行子像素和第二行子像素中的各个子像素的公共电极。例如，公共电极线CL可以包括朝向第一行子像素延伸的多个部分，该多个部分在第二衬底上的正投影可以与第一行子像素中的各个子像素的公共电极在第二衬底上的正投影至少部分交叠，这样，所述多个部分可以通过过孔与第一行子像素中的各个子像素的公共电极电连接。
在图3中，在第一子像素SP1的沿X方向的两侧，分别设置有数据线DL。在本 文中，为了描述方便，将位于第一子像素SP1右侧的数据线称为第一数据线DLA，将位于第一子像素SP1左侧的数据线称为第二数据线DLB。在第一子像素SP1的沿Y方向的下侧，依次设置有栅线GL和公共电极线CL，为了描述方便，将给第一子像素SP1供给栅极扫描信号的栅线GL称为第一栅线GL，将与第一栅线GL相邻设置的公共电极线称为第一公共电极线CL。应该理解，这仅是出于方便描述的目的，而不应该理解为对数据线、栅线和公共电极线的限制。第一数据线DLA和第二数据线DLB除了在弯折设计处(下文将详细描述)的结构略有区别外，在其他位置处的结构均可以相同。
参照图3，示意性示出了位于第一行像素P1与第二行像素P2之间的不透光区中的一个隔垫物5。需要说明的是，该隔垫物5可以是主隔垫物51，也可以是副隔垫物52。也可以说，在图3的实施例中，隔垫物5设置在第一子像素SP1中。在本文中，表述“隔垫物设置在子像素中”或“隔垫物所在的子像素”表示的意思是：该隔垫物在衬底上的正投影与该子像素在该衬底上的正投影交叠或落入该子像素在该衬底上的正投影内，或者说，该隔垫物在衬底上的正投影和与该子像素的透光区相邻的非透光区在该衬底上的正投影至少部分交叠。更具体地，隔垫物5设置在第一行像素P1中的一个第一子像素SP1中，意味着隔垫物5设置在第一行像素P1中的第一子像素SP1的靠近第二行像素P2的边缘位置处，或者说，隔垫物5在衬底上的正投影与第一子像素SP1的非透光区在衬底上的正投影至少部分交叠。
继续参照图3，第一栅线GL可以包括第一加宽部GL1和第二加宽部GL2。在平行于数据线DL的设置方向的方向(即图中的Y方向)上，第一加宽部GL1的尺寸和第二加宽部GL2的尺寸较大，大于第一栅线GL的除第一加宽部GL1和第二加宽部GL2之外的部分的尺寸。例如，第一加宽部GL1在第二衬底20上的正投影可以具有近似多边形(例如八边形或正八边形)的形状，第二加宽部GL2在第二衬底20上的正投影可以具有近似矩形(例如圆角矩形)的形状。应该理解，这些形状不是对本公开的实施例的限制，第一加宽部GL1和第二加宽部GL2还可以具有其他合适的形状。
再例如，隔垫物5在第二衬底20上的正投影可以具有近似多边形(例如八边形或正八边形)的形状。应该理解，这些形状不是对本公开的实施例的限制，隔垫物5还可以具有其他合适的形状。
需要说明的是，所述隔垫物包括面向第一衬底的上表面和远离第一衬底的下表面， 所述隔垫物的上表面的面积可以大于下表面的面积，即，所述隔垫物的截面呈梯形形状。在本文中，所述隔垫物在第一衬底或第二衬底上的正投影可以指所述隔垫物的上表面(即具有较大面积的表面)在第一衬底或第二衬底上的正投影。
在本公开的实施例中，一个隔垫物5(在本文中，为了描述方便，可以称为第一隔垫物)在第二衬底20上的正投影落入第一栅线GL在第二衬底20上的正投影内。具体地，第一隔垫物5在第二衬底20上的正投影落入第一栅线GL的第一加宽部GL1在第二衬底20上的正投影内。通过这样的设置方式，可以保证所述隔垫物支撑在所述栅线对应的位置处，避免其划伤取向膜。另外，可以使得所述隔垫物与邻近的各个子像素的透光区域的距离尽量最大化，避免其划伤取向膜。
第二基板2还可以包括设置于第二衬底20上的薄膜晶体管6。薄膜晶体管6可以包括有源层ACT、栅极6G、第一电极6S(例如源极和漏极中的一个)和第二电极6D(例如源极和漏极中的另一个)。在本文中，为了描述方便，也可以将薄膜晶体管6称为第一晶体管。
薄膜晶体管6在第二衬底20上的正投影与第一栅线GL在第二衬底20上的正投影至少部分交叠。例如，薄膜晶体管6在第二衬底20上的正投影与第一栅线GL的第二加宽部GL2在第二衬底20上的正投影至少部分交叠。示例性地，第一栅线GL的一部分形成薄膜晶体管6的栅极6G。第一栅线GL的一部分在第二衬底20上的正投影与薄膜晶体管6的有源层ACT在第二衬底20上的正投影重合，例如，第一栅线GL的第二加宽部GL2的一部分在第二衬底20上的正投影与薄膜晶体管6的有源层ACT在第二衬底20上的正投影重合。这样，栅线GL的该部分形成薄膜晶体管6的栅极6G。
在本文中，为了描述方便，将栅线GL所在的层称为第一导电层，将数据线DL所在的层称为第二导电层。应该理解，所述第一导电层和所述第二导电层是不同的层。例如，所述第二导电层设置于所述第一导电层远离所述第二衬底20的一侧。公共电极线CL可以位于所述第一导电层。薄膜晶体管的第一电极6S和第二电极6D可以位于所述第二导电层。
薄膜晶体管6的第一电极6S可以电连接至左侧的数据线DL(即第二数据线DLB)，第二电极6D可以电连接至像素电极7(下文将详细描述)。
通过这样的连接方式，可以在第一栅线GL供应的栅极扫描信号的控制下，将数据线DL(例如第二数据线)供应的数据信号传输给像素电极7，从而产生用于控制液 晶分子的电场。
继续参照图3，在X方向上，第一隔垫物5在第二衬底20上的正投影位于薄膜晶体管6在第二衬底20上的正投影与位于右侧的数据线DL在第二衬底20上的正投影之间。即，第一加宽部GL1在第二衬底20上的正投影位于第二加宽部GL2在第二衬底20上的正投影与位于右侧的数据线DL在第二衬底20上的正投影之间。
位于右侧的数据线DL(即第一数据线DLA)具有弯折部DL1。即，第一数据线DLA不是沿Y方向笔直延伸的，在与隔垫物5对应的位置处具有一弯折部DL1。具体地，隔垫物5在Y方向的投影落入弯折部DL1在Y方向的投影内。第一加宽部GL1在Y方向的投影与弯折部DL1在Y方向的投影至少部分交叠。
具体地，第一数据线DLA具有主体部DL2和弯折部DL1。在X方向上，弯折部DL1相对于主体部DL2更远离第一隔垫物5或第一加宽部GL1。换句话说，在图3所示的平面图中，弯折部DL1在第二衬底20上的正投影比主体部DL2在第二衬底20上的正投影更远离第一隔垫物5或第一加宽部GL1在第二衬底20上的正投影。即在图3所示的平面图中，弯折部DL1在第二衬底20上的正投影与第一隔垫物5或第一加宽部GL1在第二衬底20上的正投影之间沿所述X方向的距离大于主体部DL2在第二衬底20上的正投影与第一隔垫物5或第一加宽部GL1在第二衬底20上的正投影之间沿所述X方向的距离。
更具体地，弯折部DL1还具有弯折主体部DL11和2个弯折连接部DL12。弯折主体部DL11沿Y方向笔直延伸。2个弯折连接部DL12分别位于弯折主体部DL11的两端，位于一端的一个弯折连接部DL12连接主体部DL2的一段，位于另一端的一个弯折连接部DL12连接主体部DL2的另一段。
需要说明的是，虽然在本文中以不同的部分(例如主体部DL2、弯折部DL1、弯折主体部DL11、弯折连接部DL12)来描述数据线DL，但是，应该理解，这些部分(例如主体部DL2、弯折部DL1、弯折主体部DL11、弯折连接部DL12)是连续延伸的一体结构，也就是说，一根数据线DL是连续延伸的结构，而不是分段设置的。
例如，每一个弯折连接部DL12的设置方向与X方向或Y方向的夹角可以为约45度。应该理解，本公开的实施例不局限于此，所述夹角也可以采用其他的角度，例如30度、60度等。
在本公开的实施例中，靠近第一隔垫物5的数据线DL(即第一数据线DLA)在 对应第一隔垫物5的位置处进行了弯折设计，从而能够给第一隔垫物5提供足够的设置空间或滑移空间。具体地，隔垫物5设置在第一基板1上，当第一基板1与第二基板2对盒时，受限于对盒精度，第一基板1与第二基板2之间可能会产生对盒偏差，通过所述弯折设计，在即使产生所述对盒偏差的情况下，仍可以避免隔垫物5抵靠在数据线上，从而能够确保隔垫物5对第二基板提供良好地支撑。另外，在按压显示面板时，可能导致第一基板1与第二基板2之间产生一定的相对位移，通过所述弯折设计，给隔垫物5提供足够的滑移空间，可以避免隔垫物5触碰数据线。
还需要说明的是，在本公开的实施例中，第二基板上设置有所述数据线、薄膜晶体管的源极和漏极等位置的高度比其他地方高，即在这些位置会形成凸起，通过所述弯折设计，可以使得隔垫物尽量远离所述凸起，从而可以避免显示面板在数据线的位置处比其他位置的盒厚大。这样，可以减小产生暗态不均的风险。而且，由于数据线进行了弯折设计，所以，隔垫物5的尺寸可以设置得相对大，提高隔垫物5与第二基板2的接触面积，能够给第二基板2提供良好的支撑力，并且降低出现黑Gap的风险。
结合参照图3和图4，在第一子像素SP1左侧的数据线DL(即第二数据线DLB)上也进行弯折设计。第二数据线DLB位于薄膜晶体管6远离隔垫物5的一侧。具体地，在X方向上，第二数据线DLB在第二衬底20上的正投影位于薄膜晶体管6在第二衬底20上的正投影远离隔垫物5在第二衬底20上的正投影的一侧。或者说，在X方向上，第二数据线DLB在第二衬底20上的正投影与隔垫物5在第二衬底20上的正投影之间的距离大于薄膜晶体管6在第二衬底20上的正投影与隔垫物5在第二衬底20上的正投影之间的距离。
可选地，在X方向上，第二数据线DLB在第二衬底20上的正投影与第一隔垫物5在第二衬底20上的正投影之间的距离大于第一数据线DLA在第二衬底20上的正投影与第一隔垫物5在第二衬底20上的正投影之间的距离。
第二数据线DLB具有弯折部DL6。即，第二数据线DLB不是沿Y方向笔直延伸的，在与第一隔垫物5对应的位置处具有一弯折部DL6。具体地，第一隔垫物5在Y方向的投影落入弯折部DL6在Y方向的投影内。第一加宽部GL1在Y方向的投影与弯折部DL6在Y方向的投影至少部分交叠。第二加宽部GL2在Y方向的投影与弯折部DL6在Y方向的投影至少部分交叠。
具体地，第二数据线DLB具有主体部DL7和弯折部DL6。在X方向上，弯折部 DL6相对于主体部DL7更远离第一隔垫物5、第一加宽部GL1或第二加宽部GL2。换句话说，在图3所示的平面图中，弯折部DL6在第二衬底20上的正投影比主体部DL7在第二衬底20上的正投影更远离第一隔垫物5或第一加宽部GL1在第二衬底20上的正投影。即在图3所示的平面图中，弯折部DL6在第二衬底20上的正投影与第一隔垫物5或第一加宽部GL1在第二衬底20上的正投影之间沿所述X方向的距离大于主体部DL7在第二衬底20上的正投影与第一隔垫物5或第一加宽部GL1在第二衬底20上的正投影之间沿所述X方向的距离。
更具体地，弯折部DL6还具有弯折主体部DL61和2个弯折连接部DL62。弯折主体部DL61沿Y方向笔直延伸。2个弯折连接部DL62分别位于弯折主体部DL61的两端，位于一端的一个弯折连接部DL62连接主体部DL7的一段，位于另一端的一个弯折连接部DL62连接主体部DL7的另一段。
需要说明的是，虽然在本文中以不同的部分(例如主体部DL7、弯折部DL6、弯折主体部DL61、弯折连接部DL62)来描述数据线DL，但是，应该理解，这些部分(例如主体部DL7、弯折部DL6、弯折主体部DL61、弯折连接部DL62)是连续延伸的一体结构，也就是说，一根数据线DL是连续延伸的结构，而不是分段设置的。
例如，每一个弯折连接部DL62的设置方向与X方向或Y方向的夹角可以为约45度。应该理解，本公开的实施例不局限于此，所述夹角也可以采用其他的角度，例如30度、60度等。
如图3所示。薄膜晶体管6位于第二数据线DLB与隔垫物5之间，具体地，在X方向上，薄膜晶体管6在第二衬底20上的正投影位于第二数据线DLB在第二衬底20上的正投影与隔垫物5在第二衬底20上的正投影之间。第二数据线DLB在对应隔垫物5的位置处向左侧方向(即远离隔垫物5的方向)进行弯折，而第二数据线DLB与薄膜晶体管6沿X方向的距离基本上是不变的，这样有利于在第二衬底20上制作数据线和薄膜晶体管。所以，薄膜晶体管6在对应隔垫物5的位置处也相应地向左侧方向(即远离隔垫物5的方向)进行了偏移。结果，薄膜晶体管6与隔垫物5之间的距离得以增大，从而增大了隔垫物5朝左侧滑移的空间。
也就是说，在本公开的实施例中，位于第一子像素SP1两侧的数据线在对应隔垫物5的位置处分别朝向远离隔垫物5的方向上弯折，从而增大了隔垫物5朝向两侧(例如图3中的左侧和右侧)滑移的空间。这样，有利于减小、甚至避免由于两个基板对 盒不准或隔垫物滑移导致的不良。
图4示意性示出了位于多列子像素两侧的多条数据线。在本公开的一些实施例中，一些子像素中可以不设置隔垫物，例如，在图4所示的实施例中，第二子像素SP2和第三子像素SP3中没有设置隔垫物5。所述多条数据线可以包括与第一数据线DLA相邻的第三数据线DLC。第三数据线DLC也可以进行弯折设计。
具体地，第三数据线DLC具有主体部DLC2和弯折部DLC1。即，第三数据线DLC不是沿Y方向笔直延伸的，在与第一隔垫物5对应的位置处具有一弯折部DLC1。具体地，第一隔垫物5在Y方向的投影落入弯折部DLC1在Y方向的投影内。第一加宽部GL1在Y方向的投影与弯折部DLC1在Y方向的投影至少部分交叠。
可选地，第三数据线DLC的弯折方向可以与第二数据线DLB的弯折方向相同。如图4所示，第二数据线DLB的弯折部DL6朝左侧弯折，第三数据线DLC的弯折部DLC1也朝左侧弯折。
可选地，第三数据线DLC的弯折方向可以与第一数据线DLA的弯折方向相同。即，第一数据线DLB的弯折部DL1朝右侧弯折，第三数据线DLC的弯折部DLC1也均右侧弯折。
在图4所示的实施例中，第一子像素SP1、第二子像素SP2和第三子像素SP3沿X方向依次排列，以组成一个像素。多个像素沿X方向和Y方向成阵列地排列。第一子像素SP1两侧的数据线为第二数据线DLB和第一数据线DLA，第二子像素SP2两侧的数据线为第一数据线DLA和第三数据线DLC，第三子像素SP3两侧的数据线为第三数据线DLC和第二数据线DLB。即，第二数据线DLB、第一数据线DLA和第三数据线DLC沿X方向依次排列。应该理解，本公开的实施例不局限于这样的像素排列方式，相应地，当像素排列方式改变时，数据线、栅线和公共电极线等排列方式也可以相应地改变。
图11A和图11B分别是根据本公开的一些示例性实施例的显示面板的局部平面图，其中示意性示出了多行子像素以及在多行子像素中延伸的数据线。需要说明的是，图11A和图11B省略了栅线、公共电极线、像素电极、薄膜晶体管等部件的一些具体结构，以重点突出数据线沿Y方向设置的结构。
参照图11A，在相邻两列子像素(例如一列第一子像素和一列第二子像素)中，设置有多个隔垫物5，每一个隔垫物5可以位于第一数据线DLA的同一侧，例如，每 一个隔垫物5可以均位于第一子像素中，即均位于第一数据线DLA的左侧。这样，在对应每一个隔垫物5的位置处，第一数据线DLA的弯折部DL1均朝向远离隔垫物5的方向(图中为右侧方向)弯折。即，同一条数据线上设置有多个弯折部，并且所述多个弯折部的弯折方向相同。
参照图11B，在相邻两列子像素(例如一列第一子像素和一列第二子像素)中，设置有多个隔垫物5，多个隔垫物5可以位于第一数据线DLA的不同侧，例如，一部分隔垫物5可以位于第一子像素中，即位于第一数据线DLA的左侧，另一部分隔垫物可以位于第二子像素中，即位于第一数据线DLA的右侧。这样，在对应每一个隔垫物5的位置处，第一数据线DLA的多个弯折部DL1的弯折方向不同，例如，一部分弯折部朝向左侧方向弯折，另一部分弯折部朝向右侧方向弯折。即，同一条数据线上设置有多个弯折部，并且所述多个弯折部的弯折方向不相同。
在设置有隔垫物的子像素两侧的数据线具有弯折部，并且一根数据线可以具有多个弯折部。由于多个弯折部，所以设置有隔垫物的子像素两侧的数据线的长度会增加。在本公开的实施例中，在未设置有所述隔垫物的子像素两侧的数据线上也进行相同的弯折设计，即使得它们也具有多个弯折部，可以使得每一根数据线的长度都基本相同。这样，可以避免由于数据线的弯折设计而导致的数据线长度不一致的情况，有利于提高各根数据线的均一性，避免由于数据线上的电阻不同而导致的其上传输的信号不一致的情况。
返回参照图3和图4，第一栅线GL的第一加宽部GL1和第二加宽部GL2在Y方向的投影彼此至少部分交叠。第一隔垫物5在第二衬底20上的正投影落入第一加宽部GL1在第二衬底20上的正投影内，第一隔垫物5在第二衬底20上的正投影的面积小于第一加宽部GL1在第二衬底20上的正投影的面积。通过设置第一加宽部GL1，有利于使得第一隔垫物5的投影落入栅线GL的投影内。薄膜晶体管6的有源层ACT在第二衬底20上的正投影落入第二加宽部GL2在第二衬底20上的正投影内，薄膜晶体管6的有源层ACT在第二衬底20上的正投影的面积小于第二加宽部GL2在第二衬底20上的正投影的面积。通过设置第二加宽部GL2，有利于薄膜晶体管6的栅极覆盖有源层ACT。
参照图5和图6，薄膜晶体管6的第一电极6S具有第一部分6S1和第二部分6S2，第一部分6S1与数据线DL(具体为第二数据线DLB)直接接触，或者说，第一部分 6S1直接自第二数据线DLB沿X方向延伸，第一部分6S1在第二衬底20上的正投影与第二数据线DLB在第二衬底20上的正投影至少部分交叠。第二部分6S2在第二衬底20上的正投影与第二加宽部GL2在第二衬底20上的正投影至少部分交叠，例如，第二部分6S2在第二衬底20上的正投影落入第二加宽部GL2在第二衬底20上的正投影内。
例如，第一部分6S1的宽度(例如沿Y方向的尺寸)大于第二部分6S2的宽度(例如沿X方向的尺寸)。通过这样的设置，可以使得第一电极6S与数据线的接触面积较大，有利于提高二者的电接触能力，同时可以使得第一电极6S与栅极6G的交叠面积尽量小。
薄膜晶体管6的第一电极6S还可以包括第三部分6S3。第三部分6S3相对于X方向和Y方向均倾斜设置，第三部分6S3设置在第一部分6S1和第二部分6S2之间，用于连接第一部分6S1和第二部分6S2。
薄膜晶体管6的第二电极6D具有第一部分6D1和第二部分6D2，第一部分6D1与像素电极7部分交叠，或者说，第一部分6D1在第二衬底20上的正投影与像素电极7在第二衬底20上的正投影至少部分交叠。这样，第一部分6D1可以通过过孔VH1与像素电极7电接触。第二部分6D2在第二衬底20上的正投影与第二加宽部GL2在第二衬底20上的正投影至少部分交叠，例如，第二部分6D2在第二衬底20上的正投影落入第二加宽部GL2在第二衬底20上的正投影内。
例如，第一部分6D1的宽度(例如沿X方向的尺寸)大于第二部分6D2的宽度(例如沿X方向的尺寸)。通过这样的设置，可以使得第二电极6D与像素电极的电接触面积较大，有利于提高二者的电接触能力，同时可以使得第二电极6D与栅极6G的交叠面积尽量小。
薄膜晶体管6的第二电极6D还可以包括第三部分6D3，第三部分6D3可以直接自第一部分6D1朝向像素电极7延伸，即，第三部分6D3在第二衬底20上的正投影与像素电极7在第二衬底20上的正投影至少部分交叠。第三部分6D3的宽度(例如沿X方向的尺寸)大于第一部分6D1的宽度(例如沿X方向的尺寸)。
例如，第一电极6S的第二部分6S2与第二电极6D的第二部分6D2基本平行，它们基本沿Y方向设置。第一电极6S的第二部分6S2与第二电极6D的第二部分6D2在Y方向的投影基本重合。第二电极6D的第二部分6D2比第一电极6S的第二部分 6S2更靠近第一加宽部GL1。
参照图3至图6，第一隔垫物5在第二衬底20上的正投影与第一数据线DLA的弯折部DL1在第二衬底20上的正投影之间沿X方向的距离可以称为第一距离d1，第一隔垫物5在第二衬底20上的正投影与第二电极6D的第二部分6D2在第二衬底20上的正投影之间沿X方向的距离可以称为第二距离d2。例如，第一隔垫物5在第二衬底20上的正投影可以具有正多边形或圆形等形状，所述正多边形或圆形可以具有中心50，第一数据线DLA的弯折部DL1具有靠近第一隔垫物5的边缘部DL3，第二电极6D的第二部分6D2具有靠近第一隔垫物5的边缘部6D21。所述第一距离d1可以用所述中心50至所述边缘部DL3沿X方向的距离表示，或者，可以用所述第一隔垫物5与所述弯折部DL1之间沿X方向的间隔距离表示。所述第二距离d2可以用所述中心50至所述边缘部6D21沿X方向的距离表示，或者，可以用所述第一隔垫物5与所述第二部分6D2之间沿X方向的间隔距离表示。
可选地，所述第一距离d1可以基本等于第二距离d2。即，隔垫物5在X方向上朝向左侧和朝向右侧具有基本相等的滑移距离。
例如，第一数据线DLA的每一个弯折连接部DL12可以具有靠近隔垫物5的边缘部DL13。所述中心50至所述边缘部DL13之间的距离可以用第三距离d3表示。可选地，所述第三距离d3可以基本等于所述第一距离d1。
在一个示例性的实施例中，所述第一距离d1、第二距离d2和第三距离d3可以在10微米以上，例如在10～50微米范围内取值。发明人通过研究发现，第一基板和第二基板的对盒偏差通常在8微米以内，通过将所述第一距离d1、第二距离d2和第三距离d3可以在10微米以上，可以确保隔垫物5的投影位于数据线与薄膜晶体管之间。
需要说明的是，在图3的实施例中，第一数据线DLA(例如它的主体部DL2和弯折连接部DL12)在X方向的投影与第一加宽部GL1在X方向的投影至少部分交叠。本公开的实施例不局限于此，在其他实施例中，第一数据线DLA(例如它的主体部DL2和弯折连接部DL12)在X方向的投影与第一加宽部GL1在X方向的投影可以不交叠，即可以间隔设置。
参照图3和图4，栅线GL的第一加宽部GL1相对于栅线GL的其他部分(例如第二加宽部GL2)朝向公共电极线CL突出。公共电极线CL具有弯折部CL1。弯折部CL1在X方向的投影与第一加宽部GL1在X方向的投影至少部分交叠，例如，弯 折部CL1在X方向的投影与第一加宽部GL1在X方向的投影基本重合。
具体地，公共电极线CL具有主体部CL2和弯折部CL1。在Y方向上，弯折部CL1相对于主体部CL2更远离第一加宽部GL1。换句话说，在图3所示的平面图中，弯折部CL1在第二衬底20上的正投影与第一加宽部GL1在第二衬底20上的正投影之间沿所述Y方向的距离大于主体部CL2在第二衬底20上的正投影与第一加宽部GL1在第二衬底20上的正投影之间沿所述Y方向的距离。
更具体地，弯折部CL1还具有弯折主体部CL11和2个弯折连接部CL12。主体部CL2和弯折主体部CL11沿X方向笔直延伸。2个弯折连接部CL12分别位于弯折主体部CL11的两端，位于一端的一个弯折连接部CL12连接主体部CL2的一段，位于另一端的一个弯折连接部CL12连接主体部CL2的另一段。
需要说明的是，虽然在本文中以不同的部分(例如主体部CL2、弯折部CL1、弯折主体部CL11、弯折连接部CL12)来描述公共电极线CL，但是，应该理解，这些部分(例如主体部CL2、弯折部CL1、弯折主体部CL11、弯折连接部CL12)是连续延伸的一体结构，也就是说，一根公共电极线CL是连续延伸的结构，而不是分段设置的。
通过在公共电极线CL上设置弯折部，可以使得公共电极线CL与第一加宽部GL1之间的距离基本等于公共电极线CL与第二加宽部GL2之间的距离，避免公共电极线CL与第一加宽部GL1之间的间隙过小。
参照图3和图4，栅线GL具有倾斜部GL3，倾斜部GL3在第二衬底20上的正投影与数据线DL在第二衬底20上的正投影至少部分交叠。具体地，倾斜部GL3在第二衬底20上的正投影与数据线DL的弯折部DL1在第二衬底20上的正投影至少部分交叠。
结合参照图3、图4和图8，栅线GL基本沿X方向设置。在倾斜部GL3处，倾斜部GL3与X方向之间具有一定的夹角，例如，所述夹角可以在10～50度的范围内。在数据线DL与栅线GL交叠的位置处，数据线DL位于栅线GL上方，即，数据线DL需要爬升跨过栅线GL。通过设置所述倾斜部GL3，可以增大数据线DL的爬升长度，从而可以减小数据线DL在爬升栅线时断线的风险。
需要说明的是，虽然在本文中以不同的部分(例如第一加宽部GL1、第二加宽部GL2和倾斜部GL3)来描述栅线GL，但是，应该理解，这些部分(例如第一加宽部 GL1、第二加宽部GL2和倾斜部GL3)是连续延伸的一体结构，也就是说，一根栅线GL是连续延伸的结构，而不是分段设置的。
进一步地，参照图7至图9，第二基板2可以包括依次设置在第二衬底20上的第一电极层201、第一导电层(栅线GL、栅极6G和公共电极线CL所在的层)、栅绝缘层202、有源层ACT、层间介电层207、第二导电层(第一电极6S、第二电极6D、数据线DL等所在的层)、钝化层204和第二电极层205。第一电极层201和第二电极层205可以是ITO电极层。例如，公共电极8可以位于第一电极层201，像素电极7可以位于第二电极层205。公共电极8可以与公共电极线CL电连接，像素电极7可以与薄膜晶体管6的第二电极6D电连接。
可选地，第二基板2还可以包括设置在钝化层204远离第二衬底20一侧的平坦化层208。
结合参照图3和图7，在隔垫物5沿X方向的两侧，形成有两个凸起结构，即图7中所示的第一凸起结构21和第二凸起结构22。第一凸起结构21在第二衬底20上的正投影与第一数据线DLA在第二衬底20上的正投影至少部分交叠，第二凸起结构22在第二衬底20上的正投影与薄膜晶体管6在第二衬底20上的正投影至少部分交叠。在第二衬底20上设置第一数据线DLA和薄膜晶体管6的源极和漏极，导致第二衬底20上对应位置处的高度比其他位置处的高度高，从而形成了两个凸起结构21和22。
需要说明的是，在本文中，第二基板包括的“凸起结构”表示如下的一种结构：由多个堆叠膜层形成的高于邻近部分的凸起结构，具体地，该凸起结构的上表面(即远离第二衬底20的表面)距离第二衬底20的上表面的距离大于其他位置处(例如透光区TA)的取向膜4的上表面(即远离第二衬底20的表面)距离第二衬底20的上表面的距离。
通过这样的方式，第一凸起结构21和第二凸起结构22可以对隔垫物5起止挡作用，将隔垫物5在X方向的移动范围限制在两个凸起结构限定的范围内。
结合参照图3和图9，在隔垫物5沿Y方向的两侧，也形成有两个凸起结构，即图9中所示的第三凸起结构23和第四凸起结构24。同样地，第三凸起结构23和第四凸起结构24中的每一个包括由多个堆叠膜层形成的高于邻近部分的结构。
例如，第三凸起结构23在第二衬底20上的正投影与公共电极线CL在第二衬底20上的正投影至少部分交叠，具体地，第三凸起结构23在第二衬底20上的正投影与 公共电极线CL的弯折部CL1在第二衬底20上的正投影至少部分交叠。而且，第三凸起结构23还包括位于所述第二导电层中的第一凸台231。第一凸台231在第二衬底20上的正投影落入公共电极线CL的弯折部CL1在第二衬底20上的正投影内。为了承载所述第一凸台231，公共电极线CL的弯折部CL1得以加宽。具体地，公共电极线CL的弯折部CL1的弯折主体部CL11沿X方向的尺寸(即宽度)大于公共电极线CL的主体部CL2沿X方向的尺寸(即宽度)。
第三凸起结构23在第二衬底20上的正投影与像素电极7或公共电极8在第二衬底20上的正投影至少部分交叠。该像素电极7或公共电极8为沿列Y方向与设置有隔垫物5的子像素相邻的子像素的像素电极或公共电极。
由此可见，利用公共电极线CL的弯折部CL1，并设置单独的位于所述第二导电层中的第一凸台231，来形成第三凸起结构23。
再例如，第四凸起结构24包括第二凸台241和第三凸台242，第二凸台241位于所述第一导电层，所述第三凸台242位于所述第二导电层。第三凸台242在第二衬底20上的正投影落入第二凸台241在第二衬底20上的正投影内。通过增加位于第一导电层的第二凸台241和位于第二导电层的第三凸台242，可以增加相应位置处的高度，从而形成所述第四凸起结构24。
第四凸起结构24在第二衬底20上的正投影与像素电极7或公共电极8在第二衬底20上的正投影至少部分交叠。此处的像素电极7或公共电极8为设置有隔垫物5的子像素的像素电极或公共电极。
第三凸起结构23和第四凸起结构24沿Y方向分别位于隔垫物5或第一加宽部GL1的两侧。具体地，第三凸起结构23在第二衬底20上的正投影和第四凸起结构24在第二衬底20上的正投影沿Y方向分别位于隔垫物5或第一加宽部GL1在第二衬底20上的正投影的两侧。通过这样的方式，第三凸起结构23和第四凸起结构24可以对隔垫物5起止挡作用，将隔垫物5在Y方向的移动范围限制在两个凸起结构限定的范围内。
第三凸起结构23具有靠近所述隔垫物5的边缘部235，第三凸起结构24具有靠近所述隔垫物5的边缘部245。隔垫物5在第二衬底20上的正投影与第三凸起结构23在第二衬底20上的正投影之间沿Y方向的距离可以称为第四距离d4，隔垫物5在第二衬底20上的正投影与第四凸起结构24在第二衬底20上的正投影之间沿Y方向的 距离可以称为第五距离d5。例如，所述第四距离d4可以用所述中心50至所述边缘部235沿Y方向的距离表示，所述第五距离d5可以用所述中心50至所述边缘部245沿Y方向的距离表示。
可选地，所述第四距离d4可以基本等于第五距离d5。即，隔垫物5在Y方向上朝向上侧和朝向下侧具有基本相等的滑移距离。
可选地，所述第四距离d4可以大于等于所述第一距离d1。
在本公开的实施例中，通过这样的设置，在第一基板1相对于第二基板发生上、下、左、右等各个方向的偏移(该偏移可能由对盒偏差引起)时，隔垫物5具有足够的滑移空间，并且可以阻挡隔垫物5滑入所述透光区中，可以避免隔垫物划伤位于透光区中的取向膜。
在上述示例性的实施例中，隔垫物5仅设置在第一子像素SP1中，第二子像素SP2和第三子像素SP3中未设置隔垫物5。返回参照图3和图4，栅线GL位于第二子像素SP2中的部分不具有第一加宽部GL1，仅具有第二加宽部GL2，相应地，公共电极线CL位于第二子像素SP2中的部分也不具有加宽部CL1。同样地，栅线GL位于第三子像素SP3中的部分不具有第一加宽部GL1，仅具有第二加宽部GL2，相应地，公共电极线CL位于第三子像素SP3中的部分也不具有加宽部CL1。
需要说明的是，在上述实施例中，所述第一子像素SP1为红色子像素，所述第二子像素SP2为绿色子像素，所述第三子像素SP3为蓝色子像素。隔垫物5设置在红色子像素S P1中，这样，可以避免隔垫物5的设置对显示色温和显示颜色产生影响。但是，本公开的实施例不局限于此，隔垫物5可以设置在第一子像素SP1、第二子像素SP2和第三子像素SP3中的至少一个中。
例如，像素电极7可以是狭缝电极，即，像素电极7具有多个狭缝71。公共电极8可以是面状电极，公共电极线CL可以与公共电极8电连接。像素电极7在第二衬底20上的正投影与公共电极8在第二衬底20上的正投影至少部分交叠。
例如，根据本公开的一些示例性实施例的显示面板可以适用于AD-SDS(Advanced-Super Dimensional Switching，简称为ADS，即高级超维场开关)型、IPS型等类型的液晶显示装置中。在ADS型显示装置中，通过同一平面内像素电极边缘所产生的平行电场以及像素电极层与公共电极层之间产生的纵向电场，形成多维电场，使液晶盒内像素电极之间以及像素电极上方的所有液晶分子都能够产生旋转转换，从 而提高了平面取向系液晶工作效率并增大了透光效率。
需要说明的是，本公开的实施例不局限于上面的描述，例如，在其他实施例中，位于第一电极层中的电极可以是像素电极，位于第二电极层中的电极可以是公共电极。
参照图10，隔垫物5、栅线GL、数据线DL、公共电极线CL和薄膜晶体管6中每一个在第二衬底20上的正投影均落入黑矩阵12在第二衬底20上的正投影内。也就是说，它们均设置在黑矩阵12的覆盖范围之内，即都位于不透光区中。
本公开至少一个实施例还提供一种显示装置100。图12为根据本公开一实施例提供的一种显示装置的结构示意图。如图12所示，该显示装置包括根据上述任一实施例所提供的显示面板。由此，该显示装置也同样具有与其包括的显示面板的有益效果对应的技术效果，具体可参见上述描述。
例如，在一些示例中，该显示装置可以为智能手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本公开还可有其它多种实施例，在不背离本公开的精神及其实质的情况下，本领域的技术人员可根据本公开的实施例作出各种相应的改变和变形，但这些相应的改变和变形都应属于本公开所附的权利要求的保护范围。

Claims (30)

  1. 一种显示面板，包括：
    第一基板，所述第一基板包括：
    第一衬底；和
    设置在所述第一衬底上的多个隔垫物；和
    与所述第一基板相对设置的第二基板，所述第二基板包括：
    第二衬底；
    设置在所述第二衬底上的多条栅线和多条数据线，每一条所述栅线沿行方向设置，每一条所述数据线沿列方向设置；和
    沿所述行方向和所述列方向成阵列地布置在所述第二衬底上的多个子像素，所述多条栅线和所述多条数据线包围形成所述多个子像素，每一个子像素均包括透光区，
    其中，所述多个隔垫物包括至少一个第一隔垫物，所述多条数据线至少包括第一数据线，所述多个子像素包括第一子像素，所述第一数据线邻近所述第一子像素设置；
    所述第一隔垫物在所述第二衬底上的正投影邻近所述第一子像素的透光区在所述第二衬底上的正投影，所述第一隔垫物在所述第二衬底上的正投影与所述第一数据线在所述第二衬底上的正投影间隔设置；
    所述第一数据线具有主体部和弯折部，所述弯折部在所述第二衬底上的正投影相对于所述主体部在所述第二衬底上的正投影朝远离所述第一隔垫物在所述第二衬底上的正投影的方向弯折。
  2. 根据权利要求1所述的显示面板，其中，所述弯折部包括弯折主体部和两个弯折连接部，所述弯折主体部和所述第一数据线的主体部的设置方向彼此平行，所述弯折主体部的一端通过一个弯折连接部连接至所述第一数据线的主体部的一段，所述弯折主体部的另一端通过另一个弯折连接部连接至所述第一数据线的主体部的另一段。
  3. 根据权利要求1或2所述的显示面板，其中，所述多条数据线还包括第二数据线，所述第二数据线邻近所述第一子像素设置；
    所述第一数据线在所述第二衬底上的正投影和所述第二数据线在所述第二衬底上的正投影在所述行方向上分别位于所述第一隔垫物在所述第二衬底上的正投影的两侧，所述第二数据线在所述第二衬底上的正投影与所述第一隔垫物在所述第二衬底上的正投影之间沿所述行方向的距离大于所述第一数据线在所述第二衬底上的正投影与所述第一隔垫物在所述第二衬底上的正投影之间沿所述行方向的距离。
  4. 根据权利要求3所述的显示面板，其中，所述第二数据线具有主体部和弯折部，所述第二数据线的弯折部在所述列方向的投影与所述第一隔垫物在所述列方向的投影至少部分交叠，所述第二数据线的弯折部在所述第二衬底上的正投影相对于所述第二数据线的主体部在所述第二衬底上的正投影朝远离所述第一隔垫物在所述第二衬底上的正投影的方向弯折。
  5. 根据权利要求4所述的显示面板，其中，所述第二数据线的弯折部包括弯折主体部和两个弯折连接部，所述第二数据线的弯折主体部和所述第二数据线的主体部的设置方向彼此平行，所述第二数据线的弯折主体部的一端通过一个第二数据线的弯折连接部连接至所述第二数据线的主体部的一段，所述第二数据线的弯折主体部的另一端通过第二数据线的另一个弯折连接部连接至所述第二数据线的主体部的另一段。
  6. 根据权利要求4或5所述的显示面板，其中，所述多条栅线包括邻近所述第一子像素设置的第一栅线，所述第一隔垫物在所述第二衬底上的正投影落入所述第一栅线在所述第二衬底上的正投影内。
  7. 根据权利要求6所述的显示面板，其中，所述第一栅线包括第一加宽部和第二加宽部，所述第一加宽部和所述第二加宽部在所述第二衬底上的正投影位于所述第一数据线在所述第二衬底上的正投影与所述第二数据线在所述第二衬底上的正投影之间；
    所述第一加宽部和所述第二加宽部中的每一个沿所述列方向的尺寸大于所述第一栅线的其它部分沿所述列方向的尺寸，所述第一隔垫物在所述第二衬底上的正投影落入所述第一栅线的第一加宽部在所述第二衬底上的正投影内。
  8. 根据权利要求7所述的显示面板，其中，所述第二基板还包括设置在所述第二衬底上的多个薄膜晶体管，所述多个薄膜晶体管包括邻近所述第一子像素设置的至少一个第一薄膜晶体管；
    所述第一薄膜晶体管在所述第二衬底上的正投影落入所述第一栅线的第二加宽部在所述第二衬底上的正投影内。
  9. 根据权利要求8所述的显示面板，其中，所述第一薄膜晶体管在所述第二衬底上的正投影位于所述第一隔垫物在所述第二衬底上的正投影与所述第二数据线的弯折部在所述第二衬底上的正投影之间。
  10. 根据权利要求8或9所述的显示面板，其中，所述第一栅线还包括多个倾斜部，每一个倾斜部在所述第二衬底上的正投影的设置方向与所述行方向成锐角的夹角；
    所述第一数据线的弯折部在所述第二衬底上的正投影与所述第一栅线的一个倾斜部在所述第二衬底上的正投影至少部分交叠，所述第二数据线的弯折部在所述第二衬底上的正投影与所述第一栅线的另一个倾斜部在所述第二衬底上的正投影至少部分交叠。
  11. 根据权利要求10所述的显示面板，其中，所述多个子像素还包括与所述第一子像素相邻的第二子像素，所述多条数据线还包括第三数据线，所述第一数据线和所述第三数据线分别位于所述第二子像素两侧；
    所述第三数据线包括弯折部，所述第三数据线的弯折部在所述列方向的投影与所述第一数据线的弯折部和所述第二数据线的弯折部中的每一个在所述列方向的投影至少部分交叠，所述第三数据线的弯折部的弯折方向与所述第一数据线的弯折部和所述第二数据线的弯折部中的一个的弯折方向相同。
  12. 根据权利要求10所述的显示面板，其中，所述第二基板还包括设置在所述第二衬底上的多条公共电极线，每一条所述公共电极线沿所述行方向设置；
    所述多条公共电极线包括第一公共电极线，所述第一公共电极线在所述第二衬底 上的正投影与所述第一栅线在所述第二衬底上的正投影相邻，所述第一公共电极线具有主体部和弯折部，所述第一公共电极线的弯折部在所述行方向的投影与所述第一加宽部在所述行方向的投影至少部分交叠，所述第一公共电极线的弯折部在所述第二衬底上的正投影相对于所述第一公共电极线的主体部在所述第二衬底上的正投影朝远离所述第一加宽部在所述第二衬底上的正投影的方向弯折。
  13. 根据权利要求12所述的显示面板，其中，所述第一加宽部相对于所述第二加宽部和所述倾斜部中的每一个朝向所述第一公共电极线突出。
  14. 根据权利要求13所述的显示面板，其中，所述第一加宽部与所述第一公共电极线的弯折部之间沿所述列方向的间隔距离等于所述第二加宽部与所述第一公共电极线的主体部之间沿所述列方向的间隔距离。
  15. 根据权利要求12-14中任一项所述的显示面板，其中，所述第一公共电极线的弯折部沿所述列方向的尺寸大于所述第一公共电极线的主体部沿所述列方向的尺寸。
  16. 根据权利要求8或9所述的显示面板，其中，所述第一薄膜晶体管包括有源层、栅极、第一电极和第二电极，所述第二基板还包括设置在所述第二衬底上的像素电极；
    所述第一电极与所述第二数据线电连接，所述第二电极与所述像素电极电连接；
    所述第一电极具有第一部分和第二部分，所述第一电极的第一部分直接自所述第二数据线沿所述行方向延伸，所述第一电极的第二部分在所述第二衬底上的正投影落入所述第二加宽部在所述第二衬底上的正投影内；
    所述第二电极具有第一部分和第二部分，所述第二电极的第一部分在所述第二衬底上的正投影与所述像素电极在所述第二衬底上的正投影至少部分交叠，所述第二电极的第二部分在所述第二衬底上的正投影落入所述第二加宽部在所述第二衬底上的正投影内；
    所述第一电极的第一部分沿所述列方向的尺寸大于所述第一电极的第二部分沿所 述行方向的尺寸，所述第二电极的第一部分沿所述行方向的尺寸大于所述第二电极的第二部分沿所述行方向的尺寸。
  17. 根据权利要求16所述的显示面板，其中，所述第一电极的第二部分与所述第二电极的第二部分平行，所述第二电极的第二部分比所述第一电极的第二部分更靠近所述第一加宽部。
  18. 根据权利要求17所述的显示面板，其中，所述第一隔垫物在所述第二衬底上的正投影与所述第一数据线的弯折部在所述第二衬底上的正投影之间沿所述行方向间隔第一距离，所述第一隔垫物在所述第二衬底上的正投影与所述第二电极的第二部分在所述第二衬底上的正投影之间沿所述行方向间隔第二距离，所述第一距离等于所述第二距离。
  19. 根据权利要求18所述的显示面板，其中，所述第一距离大于等于10微米。
  20. 根据权利要求12-14中任一项所述的显示面板，其中，所述第二基板包括位于所述第二衬底上的第一凸起结构和第二凸起结构，所述第一凸起结构和所述第二凸起结构沿所述行方向位于所述第一隔垫物的两侧；
    所述第一凸起结构在所述第二衬底上的正投影与所述第一数据线的弯折部在所述第二衬底上的正投影至少部分交叠，所述第二凸起结构在所述第二衬底上的正投影与所述第一薄膜晶体管在所述第二衬底上的正投影至少部分交叠。
  21. 根据权利要求20所述的显示面板，其中，所述第二基板还包括位于所述第二衬底上的第三凸起结构和第四凸起结构，所述第三凸起结构和所述第四凸起结构沿所述列方向位于所述第一隔垫物的两侧；
    所述第三凸起结构在所述第二衬底上的正投影与所述第一公共电极线的弯折部在所述第二衬底上的正投影至少部分交叠，所述第四凸起结构在所述第二衬底上的正投影与所述第一子像素的像素电极在所述第二衬底上的正投影至少部分交叠。
  22. 根据权利要求21所述的显示面板，其中，所述第二基板包括设置在所述第二衬底上的第一导电层和第二导电层，所述第二导电层设置在所述第一导电层远离所述第二衬底的一侧；
    所述栅线和所述公共电极线位于所述第一导电层，所述数据线以及所述薄膜晶体管的第一电极和第二电极位于所述第二导电层。
  23. 根据权利要求22所述的显示面板，其中，所述第三凸起结构包括位于所述第二导电层中的第一凸台，所述第一凸台在所述第二衬底上的正投影落入所述第一公共电极线的弯折部在所述第二衬底上的正投影内。
  24. 根据权利要求23所述的显示面板，其中，所述第四凸起结构包括第二凸台和第三凸台，所述第二凸台位于所述第一导电层，所述第三凸台位于所述第二导电层，所述第三凸台在所述第二衬底上的正投影落入所述第二凸台在所述第二衬底上的正投影内。
  25. 根据权利要求7所述的显示面板，其中，所述第一隔垫物和所述第一加宽部中的每一个在所述第二衬底上的正投影具有八边形形状，所述第一隔垫物在所述第二衬底上的正投影的面积小于所述第一加宽部在所述第二衬底上的正投影的面积。
  26. 根据权利要求11所述的显示面板，其中，所述第一数据线、所述第二数据线和所述第三数据线中的每一个都包括多个弯折部；
    同一条数据线包括的多个弯折部的弯折方向彼此相同，或者，同一条数据线包括的多个弯折部中的至少两个弯折部的弯折方向彼此不同。
  27. 根据权利要求12所述的显示面板，其中，所述第一基板还包括设置在所述第一衬底上的黑矩阵，所述栅线、所述数据线、所述公共电极线和所述薄膜晶体管中的每一个在所述第一衬底上的正投影落入所述黑矩阵在所述第一衬底上的正投影内。
  28. 根据权利要求1或2所述的显示面板，其中，所述第一子像素为红色子像素。
  29. 根据权利要求16所述的显示面板，其中，所述第二基板包括设置在所述第二衬底上的第一电极层和第二电极层，所述第二电极层设置在所述第一电极层远离所述第二衬底的一侧；
    所述第二基板还包括设置在所述第二衬底上的公共电极，所述像素电极设置在所述第一电极层和第二电极层中的一个中，所述公共电极设置在所述第一电极层和第二电极层中的另一个中。
  30. 一种显示装置，包括根据权利要求1-29中任一项所述的显示面板。
PCT/CN2021/098966 2020-07-17 2021-06-08 显示面板和显示装置 WO2022012227A1 (zh)

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