WO2022011641A1 - 制备GaN器件的方法以及GaN器件 - Google Patents

制备GaN器件的方法以及GaN器件 Download PDF

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WO2022011641A1
WO2022011641A1 PCT/CN2020/102404 CN2020102404W WO2022011641A1 WO 2022011641 A1 WO2022011641 A1 WO 2022011641A1 CN 2020102404 W CN2020102404 W CN 2020102404W WO 2022011641 A1 WO2022011641 A1 WO 2022011641A1
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substrate
layer
gan
stress compensation
stress
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PCT/CN2020/102404
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English (en)
French (fr)
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王昆
张孝坤
杨承瑜
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华为技术有限公司
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Priority to PCT/CN2020/102404 priority Critical patent/WO2022011641A1/zh
Priority to CN202080102366.3A priority patent/CN115868006A/zh
Publication of WO2022011641A1 publication Critical patent/WO2022011641A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

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  • the present application relates to the field of semiconductor devices, and in particular, to a method for preparing a GaN device and a GaN device.
  • GaN material has the advantages of large band gap, low dielectric constant, high electron mobility, and high electron saturation velocity, and has quickly become an ideal material for the fabrication of high-power and high-frequency power electronic devices.
  • a heterogeneous substrate such as a Si substrate
  • a heterogeneous substrate is generally selected for epitaxial growth of GaN materials.
  • the lattice constants of the GaN epitaxial layer and the Si substrate are different, and there is a certain lattice mismatch.
  • Lattice mismatch will introduce a high density of dislocations into the GaN material, and the larger the lattice mismatch, the higher the dislocation density will tend to be.
  • the thermal expansion coefficients of the GaN epitaxial layer and the Si substrate are different, and there is a certain thermal mismatch.
  • the thermal mismatch will cause the Si substrate to produce huge tension on the GaN epitaxial layer when the GaN epitaxial layer is cooled from the growth temperature to room temperature. stress, which can cause cracking of the GaN epitaxial layer.
  • the main reason why the GaN epitaxial layer cracks is that the tensile stress in the GaN epitaxial layer is too large, and the material cannot withstand such tensile strain.
  • a buffer layer is introduced between the Si substrate and the GaN outer layer.
  • the lattice constant of the buffer layer is smaller than that of GaN, so that the buffer layer generates compressive strain at the interface of the GaN epitaxial layer, thereby weakening or The tensile strain generated between the Si substrate and the GaN epitaxial layer is removed.
  • the GaN epitaxial layer is epitaxially grown on the buffer layer by a method that can reduce the dislocation density, the compressive strain generated by the buffer layer at the interface of the GaN epitaxial layer will be reduced, resulting in the inability of the tensile strain generated between the Si substrate and the GaN epitaxial layer. is weakened so that the GaN epitaxial layer cracks.
  • the present application provides a method for preparing a GaN device and a GaN device, which can reduce the phenomenon of cracking of the GaN layer.
  • a first aspect of the present application provides a method of fabricating a GaN device.
  • the method includes generating a stress compensation layer on the backside of the substrate; and epitaxially growing a GaN layer on the frontside of the substrate.
  • the thermal expansion coefficient of the stress compensation layer is different from that of the substrate, that is, the thermal expansion coefficient of the stress compensation layer may be greater than or smaller than that of the substrate. Because the thermal expansion coefficient of the stress compensation layer is different from that of the substrate, the stress compensation layer applies a stress to the substrate. By setting the ratio of the thickness of the stress compensation layer to the thickness of the substrate, the stress will behave differently.
  • the stress is expressed as a tensile stress to the entire substrate, that is, the front and back sides of the substrate are both subjected to tensile stress. If the thermal expansion coefficient of the stress compensation layer is smaller than the thermal expansion coefficient of the substrate, and the ratio of the thickness of the stress compensation layer to the thickness of the substrate is small, the stress is manifested as applying tensile stress to part of the substrate and applying compressive stress to another part of the substrate , that is, the backside of the substrate is under compressive stress, and the front side of the substrate is under tensile stress.
  • the front surface of the substrate is subjected to tensile stress by preparing a stress compensation layer on the back surface of the substrate.
  • the tensile stress exerted by the substrate on the GaN layer is reduced, and the phenomenon of cracking of the GaN layer is reduced.
  • the method further includes: growing an AlGaN layer on the GaN layer.
  • the method further includes: forming a source electrode, a drain electrode and a gate electrode on the AlGaN layer.
  • the material selection and thickness of the stress compensation layer and the substrate satisfy the following conditions:
  • the ratio of the thickness of the stress compensation layer to the thickness of the substrate is smaller than a preset threshold, and the thermal expansion coefficient of the stress compensation layer is smaller than the thermal expansion coefficient of the substrate;
  • the ratio of the thickness of the substrate is greater than a preset threshold, and the thermal expansion coefficient of the stress compensation layer is greater than the thermal expansion coefficient of the substrate.
  • the thickness of the stress compensation layer is 5um to 70um.
  • the substrate is a silicon substrate, and the material of the stress compensation layer is SiO 2 .
  • the thermal expansion coefficient of SiO 2 is smaller than that of Si, and SiO 2 is resistant to high temperature. Further, compared with SiN, SiO 2 is more easily corroded, and if the stress compensation layer needs to be removed later, the cost of removing the stress compensation layer can be reduced. Further, the thermal expansion coefficient of SiO 2 is smaller than that of SiC, that is, when the substrate is a SiC substrate, SiO 2 can be used as the stress compensation layer of the SiC substrate, thereby realizing the common use of SiO 2 as the stress compensation layer for various substrates. , reducing the cost of the stress compensation layer.
  • the GaN layer is epitaxially grown on the front side of the substrate using a two-step growth method or lateral epitaxy.
  • the lattice constant of Si is about 5.43A, and that of GaN is about 3.19A.
  • the substrate is a Si substrate, a buffer layer is included between the Si substrate and the GaN layer, and the lattice constant of the buffer layer is smaller than that of GaN. Since the lattice constant of the buffer layer is smaller than that of GaN, the GaN layer is epitaxially grown on the buffer layer, and the buffer layer will exert a compressive stress on the GaN layer.
  • the compressive stress can be used to offset part or all of the tensile stress, which is the stress exerted by the Si substrate on the GaN layer during cooling due to the difference in thermal expansion coefficients. By offsetting some or all of the tensile stress, the risk of cracking of the GaN layer can be reduced. Therefore, this compressive stress is beneficial.
  • the two-step growth method or lateral epitaxy can reduce the dislocation density between the buffer layer and the GaN layer, but will reduce or even eliminate this compressive stress, thereby increasing the risk of cracking of the GaN layer.
  • the present application reduces or even cancels the tensile stress exerted by the substrate on the GaN layer by preparing a stress compensation layer on the backside of the substrate.
  • the stress compensation layer offsets the tensile stress exerted by the substrate on the GaN layer, it can be expressed by the following formula 1: F1 is the tensile stress of the stress compensation layer on the front side of the substrate, K is the elastic coefficient of the substrate, D2 is the third temperature, D1 is the first temperature, ⁇ 1 is the thermal expansion coefficient of GaN, and ⁇ 2 is the thermal expansion coefficient of the substrate.
  • the buffer layer applies a stress Y to the GaN layer.
  • the stress compensation layer needs to offset the tensile stress applied by the substrate to the GaN layer according to the above formula 1, because of the existence of the stress Y, F1 needs to be adjusted up and down. If the lattice constant of the buffer layer is greater than that of GaN, the stress Y is tensile stress, and F1 needs to be increased; if the lattice constant of the buffer layer is smaller than that of GaN, the stress Y is compressive stress, and F1 needs to be decreased. If there is no buffer layer between the substrate and the GaN layer, the above stress Y can be understood as the stress exerted by the substrate on the GaN layer.
  • the stress reduction and dislocation density decoupling are achieved by preparing the stress compensation layer.
  • the stress compensation layer is responsible for reducing the stress
  • the epitaxial growth method is responsible for reducing the dislocation density, so that the two-step growth method or lateral epitaxy can not be used without worrying about the stress problem. Therefore, reducing or even eliminating the stress Y by the two-step growth method or lateral epitaxy not only does not increase the risk of cracking of the GaN layer, but also reduces or even eliminates the influence of the stress Y on Equation 1, which is convenient to determine F1, which can then be derived from F1 Thickness and thermal expansion coefficient of the stress compensation layer.
  • the stress compensation layer is formed on the backside of the substrate
  • the stress compensation layer is formed on the backside of the substrate at a second temperature, the second temperature being greater than the second temperature.
  • the method further includes: removing the stress compensation layer.
  • the function of the stress compensation layer is to provide tensile stress on the front surface of the substrate when the GaN layer is epitaxially grown. After the epitaxial growth of the GaN layer is completed, the stress compensation layer can be removed to reduce the thickness of the GaN device.
  • the stress compensation layer is removed at a third temperature, where the third temperature is lower than the second temperature, the third temperature is lower than the first temperature, and the third temperature is lower than the first temperature.
  • the difference between the temperature and the first temperature is less than 500 degrees.
  • the present application defines the third temperature, and the third temperature is generally room temperature.
  • the stress compensation layer is removed by mechanical grinding.
  • mechanical grinding in the processing flow of GaN devices, there is generally a process of mechanical grinding.
  • by removing the stress compensation layer in the process of mechanical grinding only one process of preparing the stress compensation layer can be added without adding a process of removing the stress compensation layer, thereby reducing the increase of processes and reducing the production cost.
  • a buffer layer is further included, and the buffer layer is used for preventing the alloy reaction between the GaN layer and the substrate.
  • the buffer layer is used to prevent the alloying reaction between the GaN layer and the substrate.
  • the lattice constant of the buffer layer must be smaller than that of GaN, so that the buffer layer can reduce the tensile stress on the GaN layer.
  • the stress compensation layer bears the function of reducing stress, and the buffer layer may not need to bear the function of reducing stress, so the lattice constant of the buffer layer does not need to be smaller than that of GaN.
  • the increased range of material choices for the buffer layer provides for a lower cost, and/or material that does not block the vertical flow of current in the GaN device as a buffer layer.
  • a second aspect of the present application provides a GaN device.
  • the GaN device includes: a substrate;
  • a stress compensation layer formed on the back of the substrate
  • a GaN layer is formed on the front surface of the substrate.
  • the device further includes:
  • An AlGaN layer is formed on the front surface of the GaN layer.
  • the device further includes:
  • a source region, a drain region and a gate region are formed on the front side of the AlGaN layer.
  • the material selection and thickness of the stress compensation layer and the substrate satisfy the following conditions:
  • the ratio of the thickness of the stress compensation layer to the thickness of the substrate is smaller than a preset threshold, and the thermal expansion coefficient of the stress compensation layer is smaller than the thermal expansion coefficient of the substrate;
  • the ratio of the thickness of the substrate is greater than a preset threshold, and the thermal expansion coefficient of the stress compensation layer is greater than the thermal expansion coefficient of the substrate.
  • the thickness of the stress compensation layer is 5um to 70um.
  • the substrate is a Si substrate
  • the material of the stress compensation layer is SiO 2 .
  • a buffer layer is further included between the substrate and the GaN layer.
  • FIG. 1 is a schematic structural diagram of a GaN-based HEMT
  • FIG. 2 is a schematic diagram of warpage of a GaN device
  • FIG. 3 is a schematic diagram of a GaN device with reduced tensile stress by adding a buffer layer
  • FIG. 4 is a schematic flowchart of a method for reducing tensile stress in a GaN device according to an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a GaN device in a manufacturing process when the thickness ratio is less than a threshold in an embodiment of the present application;
  • FIG. 6 is a schematic diagram of a force of a GaN device in an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of a GaN device in a manufacturing process when the thickness ratio is greater than a threshold in an embodiment of the present application;
  • FIG. 8 is another schematic diagram of stress of the GaN device in the embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a GaN device in an embodiment of the present application.
  • the embodiments of the present application provide a method for preparing a GaN device and a GaN device, which are applied to the field of semiconductor devices and can reduce the phenomenon of cracking of the GaN layer in the GaN device.
  • Epitaxial growth broadly speaking, epitaxial growth also belongs to a thin film deposition technology.
  • extension means "extends outward".
  • This is a special thin film growth, which refers to the growth of a new single crystal on a single crystal substrate, that is, under certain conditions, on the prepared single crystal substrate, along the crystallographic axis of the original crystal, A new single crystal layer whose conductivity type, resistivity, thickness, etc. meet the requirements is grown, which is called an epitaxial layer.
  • epitaxial layer In addition to the crystallographic direction of the epitaxial layer being consistent with the substrate single crystal, other characteristics can be independently selected, such as conductivity type, resistivity, thickness, etc., can be grown according to new requirements. According to whether the materials of the epitaxial layer and the substrate are the same, epitaxy can be divided into homoepitaxy and heteroepitaxy.
  • GaN material has the advantages of large band gap, low dielectric constant, high electron mobility and high electron saturation velocity, and has quickly become an ideal material for the fabrication of high-power and high-frequency power electronic devices.
  • Epitaxial growth of an epitaxial layer of GaN material on a substrate is the basis for making GaN electronic devices (referred to as GaN devices).
  • GaN devices include heterojunction field effect transistors (HFETs), semiconductor field effect transistors (metal oxide semiconductor field effect transistors, MOSFETs), high electron mobility transistors (HEMTs), etc.
  • FIG. 1 is a schematic structural diagram of a GaN-based HEMT. Along the vertical direction, the substrate 102, the GaN layer 101 and the ALAlGaN layer 103 are respectively included.
  • the front surface of the substrate 102 is adjacent to the GaN layer 101 , and the front surface of the substrate 102 refers to the surface of the substrate 102 facing the positive vertical direction.
  • the definitions of the horizontal direction, the vertical direction and the front side of the GaN device will be used.
  • FIG. 1 is only a schematic structural diagram of a GaN-based HEMT, and other layers may also be included in the actual structure of the GaN-based HEMT.
  • a GaN layer is further included on the front surface of the AlGaN layer 103 .
  • the front surface of the AlGaN layer 103 refers to the surface of the AlGaN layer 103 facing the positive vertical direction.
  • Lattice mismatch refers to the mismatch phenomenon caused by the difference in the lattice constants of the substrate and the epitaxial layer during epitaxial growth.
  • dislocation refers to an internal microscopic defect in a crystalline material, that is, a local irregular arrangement of atoms (crystallographic defect).
  • Dislocation is a kind of line defect, which can be regarded as the boundary between the slipped part and the non-slipped part in the crystal, and its existence has a great influence on the physical properties of the material.
  • Dislocation density is defined as the total length of demarcation lines contained in a unit volume of crystal. Dislocation density can be used to describe the extent of dislocations resulting from lattice mismatch.
  • Thermal mismatch that is, thermal expansion mismatch.
  • epitaxial growth the mismatch phenomenon caused by the different thermal expansion coefficients of the substrate and the epitaxial layer.
  • epitaxial growth temperature usually GaN devices require epitaxial growth of epitaxial layers at high temperature, referred to as epitaxial growth temperature.
  • the temperature used for GaN devices is generally room temperature, and there is a difference between room temperature and epitaxial growth temperature.
  • the thermal expansion coefficients of the substrate and the epitaxial layer are different, and there is stress between the substrate and the epitaxial layer after the epitaxial growth temperature is lowered to room temperature.
  • the methods for preparing GaN devices in the embodiments of the present application are used in the process of preparing GaN devices, specifically, in the process of epitaxially growing GaN on a substrate.
  • the substrate may be a Si substrate, a SiC substrate, or the like.
  • Si substrate refers to a substrate composed of Si elemental substance
  • a SiC substrate refers to a substrate composed of compound SiC. It should be confirmed that the above-mentioned Si substrate and SiC substrate may contain some impurities. For the convenience of explanation, the following description will be made by taking the Si substrate as the substrate.
  • the crystal structure of GaN includes a hexagonal wurtzite or sphalerite structure. Among them, the hexagonal wurtzite crystal is the most stable, and the Si material has a cubic diamond structure. And the epitaxial growth of GaN epitaxial layer on Si substrate has the following difficulties: First, due to the large lattice mismatch between the GaN epitaxial layer and the Si substrate, this will cause a large dislocation density in the GaN epitaxial layer. When the dislocation density of the GaN layer and the Si substrate is large, it will affect the performance of the GaN device. In addition, the lattice constant of GaN is smaller than that of Si.
  • the Si substrate When the GaN layer is epitaxially grown on the Si substrate, the Si substrate will exert a tensile stress on the GaN layer. Secondly, the huge difference in thermal expansion coefficient between GaN and Si will cause the Si substrate to generate huge tensile stress on the GaN layer during the process of cooling the GaN layer from the epitaxial growth temperature to room temperature, causing the GaN device to warp. Affected by the above-mentioned two tensile stresses, when the GaN layer cannot withstand the pulling of the tensile stress, the GaN layer will crack, failing to meet the requirements for device fabrication and affecting the quality and performance of the GaN layer. As shown in FIG. 2, FIG.
  • 2 is a schematic diagram of warpage of a GaN device, wherein, 2b is a schematic diagram of a GaN device after epitaxial growth of the GaN layer 201 at high temperature.
  • the GaN layer 201 and the Si substrate 202 are theoretically horizontal 2a is a schematic diagram of warpage of the GaN device at room temperature.
  • the Si substrate 202 and the GaN layer 201 warp in the positive direction of the vertical direction of the GaN device. If the warpage is serious, cracks may also occur in the GaN layer 201 . Cracks in the GaN layer 201 refer to the phenomenon of cracks occurring on the front surface of the GaN layer 201 .
  • FIG. 3 is a schematic diagram of a GaN device that reduces tensile stress by adding a buffer layer.
  • 3b is a schematic structural diagram of a GaN device after epitaxially growing the buffer layer 303 and the GaN layer 301 at high temperature. At this time, the GaN layer 301, the Si substrate 302, and the buffer layer 303 are theoretically horizontal.
  • 3a is a schematic structural diagram of a GaN device at room temperature. At room temperature, the GaN layer 301 can reduce the tensile stress, so the GaN layer 301 can reduce the degree of warpage. The figure is a schematic diagram of theoretically completely eliminating the tensile stress.
  • the tensile stress on the GaN layer can be reduced by adding a buffer layer, but in order to improve the quality of the GaN device, the dislocation density between the GaN layer and the Si substrate also needs to be reduced.
  • the technical means of reducing the dislocation density are adopted, the tensile stress on the GaN layer cannot be effectively reduced.
  • the buffer layer needs to use lattice mismatch to generate compressive stress on the GaN layer, but the efficiency of reducing the dislocation density is low.
  • the dislocation density can be reduced by the two-step growth method or lateral epitaxy, but it will reduce the compressive stress on the GaN layer, thereby increasing the thermal mismatch and leading to cracking. That is, in the epitaxial growth of GaN on the Si substrate, the two goals of reducing the tensile stress on the GaN layer and reducing the dislocation density are intertwined, and the current method cannot achieve both goals at the same time.
  • the embodiments of the present application provide a method for fabricating a GaN device, which can reduce the tensile stress on a GaN layer in the GaN device. And, this method has the following benefits. First, this method can achieve mutual decoupling of reducing the tensile stress on the GaN layer and reducing the dislocation density, without reducing the effect of one target to improve the effect of another target. Second, the method is compatible with the method of increasing the buffer layer and can work together.
  • the method for preparing a GaN device provided by the embodiments of the present application will be described in detail below. Exemplarily, the features or contents marked with dotted lines in the drawings involved in the embodiments of the present application may be understood as optional operations or optional structures of the embodiments.
  • FIG. 4 is a schematic flowchart of a method for fabricating a GaN device in an embodiment of the present application.
  • step 401 at a first temperature, a stress compensation layer is prepared on the backside of the Si substrate, and the thermal expansion coefficient of the stress compensation layer is different from that of the Si substrate.
  • the front side of the Si substrate refers to the side on which the GaN layer is epitaxially grown
  • the back side of the Si substrate refers to the side opposite to the side on which the GaN layer is epitaxially grown.
  • the thermal expansion coefficient of the stress compensation layer is different from that of the Si substrate, that is, the thermal expansion coefficient of the stress compensation layer may be greater than or smaller than that of the Si substrate.
  • the relative magnitudes of the thermal expansion coefficients of the stress compensation layer and the Si substrate depend on the relative thicknesses of the stress compensation layer and the Si substrate.
  • the ratio of the thickness of the stress compensation layer to the Si substrate is greater than the threshold value, the thermal expansion coefficient of the stress compensation layer is greater than that of the Si substrate.
  • the ratio of the thickness of the stress compensation layer to the Si substrate is referred to as the thickness below. ratio; when the thickness ratio is smaller than the threshold value, the thermal expansion coefficient of the stress compensation layer is smaller than that of the Si substrate. As shown at 5a in FIG.
  • FIG. 5 is a schematic structural diagram of a GaN device in a manufacturing process when the thickness ratio is smaller than the threshold in the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of the GaN device in the manufacturing process when the thickness ratio is greater than the threshold in the embodiment of the present application.
  • 5a and 7a are schematic structural diagrams of the GaN device after the stress compensation layer is prepared on the backside of the Si substrate.
  • the GaN device in 5a includes the Si substrate 502 and the stress compensation layer 503 in sequence along the vertical direction.
  • the GaN device in 7a includes the Si substrate 702 and the stress compensation layer 703 in sequence along the vertical direction.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • sputtering to prepare stress on the backside of the Si substrate compensation layer.
  • the buffer layer plays the role of connecting the Si substrate and the GaN layer, it needs to have better epitaxial growth quality, so the epitaxial growth buffer layer needs to use metal-organic chemical vapor deposition (metal-organic compound).
  • metal-organic chemical vapor deposition metal-organic compound
  • chemical vapor deposition, MOCVD MOCVD
  • MOCVD metal-organic chemical vapor deposition
  • MOCVD metal-organic compound
  • PECVD equipment or LPCVD equipment, or sputtering equipment can effectively reduce equipment costs.
  • MOCVD equipment takes more time. Therefore, the use of PECVD equipment, LPCVD equipment, or sputtering equipment in the embodiments of the present application can effectively reduce the time cost.
  • the ratio of the thickness of the stress compensation layer to the thickness of the Si substrate is smaller than a threshold value, and the thermal expansion coefficient of the stress compensation layer is smaller than that of the Si substrate.
  • the function of the stress compensation layer is to provide tensile stress on the front surface of the Si substrate, and it may not need to bear the function of current load. Therefore, the thickness of the stress compensation layer does not affect the thickness of the Si substrate, that is, it can be assumed that the thickness of the Si substrate is fixed under the condition that the original design requirements are met.
  • the original design requirement refers to the design requirement for the thickness of the Si substrate of the GaN device without including the stress compensation layer.
  • the thickness of the stress compensation layer in the GaN device needs to be designed.
  • the present application defines that the ratio of the thickness of the stress compensation layer to the thickness of the Si substrate is less than a threshold value. Under this limitation, the time for generating the stress compensation layer can be reduced.
  • the thickness of the stress compensation layer is 5um to 70um.
  • the thickness of the stress compensation layer is limited to be 5um to 70um.
  • the material of the stress compensation layer is SiN.
  • the substrate is a Si substrate
  • the material of the stress compensation layer can be SiO 2 .
  • the thermal expansion coefficient of SiO 2 is smaller than that of Si, and SiO 2 is resistant to high temperature, and the melting point of SiO 2 is 1650 degrees.
  • the epitaxial growth temperature is generally 800 degrees, at this temperature, SiO 2 will not be melted.
  • SiO 2 is easier to be removed because it is easier to be etched, so the cost of removing the stress compensation layer can be reduced.
  • the thermal expansion coefficient of SiO 2 is smaller than that of SiC, that is, when the substrate is a SiC substrate, SiO 2 can be used as the stress compensation layer of the SiC substrate, thereby realizing the common use of SiO 2 as the stress compensation layer for various substrates. , reducing the cost of the stress compensation layer.
  • a GaN layer is epitaxially grown on the front surface of the Si substrate at a second temperature, where the second temperature is greater than the first temperature.
  • the stress compensation layer will exert a stress on the Si substrate.
  • the ratio of the thickness of the stress compensation layer to the thickness of the Si substrate the stress will manifest differently.
  • the stress compensation layer is smaller than the thermal expansion coefficient of the Si substrate, and the ratio of the thickness of the stress compensation layer to the thickness of the Si substrate is smaller than the threshold value, the stress manifests as applying tensile stress to part of the Si substrate, and to another part of the Si substrate.
  • the bottom applies compressive stress, that is, the backside of the Si substrate is subjected to compressive stress, and the front surface of the Si substrate is subjected to tensile stress.
  • 5b is another structural schematic diagram of the GaN device at the second temperature.
  • FIG. 6 is a schematic diagram of a force of a GaN device in an embodiment of the present application.
  • the ratio of the thickness d1 of the stress compensation layer 402 to the thickness d2 of the Si substrate is smaller than the threshold value, and the thermal expansion coefficient of the stress compensation layer 402 is smaller than that of the Si substrate.
  • the stress compensation layer 402 After rising from the first temperature to the second temperature, the stress compensation layer 402 applies a compressive stress to the region 401b in the Si substrate.
  • the region 401b is subjected to compressive stress, while the region 401a will instead generate tensile stress due to the action of the internal force.
  • the stress compensation layer 402 should be subjected to tensile stress.
  • the stress compensation layer is greater than the thermal expansion coefficient of the Si substrate, and the ratio of the thickness of the stress compensation layer to the thickness of the Si substrate is greater than the threshold, the stress is expressed as a tensile stress on the entire Si substrate, that is, the Si substrate’s Both the front and the back are subject to tensile stress.
  • 7b is a schematic structural diagram of the GaN device at the second temperature. Because the thermal expansion coefficient of the stress compensation layer is greater than that of the Si substrate, the stress compensation layer exerts a compressive stress on the Si substrate, so the GaN device warps in the positive direction of the vertical direction. In order to facilitate understanding of the stress on the Si substrate, 7b is described in more detail below.
  • FIG. 8 is another schematic diagram of stress of the GaN device in the embodiment of the present application.
  • the ratio of the thickness d1 of the stress compensation layer 802 to the thickness d2 of the Si substrate 801 is greater than the threshold value, and the thermal expansion coefficient of the stress compensation layer 802 is greater than that of the Si substrate 801 .
  • the stress compensation layer 802 After rising from the first temperature to the second temperature, the stress compensation layer 802 applies a compressive stress to the Si substrate 801 .
  • the stress compensation layer 802 should be subjected to a tensile stress applied by the Si substrate.
  • the threshold is described below.
  • the threshold value is related to the material of the stress compensation layer and the substrate, and also related to the length of the two in the horizontal direction. Under the condition that the materials of both the stress compensation layer and the substrate, and the length of the GaN device along the horizontal direction are not limited, the embodiments of the present application do not specifically limit the threshold value. According to the relationship between the ratio of the thickness of the stress compensation layer and the substrate and the threshold value, the embodiments of the present application describe two states, and the situation where the Si substrate is stressed in different states. In particular, referring to FIG.
  • the size of the thickness d1 of the stress compensation layer 402 can be adjusted by adjusting the thickness d1 of the stress compensation layer 402. , the thickness of the tensile stress region 401a and the compressive stress region 402b can be varied.
  • increasing the thickness d1 of the stress compensation layer 402 can make the thickness of the region 401a larger and the thickness of the region 401b smaller; and decreasing the thickness d1 of the S stress compensation layer 402 can make the thickness of the region 401b smaller, and the region The thickness of 401a becomes larger, and the thickness of region 401a approaches d2.
  • the ratio of the thickness of the region 401a to d2 in the embodiment of the present application is defined as: Considering the influence of the thickness of the stress compensation layer or the control of the thickness of the substrate on the ratio in practical applications, it is allowed to use the ratio fluctuates on the basis of
  • 5c and 7c are respectively a schematic structural diagram of a GaN device after epitaxially growing a GaN layer on the front side of the Si substrate at the second temperature.
  • 5c includes GaN layer 501
  • 7c includes GaN layer 701
  • the difference between 5c and 7c is that in 5c the front side of Si substrate 502 is warped in the negative direction of the vertical direction, and in 7c the front side of the Si substrate 702 is warped in the positive direction of the vertical direction warping.
  • a GaN layer is epitaxially grown on the front side of the substrate using a two-step growth method or lateral epitaxy.
  • the two-step growth method is to first grow the GaN nucleation layer at a low temperature, and then grow GaN at a high temperature, thereby improving the crystal quality of GaN and reducing the dislocation density.
  • Lateral epitaxy refers to the use of masks to introduce lateral growth to improve GaN crystal quality and reduce dislocation density.
  • Two-step growth method or lateral epitaxy is a method of epitaxial growth, and the use of this method will produce corresponding risks. In the embodiments of the present application, the risks of using this method are overcome, and corresponding effects can be produced. The following is related to describe.
  • the lattice constant of Si is about 5.43A, and that of GaN is about 3.19A.
  • the substrate is a Si substrate, a buffer layer is included between the Si substrate and the GaN layer, and the lattice constant of the buffer layer is smaller than that of GaN. Since the lattice constant of the buffer layer is smaller than that of GaN, the GaN layer is epitaxially grown on the buffer layer, and the buffer layer will exert a compressive stress on the GaN layer.
  • the compressive stress can be used to offset part or all of the tensile stress, which is the stress exerted by the Si substrate on the GaN layer during cooling due to the difference in thermal expansion coefficients.
  • the two-step growth method or lateral epitaxy can reduce the dislocation density between the buffer layer and the GaN layer, but will reduce or even eliminate this compressive stress, thereby increasing the risk of cracking of the GaN layer.
  • the present application reduces or even cancels the tensile stress exerted by the substrate on the GaN layer by preparing a stress compensation layer on the backside of the Si substrate.
  • the stress compensation layer offsets the tensile stress exerted by the Si substrate on the GaN layer, it can be expressed by the following formula 1: F1 is the tensile stress of the stress compensation layer on the front side of the Si substrate, K is the elastic coefficient of the Si substrate, D2 is the third temperature, D1 is the first temperature, ⁇ 1 is the thermal expansion coefficient of GaN, and ⁇ 2 is the thermal expansion of the Si substrate coefficient.
  • the buffer layer applies a stress Y to the GaN layer. If the stress compensation layer needs to offset the tensile stress exerted by the Si substrate on the GaN layer according to the above formula 1, because of the existence of the stress Y, F1 needs to be adjusted up and down. If the lattice constant of the buffer layer is greater than that of GaN, the stress Y is tensile stress, and F1 needs to be increased; if the lattice constant of the buffer layer is smaller than that of GaN, the stress Y is compressive stress, and F1 needs to be decreased. If there is no buffer layer between the Si substrate and the GaN layer, the above stress Y can be understood as the stress exerted by the Si substrate on the GaN layer.
  • the stress reduction and dislocation density decoupling are achieved by preparing the stress compensation layer.
  • the stress compensation layer is responsible for reducing the stress
  • the epitaxial growth method is responsible for reducing the dislocation density, so that the two-step growth method or lateral epitaxy can not be used without worrying about the stress problem. Therefore, reducing or even eliminating the stress Y by the two-step growth method or lateral epitaxy not only does not increase the risk of cracking of the GaN layer, but also reduces or even eliminates the influence of the stress Y on Equation 1, which is convenient to determine F1, which can then be derived from F1 Thickness and thermal expansion coefficient of the stress compensation layer.
  • the structural schematic diagrams of the GaN device after cooling are shown in 5d in FIG. 5 and 7d in FIG. 7 .
  • the length of the front surface of the Si substrate in the horizontal direction becomes longer.
  • the length of the front side of the Si substrate is h2
  • the length of the front side of the Si substrate is h2+j, Both h2 and j are positive numbers.
  • the length of the front side of the Si substrate should be the same after dropping from the second temperature to the first temperature. Therefore, it is assumed that at the first temperature, the front side of the Si substrate has the same length. The length is h1.
  • the shrinkage amount of the front surface of the Si substrate is h2-h1.
  • the shrinkage amount of the front side of the Si substrate is (h2+j)-h1.
  • the amount of shrinkage of the front surface of the Si substrate is increased by introducing tensile stress on the front surface of the Si substrate. Since the thermal expansion coefficient of GaN is greater than that of Si, the shrinkage amount of the GaN layer should be larger than that of the Si substrate.
  • increasing the shrinkage on the front side of the Si substrate can reduce or even eliminate the difference between the two shrinkages, thereby reducing or even eliminating the tensile stress exerted by the Si substrate on the GaN layer. Reduce the phenomenon of GaN layer cracking.
  • the stress compensation layer does not prevent current flow between the GaN layer and the Si substrate, preparing for the fabrication of vertical GaN devices.
  • the shrinkage of the GaN layer should be greater than that of the Si substrate, assuming that the shrinkage of the GaN layer is (h2-h1)+g.
  • the use temperature of the GaN device is lower than the first temperature
  • the embodiment of the present application defines that j is greater than g.
  • the temperature of the GaN device on the mounting equipment should be considered without considering other forces, such as the stress on the Si substrate and GaN during epitaxial growth due to the difference in lattice constants. This temperature is generally room temperature.
  • the first temperature is generally 300 degrees.
  • the GaN device is lowered from the second temperature to room temperature, and the Si substrate still produces partial tensile stress to the GaN layer. Therefore, by defining that j is greater than g, the difference between j and g is used as the compensation for the difference between the first temperature and the room temperature.
  • step 403 after the GaN layer is epitaxially grown on the front side of the Si substrate, the stress compensation layer is removed.
  • the stress compensation layer After epitaxial growth of the GaN layer on the front side of the substrate, the stress compensation layer is removed.
  • the function of the stress compensation layer is to provide tensile stress on the front surface of the substrate when the GaN layer is epitaxially grown.
  • the stress compensation layer can be removed to reduce the thickness of the GaN device.
  • the stress compensation layer is removed, the third temperature is less than the second temperature, the third temperature is less than the first temperature, and the difference between the third temperature and the first temperature is less than 500 degrees.
  • the present application defines the third temperature, and the third temperature is generally room temperature.
  • the stress compensation layer is removed by mechanical grinding.
  • mechanical grinding in the processing flow of GaN devices, there is generally a process of mechanical grinding, which is used to reduce the overall thickness of the chip.
  • the stress compensation layer in the process of mechanical grinding, only one process of preparing the stress compensation layer can be added without adding a process of removing the stress compensation layer, thereby reducing the increase of processes and reducing the production cost. It should be determined that heat is generated on the stress compensation layer during mechanical grinding. Therefore, when the stress compensation layer is removed at the third temperature, the third temperature does not refer to the temperature on the stress compensation layer during mechanical grinding, but refers to the temperature of the space where the mechanical grinding equipment is located.
  • a buffer layer is prepared on the front side of the Si substrate before epitaxially growing the GaN layer on the front side of the Si substrate.
  • the buffer layer is used to prevent the alloying reaction between the GaN layer and the Si substrate.
  • the lattice constant of the buffer layer must be smaller than that of GaN, so that the buffer layer can reduce the tensile stress on the GaN layer.
  • the stress compensation layer undertakes the function of reducing stress, and the buffer layer may not need to undertake the function of reducing stress, so the lattice constant of the buffer layer does not need to be smaller than that of GaN.
  • the range of material choices for the buffer layer is increased, providing conditions for a material that is lower in cost and/or does not block the vertical flow of current in the GaN device as a buffer layer. Further, the number of buffer layers is one. Without the need for the interaction of multiple buffer layers, the tensile stress experienced by the GaN layer is reduced layer by layer.
  • FIG. 9 is a schematic structural diagram of a GaN device in an embodiment of the present application.
  • the GaN device includes: a substrate 902;
  • the stress compensation layer 903 is formed on the back of the substrate 902;
  • the GaN layer 901 is formed on the front surface of the substrate 902 .
  • the device further includes:
  • the AlGaN layer is formed on the front surface of the GaN layer 901 .
  • the device further includes:
  • a source electrode, a drain electrode and a gate electrode are formed on the front side of the AlGaN layer.
  • the material selection and thickness of the stress compensation layer 903 and the substrate 902 satisfy the following conditions:
  • the ratio of the thickness of the stress compensation layer 903 to the thickness of the substrate 902 is smaller than a preset threshold, and the thermal expansion coefficient of the stress compensation layer 903 is smaller than the thermal expansion coefficient of the substrate 902; or, the stress compensation layer
  • the ratio of the thickness of 903 to the thickness of the substrate 902 is greater than a preset threshold, and the thermal expansion coefficient of the stress compensation layer 903 is greater than the thermal expansion coefficient of the substrate 902 .
  • the thickness of the stress compensation layer 903 is 5um to 70um.
  • the substrate 903 is a Si substrate, and the material of the stress compensation layer 902 is SiO 2 .
  • a buffer layer is further included between the substrate 902 and the GaN layer 901.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: a flash disk, a removable hard disk, a ROM, a RAM, a magnetic disk or an optical disk and other mediums that can store program codes.

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Abstract

本申请公开了一种制备GaN器件的方法，应用于半导体器件领域。方法包括：在衬底的背面生成应力补偿层；在所述衬底的正面外延生长GaN层。本申请通过在衬底的背面制备应力补偿层，使得衬底的正面受到张应力。从而可以降低衬底对GaN层施加的张应力,减少GaN层开裂的现象。

Description

制备GaN器件的方法以及GaN器件 技术领域
本申请涉及半导体器件领域，尤其涉及制备GaN器件的方法以及GaN器件。
背景技术
GaN材料具有禁带宽度大、介电常数低、高电子迁移率和高电子饱和速度等优点，迅速成为了制作大功率和高频率电力电子器件的理想材料。
目前，由于GaN的同质衬底难于制备，GaN材料的外延生长一般都选择异质衬底，例如Si衬底。GaN外延层和Si衬底的晶格常数不同，存在着一定的晶格失配。晶格失配会在GaN材料中引入高密度的位错，晶格失配越大，位错密度往往也就会越大。并且，GaN外延层和Si衬底的热膨胀系数不同，存在着一定的热失配，热失配会使GaN外延层在从生长温度降温至室温时，Si衬底对GaN外延层产生巨大的张应力，其至使得GaN外延层开裂。GaN外延层之所以会产生开裂的现象，最主要的原因就是GaN外延层中的张应力过大，材料无法承受这样的张应变。为了减少开裂，在Si衬底和GaN外层之间引入一个缓冲层，该缓冲层的晶格常数比GaN的小，使得缓冲层在GaN外延层的界面处产生压应变，以此来削弱或者消除Si衬底和GaN外延层之间产生的张应变。
若使用可以降低位错密度的方法在缓冲层上外延生长GaN外延层，会降低缓冲层在GaN外延层的界面处产生的压应变，导致Si衬底和GaN外延层之间产生的张应变无法被削弱，以致GaN外延层开裂。
发明内容
本申请提供了一种制备GaN器件的方法以及GaN器件，可以减少GaN层开裂的现象。
本申请第一方面提供了一种制备GaN器件的方法。
该方法包括在衬底的背面生成应力补偿层；在所衬底的正面外延生长GaN层。应力补偿层的热膨胀系数和衬底的热膨胀系数不同，即应力补偿层的热膨胀系数可以大于衬底的热膨胀系数，也可以小于衬底的热膨胀系数。因为应力补偿层的热膨胀系数和衬底的热膨胀系数不同，应力补偿层会对衬底施加一个应力。通过设置应力补偿层的厚度和衬底的厚度的比值，该应力会有不同的表现。若应力补偿层的热膨胀系数大于衬底的热膨胀系数，应力补偿层的厚度和衬底的厚度的比值较大，则该应力表现为对整个衬底的张应力，即衬底的正面和背面都受到张应力。若应力补偿层的热膨胀系数小于衬底的热膨胀系数，应力补偿层的厚度和衬底的厚度的比值较小，则该应力表现为对部分衬底施加张应力，对另一部分衬底施加压应力，即衬底的背面受到压应力，衬底的正面受到张应力。
本申请通过在衬底的背面制备应力补偿层，使得衬底的正面受到张应力。从而降低衬底对GaN层施加的张应力,减少GaN层开裂的现象。
在一种可能的实施方式中，所述方法还包括：在所述GaN层上生成AlGaN层。
在一种可能的实施方式中，方法还包括：在所述AlGaN层上形成源极、漏极和栅极。
在一种可能的实施方式中，应力补偿层和衬底的材料选择和厚度满足下述条件：
所述应力补偿层的厚度和所述衬底的厚度的比值小于预设的阈值，所述应力补偿层的热膨胀系数小于所述衬底的热膨胀系数；或者，所述应力补偿层的厚度和所述衬底的厚度的比值大于预设的阈值，所述应力补偿层的热膨胀系数大于所述衬底的热膨胀系数。
在一种可能的实施方式中，所述应力补偿层的厚度为5um至70um。
在一种可能的实施方式中，所述衬底是硅衬底，所述应力补偿层的材料为SiO 2。其中，SiO 2的热膨胀系数小于Si的热膨胀系数，且SiO 2耐高温。进一步地，相比于SiN，SiO 2更容易被腐蚀，若后续需要去除应力补偿层，则可以降低去除应力补偿层的成本。进一步地，SiO 2的热膨胀系数小于SiC的热膨胀系数，即当衬底为SiC衬底时，SiO 2可以作为SiC衬底的应力补偿层，从而实现多种衬底共同使用SiO 2作为应力补偿层，降低应力补偿层的成本。
在一种可能的实施方式中，使用两步生长法或侧向外延在所述衬底的正面外延生长所述GaN层。Si的晶格常数约为5.43A，GaN的晶格常数约为3.19A。现有技术中，假设衬底为Si衬底，Si衬底和GaN层之间包括缓冲层，缓冲层的晶格常数小于GaN的晶格常数。因为缓冲层的晶格常数小于GaN的晶格常数，在缓冲层上外延生长GaN层，缓冲层会对GaN层施加一个压应力。该压应力可用于抵消部分或全部的张应力，该张应力为由于热膨胀系数的差异，在降温时Si衬底对GaN层施加的应力。通过抵消部分或全部的张应力，可以降低GaN层开裂的风险。因此，该压应力是有益的。两步生长法或侧向外延可以降低缓冲层和GaN层之间的位错密度，但是会降低甚至消除该压应力，从而增加GaN层开裂的风险。
本申请通过在衬底的背面制备应力补偿层，来降低甚至抵消衬底对GaN层施加的张应力。当应力补偿层抵消衬底对GaN层施加的张应力时，可以用下列公式1来表示：
Figure PCTCN2020102404-appb-000001
F1为应力补偿层对衬底的正面的张应力，K为衬底的弹性系数，D2为第三温度，D1为第一温度，α1为GaN的热膨胀系数，α2为衬底的热膨胀系数。存在缓冲层的情况下，因为缓冲层的晶格常数与GaN的晶格常数不同，缓冲层会对GaN层施加一个应力Y。若需要按照上述公式1，使得应力补偿层抵消衬底对GaN层施加的张应力，则因为应力Y的存在，需要上下调整F1。若缓冲层的晶格常数大于GaN的晶格常数，应力Y为张应力，需要上调F1；若缓冲层的晶格常数小于GaN的晶格常数，应力Y为压应力，需要下调F1。若衬底和GaN层之间没有缓冲层，则上述应力Y可以理解为衬底对GaN层施加的应力。
在本申请中，通过制备应力补偿层，实现降低应力和降低位错密度解耦。应力补偿层负责降低应力，外延生长方法负责降低位错密度，从而可以不用担心应力问题而无法使用两步生长法或侧向外延。因此，通过两步生长法或侧向外延来降低甚至消除应力Y，不仅不会增加GaN层开裂的风险，还可以降低甚至消除应力Y对公式1的影响，方便确定F1，进而可以通过F1推导应力补偿层的厚度和热膨胀系数。
在一种可能的实施方式中，在第一温度下，在所述衬底的背面生成所述应力补偿层；
在第二温度下，在所述衬底的背面生成所述应力补偿层，所述第二温度大于所述第二温度。
在一种可能的实施方式中，在所述衬底的正面外延生长所述GaN层后，所述方法还把包括：去除所述应力补偿层。其中，应力补偿层的功能是在外延生长GaN层时，在衬底的正面提供张应力。在完成外延生长GaN层后，去除应力补偿层，可以降低GaN器件的厚度。
在一种可能的实施方式中，在第三温度下，去除所述应力补偿层，所述第三温度小于所述第二温度，所述第三温度小于所述第一温度，所述第三温度和所述第一温度的差值小于500度。其中，本申请对第三温度进了限定，第三温度一般为室温。通过在室温下去除应力补偿层，降低去除应力补偿层的成本。
在一种可能的实施方式中，通过机械研磨去除所述应力补偿层。其中，在GaN器件的加工流程中，一般会有机械研磨的工序。本申请通过在机械研磨这个工序中去除应力补偿层，可以只增加一个制备应力补偿层的工序，而无需增加去除应力补偿层的工序，从而减少工序的增加，减少生产成本。
在一种可能的实施方式中，在所述衬底和所述GaN层之间，还包括缓冲层，所述缓冲层用于阻止所述GaN层和所述衬底发生合金反应。其中，缓冲层用于阻止GaN层和衬底发生合金反应。其中，在现有技术中，缓冲层的晶格常数一定要小于GaN的晶格常数，缓冲层才有降低GaN层受到的张应力的作用。在本申请中，应力补偿层承担降低应力的功能，缓冲层可以不需要承担降低应力的功能，因此缓冲层的晶格常数可以无需小于GaN的晶格常数。增加了缓冲层对材料选择的范围，为成本更低，和/或不阻断GaN器件中的电流垂直流动的材料作为缓冲层提供了条件。
本申请第二方面提供了一种GaN器件。
该GaN器件包括：衬底；
应力补偿层，形成于所述衬底的背部；
GaN层，形成于所述衬底的正面。
在一种可能的实施方式中，所述器件还包括：
AlGaN层，形成于所述GaN层的正面。
在一种可能的实施方式中，所述器件还包括：
源区、漏区和栅区，形成于所述AlGaN层的正面。
在一种可能的实施方式中，所述应力补偿层和所述衬底的材料选择和厚度满足下述条件：
所述应力补偿层的厚度和所述衬底的厚度的比值小于预设的阈值，所述应力补偿层的热膨胀系数小于所述衬底的热膨胀系数；或者，所述应力补偿层的厚度和所述衬底的厚度的比值大于预设的阈值，所述应力补偿层的热膨胀系数大于所述衬底的热膨胀系数。
在一种可能的实施方式中，所述应力补偿层的厚度为5um至70um。
在一种可能的实施方式中，所述衬底为Si衬底，所述应力补偿层的材料为SiO 2。
在一种可能的实施方式中，在所述衬底和所述GaN层之间，还包括缓冲层。关于对本申请第二方面，或第二方面任意一种实施方式的有益效果的描述，可以参考前述对第一方面，或第一方面任意一种实施方式的有益效果的描述。
附图说明
图1为GaN基HEMT的结构示意图；
图2为GaN器件发生翘曲的示意图；
图3为通过增加缓冲层的方式减少张应力的GaN器件的示意图；
图4为本申请实施例中的在GaN器件中减少张应力的方法的流程示意图；
图5为本申请实施例中，厚度比值小于阈值时，GaN器件在制备流程中的结构示意图；
图6为本申请实施例中，GaN器件的一个受力示意图；
图7为本申请实施例中，厚度比值大于阈值时，GaN器件在制备流程中的结构示意图；
图8为本申请实施例中，GaN器件的另一个受力示意图；
图9为本申请实施例中GaN器件的一个结构示意图。
具体实施方式
本申请实施例提供了一种制备GaN器件的方法以及GaN器件,应用于半导体器件领域，可以减少GaN器件中GaN层开裂的现象。
为了方便理解本申请中的技术方案，下面对技术方案中的相关背景技术进行描述。
外延生长，从广义上说,外延生长也属于一种薄膜淀积技术。顾名思义，外延就是“向外延伸"。这是一种特殊的薄膜生长，特指在单晶衬底上生长一层新的单晶，即在一定条件下，在制备好的单晶衬底上，沿其原来晶体的结晶轴方向，生长一层导电类型，电阻率，厚度等都符合要求的新单晶层，称为外延层。外延层除了结晶方向与衬底单晶一致外，其他特性均可自主选择，如导电类型，电阻率，厚度等都可以按照新的要求生长。根据外延层与衬底的材料是否相同，可以将外延分为同质外延和异质外延，若两者材料相同，即为同质外延，反之则为异质外延。
GaN材料具有禁带宽度大，介电常数低，高电子迁移率和高电子饱和速度等优点，迅速成为了制作大功率和高频率电力电子器件的理想材料。在衬底上外延生长GaN材料的外延层，是制作GaN电子器件(简称GaN器件)的基础。GaN器件包括异质结场效应晶体管(heterojunction field effect transistor，HFET)，半导体场效应晶体管(metal oxide semiconductor filed effect transistor，MOSFET)，高电子迁移率晶体管(high electron mobility transistor,HEMT)等。如图1所示，图1为GaN基HEMT的结构示意图。沿垂直方向，分别包括衬底102，GaN层101和ALAlGaN层103。其中，衬底102的正面与GaN层101相邻，衬底102的正面是指衬底102朝向垂直方向正方向的面。在本申请实施例的后续描述中，都将沿用对GaN器件水平方向，垂直方向和正面的定义。应当确定的是，图1只是GaN基HEMT的一个结构示意图，在GaN基HEMT的实际结构中，还可以包括其它的层。例如在AlGaN层103的正面还包括GaN层。AlGaN层103的正面是指AlGaN层103朝向垂直方向正方向的面。
晶格失配，晶格失配是指在外延生长中，衬底和外延层的晶格常数不同而产生的失配现象。当在某种单晶衬底上生长另一种物质的单晶层时,由于这两种物质的晶格常数不同,会在生长界面附近产生应力,进而产生晶体缺陷——位错。位错在材料科学中，指晶体材料 的一种内部微观缺陷，即原子的局部不规则排列(晶体学缺陷)。从几何角度看，位错属于一种线缺陷，可视为晶体中已滑移部分与未滑移部分的分界线，其存在对材料的物理性能，具有极大的影响。位错密度定义为单位体积晶体中所含的分界线的总长度。位错密度可用于形容晶格失配产生的位错的程度。
热失配，即热膨胀失配。在外延生长中，衬底和外延层的热膨胀系数不同而产生的失配现象。通常GaN器件需要在高温下外延生长外延层，简称外延生长温度。GaN器件的使用的温度一般为室温，室温与外延生长温度存在差异。并且，衬底和外延层的热膨胀系数不同，在从外延生长温度降到室温后，衬底和外延层之间存在应力。
本申请实施例中的制备GaN器件的方法用于制备GaN器件的过程，具体地，用于在衬底上外延生长GaN的过程。衬底可以是Si衬底，SiC衬底等。Si衬底是指由Si单质组成的衬底，SiC衬底是由化合物SiC组成的衬底。应当确定的是，上述Si衬底和SiC衬底可能包含部分杂质。为了方便阐述，下面都将以Si衬底作为衬底进行相关描述。
GaN的晶体结构包括六方纤锌矿或闪锌矿结构。其中以六方晶系的纤锌矿结晶最为稳定，而Si材料是立方金刚石结构。并且在Si衬底外延生长GaN外延层有以下困难：首先，由于GaN外延层和Si衬底之间存在较大的晶格失配，这会造成GaN外延层中的位错密度较大，当GaN层和Si衬底的位错密度较大时，会影响GaN器件的性能。并且，GaN的晶格常数小于Si的晶格常数，在Si衬底上外延生长GaN层时，Si衬底会对GaN层施加一个张应力。其次，GaN和Si之间巨大的热膨胀系数差异，会使GaN层在从外延生长温度降温至室温的过程中，Si衬底对GaN层产生巨大的张应力，使得GaN器件发生翘曲。受到上述两个张应力的影响，当GaN层承受不住张应力的拉扯时，GaN层会发生开裂，无法达到制作器件的要求，影响GaN层的质量和性能。如图2所示，图2为GaN器件发生翘曲的示意图，其中，2b为在高温下外延生长GaN层201后GaN器件的示意图，此时，GaN层201和Si衬底202理论上呈水平状；2a为在室温下GaN器件发生翘曲的示意图，此时，受到上述两个张应力的作用，Si衬底202和GaN层201沿GaN器件的垂直方向的正方向上发生翘曲。若翘曲比较严重，也可能导致GaN层201产生裂纹，GaN层201产生裂纹是指在GaN层201的正面，发生开裂现象。
为了减少GaN层开裂，就需要减少GaN层受到的张应力，简称减少张应力。请参阅图3，图3为通过增加缓冲层的方式减少张应力的GaN器件的示意图。3b为在高温下外延生长缓冲层303和GaN层301后GaN器件的结构示意图，此时，GaN层301，Si衬底302，缓冲层303理论上呈水平状。因为缓冲层303的晶格常数小于GaN层301的晶格常数，在外延生长GaN层301的过程中，缓冲层303会对GaN层301施加一个压应力。该压应力可以减少或抵消因为热失配，降温过程中GaN层301受到的张应力。因此，如3a所示，3a为在室温下GaN器件的结构示意图。在室温下，GaN层301可以减少受到的张应力，因此GaN层301可以减少翘曲的程度，图示为理论上完全消除张应力的示意图。在没有采用降低位错密度的技术手段时，通过增加缓冲层，可以降低GaN层受到的张应力，但是为了提高GaN器件的质量，也需要降低GaN层和Si衬底之间的位错密度。在采用降低位错密度的技术手段时，无法有效降低GaN层受到的张应力。
通过上面描述可知，缓冲层需要利用晶格失配对GaN层产生压应力，但降低位错密度效率较低。通过二步生长法或侧向外延可以降低位错密度，但是会降低对GaN层产生的压应力，从而加大了热失配导致开裂。即在Si衬底上GaN外延生长中，减少GaN层受到的张应力和降低位错密度两个目标相互交织，目前方法不能同时达到两方面的目标。本申请实施例提供了一种制备GaN器件的方法，可以减少GaN器件中的GaN层受到的张应力。并且，该方法拥有以下好处。首先，该方法可以实现减少GaN层受到的张应力和降低位错密度相互解耦，不需要通过降低一个目标的效果，来提升另外一个目标的效果。其次，该方法与增加缓冲层的方法兼容，可以共同作用。下面将对本申请实施例提供的制备GaN器件的方法进行详细描述。示例性地，本申请实施例所涉及附图中的以虚线标识的特征或内容可理解为实施例可选的操作或可选的结构。
请参阅图4，图4为本申请实施例中制备GaN器件的方法的流程示意图。
在步骤401中，在第一温度下，在Si衬底的背面制备应力补偿层，所述应力补偿层的热膨胀系数和Si衬底的热膨胀系数不同。
Si衬底的正面是指外延生长GaN层的一面，Si衬底的背面指外延生长GaN层的那一面的对面。
应力补偿层的热膨胀系数和Si衬底的热膨胀系数不同，即应力补偿层的热膨胀系数可以大于Si衬底的热膨胀系数，也可以小于Si衬底的热膨胀系数。应力补偿层和Si衬底的热膨胀系数的相对大小取决于应力补偿层和Si衬底的厚度相对大小。当应力补偿层和Si衬底的厚度的比值大于阈值时，应力补偿层的热膨胀系数大于Si衬底的热膨胀系数，为了方便描述，下面将应力补偿层和Si衬底的厚度的比值称为厚度比值；当厚度比值小于阈值时，应力补偿层的热膨胀系数小于Si衬底的热膨胀系数。如图5中的5a和图7中的7a所示。图5为本申请实施例中，厚度比值小于阈值时，GaN器件在制备流程中的结构示意图。图7为本申请实施例中，厚度比值大于阈值时，GaN器件在制备流程中的结构示意图。5a和7a为在Si衬底背面制备应力补偿层后的GaN器件的结构示意图。5a中的GaN器件沿垂直方向依次包括Si衬底502，应力补偿层503。7a中的GaN器件沿垂直方向依次包括Si衬底702，应力补偿层703。
可选地，使用等离子体增强化学气相沉积法(plasma enhanced chemical vapor deposition，PECVD)，或低压力化学气相沉积法(low pressure chemical vapor deposition，LPCVD)，或溅射在Si衬底的背面制备应力补偿层。在增加缓冲层的方法中，因为缓冲层承担着联结Si衬底和GaN层的作用，需要有较好的外延生长质量，所以需要外延生长缓冲层需要采用金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)设备，而MOCVD设备一般比较昂贵。本申请实施例中的应力补偿层可以只需要承担减少GaN层受到的张应力的作用，因此，可以降低应用补偿层的外延生长质量。采用PECVD设备，或LPCVD设备，或溅射设备可以有效的降低设备成本。并且，在外延生长相同厚度的外延层的情况下，MOCVD设备需要花费更多的时间，因此本申请实施例采用PECVD设备，或LPCVD设备，或溅射设备可以有效的降低时间成本。
可选地，应力补偿层的厚度和Si衬底的厚度的比值小于阈值，应力补偿层的热膨胀系 数小于Si衬底的热膨胀系数。应力补偿层的功能是在Si衬底的正面提供张应力，可以不需要承担电流载荷的功能。因此应力补偿层的厚度不会影响Si衬底的厚度，即在满足原有设计要求的情况下，可以假设Si衬底的厚度是固定的。其中，原有设计要求是指在不包括应力补偿层的情况下，GaN器件对Si衬底的厚度的设计要求。在Si衬底的厚度是固定的情况下，需要设计GaN器件中应力补偿层的厚度。本申请限定了应力补偿层的厚度和Si衬底的厚度的比值小于阈值。在此限定下，可以减少减少生成应力补偿层的时间。
可选地，应力补偿层的厚度为5um至70um。其中，通过衬底在实际应用中的厚度，限定应力补偿层的厚度为5um至70um。
可选地，应力补偿层的材料是SiN。
可选地，衬底为Si衬底，应力补偿层的材料可以是SiO 2。其中，SiO 2的热膨胀系数小于Si的热膨胀系数，且SiO 2耐高温，SiO 2的熔点为1650度。在外延生长GaN的过程中，外延生长温度一般为800度，在此温度下，SiO 2不会因此融化。进一步地，相比于SiN，SiO 2因为更容易被腐蚀，所以更容易被去除，因此可以降低去除应力补偿层的成本。进一步地，SiO 2的热膨胀系数小于SiC的热膨胀系数，即当衬底为SiC衬底时，SiO 2可以作为SiC衬底的应力补偿层，从而实现多种衬底共同使用SiO 2作为应力补偿层，降低应力补偿层的成本。
在步骤402中，在制备应力补偿层后，在第二温度下，在Si衬底的正面外延生长GaN层，第二温度大于第一温度。
从第一温度升到第二温度，因为应力补偿层的热膨胀系数和Si衬底的热膨胀系数不同，应力补偿层会对Si衬底施加一个应力。通过设置应力补偿层的厚度和Si衬底的厚度的比值，该应力会有不同的表现。下面分别进行相应描述。
若应力补偿层的热膨胀系数小于Si衬底的热膨胀系数，应力补偿层的厚度和Si衬底的厚度的比值小于阈值，则该应力表现为对部分Si衬底施加张应力，对另一部分Si衬底施加压应力，即Si衬底的背面受到压应力，Si衬底的正面受到张应力。请参阅图5中的5b，5b为在第二温度下，GaN器件的另一个结构示意图。因为应力补偿层的热膨胀系数小于Si衬底的热膨胀系数，Si衬底对应力补偿层施加一个压应力，所以GaN器件往垂直方向的负方向翘曲。为了方便理解Si衬底受到的应力情况，下面对5b进行更为详细的描述。请参阅图6，图6为本申请实施例中，GaN器件的一个受力示意图。在图6中，应力补偿层402的厚度d1和Si衬底的厚度d2的比值小于阈值，应力补偿层402的热膨胀系数小于Si衬底的热膨胀系数。从第一温度升到第二温度后，应力补偿层402对Si衬底中的区域401b施加一个压应力。区域401b受压应力，区域401a反而会因为内力的作用产生张应力。虽然图中并未描述，应力补偿层402应当受到张应力。
若应力补偿层的热膨胀系数大于Si衬底的热膨胀系数，应力补偿层的厚度和Si衬底的厚度的比值大于阈值，则该应力表现为对整个Si衬底的张应力，即Si衬底的正面和背面都受到张应力。请参阅图7中的7b，7b为在第二温度下，GaN器件的一个结构示意图。因为应力补偿层的热膨胀系数大于Si衬底的热膨胀系数，应力补偿层对Si衬底施加一个压应力，所以GaN器件往垂直方向的正方向翘曲。为了方便理解Si衬底受到的应力情况，下面对7b进行更为详细的描述。请参阅图8，图8为本申请实施例中，GaN器件的另一个 受力示意图。在图8中，应力补偿层802的厚度d1和Si衬底801的厚度d2的比值大于阈值，应力补偿层802的热膨胀系数大于Si衬底801的热膨胀系数。从第一温度升到第二温度后，应力补偿层802对Si衬底801施加一个压应力。虽然图中并未描述，应力补偿层802应当受到Si衬底施加的一个张应力。
下面对阈值做一个相关描述。阈值跟应力补偿层，衬底的材料相关，并且，还与两者沿水平方向的长度相关。在未限定应力补偿层和衬底两者的材料，以及GaN器件沿水平方向的长度的情况下，本申请实施例并不对阈值进行具体的限定。本申请实施例通过应力补偿层和衬底的厚度的比值与阈值的关系，阐述了两种状态，以及在不同状态下，Si衬底受力的情况。特别地，请参阅图6，当应力补偿层402的厚度d1和Si衬底的厚度d2的比值小于阈值时，若Si衬底的厚度d2不变，通过调节应力补偿层402的厚度d1的大小，可以改变受张应力的区域401a和受压应力的区域402b的厚度。具体地，调大应力补偿层402的厚度d1，可以使得区域401a的厚度变大，区域401b的厚度变小；调小S应力补偿层402的厚度d1，可以使得区域401b的厚度变小，区域401a的厚度变大，并且区域401a的厚度逼近d2。
可选地，为了保证Si衬底的正面受到张应力，以及应力补偿层的厚度不会太大，本申请实施例限定区域401a的厚度和d2的比值为
Figure PCTCN2020102404-appb-000002
考虑到实际应用中应力补偿层的厚度，或衬底的厚度的控制对该比值的影响，允许在该比值
Figure PCTCN2020102404-appb-000003
的基础上，上下波动
Figure PCTCN2020102404-appb-000004
上面对第二温度下，GaN器件中Si衬底在两种状态下的受力情况进行了相应描述，下面描述在第二温度下，在Si衬底的正面外延生长GaN层。请参阅图5中的5c以及图7中7c。5c和7c分别为在第二温度下，在Si衬底的正面外延生长GaN层后的GaN器件的一个结构示意图。5c包括GaN层501,7c包括GaN层701，5c和7c的区别在于，5c中Si衬底502的正面向垂直方向的负方向翘曲，7c中Si衬底702的正面向垂直方向的正方向翘曲。
可选地，使用两步生长法或侧向外延在衬底的正面外延生长GaN层。两步生长法是先低温生长GaN成核层，再高温生长GaN，从而提高GaN的晶体质量，降低位错密度。侧向外延是指通过使用掩膜引入侧向生长来提高GaN晶体质量，降低位错密度。两步生长法或侧向外延作为外延生长的一种方法，对该方法的使用会产生相应的风险，本申请实施例中克服了使用该方法的风险，并且可以产生相应的效果，下面进行相关描述。
Si的晶格常数约为5.43A，GaN的晶格常数约为3.19A。现有技术中，假设衬底为Si衬底，Si衬底和GaN层之间包括缓冲层，缓冲层的晶格常数小于GaN的晶格常数。因为缓冲层的晶格常数小于GaN的晶格常数，在缓冲层上外延生长GaN层，缓冲层会对GaN层施加一个压应力。该压应力可用于抵消部分或全部的张应力，该张应力为由于热膨胀系数的差异，在降温时Si衬底对GaN层施加的应力。通过抵消部分或全部的张应力，可以降低GaN层开裂的风险。因此，该压应力是有益的。两步生长法或侧向外延可以降低缓冲层和GaN层之间的位错密度，但是会降低甚至消除该压应力，从而增加GaN层开裂的风险。
本申请通过在Si衬底的背面制备应力补偿层，来降低甚至抵消衬底对GaN层施加的张应力。当应力补偿层抵消Si衬底对GaN层施加的张应力时，可以用下列公式1来表示：
Figure PCTCN2020102404-appb-000005
F1为应力补偿层对Si衬底的正面的张应力，K为Si衬底的弹性系数，D2为第三温度，D1为第一温度，α1为GaN的热膨胀系数，α2为Si衬 底的热膨胀系数。存在缓冲层的情况下，因为缓冲层的晶格常数与GaN的晶格常数不同，缓冲层会对GaN层施加一个应力Y。若需要按照上述公式1，使得应力补偿层抵消Si衬底对GaN层施加的张应力，则因为应力Y的存在，需要上下调整F1。若缓冲层的晶格常数大于GaN的晶格常数，应力Y为张应力，需要上调F1；若缓冲层的晶格常数小于GaN的晶格常数，应力Y为压应力，需要下调F1。若Si衬底和GaN层之间没有缓冲层，则上述应力Y可以理解为Si衬底对GaN层施加的应力。
在本申请中，通过制备应力补偿层，实现降低应力和降低位错密度解耦。应力补偿层负责降低应力，外延生长方法负责降低位错密度，从而可以不用担心应力问题而无法使用两步生长法或侧向外延。因此，通过两步生长法或侧向外延来降低甚至消除应力Y，不仅不会增加GaN层开裂的风险，还可以降低甚至消除应力Y对公式1的影响，方便确定F1，进而可以通过F1推导应力补偿层的厚度和热膨胀系数。
在Si衬底上外延生长GaN层后，GaN器件降温后的结构示意图如图5中的5d和图7中的7d所示。通过在Si衬底的正面引入张应力，使得Si衬底的正面在水平方向上的长度变长。在第二温度下，假设不在Si衬底的正面引入张应力，Si衬底的正面的长度为h2，在Si衬底的正面引入张应力后，Si衬底的正面的长度为h2+j，h2和j都为正数。不管是否在Si衬底的正面引入张应力，从第二温度降到第一温度后，Si衬底的正面的长度应当都是相同的，因此假设在第一温度下，Si衬底的正面的长度为h1。未在Si衬底的正面引入张应力时，Si衬底的正面的缩变量为h2-h1。在Si衬底的正面引入张应力后，Si衬底的正面的缩变量为(h2+j)-h1。通过上述假设，可知，本申请实施例通过在Si衬底的正面引入张应力，增加了Si衬底的正面的缩变量。因为GaN的热膨胀系数大于Si的热膨胀系数，GaN层的缩变量应当要大于Si衬底的缩变量。在GaN层的缩变量不变的情况下，增加Si衬底的正面的缩变量，便可以减少甚至消除两个缩变量的差值，从而减少甚至消除Si衬底对GaN层施加的张应力，减少GaN层开裂的现象。特别地，应力补偿层不会阻止电流在GaN层和Si衬底之间流动，为制作垂直GaN器件做了相应准备。
可选地，GaN层的缩变量应当大于Si衬底的缩变量，假设GaN层的缩变量为(h2-h1)+g。在GaN器件的使用温度小于第一温度的情况下，本申请实施例限定j大于g。在不考虑其它受力的情况下，例如Si衬底和GaN因为晶格常数的差异而在外延生长过程中的受力，应当要考量GaN器件在安装设备上的温度。该温度一般为室温。当本申请实施例中使用等PECVD，或LPCVD，或溅射在Si衬底的背面制备应力补偿层时，第一温度一般为300度。在j等于g的情况下，GaN器件从第二温度降到室温，Si衬底仍然会对GaN层产生部分张应力。因此，通过限定j大于g，利用j与g的差值作为第一温度和室温的差值补偿。
在步骤403中，在Si衬底的正面外延生长GaN层后，去除应力补偿层。
在衬底的正面外延生长GaN层后，去除应力补偿层。其中，应力补偿层的功能是在外延生长GaN层时，在衬底的正面提供张应力。在完成外延生长GaN层后，去除应力补偿层，可以降低GaN器件的厚度。
可选地，在第三温度下，去除应力补偿层，第三温度小于第二温度，第三温度小于第一温度，第三温度和第一温度的差值小于500度。本申请对第三温度进了限定，第三温度一般为室温。通过在室温下去除应力补偿层，降低去除应力补偿层的成本。
可选地，通过机械研磨去除应力补偿层。其中，在GaN器件的加工流程中，一般会有机械研磨的工序，用于降低芯片整体的厚度。本申请通过在机械研磨这个工序中去除应力补偿层，可以只增加一个制备应力补偿层的工序，而无需增加去除应力补偿层的工序，从而减少工序的增加，减少生产成本。应当确定的是，机械研磨时会在应力补偿层上产生热量。所以当在第三温度下去除应力补偿层时，第三温度并非指机械研磨时应力补偿层上的温度，而是指机械研磨设备所处的空间的温度。
上面对本申请实施中GaN器件的制备流程做了相应描述。特别地，在Si衬底的正面上外延生长GaN层前，在Si衬底的正面制备缓冲层。缓冲层用于阻止GaN层和Si衬底发生合金反应。其中，在现有技术中，缓冲层的晶格常数一定要小于GaN的晶格常数，缓冲层才有降低GaN层受到的张应力的作用。在本申请实施例中，应力补偿层承担降低应力的功能，缓冲层可以不需要承担降低应力的功能，因此缓冲层的晶格常数可以无需小于GaN的晶格常数。增加了缓冲层对材料选择的范围，为成本更低，和/或不阻断GaN器件中的电流沿垂直方向流动的材料作为缓冲层提供了条件。进一步地，缓冲层的层数为1层。不需要多个缓冲层的相互作用，逐层降低GaN层受到的张应力。
上面对本申请实施例中的制备GaN器件的方法进行了描述，下面对本申请实施例中的GaN器件进行相关描述。
请参阅图9，图9为本申请实施例中GaN器件的一个结构示意图。
GaN器件包括：衬底902；
应力补偿层903，形成于所述衬底902的背部；
GaN层901，形成于所述衬底902的正面。
在一种可能的实施方式中，所述器件还包括：
AlGaN层，形成于所述GaN层901的正面。
在一种可能的实施方式中，所述器件还包括：
源极、漏极和栅极，形成于所述AlGaN层的正面。
在一种可能的实施方式中，所述应力补偿层903和所述衬底902的材料选择和厚度满足下述条件：
所述应力补偿层903的厚度和所述衬底902的厚度的比值小于预设的阈值，所述应力补偿层903的热膨胀系数小于所述衬底902的热膨胀系数；或者，所述应力补偿层903的厚度和所述衬底902的厚度的比值大于预设的阈值，所述应力补偿层903的热膨胀系数大于所述衬底902的热膨胀系数。
在一种可能的实施方式中，所述应力补偿层903的厚度为5um至70um。
在一种可能的实施方式中，所述衬底903为Si衬底，所述应力补偿层902的材料为SiO 2。
在一种可能的实施方式中，在所述衬底902和所述GaN层901之间，还包括缓冲层。在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨 论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：闪存盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (19)

  1. 一种制备GaN器件的方法，其特征在于，包括：
    在衬底的背面生成应力补偿层；
    在所述衬底的正面外延生长GaN层。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在所述GaN层上生成AlGaN层。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    在所述AlGaN层上形成源极、漏极和栅极。
  4. 根据权利要求1至3任意一项所述的方法，其特征在于，所述应力补偿层和所述衬底的材料选择和厚度满足下述条件：
    所述应力补偿层的厚度和所述衬底的厚度的比值小于预设的阈值，所述应力补偿层的热膨胀系数小于所述衬底的热膨胀系数；或者，所述应力补偿层的厚度和所述衬底的厚度的比值大于预设的阈值，所述应力补偿层的热膨胀系数大于所述衬底的热膨胀系数。
  5. 根据权利要求1至4任意一项所述的方法，其特征在于，所述应力补偿层的厚度为5um至70um。
  6. 根据权利要求1至5任意一项所述的方法，其特征在于，所述衬底是硅衬底，所述应力补偿层的材料为SiO 2。
  7. 根据权利要求1至6任意一项所述的方法，其特征在于，所述在所述衬底的正面外延生长GaN层包括：
    使用两步生长法或侧向外延在所述衬底的正面外延生长所述GaN层。
  8. 根据权利要求1至7任意一项所述的方法，其特征在于，所述在衬底的背面生成应力补偿层包括：
    在第一温度下，在所述衬底的背面生成所述应力补偿层；
    所述在所述衬底的正面外延生长GaN层包括：
    在第二温度下，在所述衬底的背面生成所述应力补偿层，所述第二温度大于所述第二温度。
  9. 根据权利要求8所述的方法，其特征在于，在所述衬底的正面外延生长所述GaN层后，所述方法还把包括：
    去除所述应力补偿层。
  10. 根据权利要求9所述的方法，其特征在于，所述去除所述应力补偿层包括：
    在第三温度下，去除所述应力补偿层，所述第三温度小于所述第二温度，所述第三温度小于所述第一温度，所述第三温度和所述第一温度的差值小于500度。
  11. 根据权利要求10所述的方法，其特征在于，所述去除所述应力补偿层包括：
    通过机械研磨去除所述应力补偿层。
  12. 根据权利要求1至11任意一项所述的方法，其特征在于，在所述衬底和所述GaN层之间，还包括缓冲层，所述缓冲层用于阻止所述GaN层和所述衬底发生合金反应。
  13. 一种GaN器件，其特征在于，包括：
    衬底；
    应力补偿层，形成于所述衬底的背部；
    GaN层，形成于所述衬底的正面。
  14. 根据权利要求13所述的GaN器件，其特征在于，所述器件还包括：
    AlGaN层，形成于所述GaN层的正面。
  15. 根据权利要求14所述的GaN器件，其特征在于，所述器件还包括：
    源区、漏区和栅区，形成于所述AlGaN层的正面。
  16. 根据权利要求13至15任意一项所述的GaN器件，其特征在于，所述应力补偿层和所述衬底的材料选择和厚度满足下述条件：
    所述应力补偿层的厚度和所述衬底的厚度的比值小于预设的阈值，所述应力补偿层的热膨胀系数小于所述衬底的热膨胀系数；或者，所述应力补偿层的厚度和所述衬底的厚度的比值大于预设的阈值，所述应力补偿层的热膨胀系数大于所述衬底的热膨胀系数。
  17. 根据权利要求16所述的GaN器件，其特征在于，所述应力补偿层的厚度为5um至70um。
  18. 根据权利要求13至17任意一项所述的GaN器件，其特征在于，所述衬底为Si衬底，所述应力补偿层的材料为SiO 2。
  19. 根据权利要求13至18任意一项所述的GaN器件，其特征在于，在所述衬底和所述GaN层之间，还包括缓冲层。
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