WO2022000667A1 - 像素阵列的补偿驱动方法、驱动装置以及显示设备 - Google Patents
像素阵列的补偿驱动方法、驱动装置以及显示设备 Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
Definitions
- the present application belongs to the field of information display, and in particular, relates to a compensation driving method for a pixel array, a driving device and a display device.
- AMOLED is a display screen that uses TFT as the pixel unit circuit array and then makes OLED on it.
- TFT and OLED have burn-in problems after they emit light. For example, an increase in the TFT threshold voltage leads to the same driving signal, but a smaller operating current; similarly, an increase in the OLED threshold voltage also leads to a decrease in the OLED current; for the same current, the OLED emits less light.
- TFT also has the problem of uneven threshold voltage, which will also cause uneven light emission of the display screen.
- the display driving chip of the pixel system itself has the problem of uneven driving of the driving circuits of different driving channels. Therefore, the display driver chip needs to be compensated to make the picture displayed on the display screen relatively uniform, for example, intra-pixel compensation and extra-pixel compensation.
- the existing intra-pixel compensation methods are often suitable for a small number of TFT devices, and are not effective in compensating the luminous efficiency of OLEDs, nor can they compensate for the uneven driving capability of each channel in the display driver chip.
- the present application provides a compensation driving method for a pixel array, wherein the operation time configured for each frame includes a first period and a second period, wherein the first period is the period between two adjacent frames, and the second The period includes at least the time for writing one frame of picture; the method includes: respectively writing correction signals for multiple rows in the pixel array and display signals for each row in the pixel array at different times in the second period, and at different times in the second period. There is no idle time between each write operation; in the second period, the feedback signal of a row is obtained after each correction signal of the row is written; and the row is generated based on the relationship between the feedback signal and the reference signal compensation signal.
- the method further includes writing the correction signal of at least one row in the first period, and acquiring the feedback signal of the row in the first period; and generating based on the relationship between the feedback signal of the row and the reference signal Compensation signal for this row.
- the method further includes compensating the display signal and the correction signal of the corresponding row based on the compensation signal.
- the correction signal for the row is written to the pixel unit of the i-th row, where i is a positive integer less than or equal to K.
- the correction signal for the row is written to the pixel unit of the i+K*g-th row, and the i+K*(g- 1) A feedback signal of a row pixel unit, writing a display signal to the pixel unit in other row times of the gth group, where g is an integer and 1 ⁇ g ⁇ n-1.
- the feedback signal of the pixel unit of the i-th row of the n-th group is obtained, and the feedback signal to the pixel unit of the n-th group of other row times is obtained.
- generating the compensation signal for the row based on the relationship between the feedback signal and the reference signal includes generating aging information based on a comparison result between the feedback signal and the reference signal, and generating aging information for use in the subsequent frame based on the aging information. line compensation signal.
- the second period is correspondingly divided into n+1 groups, and in the first group time of the second period, the correction signal for this row is written to the pixel unit of the i-th row, wherein, i is a positive integer less than or equal to K; the display signals of K lines are written in the remaining time of each group of the second period, and the correction signals and/or output before the other lines except the K lines are written in the other time of the group A set of feedback signals for the lines being corrected in time.
- the present application also provides a driving device for a pixel array, wherein the operation time configured for each frame of pictures includes a first time period and a second time period, wherein the first time period is a time period between two adjacent frames of pictures, The second period includes at least the time to write a frame of pictures;
- the apparatus includes a row driver, coupled to the pixel array, configured to pass a display address line to strobing pixel cells of a specified row based on the display address signal, and to pass a feedback address line to Gating feedback channels of pixel cells of a specified row based on the feedback address signal; a column driver, coupled to the pixel array, configured to write correction signals for a plurality of rows in the pixel array and the pixel array at different times of the second period, respectively.
- each row in the pixel array displays the signal, and there is no idle time between each write operation; and in the second period, the feedback signal of each row is obtained after the correction signal of the row is written; and based on the feedback signal a relationship with the reference signal to generate aging information; and a controller, coupled to the column driver and the row driver, respectively, configured to generate a compensation signal based on the aging information, and to provide the row control signal to the row driver and the column to the column controller A control signal, the compensation signal, and a display signal and a correction signal.
- the column driver is further configured to write the correction signal of at least one row in the first period, and obtain the feedback signal of the row in the first period; and based on the relationship between the feedback signal of the row and the reference signal The relationship yields aging information for that row.
- the column driver is further configured to compensate the display signal and the correction signal of the corresponding row based on the compensation signal, and write the compensated display signal and the correction signal to the pixel array.
- the column driver is configured to write display signals of K rows in each group of times of the second period, and write correction signals of a row other than the K rows and/or output the correction signals of the row at other times of the group Feedback signal.
- the column driver is configured to write a correction signal for the pixel unit in the i-th row, where i is a positive integer less than or equal to K.
- the column driver is configured to write the correction signal for this row to the i+K*g-th row of pixel cells, and output the i-th row +K*(g-1) feedback signals of row pixel units, write display signals to pixel units in other row times of the g-th group, where g is an integer and 1 ⁇ g ⁇ n-1.
- the column driver is configured to acquire the feedback signal of the pixel unit of the n-th group of the i-th row, and in the n-th group of other The display signal is written to the pixel unit during the line time.
- the present application also discloses a display device, which includes: a pixel array including N rows and M columns of pixel units; and the aforementioned driving device.
- the compensation signal provided to the pixel array can be dynamically adjusted, thereby improving the display effect and reducing the design requirements for the column driving module.
- FIG. 1A is an architecture diagram of a display system according to an embodiment of the present application.
- FIG. 1B is a schematic diagram of a pixel unit circuit according to an embodiment of the present application.
- 1C is a structural diagram of a display signal generation module according to an embodiment of the present application.
- 1D is a schematic diagram of data transmission in the prior art and an embodiment of the present application.
- 2A is a timing diagram of a display system in the prior art
- 2B is a first frame timing diagram of a display system according to an embodiment of the present application.
- 2C is a second frame timing diagram of the display system according to the embodiment of the present application.
- FIG. 3 is a flowchart of a driving method according to an embodiment of the present application.
- FIG. 4 is a structural diagram of a display system according to another embodiment of the present invention.
- a transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar transistor (BJT).
- FET field effect transistor
- BJT bipolar transistor
- the transistor When the transistor is a field effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor and the like. According to whether the carriers are electrons or holes, they can be divided into N-type transistors and P-type transistors.
- the control electrode refers to the gate of the field effect transistor.
- the first electrode can be the drain or source of the field effect transistor.
- the second electrode can be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, its control electrode refers to the base electrode of the bipolar transistor, and the first electrode can be the collector electrode of the bipolar transistor or The emitter, and the corresponding second electrode can be the emitter or the collector of the bipolar transistor.
- the transistors can be fabricated using amorphous silicon, polysilicon, oxide semiconductor, organic semiconductor, NMOS/PMOS process or CMOS process.
- the display signal generation module receives the digital display signal and digital compensation signal from the controller, converts it into an analog display signal and an analog compensation signal, and then superimposes it in the analog domain by an analog adder, thereby generating a compensated analog display. signal and supplied to the pixel unit.
- the first period or the virtual writing period is the period in the blank period between two frames, during which the data of each frame is not input; the second period or the actual display period is for writing the data for each frame. Frame picture data.
- the compensated analog correction signal may be obtained by superimposing the analog correction signal and the analog compensation signal.
- the digital compensation signal of the pixel unit is determined through a compensation algorithm.
- the digital correction signal can be a grayscale 1 signal, which is converted into an analog correction signal through the digital-to-analog converter of the display signal generation module, and then superimposed on the analog adder and the analog compensation signal to generate a compensated analog correction signal for writing.
- the expected current or voltage is expected to be fed back by the pixel unit.
- the feedback signal from the pixel unit can be obtained by means of current or voltage detection, and then the aging information of the pixel unit can be determined.
- Signal stability refers to the stability of the signal on the feedback signal line.
- FIG. 1A is an architecture diagram of a display system according to an embodiment of the present application.
- the display system includes a pixel array 100 , a row driver 200 , a column driver 300 and a controller 400 .
- the pixel array 100 includes N rows and M columns of pixel units 101, N rows of display address lines, N rows of feedback address lines, M display signal lines and M feedback signal lines, wherein the row driver 200 and the column driver 300 are respectively It is coupled to the corresponding pixel unit 101 through the aforementioned address line or signal line, and both N and M are positive integers.
- FIG. 1B is a schematic diagram of a pixel unit circuit according to an embodiment of the present application. It can be understood that, without affecting the display method of the present invention, the pixel unit 101 may have various circuit structure forms, and FIG. 1B only shows one of the forms.
- the pixel unit 101 includes a driving transistor Q1, a display switching transistor Q2, a light emitting diode OLED, and a feedback switching transistor Q3, wherein the first electrode of the driving transistor Q1 is coupled to a specified potential (eg, a high level), and the second The pole is coupled to a low potential via the light emitting diode OLED.
- a driving transistor Q1 e.g, a display switching transistor Q2, a light emitting diode OLED, and a feedback switching transistor Q3, wherein the first electrode of the driving transistor Q1 is coupled to a specified potential (eg, a high level), and the second The pole is coupled to a low potential via the light emitting diode OLED.
- the control electrode of the display switching transistor Q2 is coupled to the row driver 200 via the display address line, the first electrode is coupled to the column driver 300 via the display signal line, and the second electrode is coupled to the control electrode of the driving transistor Q1.
- the display switching transistor Q2 may transmit the compensated analog display signal or the compensated analog correction signal (eg, the compensated analog display voltage or the compensated analog correction voltage) from the display signal line to the driving transistor Q1.
- the control electrode of the feedback switching transistor Q3 is coupled to the row driver 200 via the feedback address line, the first electrode is coupled to the second electrode of the driving transistor, and the second electrode is coupled to the aging information detection module 302 via the feedback signal line, under the control of the row driver 200
- the feedback switching transistor Q3 can transmit the analog feedback signal to the feedback signal line. It can be understood that the analog feedback signal is generated based on the analog correction signal.
- the aging of the pixel unit 101 means that one or more of the threshold voltage of the driving transistor Q1 , the threshold voltage of the light emitting diode OLED and the luminous efficiency of the light emitting diode OLED change after the pixel unit 101 is used.
- the threshold voltage will drift upward (become high), on the contrary, if the driving transistor Q1 is a P-type transistor, the threshold voltage will drift downward.
- the following describes the determination of the aging condition of the pixel unit by means of current detection.
- the row driver 200 selects the pixel unit of the target row through the display address line.
- the controller 400 selects a gray-scale display signal (such as gray-scale 1) as a digital correction signal, uses the data stored in the compensation information storage module 401, determines the digital compensation signal of each pixel unit in the row through a compensation algorithm, and then calculates the digital compensation signal.
- the signal and the digital correction signal are serially input to the column driver 300 through the first transmission module 303 and the second transmission module 304, and then output in parallel to the display signal generation module 301 in the column driver 300, so as to provide the compensated analog correction signal. to the pixel unit of the target row.
- the correction signal is generated based on the grayscale 1 of the display signal and the compensation value of the pixel unit that will perform the writing operation. It can be understood that the gray scale 1 of the display signal is the same for all pixel units, but the compensation values of different pixel units may be different.
- the second transmission module 304 serially receives the digital correction signal from the controller 400
- the first transmission module 303 serially receives the digital correction signal from the controller 400 , and then outputs it in parallel to the signal generation module 301 , and after digital-to-analog conversion, superimposes After that, the compensated analog correction signal is output to the display signal line and written into the pixel unit of the target row.
- the row driver 200 gates the feedback channel of the pixel cells of the target row (e.g., turns on the feedback switching transistor Q3) through the feedback address line.
- the aging information detection module 302 includes a current copy circuit (not shown) that maintains the feedback signal line (ie, the second pole of the feedback transistor Q3) at a specified low voltage , the specified low voltage can ensure that in the presence of feedback current, the voltage of the anode of the light-emitting diode OLED is lower than its threshold voltage, so that the light-emitting diode OLED remains off during the feedback detection process. In this way, the current generated by the driving transistor Q1 under the influence of the compensated analog correction signal will flow to the feedback signal line, and then be fed back to the current copy circuit.
- the current copy circuit outputs the current on the feedback signal line to a current comparator (not shown) to compare the current with a reference current. If the current is greater than the reference current, the compensation value needs to be lowered down when compensating for the pixel unit next time, and vice versa. It can be understood that the reference current has a fixed current value and can be used to evaluate the degree of aging.
- FIG. 1C is a structural diagram of a display signal generating module 301 according to an embodiment of the present invention.
- the column driver 300 includes a display signal generation module 301 and an aging information detection module 302 , a first transmission module 303 , a second transmission module 304 and a third transmission module 305 .
- the display signal generating module 301 includes a first digital-to-analog converter 311 , a second digital-to-analog converter 312 and an analog adder 313 .
- the first digital-to-analog converter 311 receives the digital display signal from the controller 400, and outputs the corresponding analog display signal to the analog adder 313;
- the second digital-to-analog converter 312 receives digital compensation signal, and output the analog compensation signal to the analog adder 313 .
- the analog adder 313 adds the analog compensation signal and the analog display signal and outputs the compensated analog display signal to the pixel unit 101 .
- the display signal generation module 301 wants to generate an analog correction signal
- the digital correction signal and the digital compensation signal are input into the display generation module 301, so that the display generation module 301 can output the analog correction signal C_i (including M compensated analog correction signals), where i is a positive integer less than or equal to M.
- the display signal generation module 301 generates a compensated analog display signal (or a compensated analog correction signal) based on the acquired digital compensation signal, digital display signal (or digital correction signal), and provides it to the pixel array 100 .
- the aging information detection module 302 generates digital aging information based on the received analog feedback signal.
- the aging information detection module 302 may include a current copy circuit, a comparator or an analog-to-digital converter. If the aging information detection module 302 includes a comparator, the digital aging information indicates that the received analog feedback signal is larger or smaller than the expected value. Through multiple comparisons, the target compensation value can be approached, and finally each comparison result will be above or below the target compensation value.
- the digital aging information is transmitted to the controller 400 through the third transmission module 305 .
- the first transmission module 303 is used to provide the digital compensation signal from the controller 400 to the display signal generation module 301; the second transmission module 304 is used to provide the digital display signal or digital correction signal from the controller 400 to the display signal generation module 301.
- the controller 400 includes a compensation information storage module 401 and a compensation module 402, wherein the compensation module 402 performs corresponding aging compensation on each pixel unit according to the digital aging information stored in the compensation information storage module 401, that is, a specified compensation algorithm is used to determine each pixel. compensation signal for each pixel unit.
- the controller 400 provides a digital display signal and a digital compensation signal; during a correction operation, provides a digital correction signal (eg, a digital display signal corresponding to grayscale 1) and a digital compensation signal.
- Signal L_i represents each line of compensated analog display signals, which includes M compensated analog display signals
- signal C_i represents each line of compensated analog correction signals, which includes M compensated analog correction signals. It can be understood that, for the signal C_i written for each row, the analog correction signals of each pixel unit in each row may be inconsistent, depending on the aging degree of the pixel unit.
- the schematic diagram includes four parts, namely part a to part d.
- Part a Data transmission sequence of one frame of traditional display system
- the time for writing the compensated analog display signal (ie, line time) per row is t line
- the compensated analog display signal for each row is L_i, where i is a positive value less than or equal to N Integer.
- the line time t line t Frame /N, where t Frame is the time required to write a frame of display signal corresponding to one frame of picture, excluding the blank period between frames.
- the time other than t Frame belongs to the blank period between frames.
- the sum of the actual display period t Frame of each frame and the blank period T Blank between two frames is 1/60 second.
- Part b Data transmission sequence of traditional one-frame picture after grouping
- K may be an integer greater than or equal to 2.
- Part c Data transmission sequence after adding correction signal.
- the time to actually write a frame of display signal is still t Frame , and the time length of each group 4*t line ' is equal to 3*t line , therefore, compared with the traditional data transmission, after adding the correction signal
- the line time t line ' is shorter.
- the operation time configured for each frame also includes a dummy writing period within the blank period t Blank between two frames (t Blank is not specifically indicated in the figure, all periods other than t Frame belong to t Blank ).
- the virtual write period may include a set of line times (set 0), ie a length equal to 4*t line '. This dummy writing period is used to correct the pixel cells in the 1st to 3rd rows. It can be understood that the blank period t Blank is longer than or equal to a group of line times (ie, 4*t line ').
- t line ' can be represented by the following formula:
- Each set of line times includes four line times.
- one line time of the set of line times is used to perform analog correction signal writing and/or analog feedback signal detection operations, and the other three line times are used to perform display signal writing operations (the actual display period ) or perform a wait operation (virtual write period).
- the analog feedback signal S_1 corresponding to the compensated analog correction signal C_1 is detected and the compensated analog correction signal C_4 for the 4th row of pixel cells is written.
- the compensated analog correction signal is not written but only the analog feedback signal S_(N-2 ).
- Part d 1st to 3rd frame data transmission sequence
- Compensated analog correction signal C_1 is written to row 1 of the pixel array during row time t -4 ' in group 0, and idle during other row times t-3 ' to t -1' in group 0 (ie, no signal is written to the pixel array).
- the analog feedback signal S_1 corresponding to the compensated analog correction signal C_1 is detected and the compensated analog correction signal C_4 is written for the 4th line of pixel cells; in line time t 2 ′ , write the compensated analog display signal L_1.
- the operation of each line time from group 2 to group n-1 is similar to that of group 1, and will not be repeated here.
- the analog feedback signal S_(N-2) corresponding to the analog correction signal C_(N-2) is detected. As can be appreciated, as the last group, group n no longer writes the compensated analog correction signal.
- the digital aging information generated based on the analog feedback signal S_1 is transmitted to the controller 400 , and then the digital aging information for each pixel unit in the first line can be determined according to a specified compensation algorithm Compensation value, the compensation value can be used to characterize whether the aging degree of the pixel unit is greater or less than the expected value.
- the expected value refers to a pre-specified state of the pixel unit, such as one or more of the threshold voltage of the driving transistor Q1, the threshold voltage of the light emitting diode OLED and the luminous efficiency of the light emitting diode OLED.
- the compensation information storage module 401 stores the original state of each pixel unit 101 . After use, the controller 400 will update the compensation information in the compensation information storage module 401 according to the aging condition of each pixel unit 101 . information.
- the controller 400 reads the compensation information of the corresponding row from the compensation information storage module 401 and then calculates the corresponding digital compensation signal and transmits it to the column driver 300.
- the compensated analog correction signal C_2 is written to the second row of the pixel array during row time t -3' in group 0, and is idle during other periods of group 0.
- group 1 line time t 2 ' the detector corresponding to the compensated analog correction signal S_2 C_2 analog feedback signals and the analog correction signal is written for the fifth row of pixel units C_5 compensated; time to write the set of the other rows in sequence Input the compensated analog display signal to the pixel cells of the corresponding row.
- the compensated analog display signal L_1 in the line time t 3 ', write the compensated analog display signal L_2; in the line time t 4 ', write the compensated analog display signal Signal L_3.
- each line time from group 2 to group n-1 is similar to that of group 1, and will not be repeated here.
- the analog feedback signal S_(N-1) corresponding to the compensated analog correction signal C_(N-1) is detected, and the compensated analog display signals are sequentially written in other line times to the pixel unit of the corresponding row.
- the compensated analog display signal L_1 in the second frame is generated based on a new digital compensation signal, wherein the new digital compensation signal is obtained based on the digital aging information determined in the first frame update value of . It can be understood that the digital compensation signal for each row is updated every three frames.
- Line time in group 0 t -2 ' is written in the third row of the pixel array to an analog correction signal C_3, other line time 0 is set in an idle state; line time in group 1, t 3', the detector Corresponding to the analog feedback signal S_3 of the compensated analog correction signal C_3 and writing the compensated analog correction signal C_6 for the 6th row of pixel cells, in line time t 4 ′, the compensated analog display signal L_3 is written.
- the set of other row times sequentially writes the compensated analog display signals to the pixel cells of the corresponding row.
- the line time t 1 ' the compensated analog display signal written L_1; line time t 2', the write compensated L_2 are analog display signal; line time t 4 ', the compensated analog display written Signal L_3.
- the operation of each line time from group 2 to group n-1 is similar to that of group 1, and will not be repeated here.
- the analog feedback signal S_N corresponding to the compensated analog correction signal C_N is detected, and the other line times sequentially write the compensated analog display signal to the pixel cells of the corresponding line.
- the compensated analog display signal L_2 in the third and fourth frames is based on the digital aging information in the second frame produced.
- FIG. 2A is a display timing diagram of a conventional display system
- FIG. 2B is a timing diagram of a first frame of a display system according to an embodiment of the present application
- FIG. 2C is a timing diagram of a second frame of the display system according to an embodiment of the present application.
- the signal DE comes from the controller 400 and is the enable signal of the digital display signal and the digital compensation signal.
- the display signals D[7:0] and C[7:0] are valid, and each clock (PCLK)
- a digital display signal and digital compensation signal are input to the source driver 300 .
- the signal DE' is an internal signal of the column driver 300 and has a delay with respect to the signal DE.
- the display signal generation module 301 provides a compensated analog display signal to the pixel array in parallel.
- the display signal is an 8-bit monochrome digital display signal and an 8-bit digital compensation signal as an example.
- the display signal can also be 24 bits (including 3 sub-colors of red, green and blue, in this case, the digital compensation signal is also 24 bits, and every 8 bits of the digital compensation signal is for one sub-color) or higher-order color.
- the display address line SCAN_1 is used to select the first row of pixel units 101
- the display address line SCAN_2 is used to select the second row of pixel units 101
- the display address line N is used to select the Nth row of pixel units 101 .
- each row of pixel units sequentially acquires the corresponding compensated analog display signal L_i.
- FIGS. 1D , 2B and 2C Please refer to FIGS. 1D , 2B and 2C simultaneously.
- the number of line times corresponding to one frame of picture is N+ceil(N/K), that is, the line time length is t Frame /(N+ceil(N /K)), where t Frame is the actual display period of each frame (ie, the time for writing the analog display signal).
- Group 0 row time t -4 ' to t -1 ' (virtual write period)
- the display signal generation module 301 outputs the compensated analog correction signal C_1 to the display signal line of the first row, and the row driver 200 enables the display address signal SCAN_1 of the first row, so that the pixel units of the first row are turned on,
- the compensated analog correction signal C_1 is written into the first row of pixel cells.
- the compensated analog correction signal C_1 will be transmitted to the control electrode of the driving transistor of the pixel unit of the row through the display switch transistor of the pixel unit of the row, and the display address signal SCAN_1 is low level. time, is stored in the control electrodes of the drive transistors of the pixel units in the row.
- the row driver 200 enables the feedback address signal FB_1 of the pixel unit in the first row, selects the feedback channel of the pixel unit in the first row, and converts the analog feedback signal including the pixel unit in the row. supplied to the feedback signal line.
- the feedback address signal FB_1 when the feedback address signal FB_1 is at a high level, the feedback switch transistors of the pixel units in the row will be turned on. At this time, the current generated by the driving transistors of the row of pixel units under the control of the compensated analog correction signal C_1 will be transmitted to the feedback signal line through the feedback switch transistor, and then transmitted to the aging information detection module 302 .
- the feedback address signal FB_1 of the pixel unit in the first row is still at a high level, and the aging information detection module 302 detects the feedback current on the feedback signal line.
- the row driver 200 enables the display address signal SCAN_4 of the 4th row, so that the pixel units of the 4th row are turned on, and the compensated analog correction signal C_4 generated by the display signal generation module 301 is written in 4th row of pixel cells.
- the feedback address signal FB_1 of the pixel unit in the first row may be at a low level (ie, the feedback switch transistor is turned off), and accordingly, the aging information detection module 302 is configured to detect the feedback Feedback voltage on the signal line.
- the length of the feedback address signal FB_1 may also depend on the signal stabilization time on the feedback signal line. The K value can be adjusted when the signal is stable, and the length of FB_1 will also change accordingly.
- the row driver 200 enables the feedback address signal of the 4th row to gate the feedback channel of the 4th row of pixel units, so that the feedback current of the 4th row of pixel units is output to the feedback signal line.
- the display system performs an analog display signal writing operation.
- the row driver 200 enables the display address signals SCAN_1 , SCAN_2 , and SCAN_3 row by row to select the pixel units in the first, second, and third rows.
- the display signal generation module 300 writes the compensated analog display signals L_1 , L_2 , L_3 into the 1st, 2nd, and 3rd lines, respectively.
- the aging information detection module 302 will generate digital aging information based on the acquired feedback current, and transmit the digital aging information to the controller 400 through the third transmission module 305 .
- FIG. 2C shows the timing diagram of the second frame.
- the compensated analog correction signal C_2 is first written into the second frame under the action of the display address signal SCAN_2. row pixel unit. It can be understood that the writing of the compensated analog correction signal and the detection of the analog feedback signal in the second frame are delayed by one line time compared to the operation in the first frame.
- the feedback, detection, and display in the second frame are similar to those in the previous frame, and are not repeated here.
- the compensated analog correction signal C_3 is first written into the third row of pixel units under the action of the display address signal SCAN_3. It can be understood that the writing of the analog correction signal and the detection of the analog feedback signal in the third frame are delayed by one line time compared to the operation in the second frame.
- the 0th group may be included in t Frame . That is to say in this case, the second period includes n+1 groups of time, so the line time t line in each group can be expressed by the following formula:
- FIG. 3 is a flowchart of a driving method according to an embodiment of the present application.
- Drive methods include:
- the compensated analog correction signal for the pixel unit of the ith row is written to the pixel unit of the ith row, wherein i is less than or equal to K.
- the pixel cells in the i-th row are gated, and then the controller 400 writes the corresponding compensated analog correction signals to the pixel cells in the i-th row through the column driver 300 .
- the compensated analog correction may be a compensated analog correction signal.
- the virtual writing period includes a set of line times and is in a blank period between two frames of pictures.
- the compensated analog correction signal for the row is written to the pixel unit of the i+K*gth row, where 1 ⁇ g ⁇ n-1.
- Step S302 in the 1st to nth group of row times, acquire the analog feedback signal of the pixel unit of the specified row, and provide the compensated analog display signal to the pixel array.
- the analog feedback signal of the pixel unit in the i+K*(g-1) th row is obtained, and in the other row times of the gth group of row times, the processed signal is written to the pixel unit.
- Compensated analog display signal In the ith line time of the nth group of line times, the analog feedback signal of the pixel unit of the ith row in the n-1th group of pixel units is obtained, and write to the pixel unit in other line times of the nth group of line times Input the compensated analog display signal.
- the analog feedback signal is generated based on the following steps: providing a feedback channel to the pixel units in the i+K*(g-1) row; obtaining an analog feedback signal satisfying a specified signal stability through the feedback channel, wherein , the analog feedback signal is generated based on the compensated analog correction signal.
- Digital aging information is generated based on a comparison result of the analog feedback signal and a reference signal, wherein the reference signal is a reference voltage or a reference current. It can be understood that the compensated analog display signal is generated based on the digital compensation signal and the digital display signal of the pixel unit in the current frame; the compensated analog correction signal is generated based on the digital compensation signal and the digital correction signal of the pixel unit in the current frame.
- the digital compensation signal for the pixel cell in the next frame is determined based on the digital aging information.
- FIG. 4 is a structural diagram of a display system according to another embodiment of the present invention.
- the display system in FIG. 4 includes a pixel array 100', a row driver 200', a column driver 300', and a controller 400'.
- the pixel array 100' includes N rows and M columns of pixel units 101', N rows of display address lines, N rows of feedback address lines, M display signal lines and M feedback signal lines, wherein the row driver 200', the column The driver 300' is respectively coupled to the corresponding pixel unit 101' through the aforementioned address line or signal line, and N and M are both positive integers.
- the display system in FIG. 1A compensates the analog signal provided to the pixel unit in the analog domain.
- the display system in this embodiment performs compensation in the digital domain first, and the digital compensation signal and the digital display signal (or, the digital correction signal) are the compensated digital signals generated by the compensation algorithm in the controller 400 ′.
- the display signal (or, the compensated digitally corrected signal) is then provided to the column driver 300' via the transmission module 303'.
- the compensated analog display signal (or the compensated analog correction signal) is provided to the pixel unit array 100'.
- the display systems in FIG. 1A and FIG. 4 are the same, which will not be repeated here. It can be understood that the aging information detection module 302' generates digital aging information after acquiring the analog feedback signal from the pixel unit, and provides it to the controller 400' via the transmission module 304' to update the digital compensation signal.
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Abstract
一种像素阵列（100、100'）的补偿驱动方法、驱动装置以及显示设备，其中为每帧画面配置的操作时间包括第一时段（t Blank）和第二时段（t Frame），其中，第一时段（t Blank）为相邻两帧画面之间的时间段，第二时段（t Frame）至少包括写入一帧画面的时间；方法包括：在第二时段（t Frame）的不同的时间分别写入针对像素阵列（100、100'）中多行的校正信号（C_i）和像素阵列（100、100'）中各行显示信号（L_i），并且在每次写入操作之间不存在空闲时间；在第二时段（t Frame）中，每写入一行的校正信号（C_i）后获取该行的反馈信号（S_i）；以及基于反馈信号（S_i）与参考信号之间的关系产生该行的补偿信号。
Description
本申请属于信息显示领域，尤其涉及一种像素阵列的补偿驱动方法、驱动装置以及显示设备。
AMOLED是用TFT做像素单元电路陈列再在上面做OLED的显示屏。TFT和OLED在发光之后都有老化问题。譬如，TFT阈值电压上升导致同样的驱动信号，工作电流较小；类似地，OLED阈值电压上升，也导致OLED电流减少；同样的电流，OLED发出来的光少了。除了老化问题，TFT还存在阈值电压不均匀的问题，也会导致显示屏发光不均匀。
除了上面的问题之外，像素系统的显示驱动芯片本身存在不同驱动通道驱动电路驱动不均匀的问题。因此，需要显示驱动芯片做补偿，让显示屏显示的画面比较均匀，例如，像素内补偿和像素外补偿。然而，现有的像素内补偿方法往往适用于少量的TFT器件，对于OLED发光效率补偿效果不佳，也不能补偿显示驱动芯片内各个通道之前驱动能力不平均。
因此，亟需一种像素外补偿方法，能够解决像素内补偿无法解决的问题。
发明内容
本申请提供了一种像素阵列的补偿驱动方法，其中为每帧画面配置的操作时间包括第一时段和第二时段，其中，第一时段为相邻两帧画面之间 的时间段，第二时段至少包括写入一帧画面的时间；所述方法包括：在第二时段的不同的时间分别写入针对所述像素阵列中多行的校正信号和所述像素阵列中各行显示信号，并且在每次写入操做之间不存在空闲时间；在第二时段中，每写入一行的校正信号后获取该行的反馈信号；以及基于所述反馈信号与参考信号之间的关系产生该行的补偿信号。
特别的，所述方法还包括在第一时段中，写入至少一行的校正信号，并且在第一时段中获取该行的反馈信号；以及基于该行的反馈信号与参考信号之间的关系产生该行的补偿信号。
特别的，所述方法还包括基于所述补偿信号对相应行的显示信号和校正信号进行补偿。
特别的，所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数，第二时段也相应的被分为n组，在第二时段的每组时间中写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/或输出前一组时间中被校正行的反馈信号。
特别的，在第一时段中，向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数。
特别的，在第二时段的第g组中的第i个行时间中，向第i+K*g行像素单元写入用于该行的校正信号，并且输出第i+K*(g-1)行像素单元的反馈信号，在所述第g组的其他行时间中向像素单元写入显示信号，其中，g为整数且1≤g≤n-1。
特别的，在第二时段的第n组行时间的第i个行时间中，获取第n组的第i行像素单元的反馈信号，并在所述第n组的其他行时间中向像素单元写入显示信号。
特别的，基于所述反馈信号与参考信号之间的关系产生该行的补偿信号包括基于所述反馈信号与参考信号的比较结果生成老化信息，并基于所 述老化信息产生后续帧中用于该行的补偿信号。
特别的，所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数；
当所述第一时段为零时，第二时段相应的被分为n+1组，在第二时段的首组时间中向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数；在第二时段的其余每组时间都写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/或输出前一组时间中被校正行的反馈信号。
本申请还提供了一种用于像素阵列的驱动装置，其中为每帧画面配置的操作时间包括第一时段和第二时段，其中，第一时段为相邻两帧画面之间的时间段，第二时段至少包括写入一帧画面的时间；所述装置包括行驱动器，耦合到像素阵列，配置为通过显示地址线以基于显示地址信号选通指定行的像素单元，并通过反馈地址线以基于反馈地址信号选通指定行的像素单元的反馈通道；列驱动器，耦合到像素阵列，配置为在第二时段的不同的时间分别写入针对所述像素阵列中多行的校正信号和所述像素阵列中各行显示信号，并且在每次写入操做之间不存在空闲时间；以及在第二时段中，每写入一行的校正信号后获取该行的反馈信号；以及基于所述反馈信号与参考信号之间的关系产生老化信息；以及控制器，分别与列驱动器和行驱动器耦合，配置为根据所述老化信息产生补偿信号，并向行驱动器提供行控制信号，向列控制器提供列控制信号、所述补偿信号以及显示信号和校正信号。
特别的，所述列驱动器还配置为在第一时段中，写入至少一行的校正信号，并且在第一时段中获取该行的反馈信号；以及基于该行的反馈信号与参考信号之间的关系产生该行的老化信息。
特别的，所述列驱动器还配置为基于所述补偿信号对相应行的显示信号和校正信号进行补偿，并且将经补偿的显示信号和校正信号写入像素阵 列。
特别的，所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数，第二时段也相应的被分为n组；
其中，所述列驱动器配置为在第二时段的每组时间中写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/或输出该一行的反馈信号。
特别的，在第一时段中，所述列驱动器配置为向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数。
特别的，在第二时段的第g组中的第i个行时间中，所述列驱动器配置为向第i+K*g行像素单元写入用于该行的校正信号，并且输出第i+K*(g-1)行像素单元的反馈信号，在所述第g组的其他行时间中向像素单元写入显示信号，其中，g为整数且1≤g≤n-1。
特别的，在第二时段的第n组行时间的第i个行时间中，所述列驱动器配置为获取第n组的第i行像素单元的反馈信号，并在所述第n组的其他行时间中向像素单元写入显示信号。
特别的，所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数；当所述第一时段为零时，第二时段相应的被分为n+1组，所述列驱动器配置为在第二时段的首组时间中向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数；在第二时段的其余每组时间都写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/或输出前一组时间中被校正行的反馈信号。
本申请还公开了一种显示设备，其包括：像素阵列，其包括N行M列像素单元；以及，如前述的驱动装置。
通过采用本发明的技术方案，可以动态地调整提供至像素阵列的补偿 信号，从而提升显示效果，并且降低了对列驱动模块的设计要求。
参考附图示出并阐明实施例。这些附图用于阐明基本原理，从而仅仅示出了对于理解基本原理必要的方面。这些附图不是按比例的。在附图中，相同的附图标记表示相似的特征。
图1A为依据本申请实施例的显示系统架构图；
图1B为依据本申请实施例的像素单元电路示意图；
图1C为依据本申请实施例的显示信号产生模块架构图；
图1D为现有技术与本申请实施例的数据传输示意图；
图2A为现有技术的显示系统的时序图；
图2B为依据本申请实施例的显示系统的第1帧时序图；
图2C为依据本申请实施例的显示系统的第2帧时序图；
图3为依据本申请实施例的驱动方法的流程图；
图4为依据本发明另一实施例的显示系统架构图。
在以下优选的实施例的具体描述中，将参考构成本申请一部分的所附的附图。所附的附图通过示例的方式示出了能够实现本申请的特定的实施例。示例的实施例并不旨在穷尽根据本申请的所有实施例。可以理解，在不偏离本申请的范围的前提下，可以利用其他实施例，也可以进行结构性或者逻辑性的修改。因此，以下的具体描述并非限制性的，且本申请的范围由所附的权利要求所限定。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。对于附图中的各单元之间的连线，仅仅是为了便于说明，其表示至少连线 两端的单元是相互通信的，并非旨在限制未连线的单元之间无法通信。另外，两个单元之间线条的数目旨在表示该两个单元之间通信至少所涉及的信号数或至少具备的输出端，并非用于限定该两个单元之间只能如图中所示的信号来进行通信。
在以下的详细描述中，可以参看作为本申请一部分用于说明本申请的特定实施例的各个说明书附图。在附图中，相似的附图标记在不同图式中描述大体上类似的组件。本申请的各个特定实施例在以下进行了足够详细的描述，使得具备本领域相关知识和技术的普通技术人员能够实施本申请的技术方案。应当理解，还可以利用其它实施例或者对本申请的实施例进行结构、逻辑或者电性的改变。
晶体管可指任何结构的晶体管，例如场效应晶体管(FET)或者双极型晶体管(BJT)。当晶体管为场效应晶体管时，根据沟道材料不同，可以是氢化非晶硅、金属氧化物、低温多晶硅、有机晶体管等。根据载流子是电子或空穴，可以分为N型晶体管和P型晶体管，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极；当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极。晶体管可以采用非晶硅、多晶硅、氧化物半导体、有机半导体、NMOS/PMOS工艺或者CMOS工艺来制造。
对于本申请的技术方案所涉及到的一些概念说明如下：
显示信号产生模块接收到来自控制器的数字显示信号和数字补偿信号，对其进行数模转换成模拟显示信号和模拟补偿信号后在模拟域经模拟加法器进行叠加，进而生成经补偿的模拟显示信号并提供至像素单元。第一时段或虚拟写入时段是处于两帧之间的空白时段里的时间段，在该时间段，并不输入每帧画面的数据；第二时段或实际显示时段是用于写入针对 每帧画面的数据。经补偿的模拟校正信号可以是通过叠加模拟校正信号和模拟补偿信号得到的。像素单元的数字补偿信号是经过补偿算法而确定的。譬如，数字校正信号可以是灰阶1的信号，该信号经过显示信号产生模块的数模转换器转换成模拟校正信号，再在模拟加法器与模拟补偿信号叠加生成经补偿的模拟校正信号写入像素单元后，会预期像素单元反馈预期的电流或者电压。换言之，通过向像素单元写入经补偿的模拟校正信号，可以通过电流或电压检测的方式获取来自像素单元的反馈信号，进而确定像素单元的老化信息，根据该老化信息可以在下一帧调整提供至像素单元的数字补偿信号。信号稳定度是指反馈信号线上的信号的稳定程度。
图1A为依据本申请实施例的显示系统架构图。
该显示系统包括像素阵列100、行驱动器200、列驱动器300以及控制器400。具体而言，像素阵列100包括N行M列像素单元101、N行显示地址线、N行反馈地址线、M条显示信号线和M条反馈信号线，其中，行驱动器200、列驱动器300分别通过前述的地址线或者信号线来耦合至相应的像素单元101，N和M均为正整数。
图1B为依据本申请实施例的像素单元电路示意图。可以理解的是，在不影响本发明的显示方法的前提下，像素单元101可以有多种电路结构形式，图1B仅仅示出了其中一种形式。
如图所示，像素单元101包括驱动晶体管Q1、显示开关晶体管Q2、发光二极管OLED以及反馈开关晶体管Q3，其中，驱动晶体管Q1的第一极耦合至指定电位(譬如，高电平)，第二极经由发光二极管OLED耦合至低电位。
显示开关晶体管Q2的控制极经由显示地址线耦合至行驱动器200，第一极经由显示信号线耦合至列驱动器300，第二极耦合至驱动晶体管Q1的控制极，在行驱动器200的控制下，显示开关晶体管Q2可以将来自显示信号线的经补偿的模拟显示信号或经补偿的模拟校正信号(譬如，经补偿过 的模拟显示电压或经补偿过的模拟校正电压)传输至驱动晶体管Q1。反馈开关晶体管Q3的控制极经由反馈地址线耦合至行驱动器200，第一极耦合至驱动晶体管的第二极，第二极经由反馈信号线耦合至老化信息检测模块302，在行驱动器200的控制下，反馈开关晶体管Q3可以将模拟反馈信号传输至反馈信号线，可以理解的，模拟反馈信号是基于模拟校正信号而生成。
本实施例中，像素单元101的老化是指像素单元101在使用之后，驱动晶体管Q1的阈值电压、发光二极管OLED的阈值电压以及发光二极管OLED的发光效率中的一种或多种发生了变化。譬如，当N型的驱动晶体管Q1老化之后，阈值电压就会向上飘移(变高)，反之，若驱动晶体管Q1为P型晶体管，则阈值电压就会向下飘移。下面对以电流检测的方式来确定像素单元的老化情况进行阐述。
在反馈检测操作时，行驱动器200通过显示地址线选中目标行的像素单元。控制器400选一个灰阶显示信号(比如灰阶1)做数字校正信号，利用存在补偿信息储存模块401里的数据，通过补偿算法确定该行每个像素单元的数字补偿信号，再将数字补偿信号和数字校正信号经第一传输模块303和第二传输模块304串行输入到列驱动器300，再并行输出给列驱动300中的显示信号产生模块301，进而实现将经补偿的模拟校正信号提供至目标行的像素单元。
需要说明的是，校正信号基于显示信号灰阶1和将执行写入操作的像素单元的补偿值而产生。可以理解的，显示信号灰阶1对所有像素单元都是一样的，但不同像素单元的补偿值可以不一样。
第二传输模块304串行接收来自控制器400的数字校正信号，第一传输模块303串行接收来自控制器400的数字补偿信号，之后并行输出给信号产生模块301，数模转换后，再叠加之后，再输出经补偿的模拟校正信号到显示信号线上，写入目标行的像素单元。在写完该经补偿的模拟校正信 号之后，行驱动器200通过反馈地址线来选通目标行的像素单元的反馈通道(譬如，使得反馈开关晶体管Q3导通)。
如果反馈的信号是电流，那么老化信息检测模块302就会包括电流拷贝电路(未示出)，该电流拷贝电路会将反馈信号线(即，反馈晶体管Q3的第二极)维持在指定低电压，该指定低电压能够确保在有反馈电流的情况下，发光二极管OLED阳极的电压低于其阈值电压，以使得发光二极管OLED在反馈检测的过程中保持关闭状态。这样，驱动晶体管Q1在经补偿的模拟校正信号的影响下所产生的电流会流向反馈信号线，进而反馈到电流拷贝电路。电流拷贝电路把反馈信号线上的电流输出给电流比较器(未示出)，以将该电流与参考电流做比较。如果该电流大于与参考电流，则下次对该像素单元做补偿时需要向下调低补偿值，反之就向上调。可以理解的，参考电流具有固定的电流值，可以用来评估老化程度。
请参照图1A和图1C，其中，图1C为依据本发明实施例的显示信号产生模块301的架构图。
如图1A所示列驱动器300包括显示信号产生模块301和老化信息检测模块302、第一传输模块303、第二传输模块304以及第三传输模块305。
显示信号产生模块301包括第一数模转换器311、第二数模转换器312和模拟加法器313。当像素单元101被显示地址信号选通时，第一数模转换器311接收来自控制器400的数字显示信号，并输出相应的模拟显示信号至模拟加法器313；第二数模转换器312接收数字补偿信号，并输出模拟补偿信号给模拟加法器313。模拟加法器313将模拟补偿信号和模拟显示信号进行加法运算后输出经补偿的模拟显示信号给像素单元101。可以理解的，当显示信号产生模块301要产生模拟校正信号时，将数字校正信号和数字补偿信号输入到显示产生模块301中，这样显示产生模块301就可以输出针对每行的模拟校正信号C_i(包括了M个经补偿的模拟校正信号)，其中，i为小于等于M的正整数。
具体而言，显示信号产生模块301基于所获取的数字补偿信号、数字显示信号(或数字校正信号)来生成经补偿的模拟显示信号(或经补偿的模拟校正信号)，并提供至像素阵列100。老化信息检测模块302基于所接收到的模拟反馈信号来生成数字老化信息。老化信息检测模块302可以包括电流拷贝电路，比较器或者模数转换器。如果老化信息检测模块302包括比较器，数字老化信息就表示所接收到的模拟反馈信号大于或小于预期值，通过多次比较，可以接近目标补偿值，最终每次比较结果会在目标补偿值上下一格跳动；如果老化信息检测模块包括模数转换器，则数字老化信息表示模拟反馈信号与预期值的差，通过一次模数转换，可以接近或等于目标补偿值。数字老化信息通过第三传输模块305传输至控制器400。第一传输模块303用于将来自控制器400的数字补偿信号提供至显示信号产生模块301；第二传输模块304用于将来自控制器400的数字显示信号或数字校正信号提供至显示信号产生模块301。
控制器400包括补偿信息储存模块401和补偿模块402，其中，补偿模块402根据补偿信息储存模块401储存的数字老化信息对每个像素单元进行相应的老化补偿，即利用指定的补偿算法来确定每个像素单元的补偿信号。换而言之，在显示操作时，控制器400提供数字显示信号和数字补偿信号；在校正操作时，提供数字校正信号(譬如，与灰阶1相对应的数字显示信号)和数字补偿信号。
下面结合上述系统架构和图1D来阐述数据传输的时序。信号L_i表示每行经补偿的模拟显示信号，其包括了包括M个经补偿的模拟显示信号；信号C_i表示每行经补偿的模拟校正信号，其包括M个经补偿的模拟校正信号。可以理解的，针对信号C_i针对每行写入，每行中的各像素单元的模拟校正信号可以不一致，取决于该像素单元的老化程度。
如图1D所示，该示意图包括四个部分，即部分a至部分d。
部分a：传统显示系统的一帧画面的数据传输序列
对于N行的像素阵列，每行写入经补偿的模拟显示信号的时间(即，行时间)为t
line，每行的经补偿的模拟显示信号为L_i，其中，i为小于等于N的正整数。可以理解的，行时间t
line＝t
Frame/N，其中，t
Frame为一帧画面所对应的是写入一帧显示信号需要的时间，不包括帧与帧之间的空白时段。t
Frame以外的时间都属于帧与帧之间的空白时段。
在本实施例中，若帧频是60每秒，则每帧的实际显示时段t
Frame与两帧之间的空白时段T
Blank之和为1/60秒。
部分b：分组后的传统的一帧画面的数据传输序列
对于N行的像素阵列，可以将每K行作为一组，因此，N行像素阵列可以分为n组，其中，n＝ceil(N/K)，相应地，每帧的时间也被分为n组，即第1至第n组，每组时间为K*t
line。在本实施例中，K可以是大于等于2的整数，为了便于描述，下面以K＝3为例进行描述。
部分c：加入校正信号后的数据传输序列。
在部分c中，实际写入一帧显示信号的时间仍然是t
Frame，并且每组的时间长度4*t
line’等于3*t
line，因此，相较于传统的数据传输，加入校正信号后的行时间t
line’较短。在部分c中，针对每帧画面配置的操作时间还包括位于两帧之间空白时段t
Blank内的虚拟写入时段(图中没有具体表示t
Blank，t
Frame以外所有时期都属于t
Blank)。该虚拟写入时段可以包括一组行时间(组0)，即长度等于4*t
line’。该虚拟写入时段用于对第1至3行中的像素单元进行校正。可以理解的，空白时段t
Blank长于等于一组的行时间(即4*t
line’)。其中t
line’可以通过以下公式来表示：
t
line’＝t
line*[K/(K+1)]
每组行时间均包括四个行时间。在每一帧中，该组行时间的一个行时间用于执行模拟校正信号写入和/或模拟反馈信号检测操作，另外三个行时间则是用于执行显示信号写入操作(实际显示时段)或者执行等待操作(虚拟写入时段)。
具体地，在组0的行时间t
-4’中，写入针对第1行像素单元的补偿过的模拟校正信号C_1(经补偿的模拟校正信号)，并且在组1的行时间t
1’中，检测对应于经补偿的模拟校正信号C_1的模拟反馈信号S_1并且写入针对第4行像素单元的经补偿的模拟校正信号C_4。可以理解的，由于像素阵列为N行，对于最后一组(即，组n)的第一个时间段，并不写入经补偿的模拟校正信号而是仅检测模拟反馈信号S_(N-2)。
部分d：第1至第3帧数据传输序列
第1帧：
在组0中的行时间t
-4’中向像素阵列的第1行写入经补偿的模拟校正信号C_1，在组0的其他行时间t
-3’至t
-1’，则处于空闲状态(即，不向像素阵列写入信号)。在组1的行时间t
1’中，检测对应于经补偿的模拟校正信号C_1的模拟反馈信号S_1并且写入针对第4行像素单元经补偿的模拟校正信号C_4；在行时间t
2’中，写入经补偿的模拟显示信号L_1。组2至组n-1的各行时间的操作，与组1类似，在此不进行赘述。在组n的第1个行时间中，检测与模拟校正信号C_(N-2)相对应的模拟反馈信号S_(N-2)。可以理解的，作为最后一组，组n不再写入经补偿的模拟校正信号。
在一种实施方式中，在行时间t
2’，基于模拟反馈信号S_1所生成的数字老化信息被传输到控制器400，进而可以根据指定的补偿算法来确定针对第1行中各像素单元的补偿值，该补偿值可以用于表征像素单元老化程度是大于还是小于预期值。可以理解的，该预期值是指已预先指定的像素单元的状态，譬如，驱动晶体管Q1的阈值电压、发光二极管OLED的阈值电压以及发光二极管OLED的发光效率中的一个或多个。
当显示系统在正式使用前，补偿信息储存模块401储存的是各像素单元101的原始状态，在使用之后，控制器400会根据各像素单元101的老化情况来更新补偿信息储存模块401里的补偿信息。当像素单元101被显示地址信号选通时，控制器400从补偿信息存储模块401中读取相对应行 的补偿信息再计算出相对应的数字补偿信号传输到列驱动器300。
第2帧：
在组0中的行时间t
-3’中向像素阵列的第二行写入经补偿的模拟校正信号C_2，在组0的其他时间段则处于空闲状态。在组1的行时间t
2’中，检测对应于经补偿的模拟校正信号C_2的模拟反馈信号S_2并且写入针对第五行像素单元经补偿的模拟校正信号C_5；该组其他行时间依顺序写入经补偿的模拟显示信号到相对应行的像素单元。比如，行时间t
1’中，写入经补偿的模拟显示信号L_1；行时间t
3’中，写入经补偿的模拟显示信号L_2；行时间t
4’中，写入经补偿的模拟显示信号L_3。组2至组n-1的各行时间的操作，与组1类似，在此不进行赘述。在组n的第二个行时间中，检测对应于经补偿的模拟校正信号C_(N-1)的模拟反馈信号S_(N-1)，其他行时间依顺序写入经补偿的模拟显示信号到相对应行的像素单元。
在本实施例中，第2帧中的经补偿的模拟显示信号L_1是基于新的数字补偿信号而生成，其中，该新的数字补偿信号是基于在第1帧中确定的数字老化信息而获得的更新值。可以理解的，针对每行的数字补偿信号每三帧更新一次。
第3帧：
在组0中的行时间t
-2’中向像素阵列的第三行写入模拟校正信号C_3，在组0的其他行时间则处于空闲状态；在组1的行时间t
3’中，检测对应于经补偿的模拟校正信号C_3的模拟反馈信号S_3并且写入针对第6行像素单元经补偿的模拟校正信号C_6，行时间t
4’中，写入经补偿的模拟显示信号L_3。该组其他行时间依顺序写入经补偿的模拟显示信号到相对应行的像素单元。比如，行时间t
1’中，写入经补偿的模拟显示信号L_1；行时间t
2’中，写入经补偿的模拟显示信号L_2；行时间t
4’中，写入经补偿的模拟显示信号L_3。组2至组n-1的各行时间的操作，与组1类似，在此不进行赘述。在组n的第三个行时间中，检测对应于经补偿的模拟校正信号C_N 的模拟反馈信号S_N，其他行时间依顺序写入经补偿的模拟显示信号到相对应行的像素单元。
类似地，由于第2行的像素单元的数字老化信息是在第2帧中获取并更新，因此，第3、4帧中的经补偿的模拟显示信号L_2是基于第2帧中的数字老化信息而产生。
由上述可知，每三帧便能够实现对所有的像素单元进行一次校正。可以理解的，当K为2时，每两帧便能够实现对所有的像素单元进行一次校正。
图2A为传统显示系统的显示时序图，图2B为依据本申请实施例的显示系统的第1帧的时序图，图2C为依据本申请实施例的显示系统的第2帧的时序图。
信号DE来自控制器400，是数字显示信号和数字补偿信号的使能信号，当DE为高电平时，显示信号D[7:0]和C[7：0]有效，每个时钟(PCLK)输入一个数字显示信号和数字补偿信号给源驱动器300。信号DE’为列驱动器300的内部信号，相对于信号DE具有延迟，当DE’为高电平时，显示信号产生模块301并行地向像素阵列提供经补偿的模拟显示信号。为了便于描述，这里以显示信号是为8位的单色数字显示信号和8位的数字补偿信号为例进行阐述。可以理解的，显示信号也可以是24位(包括红、绿、蓝3个子颜色，这情况，那数字补偿信号也是24位，每8位数字补偿信号对于一个子颜色)或更高阶的彩色显示信号。显示地址线SCAN_1用于选通第1行像素单元101，显示地址线SCAN_2用于选通第2行像素单元101，依此类推，显示地址线N用于选通第N行像素单元101。
由图2A可知，每行像素单元依次获取相对应的经补偿的模拟显示信号L_i。
请同时参考图1D、图2B和图2C。
如时序图所示，在图1A的显示系统实施反馈检测操作后，一帧画面所 对应的行时间数是N+ceil(N/K)，即行时间长度为t
Frame/(N+ceil(N/K))，其中，t
Frame为每帧的实际显示时段(即写入模拟显示信号的时间)。
第1帧：
(1)组0：行时间t
-4’至t
-1’(虚拟写入时段)
在行时间t
-4，显示信号产生模块301输出经补偿的模拟校正信号C_1到第1行显示信号线，行驱动器200使能第1行显示地址信号SCAN_1，使得第1行像素单元导通，将经补偿的模拟校正信号C_1写入第1行像素单元。结合图1B中的像素电路可知，经补偿的模拟校正信号C_1将经由该行像素单元的显示开关晶体管传输到该行像素单元的驱动晶体管的控制极，并且在显示地址信号SCAN_1为低电平的时候，存储在该行像素单元的驱动晶体管的控制极。
在行时间t
-3’至t
-1’，行驱动器200使能第1行像素单元的反馈地址信号FB_1，选通第1行像素单元的反馈通道，把包含该行像素单元的模拟反馈信号提供到反馈信号线上。结合图1B中的像素电路可知，当反馈地址信号FB_1为高电平时，该行像素单元的反馈开关晶体管将导通。此时，该行像素单元的驱动晶体管在经补偿的模拟校正信号C_1的控制下所产生的电流将经由反馈开关晶体管传输到反馈信号线，进而传输至老化信息检测模块302。
(2)组1：行时间t
1’至t
4’
在时段t
1’，第1行像素单元的反馈地址信号FB_1仍然处于高电平，老化信息检测模块302检测反馈信号线上的反馈电流。另外，与时段t
-4’类似地，行驱动器200使能第4行显示地址信号SCAN_4，使得第4行像素单元导通，将显示信号产生模块301产生的经补偿的模拟校正信号C_4写入第4行像素单元。
在另一种实施方式中，在时段t
1’，第1行像素单元的反馈地址信号FB_1可以处于低电平(即，关闭反馈开关晶体管)，相应地，老化信息检测 模块302配置为检测反馈信号线上的反馈电压。可以理解的，反馈地址信号FB_1的长度还可以取决于反馈信号线上的信号稳定时间。K值可以根据信号稳定时做调整，FB_1的长度也会随之变化。
在时段t
2’至t
4’中，行驱动器200使能第4行的反馈地址信号选通第4行像素单元的反馈通道，使得第4行像素单元的反馈电流输出到反馈信号线。
另外，在该些时段中，显示系统会进行模拟显示信号写入操作。具体而言，行驱动器200逐行使能显示地址信号SCAN_1、SCAN_2、SCAN_3，以选通第1、2、3行的像素单元。显示信号产生模块300将经补偿的模拟显示信号L_1、L_2、L_3分别写入到第1、2、3行。
老化信息检测模块302将基于所获取的反馈电流产生数字老化信息，并通过第三传输模块305将该数字老化信息传输到控制器400。
第2帧：
图2C示出了第2帧的时序图，与前一帧不同的是，在第2帧中，首先是经补偿的模拟校正信号C_2在显示地址信号SCAN_2的作用下，被写入到第二行像素单元。可以理解的，第2帧中的经补偿的模拟校正信号的写入、模拟反馈信号的检测均比第1帧中的操作延迟了一个行时间。第2帧中的反馈、检测、显示均与前一帧类似，在此不再赘述。
第3帧(时序图未示出)：
与前一帧不同的是，在第3帧中，首先是经补偿的模拟校正信号C_3在显示地址信号SCAN_3的作用下，被写入到第三行像素单元。可以理解的，第3帧中的模拟校正信号的写入、模拟反馈信号的检测均比第2帧中的操作延迟了一个行时间。
由上可知，采用本实施例的方法，每3帧的时间完成对所有像素单元的一次校正操作。
根据一个实施例，在第一时段或虚拟写入时段时间为0且第二时段 时间长度不变的情况，可以将第0组纳入t
Frame。也就是说在这种情况下，第二时段包括n+1组时间，因此每组中的行时间t
line”可以通过以下公式表达：
t
line”＝t
line’*[n/(n+1)]
图3为依据本申请实施例的驱动方法的流程图。
请同时参考图1D。驱动方法包括：
S301：在第一时段和第1至第n-1组行时间中，向指定行像素单元写入用于该行像素单元的经补偿的模拟校正信号。
具体地，在虚拟写入时段的第i个行时间中，向第i行像素单元写入用于该行像素单元的经补偿的模拟校正信号，其中，i小于等于K。在该步骤中，第i行像素单元被选通，然后控制器400通过列驱动器300来向第i行像素单元写入相应的经补偿的模拟校正信号。可以理解的，该经补偿的模拟校正可以是经补偿过的模拟校正信号。可以理解的，虚拟写入时段包括一组行时间，并且处于两帧画面之间的空白时段中。在实际显示时段的第g组的第i个行时间中，向第i+K*g行像素单元写入用于该行的经补偿的模拟校正信号，其中，1≤g≤n-1。
步骤S302：在第1至第n组行时间中，获取指定行像素单元的模拟反馈信号，并且向像素阵列提供经补偿的模拟显示信号。
具体地，在第1至第n组行时间中，获取第i+K*(g-1)行像素单元的模拟反馈信号，在第g组行时间的其他行时间中向像素单元写入经补偿的模拟显示信号。在第n组行时间的第i个行时间中，获取第n-1组像素单元中的第i行像素单元的模拟反馈信号，并在第n组行时间的其他行时间中向像素单元写入经补偿的模拟显示信号。
在一种实施方式中，模拟反馈信号基于以下步骤来生成：向第i+K*(g-1)行像素单元提供反馈通道；通过该反馈通道获取满足指定信号稳定度的模拟反馈信号，其中，模拟反馈信号基于经补偿的模拟校正信号而生 成。基于模拟反馈信号与参考信号的比较结果，生成数字老化信息，其中，参考信号为参考电压或参考电流。可以理解的，经补偿的模拟显示信号基于像素单元在当前帧的数字补偿信号和数字显示信号来生成；经补偿的模拟校正信号基于像素单元在当前帧的数字补偿信号和数字校正信号来生成。在一种实施方式中，基于数字老化信息来确定在下一帧用于像素单元的数字补偿信号。
图4为依据本发明另一实施例的显示系统架构图。
图1A中的显示系统类似，图4中的显示系统包括像素阵列100’、行驱动器200’、列驱动器300’以及控制器400’。具体而言，像素阵列100’包括N行M列像素单元101’、N行显示地址线、N行反馈地址线、M条显示信号线和M条反馈信号线，其中，行驱动器200’、列驱动器300’分别通过前述的地址线或者信号线来耦合至相应的像素单元101’，N和M均为正整数。
由前述可知，图1A中的显示系统是在模拟域上对提供到像素单元的模拟信号进行补偿。与之不同，本实施例中的显示系统是在先数字域做补偿，数字补偿信号和数字显示信号(或者，数字校正信号)是在控制器400’中经补偿算法计算生成的经补偿的数字显示信号(或者，经补偿的数字校正信号)再经由传输模块303’提供给列驱动器300’。经过源驱动模块301’进行数模转换后，将经补偿的模拟显示信号(或者，经补偿的模拟校正信号)提供给像素单元阵列100’。
对于模拟校正信号的插入、模拟反馈信号的检测等操作，图1A和图4中的显示系统相同，在此不做赘述。可以理解的，老化信息检测模块302’获取来自像素单元的模拟反馈信号后，生成数字老化信息，并经由传输模块304’提供给控制器400’，以更新数字补偿信号。
虽然参照特定的示例来描述了本申请，其中，这些特定的示例仅仅旨在是示例性的，而不是对本申请进行限制，但对于本领域普通技术人员来 说显而易见的是，在不脱离本申请的精神和保护范围的基础上，可以对所公开的实施例进行改变、增加或者删除。
Claims (18)
- 一种像素阵列的补偿驱动方法，其中为每帧画面配置的操作时间包括第一时段和第二时段，其中，第一时段为相邻两帧画面之间的时间段，第二时段至少包括写入一帧画面的时间；所述方法包括：在第二时段的不同的时间分别写入针对所述像素阵列中多行的校正信号和所述像素阵列中各行显示信号，并且在每次写入操做之间不存在空闲时间；在第二时段中，每写入一行的校正信号后获取该行的反馈信号；以及基于所述反馈信号与参考信号之间的关系产生该行的补偿信号。
- 如权利要求1所述的方法，还包括，在第一时段中，写入至少一行的校正信号，并且在第一时段或第二时段中获取该行的反馈信号；以及基于该行的反馈信号与参考信号之间的关系产生该行的补偿信号。
- 如权利要求1或2所述的方法，还包括基于所述补偿信号对相应行的显示信号和校正信号进行补偿。
- 如权利要求3所述的方法，其中所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数，第二时段也相应的被分为n组，在第二时段的每组时间中写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/或输出前一组时间中被校正行的反馈信号。
- 如权利要求4所述的方法，其中在第一时段中，向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数。
- 如权利要求5所述的方法，其中在第二时段的第g组中的第i个行时间中，向第i+K*g行像素单元写入用于该行的校正信号，并且输出第i+K*(g-1)行像素单元的反馈信号，在所述第g组的其他行时间中向像素单元写入显示信号，其中，g为整数且1≤g≤n-1。
- 如权利要求6所述的方法，其中在第二时段的第n组行时间的第i个行时间中，获取第n组的第i行像素单元的反馈信号，并在所述第n组的其他行时间中向像素单元写入显示信号。
- 如权利要求1所述的方法，其中，基于所述反馈信号与参考信号之间的关系产生该行的补偿信号包括：基于所述反馈信号与参考信号的比较结果生成老化信息，并基于所述老化信息产生后续帧中用于该行的补偿信号。
- 如权利要求1所述的方法，其中所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数；当所述第一时段为零时，第二时段相应的被分为n+1组，在第二时段的首组时间中向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数；在第二时段的其余每组时间都写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/或输出前一组时间中被校正行的反馈信号。
- 一种用于像素阵列的驱动装置，其中为每帧画面配置的操作时间包括第一时段和第二时段，其中，第一时段为相邻两帧画面之间的时间段，第二时段至少包括写入一帧画面的时间；所述装置包括：行驱动器，耦合到像素阵列，配置为通过显示地址线以基于显示地址信号选通指定行的像素单元，并通过反馈地址线以基于反馈地址信号选通指定行的像素单元的反馈通道；列驱动器，耦合到像素阵列，配置为在第二时段的不同的时间分别写入针对所述像素阵列中多行的校正信号和所述像素阵列中各行显示信号，并且在每次写入操做之间不存在空闲时间；以及在第二时段中，每写入一行的校正信号后获取该行的反馈信号；以及基于所述反馈信号与参考信号之间的关系产生老化信息；以及控制器，分别与列驱动器和行驱动器耦合，配置为根据所述老化信息产生补偿信号，并向行驱动器提供行控制信号，向列控制器提供列控制信 号、所述补偿信号以及显示信号和校正信号。
- 如权利要求10所述的装置，其中所述列驱动器还配置为在第一时段中，写入至少一行的校正信号，并且在第一时段中获取该行的反馈信号；以及基于该行的反馈信号与参考信号之间的关系产生该行的老化信息。
- 如权利要求10或11所述的装置，其中所述列驱动器还配置为基于所述补偿信号对相应行的显示信号和校正信号进行补偿，并且将经补偿的显示信号和校正信号写入像素阵列。
- 如权利要求12所述的装置，其中所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数，第二时段也相应的被分为n组；其中，所述列驱动器配置为在第二时段的每组时间中写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/或输出该一行的反馈信号。
- 如权利要求13所述的装置，其中在第一时段中，所述列驱动器配置为向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数。
- 如权利要求14所述的装置，其中在第二时段的第g组中的第i个行时间中，所述列驱动器配置为向第i+K*g行像素单元写入用于该行的校正信号，并且输出第i+K*(g-1)行像素单元的反馈信号，在所述第g组的其他行时间中向像素单元写入显示信号，其中，g为整数且1≤g≤n-1。
- 如权利要求15所述的装置，其中，在第二时段的第n组行时间的第i个行时间中，所述列驱动器配置为获取第n组的第i行像素单元的反馈信号，并在所述第n组的其他行时间中向像素单元写入显示信号。
- 如权利要求10所述的装置，其中所述像素阵列包括N行M列像素单元，该N行像素被划分为n个组，每个组中包括K行，其中n＝ceil(N/K)，K为大于等于2的整数；当所述第一时段为零时，第二时段相应的被分为n+1组，所述列驱动器配置为在第二时段的首组时间中向第i行像素单元写入用于该行的校正信号，其中，i是小于等于K的正整数；在第二时段的其余每组时间都写入K行的显示信号，并在该组的其他时间写入除该K行外一行的校正信号和/ 或输出前一组时间中被校正行的反馈信号。
- 一种显示设备，其特征在于，包括：像素阵列，其包括N行M列像素单元；以及如权利要求10至17任一项所述的驱动装置。
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