WO2021261496A1 - Ｖｃｓｅｌモジュール - Google Patents

Ｖｃｓｅｌモジュール Download PDF

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Publication number
WO2021261496A1
WO2021261496A1 PCT/JP2021/023664 JP2021023664W WO2021261496A1 WO 2021261496 A1 WO2021261496 A1 WO 2021261496A1 JP 2021023664 W JP2021023664 W JP 2021023664W WO 2021261496 A1 WO2021261496 A1 WO 2021261496A1
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Prior art keywords
vcsel
terminal
electrode
semiconductor device
module according
Prior art date
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PCT/JP2021/023664
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English (en)
French (fr)
Japanese (ja)
Inventor
貴 秋山
仁 内村
健志 相原
博昭 原
Original Assignee
シチズン電子株式会社
シチズン時計株式会社
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Publication date
Application filed by シチズン電子株式会社, シチズン時計株式会社 filed Critical シチズン電子株式会社
Priority to US18/012,628 priority Critical patent/US20240243546A1/en
Priority to CN202180044387.9A priority patent/CN115943533A/zh
Priority to JP2022516276A priority patent/JP7155455B2/ja
Publication of WO2021261496A1 publication Critical patent/WO2021261496A1/ja
Priority to JP2022161135A priority patent/JP2022179619A/ja

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    • H—ELECTRICITY
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G01S17/06—Systems determining position data of a target
    • G01S17/08—Systems determining position data of a target for measuring distance only
    • G01S17/10—Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
    • G—PHYSICS
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    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
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Definitions

  • the present invention relates to a VCSEL module using a VCSEL (Vertical Cavity Surface Emitting Laser) as a light source.
  • VCSEL Vertical Cavity Surface Emitting Laser
  • Japanese Unexamined Patent Publication No. 2016-4506 describes a distance measuring device that measures a distance based on light (hereinafter referred to as "reflected light") in which pulsed light emitted from a light source is reflected by an object and returned.
  • the distance measuring device includes a distance image sensor, a light source, and a control unit.
  • the distance image sensor is a charge distribution type distance image sensor, and the light source is composed of a laser light irradiation device such as a VCSEL module, an LED, or the like.
  • the control unit applies a drive signal S D to the light source to emit pulsed light (light intensity signal S LP ), and outputs the first transfer signal S1 and the second transfer signal S2 to the distance image sensor.
  • FIG. 24 is a timing chart for explaining a method of measuring a distance in the above-mentioned distance measuring device.
  • the influence of the rising period T P and the falling period T F of the light intensity signal SL P on the distance measuring accuracy is reduced, and the distance measuring accuracy is improved.
  • FIG. 25 is a perspective view of the laser diode module 600.
  • the laser diode module 600 includes a substrate 610, a laser diode 620 including a plurality of laser diode DLs, a capacitor 630 including the laser diodes C1 and C2, and an IC 4 including a driver circuit 640 including a transistor TL connected in series with the laser diode DL.
  • a driver circuit 640 including a transistor TL connected in series with the laser diode DL.
  • Light is emitted from the laser diode 620 in the direction of the arrow G.
  • FIG. 26 is a circuit diagram of the laser diode module 600 shown in FIG. 25.
  • the laser diode module 600 includes a power supply terminal Vs, a control terminal ON, and a ground terminal GND.
  • a switching transistor TL and a laser diode DL are connected in series between the power supply terminal Vs and the ground terminal GND, and capacitors C1 and C2 are connected in parallel to this series circuit.
  • the control terminal ON is connected to the gate electrode of the transistor TL.
  • Japanese Patent Application Laid-Open No. 2009-105240 describes a light emitting device having a VCSEL and a resistance element whose resistance has a positive temperature characteristic and is connected in series with the VCSEL.
  • the resistance element connected in series with the VCSEL compensates for the temperature change of the impedance characteristic of the VCSEL, so that it is possible to prevent the generation of high frequency noise and the deterioration of the drive signal due to the impedance mismatch.
  • Japanese Patent Application Laid-Open No. 2004-31456 describes an optical interconnection device in which a submount substrate having an IC driver arranged on the front surface and a VCSEL arranged on the back surface is arranged on the upper part of the substrate to reduce the size.
  • FIG. 16 of US Pat. No. 8,48892 describes a device in which a submount is placed on the top of a printed wiring board, an IC chip is placed on the top of the submount, and a VCSEL is placed on the top of the IC chip.
  • FIG. 2 of JP-A-2009-8721 there is an optical module in which a light emitting element array is arranged on a printed circuit board, a drive IC is arranged on the upper part of the light emitting element array, and a memory IC is arranged on the upper part of the drive IC.
  • a light emitting element array is arranged on a printed circuit board
  • a drive IC is arranged on the upper part of the light emitting element array
  • a memory IC is arranged on the upper part of the drive IC.
  • a VCSEL module having a three-stage structure in which a switching element is arranged on the upper part of a substrate and a VCSEL is arranged on the upper part of the switching element has not been described in any document.
  • VCSEL module it is an object of the VCSEL module according to the present invention to provide a VCSEL module in which a VCSEL and a switching element are integrated and can be miniaturized.
  • a VCSEL a VCSEL, a switching element for a VCSEL placed under the VCSEL and electrically connected to the VCSEL, and a switching element placed under the switching element and electrically connected to the switching element.
  • the above VCSEL module has a current control element arranged between the VCSEL and the switching element or between the switching element and the substrate.
  • the current control element is preferably electrically connected in series with the VCSEL and the switching element.
  • the above VCSEL module further has a wiring electrode formed on the substrate. It is preferable that the switching element or the current control element is electrically connected to the wiring electrode via a solder ball, a stud bump, or a metal piece.
  • connection portion of the wiring electrode connected to the gate electrode of the current control element is formed thicker than the other portions.
  • the above VCSEL module preferably further has a capacitor electrically connected to the VCSEL.
  • the above VCSEL module further has a first metal electrode.
  • the substrate functions as a second metal electrode and
  • the VCSEL has a VCSEL first terminal arranged on the front surface and a VCSEL second terminal arranged on the back surface, and the switching element is formed in the semiconductor device.
  • the semiconductor device preferably has a first terminal connected to the first electrode and the cathode, a second terminal connected to the cathode, and a third terminal connected to the second electrode.
  • the semiconductor device has a current control element that controls the current flowing through the VCSEL, and the current control element is between the second terminal and the switching element, or between the switching element and the third terminal. It is preferable to be connected to.
  • the semiconductor device has a rectangular flat plate shape including a first side surface, a second side surface orthogonal to the first side surface, a third side surface, and a fourth side surface, an upper surface, and a lower surface facing the first side surface.
  • the first terminal is located at the end of the upper surface along the first side surface close to the first electrode.
  • the second terminal is located in the center of the upper surface.
  • the third terminal is preferably located at the end of the upper surface along the second or third side surface.
  • the first electrode and the first terminal are connected by a plurality of bonding wires.
  • the second electrode and the third terminal are connected by a plurality of bonding wires.
  • the semiconductor device has a monitoring circuit relating to the temperature of the VCSEL, the current flowing through the VCSEL, or the amount of light emitted from the VCSEL. It is preferable that the terminal for the monitoring circuit connected to the monitoring circuit is arranged at the end of the surface of the semiconductor device along the fourth surface.
  • the above VCSEL module further has a third electrode connected to the terminal for the monitoring circuit.
  • the above VCSEL module may further have a resin frame formed to cover a part of the surface of the first electrode and the second electrode, and a part of the surface of the first terminal and the third terminal. preferable.
  • the frame preferably has a support surface on which an opening visible to the VCSEL is formed.
  • the above-mentioned VCSEL module further has an optical element that is supported by the support surface and transmits the light emitted from the VCSEL.
  • the frame has a convex portion that protrudes inward from the outer wall of the frame and above the support surface in order to position the optical element.
  • a heat dissipation path for transmitting heat radiation from the VCSEL toward the second electrode is formed between the second terminal and the lower surface of the semiconductor device in the semiconductor device.
  • the semiconductor device has a fourth terminal, which is connected to a second electrode.
  • the fourth terminal is arranged at the end of the upper surface along the other of the second side surface or the third side surface where the third terminal is arranged. It is preferable that the current flowing into the semiconductor device from the cathode of the VCSEL is divided into the left and right sides of the semiconductor device by the third terminal and the fourth terminal and flows to the second electrode.
  • the VCSEL module it is possible to provide a VCSEL module in which the VCSEL and the switching element are integrated and can be miniaturized.
  • FIG. 100 It is a side view of the VCSEL module 100 which concerns on 1st Embodiment.
  • (A) is a bottom view of the first FET 201 included in the VCSEL module 100, and (b) is a top view of the first FET 201.
  • It is a characteristic diagram of the VCSEL module 100 shown in FIG. (A) to (f) are explanatory views of the manufacturing method of the VCSEL module 100.
  • (A) to (f) are explanatory views of the manufacturing method of the VCSEL module 130 which is the first modification of the VCSEL 100 module.
  • FIG. 1 A perspective view of the manufacturing method of the VCSEL module 140 which is the second modification of the VCSEL 100 module.
  • (A) is a top view of the VCSEL100 module 100 with a frame, and (b) is a cross-sectional view taken along the line AA shown in (a).
  • (A) is a top view of the VCSEL100 module 100'with a frame, and (b) is a cross-sectional view taken along line BB shown in (a).
  • FIG. 10 excluding an optical element and a frame. It is sectional drawing of the VCSEL module 150 along the CC line shown in FIG. It is a perspective view of the frame shown in FIG. It is a circuit diagram of the VCSEL module 150 shown in FIG. It is a figure which shows the connection relationship of the 2nd electrode, a semiconductor device and a light emitting element shown in FIG. 10 schematically. It is explanatory drawing of the manufacturing method of the VCSEL module 150 shown in FIG. It is a top view corresponding to the electrode preparation process shown in FIG. It is a top view corresponding to the semiconductor device mounting process shown in FIG. It is a top view corresponding to the light emitting element mounting process shown in FIG. It is a top view corresponding to the bonding wire process shown in FIG.
  • FIG. (A) It is a top view corresponding to the frame forming process shown in FIG. (A) is a plan view of a portion of the VCSEL module 150 excluding the portion other than the base of the frame 318, (b) is a cross-sectional view taken along the DD line of (a), and (c) is (a). It is sectional drawing along the EE line. It is a timing chart of the ranging device shown as a prior art. It is a perspective view of the laser diode module 600 shown as a prior art. It is a circuit diagram of the laser diode module 600 shown in FIG.
  • FIG. 1 is a side view of the VCSEL module 100 according to the first embodiment.
  • the VCSEL module 100 includes a substrate 101, a VCSEL 105, a first FET 201, and a second FET 202.
  • the second FET 202, the first FET 201, and the VCSEL 105 are stacked on the substrate 101 in this order from the lower side of the figure.
  • a capacitor 113 (see FIG. 3) is mounted on the substrate 101, or a terminal electrode for connecting to an external circuit is formed.
  • a member constituting the stack structure that is, a VCSEL 105 is formed.
  • the first FET 201, the second FET 202, and the members related to the mounting thereof are shown in the figure.
  • An optical component that controls the light distribution of the VCSEL 105 such as a lens, may be arranged on the VCSEL 105, or a wall-shaped structure may be provided outside the stack structure, which will be described later.
  • the substrate 101 is a flat plate whose base material is made of aluminum nitride, and has a patterned metal layer (wiring electrodes 110a to 110d, etc.) on the upper surface thereof.
  • the base material is not limited to aluminum nitride, and may be a resin such as FR4.
  • the VCSEL 105 is a surface emitting type light source which is an aggregate of laser diodes in which an anode is arranged on the upper surface and a cathode is arranged on the lower surface.
  • the anode is connected to the wiring electrode 110a by the bonding wire 109, and the cathode is connected to the drain electrode 206 of the first FET 201 via the first conductive adhesive member 103.
  • the VCSEL 105 has a thickness of 200 ⁇ m and a plane size of 1.0 mm ⁇ 1.0 mm, but the size is not limited thereto.
  • the first FET 201 is provided with a drain electrode 206 over the entire upper surface of the FET die 203, and is provided with a source electrode 204 and a gate electrode 205 on the lower surface.
  • the source electrode 204 included in the first FET 201 is connected to the drain electrode 206 included in the second FET 202 via the first conductive adhesive member 103
  • the gate electrode 205 is connected to the drain electrode 206 included in the second FET 202 via the second conductive member 107. It is connected to the wiring electrode 110b.
  • the second FET 202 is the same as the first FET 201, and the source electrode 204 and the gate electrode 205 included in the second FET 202 are the wiring electrode 110d and the wiring electrode 110c, respectively, via the first conductive adhesive member 103. Is connected to.
  • the first and second FETs 201 and 202 have a thickness of 100 ⁇ m and a plane size of 1.4 mm ⁇ 1.4 mm, and the electrodes 204 to 206 are Ni-A
  • the first conductive adhesive member 103 is a member having adhesiveness and conductivity such as sintered Ag, AuSn, and solder, and is not limited to these as long as it has adhesiveness and conductivity.
  • the second conductive member 107 includes a solder ball 107a (see FIG. 5) as a member capable of increasing the height.
  • a solder plate, a gold bump, a metal plate, or the like can be used for the second conductive member 107.
  • the first conductive adhesive member 103 and the second conductive member 107 are preferably metal materials having a low electrical resistivity. Impedance can be kept low, and the VCSEL module 100 tends to pass a large current in a short period of time.
  • FIG. 2 is a bottom view (a) and a top view (b) of the first FET 201 included in the VCSEL module 100.
  • the first FET 201 is shown on the bottom surface as a small area drain electrode 206 indicated by “D”, a large area source electrode 204 indicated by “S”, and “G”.
  • a small area gate electrode 205 is arranged.
  • a drain electrode 206 occupying the entire upper surface indicated by “D” is arranged on the upper surface of the first FET 201.
  • the drain electrode 206 on the back surface is connected to the drain electrode 206 on the upper surface inside the first FET 201, but is not connected to the wiring electrodes 110a to 110d of the substrate 101 (see FIG. 1). Since the first FET 201 has a trench structure, a current flows from the upper surface to the lower surface. Further, since the second FET 202 has exactly the same structure and characteristics as the first FET 201, the description thereof will be omitted.
  • FIG. 3 is a circuit diagram of the VCSEL module 100.
  • the VCSEL 105 and the first and second FETs 201 and 202 are shown as circuit elements, but as described above, the capacitor 113 is also mounted on the substrate 101. Therefore, in FIG. 3, the circuit related to the capacitor 113 and the capacitor 113 is shown by a dotted line.
  • the VCSEL module 100 has a power supply terminal 111a, a gate terminal 111b of the first FET 201, a gate terminal 111c of the second FET 202, and a source terminal 111d.
  • the VCSEL 105, the first FET 201 and the second FET 202 are connected in series between the power supply terminal 111a and the source terminal 111d, and the capacitor 113 is connected in parallel to this series circuit.
  • Each of the terminals 111a to 111d is a terminal electrode formed on the lower surface of the substrate 101 for connecting to an external device, and the wiring electrodes 110a to 110d are electrically connected through holes and vias provided in the substrate 101. Is connected .
  • the external power supply (not shown) mainly charges the capacitor 113 via the power supply terminal 111a when the light is not emitted.
  • the external power supply cannot respond in this period and only from the power supply terminal 111a. Then, the current required for this 10 (ns) period cannot be supplied. Therefore, most of the current that causes the VCSEL 105 to emit light is due to the discharge of the capacitor 113.
  • a predetermined constant voltage is applied to the gate terminal 111b from the outside, and the first FET 201 functions as a current control element.
  • a control pulse having a width of about 10 (ns) is applied to the gate terminal 111c from the outside, and the second FET 202 functions as a switching element.
  • FIG. 4 is a characteristic diagram obtained by simulation of the current 401 flowing through the VCSEL 105 when a control pulse having a width of 10 (ns) is applied to the gate terminal 111c (see FIG. 3).
  • the vertical axis represents the current (A), and the horizontal axis represents the time (ns).
  • FIG. 4 also shows a current 402 flowing through the laser diode DL of the laser diode module 600 shown in FIGS. 25 and 26 as a conventional example.
  • the inductance of the current path that returns from the capacitor 113 to the capacitor 113 via the VCSEL 105 is set to 1 (nH).
  • the VCSEL 105 enters a constant current operation within 1 (ns) from the rising edge of the current when a control pulse is applied to the gate terminal 111c.
  • the current 402 of the conventional example when the control pulse is applied, the current value continues to increase until the application of the control pulse is completed.
  • the waveform of the current 401 of the VCSEL 105 has a rising edge of 1 (ns) or less and a flat top, and a flat portion of about 8 (ns) is secured with respect to the control pulse. Since the amount of light emitted from the VCSEL 105 is proportional to the input current, it is possible to keep the amount of light emitted from the VCSEL 105 constant during the period of the flat portion.
  • FIG. 5 is an explanatory diagram of a manufacturing method of the VCSEL module 100.
  • 5 (a) to 5 (f) show side views of characteristic states in each process.
  • VCSEL105, the first and second FETs 201 and 202, and members other than these are not shown.
  • a substrate 101 having wiring electrodes 110a to 110d on the upper surface is prepared.
  • the first conductive adhesive member 103 is applied to the upper surfaces of the wiring electrodes 110b to 110d except for the wiring electrodes 110a for the bonding wire.
  • the second FET 202 is connected to the substrate 101. At this time, the second FET 202 is arranged so that the gate electrode 205 and the source electrode 204 overlap the wiring electrodes 110c and 110d, respectively, via the first conductive adhesive member 103.
  • the solder balls 107a are arranged on the wiring electrode 110b, and the first conductive adhesive member 103 is applied to the upper surface of the second FET 202.
  • the first conductive adhesive 103 is interposed between the solder ball 107a and the wiring electrode 110b to fix the solder ball 107a.
  • the solder ball 107a can be fixed by another method such as flux, the first conductive adhesive is used.
  • the adhesive member 103 is not always necessary.
  • the first FET 201 is connected to the upper surface of the second FET 202. It is assumed that the VCSEL 105 is previously connected to the upper surface of the first FET 201 by the first conductive adhesive member 103. Further, the gate electrode 205 included in the first FET 201 is connected to the solder ball 107a, and the source electrode 204 is connected to the drain electrode 206 of the second FET 202 via the first conductive adhesive member 103.
  • the VCSEL module 100 is heated to stabilize the connection state.
  • the first conductive adhesive member 103 is cured by the first heating.
  • the temperature is raised to melt the solder balls 107a, and the solder balls 107a are connected to the first conductive adhesive member 103.
  • the solder ball 107a and the gate electrode 205 of the second FET 202 are also connected.
  • the second conductive member 107 is completed by connecting the solder ball 107a and the first conductive adhesive member 103.
  • the bonding wire 109 is connected between the anode of the VCSEL 105 and the wiring electrode 110a.
  • the solder ball 107 is directly connected to the electrode 110b.
  • the VCSEL module 100 has a structure in which the VCSEL 105, the first FET 201 which is a current control element, the second FET 202 which is a switching element, and the substrate 101 are stacked in four stages. Further, since the first FET 201 is not always necessary, the VCSEL module 100 has a structure (three-stage stack structure) in which the VCSEL 105, the second FET 202 as a switching element, and the substrate 101 are stacked in three stages. You may have it.
  • a current flows almost linearly from the anode on the upper surface to the cathode on the lower surface.
  • a current flows substantially linearly from the drain electrode 206 on the upper surface to the source electrode 204 on the lower surface. That is, in the stack structure including the VCSEL 105 and the first and second FETs 201 and 202, a current flows linearly from the upper part to the lower part in a short distance.
  • the inductance is minimized, so that the rising and falling characteristics of the current are improved.
  • this stack structure includes a first FET 201 that functions as a current control element in the current path, even if an extremely short pulse current is applied, the current does not continue to rise during that time (FIG. FIG.). 4) Current 401).
  • the VCSEL module 100 minimizes the inductance of the current path including the VCSEL 105, so that the rise and fall times of the pulse current flowing through the VCSEL 105 can be suppressed to 1 (ns) or less, and the control pulse. Even if the width is extremely short, the top of the current waveform is flattened by the first FET 201 that functions as a current control element within the control pulse width. Therefore, the VCSEL module 100 improves the waveform of the pulse current flowing through the VCSEL 105 so as to approach a square wave (see the current 401 in FIG. 4).
  • the first FET 201 is made to function as a current control element and the second FET 202 is made to function as a switching element, but the arrangement of the first FET 201 and the second FET 202 may be reversed upside down. ..
  • the first FET 201 was arranged above the second FET 202 with the VCSEL 105 mounted on the first FET 201 in advance, but the first FET 201 was placed.
  • the VCSEL 105 may be mounted on the first FET 201 after being arranged on the upper part of the second FET 202.
  • the same element is used for the first FET 201 and the second FET 202, but it is possible to realize a stack structure even if FETs of different sizes are used for each, and even so. A similar effect can be obtained.
  • FIG. 6 is an explanatory diagram of a VCSEL module 130, which is a first modification of the VCSEL module 100, and a manufacturing method thereof.
  • 6 (a) to 6 (f) show side views of characteristic states in each process.
  • FIGS. 6 (a) to 6 (f) only the VCSEL 105, the first and second FETs 201 and 202, and the members related to the mounting thereof, such as the capacitor 113 (see FIG. 3), are not shown. Also, the optical elements and frames that may be added are not shown.
  • the second conductive member 107 that connects the gate electrode 205 of the first FET 201 and the wiring electrode 110b of the substrate 101 is not limited to the member including the solder balls 107a. Therefore, in the VCSEL module 130, the VCSEL module 130 including the metal piece in the second conductive member 107 will be described.
  • the structure of the VCSEL module 130 will be described with reference to FIG. 6 (f).
  • the second FET 202, the first FET 201, and the VCSEL 105 are laminated on the substrate 101 in this order from the lower side of the figure.
  • the second conductive member 107c the first conductive adhesive member 103, the metal piece 107b, and the first conductive adhesive member 103 are laminated from the bottom.
  • the VCSEL module 130 has the same basic structure as the VCSEL module 100, and the gate electrode 205 of the first FET 201 and the wiring electrode 110b are connected to each other. Only the two conductive members 107c are different.
  • the first FET 201 is not always required in the VCSEL module 130.
  • a substrate 101 having wiring electrodes 110a to 110d on the upper surface is prepared.
  • the first conductive adhesive member 103 is applied to the upper surfaces of the wiring electrodes 110b to 110d except for the wiring electrodes 110a for the bonding wire.
  • the second FET 202 and the metal piece 107b are connected to the substrate 101.
  • the second FET 202 is arranged so that the gate electrode 205 and the source electrode 204 overlap the wiring electrodes 110c and 110d, respectively, via the first conductive adhesive member 103.
  • the metal piece 107b is arranged so as to overlap the wiring electrode 110b via the first conductive adhesive member 103.
  • the first conductive adhesive member 103 is applied to the upper surfaces of the metal piece 107b and the second FET 202.
  • the first FET 201 equipped with the VCSEL 105 is connected to the upper surface of the metal piece 107b and the second FET 202.
  • the VCSEL module 100 is heated to cure the first conductive adhesive member 103.
  • the second conductive member 107c is also completed.
  • the solder balls 107a are melted and connected to the cured first conductive connecting member 103 on the wiring electrode 110b, so that the temperature profile is complicated. The manufacturing conditions become difficult.
  • the connection with the metal piece 107b is completed only by curing the first conductive connecting member 103, so that the temperature profile of the VCSEL module 130 is simplified. That is, since it is only necessary to consider the curing of the first conductive resin 103 with respect to heating, the manufacturing conditions are facilitated.
  • the metal piece 107b is arranged together with the second FET 202 in the process shown in FIG. 6 (c), the load increase in the process is small. Further, the metal piece 107b has less variation in the outer shape than the solder ball 107, which also contributes to facilitation of the manufacturing process.
  • FIG. 7 is an explanatory diagram of a VCSEL module 140, which is a second modification of the VCSEL module 100, and a manufacturing method thereof.
  • 7 (a) to 7 (f) show side views of characteristic states in each process.
  • FIGS. 7A to 7F only the capacitor 113 (see FIG. 3), VCSEL105, the first and second FETs 201 and 202, and the members related to the mounting thereof are not shown. Also, the optical elements and frames that may be added are not shown.
  • the VCSEL module 100 and the VCSEL module 130 employ the second conductive members 107 and 107c including the solder balls 107a and the metal pieces 107b, respectively.
  • the second conductive member 107 is not always required for the connection between the gate electrode 205 of the first FET 201 and the wiring electrode 110b of the substrate 101. Therefore, the VCSEL module 140 that does not use the second conductive members 107, 107b, etc. will be described.
  • the structure of the VCSEL module 140 will be described with reference to FIG. 7 (f).
  • the second FET 202, the first FET 201, and the VCSEL 105 are laminated on the substrate 101 in this order from the lower side of the figure.
  • a thick copper plating layer 107 is formed on the upper portion of the wiring electrode 110b, and the gate electrode 205 of the first FET 201 is connected to the wiring electrode 110b via the first conductive adhesive member 103 and the thick copper plating layer 107d. You are connected. Comparing FIG. 7 (f) with FIG.
  • the VCSEL module 140 has the same basic structure as the VCSEL module 100, and has a structure for connecting the gate electrode 205 and the wiring electrode 110b of the first FET 201. Only the difference. Similarly to the VCSEL module 100, the first FET 201 is not always required in the VCSEL module 130.
  • a substrate 101 having wiring electrodes 110a to 110d on the upper surface is prepared.
  • the wiring electrode 110b is provided with a thick copper plating layer 107d formed by a plating method on the upper portion, and is thicker than the other wiring electrodes 110a, 110c, 110d.
  • the first conductive adhesive member 103 is mounted on the upper surfaces of the wiring electrodes 110c and 110d, except for the wiring electrode 110a for the bonding wire and the wiring electrode 110b provided with the thick copper plating layer 107d. Apply.
  • the second FET 202 is connected to the substrate 101. At this time, the second FET 202 is arranged so that the gate electrode 205 and the source electrode 204 overlap the wiring electrodes 110c and 110d, respectively, via the first conductive adhesive member 103.
  • the first conductive adhesive member 103 is applied to the upper surfaces of the thick copper plating layer 107d and the second FET 202.
  • the first FET 201 equipped with the VCSEL 105 is connected to the upper surface of the thick copper plating layer 107d and the second FET 202.
  • the VCSEL module 140 is heated to cure the first conductive adhesive member 103. At this time, the connection between the gate electrode 205 of the second FET 202 and the wiring electrode 110b is also completed.
  • the manufacturing process of the VCSEL module 140 shown in FIGS. 7 (b) to 7 (f) is simplified from the manufacturing process of the VCSEL module 130 shown in FIGS. 6 (b) to 6 (f). That is, in the manufacturing process of the VCSEL module 140, there is no step of forming the second conductive member 107c.
  • FIG. 8 is a diagram showing a VCSEL module 100 to which the first frame 500 is added.
  • 8 (a) is a top view
  • FIG. 8 (b) is a cross-sectional view taken along the line AA of FIG. 8 (a).
  • the first frame 500 is a black resin member, and is formed on the upper portion of the substrate 101 so as to cover the entire VCSEL module 100 except for a portion where a part of the VCSEL 105 is exposed from the portion of the central opening 501. Be placed. By covering the VCSEL module 100 with the first frame 500, the environmental resistance is improved and the state suitable for long-term use is obtained. The light emitted from the VCSEL 105 is emitted to the outside through the opening 501.
  • An optical element having predetermined optical characteristics may be arranged so as to cover the opening 501.
  • a light transmissive member formed of a thermoplastic resin such as a polyarylate resin, a thermosetting resin such as a silicone resin, and an ultraviolet curable resin such as an epoxy resin can be used.
  • FIG. 9 is a diagram showing a VCSEL module 100 ′ to which the second frame 510 is added.
  • 9 (a) is a top view
  • FIG. 9 (b) is a cross-sectional view taken along the line BB of FIG. 9 (a).
  • the VCSEL module 100 ′ uses the VCSEL module 100 instead of the bonding wire 109 by using a relay electrode 512, a first bonding wire 513, and a second bonding wire 514 arranged on the upper surface of the first FET 201.
  • the other configurations are the same.
  • the wiring electrode 110a and the relay electrode 512 are connected by the first bonding wire 513, and the relay electrode 512 and the anode of the VCSEL 105 are connected by the second bonding wire 514.
  • the second frame 510 is a black resin member so as to cover the entire VCSEL module 100'except for a portion where the entire VCSEL 105 and a part of the relay electrode 512 are exposed from the portion of the central opening 511. Is placed on top of the substrate 101. By covering the VCSEL module 100'with the second frame 510, the environmental resistance is improved and the state suitable for long-term use is obtained.
  • the light emitted from the VCSEL 105 is emitted to the outside through the opening 511.
  • an optical element having a predetermined optical characteristic may be arranged so as to cover the opening 511.
  • the VCSEL module 100'excluding the VCSEL 105 and the second bonding wire 514 is covered with the frame 510, and then the VCSEL 105 is mounted and the second bonding wire 514 is used. It became possible to connect. This increases the degree of freedom in design.
  • the rise time is set to 1 even if the pulse current flowing through the vertical resonator type surface emitting laser (VCSEL) that emits surface light in the direction perpendicular to the mounting surface as a light source has a short pulse width. It is possible to provide a VCSEL module which is suppressed to (ns) or less and further improved so that this waveform approaches a square wave.
  • VCSEL vertical resonator type surface emitting laser
  • the VCSEL comprises a first FET located under the VCSEL and a second FET located under the first FET, the first FET or the second FET.
  • One of the FETs is a switching element, and the other is a current control element.
  • the VCSEL, the switching element, and the current control element form a four-stage stack structure.
  • a current flows substantially linearly from the anode on the upper surface to the cathode on the lower surface.
  • the first and second FETs used as the switching element and the current control element the current flows substantially linearly from the drain electrode on the upper surface to the source electrode on the lower surface. Therefore, in the stack structure including the VCSEL and the first and second FETs, the current flows linearly from the upper part to the lower part.
  • the current path is straight and short, so that the inductance is minimized.
  • the stack structure includes a current control element in the current path, the current does not continue to increase for a short period given by the pulse width.
  • the above VCSEL module may further include a capacitor that supplies current to the VCSEL.
  • the above VCSEL module may further include a circuit board, and the gate electrode of the first FET and the wiring electrode of the circuit board may be connected via a solder ball, a stud bump, or a metal piece.
  • the VCSEL module further includes a circuit board, and the wiring electrode of the circuit board connected to the gate electrode of the first FET may be thicker than other wiring electrodes formed on the circuit board.
  • the rise of the pulse current flowing through the VCSEL is suppressed to 1 ns or less, and in addition, during a short period given by the width of the pulse current.
  • the current control element flattens the top of the current waveform. Therefore, in the above VCSEL module, the waveform of the pulse current flowing through the VCSEL is improved so as to approach a square wave.
  • FIG. 10 is a perspective view of the VCSEL module 150 according to the second embodiment
  • FIG. 11 is a perspective view of the VCSEL module 150 shown in FIG. 10 excluding the optical element
  • FIG. 12 is a view excluding the optical element and the frame.
  • 10 is a perspective view of the VCSEL module 150 shown in FIG. 10
  • FIG. 13 is a cross-sectional view of the VCSEL module 150 along the line CC shown in FIG.
  • the VCSEL module 150 includes a first electrode 311, a second electrode 312, nine monitoring control electrodes 313, a pair of dummy electrodes 314, a semiconductor device 315, a VCSEL 316, an optical element 317, and a frame 318. It is a lead frame package having a plurality of bonding wires 319.
  • the second electrode 312, the semiconductor device 315 and the VCSEL 316 are arranged so as to be superimposed.
  • the semiconductor device 315 has a rectangular planar shape, and has a first side 321 and a second side 322, a third side 323, and a fourth side 324.
  • Each of the first electrode 311 and the second electrode 312, the nine monitoring and control electrodes 313, and the pair of dummy electrodes 314 are formed of a conductive member having high heat dissipation such as aluminum and copper, and are arranged apart from each other. ..
  • the number of electrodes is an example and is not limited to the above.
  • the first electrode 311 has a substantially rectangular planar shape extending in the longitudinal direction, and is arranged so as to extend in the longitudinal direction parallel to the extending direction of the first side 321 of the semiconductor device 315 having the rectangular planar shape. To.
  • the first electrode 311 is electrically connected to the anode of the VCSEL 316 via the first terminal 31 arranged on the surface of the semiconductor device 315 via a plurality of bonding wires 319 arranged along the stretching direction of the first side 321. Be connected.
  • the second electrode 312 has a first protruding portion 312a and a second protruding portion on which the semiconductor device 315 is mounted and is arranged close to each of the second side 322, the third side 323, and the fourth side 324 of the semiconductor device 315. It has 312b and a third protrusion 312c.
  • the second electrode 312 is electrically connected to the semiconductor device 315 via a plurality of bonding wires 319 having one end connected to the first protruding portion 312a, the second protruding portion 312b, and the third protruding portion 312c.
  • the second electrode 312 is thermally connected to the semiconductor device 315 via an adhesive member having a high thermal conductivity such as a resin material containing a metal.
  • the five monitoring control electrodes 313 are located between the first protruding portion 312a and the third protruding portion 312c so as to be along the second side 322 and the fourth side 324 of the semiconductor device 315. Is placed in. The other four monitoring control electrodes 313 of the nine monitoring control electrodes 313 are aligned with the third side 323 and the fourth side 324 of the semiconductor device 315 between the second protruding portion 312b and the third protruding portion 312c. Is placed in. Each of the nine monitoring control electrodes 313 is electrically connected to the semiconductor device 315 via the bonding wire 319.
  • the pair of dummy electrodes 314 are arranged at both ends of the first electrode 311 in the longitudinal direction so as to be separated from the first electrode 311.
  • the semiconductor device 315 has a first terminal 331, a second terminal 332, a third terminal 333, a fourth terminal 334, a fifth terminal 335, and nine monitoring control terminals 336, and is an anode of the VCSEL 316.
  • the drive current flowing between the cathode and the cathode is monitored and controlled.
  • the first terminal 331 has a rectangular planar shape and is arranged on the surface of the semiconductor device 315 along the first side 321 facing the first electrode 311.
  • the length of the side along the first side 321 facing the first electrode 311 of the first terminal 331 is preferably longer than the side along the first side 321 facing the first electrode 311 of the VCSEL 316.
  • the number of wires from the anode terminals arranged on almost all of at least one side of the VCSEL 316 can be maximized, and the voltage drop due to the wiring resistance is suppressed.
  • the length of the side orthogonal to the first side 321 facing the first electrode 311 of the first terminal 331 is preferably shorter than the side along the first side 321 facing the first electrode 311 of the VCSEL 316.
  • the length of the side orthogonal to the first side 321 facing the first electrode 311 of the first terminal 331 is determined according to the sizes of the semiconductor device 315 and the VCSEL 316, and the first side facing the first electrode 311 is determined. It may be longer than the side along 321 or may be the same.
  • a plurality of bonding wires 319 that electrically connect the first electrode 311 and the first terminal 331 are formed along the extending direction of the first side 321. Be placed.
  • a plurality of bonding wires 319 that electrically connect the first electrode 311 and the anode of the VCSEL 316 are arranged along the extending direction of the first side 321. Will be done.
  • the second terminal 332 has a rectangular planar shape and is arranged in the center of the surface of the semiconductor device 315.
  • VCSEL316 is mounted on the second terminal 332, and the second terminal 332 and the cathode of the VCSEL316 are electrically connected to each other.
  • Each of the third terminal 333 and the fourth terminal 334 has a rectangular planar shape extending in the longitudinal direction to the second side 322 and the third side 323 orthogonal to the first side 321. It is arranged on the surface of the semiconductor device 315 along each of the three sides 323.
  • a plurality of bonding wires 319 that electrically connect between the first protrusion 312a and the third terminal 333 are arranged along the extending direction of the second side 322.
  • a plurality of bonding wires 319 that electrically connect between the second protrusion 312b and the fourth terminal 334 are arranged along the extending direction of the third side 323.
  • the fifth terminal 335 has a rectangular planar shape and is arranged in the vicinity of the central portion of the fourth side 324. At the fifth terminal 335, a bonding wire 319 for electrically connecting the third protrusion 312c and the fifth terminal 335 is arranged.
  • Each of the nine monitoring control terminals 336 has a rectangular planar shape and is arranged in the vicinity of the second side 322, the third side 323, and the fourth side 324.
  • a bonding wire 319 that electrically connects the nine monitoring control electrodes 313 to each of the nine monitoring control terminals 336 is arranged.
  • the semiconductor device 315 can be said to be a single-sided wiring board capable of a complicated circuit configuration, and has a high degree of freedom in wiring design.
  • the high degree of freedom in wiring design means that the width of the wiring is 1 ⁇ m or more, 5 ⁇ m or more, or 10 ⁇ m or more, and may be narrower than 50 ⁇ m or less, 100 ⁇ m or less, or 200 ⁇ m, and the wiring pitch is 1 ⁇ m or more and 5 ⁇ m.
  • the first terminal 331, the second terminal 332, the third terminal 333, the fourth terminal 334, the fifth terminal 335, and nine monitoring control terminals 336 can be easily provided at suitable positions on each side of the semiconductor device 315. Can be placed in. At this time, it is easy to arrange the first electrode 311 and the second electrode 312, the monitoring control electrode 313, and the dummy electrode 314 in the vicinity of each terminal so that the wire length is the shortest, and each terminal and each terminal can be easily arranged. Since the wire length of the electrode can be minimized, the risk of disconnection of the bonding wire 319 is reduced. Further, since the arrangement of each electrode is easy, a lead frame having a low degree of freedom in wiring design can be used.
  • the low degree of freedom in wiring design means, for example, that the width of the wiring is 200 ⁇ m or more, or 300 ⁇ m or more, and the pitch of the wiring is 200 ⁇ m or more.
  • the lead frame may be made of, for example, a metal material such as copper, a single layer or a single layer metal material, and the surface layer may be made of gold, silver, etc. all around. Plating may be formed.
  • VCSEL316 a plurality of emitters that emit laser light are arranged on the surface in an array at equal intervals.
  • the VCSEL 316 has, for example, 364 (26 ⁇ 14) emitters, the 364 emitters are arranged at a pitch of 0.0385 mm.
  • the VCSEL 316 has an anode arranged on the front surface and a cathode arranged on the back surface, and emits light depending on the supply of a current between the anode and the cathode.
  • the optical element 317 is a light-transmitting member made of a thermoplastic resin such as a polyarylate resin, a thermosetting resin such as a silicone resin, and an ultraviolet curable resin such as an epoxy resin.
  • a diffusion surface such as a textured surface for diffusing the light emitted from the VCSEL 316 is formed.
  • the optical element 317 forms and homogenizes the light emitted from the VCSEL 316 to emit light having a desired light distribution.
  • the optical element 317 is preferably made of a material that transmits the wavelength of the light emitted from the VCSEL 316 so that the luminous efficiency of the VCSEL module 150 does not decrease.
  • the transmittance of the optical element 317 is preferably 90% or more, more preferably 95% or more .
  • FIG. 14 is a perspective view of the frame 318.
  • the frame 318 is a black resin member, and has a first wall portion 341, a second wall portion 342, a third wall portion 343, a fourth wall portion 344, a support surface 345, and a first convex portion. It has 346 and a second convex portion 347.
  • the frame 318 is arranged so as to cover the surfaces of the first electrode 311 and the second electrode 312, a part of the first terminal 331, and the third terminal 333 and the fourth terminal 334.
  • the bottom surfaces of the first electrode 311 and the second electrode 312, the monitoring control electrode 313, and the dummy electrode 314 are not covered by the frame 318.
  • the bottom surface of the frame 318 forms the same surface as the bottom surfaces of the first electrode 311 and the second electrode 312, the monitoring control electrode 313, and the dummy electrode 314. It can be said that the bottom surfaces of the first electrode 311 and the second electrode 312, the monitoring control electrode 313, and the dummy electrode 314 have, for example, surface contact with a heat sink (not shown), and thus have a large heat dissipation path.
  • Each of the first wall portion 341, the second wall portion 342, the third wall portion 343, and the fourth wall portion 344 is the first side 321 of the semiconductor device 315, the second side 322, the third side 323, and the fourth side 24. Stretch parallel to each of the.
  • the support surface 345 is surrounded by the first wall portion 341, the second wall portion 342, the third wall portion 343, and the fourth wall portion 344, and a rectangular opening 348 in which the VCSEL 316 can be visually recognized is formed in the center.
  • the first convex portion 346 is arranged in the central portion of the inner wall of the second wall portion 342 so as to project in the direction of the third wall portion 343 facing the second wall portion 342.
  • the second convex portion 347 is arranged in the central portion of the inner wall of the third wall portion 343 so as to project in the direction of the second wall portion 342 facing the third wall portion 343.
  • Each of the first convex portion 346 and the second convex portion 347 is arranged so as to face the end portion of the optical element 317.
  • FIG. 15 is a circuit diagram of the VCSEL module 150.
  • the semiconductor device 315 further includes a current control element 351, a switching element 352, and a monitoring control circuit 353.
  • the semiconductor device 315 controls the current control element 351 and the switching element 352 connected in series to the VCSEL 316, and the monitoring control circuit 353 monitors the current flowing through the VCSEL 316 to monitor and control the light emission of the VCSEL 316.
  • the current control element 351 and the switching element 352 are n-type metal oxide film semiconductor field effect transistors (Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • the current control element 351 and the switching element 352 are connected to the second terminal 332, the third terminal 333 and the fourth terminal 334 via the VCSEL 316, the current control element 351 controls the drive current amount, and the switching element 352 controls the drive current amount. It is a drive element that controls switching of drive current on and off.
  • the gate of the current control element 351 is connected to one of the monitoring control electrodes 313 via one of the monitoring control terminals 336.
  • the source of the current control element 351 is connected to the drain of the switching element 352, and the drain of the current control element 351 is connected to the cathode of the VCSEL 316 via the second terminal 332.
  • the gate of the switching element 352 is connected to the monitoring control circuit 353, and the source of the switching element 352 is connected to the second electrode via the third terminal 333 and the fourth terminal 334.
  • the current control element 351 is located between the anode (also referred to as the VCSEL first terminal) and the cathode (also referred to as the VCSEL second terminal) of the VCSEL 316 and the current control element 351 based on the current setting signal applied to the monitoring control electrode 313. Controls the amount of drive current flowing between the source and drain of the.
  • the switching element 352 is turned on and off based on the periodic signal generated by the monitoring control circuit 353, so that the drive current flowing between the anode and the cathode of the VCSEL 316 and between the source and the drain of the switching element 352 has a predetermined period. Turn on and off with. ..
  • the monitoring control circuit 353 includes a current drive circuit 354, a temperature monitoring circuit 355, a current monitoring circuit 356, and a light amount monitoring circuit 357.
  • the current drive circuit 354 generates a periodic signal based on the signal input from the monitoring control electrode 313 via the monitoring control terminal 336, and applies the generated periodic signal to the gate of the switching element 352.
  • the monitoring control circuit 353 is grounded by being supplied with a power supply voltage from the monitoring control terminal 336 and being connected to the second electrode 312 via the fifth terminal 335.
  • the temperature monitoring circuit 355 has a thermistor, measures the temperature of VCSEL316 arranged on the surface of the semiconductor device 315, and when the temperature measured by the thermistor exceeds a predetermined threshold temperature, an alarm signal is sent to the monitoring control terminal. It is output from the monitoring control electrode 313 via 336.
  • the light amount monitoring circuit 357 receives an alarm signal when a light amount signal indicating the amount of light emitted from the VCSEL316 is input from a photoelectric conversion element (not shown) and the amount of light corresponding to the input light amount signal is out of a predetermined light amount range. Is output from the monitoring control electrode 313 via the monitoring control terminal 336.
  • the monitoring control circuit 353 does not necessarily have all of the current drive circuit 354, the temperature monitoring circuit 355, the current monitoring circuit 356, and the light amount monitoring circuit 357, but at least one of them. Is preferable to have.
  • FIG. 16 is a diagram schematically showing the connection relationship between the second electrode 312, the semiconductor device 315, and the VCSEL 316.
  • the semiconductor device 315 further includes a silicon substrate 360, a first wiring layer 361, a second wiring layer 362, a third wiring layer 363, a fourth wiring layer 364, and an insulating layer 365.
  • a p-type semiconductor doped with boron or the like, an n-type semiconductor doped with phosphorus or the like, or the like is formed on the surface of the silicon substrate 360.
  • the n-type semiconductor and p-type semiconductor formed on the surface of the silicon substrate 360 form semiconductor elements included in each of the current control element 351 and the switching element 352 and the monitoring control circuit 353.
  • Each of the first wiring layer 361 to the fourth wiring layer 364 has a plurality of wiring layers formed of a conductive member such as aluminum, and also referred to as vias, and has an interlayer connection portion for connecting the plurality of wiring layers. ..
  • the first wiring layer 361 electrically connects between the second terminal 332 and the current control element 351 and the second wiring layer 362 electrically connects between the current control element 351 and the switching element 352.
  • the third wiring layer 363 electrically connects between the third terminal 333 and the switching element 352, and the fourth wiring layer 364 electrically connects between the fourth terminal 334 and the switching element 352.
  • the insulating layer 365 is a silicon oxide film, and insulates the respective layers of the first wiring layer 361 to the fourth wiring layer 364.
  • the insulating layer 365 is described as thicker than the silicon substrate 360, but this is for the purpose of explaining the layer structure. In reality, the insulating layer 365 is a thin film of several 1000 ⁇ , and the silicon substrate 360 is 200 ⁇ m. It has a thick structure.
  • FIG. 17 is a flowchart showing a manufacturing method of the VCSEL module 150.
  • 18 is a plan view corresponding to the electrode preparation process shown in FIG. 17,
  • FIG. 19 is a plan view corresponding to the semiconductor device mounting process shown in FIG. 17, and
  • FIG. 20 corresponds to the light emitting device mounting process shown in FIG. It is a plan view.
  • 21 is a plan view corresponding to the wire bonding process shown in FIG. 17, and
  • FIG. 22 is a plan view corresponding to the frame forming process shown in FIG. 17 to 22 show a manufacturing method in which a single VCSEL module 150 is manufactured, but a plurality of VCSEL modules 150 are manufactured by a manufacturing method similar to the manufacturing method described with reference to FIGS. 17 to 22. May be manufactured at the same time and then individualized.
  • each of the first electrode 311 and the second electrode 312, the plurality of monitoring control electrodes 313, and the pair of dummy electrodes 314 are arranged at predetermined positions separated from each other. (S101).
  • the outer shape of the frame 318 added in the frame forming step is shown by a dotted line.
  • the semiconductor device 315 is mounted on the second electrode 312 (S102).
  • the semiconductor device 315 is mounted on the second electrode 312 by adhering to the surface of the second electrode 312 via a conductive adhesive member having a high thermal conductivity such as a resin material containing a metal.
  • the VCSEL 316 is mounted on the second terminal 332 arranged on the surface of the semiconductor device 315 (S103).
  • the cathode of the VCSEL 316 is electrically connected to the second terminal 332 by adhering to the surface of the second terminal 332 via a conductive adhesive member such as gold-tin solder.
  • the VCSEL 316 is arranged so as to be superimposed on the second electrode 312 and the semiconductor device 315.
  • the frame 318 includes the surfaces of the first electrode 311 and the second electrode 312, a part of the first terminal 331, and the third terminal 333 and the fourth terminal 334. Is formed so as to cover (S105).
  • the frame 318 is formed by injecting the raw material of the frame 318 into a mold having a shape corresponding to the shape of the frame 318, and then heating and solidifying the raw material of the frame 318.
  • the optical element 317 is mounted on the support surface 345 of the frame 318 (S106), and the VCSEL module 150 is completed.
  • the optical element 317 is mounted on the support surface 345 by adhering to the support surface 345 via an adhesive formed of a resin material such as a silicone resin.
  • the VCSEL module 150 since the VCSEL 316 is arranged so as to be superimposed on the semiconductor device 315 which is a drive device for driving the VCSEL 316, the semiconductor device 315 and the VCSEL 316 can be integrated and miniaturized. Further, the VCSEL module 150 has a structure (three-stage stack structure) in which the VCSEL 316, the semiconductor device 315 for driving (switching) the VCSEL 316, and the second electrode 312 for grounding the semiconductor device 315 are stacked in three stages. Therefore, further miniaturization is possible.
  • the heat radiated from the VCSEL 316 during light emission is dissipated to the second electrode 312 formed of a material having high thermal conductivity via the semiconductor device 315, so that the VCSEL module 150 is good.
  • the heat radiated from the VCSEL 316 is the silicon substrate 360 on which the second terminal 332, the first wiring layer 361, the insulating layer 365, the current control element 351 and the switching element 352 are formed. The heat is dissipated to the second electrode 312 via the above.
  • the silicon substrate 360 which is the main constituent member, has a high thermal conductivity of 160 W / mK, good heat dissipation can be realized. Further, as described above, the thermal conductivity of the insulating layer 365 is lower than that of the silicon substrate 360, but since the insulating layer 365 is as thin as several thousand ⁇ , there is no effect on heat dissipation.
  • the first electrode 311 and the first terminal 331 are connected by a plurality of bonding wires 319.
  • the VCSEL 316 is mounted on the first terminal 331, it is arranged at a position separated from the upper end of the first side 321 so as not to protrude from the first side 321 of the semiconductor device 315.
  • the length of 319 becomes longer.
  • the bonding wire 319 connecting between the VCSEL 316 and the first electrode 311 is separated from the VCSEL module 1506 at the upper end of the first side so as not to touch the upper end of the first side of the semiconductor device 315.
  • the wire becomes longer by the distance separated.
  • the VCSEL module 150 since the bonding wire 319 can be arranged in the vicinity of the first side 321 of the first terminal 331, the VCSEL module 150 has the first electrode 311 as compared with the case where the VCSEL 316 is mounted on the first terminal 331. The voltage drop due to the resistance of the wiring between the first terminal 331 and the first terminal 331 is suppressed. For example, since the wire from the VCSEL 316 to the first electrode 311 is separated from the VCSEL module 1506 at the upper end of the first side so as not to touch the upper end of the first side of the semiconductor device 315, the bonding wire 319 is separated by the separated distance. The length of is longer.
  • the VCSEL module 150 can directly connect the bonding wire 319 from the VCSEL 316 to the first terminal 331 located at a position lower than the height of the light emitting element, via the first terminal 331 having a large area, a wide width, and a small wiring resistance. Since the VCSEL module 150 can be connected to the first electrode 1 by the above-mentioned wire path, the VCSEL module 150 is located between the first electrode 311 and the anode as compared with the case where the VCSEL 316 and the first electrode 311 are connected by the bonding wire 319. The voltage drop due to the wiring resistance is suppressed, and the wiring inductance is also reduced.
  • the second electrode 312 and each of the third terminal 333 and the fourth terminal 334 are connected by a plurality of bonding wires 319, the second electrode 312 and the semiconductor device 315 are grounded. The voltage rise due to the wiring resistance between and is suppressed.
  • the first terminal 331 is arranged along the first side 321 facing the first electrode 311 and the second terminal 332 is arranged in the center of the surface of the semiconductor device 315, and the third terminal 333 and the fourth terminal 332 are arranged.
  • the terminals 334 are arranged along the second side 322 and the third side 323.
  • the first terminal 331, the second terminal 332, the third terminal 333, and the fourth terminal 334 are arranged apart from each other, so that the first terminal 331, the second terminal 332, and the third terminal 333 are separated from each other. It is possible to reduce the possibility that noise will be generated in the drive current due to interference of the drive current flowing between the fourth terminal 334 and the fourth terminal 334.
  • the drive current interferes with the signals input / output from the monitoring control circuit 353.
  • the risk of noise can be reduced.
  • the monitoring control electrode 313 connected to each of the plurality of monitoring control terminals 336 is arranged along the fourth side 324, the drive current interferes with the signal input / output from the monitoring control circuit 353, and the drive current interferes with the signal. The risk of noise in the drive current can be further reduced.
  • the surfaces of the first electrode 311 and the second electrode 312, a part of the first terminal 331, and the third terminal 333 and the fourth terminal 334 are made of a resin frame arranged after the wire bonding step. Covered by 318. Since the wire bonding step is executed before arranging the frame 318 that functions as the frame material, the VCSEL module 150 can be miniaturized without securing the separation distance in the wire bonding step.
  • the adhesive strength between the second electrode 312 and the semiconductor device 315 is reinforced by the frame 318, and the semiconductor device 315 is the second electrode. It can be prevented from peeling from 312.
  • the optical element 317 is surrounded by the first wall portion 341, the second wall portion 342, the third wall portion 343, and the fourth wall portion 344, and an opening 348 in which the VCSEL 316 can be visually recognized is formed in the center. It is supported by a support surface 345. In the VCSEL module 150, since the optical element 317 is supported by the support surface 345, the size of the optical element 317, which has a high manufacturing cost, can be minimized, so that the manufacturing cost of the VCSEL module 150 can be reduced.
  • the frame 318 has a pair of first convex portions 346 and second convex portions 347 arranged so as to sandwich the optical element 317. Therefore, when the VCSEL module 150 is manufactured, the optical element 317 is arranged. The position can be easily determined.
  • FIG. 23 is a diagram for explaining the flow of current in the VCSEL module 150.
  • 23 (a) is a plan view of the VCSEL module 150 excluding the portion other than the base of the frame 318
  • FIG. 23 (b) is a cross-sectional view of the VCSEL module 150 along the DD line of FIG. 23 (a).
  • FIG. 23 (c) is a cross-sectional view of the VCSEL module 150 along the line EE of FIG. 23 (a).
  • the thickness direction of the VCSEL module 150 is the + Z direction
  • the upper direction in the drawing in FIG. 23 (a) is the + Y direction
  • the left direction in the drawing is the + X direction.
  • the current flowing from the first electrode 311 flows into the first terminal 331 of the semiconductor device 315 via the bonding wire 319 (from the + Z direction to the + X direction).
  • the current flowing into the anode of VCSEL316 flows into the semiconductor device 315 from the cathode of VCSEL316 (located on the back surface of VCSEL105) (in the ⁇ Z direction).
  • the current flowing out from the semiconductor device 315 returns to the second electrode 312 and wraps around in the direction of the arrow F8 ( ⁇ X direction).
  • the current flowing into the semiconductor device 315 is a bonding wire from the third terminal 333 via the current control element 351 and the switching element 352 formed in the semiconductor device 315. It flows to the second electrode 312 via the 319 (from the ⁇ Y direction to the ⁇ Z direction), and flows from the fourth terminal 334 of the semiconductor device 315 to the second electrode 312 via the bonding wire 319 as shown by the arrows F11 and F12. (From + Y direction to -Z direction).
  • the current loops of the arrows F9 and F10 and the arrows F11 and F12 have symmetrical shapes. As a whole, as shown in FIG.
  • a current loop is formed from the left side in the figure to the lower side (arrow F1 direction) and the upper side (arrow F2 direction).
  • small current loops are formed three-dimensionally at the same time in the X direction, the Y direction, and the Z direction, so that the overall inductance can be lowered. It became.
  • the VCSEL 316, the semiconductor device 315, and the second electrode have a three-stage stack structure in the Z direction, so that the current path flowing out from the VCSEL 316 can be shortened. In addition, the current loop can be reduced. Further, since the VCSEL 316 and the semiconductor device 315 are connected to each other by metals instead of bonding wires, the inductance can be lowered and the high frequency switching characteristics are improved. Further, since the current flowing out from the semiconductor device 315 is evenly divided not in one direction but in the upper and lower two directions ( ⁇ Y direction) in the figure, it is possible to secure a current path having a lower inductance. ing.
  • the inductance is increased. It is possible to secure a low current path.

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JP2022516276A JP7155455B2 (ja) 2020-06-22 2021-06-22 Ｖｃｓｅｌモジュール
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JPH06237016A (ja) * 1993-02-09 1994-08-23 Matsushita Electric Ind Co Ltd 光ファイバモジュールおよびその製造方法
JP2012037276A (ja) * 2010-08-04 2012-02-23 Sharp Corp 光学式測距装置
WO2014017256A1 (ja) * 2012-07-24 2014-01-30 シャープ株式会社 光学式測距装置および電子機器
WO2018100082A1 (en) * 2016-11-30 2018-06-07 Sony Semiconductor Solutions Corporation Apparatus and method
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JP2019158693A (ja) * 2018-03-15 2019-09-19 株式会社リコー 受光装置、物体検出装置、距離測定装置、移動体装置、ノイズ計測方法、物体検出方法及び距離測定方法
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JP2022179619A (ja) 2022-12-02

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