WO2021258926A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

Info

Publication number
WO2021258926A1
WO2021258926A1 PCT/CN2021/094472 CN2021094472W WO2021258926A1 WO 2021258926 A1 WO2021258926 A1 WO 2021258926A1 CN 2021094472 W CN2021094472 W CN 2021094472W WO 2021258926 A1 WO2021258926 A1 WO 2021258926A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
shift register
gate
register unit
Prior art date
Application number
PCT/CN2021/094472
Other languages
English (en)
French (fr)
Inventor
马睿
马小叶
邵贤杰
杜瑞芳
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/778,566 priority Critical patent/US11908430B2/en
Publication of WO2021258926A1 publication Critical patent/WO2021258926A1/zh
Priority to US18/395,828 priority patent/US20240135898A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • a pixel array of a liquid crystal display usually includes multiple rows of gate lines and multiple columns of data lines interlaced therewith.
  • the gate line can be driven by an attached integrated drive circuit.
  • GOA Gate-driver On Array
  • a GOA composed of multiple cascaded shift register units can be used to provide switch-state voltage signals for multiple rows of gate lines of the pixel array, thereby controlling the multiple rows of gate lines to turn on sequentially, and the data lines correspond to the pixel array.
  • the pixel units of the rows provide data signals to form the gray-scale voltages required by each gray-scale of the displayed image, and then display each frame of image.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate and a plurality of shift register units arranged on the base substrate, the plurality of shift register units are arranged side by side along a first direction;
  • Each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit, and a frame reset signal connection trace;
  • the frame reset signal connection trace extends in the second direction and is configured to The first reset circuit provides a frame reset signal, and the second direction and the first direction cross each other;
  • the input circuit is configured to respond to the input signal to control the level of the first node;
  • the output circuit is Is configured to receive a clock signal and output the clock signal as an output signal to the output terminal under the control of the level of the first node;
  • the first reset circuit is configured to respond to the frame reset signal to The first node and the output terminal are reset in the time period between two display frames of the display substrate;
  • the first reset circuit includes a first transistor and a second transistor, and the frame reset
  • the first transistor and the second transistor are arranged adjacently along the second direction;
  • the shift register unit further includes An extended first voltage connection trace, the first voltage connection trace is configured to provide a first voltage to the shift register unit, and the first voltage is used in one of two display frames of the display substrate
  • the first node and the output terminal are reset within a period of time;
  • the first voltage connection trace, the first pole and the second pole of the first transistor, the first pole of the second transistor Both the pole and the second pole are arranged on the second conductive layer;
  • the first pole of the first transistor is electrically connected to the first node, and the first pole of the second transistor is electrically connected to the output terminal, Both the second pole of the first transistor and the second pole of the second transistor are electrically connected to the first voltage connection wire.
  • the shift register unit further includes a branch wiring disposed on the second conductive layer and extending along the first direction, and the branch wiring is connected to the The first voltage connection trace is connected; the second pole of the first transistor and the second pole of the second transistor are respectively arranged on both sides of the branch trace, and both are connected to the branch trace.
  • the first transistor and the second transistor have the same size.
  • the plurality of shift register units include a first shift register unit and a second shift register unit that are adjacently arranged in the first direction, and the The first shift register unit and the second shift register unit share the same first voltage connection trace, and are axially symmetrically distributed with respect to the first voltage connection trace.
  • the shift register unit further includes an input signal connection trace extending along the second direction, and the input signal connection trace is configured to be connected to the input signal
  • the circuit provides the input signal; the input circuit includes a third transistor, the input signal connection trace and the gate of the third transistor are both arranged on the first conductive layer, and the gate of the third transistor Connected to the input signal connection trace; the first electrode and the second electrode of the third transistor are both arranged on the second conductive layer, and the first electrode of the third transistor is connected to the gate of the third transistor.
  • the second electrode of the third transistor is connected to the first electrode of the first transistor, and the first node is the second electrode of the third transistor and the first electrode of the first transistor.
  • the shift register unit further includes a second switching electrode provided on the first conductive layer and a third switching electrode provided on the second conductive layer. Electrode, the orthographic projection of the second transfer electrode and the third transfer electrode on the base substrate at least partially overlap; the second transfer electrode is connected to the gate of the third transistor, so The third switching electrode is connected to the first electrode of the third transistor, and the second switching electrode is electrically connected to the third switching electrode.
  • the first electrode of the third transistor includes a first connection portion extending along the first direction and a plurality of first protrusions extending along the second direction.
  • the first connecting portion is connected to the third transfer electrode, the plurality of first protrusions are respectively connected to the first connecting portion, and a plurality of first protrusions are formed between the plurality of first protrusions.
  • the second electrode of the third transistor includes a second connecting portion extending along the first direction and a plurality of second protrusions extending along the second direction, the plurality of second protrusions Are respectively connected to the second connecting portion, a plurality of second recessed portions are formed between the plurality of second protrusions; the plurality of first protrusions extend into the plurality of second recessed portions, so that The plurality of second protrusions and the plurality of first protrusions are sequentially arranged at intervals along the first direction.
  • the shift register unit further includes a clock signal connection trace extending along the second direction, and the clock signal connection trace is configured to output to the
  • the circuit provides a clock signal;
  • the output circuit includes a fourth transistor and a first capacitor;
  • the gate of the fourth transistor and the first electrode of the first capacitor are arranged on the first conductive layer, and the first The first electrode of the capacitor is located on the side of the gate of the fourth transistor close to the display area of the display substrate;
  • the clock signal connection traces are all arranged on the second conductive layer;
  • the gate of the fourth transistor is electrically connected to the second electrode of the third transistor, and the first electrode of the fourth transistor is electrically connected to the second electrode of the third transistor.
  • the clock signal connection trace is connected to receive the clock signal, the second electrode of the fourth transistor is connected to the first electrode of the second transistor; the first electrode of the first capacitor is connected to the first electrode of the fourth transistor The gate is connected, and the second electrode of the first capacitor is connected to the second electrode of the fourth transistor.
  • the fourth transistor includes a plurality of sub-transistors connected in parallel along the second direction, and each of the sub-transistors includes a gate provided on the first conductive layer. Electrode, the first electrode and the second electrode provided on the second conductive layer, and the active layer provided on the semiconductor layer; the gates of the plurality of sub-transistors are connected to each other, and the first The poles are connected to each other, the second poles of the plurality of sub-transistors are connected to each other, and the active layers of the plurality of sub-transistors are sequentially arranged along the second direction, and are independent of each other and not connected.
  • the orthographic projection of the clock signal connection trace and the input signal connection trace on the base substrate is parallel and partially overlapped.
  • the shift register unit further includes a fourth switching electrode provided on the first conductive layer and a fifth switching electrode provided on the second conductive layer.
  • the fourth transfer electrode is between the gate of the third transistor and the gate of the first transistor, and the fifth transfer electrode is between the second electrode of the third transistor and the first transistor.
  • the fourth transfer electrode is electrically connected to the gate of the fourth transistor
  • the fifth transfer electrode is connected to the first pole of the first transistor and the third transistor The second pole is connected.
  • the shift register unit further includes a first connection electrode disposed on the first conductive layer, and two ends of the first connection electrode are respectively connected to the first connection electrode.
  • the gates of the four transistors are connected to the fourth transfer electrode; the first connection electrode is located on the side of the input signal connection trace close to the first transistor, and the first connection electrode is connected to the input
  • the signal connection traces are parallel to the orthographic projection portion on the base substrate.
  • the shift register unit further includes a control circuit configured to control the level of the second node according to the level of the first node;
  • the control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the gate of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor, and the eighth transistor.
  • the gates of the transistors are all arranged on the first conductive layer, the first and second electrodes of the fifth transistor, the first and second electrodes of the sixth transistor, and the first and second electrodes of the seventh transistor.
  • the electrode and the second electrode and the first electrode and the second electrode of the eighth transistor are all arranged on the second conductive layer; the gate of the eighth transistor is electrically connected to the first electrode of the eighth transistor, And is configured to receive a second voltage different from the first voltage, the second electrode of the eighth transistor is connected to the first electrode of the seventh transistor, and the gate of the seventh transistor is connected to the first electrode of the seventh transistor.
  • the gates of the six transistors are connected, the second electrode of the seventh transistor is connected to the first voltage connection trace; the gate of the fifth transistor is electrically connected to the second electrode of the eighth transistor, the The first electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, the second electrode of the fifth transistor is electrically connected to the first electrode of the eighth transistor, and the gate of the sixth transistor Is connected to the fourth transfer electrode, the second electrode of the sixth transistor is connected to the first voltage connection line; the second node is the first electrode of the fifth transistor and the sixth The junction of the first pole of the transistor.
  • the eighth transistor, the seventh transistor, and the sixth transistor are arranged adjacent to each other in the second direction, and the fifth transistor and the The eighth transistor is arranged adjacently along the first direction, and the sixth transistor and the third transistor are arranged adjacently along the first direction.
  • the shift register unit further includes a sixth switching electrode provided on the first conductive layer and a seventh switching electrode provided on the second conductive layer.
  • the sixth transfer electrode is between the gate of the fifth transistor and the gate of the eighth transistor, and is connected to the gate of the eighth transistor;
  • the seventh transfer electrode is in the Between the second electrode of the fifth transistor and the first electrode of the eighth transistor, and is connected to both the second electrode of the fifth transistor and the first electrode of the eighth transistor.
  • the shift register unit further includes an eighth switch electrode provided on the first conductive layer and a ninth switch electrode provided on the second conductive layer.
  • the eighth transfer electrode is on a side of the sixth transfer electrode close to the display area, and the eighth transfer electrode and the sixth transfer electrode are arranged adjacently along the second direction
  • the ninth switch electrode is on the side of the seventh switch electrode close to the display area, and the ninth switch electrode and the seventh switch electrode are arranged adjacent to each other along the second direction Cloth;
  • the eighth transfer electrode is connected to the gate of the fifth transistor, and the ninth transfer electrode is connected to the second electrode of the eighth transistor and the first electrode of the seventh transistor.
  • the shift register unit further includes a second reset circuit, and the second reset circuit is configured to control the second node in response to the input signal.
  • the second reset circuit includes a ninth transistor, the gate of the ninth transistor is arranged on the first conductive layer, and the first and second electrodes of the ninth transistor are arranged on the second Conductive layer; the gate of the ninth transistor is connected to the second transfer electrode, the first electrode of the ninth transistor is connected to the first electrode of the fifth transistor, and the second electrode of the ninth transistor The electrode is connected to the second electrode of the seventh transistor.
  • the fifth transistor, the ninth transistor, and the third transistor are arranged in sequence along the second direction; the second switching electrode is located at the Between the gate of the ninth transistor and the gate of the third transistor; the ninth transistor and the seventh transistor are arranged adjacently along the first direction.
  • the shift register unit further includes a second connection electrode disposed on the second conductive layer, and two ends of the second connection electrode are connected to the ninth transistor respectively.
  • the first electrode of the sixth transistor is connected to the first electrode of the sixth transistor.
  • the shift register unit further includes a third reset circuit, and the third reset circuit is configured to control all the components under the control of the level of the second node.
  • the first node and the output terminal are reset;
  • the third reset circuit includes a tenth transistor and an eleventh transistor; the gate of the tenth transistor and the gate of the eleventh transistor are arranged in the The first conductive layer, the first and second electrodes of the tenth transistor, and the first and second electrodes of the eleventh transistor are arranged on the second conductive layer; the gate of the tenth transistor The electrode is connected to the gate of the eleventh transistor, and the gate of the tenth transistor and the gate of the eleventh transistor are both electrically connected to the second node.
  • the electrode is connected to the first electrode of the first transistor, the first electrode of the eleventh transistor is connected to the first electrode of the second transistor, and the second electrode of the tenth transistor is connected to the eleventh electrode.
  • the second poles of the transistors are all electrically connected to the first voltage connection wiring.
  • the tenth transistor and the eleventh transistor are arranged adjacently along the second direction, and the tenth transistor and the first transistor are arranged along the The eleventh transistor and the second transistor are arranged adjacently in the first direction, and the eleventh transistor and the second transistor are arranged adjacently in the first direction.
  • the shift register unit further includes a tenth transfer electrode provided on the first conductive layer and an eleventh switch electrode provided on the second conductive layer. Connecting electrodes, the orthographic projections of the tenth connecting electrode and the eleventh connecting electrode on the base substrate at least partially overlap, and the tenth connecting electrode and the eleventh connecting electrode Electrically connected; the tenth transfer electrode is between the gate of the sixth transistor and the gate of the tenth transistor, and is connected to the gate of the tenth transistor; the eleventh transfer The electrode is connected to the first electrode of the sixth transistor.
  • the length of the eleventh transistor is equal to the length of the second transistor, and the length of the tenth transistor is smaller than the length of the eleventh transistor, so The width of the tenth transistor is equal to the width of the eleventh transistor.
  • the shift register unit further includes a fourth reset circuit configured to reset the first node in response to a scan reset signal;
  • the fourth reset circuit includes a twelfth transistor, the twelfth transistor is located on the side of the first capacitor close to the display area; the gate of the twelfth transistor is provided on the first conductive layer , The first electrode and the second electrode of the twelfth transistor are arranged on the second conductive layer; the gate of the twelfth transistor is configured to receive the scan reset signal, and the second electrode of the twelfth transistor The first pole is electrically connected to the first node, and the second pole of the twelfth transistor is connected to the first voltage connection line.
  • the shift register unit further includes a twelfth switching electrode disposed on the second conductive layer, and the twelfth switching electrode is connected to the twelfth switching electrode.
  • the first pole of the transistor is connected, the orthographic projection of the twelfth transfer electrode and the first pole of the first capacitor on the base substrate at least partially overlap, and the twelfth transfer electrode and the first pole of the first capacitor overlap at least partially.
  • the first pole of the first capacitor is electrically connected.
  • the shape of the orthographic projection of one of the first electrode and the second electrode of any transistor in the shift register unit on the base substrate includes at least A U-shape
  • the shape of the orthographic projection of the other of the first pole and the second pole of the transistor on the base substrate includes at least one I-shape
  • the orthographic projection of the gate of any transistor in the shift register unit on the base substrate covers the active layer of the transistor on the substrate. Orthographic projection on the substrate.
  • the plurality of shift register units include a first shift register unit, a second shift register unit, and a second shift register unit that are arranged adjacent to each other in the first direction.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate provided by any embodiment of the present disclosure.
  • Fig. 1A is a schematic circuit diagram of a shift register unit
  • FIG. 1B is a signal timing diagram corresponding to the operation of the shift register unit shown in FIG. 1A;
  • FIG. 1C is a layout diagram corresponding to the shift register unit shown in FIG. 1A;
  • 2A is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure
  • 2B is a schematic circuit diagram of a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 3 is a signal timing diagram corresponding to the operation of the shift register unit shown in FIG. 2B;
  • 4A is a simulation diagram of the potential of the first node in the shift register unit shown in FIG. 1A and the shift register unit shown in FIG. 2B;
  • FIG. 4B is a schematic diagram after enlarging the part enclosed by the dashed ellipse in FIG. 4A;
  • 5A is a test result of actual testing of the potential of the first node in the shift register unit shown in FIG. 1A and the shift register unit shown in FIG. 2B;
  • FIG. 5B is a test result of actual testing of the potential of the second node in the shift register unit shown in FIG. 1A and the shift register unit shown in FIG. 2B;
  • FIG. 6 shows a schematic diagram of cascading multiple shift register units as shown in FIG. 2B;
  • FIG. 7 is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a layout diagram corresponding to the shift register unit shown in FIG. 2B;
  • 9A, 9B, and 9C are layout diagrams corresponding to the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. 8 respectively;
  • FIG. 9D is a layout diagram of the vias used in FIG. 8;
  • FIG. 10 is a schematic cross-sectional view of various layer structures included in a display substrate provided by at least one embodiment of the present disclosure
  • 11A is a schematic cross-sectional view of a display substrate at a position including a via hole according to at least one embodiment of the present disclosure
  • FIG. 11B is a schematic cross-sectional view of a display substrate at a position including a via hole according to at least one embodiment of the present disclosure
  • FIG. 12 is a layout diagram corresponding to the schematic diagram of cascading multiple shift register units shown in FIG. 6; FIG.
  • 13A, 13B, and 13C are respectively corresponding layout diagrams of the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. 12;
  • FIG. 14 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display panel in order to achieve low cost and narrow frame, GOA (Gate-driver On Array) technology can be used, that is, the gate drive circuit is integrated on the array substrate of the display panel through thin film transistor process, so as to realize the narrow frame and Advantages such as reducing assembly costs.
  • the display panel may be a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, or a quantum dot light emitting diode (QLED) display panel.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • FIG. 1A shows a schematic circuit diagram of a shift register unit, and multiple shift register units can be cascaded to form a gate drive circuit.
  • the shift register unit includes nine transistors (T1 to T9) and a storage capacitor (C0).
  • FIG. 1C is a layout diagram corresponding to the shift register unit shown in FIG. 1A, and correspondingly shows the position of each transistor on the display substrate, as well as related electrodes, active layers, wiring, and the like.
  • the above-mentioned transistors are all N-type transistors.
  • the following also takes N-type transistors as an example for description, but the embodiments of the present disclosure are not limited to this situation.
  • at least some of these transistors can be replaced with P-type transistors.
  • the first voltage terminal VGL in FIG. 1A is configured to be connected to a DC low-level signal
  • the second voltage terminal VDD is configured to be connected to a DC high-level signal.
  • the clock signal terminal CLK inputs a low level signal
  • the input terminal IP inputs a high level signal. Since the input terminal IP inputs a high level signal, the first transistor T1 is turned on, so that the high level input from the input terminal IP charges the storage capacitor C0, and the potential of the first node N1 is pulled up to the first high level.
  • the first node N1 may be a pull-up node (PU).
  • the third node N3 may be a pull-down control node (PD_CN).
  • the sixth transistor T6 Since the potential of the first node N1 is at the first high level, the sixth transistor T6 is turned on, so that the third node N3 is electrically connected to the first voltage terminal VGL.
  • the fifth transistor T5 and the sixth transistor T6 can be configured (for example, the size ratio, threshold voltage, etc.) of the two transistors when T5 and T6 are both turned on, the potential of the third node N3 is pulled It is low to a lower level, and the low level does not make the third transistor T3 fully turn on.
  • the fourth transistor T4 Since the potential of the first node N1 is at the first high level, the fourth transistor T4 is turned on, so that the potential of the second node N2 is pulled down to a low level.
  • the second node N2 may be a drop-down node (PD).
  • the output terminal OP outputs the low level.
  • the clock signal terminal CLK inputs a high level signal
  • the input terminal IP inputs a low level signal. Since the input terminal IP inputs a low-level signal, the first transistor T1 is turned off, and the first node N1 maintains the first high level of the previous stage, so that the second transistor T2 remains on, because the clock signal terminal CLK is input at this stage High level, so the output terminal OP outputs the high level.
  • the high level can pass through the parasitic capacitance of the second transistor T2 (including the parasitic capacitance between the gate and the first pole, and the gate and the second stage
  • the parasitic capacitance between) and the storage capacitor C0 increase the potential coupling of the first node N1 to the second high level, so that the second transistor T2 is turned on more fully. Since the potential of the first node N1 is at a high level, the fourth transistor T4 continues to be turned on, so that the potential of the second node N2 continues to be maintained at a low level.
  • the signal input from the clock signal terminal CLK changes from a high level to a low level, and the low level is output to the output terminal OP through the turned-on second transistor T2.
  • the level change of the clock signal terminal CLK will pull down the potential coupling of the first node N1 to the first high level through the parasitic of the turned-on second transistor T2 and the storage capacitor C0.
  • the ninth transistor T9 is turned on, so that the first node N1 is electrically connected to the first voltage terminal VGL, and the potential of the first node N1 is pulled low. Level, so that the second transistor T2 is turned off.
  • the sixth transistor T6 and the fourth transistor T4 are turned off, the discharge path of the third node N3 and the second node N2 is cut off, and the potential of the second node N2 is charged to a high level, As a result, the seventh transistor T7 and the eighth transistor T8 are turned on, and the potentials of the first node N1 and the output terminal OP are respectively pulled down to the low level input by the first voltage terminal VGL, which further eliminates the non-operation of the shift register unit.
  • the noise may be generated at the output terminal and the first node N1.
  • the fifth transistor T5 and the sixth transistor T6 need to meet a certain configuration relationship (for example, the size ratio of the two meets a certain configuration relationship), so that the third The potential of the node N3 is pulled down to a lower level. If the potential of the third node N3 cannot completely turn off the third transistor T3, the high level signal of the second voltage terminal VDD will charge the second node N2, causing the seventh transistor T7 to be partially turned on. The charging process of the first node N1 is affected, and the normal output of the output terminal OP may be affected in severe cases.
  • a certain configuration relationship for example, the size ratio of the two meets a certain configuration relationship
  • At least one embodiment of the present disclosure provides a shift register unit.
  • the shift register unit can avoid a competitive relationship between charging and discharging of the first node, so that the first node can be charged more fully, and the use of the shift register can be improved.
  • the reliability of the unit s product.
  • the first node and the output terminal can be reset in the time period between two display frames to reduce the influence of noise, so that the reliability of the product using the shift register unit can be improved.
  • At least one embodiment of the present disclosure also provides a display substrate including the above-mentioned shift register unit.
  • the layout of the display substrate can be made more compact. Therefore, the area occupied by the peripheral area of the display substrate can be reduced, and the frame size of the display device including the display substrate can be reduced.
  • At least one embodiment of the present disclosure provides a shift register unit 200 that can be cascaded to form a gate drive circuit, and the gate drive circuit can be used in a display substrate, for example, to drive the display of the display substrate. Multiple rows of pixel units in the area are scanned and displayed.
  • the shift register unit 200 includes an input circuit 210, an output circuit 220, a first reset circuit 230, a control circuit 240, a second reset circuit 250, a third reset circuit 260, and a fourth reset circuit 270.
  • the input circuit 210 is configured to control the level of the first node N1 in response to an input signal.
  • the first node N1 may be a pull-up node (PU).
  • the input circuit 210 is electrically connected to the input terminal IP, so that when the input circuit 210 is turned on, the input signal input from the input terminal IP can be used to control the level of the first node N1, for example, pull high.
  • the input circuit 210 includes a third transistor M3.
  • the gate G3 of the third transistor M3 and the first electrode D3 of the third transistor M3 are electrically connected, and both are electrically connected to the input terminal IP to receive the input signal; the second electrode S3 of the third transistor M3 is electrically connected to the first node N1 .
  • the output circuit 220 is configured to receive a clock signal, and output the clock signal as an output signal to the output terminal OP under the control of the level of the first node.
  • the output circuit 220 is electrically connected to the clock signal terminal CLK and the output terminal OP.
  • the output circuit 220 is turned on, the clock signal received from the clock signal terminal CLK can be output as an output signal to the output terminal. OP.
  • the output circuit 220 includes a fourth transistor M4 and a first capacitor C1.
  • the gate G4 of the fourth transistor M4 is electrically connected to the first node N1
  • the first electrode D4 of the fourth transistor M4 is electrically connected to the clock signal terminal CLK to receive the clock signal
  • the second electrode S4 of the fourth transistor M4 is electrically connected to the output terminal OP Electric connection.
  • the first pole 801 of the first capacitor C1 is electrically connected to the first node N1
  • the second pole 802 of the first capacitor C1 is electrically connected to the output terminal OP.
  • the first reset circuit 230 is configured to respond to the frame reset signal to reset the first node N1 and the output terminal OP in a time period between two display frames of the display substrate.
  • the first reset circuit 230 is electrically connected to the frame reset signal terminal STV to receive the frame reset signal
  • the first reset circuit 230 is electrically connected to the first voltage terminal VGL to receive the first voltage, for example, the first The voltage can be a low-level voltage.
  • the first reset circuit 230 is also electrically connected to the first node N1 and the output terminal OP.
  • the first reset circuit 230 In the time period between two adjacent display frames of the display substrate, when the first reset circuit 230 is turned on in response to the frame reset signal, the first node N1 and the first node N1 and The output terminal OP performs a reset operation, so that the noise on the first node N1 and the output terminal OP can be reduced or eliminated, so that the reliability of the product using the shift register unit 200 can be improved.
  • the first reset circuit 230 includes a first transistor M1 and a second transistor M2.
  • the gate G1 of the first transistor M1 is electrically connected to the frame reset signal terminal STV to receive the frame reset signal
  • the first electrode D1 of the first transistor M1 is electrically connected to the first node N1
  • the second electrode S1 of the first transistor M1 is electrically connected to the first node N1.
  • a voltage terminal VGL is electrically connected to receive a low-level first voltage.
  • the gate G2 of the second transistor M2 is electrically connected to the frame reset signal terminal STV to receive the frame reset signal, the first electrode D2 of the second transistor M2 is electrically connected to the output terminal OP, and the second electrode S2 of the second transistor M2 is electrically connected to the first
  • the voltage terminal VGL is electrically connected to receive a low-level first voltage.
  • the first node N1 is a junction point of the second electrode S3 of the third transistor M3, the first electrode D1 of the first transistor M1 and the gate G4 of the fourth transistor M4.
  • the control circuit 240 is configured to control the level of the second node N2 according to the level of the first node N1.
  • the second node N2 may be a drop-down node (PD).
  • the control circuit 240 is electrically connected to the first voltage terminal VGL to receive a low-level first voltage; the control circuit 240 is electrically connected to the second voltage terminal VDD to receive a second voltage different from the first voltage.
  • the voltage for example, the second voltage may be a high-level voltage.
  • the control circuit 240 is also electrically connected to the first node N1 and the second node N2.
  • the control circuit 240 controls the level of the second node N2 to be low; when the level of the first node N1 is low, the control circuit 240 combines The high-level second voltage received by the second voltage terminal VDD can be controlled so that the level of the second node N2 is high.
  • the control circuit 240 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.
  • the gate G8 of the eighth transistor M8 is electrically connected to the first electrode D8 of the eighth transistor M8, and both are electrically connected to the second voltage terminal VDD to receive the high-level second voltage; the second electrode S8 of the eighth transistor M8 It is electrically connected to the third node N3.
  • the third node N3 may be a pull-down control node (PD_CN).
  • the gate G7 of the seventh transistor M7 is electrically connected to the first node N1, the first electrode D7 of the seventh transistor M7 is electrically connected to the third node N3, and the second electrode S7 of the seventh transistor M7 is electrically connected to the first voltage terminal VGL To receive the low-level first voltage.
  • the gate G5 of the fifth transistor M5 is electrically connected to the third node N3, the first electrode D5 of the fifth transistor M5 is electrically connected to the second node N2, and the second electrode S5 of the fifth transistor M5 is electrically connected to the second voltage terminal VDD To receive the high-level second voltage.
  • the gate of the sixth transistor M6 is electrically connected to the first node N1, the first electrode D6 of the sixth transistor M6 is electrically connected to the second node N2, and the second electrode S6 of the sixth transistor M6 is electrically connected to the first voltage terminal VGL to Receive the low-level first voltage.
  • the second node N2 is the junction point of the first pole D5 of the fifth transistor M5 and the first pole D6 of the sixth transistor M6;
  • the third node N3 is the second pole S8 of the eighth transistor M8 and the fifth transistor M5.
  • each node (first node N1, second node N2, third node N3) and each signal terminal (input terminal IP, output terminal OP, frame reset signal terminal STV, The scan reset signal terminal RST, the clock signal terminal CLK, etc.) are all set to better describe the circuit structure, and do not represent actual components.
  • the node represents the junction of the related circuit connections in the circuit structure, that is, the related circuits connected with the same node identifier are electrically connected to each other.
  • the second reset circuit 250 is configured to control the level of the second node N2 in response to the input signal.
  • the second reset circuit 250 is electrically connected to the input terminal IP to receive an input signal
  • the second reset circuit 250 is also electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
  • the second reset circuit 250 is also electrically connected to the second node N2.
  • the input circuit 210 uses the input signal to charge the first node N1
  • the second reset circuit 250 can be turned on in response to the input signal, so that the low-level first voltage can be used to control the second node N2.
  • Level for example, pulls down the potential of the second node N2 to a low level.
  • the potential of the second node N2 does not affect the charging process of the first node N1, so that the charging of the first node N1 More fully, the reliability of the product using the shift register unit 200 can be improved.
  • the second reset circuit 250 includes a ninth transistor M9.
  • the gate G9 of the ninth transistor M9 is electrically connected to the input terminal IP to receive the input signal
  • the first electrode D9 of the ninth transistor M9 is electrically connected to the second node N2
  • the second electrode S9 of the ninth transistor M9 is electrically connected to the first voltage terminal
  • the VGL is electrically connected to receive the low-level first voltage.
  • the third reset circuit 260 is configured to reset the first node N1 and the output terminal OP under the control of the level of the second node N2.
  • the third reset circuit 260 is electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
  • the third reset circuit 260 is also connected to the first node N1, the second node N2, and The output terminal OP is electrically connected.
  • the third reset circuit 260 is turned on under the control of the level of the second node N2 (for example, the level of the second node N2 is a high level)
  • the first voltage of a low level can be used for the first voltage respectively.
  • a node N1 and the output terminal OP are reset, so that the noise on the first node N1 and the output terminal OP can be reduced or eliminated.
  • the third reset circuit 260 includes a tenth transistor M10 and an eleventh transistor M11.
  • the gate G10 of the tenth transistor M10 is electrically connected to the second node N2
  • the first electrode D10 of the tenth transistor M10 is electrically connected to the first node N1
  • the second electrode S10 of the tenth transistor M10 is electrically connected to the first voltage terminal VGL To receive the low-level first voltage.
  • the gate G11 of the eleventh transistor M11 is electrically connected to the second node N2, the first electrode D11 of the eleventh transistor M11 is electrically connected to the output terminal OP, and the second electrode S11 of the eleventh transistor M11 is electrically connected to the first voltage terminal VGL It is electrically connected to receive a low-level first voltage.
  • the fourth reset circuit 270 is configured to reset the first node N1 in response to the scan reset signal, for example, pull down the level of the first node N1, thereby reducing possible noise on the first node N1.
  • the fourth reset circuit 270 is electrically connected to the scan reset signal terminal RST to receive the scan reset signal, and electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
  • the fourth reset circuit 270 is also electrically connected to the first node N1. For example, when the fourth reset circuit 270 is turned on in response to the scan reset signal, the first node N1 may be reset by using a low-level first voltage, thereby pulling down the level of the first node N1.
  • the fourth reset circuit 270 includes a twelfth transistor M12.
  • the gate G12 of the twelfth transistor M12 is electrically connected to the scan reset signal terminal RST to receive the scan reset signal
  • the first electrode D12 of the twelfth transistor M12 is electrically connected to the first node N1
  • the second electrode of the twelfth transistor M12 S12 is electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
  • connection in the foregoing description of the connection relationship in the shift register unit 200 shown in FIG. 2B, "electrical connection” is used.
  • the “electrical connection” of two components indicates that the two components are electrically connected, including direct connection and indirect connection, that is, in the corresponding layout drawing, the two components can be directly connected (for example, integrated) to Electrical connection is achieved, or the two components can be electrically connected through other components arranged between the two components.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • the high level and the low level are relative.
  • the high level indicates a higher voltage range (for example, the high level may adopt 5V, 10V or other suitable voltages), and multiple high levels may be the same or different.
  • the low level represents a lower voltage range (for example, the low level can adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels can be the same or different.
  • the minimum value of the high level is greater than the maximum value of the low level.
  • the working principle of the shift register unit 200 shown in FIG. 2B is described below in conjunction with the signal timing diagram shown in FIG. 3.
  • the first phase P1 the second phase P2, the third phase P3, and the fourth phase shown in FIG.
  • the potential level of the signal timing diagram shown in FIG. 3 is only schematic, and does not represent the true potential value.
  • the clock signal terminal CLK inputs a low level signal
  • the input terminal IP inputs a high level signal. Since the input terminal IP inputs a high level signal, the third transistor M3 is turned on, so that the high level input from the input terminal IP charges the first capacitor C1, and the potential of the first node N1 is pulled up to the first high level.
  • the eighth transistor M8 Since the second voltage terminal VDD is configured to be connected to the DC high-level signal, the eighth transistor M8 remains turned on, and the high level input from the second voltage terminal VDD charges the third node N3. Since the potential of the first node N1 is at the first high level, the seventh transistor M7 is turned on, so that the third node N3 is electrically connected to the first voltage terminal VGL. In terms of transistor design, the eighth transistor M8 and the seventh transistor M7 can be configured (for example, the size ratio, threshold voltage, etc.) of the two transistors, when both M8 and M7 are turned on, the potential of the third node N3 is pulled It is low to a lower level, which will not turn on the fifth transistor M5 completely. Since the potential of the first node N1 is at the first high level, the sixth transistor M6 is turned on, so that the potential of the second node N2 is pulled down to a low level.
  • the ninth transistor M9 is turned on, and the turned-on ninth transistor M9 can use the low-level first voltage to pull down the potential of the second node N2 to a low level.
  • the clock signal terminal CLK inputs a low level at this time, so at this stage, the output terminal OP outputs the low level.
  • the second reset circuit 250 is the first The nine transistor M9 can also directly pull down the potential of the second node N2 to a low level, so as to ensure that the potential of the second node N2 will not affect the charging process of the first node N1, thereby enabling the charging of the first node N1 More fully, the reliability of the product using the shift register unit 200 is improved.
  • the clock signal terminal CLK inputs a high-level signal
  • the input terminal IP inputs a low-level signal. Since the input terminal IP inputs a low level signal, the third transistor M3 is turned off, and the first node N1 maintains the first high level of the previous stage, so that the fourth transistor M4 remains on, because the clock signal terminal CLK is input at this stage High level, so the output terminal OP outputs the high level.
  • the high level can pass through the parasitic capacitance of the fourth transistor M4 (including the parasitic capacitance between the gate and the first pole, and the gate and the second stage
  • the parasitic capacitance between) and the first capacitance C1 raise the potential coupling of the first node N1 to the second high level, so that the fourth transistor M4 is turned on more fully.
  • the sixth transistor M6 continues to be turned on, so that the potential of the second node N2 continues to be maintained at a low level.
  • the signal input from the clock signal terminal CLK changes from a high level to a low level, and the low level is output to the output terminal OP through the turned-on fourth transistor M4.
  • the level change of the clock signal terminal CLK will pull down the potential coupling of the first node N1 to the first high level through the parasitic of the turned-on fourth transistor M4 and the first capacitor C1.
  • the twelfth transistor M12 is turned on, so that the first node N1 is electrically connected to the first voltage terminal VGL, and the potential of the first node N1 is pulled down to Low level, so that the fourth transistor M4 is turned off.
  • the sixth transistor M6 and the seventh transistor M7 are turned off, the discharge path of the third node N3 and the second node N2 is cut off, and the potential of the second node N2 is charged to a high level, As a result, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the potentials of the first node N1 and the output terminal OP are respectively pulled down to the low level input by the first voltage terminal VGL, thereby further eliminating the shift register unit 200
  • the noise that may be generated at the output terminal OP and the first node N1 in the non-output stage improves the reliability of the product using the shift register unit 200.
  • the first transistor M1 and the second transistor M2 are turned on, so that the low-level first voltage can be applied to the first node respectively.
  • N1 and the output terminal OP perform a reset operation, so that the noise on the first node N1 and the output terminal OP can be reduced or eliminated, so that the reliability of the product using the shift register unit 200 can be improved.
  • the fifth stage P5 and the sixth stage P6 are located in the time period BL between the two display frames.
  • the fifth stage P5 is closer to the current frame than the sixth stage P6, and the sixth stage P6 Compared to the fifth stage, P5 is closer to the next frame.
  • Fig. 3 shows three examples of three frame reset signals, namely STV(1), STV(2), and STV(3). That is, the first reset circuit 230 in the shift register unit 200 may reset the first node N1 and the output terminal OP only in the fifth stage P5, or may only reset the first node N1 and the output terminal OP in the sixth stage P6. OP resets, or alternatively, the first node N1 and the output terminal OP may be reset in the fifth stage P5 and the sixth stage P6 at the same time.
  • the positions of the fifth stage P5 and the sixth stage P6 in the time period BL in FIG. 3 are only illustrative, and the embodiments of the present disclosure include but are not limited to this; the time in FIG. 3 In the segment BL, more reset operations may be performed on the first node N1 and the output terminal OP, which is not limited in the embodiment of the present disclosure.
  • FIGS. 4A and 4B The potential of the first node N1 in the shift register unit shown in FIG. 1A and the shift register unit 200 shown in FIG. 2B is simulated, and the simulation results are shown in FIGS. 4A and 4B. It should be noted that in FIG. 4A, since there are many overlapping parts of the two curves, the part enclosed by the dashed ellipse in FIG. 4A is enlarged and shown in FIG. 4B.
  • curve L1 is a simulated change curve corresponding to the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B
  • curve L2 is corresponding to the first node in the shift register unit shown in FIG. 1A.
  • the simulated change curve of the potential of the node N1. It can be seen from FIG. 4B that the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B is higher than the potential of the first node N1 in the shift register unit shown in FIG. 1A, and the difference dY 0.30439V. That is to say, compared to the shift register unit shown in FIG. 1A, the shift register unit 200 shown in FIG. The reliability of products using the shift register unit 200 can be improved.
  • FIG. 5A is a test result of actual testing of the potential of the first node N1 in the shift register unit shown in FIG. 1A and the shift register unit 200 shown in FIG. 2B.
  • Curve L3 is a test change curve corresponding to the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B
  • curve L4 is a test corresponding to the potential of the first node N1 in the shift register unit shown in FIG. 1A Curve. It can be seen from FIG. 5A that the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B is higher than the potential of the first node N1 in the shift register unit shown in FIG. 1A.
  • FIG. 5B is a test result of actual testing of the potential of the second node N2 in the shift register unit shown in FIG. 1A and the shift register unit 200 shown in FIG. 2B.
  • Curve L5 is a test change curve corresponding to the potential of the second node N2 in the shift register unit 200 shown in FIG. 2B
  • curve L6 is a test corresponding to the potential of the second node N2 in the shift register unit shown in FIG. 1A Curve. It can be seen from FIG. 5B that, relative to the potential of the second node N2 in the shift register unit shown in FIG. 1A, the potential of the second node N2 in the shift register unit 200 shown in FIG. 2B can be changed more quickly.
  • a plurality of shift register units 200 as shown in FIG. 2B can be cascaded to form a gate driving circuit, and the gate driving circuit can drive multiple rows of pixel units in the display area of the display substrate to scan and display sequentially.
  • FIG. 6 shows a schematic diagram of cascading multiple shift register units 200 as shown in FIG. 2B.
  • the output signals of the six shift register units 200 are respectively provided to the Nth row, N+1th row, N+2th row, N+3th row, N+4th row, and Nth row in the display area.
  • N+5 rows of pixel units are used to drive pixel units for scanning display.
  • N is an integer greater than or equal to 1.
  • the output terminal OP of the first shift register unit 200(1) is electrically connected to the input terminal IP of the fourth shift register unit 200(4), so that the first shift register unit 200
  • the output signal of (1) is provided to the fourth shift register unit 200(4) as an input signal
  • the output terminal OP of the second shift register unit 200(2) and the fifth shift register unit 200(5) The input terminal IP is electrically connected, so that the output signal of the second shift register unit 200(2) is provided to the fifth shift register unit 200(5) as an input signal
  • the output terminal OP is electrically connected to the input terminal IP of the sixth shift register unit 200(6), so that the output signal of the third shift register unit 200(3) is provided to the sixth shift register unit 200(6) to As an input signal; and so on, other shift register units included in the gate drive circuit can also be cascaded in this way, and will not be repeated here.
  • the output terminal OP of the nth stage shift register unit is electrically connected to the input terminal IP of the n+3 stage shift register unit, so that the output signal of the nth stage shift register unit is provided
  • the shift register unit to the n+3th stage is used as an input signal; n is an integer greater than or equal to 1.
  • other shift register units included in the gate drive circuit can also be cascaded in this way, and will not be repeated here.
  • the input terminals of the first three shift register units of the gate drive circuit can receive separate input signals.
  • the scanning reset signal terminal RST of the first shift register unit 200(1) is electrically connected to the output terminal OP of the fourth shift register unit 200(4), so that the fourth shift register The output signal of the unit 200(4) is provided to the first shift register unit 200(1) as a scanning reset signal; the scanning reset signal terminal RST of the second shift register unit 200(2) and the fifth shift register unit The output terminal OP of 200(5) is electrically connected, so that the output signal of the fifth shift register unit 200(5) is provided to the second shift register unit 200(2) as a scanning reset signal; the third shift register The scanning reset signal terminal RST of the unit 200(3) is electrically connected to the output terminal OP of the sixth shift register unit 200(6), so that the output signal of the sixth shift register unit 200(6) is provided to the third shift register unit 200(6).
  • the bit register unit 200(3) is used as a scanning reset signal; by analogy, other shift register units included in the gate drive circuit can also be cascaded in this way, and will not be repeated.
  • the scanning reset signal terminal RST of the nth stage shift register unit is electrically connected to the output terminal OP of the n+3 stage shift register unit, so that the n+3 stage shift register unit
  • the output signal is provided to the n-th stage shift register unit as a scan reset signal; n is an integer greater than or equal to 1.
  • the reset terminals of the last three shift register units of the gate drive circuit can receive a single scan reset signal.
  • the display substrate may further include a plurality of signal lines that provide various signals for the gate driving circuit.
  • the plurality of signal lines includes six clock signal lines (first clock signal line CLK1, second clock signal line CLK2, third clock signal line CLK3, fourth clock signal line CLK4, fifth clock signal line CLK5 and the sixth clock signal line CLK6) and the frame reset signal line STVL that provides the frame reset signal.
  • the display substrate may also include other voltage signal lines, such as voltage signal lines that provide the first voltage or the second voltage, which will not be repeated here.
  • the first shift register unit 200 (1), the second shift register unit 200 (2), the third shift register unit 200 (3), the fourth shift register unit 200 (4), the fifth shift register The clock signal terminals CLK of the unit 200(5) and the sixth shift register unit 200(6) are electrically connected to provide the required clock signal.
  • the clock signal used by the gate driving circuit is 6CLK, that is, the clock signal received by each of the six adjacent shift register units 200 is one cycle.
  • clock signal of 6CLK used in FIG. 6 is only illustrative, and the gate driving circuit may also use other clock signals such as 2CLK, 4CLK, etc., which is not limited in the embodiment of the present disclosure.
  • the frame reset signal line STVL is electrically connected to the frame reset signal terminals STV of all shift register units 200 in the gate driving circuit.
  • the display substrate may further include a timing controller 400, which is electrically connected to the aforementioned multiple clock signal lines and the frame reset signal line STVL to provide corresponding signals.
  • the display substrate 10 includes a base substrate 100 and a plurality of shift register units arranged on the base substrate.
  • the shift register unit may adopt the shift register unit 200 shown in FIG. 2B.
  • the plurality of shift register units 200 are arranged side by side along the first direction R1.
  • the multiple shift register units 200 can be cascaded to form a gate driving circuit 500, and the gate driving circuit 500 can drive multiple rows of pixel units PU in the display area 110 of the display substrate 10 for scanning display.
  • each shift register unit 200 is electrically connected to the pixel unit PU of the corresponding row through a gate line GL.
  • the base substrate 100 may be made of, for example, glass, plastic, quartz or other suitable materials, which is not limited in the embodiment of the present disclosure.
  • FIG. 8 is an exemplary layout diagram corresponding to the shift register unit 200 shown in FIG. 2B, and FIG. 9A, FIG. 9B, and FIG. 9C are respectively corresponding to the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. Layout;
  • Figure 9D is a layout diagram of part of the vias used in Figure 8;
  • Figure 10 is a schematic cross-sectional view showing the various layer structures included in the substrate 10, and Figures 11A-11B show the substrate 10 at the position including the via Schematic diagram of the cross-section.
  • the display substrate 10 includes a base substrate 100, a first conductive layer 601, a first insulating layer 602, a semiconductor layer 603, a second conductive layer 604, and a second insulating layer 605.
  • the gate of a certain transistor in the shift register unit 200 may be arranged on the first conductive layer 601
  • the first and second electrodes of the transistor may be arranged on the second conductive layer 604, and the active layer of the transistor may be It is provided on the semiconductor layer 603; for example, the first insulating layer 602 may be a gate insulating layer
  • the second insulating layer 605 may be a passivation layer.
  • FIG. 10 only schematically shows a part of the layer structure. According to needs, the display substrate 10 may also include other layer structures, which are not limited in the embodiment of the present disclosure.
  • the material of the first conductive layer 601 and the second conductive layer 604 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, which is not limited in the embodiment of the present disclosure.
  • the material of the first conductive layer 601 may be the same as the material of the second conductive layer 604, which will not be repeated here.
  • the material of the first insulating layer 602 and the second insulating layer 605 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or other suitable materials.
  • inorganic insulating materials such as SiNx, SiOx, SiNxOy
  • organic insulating materials such as organic resins, or other suitable materials.
  • each of the plurality of shift register units 200 included in the display substrate 10 includes an input circuit 210, an output circuit 220, a first reset circuit 230, and a frame reset signal Connect trace CL1.
  • the frame reset signal connection line CL1 can be connected to the frame reset signal line STVL to receive the frame reset signal.
  • the input circuit 210, the output circuit 220, and the first reset circuit 230 reference may be made to the above description of the shift register unit 200, which will not be repeated here.
  • the frame reset signal connection line CL1 extends along the second direction R2 and is configured to provide a frame reset signal to the first reset circuit 230, and the second direction R2 and the first direction R1 cross each other.
  • the second direction R2 is perpendicular to the first direction R1.
  • the second direction R2 may be the extending direction of the gate line GL.
  • the first reset circuit 230 includes a first transistor M1 and a second transistor M2. As shown in FIG. 9A, the frame reset signal is connected to the wiring CL1 and the gate G1 of the first transistor M1. And the gate G2 of the second transistor M2 is arranged on the first conductive layer 601.
  • the shift register unit 200 further includes a first transfer electrode TE1 disposed on the second conductive layer 604.
  • the gate G1 of the first transistor M1 and the gate G1 of the second transistor M2 The gate G2 is connected, and both are electrically connected to the frame reset signal connection line CL1 through the first transfer electrode TE1.
  • the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are both connected to the connection part 301.
  • the frame reset signal connection trace CL1 located on the first conductive layer 601 includes a connection portion 302
  • the first transfer electrode TE1 located on the second conductive layer 604 includes a connection portion 303 and a connection portion 304 .
  • the orthographic projections of the connecting portion 301 and the connecting portion 303 on the base substrate 100 at least partially overlap, and the orthographic projections of the connecting portion 302 and the connecting portion 304 on the base substrate 100 at least partially overlap.
  • the connecting portion 301 located on the first conductive layer 601 may be electrically connected to the connecting portion 303 located on the second conductive layer 604 through the via holes VH1 and VH2, and the connecting portion 302 located on the first conductive layer 601 may be electrically connected to the connecting portion 303 located on the second conductive layer 601 through the via holes VH3 and VH4.
  • the connection portion 304 of the second conductive layer 604 is electrically connected.
  • FIG. 11A shows a schematic diagram of the electrical connection between the connecting portion 301 located on the first conductive layer 601 and the connecting portion 303 located on the second conductive layer 604.
  • the connecting portion 303 may be directly contacted with the connecting portion 301 through the via holes VH1 and VH2, thereby achieving electrical connection.
  • the connecting portion 303 in the example shown in FIG. 11A is connected to the connecting portion 301 through two vias, and the embodiments of the present disclosure include but are not limited to this.
  • the connecting portion 303 may also be connected to the connecting portion 301 through only one via VH1.
  • the electrical connection when describing the electrical connection between a component located on the first conductive layer 601 and a component located on the second conductive layer 604, the electrical connection is described by using two vias as an example.
  • the embodiments of the present disclosure include but are not limited thereto, and the two components may also be electrically connected through one via, three vias, or more vias.
  • the frame reset signal connection trace CL1 located on the first conductive layer 601 passes through the first transfer electrode TE1 located on the second conductive layer 604 and is connected to the first conductive layer 601.
  • the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are electrically connected, so that the frame reset signal connection trace CL1 can avoid other components during the layout, making the layout simpler and more reasonable, and in addition, it can reduce walking
  • the number of layers required for the line jumper reduces the number of masks required in the process, thereby reducing the manufacturing cost of the display substrate 10.
  • the first transistor M1 and the second transistor M2 are arranged adjacently along the second direction R2.
  • the adjacent arrangement of the first transistor M1 and the second transistor M2 along the second direction R2 can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10. Therefore, the size of the frame of the display device including the display substrate 10 can be reduced, thereby facilitating the realization of a display device with a narrow frame.
  • the first transistor M1 and the second transistor M2 have the same size.
  • the length of the first transistor M1 is equal to the length of the second transistor M2
  • the width of the first transistor M1 is equal to the width of the second transistor M2.
  • the first transistor M1 and the second transistor M2 have the same aspect ratio.
  • the same size (length and width) of the first transistor M1 and the second transistor M2 with substantially rectangular outlines can make the characteristics of the two transistors the same, for example, the conduction current is equal, so that The noise reduction characteristic of the first transistor M1 to the first node N1 is the same as the noise reduction characteristic of the second transistor M2 to the output terminal OP.
  • the shift register unit 200 further includes a first voltage connection trace CL2 extending along the second direction R2.
  • the first voltage connection trace CL2 is configured to provide a first voltage to the shift register unit 200.
  • a voltage is used to reset the first node N1 and the output terminal OP in the time period BL between two display frames of the display substrate 10.
  • the first voltage is a low-level voltage.
  • the first voltage connection trace CL2, the first electrode D1 and the second electrode S1 of the first transistor M1, the first electrode D2 and the second electrode S2 of the second transistor M2 are all arranged on the second conductive layer 604.
  • the first electrode D1 of the first transistor M1 is electrically connected to the first node N1
  • the first electrode D2 of the second transistor M2 is electrically connected to the output terminal OP
  • the second electrode S1 of the first transistor M1 and the second electrode S1 of the second transistor M2 are electrically connected.
  • the poles S2 are electrically connected to the first voltage connection line CL2.
  • the shift register unit 200 further includes a branch wiring BL disposed on the second conductive layer 604 and extending along the first direction R1, and the branch wiring BL is connected to the first voltage Connect the trace CL2 connection.
  • the second pole S1 of the first transistor M1 and the second pole S2 of the second transistor M2 are respectively arranged on both sides of the branch wiring BL, and both are connected to the branch wiring BL.
  • the second pole S1 of the first transistor M1 and the second pole S2 of the second transistor M2 are electrically connected to the first voltage connection wiring CL2 through the branch wiring BL.
  • the second pole S1 of the first transistor M1 and the second pole S2 of the second transistor M2 may also be symmetrically arranged on both sides of the branch wiring BL.
  • the first transistor M1 further includes an active layer AC1 located on the semiconductor layer 603, and the second transistor M2 further includes an active layer AC2 located on the semiconductor layer 603.
  • the shift register unit 200 further includes an input signal connection line CL3 extending along the second direction R2, and the input signal connection line CL3 is configured to provide an input signal to the input circuit 210.
  • the input signal connection line CL3 of a shift register unit of a certain stage may be connected to the output terminal OP of the shift register unit of another stage.
  • the input circuit 210 includes a third transistor M3. As shown in FIG. 9A, the input signal connection wiring CL3 and the gate G3 of the third transistor M3 are both provided on the first conductive layer 601, and the gate G3 of the third transistor M3 is connected to the input signal. Connect the trace CL3 connection. In the embodiment of the present disclosure, by setting the input signal connection line CL3 connected to the input circuit 210 (the third transistor M3), it is convenient for multiple shift register units to realize cascade connection.
  • the first electrode D3 and the second electrode S3 of the third transistor M3 are both arranged on the second conductive layer 604, the first electrode D3 of the third transistor M3 and the gate G3 of the third transistor M3 Electrically connected, the second electrode S3 of the third transistor M3 is connected to the first electrode D1 of the first transistor M1, and the first node N1 is between the second electrode S3 of the third transistor M3 and the first electrode D1 of the first transistor M1 Meeting point.
  • the third transistor M3 further includes an active layer AC3 located on the semiconductor layer 603.
  • the shift register unit 200 further includes a second transfer electrode TE2 provided on the first conductive layer 601 and a third transfer electrode TE3 provided on the second conductive layer 604.
  • the orthographic projections of the connecting electrode TE2 and the third connecting electrode TE3 on the base substrate 100 at least partially overlap.
  • the second transfer electrode TE2 is connected to the gate G3 of the third transistor M3, the third transfer electrode TE3 is connected to the first electrode D3 of the third transistor M3, and the second transfer electrode TE2 is electrically connected to the third transfer electrode TE3 .
  • the second transfer electrode TE2 located on the first conductive layer 601 may be electrically connected to the third transfer electrode TE3 located on the second conductive layer 604 through the via holes VH5 and VH6.
  • the second transfer electrode TE2 directly contacts the third transfer electrode TE3 through the via holes VH5 and VH6 to achieve electrical connection.
  • the first electrode D3 of the third transistor M3 includes a first connection portion 701 extending along the first direction R1 and a plurality of first protrusions 702 extending along the second direction R2.
  • 701 is connected to the third transition electrode TE3
  • a plurality of first protrusions 702 are respectively connected to the first connection part 701, and a plurality of first recesses are formed between the plurality of first protrusions 702. That is, the shape of the orthographic projection of the first electrode D3 of the third transistor M3 on the base substrate 100 includes a plurality of U shapes.
  • the second electrode S3 of the third transistor M3 includes a second connecting portion 703 extending in the first direction R1 and a plurality of second protrusions 704 extending in the second direction R2, and the plurality of second protrusions 704 are respectively connected to the second The portions 703 are connected, and a plurality of second recesses are formed between the plurality of second protrusions 704. That is, the shape of the orthographic projection of the second electrode S3 of the third transistor M3 on the base substrate 100 includes a plurality of U shapes.
  • the plurality of first protrusions 702 extend into the plurality of second recesses between the plurality of second protrusions 704, so that the plurality of second protrusions 704 and the plurality of first protrusions 702 are sequentially along the first direction R1. Arranged at intervals.
  • adopting such a layout structure for the first electrode and the second electrode of the third transistor M3 can increase the conduction current of the third transistor M3.
  • the use of a layout structure similar to the third transistor M3 for the first pole and the second pole of other transistors can also increase the on-current of the transistor.
  • the shift register unit 200 further includes a clock signal connection trace CL4 extending along the second direction R2, and the clock signal connection trace CL4 is configured to provide a clock signal to the output circuit 220.
  • the clock signal connection line CL4 and the clock signal line (for example, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5 And one of the sixth clock signal lines CLK6) is electrically connected to receive the clock signal.
  • the output circuit 220 includes a fourth transistor M4 and a first capacitor C1. As shown in FIG. 9A, the gate G4 of the fourth transistor M4 and the first electrode 801 of the first capacitor C1 are disposed on the first conductive layer 601, and the first electrode 801 of the first capacitor C1 is disposed on the gate of the fourth transistor M4. G4 is close to the side of the display area 110 of the display substrate 10.
  • the first electrode D4 and the second electrode S4 of the fourth transistor M4, the second electrode 802 of the first capacitor C1, and the clock signal connection wiring CL4 are all disposed on the second conductive layer 604.
  • the fourth transistor M4 further includes an active layer AC4 located on the semiconductor layer 603.
  • the fourth transistor M4 includes a plurality of sub-transistors ST connected in parallel along the second direction R2, and each sub-transistor ST includes a gate provided on the first conductive layer 601 and a gate provided on the first conductive layer 601.
  • the gates of the multiple sub-transistors ST are connected to each other, the first electrodes of the multiple sub-transistors ST are connected to each other, the second electrodes of the multiple sub-transistors ST are connected to each other, and the active layers of the multiple sub-transistors ST are sequentially arranged along the second direction R2, and Independent of each other and not connected.
  • the fourth transistor M4 adopts a form in which a plurality of sub-transistors ST are connected in parallel, which can improve the driving capability of the output signal of the fourth transistor M4.
  • the orthographic projection portions of the clock signal connection trace CL4 and the input signal connection trace CL3 on the base substrate 100 are parallel and partially overlapped.
  • the input signal connection trace CL3 and the clock signal connection trace CL4 are respectively arranged on the first conductive layer 601 and the second conductive layer 604, so that the two traces can avoid each other, so that The layout of the display substrate 10 is simpler and more reasonable.
  • the gate G4 of the fourth transistor M4 is electrically connected to the second pole S3 of the third transistor M3, and the first pole D4 of the fourth transistor M4 is connected to the clock signal connection line CL4 to receive the clock.
  • the second pole S4 of the fourth transistor M4 is connected to the first pole D2 of the second transistor M2.
  • the first electrode 801 of the first capacitor C1 is connected to the gate G4 of the fourth transistor M4, and the second electrode 802 of the first capacitor C1 is connected to the second electrode 802 of the fourth transistor M4.
  • the shift register unit 200 further includes a fourth transfer electrode TE4 arranged on the first conductive layer 601 and a fifth transfer electrode TE5 arranged on the second conductive layer 604.
  • the orthographic projections of the connecting electrode TE4 and the fifth connecting electrode TE5 on the base substrate at least partially overlap, and the fourth connecting electrode TE4 and the fifth connecting electrode TE5 are electrically connected.
  • the fourth transfer electrode TE4 located on the first conductive layer 601 may be electrically connected to the fifth transfer electrode TE5 located on the second conductive layer 604 through the via holes VH7 and VH8.
  • the fourth transfer electrode TE4 is in direct contact with the fifth transfer electrode TE5 through the via holes VH7 and VH8 to achieve electrical connection.
  • the fourth transfer electrode TE4 is between the gate G3 of the third transistor M3 and the gate G1 of the first transistor M1, and the fifth transfer electrode TE5 is between the second electrode S3 of the third transistor M3 and the second electrode S3 of the first transistor M1. Between one pole D1.
  • the fourth transfer electrode TE4 is electrically connected to the gate G4 of the fourth transistor M4, and the fifth transfer electrode TE5 is connected to the first electrode D1 of the first transistor M1 and the second electrode S3 of the third transistor M3.
  • the shift register unit 200 further includes a first connection electrode CE1 disposed on the first conductive layer 601, and two ends of the first connection electrode CE1 are respectively connected to the gate G4 and the gate G4 of the fourth transistor M4
  • the fourth transfer electrode TE4 is connected.
  • the first connection electrode CE1 is located on a side of the input signal connection trace CL3 close to the first transistor M1, and the first connection electrode CE1 is parallel to the orthographic projection portion of the input signal connection trace CL3 on the base substrate 100.
  • the gate G4 of the fourth transistor M4 is connected to the second electrode S3 of the third transistor M3 through the first connection electrode CE1, the fourth transfer electrode TE4, the via holes VH7 and VH8, and the fifth transfer electrode TE5.
  • Electric connection Using this method of connecting electrodes and switching electrodes to achieve electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the amount of work in the process. The number of masks is required, thereby reducing the manufacturing cost of the display substrate 10.
  • the shift register unit 200 further includes a control circuit 240 configured to control the level of the second node N2 according to the level of the first node N1.
  • control circuit 240 For the control circuit 240, reference may be made to the above description of the shift register unit 200, which will not be repeated here.
  • the control circuit 240 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.
  • the eighth transistor M8, the seventh transistor M7, and the sixth transistor M6 are arranged adjacent to each other in the second direction R2
  • the fifth transistor M5 and the eighth transistor M8 are arranged adjacent to each other in the first direction R1
  • the sixth transistor M6 The third transistor M3 and the third transistor M3 are adjacently arranged along the first direction R1.
  • the use of this arrangement can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10, thereby reducing the area including the display substrate 10.
  • the size of the frame of the display device is beneficial to realize a display device with a narrow frame.
  • the fifth transistor M5 further includes an active layer AC5 located on the semiconductor layer 603; the sixth transistor M6 further includes an active layer AC6 located on the semiconductor layer 603; the seventh transistor M7 further includes an active layer AC5 located on the semiconductor layer 603 Source layer AC7; the eighth transistor M8 also includes an active layer AC8 located on the semiconductor layer 603.
  • the gate G8 of the eighth transistor M8 is electrically connected to the first electrode D8 of the eighth transistor M8, and is configured to receive a second voltage different from the first voltage.
  • the second voltage is a high-level voltage.
  • the second electrode S8 of the eighth transistor M8 is connected to the first electrode D7 of the seventh transistor M7, the gate G7 of the seventh transistor M7 is connected to the gate G6 of the sixth transistor M6, and the second electrode S7 of the seventh transistor M7 is connected to
  • the first voltage connection line CL2 is connected to receive a low-level first voltage.
  • the gate G5 of the fifth transistor M5 is electrically connected to the second electrode S8 of the eighth transistor M8, the first electrode D5 of the fifth transistor M5 is electrically connected to the first electrode D6 of the sixth transistor M6, and the second electrode D6 of the fifth transistor M5 is electrically connected.
  • the pole S5 is electrically connected to the first pole D8 of the eighth transistor M8, the gate G6 of the sixth transistor M6 is connected to the fourth transfer electrode TE4, and the second pole S6 of the sixth transistor M6 is connected to the first voltage connection line CL2 .
  • the second node N2 is a junction point of the first electrode D5 of the fifth transistor M5 and the first electrode D6 of the sixth transistor M6.
  • the shift register unit 200 further includes a sixth transfer electrode TE6 provided on the first conductive layer 601 and a seventh transfer electrode TE7 provided on the second conductive layer 604.
  • the orthographic projections of the connecting electrode TE6 and the seventh connecting electrode TE7 on the base substrate 100 at least partially overlap, and the sixth connecting electrode TE6 is electrically connected to the seventh connecting electrode TE7.
  • the sixth transfer electrode TE6 located on the first conductive layer 601 may be electrically connected to the seventh transfer electrode TE7 located on the second conductive layer 604 through the via holes VH9 and VH10.
  • the sixth transfer electrode TE6 is in direct contact with the seventh transfer electrode TE7 through the via holes VH9 and VH10 to achieve electrical connection.
  • the sixth transfer electrode TE6 is between the gate G5 of the fifth transistor M5 and the gate G8 of the eighth transistor M8, and is connected to the gate G8 of the eighth transistor M8.
  • the seventh transfer electrode TE7 is between the second electrode S5 of the fifth transistor M5 and the first electrode D8 of the eighth transistor M8, and is connected to the second electrode S5 of the fifth transistor M5 and the first electrode D8 of the eighth transistor M8 Both are connected.
  • the gate G8 of the eighth transistor M8 is electrically connected to the first electrode D8 of the eighth transistor M8 through the sixth transfer electrode TE6, the via holes VH9 and VH10, and the seventh transfer electrode TE7.
  • Using the transfer electrode to realize the electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the number of masks required in the process. Therefore, the manufacturing cost of the display substrate 10 is reduced.
  • the shift register unit 200 further includes an eighth transfer electrode TE8 provided on the first conductive layer 601 and a ninth transfer electrode TE9 provided on the second conductive layer 604.
  • the orthographic projections of the connecting electrode TE8 and the ninth connecting electrode TE9 on the base substrate 100 at least partially overlap, and the eighth connecting electrode TE8 and the ninth connecting electrode TE9 are electrically connected.
  • the eighth transfer electrode TE8 on the first conductive layer 601 may be electrically connected to the ninth transfer electrode TE9 on the second conductive layer 604 through the via holes VH11 and VH12.
  • the eighth transfer electrode TE8 directly contacts the ninth transfer electrode TE9 through the via holes VH11 and VH12 to achieve electrical connection.
  • the eighth transfer electrode TE8 is on the side of the sixth transfer electrode TE6 close to the display area 110, and the eighth transfer electrode TE8 and the sixth transfer electrode TE6 are opposite to each other along the second direction R2. Neighboring arrangement.
  • the ninth transition electrode TE9 is on a side of the seventh transition electrode TE7 close to the display area 110, and the ninth transition electrode TE9 and the seventh transition electrode TE7 are adjacently arranged along the second direction R2.
  • the eighth transfer electrode TE8 is connected to the gate G5 of the fifth transistor M5, and the ninth transfer electrode TE9 is connected to the second electrode S8 of the eighth transistor M8 and the first electrode D7 of the seventh transistor M7. That is, the gate G5 of the fifth transistor M5 is electrically connected to the second electrode S8 of the eighth transistor M8 through the eighth transfer electrode TE8, the via holes VH11 and VH12, and the ninth transfer electrode TE9.
  • Using the transfer electrode to realize the electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the number of masks required in the process. Therefore, the manufacturing cost of the display substrate 10 is reduced.
  • the shift register unit 200 further includes a second reset circuit 250 configured to control the level of the second node N2 in response to an input signal.
  • a second reset circuit 250 configured to control the level of the second node N2 in response to an input signal.
  • the second reset circuit 250 includes a ninth transistor M9. As shown in FIG. 8, the fifth transistor M5, the ninth transistor M9, and the third transistor M3 are sequentially arranged along the second direction R2, and the ninth transistor M9 and the seventh transistor M7 They are arranged adjacently along the first direction R1. In the embodiment of the present disclosure, the use of this arrangement can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10, thereby reducing the area including the display substrate 10. The size of the frame of the display device is beneficial to realize a display device with a narrow frame.
  • the gate G9 of the ninth transistor M9 is disposed on the first conductive layer 601, and the first electrode D9 and the second electrode S9 of the ninth transistor M9 are disposed on the second conductive layer 604.
  • the ninth transistor M9 further includes an active layer AC9 located on the semiconductor layer 603.
  • the gate G9 of the ninth transistor M9 is connected to the second transfer electrode TE2
  • the first electrode D9 of the ninth transistor M9 is connected to the first electrode D5 of the fifth transistor M5
  • the ninth transistor M9 is connected to the first electrode D5 of the fifth transistor M5.
  • the second pole S9 of M9 is connected to the second pole S7 of the seventh transistor M7.
  • the second transfer electrode TE2 is located between the gate G9 of the ninth transistor M9 and the gate G3 of the third transistor M3.
  • the shift register unit 200 further includes a second connection electrode CE2 provided on the second conductive layer 604. Both ends of the second connecting electrode CE2 are respectively connected to the first electrode D9 of the ninth transistor M9 and the first electrode D6 of the sixth transistor M6.
  • the first electrode D5 of the fifth transistor M5 is electrically connected to the first electrode D6 of the sixth transistor M6 through the first electrode D9 of the ninth transistor M9 and the second connection electrode CE2.
  • the shift register unit 200 further includes a third reset circuit 260 configured to perform control on the first node N1 and the output terminal OP under the control of the level of the second node N2. Reset.
  • the third reset circuit 260 reference may be made to the above description of the shift register unit 200, which is not repeated here.
  • the third reset circuit 260 includes a tenth transistor M10 and an eleventh transistor M11. As shown in FIG. 8, the tenth transistor M10 and the eleventh transistor M11 are arranged adjacent to each other along the second direction R2. The transistors M1 are arranged adjacently along the first direction R1, and the eleventh transistor M11 and the second transistor M2 are arranged adjacently along the first direction R1. In the embodiment of the present disclosure, the use of this arrangement can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10, thereby reducing the area including the display substrate 10. The size of the frame of the display device is beneficial to realize a display device with a narrow frame.
  • the length of the eleventh transistor M11 is equal to the length of the second transistor M2; for example, the length of the eleventh transistor M11 is also equal to the length of the first transistor M1; for example, , The width of the eleventh transistor M11 is greater than the width of the second transistor M2.
  • the length of the tenth transistor M10 is smaller than the length of the eleventh transistor M11.
  • the width of the tenth transistor M10 is equal to the width of the eleventh transistor M11.
  • the layout can be made more compact, and the layout space can be saved, thereby reducing the size of the layout.
  • the area occupied by the peripheral area of the display substrate 10 can thereby reduce the size of the frame of the display device including the display substrate 10, thereby facilitating the realization of a display device with a narrow frame.
  • the gate G10 of the tenth transistor M10 and the gate G11 of the eleventh transistor M11 are arranged on the first conductive layer 601, and the first electrode D10 and the second electrode S10 of the tenth transistor M10, And the first electrode D11 and the second electrode S11 of the eleventh transistor M11 are arranged on the second conductive layer 604.
  • the tenth transistor M10 further includes an active layer AC10 located on the semiconductor layer 603, and the eleventh transistor M11 further includes an active layer AC11 located on the semiconductor layer 603.
  • the gate G10 of the tenth transistor M10 is connected to the gate G11 of the eleventh transistor M11, and the gate G10 of the tenth transistor M10 and the gate G11 of the eleventh transistor M11 are both connected to
  • the second node N2 is electrically connected
  • the first electrode D10 of the tenth transistor M10 is connected to the first electrode D1 of the first transistor M1
  • the first electrode D11 of the eleventh transistor M11 is connected to the first electrode D2 of the second transistor M2
  • the second pole S10 of the tenth transistor M10 and the second pole S11 of the eleventh transistor M11 are both electrically connected to the first voltage connection line CL2.
  • the second pole S10 of the tenth transistor M10 and the second pole S11 of the eleventh transistor M11 are both connected to the branch wiring BL, thereby achieving electrical connection with the first voltage connection wiring CL2.
  • the shift register unit 200 further includes a tenth transfer electrode TE10 arranged on the first conductive layer 601 and an eleventh transfer electrode TE11 arranged on the second conductive layer 604,
  • the orthographic projections of the transfer electrode TE10 and the eleventh transfer electrode TE11 on the base substrate 100 at least partially overlap, and the tenth transfer electrode TE10 is electrically connected to the eleventh transfer electrode TE11.
  • the tenth transfer electrode TE10 on the first conductive layer 601 may be electrically connected to the eleventh transfer electrode TE11 on the second conductive layer 604 through the via holes VH13 and VH14.
  • the tenth transfer electrode TE10 is in direct contact with the eleventh transfer electrode TE11 through the via holes VH13 and VH14 to achieve electrical connection.
  • the tenth transfer electrode TE10 is between the gate G6 of the sixth transistor M6 and the gate G10 of the tenth transistor M10, and is connected to the gate G10 of the tenth transistor M10.
  • the eleventh transfer electrode T11 is connected to the first electrode D6 of the sixth transistor M6.
  • the gate G10 of the tenth transistor M10 and the gate G11 of the eleventh transistor M11 are connected to the sixth transistor M6 through the tenth transfer electrode TE10, the via holes VH13 and VH14, and the eleventh transfer electrode TE11.
  • the electrical connection of the first pole D6 is to realize the electrical connection with the second node N2.
  • Using the transfer electrode to realize the electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the number of masks required in the process. Therefore, the manufacturing cost of the display substrate 10 is reduced.
  • the shift register unit 200 further includes a fourth reset circuit 270 configured to reset the first node N1 in response to a scan reset signal.
  • a fourth reset circuit 270 configured to reset the first node N1 in response to a scan reset signal.
  • the fourth reset circuit 270 includes a twelfth transistor M12. As shown in FIG. 8, the twelfth transistor M12 is located on the side of the first capacitor C1 close to the display area 110. That is, the twelfth transistor M12 is located between the first capacitor C1 and the display area 110. In this way, the twelfth transistor M12 can be more easily connected to the output terminals of other shift register units to receive the scan reset signal, namely , It is convenient for multiple shift register units to realize cascade connection.
  • the gate G12 of the twelfth transistor M12 is disposed on the first conductive layer 601, and the first electrode D12 and the second electrode S12 of the twelfth transistor M12 are disposed on the second conductive layer 604.
  • the twelfth transistor M12 further includes an active layer AC12 located on the semiconductor layer 603.
  • the gate G12 of the twelfth transistor M12 is configured to receive a scan reset signal.
  • the gate G12 of the twelfth transistor M12 in a certain stage of shift register unit 200 can be connected to the output terminal OP of another stage of shift register unit to receive scanning. Reset signal.
  • the first electrode D12 of the twelfth transistor M12 is electrically connected to the first node N1, and the second electrode S12 of the twelfth transistor M12 is connected to the first voltage connection line CL2 to receive a low-level first voltage.
  • the shift register unit 200 further includes a twelfth transfer electrode TE12 disposed on the second conductive layer 604, and the twelfth transfer electrode TE12 is connected to the first electrode D12 of the twelfth transistor M12.
  • the orthographic projection of the twelfth transfer electrode TE12 and the first electrode 801 of the first capacitor C1 on the base substrate 100 at least partially overlap, and the twelfth transfer electrode TE12 is electrically connected to the first electrode 801 of the first capacitor C1 .
  • the twelfth transfer electrode TE12 may be electrically connected to the first electrode 801 of the first capacitor C1 through the via holes VH15 and VH16.
  • the twelfth transfer electrode TE12 is in direct contact with the first electrode 801 of the first capacitor C1 through the via holes VH15 and VH16 to achieve electrical connection.
  • the first electrode D12 of the twelfth transistor M12 is electrically connected to the first node N1 through the twelfth transfer electrode TE12, the via holes VH15 and VH16, and the first electrode 801 of the first capacitor C1.
  • the shift register unit 200 further includes a thirteenth transfer electrode TE13 provided on the first conductive layer 601 and a fourteenth transfer electrode TE14 provided on the second conductive layer 604 ,
  • the orthographic projections of the thirteenth transfer electrode TE13 and the fourteenth transfer electrode TE14 on the base substrate 100 at least partially overlap, and the thirteenth transfer electrode TE13 and the fourteenth transfer electrode TE14 are electrically connected.
  • the thirteenth transfer electrode TE13 on the first conductive layer 601 can be electrically connected to the fourteenth transfer electrode TE14 on the second conductive layer 604 through the via holes VH17 and VH18.
  • the thirteenth transfer electrode TE13 is in direct contact with the fourteenth transfer electrode TE14 through the via holes VH17 and VH18 to achieve electrical connection.
  • the fourteenth transition electrode TE14 is connected to the second electrode 802 (output terminal OP) of the first capacitor C1.
  • the thirteenth transfer electrode TE13 in the shift register unit 200 of a certain stage can be connected to the gate G12 of the twelfth transistor M12 of the shift register unit of another stage. It is connected to provide a scanning reset signal, or connected to the input signal connection line CL3 of the shift register unit of other stages to provide an input signal; that is, it is convenient for multiple shift register units to realize cascade connection.
  • the components located on the first conductive layer 601 for example, the gate of the transistor
  • the components located on the second conductive layer 604 can be made by appropriately setting the transfer electrodes and the via holes. (For example, the first stage or the second pole of the transistor) is electrically connected, so as to realize the corresponding circuit structure.
  • the layout of the display substrate 10 can be made more reasonable and compact.
  • the number of layers required for wiring jumpers can be reduced, and the number of masks required in the process can be reduced, thereby reducing the manufacturing cost of the display substrate 10.
  • the planar shape of the gates G1 to G12 of the respective transistors of the shift register unit 200 is a block shape, for example, all are substantially rectangular.
  • the planar shapes of the active layers AC1 to AC12 of the respective transistors of the shift register unit 200 are block-shaped, for example, are substantially rectangular, and are arranged substantially uniformly, thereby facilitating contact with the block-shaped gate G1.
  • ⁇ G12 corresponds to and facilitates the realization of the patterning process for the semiconductor layer and the maintenance of the etching uniformity during the etching process.
  • each transistor of the shift register unit 200 has a block-like planar shape, for example, substantially uniform. It is rectangular, corresponding to the bulk active layers AC1 to AC12, and defines one or more U-shaped channel regions in combination, which increases the channel width while reducing the channel length, thereby increasing the channel length of each transistor.
  • the width-to-length ratio of the channel area helps to improve the switching performance of each transistor.
  • FIG. 1C is a layout diagram corresponding to the shift register unit shown in FIG. 1A. Comparing FIG. 1C and FIG. 8, it can be found that there is a large gap space between each transistor in the shift register unit shown in FIG. 1C, the layout is not compact, and a lot of layout space is wasted.
  • the layout of the display substrate 10 can be made more compact by designing the layout of each transistor and wiring in the shift register unit. Therefore, the layout space is saved, so that the area occupied by the peripheral area of the display substrate 10 can be reduced, and the frame size of the display device including the display substrate 10 can be reduced, thereby facilitating the realization of a display device with a narrow frame.
  • the shape of the orthographic projection of one of the first pole and the second pole (for example, the first stage) of any transistor in the shift register unit 200 on the base substrate 100 includes at least one U-shaped
  • the shape of the orthographic projection of the other of the first electrode and the second electrode (for example, the second electrode) of the transistor on the base substrate 100 includes at least one I-shaped.
  • the first electrode D1 of the first transistor M1, the first electrode D2 of the second transistor M2, the first electrode D5 of the fifth transistor M5, the first electrode D7 of the seventh transistor M7, and the first electrode of the eighth transistor M8 The shape of the orthographic projection of the first electrode D9 of the ninth transistor M9 and the first electrode D12 of the twelfth transistor M12 on the base substrate 100 is a U-shape, the second electrode S1 of the first transistor M1 and the second transistor The second pole S2 of M2, the second pole S5 of the fifth transistor M5, the second pole S7 of the seventh transistor M7, the second pole S8 of the eighth transistor M8, the second pole S9 of the ninth transistor M9, the twelfth pole
  • the shape of the orthographic projection of the second pole S12 of the transistor M12 on the base substrate 100 is an I-shape, and the second pole pair of the above-mentioned transistor extends into the corresponding first pole.
  • the first electrode D3 of the third transistor M3, the first electrode D4 of the fourth transistor M4, the first electrode D6 of the sixth transistor M6, the first electrode D10 of the tenth transistor M10, and the first electrode D10 of the eleventh transistor M11 The shape of the orthographic projection of one pole D11 on the base substrate 100 includes a plurality of U shapes, the second pole S3 of the third transistor M3, the second pole S4 of the fourth transistor M4, the second pole S6 of the sixth transistor M6, The shape of the orthographic projection of the second electrode S10 of the tenth transistor M10 and the second electrode S11 of the eleventh transistor M11 on the base substrate 100 includes a plurality of U shapes, and the first and second electrodes of the above-mentioned transistors cross each other .
  • the orthographic projection of the gate of any transistor in the shift register unit 200 on the base substrate 100 covers the orthographic projection of the active layer of the transistor on the base substrate.
  • the orthographic projection of the gate of any transistor on the base substrate 100 can be made to coincide with the orthographic projection of the active layer of the transistor on the base substrate.
  • the material of the semiconductor layer 603 may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
  • the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)).
  • IGZO indium gallium zinc oxide
  • polysilicon includes low-temperature polysilicon or high-temperature polysilicon, etc., which is not limited in the embodiments of the present disclosure.
  • FIG. 12 is a layout diagram corresponding to the schematic diagram of cascading multiple shift register units shown in FIG. 6.
  • 13A, 13B, and 13C are layout diagrams corresponding to the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. 12, respectively.
  • the multiple shift register units include a first shift register unit 200(1) and a second shift register unit 200(2) that are adjacently arranged in the first direction R1.
  • the bit register unit 200(1) and the second shift register unit 200(2) share the same first voltage connection line CL2, and are distributed axisymmetrically with respect to the first voltage connection line CL2.
  • the third shift register unit 200(3) and the fourth shift register unit 200(4) share the same first voltage connection line CL2, and are distributed axisymmetrically with respect to the first voltage connection line CL2;
  • the five shift register unit 200(5) and the sixth shift register unit 200(6) share the same first voltage connection line CL2, and are distributed axisymmetrically with respect to the first voltage connection line CL2.
  • two adjacent shift register units share the same first voltage connection trace, which can reduce the number of first voltage connection traces by half, thereby saving the first voltage connection trace.
  • the layout space corresponding to the voltage connection traces makes the layout of the display substrate 10 more compact and saves layout space, so that the area occupied by the peripheral area of the display substrate 10 can be reduced, thereby reducing the size of the display substrate 10
  • the size of the frame of the display device facilitates the realization of a display device with a narrow frame.
  • the plurality of shift register units include a first shift register unit 200(1) and a second shift register unit 200 arranged adjacently in the first direction R1.
  • the input circuit 210 (input signal connection line CL3) in the fourth shift register unit 200(4) is connected to the output circuit 220 (the thirteenth transfer electrode TE13) of the first shift register unit 200(1) to The output signal of the first shift register unit 200(1) is used as the input signal of the fourth shift register unit 200(4).
  • At least one embodiment of the present disclosure further provides a display device 1.
  • the display device 1 includes any display substrate 10 provided by the embodiment of the present disclosure.
  • the display device 1 in this embodiment can be: LCD panel, LCD TV, display, OLED panel, OLED TV, QLED panel, QLED TV, electronic paper, mobile phone, tablet computer, notebook computer, digital photo frame, Any product or component with a display function, such as a navigator.
  • the display device 1 may also include other conventional components such as a display panel, which is not limited in the embodiment of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示基板和显示装置。该显示基板(10)包括衬底基板(100)以及设置在衬底基板上的多个移位寄存器单元(200)，多个移位寄存器单元(200)沿第一方向(R1)并列排布；多个移位寄存器单元(200)中的每个包括输入电路(210)、输出电路(220)、第一复位电路(230)和帧复位信号连接走线(STVL)；帧复位信号连接走线(STVL)沿第二方向(R2)延伸，且被配置为向第一复位电路(230)提供帧复位信号；第一复位电路(230)被配置为响应于帧复位信号，以在显示基板(10)的两个显示帧之间的时间段内对第一节点(N1)以及输出端(OP)进行复位；第一复位电路(230)包括第一晶体管(M1)和第二晶体管(M2)，帧复位信号连接走线(STVL)、第一晶体管(M1)的栅极(G1)以及第二晶体管(M2)的栅极(G2)设置在第一导电层(601)；移位寄存器单元(200)还包括设置在第二导电层(604)的第一转接电极(TE1)。本公开的实施例提供的显示基板以及显示装置可以提高产品的信赖性。

Description

显示基板和显示装置
本申请要求于2020年6月24日递交的中国专利申请第202010592567.8号的优先权，出于所有目的，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
在显示技术领域，例如液晶显示的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate-driver On Array)来对栅线进行驱动。
例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素单元提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
发明内容
本公开至少一实施例提供一种显示基板，包括：衬底基板以及设置在所述衬底基板上的多个移位寄存器单元，所述多个移位寄存器单元沿第一方向并列排布；所述多个移位寄存器单元中的每个包括输入电路、输出电路、第一复位电路和帧复位信号连接走线；所述帧复位信号连接走线沿第二方向延伸，且被配置为向所述第一复位电路提供帧复位信号，所述第二方向与所述第一方向彼此交叉；所述输入电路被配置为响应于输入信号以控制第一节点的电平；所述输出电路被配置为接收时钟信号，并在所述第一节点的电平的控制下将所述时钟信号作为输出信号输出至输出端；所述第一复位电路被配置为响应于所述帧复位信号，以在所述显示基板的两个显示帧之间的时间段内对所述第一节点以及所述输出端进行复位；所述第一复位电路包括第一晶体管和第二晶体管，所述帧复位信号连接走线、所述第一晶体管的栅极以及所述第二晶体管的栅极设置在第一导电层；所述移位寄存器单元还包括设置在第二导电层的第一转接电极，所述第一晶体管的栅极与所述第二晶体管的栅极连接，且均通过所述第一转接电极与所述帧复位信号连接走线电连接。
例如，在本公开一实施例提供的显示基板中，所述第一晶体管与所述第二晶体管沿所述第二方向相邻排布；所述移位寄存器单元还包括沿所述第二方向延伸的第一电压连接走线，所述第一电压连接走线被配置为向所述移位寄存器单元提供第一电压，所述第一电压用于在所述显示基板的两个显示帧之间的时间段内对所述第一节点以及所述输出端进行复位；所述第一电压连接走线、所述第一晶体管的第一极和第二极、所述第二晶体管的第一 极和第二极均设置在所述第二导电层；所述第一晶体管的第一极与所述第一节点电连接，所述第二晶体管的第一极与所述输出端电连接，所述第一晶体管的第二极以及所述第二晶体管的第二极均与所述第一电压连接走线电连接。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在所述第二导电层且沿所述第一方向延伸的分支走线，所述分支走线与所述第一电压连接走线连接；所述第一晶体管的第二极和所述第二晶体管的第二极分别布置在所述分支走线的两侧，且均与所述分支走线连接。
例如，在本公开一实施例提供的显示基板中，所述第一晶体管与所述第二晶体管的尺寸相同。
例如，在本公开一实施例提供的显示基板中，所述多个移位寄存器单元包括在所述第一方向上相邻设置的第一移位寄存器单元和第二移位寄存器单元，所述第一移位寄存器单元与所述第二移位寄存器单元共用同一条所述第一电压连接走线，且相对于所述第一电压连接走线轴对称分布。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括沿所述第二方向延伸的输入信号连接走线，所述输入信号连接走线被配置为向所述输入电路提供所述输入信号；所述输入电路包括第三晶体管，所述输入信号连接走线以及所述第三晶体管的栅极均设置在所述第一导电层，所述第三晶体管的栅极与所述输入信号连接走线连接；所述第三晶体管的第一极和第二极均设置在所述第二导电层，所述第三晶体管的第一极与所述第三晶体管的栅极电连接，所述第三晶体管的第二极与所述第一晶体管的第一极连接，且所述第一节点为所述第三晶体管的第二极与所述第一晶体管的第一极的汇合点。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在所述第一导电层的第二转接电极以及设置在所述第二导电层的第三转接电极，所述第二转接电极和所述第三转接电极在所述衬底基板上的正投影至少部分重叠；所述第二转接电极与所述第三晶体管的栅极连接，所述第三转接电极与所述第三晶体管的第一极连接，所述第二转接电极与所述第三转接电极电连接。
例如，在本公开一实施例提供的显示基板中，所述第三晶体管的第一极包括沿所述第一方向延伸的第一连接部以及多个沿所述第二方向延伸的第一突出部，所述第一连接部与所述第三转接电极连接，所述多个第一突出部分别与所述第一连接部连接，所述多个第一突出部之间形成多个第一凹陷部；所述第三晶体管的第二极包括沿所述第一方向延伸的第二连接部以及多个沿所述第二方向延伸的第二突出部，所述多个第二突出部分别与所述第二连接部连接，所述多个第二突出部之间形成多个第二凹陷部；所述多个第一突出部伸入所述多个第二凹陷部中，以使得所述多个第二突出部和所述多个第一突出部沿所述第一方向依次间隔排布。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括沿所述第二方向延伸的时钟信号连接走线，所述时钟信号连接走线被配置为向所述输出电路提供时钟信号；所述输出电路包括第四晶体管和第一电容；所述第四晶体管的栅极以及所述第一电 容的第一极设置在所述第一导电层，且所述第一电容的第一极位于所述第四晶体管的栅极靠近所述显示基板的显示区域的一侧；所述第四晶体管的第一极和第二极、所述第一电容的第二极以及所述时钟信号连接走线均设置在所述第二导电层；所述第四晶体管的栅极与所述第三晶体管的第二极电连接，所述第四晶体管的第一极与所述时钟信号连接走线连接以接收所述时钟信号，所述第四晶体管的第二极与所述第二晶体管的第一极连接；所述第一电容的第一极与所述第四晶体管的栅极连接，所述第一电容的第二极与所述第四晶体管的第二极连接。
例如，在本公开一实施例提供的显示基板中，所述第四晶体管包括多个沿所述第二方向并联的子晶体管，每个所述子晶体管包括设置在所述第一导电层的栅极、设置在所述第二导电层的第一极和第二极、以及设置在半导体层的有源层；多个所述子晶体管的栅极彼此连接，多个所述子晶体管的第一极彼此连接，多个所述子晶体管的第二极彼此连接，多个所述子晶体管的有源层沿所述第二方向依次排布，且彼此独立不连接。
例如，在本公开一实施例提供的显示基板中，所述时钟信号连接走线与所述输入信号连接走线在所述衬底基板上的正投影部分平行，且部分重叠。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在所述第一导电层的第四转接电极和设置在所述第二导电层的第五转接电极，所述第四转接电极和所述第五转接电极在所述衬底基板上的正投影至少部分重叠，且所述第四转接电极与所述第五转接电极电连接；所述第四转接电极在所述第三晶体管的栅极与所述第一晶体管的栅极之间，所述第五转接电极在所述第三晶体管的第二极与所述第一晶体管的第一极之间；所述第四转接电极与所述第四晶体管的栅极电连接，所述第五转接电极与所述第一晶体管的第一极以及所述第三晶体管的第二极连接。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在所述第一导电层的第一连接电极，所述第一连接电极的两端分别与所述第四晶体管的栅极以及所述第四转接电极连接；所述第一连接电极位于所述输入信号连接走线靠近所述第一晶体管的一侧，且所述第一连接电极与所述输入信号连接走线在所述衬底基板上的正投影部分平行。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括控制电路，所述控制电路配置为根据所述第一节点的电平控制第二节点的电平；所述控制电路包括第五晶体管、第六晶体管、第七晶体管以及第八晶体管，所述第五晶体管的栅极、所述第六晶体管的栅极、所述第七晶体管的栅极以及所述第八晶体管的栅极均设置在所述第一导电层，所述第五晶体管的第一极和第二极、所述第六晶体管的第一极和第二极、所述第七晶体管的第一极和第二极以及所述第八晶体管的第一极和第二极均设置在所述第二导电层；所述第八晶体管的栅极与所述第八晶体管的第一极电连接，且被配置为接收不同于所述第一电压的第二电压，所述第八晶体管的第二极与所述第七晶体管的第一极连接，所述第七晶体管的栅极与所述第六晶体管的栅极连接，所述第七晶体管的第二极与所述第一电压连接走线连接；所述第五晶体管的栅极与所述第八晶体管的第二极电连接，所述第五晶体管 的第一极与所述第六晶体管的第一极电连接，所述第五晶体管的第二极与所述第八晶体管的第一极电连接，所述第六晶体管的栅极与所述第四转接电极连接，所述第六晶体管的第二极与所述第一电压连接走线连接；所述第二节点为所述第五晶体管的第一极与所述第六晶体管的第一极的汇合点。
例如，在本公开一实施例提供的显示基板中，所述第八晶体管、所述第七晶体管以及所述第六晶体管沿所述第二方向依次相邻排布，所述第五晶体管和所述第八晶体管沿所述第一方向相邻排布，所述第六晶体管和所述第三晶体管沿所述第一方向相邻排布。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在所述第一导电层的第六转接电极和设置在所述第二导电层的第七转接电极，所述第六转接电极和所述第七转接电极在所述衬底基板上的正投影至少部分重叠，且所述第六转接电极与所述第七转接电极电连接；所述第六转接电极在所述第五晶体管的栅极与所述第八晶体管的栅极之间，且与所述第八晶体管的栅极连接；所述第七转接电极在所述第五晶体管的第二极与所述第八晶体管的第一极之间，且与所述第五晶体管的第二极以及所述第八晶体管的第一极均连接。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在所述第一导电层的第八转接电极和设置在所述第二导电层的第九转接电极，所述第八转接电极和所述第九转接电极在所述衬底基板上的正投影至少部分重叠，且所述第八转接电极与所述第九转接电极电连接；所述第八转接电极在所述第六转接电极靠近所述显示区域的一侧，且所述第八转接电极与所述第六转接电极沿所述第二方向相邻排布；所述第九转接电极在所述第七转接电极靠近所述显示区域的一侧，且所述第九转接电极与所述第七转接电极沿所述第二方向相邻排布；所述第八转接电极与所述第五晶体管的栅极连接，所述第九转接电极与所述第八晶体管的第二极以及所述第七晶体管的第一极连接。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括第二复位电路，所述第二复位电路被配置为响应于所述输入信号以控制所述第二节点的电平；所述第二复位电路包括第九晶体管，所述第九晶体管的栅极设置在所述第一导电层，所述第九晶体管的第一极和第二极设置在所述第二导电层；所述第九晶体管的栅极与所述第二转接电极连接，所述第九晶体管的第一极与所述第五晶体管的第一极连接，所述第九晶体管的第二极与所述第七晶体管的第二极连接。
例如，在本公开一实施例提供的显示基板中，所述第五晶体管、所述第九晶体管以及所述第三晶体管沿所述第二方向依次排布；所述第二转接电极位于所述第九晶体管的栅极与所述第三晶体管的栅极之间；所述第九晶体管与所述第七晶体管沿所述第一方向相邻排布。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在第二导电层的第二连接电极，所述第二连接电极的两端分别与所述第九晶体管的第一极以及所述第六晶体管的第一极连接。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括第三复位电 路，所述第三复位电路被配置为在所述第二节点的电平的控制下对所述第一节点以及所述输出端进行复位；所述第三复位电路包括第十晶体管和第十一晶体管；所述第十晶体管的栅极和所述第十一晶体管的栅极设置在所述第一导电层，所述第十晶体管的第一极和第二极、以及所述第十一晶体管的第一极和第二极设置在所述第二导电层；所述第十晶体管的栅极与所述第十一晶体管的栅极连接，且所述第十晶体管的栅极和所述第十一晶体管的栅极均与所述第二节点电连接，所述第十晶体管的第一极与所述第一晶体管的第一极连接，所述第十一晶体管的第一极与所述第二晶体管的第一极连接，所述第十晶体管的第二极和所述第十一晶体管的第二极均与所述第一电压连接走线电连接。
例如，在本公开一实施例提供的显示基板中，所述第十晶体管和所述第十一晶体管沿所述第二方向相邻排布，所述第十晶体管和所述第一晶体管沿所述第一方向相邻排布，所述第十一晶体管和所述第二晶体管沿所述第一方向相邻排布。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在所述第一导电层的第十转接电极以及设置在所述第二导电层的第十一转接电极，所述第十转接电极和所述第十一转接电极在所述衬底基板上的正投影至少部分重叠，且所述第十转接电极与所述第十一转接电极电连接；所述第十转接电极在所述第六晶体管的栅极与所述第十晶体管的栅极之间，且与所述第十晶体管的栅极连接；所述第十一转接电极与所述第六晶体管的第一极连接。
例如，在本公开一实施例提供的显示基板中，所述第十一晶体管的长与所述第二晶体管的长相等，所述第十晶体管的长小于所述第十一晶体管的长，所述第十晶体管的宽与所述第十一晶体管的宽相等。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括第四复位电路，所述第四复位电路被配置为响应于扫描复位信号对所述第一节点进行复位；所述第四复位电路包括第十二晶体管，所述第十二晶体管位于所述第一电容靠近所述显示区域的一侧；所述第十二晶体管的栅极设置在所述第一导电层，所述第十二晶体管的第一极和第二极设置在所述第二导电层；所述第十二晶体管的栅极被配置为接收所述扫描复位信号，所述第十二晶体管的第一极与所述第一节点电连接，所述第十二晶体管的第二极与所述第一电压连接走线连接。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元还包括设置在第二导电层的第十二转接电极，所述第十二转接电极与所述第十二晶体管的第一极连接，所述第十二转接电极和所述第一电容的第一极在所述衬底基板上的正投影至少部分重叠，且所述第十二转接电极与所述第一电容的第一极电连接。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元中的任意一个晶体管的第一极和第二极中的一个在所述衬底基板上的正投影的形状包括至少一个U型，该晶体管的第一极和第二极中的另一个在所述衬底基板上的正投影的形状包括至少一个I型。
例如，在本公开一实施例提供的显示基板中，所述移位寄存器单元中的任意一个晶体管的栅极在所述衬底基板上的正投影覆盖该晶体管的有源层在所述衬底基板上的正投影。
例如，在本公开一实施例提供的显示基板中，所述多个移位寄存器单元包括在所述第一方向上依次相邻设置的第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元以及第四移位寄存器单元；所述第四移位寄存器单元中的输入电路与所述第一移位寄存器单元的输出电路连接，以将所述第一移位寄存器单元的输出信号作为所述第四移位寄存器单元的输入信号。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种移位寄存器单元的电路示意图；
图1B为对应于图1A中所示的移位寄存器单元工作时的信号时序图；
图1C为对应图1A中所示的移位寄存器单元的布局图；
图2A为本公开至少一实施例提供的一种移位寄存器单元的示意图；
图2B为本公开至少一实施例提供的一种移位寄存器单元的电路示意图；
图3为对应于图2B中所示的移位寄存器单元工作时的信号时序图；
图4A为图1A中所示的移位寄存器单元和图2B中所示的移位寄存器单元中的第一节点的电位的仿真图；
图4B为将图4A中的虚线椭圆所围成的部分放大后的示意图；
图5A为对图1A中所示的移位寄存器单元和图2B中所示的移位寄存器单元中的第一节点的电位进行实际测试的测试结果；
图5B为对图1A中所示的移位寄存器单元和图2B中所示的移位寄存器单元中的第二节点的电位进行实际测试的测试结果；
图6示出了一种多个如图2B所示的移位寄存器单元进行级联的示意图；
图7为本公开至少一实施例提供的一种显示基板的示意图；
图8为对应图2B所示的移位寄存器单元的布局图；
图9A、图9B、图9C分别为对应图8中的第一导电层、第二导电层以及半导体层的布局图；
图9D为图8中所采用的过孔的布局图；
图10为本公开至少一实施例提供的一种显示基板所包括的各个层结构的截面示意图；
图11A为本公开至少一实施例提供的一种显示基板在包括过孔的位置处的截面示意图；
图11B为本公开至少一实施例提供的一种显示基板在包括过孔的位置处的截面示意图；
图12为对应于图6所示的多个移位寄存器单元级联的示意图的布局图；
图13A、图13B、图13C分别为对应图12中的第一导电层、第二导电层以及半导体 层的布局图；以及
图14为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示面板技术中，为了实现低成本和窄边框，可以采用GOA(Gate-driver On Array)技术，即将栅极驱动电路通过薄膜晶体管工艺集成在显示面板的阵列基板上，从而可以实现窄边框和降低装配成本等优势。该显示面板可以为液晶显示(LCD)面板、有机发光二极管(OLED)显示面板或量子点发光二极管(QLED)显示面板。
图1A示出了一种移位寄存器单元的电路示意图，多个该移位寄存器单元可以被级联以形成栅极驱动电路。如图1A所示，该移位寄存器单元包括九个晶体管(T1至T9)和存储电容(C0)。图1C为对应图1A中所示的移位寄存器单元的布局图，对应地示出了各个晶体管在显示基板上的位置以及相关电极、有源层、走线等。
关于该移位寄存器单元中的各个晶体管以及存储电容的连接关系可以参考图1A，这里不再一一赘述。例如，上述晶体管均为N型晶体管。下面也以N型晶体管为例进行说明，但是本公开的实施例不限于这种情形，例如这些晶体管中至少部分可以替换为P型晶体管。
例如，图1A中的第一电压端VGL被配置为连接至直流低电平信号，第二电压端VDD被配置为连接至直流高电平信号，下面结合图1B所示的信号时序图来说明图1A所示的移位寄存器单元的工作原理，在图1B所示的第一阶段S1、第二阶段S2、第三阶段S3以及第四阶段S4共四个阶段中，该移位寄存器单元进行如下操作。
在第一阶段S1，时钟信号端CLK输入低电平信号，输入端IP输入高电平信号。由于输入端IP输入高电平信号，第一晶体管T1导通，使得输入端IP输入的高电平对存储电容C0进行充电，第一节点N1的电位被拉高至第一高电平。例如，在本公开的实施例中，第 一节点N1可以为上拉节点(PU)。
由于第二电压端VDD被配置为连接至直流高电平信号，所以第五晶体管T5保持导通，第二电压端VDD输入的高电平对第三节点N3进行充电。例如，在本公开的实施例中，第三节点N3可以为下拉控制节点(PD_CN)。
又由于第一节点N1的电位为第一高电平，第六晶体管T6导通，从而使得第三节点N3和第一电压端VGL电连接。在晶体管的设计上，可以将第五晶体管T5和第六晶体管T6配置为(例如对二者的尺寸比、阈值电压等配置)在T5和T6均导通时，第三节点N3的电位被拉低到一个较低的电平，该低电平不会使第三晶体管T3完全开启。又由于第一节点N1的电位为第一高电平，第四晶体管T4导通，使得第二节点N2的电位被拉低至低电平。例如，在本公开的实施例中，第二节点N2可以为下拉节点(PD)。
需要说明的是，图1B中所示的信号时序图的电位高低仅是示意性的，不代表真实电位值。
由于第一节点N1处于第一高电平，第二晶体管T2导通，此时时钟信号端CLK输入低电平，所以在此阶段，输出端OP输出该低电平。
在第二阶段S2，时钟信号端CLK输入高电平信号，输入端IP输入低电平信号。由于输入端IP输入低电平信号，第一晶体管T1截止，第一节点N1保持上一阶段的第一高电平，从而使得第二晶体管T2保持导通，由于在此阶段时钟信号端CLK输入高电平，所以输出端OP输出该高电平。
同时，由于时钟信号端CLK以及输出端OP为高电平，该高电平可以通过第二晶体管T2的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)和存储电容C0将第一节点N1的电位耦合升高至第二高电平，使得第二晶体管T2的导通更充分。由于第一节点N1的电位为高电平，第四晶体管T4继续导通，使得第二节点N2的电位继续保持在低电平。
在第三阶段S3，时钟信号端CLK输入的信号由高电平变为低电平，该低电平通过导通的第二晶体管T2输出至输出端OP。另外，时钟信号端CLK的电平变化会通过导通的第二晶体管T2的寄生以及存储电容C0将第一节点N1的电位耦合拉低至第一高电平。
在第四阶段S4，由于扫描复位信号端RST输入高电平信号，第九晶体管T9导通，使得第一节点N1与第一电压端VGL电连接，第一节点N1的电位被拉低到低电平，从而第二晶体管T2截止。
由于第一节点N1的电位处于低电平，第六晶体管T6和第四晶体管T4截止，第三节点N3和第二节点N2的放电路径被截止，第二节点N2的电位被充电至高电平，由此使得第七晶体管T7和第八晶体管T8导通，分别将第一节点N1以及输出端OP的电位拉低到第一电压端VGL输入的低电平，进一步消除了移位寄存器单元在非输出阶段其输出端和第一节点N1处可能产生的噪声。
上述移位寄存器单元在工作时，在第一阶段S1中，需要第五晶体管T5和第六晶体管T6满足一定的配置关系(例如二者的尺寸比例满足一定的配置关系)，才可以使得第三节 点N3的电位被拉低到一个较低的电平。如果第三节点N3的电位无法将第三晶体管T3完全关闭，此时第二电压端VDD的高电平信号就会对第二节点N2进行充电，从而造成第七晶体管T7部分开启，这将会影响第一节点N1的充电过程，严重时可能会影响输出端OP的正常输出。
也就是说，图1A所示的移位寄存器单元在工作时，对第一节点N1的充电和放电存在竞争关系，可能会造成对第一节点N1的充电不足；另外，随着使用时间的积累，该移位寄存器单元中的各个晶体管的阈值电压可能会发生漂移，且各个晶体管的阈值电压的漂移量可能会不同，这也会影响上述竞争关系，从而影响对第一节点N1的充电过程，进而影响产品寿命。
本公开至少一实施例提供一种移位寄存器单元，该移位寄存器单元可以避免第一节点的充电和放电存在竞争关系，使得对第一节点的充电更充分，从而可以提高采用该移位寄存器单元的产品的信赖性。另外，还可以在两个显示帧之间的时间段内对第一节点以及输出端进行复位以降低噪声的影响，从而可以提高采用该移位寄存器单元的产品的信赖性。
另外，本公开至少一实施例还提供一种包括上述移位寄存器单元的显示基板，通过对移位寄存器单元中的晶体管以及连接走线进行合理的排布，可以使得该显示基板的布局更加紧凑，从而可以减小该显示基板中的周边区域所占用的面积，从而可以减小包括该显示基板的显示装置的边框尺寸。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开的至少一实施例提供一种移位寄存器单元200，该移位寄存器单元可以被级联以形成栅极驱动电路，该栅极驱动电路可以用于显示基板中，例如驱动显示基板的显示区域中的多行像素单元进行扫描显示。
如图2A和图2B所示，该移位寄存器单元200包括输入电路210、输出电路220、第一复位电路230、控制电路240、第二复位电路250、第三复位电路260和第四复位电路270。
输入电路210被配置为响应于输入信号以控制第一节点N1的电平。例如，在本公开的实施例中，第一节点N1可以为上拉节点(PU)。例如，如图2A所示，输入电路210和输入端IP电连接，从而当输入电路210导通时可以利用输入端IP输入的输入信号对第一节点N1的电平进行控制，例如，拉高第一节点N1的电平。
例如，如图2B所示，输入电路210包括第三晶体管M3。第三晶体管M3的栅极G3和第三晶体管M3的第一极D3电连接，且均与输入端IP电连接以接收输入信号；第三晶体管M3的第二极S3与第一节点N1电连接。
输出电路220被配置为接收时钟信号，并在所述第一节点的电平的控制下将所述时钟信号作为输出信号输出至输出端OP。例如，如图2A所示，输出电路220和时钟信号端CLK以及输出端OP电连接，当输出电路220导通时，可以将从时钟信号端CLK接收到的时钟信号作为输出信号输出至输出端OP。
例如，如图2B所示，输出电路220包括第四晶体管M4和第一电容C1。第四晶体管 M4的栅极G4与第一节点N1电连接，第四晶体管M4的第一极D4与时钟信号端CLK电连接以接收时钟信号，第四晶体管M4的第二极S4与输出端OP电连接。第一电容C1的第一极801与第一节点N1电连接，第一电容C1的第二极802与输出端OP电连接。
第一复位电路230被配置为响应于帧复位信号，以在显示基板的两个显示帧之间的时间段内对第一节点N1以及输出端OP进行复位。例如，如图2A所示，第一复位电路230与帧复位信号端STV电连接以接收帧复位信号，第一复位电路230与第一电压端VGL电连接以接收第一电压，例如，第一电压可以为低电平电压。另外，第一复位电路230还与第一节点N1以及输出端OP电连接。在显示基板的相邻的两个显示帧之间的时间段内，当第一复位电路230响应于帧复位信号而导通时，可以利用低电平的第一电压分别对第一节点N1以及输出端OP进行复位操作，从而可以降低或消除第一节点N1以及输出端OP上的噪声，从而可以提高采用该移位寄存器单元200的产品的信赖性。
例如，如图2B所示，第一复位电路230包括第一晶体管M1和第二晶体管M2。第一晶体管M1的栅极G1与帧复位信号端STV电连接以接收帧复位信号，第一晶体管M1的第一极D1与第一节点N1电连接，第一晶体管M1的第二极S1与第一电压端VGL电连接以接收低电平的第一电压。第二晶体管M2的栅极G2与帧复位信号端STV电连接以接收帧复位信号，第二晶体管M2的第一极D2与输出端OP电连接，第二晶体管M2的第二极S2与第一电压端VGL电连接以接收低电平的第一电压。
例如，第一节点N1为第三晶体管M3的第二极S3与第一晶体管M1的第一极D1以及第四晶体管M4的栅极G4的汇合点。
控制电路240配置为根据第一节点N1的电平控制第二节点N2的电平。例如，在本公开的实施例中，第二节点N2可以为下拉节点(PD)。例如，如图2A所示，控制电路240与第一电压端VGL电连接以接收低电平的第一电压；控制电路240与第二电压端VDD电连接以接收不同于第一电压的第二电压，例如，第二电压可以为高电平电压。另外，控制电路240还与第一节点N1以及第二节点N2电连接。例如，当第一节点N1的电平为高电平时，控制电路240控制第二节点N2的电平为低电平；当第一节点N1的电平为低电平时，控制电路240结合从第二电压端VDD接收到的高电平的第二电压可以控制使得第二节点N2的电平为高电平。
例如，如图2B所示，该控制电路240包括第五晶体管M5、第六晶体管M6、第七晶体管M7以及第八晶体管M8。第八晶体管M8的栅极G8与第八晶体管M8的第一极D8电连接，且均与第二电压端VDD电连接以接收高电平的第二电压；第八晶体管M8的第二极S8与第三节点N3电连接，例如，第三节点N3可以为下拉控制节点(PD_CN)。第七晶体管M7的栅极G7与第一节点N1电连接，第七晶体管M7的第一极D7与第三节点N3电连接，第七晶体管M7的第二极S7与第一电压端VGL电连接以接收低电平的第一电压。第五晶体管M5的栅极G5与第三节点N3电连接，第五晶体管M5的第一极D5与第二节点N2电连接，第五晶体管M5的第二极S5与第二电压端VDD电连接以接收高电平的第二电压。第六晶体管M6的栅极与第一节点N1电连接，第六晶体管M6的第一极 D6与第二节点N2电连接，第六晶体管M6的第二极S6与第一电压端VGL电连接以接收低电平的第一电压。
例如，第二节点N2为第五晶体管M5的第一极D5与第六晶体管M6的第一极D6的汇合点；第三节点N3为第八晶体管M8的第二极S8与第五晶体管M5的栅极G5以及第七晶体管M7的第一极D7的汇合点。
需要说明的是，在本公开的实施例中，各个节点(第一节点N1、第二节点N2、第三节点N3)和各个信号端(输入端IP、输出端OP、帧复位信号端STV、扫描复位信号端RST、时钟信号端CLK等)均是为了更好地描述电路结构而设置的，并非表示实际存在的部件。节点表示电路结构中相关电路连接的汇合点，即与具有相同节点标识连接的相关电路彼此之间是电连接的。
第二复位电路250被配置为响应于输入信号以控制第二节点N2的电平。例如，如图2A所示，第二复位电路250与输入端IP电连接以接收输入信号，第二复位电路250还与第一电压端VGL电连接以接收低电平的第一电压。另外，第二复位电路250还与第二节点N2电连接。例如，当输入电路210利用输入信号对第一节点N1进行充电时，该第二复位电路250可以响应于该输入信号而导通，从而可以利用低电平的第一电压控制第二节点N2的电平，例如，将第二节点N2的电位拉低至低电平。
在本公开的上述实施例提供的移位寄存器单元200中，通过设置第二复位电路250可以使得第二节点N2的电位不影响对第一节点N1的充电过程，使得对第一节点N1的充电更充分，从而可以提高采用该移位寄存器单元200的产品的信赖性。
例如，如图2B所示，该第二复位电路250包括第九晶体管M9。第九晶体管M9的栅极G9与输入端IP电连接以接收输入信号，第九晶体管M9的第一极D9与第二节点N2电连接，第九晶体管M9的第二极S9与第一电压端VGL电连接以接收低电平的第一电压。
第三复位电路260被配置为在第二节点N2的电平的控制下对第一节点N1以及输出端OP进行复位。例如，如图2A所示，第三复位电路260与第一电压端VGL电连接以接收低电平的第一电压，另外，第三复位电路260还与第一节点N1、第二节点N2以及输出端OP电连接。例如，当第三复位电路260在第二节点N2的电平的控制下导通时(例如，第二节点N2的电平为高电平)，可以利用低电平的第一电压分别对第一节点N1以及输出端OP进行复位，从而可以降低或消除第一节点N1以及输出端OP上的噪声。
例如，如图2B所示，第三复位电路260包括第十晶体管M10和第十一晶体管M11。第十晶体管M10的栅极G10与第二节点N2电连接，第十晶体管M10的第一极D10与第一节点N1电连接，第十晶体管M10的第二极S10与第一电压端VGL电连接以接收低电平的第一电压。第十一晶体管M11的栅极G11与第二节点N2电连接，第十一晶体管M11的第一极D11与输出端OP电连接，第十一晶体管M11的第二极S11与第一电压端VGL电连接以接收低电平的第一电压。
第四复位电路270被配置为响应于扫描复位信号对第一节点N1进行复位，例如，拉低第一节点N1的电平，从而降低第一节点N1上可能存在的噪声。例如，如图2A所示， 第四复位电路270与扫描复位信号端RST电连接以接收扫描复位信号，以及与第一电压端VGL电连接以接收低电平的第一电压。另外，第四复位电路270还与第一节点N1电连接。例如，当第四复位电路270响应于扫描复位信号而导通时，可以利用低电平的第一电压对第一节点N1进行复位，从而拉低第一节点N1的电平。
例如，如图2B所示，该第四复位电路270包括第十二晶体管M12。第十二晶体管M12的栅极G12与扫描复位信号端RST电连接以接收扫描复位信号，第十二晶体管M12的第一极D12与第一节点N1电连接，第十二晶体管M12的第二极S12与第一电压端VGL电连接以接收低电平的第一电压。
需要说明的是，在上述描述图2B所示的移位寄存器单元200中的连接关系时，均采用了“电连接”。这里，两个部件“电连接”表明该两个部件之间是电气连接的，包括直接连接和间接连接，即在对应的布局图中，该两个部件可以直接连接(例如一体化形成)以实现电气连接，或者该两个部件可以通过设置在该两个部件之间的其它部件以实现电气连接。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极(即源极和漏极)，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
另外，需要说明的是，在本公开的实施例中，高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合适的电压)，且多个高电平可以相同也可以不同。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个低电平可以相同也可以不同。例如，高电平的最小值比低电平的最大值大。
下面结合图3所示的信号时序图来描述图2B所示的移位寄存器单元200的工作原理，在图3所示的第一阶段P1、第二阶段P2、第三阶段P3、第四阶段P4、第五阶段P5以及第六阶段P6共六个阶段中，该移位寄存器单元200进行如下操作。需要说明的是，图3中所示的信号时序图的电位高低仅是示意性的，不代表真实电位值。
在第一阶段P1，时钟信号端CLK输入低电平信号，输入端IP输入高电平信号。由于输入端IP输入高电平信号，第三晶体管M3导通，使得输入端IP输入的高电平对第一电容C1进行充电，第一节点N1的电位被拉高至第一高电平。
由于第二电压端VDD被配置为连接至直流高电平信号，所以第八晶体管M8保持导通，第二电压端VDD输入的高电平对第三节点N3进行充电。又由于第一节点N1的电位 为第一高电平，第七晶体管M7导通，从而使得第三节点N3和第一电压端VGL电连接。在晶体管的设计上，可以将第八晶体管M8和第七晶体管M7配置为(例如对二者的尺寸比、阈值电压等配置)在M8和M7均导通时，第三节点N3的电位被拉低到一个较低的电平，该低电平不会使第五晶体管M5完全开启。又由于第一节点N1的电位为第一高电平，第六晶体管M6导通，使得第二节点N2的电位被拉低至低电平。
另外，由于输入端IP输入高电平信号，使得第九晶体管M9导通，导通的第九晶体管M9可以利用低电平的第一电压将第二节点N2的电位拉低至低电平。
由于第一节点N1处于第一高电平，第四晶体管M4导通，此时时钟信号端CLK输入低电平，所以在此阶段，输出端OP输出该低电平。
如上所述，当图2B所示的移位寄存器单元200工作在第一阶段S1时，即使控制电路240不能完全将第二节点N2的电位拉低至低电平，第二复位电路250即第九晶体管M9也可以直接将第二节点N2的电位拉低至低电平，从而保证第二节点N2的电位不会影响对第一节点N1的充电过程，从而可以使得对第一节点N1的充电更充分，提高采用该移位寄存器单元200的产品的信赖性。
在第二阶段P2，时钟信号端CLK输入高电平信号，输入端IP输入低电平信号。由于输入端IP输入低电平信号，第三晶体管M3截止，第一节点N1保持上一阶段的第一高电平，从而使得第四晶体管M4保持导通，由于在此阶段时钟信号端CLK输入高电平，所以输出端OP输出该高电平。
同时，由于时钟信号端CLK以及输出端OP为高电平，该高电平可以通过第四晶体管M4的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)和第一电容C1将第一节点N1的电位耦合升高至第二高电平，使得第四晶体管M4的导通更充分。由于第一节点N1的电位为高电平，第六晶体管M6继续导通，使得第二节点N2的电位继续保持在低电平。
在第三阶段P3，时钟信号端CLK输入的信号由高电平变为低电平，该低电平通过导通的第四晶体管M4输出至输出端OP。另外，时钟信号端CLK的电平变化会通过导通的第四晶体管M4的寄生以及第一电容C1将第一节点N1的电位耦合拉低至第一高电平。
在第四阶段P4，由于扫描复位信号端RST输入高电平信号，第十二晶体管M12导通，使得第一节点N1与第一电压端VGL电连接，第一节点N1的电位被拉低到低电平，从而第四晶体管M4截止。
由于第一节点N1的电位处于低电平，第六晶体管M6和第七晶体管M7截止，第三节点N3和第二节点N2的放电路径被截止，第二节点N2的电位被充电至高电平，由此使得第十晶体管M10和第十一晶体管M11导通，分别将第一节点N1以及输出端OP的电位拉低到第一电压端VGL输入的低电平，进一步消除了移位寄存器单元200在非输出阶段其输出端OP和第一节点N1处可能产生的噪声，提高采用该移位寄存器单元200的产品的信赖性。
在第五阶段P5或第六阶段P6，由于帧复位信号端STV输入高电平信号，第一晶体管 M1和第二晶体管M2导通，从而可以利用低电平的第一电压分别对第一节点N1以及输出端OP进行复位操作，从而可以降低或消除第一节点N1以及输出端OP上的噪声，从而可以提高采用该移位寄存器单元200的产品的信赖性。
需要说明的是，第五阶段P5和第六阶段P6位于两个显示帧之间的时间段BL内，例如，第五阶段P5相对于第六阶段P6更靠近于当前帧，而第六阶段P6相对于第五阶段P5更靠近于后一帧。图3中示出了三种帧复位信号的三种示例，分别为STV(1)、STV(2)、STV(3)。即，移位寄存器单元200中的第一复位电路230可以仅在第五阶段P5对第一节点N1以及输出端OP进行复位，或者，可以仅在第六阶段P6对第一节点N1以及输出端OP进行复位，又或者，可以同时在第五阶段P5和第六阶段P6对第一节点N1以及输出端OP进行复位。
另外，需要说明的是，图3中的第五阶段P5以及第六阶段P6在时间段BL中的位置仅是示意性的，本公开的实施例包括但不限于此；在图3中的时间段BL内，还可以对第一节点N1以及输出端OP进行更多次的复位操作，本公开的实施例对此不作限制。
对图1A中所示的移位寄存器单元和图2B中所示的移位寄存器单元200中的第一节点N1的电位进行仿真，仿真结果如图4A和4B所示。其中需要说明的是，在图4A中，由于两条曲线重合的部分较多，故将图4A中的虚线椭圆所围成的部分放大后示于图4B。
如图4B所示，曲线L1为对应图2B所示的移位寄存器单元200中的第一节点N1的电位的仿真变化曲线，曲线L2为对应图1A所示的移位寄存器单元中的第一节点N1的电位的仿真变化曲线。从图4B可以看出，图2B所示的移位寄存器单元200中的第一节点N1的电位高于图1A所示的移位寄存器单元中的第一节点N1的电位，且差值dY＝0.30439V。也就是说，相对于图1A所示的移位寄存器单元，采用图2B所示的移位寄存器单元200可以使得对第一节点N1的充电更充分，使得第一节点N1的电位更高，从而可以提高采用该移位寄存器单元200的产品的信赖性。
图5A为对图1A中所示的移位寄存器单元和图2B中所示的移位寄存器单元200中的第一节点N1的电位进行实际测试的测试结果。曲线L3为对应图2B所示的移位寄存器单元200中的第一节点N1的电位的测试变化曲线，曲线L4为对应图1A所示的移位寄存器单元中的第一节点N1的电位的测试变化曲线。从图5A可以看出，图2B所示的移位寄存器单元200中的第一节点N1的电位高于图1A所示的移位寄存器单元中的第一节点N1的电位。
图5B为对图1A中所示的移位寄存器单元和图2B中所示的移位寄存器单元200中的第二节点N2的电位进行实际测试的测试结果。曲线L5为对应图2B所示的移位寄存器单元200中的第二节点N2的电位的测试变化曲线，曲线L6为对应图1A所示的移位寄存器单元中的第二节点N2的电位的测试变化曲线。从图5B可以看出，相对于图1A所示的移位寄存器单元中的第二节点N2的电位，图2B所示的移位寄存器单元200中的第二节点N2的电位可以更快地被拉低至低电平，从而降低第二节点N2的电位对第一节点N1的电位的影响，从而使得对第一节点N1的充电更充分，从而可以提高采用该移位寄存器单元 200的产品的信赖性。
多个如图2B所示的移位寄存器单元200可以级联构成一个栅极驱动电路，该栅极驱动电路可以驱动显示基板的显示区域中的多行像素单元依次进行扫描显示。
图6示出了一种多个如图2B所示的移位寄存器单元200进行级联的示意图。需要说明的是，图6中仅示意性地示出了六个移位寄存器单元200，例如，分别为第一移位寄存器单元200(1)、第二移位寄存器单元200(2)、第三移位寄存器单元200(3)、第四移位寄存器单元200(4)、第五移位寄存器单元200(5)、第六移位寄存器单元200(6)。例如，该六个移位寄存器单元200的输出信号分别被提供至显示区域中的第N行、第N+1行、第N+2行、第N+3行、第N+4行、第N+5行像素单元，以驱动像素单元进行扫描显示。例如，N为大于等于1的整数。
在图6所示的示例中，第一移位寄存器单元200(1)的输出端OP与第四移位寄存器单元200(4)的输入端IP电连接，从而使得第一移位寄存器单元200(1)的输出信号被提供至第四移位寄存器单元200(4)以作为输入信号；第二移位寄存器单元200(2)的输出端OP与第五移位寄存器单元200(5)的输入端IP电连接，从而使得第二移位寄存器单元200(2)的输出信号被提供至第五移位寄存器单元200(5)以作为输入信号；第三移位寄存器单元200(3)的输出端OP与第六移位寄存器单元200(6)的输入端IP电连接，从而使得第三移位寄存器单元200(3)的输出信号被提供至第六移位寄存器单元200(6)以作为输入信号；以此类推，该栅极驱动电路中包括的其它移位寄存器单元也可以按照这种方式进行级联，不再赘述。
在上述栅极驱动电路中，第n级移位寄存器单元的输出端OP与第n+3级移位寄存器单元的输入端IP电连接，从而使得第n级移位寄存器单元的输出信号被提供至第n+3级移位寄存器单元以作为输入信号；n为大于等于1的整数。以此类推，该栅极驱动电路中包括的其它移位寄存器单元也可以按照这种方式进行级联，不再赘述。
另外，需要说明的是，在图6所示的级联方式下，该栅极驱动电路的前三个移位寄存器单元的输入端可以接收单独的输入信号。
在图6所示的示例中，第一移位寄存器单元200(1)的扫描复位信号端RST与第四移位寄存器单元200(4)的输出端OP电连接，从而使得第四移位寄存器单元200(4)的输出信号被提供至第一移位寄存器单元200(1)以作为扫描复位信号；第二移位寄存器单元200(2)的扫描复位信号端RST与第五移位寄存器单元200(5)的输出端OP电连接，从而使得第五移位寄存器单元200(5)的输出信号被提供至第二移位寄存器单元200(2)以作为扫描复位信号；第三移位寄存器单元200(3)的扫描复位信号端RST与第六移位寄存器单元200(6)的输出端OP电连接，从而使得第六移位寄存器单元200(6)的输出信号被提供至第三移位寄存器单元200(3)以作为扫描复位信号；以此类推，该栅极驱动电路中包括的其它移位寄存器单元也可以按照这种方式进行级联，不再赘述。
在上述栅极驱动电路中，第n级移位寄存器单元的扫描复位信号端RST与第n+3级移位寄存器单元的输出端OP电连接，从而使得第n+3级移位寄存器单元的输出信号被提供至第n级移位寄存器单元以作为扫描复位信号；n为大于等于1的整数。以此类推，该栅 极驱动电路中包括的其它移位寄存器单元也可以按照这种方式进行级联，不再赘述。
另外，需要说明的是，在图6所示的级联方式下，该栅极驱动电路的最后三个移位寄存器单元的复位端可以接收单独的扫描复位信号。
如图6所示，在该栅极驱动电路设置在一个显示基板的情形中，该显示基板还可以包括为该栅极驱动电路提供各种信号的多条信号线。例如，该多条信号线包括提供时钟信号的六条时钟信号线(第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5以及第六时钟信号线CLK6)和提供帧复位信号的帧复位信号线STVL。需要说明的是，该显示基板还可以包括其它电压信号线，例如提供第一电压或第二电压的电压信号线，这里不再赘述。
例如，如图6所示，第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5以及第六时钟信号线CLK6分别与第一移位寄存器单元200(1)、第二移位寄存器单元200(2)、第三移位寄存器单元200(3)、第四移位寄存器单元200(4)、第五移位寄存器单元200(5)以及第六移位寄存器单元200(6)的时钟信号端CLK电连接以提供所需的时钟信号。在图6所示的示例中，该栅极驱动电路采用的时钟信号为6CLK，即每相邻的六个移位寄存器单元200所接收的时钟信号为一个循环。
需要说明的是，图6中所采用的6CLK的时钟信号仅是示意性地，该栅极驱动电路还可以采用2CLK、4CLK等其它时钟信号，本公开的实施例对此不作限定。
如图6所示，帧复位信号线STVL与该栅极驱动电路中的所有移位寄存器单元200的帧复位信号端STV均电连接。例如，该显示基板还可以包括时序控制器400，该时序控制器400与上述多条时钟信号线以及帧复位信号线STVL电连接以提供相应的信号。
本公开的至少一实施例还提供一种显示基板10。如图7所示，该显示基板10包括衬底基板100以及设置在衬底基板上的多个移位寄存器单元，例如，该移位寄存器单元可以采用图2B中所示的移位寄存器单元200。多个移位寄存器单元200沿第一方向R1并列排布。例如，该多个移位寄存器单元200级联可以构成一栅极驱动电路500，该栅极驱动电路500可以驱动显示基板10的显示区域110中的多行像素单元PU进行扫描显示。例如，每个移位寄存器单元200通过一条栅线GL与对应行的像素单元PU电连接。
在本公开的实施例中，例如，衬底基板100可以采用例如玻璃、塑料、石英或其他适合的材料，本公开的实施例对此不作限制。
图8为对应图2B所示的移位寄存器单元200的一种示例性布局图，图9A、图9B、图9C分别为对应图8中的第一导电层、第二导电层以及半导体层的布局图；图9D为图8中所采用的部分过孔的布局图；图10为显示基板10所包括的各个层结构的截面示意图，图11A-11B为显示基板10在包括过孔的位置处的截面示意图。
例如，如图10所示，以一个晶体管为例对显示基板10包括的各个层结构进行示意。例如，该显示基板10包括衬底基板100、第一导电层601、第一绝缘层602、半导体层603、第二导电层604以及第二绝缘层605。例如，移位寄存器单元200中的某一个晶体管的栅 极可以设置在第一导电层601，该晶体管的第一极和第二极可以设置在第二导电层604，该晶体管的有源层可以设置在半导体层603；例如，第一绝缘层602可以为栅绝缘层，第二绝缘层605可以为钝化层。需要说明的是，图10仅示意性地示出了部分层结构，根据需要，该显示基板10还可以包括其它层结构，本公开的实施例对此不作限定。
例如，上述第一导电层601和第二导电层604的材料可以包括钛、钛合金、铝、铝合金、铜、铜合金或其他任意适合的复合材料，本公开的实施例对此不作限定。例如，第一导电层601的材料可以与第二导电层604的材料相同，在此不再赘述。
例如，第一绝缘层602和第二绝缘层605的材料可以包括例如SiNx、SiOx、SiNxOy等无机绝缘材料、例如有机树脂等有机绝缘材料，或其它适合的材料，本公开的实施例对此不作限定。
下面结合图8-图11B对图2A和图2B中所示的移位寄存器单元200在显示基板10中的布局设计进行描述。
如图2A、图2B以及图8-图10所示，显示基板10中包括的多个移位寄存器单元200中的每个包括输入电路210、输出电路220、第一复位电路230和帧复位信号连接走线CL1。例如，该帧复位信号连接走线CL1可以与上述帧复位信号线STVL连接以接收帧复位信号。关于输入电路210、输出电路220以及第一复位电路230可以参考上述关于移位寄存器单元200的描述，这里不再赘述。
该帧复位信号连接走线CL1沿第二方向R2延伸，且被配置为向第一复位电路230提供帧复位信号，第二方向R2与第一方向R1彼此交叉。例如，在一些示例中，第二方向R2与第一方向R1垂直。例如，第二方向R2可以为栅线GL的延伸方向。
如图2B以及图8-图10所示，第一复位电路230包括第一晶体管M1和第二晶体管M2，如图9A所示，帧复位信号连接走线CL1、第一晶体管M1的栅极G1以及第二晶体管M2的栅极G2设置在第一导电层601。
如图9B所示，移位寄存器单元200还包括设置在第二导电层604的第一转接电极TE1，如图9A-9B所示，第一晶体管M1的栅极G1与第二晶体管M2的栅极G2连接，且均通过第一转接电极TE1与帧复位信号连接走线CL1电连接。例如，第一晶体管M1的栅极G1与第二晶体管M2的栅极G2均连接至连接部301。
如图9A、9B、9D所示，位于第一导电层601的帧复位信号连接走线CL1包括连接部302，位于第二导电层604的第一转接电极TE1包括连接部303和连接部304。连接部301和连接部303在衬底基板100上的正投影至少部分重叠，连接部302和连接部304在衬底基板100上的正投影至少部分重叠。位于第一导电层601的连接部301可以通过过孔VH1和VH2与位于第二导电层604的连接部303电连接，位于第一导电层601的连接部302可以通过过孔VH3和VH4与位于第二导电层604的连接部304电连接。
例如，图11A示出了位于第一导电层601的连接部301与位于第二导电层604的连接部303的电连接的示意图。例如，在形成连接部303时，可以使得连接部303通过过孔VH1和VH2与连接部301直接接触，从而实现电连接。
需要说明的是，图11A所示的示例中的连接部303是通过两个过孔与连接部301连接的，本公开的实施例包括但不限于此。例如，在其它一些示例中，如图11B所示，连接部303还可以仅通过一个过孔VH1与连接部301连接。
在本公开的实施例中，在描述位于第一导电层601的一个部件和位于第二导电层604的一个部件电连接时，均是以通过两个过孔实现电连接为例来说明的，本公开的实施例包括但不限于此，该两个部件还可以通过一个过孔、三个过孔或更多个过孔实现电连接。
在本公开的实施例提供的显示基板10中，位于第一导电层601的帧复位信号连接走线CL1通过位于第二导电层604的第一转接电极TE1后与位于第一导电层601的第一晶体管M1的栅极G1以及第二晶体管M2的栅极G2实现电连接，使得帧复位信号连接走线CL1在布局时可以避开其它部件，使得布局更加简单、合理，另外还可以减少走线跨接所需的层数，减少工艺制程中所需掩膜数量，从而降低该显示基板10的制造成本。
如图8所示，第一晶体管M1与第二晶体管M2沿第二方向R2相邻排布。在本公开的实施例中，第一晶体管M1与第二晶体管M2沿第二方向R2相邻排布可以使得布局更加紧凑，节省布局空间，从而可以减小该显示基板10中的周边区域所占用的面积，从而可以减小包括该显示基板10的显示装置的边框尺寸，从而有利于实现窄边框的显示装置。
如图8所示，在本公开的一些示例中，第一晶体管M1与第二晶体管M2的尺寸相同。例如，第一晶体管M1的长与第二晶体管M2的长相等，第一晶体管M1的宽与第二晶体管M2的宽相等。例如，第一晶体管M1与第二晶体管M2的宽长比一致。
在本公开的实施例中，使轮廓大致呈矩形的第一晶体管M1与第二晶体管M2的尺寸(长与宽)相同可以使得该两个晶体管的特性相同，例如导通电流相等，从而可以使得第一晶体管M1对第一节点N1的降噪特性与第二晶体管M2对输出端OP的降噪特性相同。
如图9B所示，移位寄存器单元200还包括沿第二方向R2延伸的第一电压连接走线CL2，第一电压连接走线CL2被配置为向移位寄存器单元200提供第一电压，第一电压用于在显示基板10的两个显示帧之间的时间段BL内对第一节点N1以及输出端OP进行复位。例如，在本公开的实施例中，第一电压为低电平电压。
如图9B所示，第一电压连接走线CL2、第一晶体管M1的第一极D1和第二极S1、第二晶体管M2的第一极D2和第二极S2均设置在第二导电层604。
第一晶体管M1的第一极D1与第一节点N1电连接，第二晶体管M2的第一极D2与输出端OP电连接，第一晶体管M1的第二极S1以及第二晶体管M2的第二极S2均与第一电压连接走线CL2电连接。
例如，在一些示例中，如图9B所示，该移位寄存器单元200还包括设置在第二导电层604且沿第一方向R1延伸的分支走线BL，该分支走线BL与第一电压连接走线CL2连接。第一晶体管M1的第二极S1和第二晶体管M2的第二极S2分别布置在分支走线BL的两侧，且均与分支走线BL连接。也就是说，第一晶体管M1的第二极S1以及第二晶体管M2的第二极S2通过该分支走线BL实现了与第一电压连接走线CL2的电连接。
例如，在其它一些示例中，第一晶体管M1的第二极S1和第二晶体管M2的第二极S2 还可以对称的布置在分支走线BL的两侧。
如图9C所示，第一晶体管M1还包括位于半导体层603的有源层AC1，第二晶体管M2还包括位于半导体层603的有源层AC2。
如图9A所示，该移位寄存器单元200还包括沿第二方向R2延伸的输入信号连接走线CL3，该输入信号连接走线CL3被配置为向输入电路210提供输入信号。例如，当多个移位寄存器单元200进行级联时，某一级移位寄存器单元的输入信号连接走线CL3可以与其它级移位寄存器单元的输出端OP连接。
输入电路210包括第三晶体管M3，如图9A所示，输入信号连接走线CL3以及第三晶体管M3的栅极G3均设置在第一导电层601，第三晶体管M3的栅极G3与输入信号连接走线CL3连接。在本公开的实施例中，通过设置与输入电路210(第三晶体管M3)连接的输入信号连接走线CL3，便于多个移位寄存器单元实现级联。
如图9A-图9B所示，第三晶体管M3的第一极D3和第二极S3均设置在第二导电层604，第三晶体管M3的第一极D3与第三晶体管M3的栅极G3电连接，第三晶体管M3的第二极S3与第一晶体管M1的第一极D1连接，且第一节点N1为第三晶体管M3的第二极S3与第一晶体管M1的第一极D1的汇合点。
如图9C所示，第三晶体管M3还包括位于半导体层603的有源层AC3。
如图9A-图9B所示，该移位寄存器单元200还包括设置在第一导电层601的第二转接电极TE2以及设置在第二导电层604的第三转接电极TE3，第二转接电极TE2和第三转接电极TE3在衬底基板100上的正投影至少部分重叠。
第二转接电极TE2与第三晶体管M3的栅极G3连接，第三转接电极TE3与第三晶体管M3的第一极D3连接，第二转接电极TE2与第三转接电极TE3电连接。
例如，如图9D所示，位于第一导电层601的第二转接电极TE2可以通过过孔VH5和VH6与位于第二导电层604的第三转接电极TE3电连接。例如，第二转接电极TE2通过过孔VH5和VH6与第三转接电极TE3直接接触从而实现电连接。
例如，如图9B所示，第三晶体管M3的第一极D3包括沿第一方向R1延伸的第一连接部701以及多个沿第二方向R2延伸的第一突出部702，第一连接部701与第三转接电极TE3连接，多个第一突出部702分别与第一连接部701连接，多个第一突出部702之间形成多个第一凹陷部。即第三晶体管M3的第一极D3在衬底基板100上的正投影的形状包括多个U型。
第三晶体管M3的第二极S3包括沿第一方向R1延伸的第二连接部703以及多个沿第二方向R2延伸的第二突出部704，多个第二突出部704分别与第二连接部703连接，多个第二突出部704之间形成多个第二凹陷部。即第三晶体管M3的第二极S3在衬底基板100上的正投影的形状包括多个U型。
多个第一突出部702伸入多个第二突出部704之间的多个第二凹陷部中，以使得多个第二突出部704和多个第一突出部702沿第一方向R1依次间隔排布。
在本公开的实施例中，第三晶体管M3的第一极和第二极采用这种布局结构可以提高 该第三晶体管M3的导通电流。类似地，在后续的描述中，其它晶体管的第一极和第二极采用类似第三晶体管M3的布局结构也可以提高该晶体管的导通电流。
如图9B所示，该移位寄存器单元200还包括沿第二方向R2延伸的时钟信号连接走线CL4，该时钟信号连接走线CL4被配置为向输出电路220提供时钟信号。例如，该时钟信号连接走线CL4与时钟信号线(例如，第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5以及第六时钟信号线CLK6中的一个)电连接以接收时钟信号。
输出电路220包括第四晶体管M4和第一电容C1。如图9A所示，第四晶体管M4的栅极G4以及第一电容C1的第一极801设置在第一导电层601，且第一电容C1的第一极801位于第四晶体管M4的栅极G4靠近显示基板10的显示区域110的一侧。
如图9B所示，第四晶体管M4的第一极D4和第二极S4、第一电容C1的第二极802以及时钟信号连接走线CL4均设置在第二导电层604。
如图9C所示，第四晶体管M4还包括位于半导体层603的有源层AC4。
例如，如图8、图9A-9C所示，第四晶体管M4包括多个沿第二方向R2并联的子晶体管ST，每个子晶体管ST包括设置在第一导电层601的栅极、设置在第二导电层604的第一极和第二极、以及设置在半导体层603的有源层。多个子晶体管ST的栅极彼此连接，多个子晶体管ST的第一极彼此连接，多个子晶体管ST的第二极彼此连接，多个子晶体管ST的有源层沿第二方向R2依次排布，且彼此独立不连接。
在本公开的实施例中，第四晶体管M4采用多个子晶体管ST并联的形式可以提高第四晶体管M4的输出信号的驱动能力。
例如，如图9A-图9B所示，时钟信号连接走线CL4与输入信号连接走线CL3在衬底基板100上的正投影部分平行，且部分重叠。在本公开的实施例中，将输入信号连接走线CL3和时钟信号连接走线CL4分别设置在第一导电层601和第二导电层604，可以使得该两条走线可以避开彼此，使得该显示基板10的布局更加简单、合理。
如图9A-图9B所示，第四晶体管M4的栅极G4与第三晶体管M3的第二极S3电连接，第四晶体管M4的第一极D4与时钟信号连接走线CL4连接以接收时钟信号，第四晶体管M4的第二极S4与第二晶体管M2的第一极D2连接。第一电容C1的第一极801与第四晶体管M4的栅极G4连接，第一电容C1的第二极802与第四晶体管M4的第二极802连接。
如图9A-图9B所示，该移位寄存器单元200还包括设置在第一导电层601的第四转接电极TE4和设置在第二导电层604的第五转接电极TE5，第四转接电极TE4和第五转接电极TE5在衬底基板上的正投影至少部分重叠，且第四转接电极TE4与第五转接电极TE5电连接。
如图9D所示，位于第一导电层601的第四转接电极TE4可以通过过孔VH7和VH8与位于第二导电层604的第五转接电极TE5电连接。例如，第四转接电极TE4通过过孔VH7和VH8与第五转接电极TE5直接接触从而实现电连接。
第四转接电极TE4在第三晶体管M3的栅极G3与第一晶体管M1的栅极G1之间，第五转接电极TE5在第三晶体管M3的第二极S3与第一晶体管M1的第一极D1之间。第四转接电极TE4与第四晶体管M4的栅极G4电连接，第五转接电极TE5与第一晶体管M1的第一极D1以及第三晶体管M3的第二极S3连接。
例如，如图9A所示，该移位寄存器单元200还包括设置在第一导电层601的第一连接电极CE1，该第一连接电极CE1的两端分别与第四晶体管M4的栅极G4以及第四转接电极TE4连接。第一连接电极CE1位于输入信号连接走线CL3靠近第一晶体管M1的一侧，且第一连接电极CE1与输入信号连接走线CL3在衬底基板100上的正投影部分平行。
也就是说，第四晶体管M4的栅极G4通过第一连接电极CE1、第四转接电极TE4、过孔VH7和VH8、第五转接电极TE5实现与第三晶体管M3的第二极S3的电连接。采用这种连接电极以及转接电极实现电连接的方式，不仅可以使得移位寄存器单元10中的晶体管的布局更加紧凑，另外还可以减少走线跨接所需的层数，减少工艺制程中所需掩膜数量，从而降低该显示基板10的制造成本。
在一些实施例中，该移位寄存器单元200还包括控制电路240，该控制电路240配置为根据第一节点N1的电平控制第二节点N2的电平。关于控制电路240可以参考上述关于移位寄存器单元200的描述，这里不再赘述。
如图8、图9A-图9B所示，该控制电路240包括第五晶体管M5、第六晶体管M6、第七晶体管M7以及第八晶体管M8。例如，第八晶体管M8、第七晶体管M7以及第六晶体管M6沿第二方向R2依次相邻排布，第五晶体管M5和第八晶体管M8沿第一方向R1相邻排布，第六晶体管M6和第三晶体管M3沿第一方向R1相邻排布。在本公开的实施例中，采用这种排布方式可以使得布局更加紧凑，节省布局空间，从而可以减小该显示基板10中的周边区域所占用的面积，从而可以减小包括该显示基板10的显示装置的边框尺寸，从而有利于实现窄边框的显示装置。
第五晶体管M5的栅极G5、第六晶体管M6的栅极G6、第七晶体管M7的栅极G7以及第八晶体管M8的栅极G8均设置在第一导电层601，第五晶体管M5的第一极D5和第二极S5、第六晶体管M6的第一极D6和第二极S6、第七晶体管M7的第一极D7和第二极S7以及第八晶体管M8的第一极D8和第二极S8均设置在第二导电层604。
如图9C所示，第五晶体管M5还包括位于半导体层603的有源层AC5；第六晶体管M6还包括位于半导体层603的有源层AC6；第七晶体管M7还包括位于半导体层603的有源层AC7；第八晶体管M8还包括位于半导体层603的有源层AC8。
如图9A-图9B所示，第八晶体管M8的栅极G8与第八晶体管M8的第一极D8电连接，且被配置为接收不同于第一电压的第二电压。例如，在本公开的实施例中，第二电压为高电平电压。
第八晶体管M8的第二极S8与第七晶体管M7的第一极D7连接，第七晶体管M7的栅极G7与第六晶体管M6的栅极G6连接，第七晶体管M7的第二极S7与第一电压连接走线CL2连接以接收低电平的第一电压。
第五晶体管M5的栅极G5与第八晶体管M8的第二极S8电连接，第五晶体管M5的第一极D5与第六晶体管M6的第一极D6电连接，第五晶体管M5的第二极S5与第八晶体管M8的第一极D8电连接，第六晶体管M6的栅极G6与第四转接电极TE4连接，第六晶体管M6的第二极S6与第一电压连接走线CL2连接。第二节点N2为第五晶体管M5的第一极D5与第六晶体管M6的第一极D6的汇合点。
如图9A-图9B所示，该移位寄存器单元200还包括设置在第一导电层601的第六转接电极TE6和设置在第二导电层604的第七转接电极TE7，第六转接电极TE6和第七转接电极TE7在衬底基板100上的正投影至少部分重叠，且第六转接电极TE6与第七转接电极TE7电连接。
如图9D所示，位于第一导电层601的第六转接电极TE6可以通过过孔VH9和VH10与位于第二导电层604的第七转接电极TE7电连接。例如，第六转接电极TE6通过过孔VH9和VH10与第七转接电极TE7直接接触从而实现电连接。
如图9A-图9B所示，第六转接电极TE6在第五晶体管M5的栅极G5与第八晶体管M8的栅极G8之间，且与第八晶体管M8的栅极G8连接。第七转接电极TE7在第五晶体管M5的第二极S5与第八晶体管M8的第一极D8之间，且与第五晶体管M5的第二极S5以及第八晶体管M8的第一极D8均连接。
如上所述，第八晶体管M8的栅极G8通过第六转接电极TE6、过孔VH9和VH10、第七转接电极TE7实现与第八晶体管M8的第一极D8的电连接。采用转接电极实现电连接的方式，不仅可以使得移位寄存器单元10中的晶体管的布局更加紧凑，另外还可以减少走线跨接所需的层数，减少工艺制程中所需掩膜数量，从而降低该显示基板10的制造成本。
如图9A-图9B所示，该移位寄存器单元200还包括设置在第一导电层601的第八转接电极TE8和设置在第二导电层604的第九转接电极TE9，第八转接电极TE8和第九转接电极TE9在衬底基板100上的正投影至少部分重叠，且第八转接电极TE8与第九转接电极TE9电连接。
如图9D所示，位于第一导电层601的第八转接电极TE8可以通过过孔VH11和VH12与位于第二导电层604的第九转接电极TE9电连接。例如，第八转接电极TE8通过过孔VH11和VH12与第九转接电极TE9直接接触从而实现电连接。
如图9A-图9B所示，第八转接电极TE8在第六转接电极TE6靠近显示区域110的一侧，且第八转接电极TE8与第六转接电极TE6沿第二方向R2相邻排布。第九转接电极TE9在第七转接电极TE7靠近显示区域110的一侧，且第九转接电极TE9与第七转接电极TE7沿第二方向R2相邻排布。
第八转接电极TE8与第五晶体管M5的栅极G5连接，第九转接电极TE9与第八晶体管M8的第二极S8以及第七晶体管M7的第一极D7连接。也就是说，第五晶体管M5的栅极G5通过第八转接电极TE8、过孔VH11和VH12、第九转接电极TE9实现与第八晶体管M8的第二极S8的电连接。采用转接电极实现电连接的方式，不仅可以使得移位寄存 器单元10中的晶体管的布局更加紧凑，另外还可以减少走线跨接所需的层数，减少工艺制程中所需掩膜数量，从而降低该显示基板10的制造成本。
在一些实施例中，该移位寄存器单元200还包括第二复位电路250，该第二复位电路250被配置为响应于输入信号以控制第二节点N2的电平。关于第二复位电路250可以参考上述关于移位寄存器单元200的描述，这里不再赘述。
第二复位电路250包括第九晶体管M9，如图8所示，第五晶体管M5、第九晶体管M9以及第三晶体管M3沿第二方向R2依次排布，且第九晶体管M9与第七晶体管M7沿第一方向R1相邻排布。在本公开的实施例中，采用这种排布方式可以使得布局更加紧凑，节省布局空间，从而可以减小该显示基板10中的周边区域所占用的面积，从而可以减小包括该显示基板10的显示装置的边框尺寸，从而有利于实现窄边框的显示装置。
如图9A-图9B所示，第九晶体管M9的栅极G9设置在第一导电层601，第九晶体管M9的第一极D9和第二极S9设置在第二导电层604。如图9C所示，第九晶体管M9还包括位于半导体层603的有源层AC9。
如图9A-图9B所示，第九晶体管M9的栅极G9与第二转接电极TE2连接，第九晶体管M9的第一极D9与第五晶体管M5的第一极D5连接，第九晶体管M9的第二极S9与第七晶体管M7的第二极S7连接。第二转接电极TE2位于第九晶体管M9的栅极G9与第三晶体管M3的栅极G3之间。
如图9B所示，该移位寄存器单元200还包括设置在第二导电层604的第二连接电极CE2。该第二连接电极CE2的两端分别与第九晶体管M9的第一极D9以及第六晶体管M6的第一极D6连接。也就是说，第五晶体管M5的第一极D5通过第九晶体管M9的第一极D9以及第二连接电极CE2实现与第六晶体管M6的第一极D6的电连接。
在一些实施例中，该移位寄存器单元200还包括第三复位电路260，该第三复位电路260被配置为在第二节点N2的电平的控制下对第一节点N1以及输出端OP进行复位。关于第三复位电路260可以参考上述关于移位寄存器单元200的描述，这里不再赘述。
第三复位电路260包括第十晶体管M10和第十一晶体管M11，如图8所示，第十晶体管M10和第十一晶体管M11沿第二方向R2相邻排布，第十晶体管M10和第一晶体管M1沿第一方向R1相邻排布，第十一晶体管M11和第二晶体管M2沿第一方向R1相邻排布。在本公开的实施例中，采用这种排布方式可以使得布局更加紧凑，节省布局空间，从而可以减小该显示基板10中的周边区域所占用的面积，从而可以减小包括该显示基板10的显示装置的边框尺寸，从而有利于实现窄边框的显示装置。
如图8所示，在本公开的一些示例中，第十一晶体管M11的长与第二晶体管M2的长相等；例如，第十一晶体管M11的长还与第一晶体管M1的长相等；例如，第十一晶体管M11的宽大于第二晶体管M2的宽。
例如，第十晶体管M10的长小于第十一晶体管M11的长。又例如，第十晶体管M10的宽与第十一晶体管M11的宽相等。
在本公开的实施例中，通过对轮廓大致呈矩形的第十晶体管M10以及第十一晶体管 M11的尺寸(长与宽)进行设计，可以使得布局更加紧凑，节省布局空间，从而可以减小该显示基板10中的周边区域所占用的面积，从而可以减小包括该显示基板10的显示装置的边框尺寸，从而有利于实现窄边框的显示装置。
如图9A-图9B所示，第十晶体管M10的栅极G10和第十一晶体管M11的栅极G11设置在第一导电层601，第十晶体管M10的第一极D10和第二极S10、以及第十一晶体管M11的第一极D11和第二极S11设置在第二导电层604。
如图9C所示，第十晶体管M10还包括位于半导体层603的有源层AC10，第十一晶体管M11还包括位于半导体层603的有源层AC11。
如图9A-图9B所示，第十晶体管M10的栅极G10与第十一晶体管M11的栅极G11连接，且第十晶体管M10的栅极G10和第十一晶体管M11的栅极G11均与第二节点N2电连接，第十晶体管M10的第一极D10与第一晶体管M1的第一极D1连接，第十一晶体管M11的第一极D11与第二晶体管M2的第一极D2连接，第十晶体管M10的第二极S10和第十一晶体管M11的第二极S11均与第一电压连接走线CL2电连接。
例如，第十晶体管M10的第二极S10和第十一晶体管M11的第二极S11均与分支走线BL连接，从而实现与第一电压连接走线CL2的电连接。
如图9A-图9B所示，该移位寄存器单元200还包括设置在第一导电层601的第十转接电极TE10以及设置在第二导电层604的第十一转接电极TE11，第十转接电极TE10和第十一转接电极TE11在衬底基板100上的正投影至少部分重叠，且第十转接电极TE10与第十一转接电极TE11电连接。
如图9D所示，位于第一导电层601的第十转接电极TE10可以通过过孔VH13和VH14与位于第二导电层604的第十一转接电极TE11电连接。例如，第十转接电极TE10通过过孔VH13和VH14与第十一转接电极TE11直接接触从而实现电连接。
如图9A-图9B所示，第十转接电极TE10在第六晶体管M6的栅极G6与第十晶体管M10的栅极G10之间，且与第十晶体管M10的栅极G10连接。第十一转接电极T11与第六晶体管M6的第一极D6连接。也就是说，第十晶体管M10的栅极G10以及第十一晶体管M11的栅极G11通过第十转接电极TE10、过孔VH13和VH14、第十一转接电极TE11实现与第六晶体管M6的第一极D6的电连接，即实现与第二节点N2的电连接。采用转接电极实现电连接的方式，不仅可以使得移位寄存器单元10中的晶体管的布局更加紧凑，另外还可以减少走线跨接所需的层数，减少工艺制程中所需掩膜数量，从而降低该显示基板10的制造成本。
在一些实施例中，该移位寄存器单元200还包括第四复位电路270，该第四复位电路270被配置为响应于扫描复位信号对第一节点N1进行复位。关于第四复位电路270可以参考上述关于移位寄存器单元200的描述，这里不再赘述。
该第四复位电路270包括第十二晶体管M12，如图8所示，第十二晶体管M12位于第一电容C1靠近显示区域110的一侧。即，第十二晶体管M12位于第一电容C1与显示区域110之间，采用这种方式，可以使得第十二晶体管M12更便于与其它移位寄存器单元 的输出端连接以接收扫描复位信号，即，便于多个移位寄存器单元实现级联。
如图9A-图9B所示，第十二晶体管M12的栅极G12设置在第一导电层601，第十二晶体管M12的第一极D12和第二极S12设置在第二导电层604。如图9C所示，第十二晶体管M12还包括位于半导体层603的有源层AC12。
如图9A-图9B所示，第十二晶体管M12的栅极G12被配置为接收扫描复位信号。例如，当多个移位寄存器单元200进行级联时，某一级移位寄存器单元200中的第十二晶体管M12的栅极G12可以与其它级移位寄存器单元的输出端OP连接以接收扫描复位信号。
第十二晶体管M12的第一极D12与第一节点N1电连接，第十二晶体管M12的第二极S12与第一电压连接走线CL2连接以接收低电平的第一电压。
如图9B所示，该移位寄存器单元200还包括设置在第二导电层604的第十二转接电极TE12，第十二转接电极TE12与第十二晶体管M12的第一极D12连接。第十二转接电极TE12和第一电容C1的第一极801在衬底基板100上的正投影至少部分重叠，且第十二转接电极TE12与第一电容C1的第一极801电连接。
例如，如图9C所示，第十二转接电极TE12可以通过过孔VH15和VH16与第一电容C1的第一极801电连接。例如，第十二转接电极TE12通过过孔VH15和VH16与第一电容C1的第一极801直接接触从而实现电连接。
也就是说，第十二晶体管M12的第一极D12通过第十二转接电极TE12、过孔VH15和VH16、第一电容C1的第一极801实现与第一节点N1的电连接。
例如，如图9A-图9B所示，该移位寄存器单元200还包括设置在第一导电层601的第十三转接电极TE13以及设置在第二导电层604的第十四转接电极TE14，第十三转接电极TE13和第十四转接电极TE14在衬底基板100上的正投影至少部分重叠，且第十三转接电极TE13与第十四转接电极TE14电连接。
如图9D所示，位于第一导电层601的第十三转接电极TE13可以通过过孔VH17和VH18与位于第二导电层604的第十四转接电极TE14电连接。例如，第十三转接电极TE13通过过孔VH17和VH18与第十四转接电极TE14直接接触从而实现电连接。
如图9A-图9B所示，第十四转接电极TE14与第一电容C1的第二极802(输出端OP)连接。例如，当多个移位寄存器单元200进行级联时，某一级移位寄存器单元200中的第十三转接电极TE13可以与其它级移位寄存器单元的第十二晶体管M12的栅极G12连接以提供扫描复位信号，或者与其它级移位寄存器单元的输入信号连接走线CL3连接以提供输入信号；即，便于多个移位寄存器单元实现级联。
在本公开的实施例提供的显示基板10中，通过合理的设置转接电极以及过孔，可以使得位于第一导电层601的部件(例如晶体管的栅极)与位于第二导电层604的部件(例如晶体管的第一级或第二极)实现电连接，从而实现相应的电路结构。采用这种方式可以使得显示基板10的布局更加合理、紧凑，另外还可以减少走线跨接所需的层数，减少工艺制程中所需掩膜数量，从而降低该显示基板10的制造成本。
如图9A所示，移位寄存器单元200的各个晶体管的栅极G1～G12的平面形状为块状， 例如基本上均为矩形。
如图9C所示，移位寄存器单元200的各个晶体管的有源层AC1～AC12的平面形状为块状，例如基本上均为矩形，且大致均匀地布置，从而有利于与块状栅极G1～G12对应，且有利于实现用于半导体层的构图工艺以及保持刻蚀过程中的刻蚀均匀性。
如图9B所示，移位寄存器单元200的各个晶体管的源极和漏极(其中一个为U型电极另一个为I型电极)整体上的外轮廓的平面形状为块状，例如基本上均为矩形，与块状有源层AC1～AC12对应，组合定义了一个或多个U型沟道区，增加了沟道宽度的同时有利于减小沟道长度，由此增加了各个晶体管的沟道区宽长比，有助于改善各个晶体管的开关性能。
图1C为对应图1A中所示的移位寄存器单元的布局图。比较图1C和图8可以发现，图1C中所示的移位寄存器单元中的各个晶体管之间存在较大的间隙空间，布局不紧凑，浪费了很多布局空间。而在本公开的上述实施例提供的显示基板10中，如图8所示，通过对移位寄存器单元中的各个晶体管以及走线的排布进行设计，可以使得该显示基板10的布局更加紧凑，节省布局空间，从而可以减小该显示基板10中的周边区域所占用的面积，从而可以减小包括该显示基板10的显示装置的边框尺寸，从而有利于实现窄边框的显示装置。
例如，如图9B所示，该移位寄存器单元200中的任意一个晶体管的第一极和第二极中的一个(例如第一级)在衬底基板100上的正投影的形状包括至少一个U型，该晶体管的第一极和第二极中的另一个(例如第二极)在衬底基板100上的正投影的形状包括至少一个I型。
例如，第一晶体管M1的第一极D1、第二晶体管M2的第一极D2、第五晶体管M5的第一极D5、第七晶体管M7的第一极D7、第八晶体管M8的第一极D8、第九晶体管M9的第一极D9、第十二晶体管M12的第一极D12在衬底基板100上的正投影的形状为U型，第一晶体管M1的第二极S1、第二晶体管M2的第二极S2、第五晶体管M5的第二极S5、第七晶体管M7的第二极S7、第八晶体管M8的第二极S8、第九晶体管M9的第二极S9、第十二晶体管M12的第二极S12在衬底基板100上的正投影的形状为I型，且上述晶体管的第二极对伸入对应的第一极中。
又例如，第三晶体管M3的第一极D3、第四晶体管M4的第一极D4、第六晶体管M6的第一极D6、第十晶体管M10的第一极D10、第十一晶体管M11的第一极D11在衬底基板100上的正投影的形状包括多个U型，第三晶体管M3的第二极S3、第四晶体管M4的第二极S4、第六晶体管M6的第二极S6、第十晶体管M10的第二极S10、第十一晶体管M11的第二极S11在衬底基板100上的正投影的形状包括多个U型，其上述晶体管的第一极与第二极彼此交叉。
例如，如图9A和图9C所示，该移位寄存器单元200中的任意一个晶体管的栅极在衬底基板100上的正投影覆盖该晶体管的有源层在衬底基板上的正投影。例如，在一个示例中，可以使得任意一个晶体管的栅极在衬底基板100上的正投影与该晶体管的有源层在衬 底基板上的正投影重合。
在本公开的实施例中，例如，半导体层603的材料可以包括氧化物半导体、有机半导体或非晶硅、多晶硅等，例如，氧化物半导体包括金属氧化物半导体(例如氧化铟镓锌(IGZO))，多晶硅包括低温多晶硅或者高温多晶硅等，本公开的实施例对此不作限定。
图12为对应于图6所示的多个移位寄存器单元级联的示意图的布局图。图13A、图13B、图13C分别为对应图12中的第一导电层、第二导电层以及半导体层的布局图。
例如，如图12所示，多个移位寄存器单元包括在第一方向R1上相邻设置的第一移位寄存器单元200(1)和第二移位寄存器单元200(2)，第一移位寄存器单元200(1)与第二移位寄存器单元200(2)共用同一条第一电压连接走线CL2，且相对于第一电压连接走线CL2轴对称分布。类似地，第三移位寄存器单元200(3)与第四移位寄存器单元200(4)共用同一条第一电压连接走线CL2，且相对于第一电压连接走线CL2轴对称分布；第五移位寄存器单元200(5)与第六移位寄存器单元200(6)共用同一条第一电压连接走线CL2，且相对于第一电压连接走线CL2轴对称分布。
在本公开的实施例提供的显示基板10中，相邻的两个移位寄存器单元共用同一条第一电压连接走线可以使得第一电压连接走线的数量节省一半，从而也节省了第一电压连接走线对应的布局空间，使得该显示基板10的布局更加紧凑，节省布局空间，从而可以减小该显示基板10中的周边区域所占用的面积，从而可以减小包括该显示基板10的显示装置的边框尺寸，从而有利于实现窄边框的显示装置。
例如，如图12、图13A-图13C所示，多个移位寄存器单元包括在第一方向R1上依次相邻设置的第一移位寄存器单元200(1)、第二移位寄存器单元200(2)、第三移位寄存器单元200(3)以及第四移位寄存器单元200(4)。第四移位寄存器单元200(4)中的输入电路210(输入信号连接走线CL3)与第一移位寄存器单元200(1)的输出电路220(第十三转接电极TE13)连接，以将第一移位寄存器单元200(1)的输出信号作为第四移位寄存器单元200(4)的输入信号。关于多个移位寄存器单元级联的详细描述可以参考关于图6的描述，这里不再赘述。
本公开的至少一实施例还提供一种显示装置1，如图14所示，该显示装置1包括本公开的实施例提供的任一显示基板10。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、QLED面板、QLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例中关于移位寄存器单元200以及显示基板10的相应描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (30)

  1. 一种显示基板，包括：衬底基板以及设置在所述衬底基板上的多个移位寄存器单元，其中，
    所述多个移位寄存器单元沿第一方向并列排布；
    所述多个移位寄存器单元中的每个包括输入电路、输出电路、第一复位电路和帧复位信号连接走线；
    所述帧复位信号连接走线沿第二方向延伸，且被配置为向所述第一复位电路提供帧复位信号，所述第二方向与所述第一方向彼此交叉；
    所述输入电路被配置为响应于输入信号以控制第一节点的电平；
    所述输出电路被配置为接收时钟信号，并在所述第一节点的电平的控制下将所述时钟信号作为输出信号输出至输出端；
    所述第一复位电路被配置为响应于所述帧复位信号，以在所述显示基板的两个显示帧之间的时间段内对所述第一节点以及所述输出端进行复位；
    所述第一复位电路包括第一晶体管和第二晶体管，所述帧复位信号连接走线、所述第一晶体管的栅极以及所述第二晶体管的栅极设置在第一导电层；
    所述移位寄存器单元还包括设置在第二导电层的第一转接电极，所述第一晶体管的栅极与所述第二晶体管的栅极连接，且均通过所述第一转接电极与所述帧复位信号连接走线电连接。
  2. 根据权利要求1所述的显示基板，其中，
    所述第一晶体管与所述第二晶体管沿所述第二方向相邻排布；
    所述移位寄存器单元还包括沿所述第二方向延伸的第一电压连接走线，所述第一电压连接走线被配置为向所述移位寄存器单元提供第一电压，所述第一电压用于在所述显示基板的两个显示帧之间的时间段内对所述第一节点以及所述输出端进行复位；
    所述第一电压连接走线、所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极均设置在所述第二导电层；
    所述第一晶体管的第一极与所述第一节点电连接，所述第二晶体管的第一极与所述输出端电连接，所述第一晶体管的第二极以及所述第二晶体管的第二极均与所述第一电压连接走线电连接。
  3. 根据权利要求2所述的显示基板，其中，
    所述移位寄存器单元还包括设置在所述第二导电层且沿所述第一方向延伸的分支走线，所述分支走线与所述第一电压连接走线连接；
    所述第一晶体管的第二极和所述第二晶体管的第二极分别布置在所述分支走线的两侧，且均与所述分支走线连接。
  4. 根据权利要求1-3任一所述的显示基板，其中，所述第一晶体管与所述第二晶体管的尺寸相同。
  5. 根据权利要求2-4任一所述的显示基板，其中，
    所述多个移位寄存器单元包括在所述第一方向上相邻设置的第一移位寄存器单元和第二移位寄存器单元，
    所述第一移位寄存器单元与所述第二移位寄存器单元共用同一条所述第一电压连接走线，且相对于所述第一电压连接走线轴对称分布。
  6. 根据权利要求2-5任一所述的显示基板，其中，
    所述移位寄存器单元还包括沿所述第二方向延伸的输入信号连接走线，所述输入信号连接走线被配置为向所述输入电路提供所述输入信号；
    所述输入电路包括第三晶体管，所述输入信号连接走线以及所述第三晶体管的栅极均设置在所述第一导电层，所述第三晶体管的栅极与所述输入信号连接走线连接；
    所述第三晶体管的第一极和第二极均设置在所述第二导电层，所述第三晶体管的第一极与所述第三晶体管的栅极电连接，所述第三晶体管的第二极与所述第一晶体管的第一极连接，且所述第一节点为所述第三晶体管的第二极与所述第一晶体管的第一极的汇合点。
  7. 根据权利要求6所述的显示基板，其中，
    所述移位寄存器单元还包括设置在所述第一导电层的第二转接电极以及设置在所述第二导电层的第三转接电极，所述第二转接电极和所述第三转接电极在所述衬底基板上的正投影至少部分重叠；
    所述第二转接电极与所述第三晶体管的栅极连接，所述第三转接电极与所述第三晶体管的第一极连接，所述第二转接电极与所述第三转接电极电连接。
  8. 根据权利要求7所述的显示基板，其中，
    所述第三晶体管的第一极包括沿所述第一方向延伸的第一连接部以及多个沿所述第二方向延伸的第一突出部，
    所述第一连接部与所述第三转接电极连接，所述多个第一突出部分别与所述第一连接部连接，所述多个第一突出部之间形成多个第一凹陷部；
    所述第三晶体管的第二极包括沿所述第一方向延伸的第二连接部以及多个沿所述第二方向延伸的第二突出部，所述多个第二突出部分别与所述第二连接部连接，所述多个第二突出部之间形成多个第二凹陷部；
    所述多个第一突出部伸入所述多个第二凹陷部中，以使得所述多个第二突出部和所述多个第一突出部沿所述第一方向依次间隔排布。
  9. 根据权利要求7或8所述的显示基板，其中，
    所述移位寄存器单元还包括沿所述第二方向延伸的时钟信号连接走线，所述时钟信号连接走线被配置为向所述输出电路提供时钟信号；
    所述输出电路包括第四晶体管和第一电容；
    所述第四晶体管的栅极以及所述第一电容的第一极设置在所述第一导电层，且所述第一电容的第一极位于所述第四晶体管的栅极靠近所述显示基板的显示区域的一侧；
    所述第四晶体管的第一极和第二极、所述第一电容的第二极以及所述时钟信号连接走 线均设置在所述第二导电层；
    所述第四晶体管的栅极与所述第三晶体管的第二极电连接，所述第四晶体管的第一极与所述时钟信号连接走线连接以接收所述时钟信号，所述第四晶体管的第二极与所述第二晶体管的第一极连接；
    所述第一电容的第一极与所述第四晶体管的栅极连接，所述第一电容的第二极与所述第四晶体管的第二极连接。
  10. 根据权利要求9所述的显示基板，其中，
    所述第四晶体管包括多个沿所述第二方向并联的子晶体管，每个所述子晶体管包括设置在所述第一导电层的栅极、设置在所述第二导电层的第一极和第二极、以及设置在半导体层的有源层；
    多个所述子晶体管的栅极彼此连接，多个所述子晶体管的第一极彼此连接，多个所述子晶体管的第二极彼此连接，多个所述子晶体管的有源层沿所述第二方向依次排布，且彼此独立不连接。
  11. 根据权利要求9或10所述的显示基板，其中，
    所述时钟信号连接走线与所述输入信号连接走线在所述衬底基板上的正投影部分平行，且部分重叠。
  12. 根据权利要求9-11任一所述的显示基板，其中，
    所述移位寄存器单元还包括设置在所述第一导电层的第四转接电极和设置在所述第二导电层的第五转接电极，所述第四转接电极和所述第五转接电极在所述衬底基板上的正投影至少部分重叠，且所述第四转接电极与所述第五转接电极电连接；
    所述第四转接电极在所述第三晶体管的栅极与所述第一晶体管的栅极之间，所述第五转接电极在所述第三晶体管的第二极与所述第一晶体管的第一极之间；
    所述第四转接电极与所述第四晶体管的栅极电连接，所述第五转接电极与所述第一晶体管的第一极以及所述第三晶体管的第二极连接。
  13. 根据权利要求12所述的显示基板，其中，
    所述移位寄存器单元还包括设置在所述第一导电层的第一连接电极，所述第一连接电极的两端分别与所述第四晶体管的栅极以及所述第四转接电极连接；
    所述第一连接电极位于所述输入信号连接走线靠近所述第一晶体管的一侧，且所述第一连接电极与所述输入信号连接走线在所述衬底基板上的正投影部分平行。
  14. 根据权利要求12或13所述的显示基板，其中，所述移位寄存器单元还包括控制电路，所述控制电路配置为根据所述第一节点的电平控制第二节点的电平；
    所述控制电路包括第五晶体管、第六晶体管、第七晶体管以及第八晶体管，所述第五晶体管的栅极、所述第六晶体管的栅极、所述第七晶体管的栅极以及所述第八晶体管的栅极均设置在所述第一导电层，所述第五晶体管的第一极和第二极、所述第六晶体管的第一极和第二极、所述第七晶体管的第一极和第二极以及所述第八晶体管的第一极和第二极均设置在所述第二导电层；
    所述第八晶体管的栅极与所述第八晶体管的第一极电连接，且被配置为接收不同于所述第一电压的第二电压，所述第八晶体管的第二极与所述第七晶体管的第一极连接，所述第七晶体管的栅极与所述第六晶体管的栅极连接，所述第七晶体管的第二极与所述第一电压连接走线连接；
    所述第五晶体管的栅极与所述第八晶体管的第二极电连接，所述第五晶体管的第一极与所述第六晶体管的第一极电连接，所述第五晶体管的第二极与所述第八晶体管的第一极电连接，所述第六晶体管的栅极与所述第四转接电极连接，所述第六晶体管的第二极与所述第一电压连接走线连接；
    所述第二节点为所述第五晶体管的第一极与所述第六晶体管的第一极的汇合点。
  15. 根据权利要求14所述的显示基板，其中，
    所述第八晶体管、所述第七晶体管以及所述第六晶体管沿所述第二方向依次相邻排布，所述第五晶体管和所述第八晶体管沿所述第一方向相邻排布，所述第六晶体管和所述第三晶体管沿所述第一方向相邻排布。
  16. 根据权利要求14或15所述的显示基板，其中，
    所述移位寄存器单元还包括设置在所述第一导电层的第六转接电极和设置在所述第二导电层的第七转接电极，所述第六转接电极和所述第七转接电极在所述衬底基板上的正投影至少部分重叠，且所述第六转接电极与所述第七转接电极电连接；
    所述第六转接电极在所述第五晶体管的栅极与所述第八晶体管的栅极之间，且与所述第八晶体管的栅极连接；
    所述第七转接电极在所述第五晶体管的第二极与所述第八晶体管的第一极之间，且与所述第五晶体管的第二极以及所述第八晶体管的第一极均连接。
  17. 根据权利要求16所述的显示基板，其中，
    所述移位寄存器单元还包括设置在所述第一导电层的第八转接电极和设置在所述第二导电层的第九转接电极，所述第八转接电极和所述第九转接电极在所述衬底基板上的正投影至少部分重叠，且所述第八转接电极与所述第九转接电极电连接；
    所述第八转接电极在所述第六转接电极靠近所述显示区域的一侧，且所述第八转接电极与所述第六转接电极沿所述第二方向相邻排布；
    所述第九转接电极在所述第七转接电极靠近所述显示区域的一侧，且所述第九转接电极与所述第七转接电极沿所述第二方向相邻排布；
    所述第八转接电极与所述第五晶体管的栅极连接，所述第九转接电极与所述第八晶体管的第二极以及所述第七晶体管的第一极连接。
  18. 根据权利要求14-17任一所述的显示基板，其中，所述移位寄存器单元还包括第二复位电路，所述第二复位电路被配置为响应于所述输入信号以控制所述第二节点的电平；
    所述第二复位电路包括第九晶体管，所述第九晶体管的栅极设置在所述第一导电层，所述第九晶体管的第一极和第二极设置在所述第二导电层；
    所述第九晶体管的栅极与所述第二转接电极连接，所述第九晶体管的第一极与所述第 五晶体管的第一极连接，所述第九晶体管的第二极与所述第七晶体管的第二极连接。
  19. 根据权利要求18所述的显示基板，其中，
    所述第五晶体管、所述第九晶体管以及所述第三晶体管沿所述第二方向依次排布；
    所述第二转接电极位于所述第九晶体管的栅极与所述第三晶体管的栅极之间；
    所述第九晶体管与所述第七晶体管沿所述第一方向相邻排布。
  20. 根据权利要求19所述的显示基板，其中，所述移位寄存器单元还包括设置在第二导电层的第二连接电极，
    所述第二连接电极的两端分别与所述第九晶体管的第一极以及所述第六晶体管的第一极连接。
  21. 根据权利要求18-20任一所述的显示基板，其中，所述移位寄存器单元还包括第三复位电路，所述第三复位电路被配置为在所述第二节点的电平的控制下对所述第一节点以及所述输出端进行复位；
    所述第三复位电路包括第十晶体管和第十一晶体管；
    所述第十晶体管的栅极和所述第十一晶体管的栅极设置在所述第一导电层，所述第十晶体管的第一极和第二极、以及所述第十一晶体管的第一极和第二极设置在所述第二导电层；
    所述第十晶体管的栅极与所述第十一晶体管的栅极连接，且所述第十晶体管的栅极和所述第十一晶体管的栅极均与所述第二节点电连接，所述第十晶体管的第一极与所述第一晶体管的第一极连接，所述第十一晶体管的第一极与所述第二晶体管的第一极连接，所述第十晶体管的第二极和所述第十一晶体管的第二极均与所述第一电压连接走线电连接。
  22. 根据权利要求21所述的显示基板，其中，
    所述第十晶体管和所述第十一晶体管沿所述第二方向相邻排布，所述第十晶体管和所述第一晶体管沿所述第一方向相邻排布，所述第十一晶体管和所述第二晶体管沿所述第一方向相邻排布。
  23. 根据权利要求22所述的显示基板，其中，
    所述移位寄存器单元还包括设置在所述第一导电层的第十转接电极以及设置在所述第二导电层的第十一转接电极，所述第十转接电极和所述第十一转接电极在所述衬底基板上的正投影至少部分重叠，且所述第十转接电极与所述第十一转接电极电连接；
    所述第十转接电极在所述第六晶体管的栅极与所述第十晶体管的栅极之间，且与所述第十晶体管的栅极连接；
    所述第十一转接电极与所述第六晶体管的第一极连接。
  24. 根据权利要求21-23任一所述的显示基板，其中，所述第十一晶体管的长与所述第二晶体管的长相等，所述第十晶体管的长小于所述第十一晶体管的长，所述第十晶体管的宽与所述第十一晶体管的宽相等。
  25. 根据权利要求21-24任一所述的显示基板，其中，所述移位寄存器单元还包括第四复位电路，所述第四复位电路被配置为响应于扫描复位信号对所述第一节点进行复位；
    所述第四复位电路包括第十二晶体管，所述第十二晶体管位于所述第一电容靠近所述显示区域的一侧；
    所述第十二晶体管的栅极设置在所述第一导电层，所述第十二晶体管的第一极和第二极设置在所述第二导电层；
    所述第十二晶体管的栅极被配置为接收所述扫描复位信号，所述第十二晶体管的第一极与所述第一节点电连接，所述第十二晶体管的第二极与所述第一电压连接走线连接。
  26. 根据权利要求25所述的显示基板，其中，
    所述移位寄存器单元还包括设置在第二导电层的第十二转接电极，所述第十二转接电极与所述第十二晶体管的第一极连接，
    所述第十二转接电极和所述第一电容的第一极在所述衬底基板上的正投影至少部分重叠，且所述第十二转接电极与所述第一电容的第一极电连接。
  27. 根据权利要求25或26所述的显示基板，其中，
    所述移位寄存器单元中的任意一个晶体管的第一极和第二极中的一个在所述衬底基板上的正投影的形状包括至少一个U型，
    该晶体管的第一极和第二极中的另一个在所述衬底基板上的正投影的形状包括至少一个I型。
  28. 根据权利要求1-27任一所述的显示基板，其中，
    所述移位寄存器单元中的任意一个晶体管的栅极在所述衬底基板上的正投影覆盖该晶体管的有源层在所述衬底基板上的正投影。
  29. 根据权利要求1-28任一所述的显示基板，其中，所述多个移位寄存器单元包括在所述第一方向上依次相邻设置的第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元以及第四移位寄存器单元；
    所述第四移位寄存器单元中的输入电路与所述第一移位寄存器单元的输出电路连接，以将所述第一移位寄存器单元的输出信号作为所述第四移位寄存器单元的输入信号。
  30. 一种显示装置，包括如权利要求1-29任一所述的显示基板。
PCT/CN2021/094472 2020-06-23 2021-05-19 显示基板和显示装置 WO2021258926A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/778,566 US11908430B2 (en) 2020-06-24 2021-05-19 Display substrate and display device
US18/395,828 US20240135898A1 (en) 2020-06-23 2023-12-26 Display substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010592567.8 2020-06-23
CN202010592567.8A CN113838404B (zh) 2020-06-24 2020-06-24 显示基板和显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/778,566 A-371-Of-International US11908430B2 (en) 2020-06-24 2021-05-19 Display substrate and display device
US18/395,828 Continuation US20240135898A1 (en) 2020-06-23 2023-12-26 Display substrate and display device

Publications (1)

Publication Number Publication Date
WO2021258926A1 true WO2021258926A1 (zh) 2021-12-30

Family

ID=78964988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/094472 WO2021258926A1 (zh) 2020-06-23 2021-05-19 显示基板和显示装置

Country Status (3)

Country Link
US (2) US11908430B2 (zh)
CN (1) CN113838404B (zh)
WO (1) WO2021258926A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114724613B (zh) * 2022-06-09 2022-10-28 北京京东方技术开发有限公司 显示基板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105405808A (zh) * 2015-09-09 2016-03-16 友达光电股份有限公司 制作光学感测元件与薄膜晶体管元件的方法
CN108182921A (zh) * 2018-01-03 2018-06-19 上海中航光电子有限公司 一种阵列基板、显示面板与显示装置
CN108563082A (zh) * 2018-04-27 2018-09-21 京东方科技集团股份有限公司 电路基板、显示装置及驱动方法
CN110415637A (zh) * 2019-08-29 2019-11-05 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN111210758A (zh) * 2020-02-28 2020-05-29 合肥鑫晟光电科技有限公司 栅极驱动电路及显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011065045A1 (ja) * 2009-11-30 2011-06-03 シャープ株式会社 走査信号線駆動回路およびこれを備えた表示装置
CN104517564B (zh) * 2015-01-04 2017-10-27 京东方科技集团股份有限公司 阵列基板和显示装置
CN104867472B (zh) 2015-06-15 2017-10-17 合肥京东方光电科技有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN106023914A (zh) * 2016-05-16 2016-10-12 京东方科技集团股份有限公司 移位寄存器及其操作方法
CN206134207U (zh) * 2016-10-31 2017-04-26 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路及显示面板
CN107274856A (zh) * 2017-08-22 2017-10-20 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN108053789B (zh) * 2018-02-12 2021-02-05 合肥鑫晟光电科技有限公司 显示装置、栅极驱动器及其控制方法
CN108648685B (zh) * 2018-07-25 2022-03-04 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108962118B (zh) 2018-07-25 2022-03-11 京东方科技集团股份有限公司 Goa单元、goa电路及其驱动方法、阵列基板
CN208834749U (zh) 2018-09-17 2019-05-07 北京京东方技术开发有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN110503921B (zh) 2019-09-18 2020-11-10 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、显示装置
CN110648621B (zh) 2019-10-30 2023-04-18 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路及显示装置
CN110827783B (zh) 2019-12-16 2022-03-18 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105405808A (zh) * 2015-09-09 2016-03-16 友达光电股份有限公司 制作光学感测元件与薄膜晶体管元件的方法
CN108182921A (zh) * 2018-01-03 2018-06-19 上海中航光电子有限公司 一种阵列基板、显示面板与显示装置
CN108563082A (zh) * 2018-04-27 2018-09-21 京东方科技集团股份有限公司 电路基板、显示装置及驱动方法
CN110415637A (zh) * 2019-08-29 2019-11-05 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN111210758A (zh) * 2020-02-28 2020-05-29 合肥鑫晟光电科技有限公司 栅极驱动电路及显示装置

Also Published As

Publication number Publication date
US11908430B2 (en) 2024-02-20
CN113838404A (zh) 2021-12-24
US20230012488A1 (en) 2023-01-19
CN113838404B (zh) 2023-01-24
US20240135898A1 (en) 2024-04-25

Similar Documents

Publication Publication Date Title
US11361693B2 (en) Shift register unit, gate driving circuit, display device, and driving method
US11996039B2 (en) Display panel and display device
US11776481B2 (en) Display substrate and manufacture method thereof, and display device
US20240112638A1 (en) Display substrate and manufacturing method thereof, display device
CN116027600A (zh) 显示基板及其制作方法、显示装置
US11967286B2 (en) Display substrate and manufacturing method thereof, display device
US11990089B2 (en) Display substrate and manufacturing method thereof, display device
US20230252941A1 (en) Display substrate and manufacturing method thereof, display device
US11705048B2 (en) Shift register unit, circuit structure, gate drive circuit, drive circuit and display device
US11594184B2 (en) Display substrate and manufacturing method thereof, display device
US20240135898A1 (en) Display substrate and display device
WO2020097816A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
CN114974153B (zh) 移位寄存器、驱动电路、驱动方法及显示装置
US20230162684A1 (en) Display substrate and manufacturing method thereof, and display device
KR20220030599A (ko) 디스플레이 장치의 게이트 드라이버 및 그 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21829765

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21829765

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.09.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21829765

Country of ref document: EP

Kind code of ref document: A1