WO2021258926A1 - 显示基板和显示装置 - Google Patents
显示基板和显示装置 Download PDFInfo
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- WO2021258926A1 WO2021258926A1 PCT/CN2021/094472 CN2021094472W WO2021258926A1 WO 2021258926 A1 WO2021258926 A1 WO 2021258926A1 CN 2021094472 W CN2021094472 W CN 2021094472W WO 2021258926 A1 WO2021258926 A1 WO 2021258926A1
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- transistor
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- shift register
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Definitions
- the embodiment of the present disclosure relates to a display substrate and a display device.
- a pixel array of a liquid crystal display usually includes multiple rows of gate lines and multiple columns of data lines interlaced therewith.
- the gate line can be driven by an attached integrated drive circuit.
- GOA Gate-driver On Array
- a GOA composed of multiple cascaded shift register units can be used to provide switch-state voltage signals for multiple rows of gate lines of the pixel array, thereby controlling the multiple rows of gate lines to turn on sequentially, and the data lines correspond to the pixel array.
- the pixel units of the rows provide data signals to form the gray-scale voltages required by each gray-scale of the displayed image, and then display each frame of image.
- At least one embodiment of the present disclosure provides a display substrate, including: a base substrate and a plurality of shift register units arranged on the base substrate, the plurality of shift register units are arranged side by side along a first direction;
- Each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit, and a frame reset signal connection trace;
- the frame reset signal connection trace extends in the second direction and is configured to The first reset circuit provides a frame reset signal, and the second direction and the first direction cross each other;
- the input circuit is configured to respond to the input signal to control the level of the first node;
- the output circuit is Is configured to receive a clock signal and output the clock signal as an output signal to the output terminal under the control of the level of the first node;
- the first reset circuit is configured to respond to the frame reset signal to The first node and the output terminal are reset in the time period between two display frames of the display substrate;
- the first reset circuit includes a first transistor and a second transistor, and the frame reset
- the first transistor and the second transistor are arranged adjacently along the second direction;
- the shift register unit further includes An extended first voltage connection trace, the first voltage connection trace is configured to provide a first voltage to the shift register unit, and the first voltage is used in one of two display frames of the display substrate
- the first node and the output terminal are reset within a period of time;
- the first voltage connection trace, the first pole and the second pole of the first transistor, the first pole of the second transistor Both the pole and the second pole are arranged on the second conductive layer;
- the first pole of the first transistor is electrically connected to the first node, and the first pole of the second transistor is electrically connected to the output terminal, Both the second pole of the first transistor and the second pole of the second transistor are electrically connected to the first voltage connection wire.
- the shift register unit further includes a branch wiring disposed on the second conductive layer and extending along the first direction, and the branch wiring is connected to the The first voltage connection trace is connected; the second pole of the first transistor and the second pole of the second transistor are respectively arranged on both sides of the branch trace, and both are connected to the branch trace.
- the first transistor and the second transistor have the same size.
- the plurality of shift register units include a first shift register unit and a second shift register unit that are adjacently arranged in the first direction, and the The first shift register unit and the second shift register unit share the same first voltage connection trace, and are axially symmetrically distributed with respect to the first voltage connection trace.
- the shift register unit further includes an input signal connection trace extending along the second direction, and the input signal connection trace is configured to be connected to the input signal
- the circuit provides the input signal; the input circuit includes a third transistor, the input signal connection trace and the gate of the third transistor are both arranged on the first conductive layer, and the gate of the third transistor Connected to the input signal connection trace; the first electrode and the second electrode of the third transistor are both arranged on the second conductive layer, and the first electrode of the third transistor is connected to the gate of the third transistor.
- the second electrode of the third transistor is connected to the first electrode of the first transistor, and the first node is the second electrode of the third transistor and the first electrode of the first transistor.
- the shift register unit further includes a second switching electrode provided on the first conductive layer and a third switching electrode provided on the second conductive layer. Electrode, the orthographic projection of the second transfer electrode and the third transfer electrode on the base substrate at least partially overlap; the second transfer electrode is connected to the gate of the third transistor, so The third switching electrode is connected to the first electrode of the third transistor, and the second switching electrode is electrically connected to the third switching electrode.
- the first electrode of the third transistor includes a first connection portion extending along the first direction and a plurality of first protrusions extending along the second direction.
- the first connecting portion is connected to the third transfer electrode, the plurality of first protrusions are respectively connected to the first connecting portion, and a plurality of first protrusions are formed between the plurality of first protrusions.
- the second electrode of the third transistor includes a second connecting portion extending along the first direction and a plurality of second protrusions extending along the second direction, the plurality of second protrusions Are respectively connected to the second connecting portion, a plurality of second recessed portions are formed between the plurality of second protrusions; the plurality of first protrusions extend into the plurality of second recessed portions, so that The plurality of second protrusions and the plurality of first protrusions are sequentially arranged at intervals along the first direction.
- the shift register unit further includes a clock signal connection trace extending along the second direction, and the clock signal connection trace is configured to output to the
- the circuit provides a clock signal;
- the output circuit includes a fourth transistor and a first capacitor;
- the gate of the fourth transistor and the first electrode of the first capacitor are arranged on the first conductive layer, and the first The first electrode of the capacitor is located on the side of the gate of the fourth transistor close to the display area of the display substrate;
- the clock signal connection traces are all arranged on the second conductive layer;
- the gate of the fourth transistor is electrically connected to the second electrode of the third transistor, and the first electrode of the fourth transistor is electrically connected to the second electrode of the third transistor.
- the clock signal connection trace is connected to receive the clock signal, the second electrode of the fourth transistor is connected to the first electrode of the second transistor; the first electrode of the first capacitor is connected to the first electrode of the fourth transistor The gate is connected, and the second electrode of the first capacitor is connected to the second electrode of the fourth transistor.
- the fourth transistor includes a plurality of sub-transistors connected in parallel along the second direction, and each of the sub-transistors includes a gate provided on the first conductive layer. Electrode, the first electrode and the second electrode provided on the second conductive layer, and the active layer provided on the semiconductor layer; the gates of the plurality of sub-transistors are connected to each other, and the first The poles are connected to each other, the second poles of the plurality of sub-transistors are connected to each other, and the active layers of the plurality of sub-transistors are sequentially arranged along the second direction, and are independent of each other and not connected.
- the orthographic projection of the clock signal connection trace and the input signal connection trace on the base substrate is parallel and partially overlapped.
- the shift register unit further includes a fourth switching electrode provided on the first conductive layer and a fifth switching electrode provided on the second conductive layer.
- the fourth transfer electrode is between the gate of the third transistor and the gate of the first transistor, and the fifth transfer electrode is between the second electrode of the third transistor and the first transistor.
- the fourth transfer electrode is electrically connected to the gate of the fourth transistor
- the fifth transfer electrode is connected to the first pole of the first transistor and the third transistor The second pole is connected.
- the shift register unit further includes a first connection electrode disposed on the first conductive layer, and two ends of the first connection electrode are respectively connected to the first connection electrode.
- the gates of the four transistors are connected to the fourth transfer electrode; the first connection electrode is located on the side of the input signal connection trace close to the first transistor, and the first connection electrode is connected to the input
- the signal connection traces are parallel to the orthographic projection portion on the base substrate.
- the shift register unit further includes a control circuit configured to control the level of the second node according to the level of the first node;
- the control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the gate of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor, and the eighth transistor.
- the gates of the transistors are all arranged on the first conductive layer, the first and second electrodes of the fifth transistor, the first and second electrodes of the sixth transistor, and the first and second electrodes of the seventh transistor.
- the electrode and the second electrode and the first electrode and the second electrode of the eighth transistor are all arranged on the second conductive layer; the gate of the eighth transistor is electrically connected to the first electrode of the eighth transistor, And is configured to receive a second voltage different from the first voltage, the second electrode of the eighth transistor is connected to the first electrode of the seventh transistor, and the gate of the seventh transistor is connected to the first electrode of the seventh transistor.
- the gates of the six transistors are connected, the second electrode of the seventh transistor is connected to the first voltage connection trace; the gate of the fifth transistor is electrically connected to the second electrode of the eighth transistor, the The first electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, the second electrode of the fifth transistor is electrically connected to the first electrode of the eighth transistor, and the gate of the sixth transistor Is connected to the fourth transfer electrode, the second electrode of the sixth transistor is connected to the first voltage connection line; the second node is the first electrode of the fifth transistor and the sixth The junction of the first pole of the transistor.
- the eighth transistor, the seventh transistor, and the sixth transistor are arranged adjacent to each other in the second direction, and the fifth transistor and the The eighth transistor is arranged adjacently along the first direction, and the sixth transistor and the third transistor are arranged adjacently along the first direction.
- the shift register unit further includes a sixth switching electrode provided on the first conductive layer and a seventh switching electrode provided on the second conductive layer.
- the sixth transfer electrode is between the gate of the fifth transistor and the gate of the eighth transistor, and is connected to the gate of the eighth transistor;
- the seventh transfer electrode is in the Between the second electrode of the fifth transistor and the first electrode of the eighth transistor, and is connected to both the second electrode of the fifth transistor and the first electrode of the eighth transistor.
- the shift register unit further includes an eighth switch electrode provided on the first conductive layer and a ninth switch electrode provided on the second conductive layer.
- the eighth transfer electrode is on a side of the sixth transfer electrode close to the display area, and the eighth transfer electrode and the sixth transfer electrode are arranged adjacently along the second direction
- the ninth switch electrode is on the side of the seventh switch electrode close to the display area, and the ninth switch electrode and the seventh switch electrode are arranged adjacent to each other along the second direction Cloth;
- the eighth transfer electrode is connected to the gate of the fifth transistor, and the ninth transfer electrode is connected to the second electrode of the eighth transistor and the first electrode of the seventh transistor.
- the shift register unit further includes a second reset circuit, and the second reset circuit is configured to control the second node in response to the input signal.
- the second reset circuit includes a ninth transistor, the gate of the ninth transistor is arranged on the first conductive layer, and the first and second electrodes of the ninth transistor are arranged on the second Conductive layer; the gate of the ninth transistor is connected to the second transfer electrode, the first electrode of the ninth transistor is connected to the first electrode of the fifth transistor, and the second electrode of the ninth transistor The electrode is connected to the second electrode of the seventh transistor.
- the fifth transistor, the ninth transistor, and the third transistor are arranged in sequence along the second direction; the second switching electrode is located at the Between the gate of the ninth transistor and the gate of the third transistor; the ninth transistor and the seventh transistor are arranged adjacently along the first direction.
- the shift register unit further includes a second connection electrode disposed on the second conductive layer, and two ends of the second connection electrode are connected to the ninth transistor respectively.
- the first electrode of the sixth transistor is connected to the first electrode of the sixth transistor.
- the shift register unit further includes a third reset circuit, and the third reset circuit is configured to control all the components under the control of the level of the second node.
- the first node and the output terminal are reset;
- the third reset circuit includes a tenth transistor and an eleventh transistor; the gate of the tenth transistor and the gate of the eleventh transistor are arranged in the The first conductive layer, the first and second electrodes of the tenth transistor, and the first and second electrodes of the eleventh transistor are arranged on the second conductive layer; the gate of the tenth transistor The electrode is connected to the gate of the eleventh transistor, and the gate of the tenth transistor and the gate of the eleventh transistor are both electrically connected to the second node.
- the electrode is connected to the first electrode of the first transistor, the first electrode of the eleventh transistor is connected to the first electrode of the second transistor, and the second electrode of the tenth transistor is connected to the eleventh electrode.
- the second poles of the transistors are all electrically connected to the first voltage connection wiring.
- the tenth transistor and the eleventh transistor are arranged adjacently along the second direction, and the tenth transistor and the first transistor are arranged along the The eleventh transistor and the second transistor are arranged adjacently in the first direction, and the eleventh transistor and the second transistor are arranged adjacently in the first direction.
- the shift register unit further includes a tenth transfer electrode provided on the first conductive layer and an eleventh switch electrode provided on the second conductive layer. Connecting electrodes, the orthographic projections of the tenth connecting electrode and the eleventh connecting electrode on the base substrate at least partially overlap, and the tenth connecting electrode and the eleventh connecting electrode Electrically connected; the tenth transfer electrode is between the gate of the sixth transistor and the gate of the tenth transistor, and is connected to the gate of the tenth transistor; the eleventh transfer The electrode is connected to the first electrode of the sixth transistor.
- the length of the eleventh transistor is equal to the length of the second transistor, and the length of the tenth transistor is smaller than the length of the eleventh transistor, so The width of the tenth transistor is equal to the width of the eleventh transistor.
- the shift register unit further includes a fourth reset circuit configured to reset the first node in response to a scan reset signal;
- the fourth reset circuit includes a twelfth transistor, the twelfth transistor is located on the side of the first capacitor close to the display area; the gate of the twelfth transistor is provided on the first conductive layer , The first electrode and the second electrode of the twelfth transistor are arranged on the second conductive layer; the gate of the twelfth transistor is configured to receive the scan reset signal, and the second electrode of the twelfth transistor The first pole is electrically connected to the first node, and the second pole of the twelfth transistor is connected to the first voltage connection line.
- the shift register unit further includes a twelfth switching electrode disposed on the second conductive layer, and the twelfth switching electrode is connected to the twelfth switching electrode.
- the first pole of the transistor is connected, the orthographic projection of the twelfth transfer electrode and the first pole of the first capacitor on the base substrate at least partially overlap, and the twelfth transfer electrode and the first pole of the first capacitor overlap at least partially.
- the first pole of the first capacitor is electrically connected.
- the shape of the orthographic projection of one of the first electrode and the second electrode of any transistor in the shift register unit on the base substrate includes at least A U-shape
- the shape of the orthographic projection of the other of the first pole and the second pole of the transistor on the base substrate includes at least one I-shape
- the orthographic projection of the gate of any transistor in the shift register unit on the base substrate covers the active layer of the transistor on the substrate. Orthographic projection on the substrate.
- the plurality of shift register units include a first shift register unit, a second shift register unit, and a second shift register unit that are arranged adjacent to each other in the first direction.
- At least one embodiment of the present disclosure further provides a display device, including the display substrate provided by any embodiment of the present disclosure.
- Fig. 1A is a schematic circuit diagram of a shift register unit
- FIG. 1B is a signal timing diagram corresponding to the operation of the shift register unit shown in FIG. 1A;
- FIG. 1C is a layout diagram corresponding to the shift register unit shown in FIG. 1A;
- 2A is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure
- 2B is a schematic circuit diagram of a shift register unit provided by at least one embodiment of the present disclosure
- FIG. 3 is a signal timing diagram corresponding to the operation of the shift register unit shown in FIG. 2B;
- 4A is a simulation diagram of the potential of the first node in the shift register unit shown in FIG. 1A and the shift register unit shown in FIG. 2B;
- FIG. 4B is a schematic diagram after enlarging the part enclosed by the dashed ellipse in FIG. 4A;
- 5A is a test result of actual testing of the potential of the first node in the shift register unit shown in FIG. 1A and the shift register unit shown in FIG. 2B;
- FIG. 5B is a test result of actual testing of the potential of the second node in the shift register unit shown in FIG. 1A and the shift register unit shown in FIG. 2B;
- FIG. 6 shows a schematic diagram of cascading multiple shift register units as shown in FIG. 2B;
- FIG. 7 is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
- FIG. 8 is a layout diagram corresponding to the shift register unit shown in FIG. 2B;
- 9A, 9B, and 9C are layout diagrams corresponding to the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. 8 respectively;
- FIG. 9D is a layout diagram of the vias used in FIG. 8;
- FIG. 10 is a schematic cross-sectional view of various layer structures included in a display substrate provided by at least one embodiment of the present disclosure
- 11A is a schematic cross-sectional view of a display substrate at a position including a via hole according to at least one embodiment of the present disclosure
- FIG. 11B is a schematic cross-sectional view of a display substrate at a position including a via hole according to at least one embodiment of the present disclosure
- FIG. 12 is a layout diagram corresponding to the schematic diagram of cascading multiple shift register units shown in FIG. 6; FIG.
- 13A, 13B, and 13C are respectively corresponding layout diagrams of the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. 12;
- FIG. 14 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
- the display panel in order to achieve low cost and narrow frame, GOA (Gate-driver On Array) technology can be used, that is, the gate drive circuit is integrated on the array substrate of the display panel through thin film transistor process, so as to realize the narrow frame and Advantages such as reducing assembly costs.
- the display panel may be a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, or a quantum dot light emitting diode (QLED) display panel.
- LCD liquid crystal display
- OLED organic light emitting diode
- QLED quantum dot light emitting diode
- FIG. 1A shows a schematic circuit diagram of a shift register unit, and multiple shift register units can be cascaded to form a gate drive circuit.
- the shift register unit includes nine transistors (T1 to T9) and a storage capacitor (C0).
- FIG. 1C is a layout diagram corresponding to the shift register unit shown in FIG. 1A, and correspondingly shows the position of each transistor on the display substrate, as well as related electrodes, active layers, wiring, and the like.
- the above-mentioned transistors are all N-type transistors.
- the following also takes N-type transistors as an example for description, but the embodiments of the present disclosure are not limited to this situation.
- at least some of these transistors can be replaced with P-type transistors.
- the first voltage terminal VGL in FIG. 1A is configured to be connected to a DC low-level signal
- the second voltage terminal VDD is configured to be connected to a DC high-level signal.
- the clock signal terminal CLK inputs a low level signal
- the input terminal IP inputs a high level signal. Since the input terminal IP inputs a high level signal, the first transistor T1 is turned on, so that the high level input from the input terminal IP charges the storage capacitor C0, and the potential of the first node N1 is pulled up to the first high level.
- the first node N1 may be a pull-up node (PU).
- the third node N3 may be a pull-down control node (PD_CN).
- the sixth transistor T6 Since the potential of the first node N1 is at the first high level, the sixth transistor T6 is turned on, so that the third node N3 is electrically connected to the first voltage terminal VGL.
- the fifth transistor T5 and the sixth transistor T6 can be configured (for example, the size ratio, threshold voltage, etc.) of the two transistors when T5 and T6 are both turned on, the potential of the third node N3 is pulled It is low to a lower level, and the low level does not make the third transistor T3 fully turn on.
- the fourth transistor T4 Since the potential of the first node N1 is at the first high level, the fourth transistor T4 is turned on, so that the potential of the second node N2 is pulled down to a low level.
- the second node N2 may be a drop-down node (PD).
- the output terminal OP outputs the low level.
- the clock signal terminal CLK inputs a high level signal
- the input terminal IP inputs a low level signal. Since the input terminal IP inputs a low-level signal, the first transistor T1 is turned off, and the first node N1 maintains the first high level of the previous stage, so that the second transistor T2 remains on, because the clock signal terminal CLK is input at this stage High level, so the output terminal OP outputs the high level.
- the high level can pass through the parasitic capacitance of the second transistor T2 (including the parasitic capacitance between the gate and the first pole, and the gate and the second stage
- the parasitic capacitance between) and the storage capacitor C0 increase the potential coupling of the first node N1 to the second high level, so that the second transistor T2 is turned on more fully. Since the potential of the first node N1 is at a high level, the fourth transistor T4 continues to be turned on, so that the potential of the second node N2 continues to be maintained at a low level.
- the signal input from the clock signal terminal CLK changes from a high level to a low level, and the low level is output to the output terminal OP through the turned-on second transistor T2.
- the level change of the clock signal terminal CLK will pull down the potential coupling of the first node N1 to the first high level through the parasitic of the turned-on second transistor T2 and the storage capacitor C0.
- the ninth transistor T9 is turned on, so that the first node N1 is electrically connected to the first voltage terminal VGL, and the potential of the first node N1 is pulled low. Level, so that the second transistor T2 is turned off.
- the sixth transistor T6 and the fourth transistor T4 are turned off, the discharge path of the third node N3 and the second node N2 is cut off, and the potential of the second node N2 is charged to a high level, As a result, the seventh transistor T7 and the eighth transistor T8 are turned on, and the potentials of the first node N1 and the output terminal OP are respectively pulled down to the low level input by the first voltage terminal VGL, which further eliminates the non-operation of the shift register unit.
- the noise may be generated at the output terminal and the first node N1.
- the fifth transistor T5 and the sixth transistor T6 need to meet a certain configuration relationship (for example, the size ratio of the two meets a certain configuration relationship), so that the third The potential of the node N3 is pulled down to a lower level. If the potential of the third node N3 cannot completely turn off the third transistor T3, the high level signal of the second voltage terminal VDD will charge the second node N2, causing the seventh transistor T7 to be partially turned on. The charging process of the first node N1 is affected, and the normal output of the output terminal OP may be affected in severe cases.
- a certain configuration relationship for example, the size ratio of the two meets a certain configuration relationship
- At least one embodiment of the present disclosure provides a shift register unit.
- the shift register unit can avoid a competitive relationship between charging and discharging of the first node, so that the first node can be charged more fully, and the use of the shift register can be improved.
- the reliability of the unit s product.
- the first node and the output terminal can be reset in the time period between two display frames to reduce the influence of noise, so that the reliability of the product using the shift register unit can be improved.
- At least one embodiment of the present disclosure also provides a display substrate including the above-mentioned shift register unit.
- the layout of the display substrate can be made more compact. Therefore, the area occupied by the peripheral area of the display substrate can be reduced, and the frame size of the display device including the display substrate can be reduced.
- At least one embodiment of the present disclosure provides a shift register unit 200 that can be cascaded to form a gate drive circuit, and the gate drive circuit can be used in a display substrate, for example, to drive the display of the display substrate. Multiple rows of pixel units in the area are scanned and displayed.
- the shift register unit 200 includes an input circuit 210, an output circuit 220, a first reset circuit 230, a control circuit 240, a second reset circuit 250, a third reset circuit 260, and a fourth reset circuit 270.
- the input circuit 210 is configured to control the level of the first node N1 in response to an input signal.
- the first node N1 may be a pull-up node (PU).
- the input circuit 210 is electrically connected to the input terminal IP, so that when the input circuit 210 is turned on, the input signal input from the input terminal IP can be used to control the level of the first node N1, for example, pull high.
- the input circuit 210 includes a third transistor M3.
- the gate G3 of the third transistor M3 and the first electrode D3 of the third transistor M3 are electrically connected, and both are electrically connected to the input terminal IP to receive the input signal; the second electrode S3 of the third transistor M3 is electrically connected to the first node N1 .
- the output circuit 220 is configured to receive a clock signal, and output the clock signal as an output signal to the output terminal OP under the control of the level of the first node.
- the output circuit 220 is electrically connected to the clock signal terminal CLK and the output terminal OP.
- the output circuit 220 is turned on, the clock signal received from the clock signal terminal CLK can be output as an output signal to the output terminal. OP.
- the output circuit 220 includes a fourth transistor M4 and a first capacitor C1.
- the gate G4 of the fourth transistor M4 is electrically connected to the first node N1
- the first electrode D4 of the fourth transistor M4 is electrically connected to the clock signal terminal CLK to receive the clock signal
- the second electrode S4 of the fourth transistor M4 is electrically connected to the output terminal OP Electric connection.
- the first pole 801 of the first capacitor C1 is electrically connected to the first node N1
- the second pole 802 of the first capacitor C1 is electrically connected to the output terminal OP.
- the first reset circuit 230 is configured to respond to the frame reset signal to reset the first node N1 and the output terminal OP in a time period between two display frames of the display substrate.
- the first reset circuit 230 is electrically connected to the frame reset signal terminal STV to receive the frame reset signal
- the first reset circuit 230 is electrically connected to the first voltage terminal VGL to receive the first voltage, for example, the first The voltage can be a low-level voltage.
- the first reset circuit 230 is also electrically connected to the first node N1 and the output terminal OP.
- the first reset circuit 230 In the time period between two adjacent display frames of the display substrate, when the first reset circuit 230 is turned on in response to the frame reset signal, the first node N1 and the first node N1 and The output terminal OP performs a reset operation, so that the noise on the first node N1 and the output terminal OP can be reduced or eliminated, so that the reliability of the product using the shift register unit 200 can be improved.
- the first reset circuit 230 includes a first transistor M1 and a second transistor M2.
- the gate G1 of the first transistor M1 is electrically connected to the frame reset signal terminal STV to receive the frame reset signal
- the first electrode D1 of the first transistor M1 is electrically connected to the first node N1
- the second electrode S1 of the first transistor M1 is electrically connected to the first node N1.
- a voltage terminal VGL is electrically connected to receive a low-level first voltage.
- the gate G2 of the second transistor M2 is electrically connected to the frame reset signal terminal STV to receive the frame reset signal, the first electrode D2 of the second transistor M2 is electrically connected to the output terminal OP, and the second electrode S2 of the second transistor M2 is electrically connected to the first
- the voltage terminal VGL is electrically connected to receive a low-level first voltage.
- the first node N1 is a junction point of the second electrode S3 of the third transistor M3, the first electrode D1 of the first transistor M1 and the gate G4 of the fourth transistor M4.
- the control circuit 240 is configured to control the level of the second node N2 according to the level of the first node N1.
- the second node N2 may be a drop-down node (PD).
- the control circuit 240 is electrically connected to the first voltage terminal VGL to receive a low-level first voltage; the control circuit 240 is electrically connected to the second voltage terminal VDD to receive a second voltage different from the first voltage.
- the voltage for example, the second voltage may be a high-level voltage.
- the control circuit 240 is also electrically connected to the first node N1 and the second node N2.
- the control circuit 240 controls the level of the second node N2 to be low; when the level of the first node N1 is low, the control circuit 240 combines The high-level second voltage received by the second voltage terminal VDD can be controlled so that the level of the second node N2 is high.
- the control circuit 240 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.
- the gate G8 of the eighth transistor M8 is electrically connected to the first electrode D8 of the eighth transistor M8, and both are electrically connected to the second voltage terminal VDD to receive the high-level second voltage; the second electrode S8 of the eighth transistor M8 It is electrically connected to the third node N3.
- the third node N3 may be a pull-down control node (PD_CN).
- the gate G7 of the seventh transistor M7 is electrically connected to the first node N1, the first electrode D7 of the seventh transistor M7 is electrically connected to the third node N3, and the second electrode S7 of the seventh transistor M7 is electrically connected to the first voltage terminal VGL To receive the low-level first voltage.
- the gate G5 of the fifth transistor M5 is electrically connected to the third node N3, the first electrode D5 of the fifth transistor M5 is electrically connected to the second node N2, and the second electrode S5 of the fifth transistor M5 is electrically connected to the second voltage terminal VDD To receive the high-level second voltage.
- the gate of the sixth transistor M6 is electrically connected to the first node N1, the first electrode D6 of the sixth transistor M6 is electrically connected to the second node N2, and the second electrode S6 of the sixth transistor M6 is electrically connected to the first voltage terminal VGL to Receive the low-level first voltage.
- the second node N2 is the junction point of the first pole D5 of the fifth transistor M5 and the first pole D6 of the sixth transistor M6;
- the third node N3 is the second pole S8 of the eighth transistor M8 and the fifth transistor M5.
- each node (first node N1, second node N2, third node N3) and each signal terminal (input terminal IP, output terminal OP, frame reset signal terminal STV, The scan reset signal terminal RST, the clock signal terminal CLK, etc.) are all set to better describe the circuit structure, and do not represent actual components.
- the node represents the junction of the related circuit connections in the circuit structure, that is, the related circuits connected with the same node identifier are electrically connected to each other.
- the second reset circuit 250 is configured to control the level of the second node N2 in response to the input signal.
- the second reset circuit 250 is electrically connected to the input terminal IP to receive an input signal
- the second reset circuit 250 is also electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
- the second reset circuit 250 is also electrically connected to the second node N2.
- the input circuit 210 uses the input signal to charge the first node N1
- the second reset circuit 250 can be turned on in response to the input signal, so that the low-level first voltage can be used to control the second node N2.
- Level for example, pulls down the potential of the second node N2 to a low level.
- the potential of the second node N2 does not affect the charging process of the first node N1, so that the charging of the first node N1 More fully, the reliability of the product using the shift register unit 200 can be improved.
- the second reset circuit 250 includes a ninth transistor M9.
- the gate G9 of the ninth transistor M9 is electrically connected to the input terminal IP to receive the input signal
- the first electrode D9 of the ninth transistor M9 is electrically connected to the second node N2
- the second electrode S9 of the ninth transistor M9 is electrically connected to the first voltage terminal
- the VGL is electrically connected to receive the low-level first voltage.
- the third reset circuit 260 is configured to reset the first node N1 and the output terminal OP under the control of the level of the second node N2.
- the third reset circuit 260 is electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
- the third reset circuit 260 is also connected to the first node N1, the second node N2, and The output terminal OP is electrically connected.
- the third reset circuit 260 is turned on under the control of the level of the second node N2 (for example, the level of the second node N2 is a high level)
- the first voltage of a low level can be used for the first voltage respectively.
- a node N1 and the output terminal OP are reset, so that the noise on the first node N1 and the output terminal OP can be reduced or eliminated.
- the third reset circuit 260 includes a tenth transistor M10 and an eleventh transistor M11.
- the gate G10 of the tenth transistor M10 is electrically connected to the second node N2
- the first electrode D10 of the tenth transistor M10 is electrically connected to the first node N1
- the second electrode S10 of the tenth transistor M10 is electrically connected to the first voltage terminal VGL To receive the low-level first voltage.
- the gate G11 of the eleventh transistor M11 is electrically connected to the second node N2, the first electrode D11 of the eleventh transistor M11 is electrically connected to the output terminal OP, and the second electrode S11 of the eleventh transistor M11 is electrically connected to the first voltage terminal VGL It is electrically connected to receive a low-level first voltage.
- the fourth reset circuit 270 is configured to reset the first node N1 in response to the scan reset signal, for example, pull down the level of the first node N1, thereby reducing possible noise on the first node N1.
- the fourth reset circuit 270 is electrically connected to the scan reset signal terminal RST to receive the scan reset signal, and electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
- the fourth reset circuit 270 is also electrically connected to the first node N1. For example, when the fourth reset circuit 270 is turned on in response to the scan reset signal, the first node N1 may be reset by using a low-level first voltage, thereby pulling down the level of the first node N1.
- the fourth reset circuit 270 includes a twelfth transistor M12.
- the gate G12 of the twelfth transistor M12 is electrically connected to the scan reset signal terminal RST to receive the scan reset signal
- the first electrode D12 of the twelfth transistor M12 is electrically connected to the first node N1
- the second electrode of the twelfth transistor M12 S12 is electrically connected to the first voltage terminal VGL to receive a low-level first voltage.
- connection in the foregoing description of the connection relationship in the shift register unit 200 shown in FIG. 2B, "electrical connection” is used.
- the “electrical connection” of two components indicates that the two components are electrically connected, including direct connection and indirect connection, that is, in the corresponding layout drawing, the two components can be directly connected (for example, integrated) to Electrical connection is achieved, or the two components can be electrically connected through other components arranged between the two components.
- the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
- thin film transistors are used as examples for description.
- the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
- one pole is directly described as the first pole and the other pole is the second pole.
- transistors can be divided into N-type and P-type transistors according to their characteristics.
- the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
- the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
- the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
- the high level and the low level are relative.
- the high level indicates a higher voltage range (for example, the high level may adopt 5V, 10V or other suitable voltages), and multiple high levels may be the same or different.
- the low level represents a lower voltage range (for example, the low level can adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels can be the same or different.
- the minimum value of the high level is greater than the maximum value of the low level.
- the working principle of the shift register unit 200 shown in FIG. 2B is described below in conjunction with the signal timing diagram shown in FIG. 3.
- the first phase P1 the second phase P2, the third phase P3, and the fourth phase shown in FIG.
- the potential level of the signal timing diagram shown in FIG. 3 is only schematic, and does not represent the true potential value.
- the clock signal terminal CLK inputs a low level signal
- the input terminal IP inputs a high level signal. Since the input terminal IP inputs a high level signal, the third transistor M3 is turned on, so that the high level input from the input terminal IP charges the first capacitor C1, and the potential of the first node N1 is pulled up to the first high level.
- the eighth transistor M8 Since the second voltage terminal VDD is configured to be connected to the DC high-level signal, the eighth transistor M8 remains turned on, and the high level input from the second voltage terminal VDD charges the third node N3. Since the potential of the first node N1 is at the first high level, the seventh transistor M7 is turned on, so that the third node N3 is electrically connected to the first voltage terminal VGL. In terms of transistor design, the eighth transistor M8 and the seventh transistor M7 can be configured (for example, the size ratio, threshold voltage, etc.) of the two transistors, when both M8 and M7 are turned on, the potential of the third node N3 is pulled It is low to a lower level, which will not turn on the fifth transistor M5 completely. Since the potential of the first node N1 is at the first high level, the sixth transistor M6 is turned on, so that the potential of the second node N2 is pulled down to a low level.
- the ninth transistor M9 is turned on, and the turned-on ninth transistor M9 can use the low-level first voltage to pull down the potential of the second node N2 to a low level.
- the clock signal terminal CLK inputs a low level at this time, so at this stage, the output terminal OP outputs the low level.
- the second reset circuit 250 is the first The nine transistor M9 can also directly pull down the potential of the second node N2 to a low level, so as to ensure that the potential of the second node N2 will not affect the charging process of the first node N1, thereby enabling the charging of the first node N1 More fully, the reliability of the product using the shift register unit 200 is improved.
- the clock signal terminal CLK inputs a high-level signal
- the input terminal IP inputs a low-level signal. Since the input terminal IP inputs a low level signal, the third transistor M3 is turned off, and the first node N1 maintains the first high level of the previous stage, so that the fourth transistor M4 remains on, because the clock signal terminal CLK is input at this stage High level, so the output terminal OP outputs the high level.
- the high level can pass through the parasitic capacitance of the fourth transistor M4 (including the parasitic capacitance between the gate and the first pole, and the gate and the second stage
- the parasitic capacitance between) and the first capacitance C1 raise the potential coupling of the first node N1 to the second high level, so that the fourth transistor M4 is turned on more fully.
- the sixth transistor M6 continues to be turned on, so that the potential of the second node N2 continues to be maintained at a low level.
- the signal input from the clock signal terminal CLK changes from a high level to a low level, and the low level is output to the output terminal OP through the turned-on fourth transistor M4.
- the level change of the clock signal terminal CLK will pull down the potential coupling of the first node N1 to the first high level through the parasitic of the turned-on fourth transistor M4 and the first capacitor C1.
- the twelfth transistor M12 is turned on, so that the first node N1 is electrically connected to the first voltage terminal VGL, and the potential of the first node N1 is pulled down to Low level, so that the fourth transistor M4 is turned off.
- the sixth transistor M6 and the seventh transistor M7 are turned off, the discharge path of the third node N3 and the second node N2 is cut off, and the potential of the second node N2 is charged to a high level, As a result, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the potentials of the first node N1 and the output terminal OP are respectively pulled down to the low level input by the first voltage terminal VGL, thereby further eliminating the shift register unit 200
- the noise that may be generated at the output terminal OP and the first node N1 in the non-output stage improves the reliability of the product using the shift register unit 200.
- the first transistor M1 and the second transistor M2 are turned on, so that the low-level first voltage can be applied to the first node respectively.
- N1 and the output terminal OP perform a reset operation, so that the noise on the first node N1 and the output terminal OP can be reduced or eliminated, so that the reliability of the product using the shift register unit 200 can be improved.
- the fifth stage P5 and the sixth stage P6 are located in the time period BL between the two display frames.
- the fifth stage P5 is closer to the current frame than the sixth stage P6, and the sixth stage P6 Compared to the fifth stage, P5 is closer to the next frame.
- Fig. 3 shows three examples of three frame reset signals, namely STV(1), STV(2), and STV(3). That is, the first reset circuit 230 in the shift register unit 200 may reset the first node N1 and the output terminal OP only in the fifth stage P5, or may only reset the first node N1 and the output terminal OP in the sixth stage P6. OP resets, or alternatively, the first node N1 and the output terminal OP may be reset in the fifth stage P5 and the sixth stage P6 at the same time.
- the positions of the fifth stage P5 and the sixth stage P6 in the time period BL in FIG. 3 are only illustrative, and the embodiments of the present disclosure include but are not limited to this; the time in FIG. 3 In the segment BL, more reset operations may be performed on the first node N1 and the output terminal OP, which is not limited in the embodiment of the present disclosure.
- FIGS. 4A and 4B The potential of the first node N1 in the shift register unit shown in FIG. 1A and the shift register unit 200 shown in FIG. 2B is simulated, and the simulation results are shown in FIGS. 4A and 4B. It should be noted that in FIG. 4A, since there are many overlapping parts of the two curves, the part enclosed by the dashed ellipse in FIG. 4A is enlarged and shown in FIG. 4B.
- curve L1 is a simulated change curve corresponding to the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B
- curve L2 is corresponding to the first node in the shift register unit shown in FIG. 1A.
- the simulated change curve of the potential of the node N1. It can be seen from FIG. 4B that the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B is higher than the potential of the first node N1 in the shift register unit shown in FIG. 1A, and the difference dY 0.30439V. That is to say, compared to the shift register unit shown in FIG. 1A, the shift register unit 200 shown in FIG. The reliability of products using the shift register unit 200 can be improved.
- FIG. 5A is a test result of actual testing of the potential of the first node N1 in the shift register unit shown in FIG. 1A and the shift register unit 200 shown in FIG. 2B.
- Curve L3 is a test change curve corresponding to the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B
- curve L4 is a test corresponding to the potential of the first node N1 in the shift register unit shown in FIG. 1A Curve. It can be seen from FIG. 5A that the potential of the first node N1 in the shift register unit 200 shown in FIG. 2B is higher than the potential of the first node N1 in the shift register unit shown in FIG. 1A.
- FIG. 5B is a test result of actual testing of the potential of the second node N2 in the shift register unit shown in FIG. 1A and the shift register unit 200 shown in FIG. 2B.
- Curve L5 is a test change curve corresponding to the potential of the second node N2 in the shift register unit 200 shown in FIG. 2B
- curve L6 is a test corresponding to the potential of the second node N2 in the shift register unit shown in FIG. 1A Curve. It can be seen from FIG. 5B that, relative to the potential of the second node N2 in the shift register unit shown in FIG. 1A, the potential of the second node N2 in the shift register unit 200 shown in FIG. 2B can be changed more quickly.
- a plurality of shift register units 200 as shown in FIG. 2B can be cascaded to form a gate driving circuit, and the gate driving circuit can drive multiple rows of pixel units in the display area of the display substrate to scan and display sequentially.
- FIG. 6 shows a schematic diagram of cascading multiple shift register units 200 as shown in FIG. 2B.
- the output signals of the six shift register units 200 are respectively provided to the Nth row, N+1th row, N+2th row, N+3th row, N+4th row, and Nth row in the display area.
- N+5 rows of pixel units are used to drive pixel units for scanning display.
- N is an integer greater than or equal to 1.
- the output terminal OP of the first shift register unit 200(1) is electrically connected to the input terminal IP of the fourth shift register unit 200(4), so that the first shift register unit 200
- the output signal of (1) is provided to the fourth shift register unit 200(4) as an input signal
- the output terminal OP of the second shift register unit 200(2) and the fifth shift register unit 200(5) The input terminal IP is electrically connected, so that the output signal of the second shift register unit 200(2) is provided to the fifth shift register unit 200(5) as an input signal
- the output terminal OP is electrically connected to the input terminal IP of the sixth shift register unit 200(6), so that the output signal of the third shift register unit 200(3) is provided to the sixth shift register unit 200(6) to As an input signal; and so on, other shift register units included in the gate drive circuit can also be cascaded in this way, and will not be repeated here.
- the output terminal OP of the nth stage shift register unit is electrically connected to the input terminal IP of the n+3 stage shift register unit, so that the output signal of the nth stage shift register unit is provided
- the shift register unit to the n+3th stage is used as an input signal; n is an integer greater than or equal to 1.
- other shift register units included in the gate drive circuit can also be cascaded in this way, and will not be repeated here.
- the input terminals of the first three shift register units of the gate drive circuit can receive separate input signals.
- the scanning reset signal terminal RST of the first shift register unit 200(1) is electrically connected to the output terminal OP of the fourth shift register unit 200(4), so that the fourth shift register The output signal of the unit 200(4) is provided to the first shift register unit 200(1) as a scanning reset signal; the scanning reset signal terminal RST of the second shift register unit 200(2) and the fifth shift register unit The output terminal OP of 200(5) is electrically connected, so that the output signal of the fifth shift register unit 200(5) is provided to the second shift register unit 200(2) as a scanning reset signal; the third shift register The scanning reset signal terminal RST of the unit 200(3) is electrically connected to the output terminal OP of the sixth shift register unit 200(6), so that the output signal of the sixth shift register unit 200(6) is provided to the third shift register unit 200(6).
- the bit register unit 200(3) is used as a scanning reset signal; by analogy, other shift register units included in the gate drive circuit can also be cascaded in this way, and will not be repeated.
- the scanning reset signal terminal RST of the nth stage shift register unit is electrically connected to the output terminal OP of the n+3 stage shift register unit, so that the n+3 stage shift register unit
- the output signal is provided to the n-th stage shift register unit as a scan reset signal; n is an integer greater than or equal to 1.
- the reset terminals of the last three shift register units of the gate drive circuit can receive a single scan reset signal.
- the display substrate may further include a plurality of signal lines that provide various signals for the gate driving circuit.
- the plurality of signal lines includes six clock signal lines (first clock signal line CLK1, second clock signal line CLK2, third clock signal line CLK3, fourth clock signal line CLK4, fifth clock signal line CLK5 and the sixth clock signal line CLK6) and the frame reset signal line STVL that provides the frame reset signal.
- the display substrate may also include other voltage signal lines, such as voltage signal lines that provide the first voltage or the second voltage, which will not be repeated here.
- the first shift register unit 200 (1), the second shift register unit 200 (2), the third shift register unit 200 (3), the fourth shift register unit 200 (4), the fifth shift register The clock signal terminals CLK of the unit 200(5) and the sixth shift register unit 200(6) are electrically connected to provide the required clock signal.
- the clock signal used by the gate driving circuit is 6CLK, that is, the clock signal received by each of the six adjacent shift register units 200 is one cycle.
- clock signal of 6CLK used in FIG. 6 is only illustrative, and the gate driving circuit may also use other clock signals such as 2CLK, 4CLK, etc., which is not limited in the embodiment of the present disclosure.
- the frame reset signal line STVL is electrically connected to the frame reset signal terminals STV of all shift register units 200 in the gate driving circuit.
- the display substrate may further include a timing controller 400, which is electrically connected to the aforementioned multiple clock signal lines and the frame reset signal line STVL to provide corresponding signals.
- the display substrate 10 includes a base substrate 100 and a plurality of shift register units arranged on the base substrate.
- the shift register unit may adopt the shift register unit 200 shown in FIG. 2B.
- the plurality of shift register units 200 are arranged side by side along the first direction R1.
- the multiple shift register units 200 can be cascaded to form a gate driving circuit 500, and the gate driving circuit 500 can drive multiple rows of pixel units PU in the display area 110 of the display substrate 10 for scanning display.
- each shift register unit 200 is electrically connected to the pixel unit PU of the corresponding row through a gate line GL.
- the base substrate 100 may be made of, for example, glass, plastic, quartz or other suitable materials, which is not limited in the embodiment of the present disclosure.
- FIG. 8 is an exemplary layout diagram corresponding to the shift register unit 200 shown in FIG. 2B, and FIG. 9A, FIG. 9B, and FIG. 9C are respectively corresponding to the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. Layout;
- Figure 9D is a layout diagram of part of the vias used in Figure 8;
- Figure 10 is a schematic cross-sectional view showing the various layer structures included in the substrate 10, and Figures 11A-11B show the substrate 10 at the position including the via Schematic diagram of the cross-section.
- the display substrate 10 includes a base substrate 100, a first conductive layer 601, a first insulating layer 602, a semiconductor layer 603, a second conductive layer 604, and a second insulating layer 605.
- the gate of a certain transistor in the shift register unit 200 may be arranged on the first conductive layer 601
- the first and second electrodes of the transistor may be arranged on the second conductive layer 604, and the active layer of the transistor may be It is provided on the semiconductor layer 603; for example, the first insulating layer 602 may be a gate insulating layer
- the second insulating layer 605 may be a passivation layer.
- FIG. 10 only schematically shows a part of the layer structure. According to needs, the display substrate 10 may also include other layer structures, which are not limited in the embodiment of the present disclosure.
- the material of the first conductive layer 601 and the second conductive layer 604 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, which is not limited in the embodiment of the present disclosure.
- the material of the first conductive layer 601 may be the same as the material of the second conductive layer 604, which will not be repeated here.
- the material of the first insulating layer 602 and the second insulating layer 605 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or other suitable materials.
- inorganic insulating materials such as SiNx, SiOx, SiNxOy
- organic insulating materials such as organic resins, or other suitable materials.
- each of the plurality of shift register units 200 included in the display substrate 10 includes an input circuit 210, an output circuit 220, a first reset circuit 230, and a frame reset signal Connect trace CL1.
- the frame reset signal connection line CL1 can be connected to the frame reset signal line STVL to receive the frame reset signal.
- the input circuit 210, the output circuit 220, and the first reset circuit 230 reference may be made to the above description of the shift register unit 200, which will not be repeated here.
- the frame reset signal connection line CL1 extends along the second direction R2 and is configured to provide a frame reset signal to the first reset circuit 230, and the second direction R2 and the first direction R1 cross each other.
- the second direction R2 is perpendicular to the first direction R1.
- the second direction R2 may be the extending direction of the gate line GL.
- the first reset circuit 230 includes a first transistor M1 and a second transistor M2. As shown in FIG. 9A, the frame reset signal is connected to the wiring CL1 and the gate G1 of the first transistor M1. And the gate G2 of the second transistor M2 is arranged on the first conductive layer 601.
- the shift register unit 200 further includes a first transfer electrode TE1 disposed on the second conductive layer 604.
- the gate G1 of the first transistor M1 and the gate G1 of the second transistor M2 The gate G2 is connected, and both are electrically connected to the frame reset signal connection line CL1 through the first transfer electrode TE1.
- the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are both connected to the connection part 301.
- the frame reset signal connection trace CL1 located on the first conductive layer 601 includes a connection portion 302
- the first transfer electrode TE1 located on the second conductive layer 604 includes a connection portion 303 and a connection portion 304 .
- the orthographic projections of the connecting portion 301 and the connecting portion 303 on the base substrate 100 at least partially overlap, and the orthographic projections of the connecting portion 302 and the connecting portion 304 on the base substrate 100 at least partially overlap.
- the connecting portion 301 located on the first conductive layer 601 may be electrically connected to the connecting portion 303 located on the second conductive layer 604 through the via holes VH1 and VH2, and the connecting portion 302 located on the first conductive layer 601 may be electrically connected to the connecting portion 303 located on the second conductive layer 601 through the via holes VH3 and VH4.
- the connection portion 304 of the second conductive layer 604 is electrically connected.
- FIG. 11A shows a schematic diagram of the electrical connection between the connecting portion 301 located on the first conductive layer 601 and the connecting portion 303 located on the second conductive layer 604.
- the connecting portion 303 may be directly contacted with the connecting portion 301 through the via holes VH1 and VH2, thereby achieving electrical connection.
- the connecting portion 303 in the example shown in FIG. 11A is connected to the connecting portion 301 through two vias, and the embodiments of the present disclosure include but are not limited to this.
- the connecting portion 303 may also be connected to the connecting portion 301 through only one via VH1.
- the electrical connection when describing the electrical connection between a component located on the first conductive layer 601 and a component located on the second conductive layer 604, the electrical connection is described by using two vias as an example.
- the embodiments of the present disclosure include but are not limited thereto, and the two components may also be electrically connected through one via, three vias, or more vias.
- the frame reset signal connection trace CL1 located on the first conductive layer 601 passes through the first transfer electrode TE1 located on the second conductive layer 604 and is connected to the first conductive layer 601.
- the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are electrically connected, so that the frame reset signal connection trace CL1 can avoid other components during the layout, making the layout simpler and more reasonable, and in addition, it can reduce walking
- the number of layers required for the line jumper reduces the number of masks required in the process, thereby reducing the manufacturing cost of the display substrate 10.
- the first transistor M1 and the second transistor M2 are arranged adjacently along the second direction R2.
- the adjacent arrangement of the first transistor M1 and the second transistor M2 along the second direction R2 can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10. Therefore, the size of the frame of the display device including the display substrate 10 can be reduced, thereby facilitating the realization of a display device with a narrow frame.
- the first transistor M1 and the second transistor M2 have the same size.
- the length of the first transistor M1 is equal to the length of the second transistor M2
- the width of the first transistor M1 is equal to the width of the second transistor M2.
- the first transistor M1 and the second transistor M2 have the same aspect ratio.
- the same size (length and width) of the first transistor M1 and the second transistor M2 with substantially rectangular outlines can make the characteristics of the two transistors the same, for example, the conduction current is equal, so that The noise reduction characteristic of the first transistor M1 to the first node N1 is the same as the noise reduction characteristic of the second transistor M2 to the output terminal OP.
- the shift register unit 200 further includes a first voltage connection trace CL2 extending along the second direction R2.
- the first voltage connection trace CL2 is configured to provide a first voltage to the shift register unit 200.
- a voltage is used to reset the first node N1 and the output terminal OP in the time period BL between two display frames of the display substrate 10.
- the first voltage is a low-level voltage.
- the first voltage connection trace CL2, the first electrode D1 and the second electrode S1 of the first transistor M1, the first electrode D2 and the second electrode S2 of the second transistor M2 are all arranged on the second conductive layer 604.
- the first electrode D1 of the first transistor M1 is electrically connected to the first node N1
- the first electrode D2 of the second transistor M2 is electrically connected to the output terminal OP
- the second electrode S1 of the first transistor M1 and the second electrode S1 of the second transistor M2 are electrically connected.
- the poles S2 are electrically connected to the first voltage connection line CL2.
- the shift register unit 200 further includes a branch wiring BL disposed on the second conductive layer 604 and extending along the first direction R1, and the branch wiring BL is connected to the first voltage Connect the trace CL2 connection.
- the second pole S1 of the first transistor M1 and the second pole S2 of the second transistor M2 are respectively arranged on both sides of the branch wiring BL, and both are connected to the branch wiring BL.
- the second pole S1 of the first transistor M1 and the second pole S2 of the second transistor M2 are electrically connected to the first voltage connection wiring CL2 through the branch wiring BL.
- the second pole S1 of the first transistor M1 and the second pole S2 of the second transistor M2 may also be symmetrically arranged on both sides of the branch wiring BL.
- the first transistor M1 further includes an active layer AC1 located on the semiconductor layer 603, and the second transistor M2 further includes an active layer AC2 located on the semiconductor layer 603.
- the shift register unit 200 further includes an input signal connection line CL3 extending along the second direction R2, and the input signal connection line CL3 is configured to provide an input signal to the input circuit 210.
- the input signal connection line CL3 of a shift register unit of a certain stage may be connected to the output terminal OP of the shift register unit of another stage.
- the input circuit 210 includes a third transistor M3. As shown in FIG. 9A, the input signal connection wiring CL3 and the gate G3 of the third transistor M3 are both provided on the first conductive layer 601, and the gate G3 of the third transistor M3 is connected to the input signal. Connect the trace CL3 connection. In the embodiment of the present disclosure, by setting the input signal connection line CL3 connected to the input circuit 210 (the third transistor M3), it is convenient for multiple shift register units to realize cascade connection.
- the first electrode D3 and the second electrode S3 of the third transistor M3 are both arranged on the second conductive layer 604, the first electrode D3 of the third transistor M3 and the gate G3 of the third transistor M3 Electrically connected, the second electrode S3 of the third transistor M3 is connected to the first electrode D1 of the first transistor M1, and the first node N1 is between the second electrode S3 of the third transistor M3 and the first electrode D1 of the first transistor M1 Meeting point.
- the third transistor M3 further includes an active layer AC3 located on the semiconductor layer 603.
- the shift register unit 200 further includes a second transfer electrode TE2 provided on the first conductive layer 601 and a third transfer electrode TE3 provided on the second conductive layer 604.
- the orthographic projections of the connecting electrode TE2 and the third connecting electrode TE3 on the base substrate 100 at least partially overlap.
- the second transfer electrode TE2 is connected to the gate G3 of the third transistor M3, the third transfer electrode TE3 is connected to the first electrode D3 of the third transistor M3, and the second transfer electrode TE2 is electrically connected to the third transfer electrode TE3 .
- the second transfer electrode TE2 located on the first conductive layer 601 may be electrically connected to the third transfer electrode TE3 located on the second conductive layer 604 through the via holes VH5 and VH6.
- the second transfer electrode TE2 directly contacts the third transfer electrode TE3 through the via holes VH5 and VH6 to achieve electrical connection.
- the first electrode D3 of the third transistor M3 includes a first connection portion 701 extending along the first direction R1 and a plurality of first protrusions 702 extending along the second direction R2.
- 701 is connected to the third transition electrode TE3
- a plurality of first protrusions 702 are respectively connected to the first connection part 701, and a plurality of first recesses are formed between the plurality of first protrusions 702. That is, the shape of the orthographic projection of the first electrode D3 of the third transistor M3 on the base substrate 100 includes a plurality of U shapes.
- the second electrode S3 of the third transistor M3 includes a second connecting portion 703 extending in the first direction R1 and a plurality of second protrusions 704 extending in the second direction R2, and the plurality of second protrusions 704 are respectively connected to the second The portions 703 are connected, and a plurality of second recesses are formed between the plurality of second protrusions 704. That is, the shape of the orthographic projection of the second electrode S3 of the third transistor M3 on the base substrate 100 includes a plurality of U shapes.
- the plurality of first protrusions 702 extend into the plurality of second recesses between the plurality of second protrusions 704, so that the plurality of second protrusions 704 and the plurality of first protrusions 702 are sequentially along the first direction R1. Arranged at intervals.
- adopting such a layout structure for the first electrode and the second electrode of the third transistor M3 can increase the conduction current of the third transistor M3.
- the use of a layout structure similar to the third transistor M3 for the first pole and the second pole of other transistors can also increase the on-current of the transistor.
- the shift register unit 200 further includes a clock signal connection trace CL4 extending along the second direction R2, and the clock signal connection trace CL4 is configured to provide a clock signal to the output circuit 220.
- the clock signal connection line CL4 and the clock signal line (for example, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5 And one of the sixth clock signal lines CLK6) is electrically connected to receive the clock signal.
- the output circuit 220 includes a fourth transistor M4 and a first capacitor C1. As shown in FIG. 9A, the gate G4 of the fourth transistor M4 and the first electrode 801 of the first capacitor C1 are disposed on the first conductive layer 601, and the first electrode 801 of the first capacitor C1 is disposed on the gate of the fourth transistor M4. G4 is close to the side of the display area 110 of the display substrate 10.
- the first electrode D4 and the second electrode S4 of the fourth transistor M4, the second electrode 802 of the first capacitor C1, and the clock signal connection wiring CL4 are all disposed on the second conductive layer 604.
- the fourth transistor M4 further includes an active layer AC4 located on the semiconductor layer 603.
- the fourth transistor M4 includes a plurality of sub-transistors ST connected in parallel along the second direction R2, and each sub-transistor ST includes a gate provided on the first conductive layer 601 and a gate provided on the first conductive layer 601.
- the gates of the multiple sub-transistors ST are connected to each other, the first electrodes of the multiple sub-transistors ST are connected to each other, the second electrodes of the multiple sub-transistors ST are connected to each other, and the active layers of the multiple sub-transistors ST are sequentially arranged along the second direction R2, and Independent of each other and not connected.
- the fourth transistor M4 adopts a form in which a plurality of sub-transistors ST are connected in parallel, which can improve the driving capability of the output signal of the fourth transistor M4.
- the orthographic projection portions of the clock signal connection trace CL4 and the input signal connection trace CL3 on the base substrate 100 are parallel and partially overlapped.
- the input signal connection trace CL3 and the clock signal connection trace CL4 are respectively arranged on the first conductive layer 601 and the second conductive layer 604, so that the two traces can avoid each other, so that The layout of the display substrate 10 is simpler and more reasonable.
- the gate G4 of the fourth transistor M4 is electrically connected to the second pole S3 of the third transistor M3, and the first pole D4 of the fourth transistor M4 is connected to the clock signal connection line CL4 to receive the clock.
- the second pole S4 of the fourth transistor M4 is connected to the first pole D2 of the second transistor M2.
- the first electrode 801 of the first capacitor C1 is connected to the gate G4 of the fourth transistor M4, and the second electrode 802 of the first capacitor C1 is connected to the second electrode 802 of the fourth transistor M4.
- the shift register unit 200 further includes a fourth transfer electrode TE4 arranged on the first conductive layer 601 and a fifth transfer electrode TE5 arranged on the second conductive layer 604.
- the orthographic projections of the connecting electrode TE4 and the fifth connecting electrode TE5 on the base substrate at least partially overlap, and the fourth connecting electrode TE4 and the fifth connecting electrode TE5 are electrically connected.
- the fourth transfer electrode TE4 located on the first conductive layer 601 may be electrically connected to the fifth transfer electrode TE5 located on the second conductive layer 604 through the via holes VH7 and VH8.
- the fourth transfer electrode TE4 is in direct contact with the fifth transfer electrode TE5 through the via holes VH7 and VH8 to achieve electrical connection.
- the fourth transfer electrode TE4 is between the gate G3 of the third transistor M3 and the gate G1 of the first transistor M1, and the fifth transfer electrode TE5 is between the second electrode S3 of the third transistor M3 and the second electrode S3 of the first transistor M1. Between one pole D1.
- the fourth transfer electrode TE4 is electrically connected to the gate G4 of the fourth transistor M4, and the fifth transfer electrode TE5 is connected to the first electrode D1 of the first transistor M1 and the second electrode S3 of the third transistor M3.
- the shift register unit 200 further includes a first connection electrode CE1 disposed on the first conductive layer 601, and two ends of the first connection electrode CE1 are respectively connected to the gate G4 and the gate G4 of the fourth transistor M4
- the fourth transfer electrode TE4 is connected.
- the first connection electrode CE1 is located on a side of the input signal connection trace CL3 close to the first transistor M1, and the first connection electrode CE1 is parallel to the orthographic projection portion of the input signal connection trace CL3 on the base substrate 100.
- the gate G4 of the fourth transistor M4 is connected to the second electrode S3 of the third transistor M3 through the first connection electrode CE1, the fourth transfer electrode TE4, the via holes VH7 and VH8, and the fifth transfer electrode TE5.
- Electric connection Using this method of connecting electrodes and switching electrodes to achieve electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the amount of work in the process. The number of masks is required, thereby reducing the manufacturing cost of the display substrate 10.
- the shift register unit 200 further includes a control circuit 240 configured to control the level of the second node N2 according to the level of the first node N1.
- control circuit 240 For the control circuit 240, reference may be made to the above description of the shift register unit 200, which will not be repeated here.
- the control circuit 240 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.
- the eighth transistor M8, the seventh transistor M7, and the sixth transistor M6 are arranged adjacent to each other in the second direction R2
- the fifth transistor M5 and the eighth transistor M8 are arranged adjacent to each other in the first direction R1
- the sixth transistor M6 The third transistor M3 and the third transistor M3 are adjacently arranged along the first direction R1.
- the use of this arrangement can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10, thereby reducing the area including the display substrate 10.
- the size of the frame of the display device is beneficial to realize a display device with a narrow frame.
- the fifth transistor M5 further includes an active layer AC5 located on the semiconductor layer 603; the sixth transistor M6 further includes an active layer AC6 located on the semiconductor layer 603; the seventh transistor M7 further includes an active layer AC5 located on the semiconductor layer 603 Source layer AC7; the eighth transistor M8 also includes an active layer AC8 located on the semiconductor layer 603.
- the gate G8 of the eighth transistor M8 is electrically connected to the first electrode D8 of the eighth transistor M8, and is configured to receive a second voltage different from the first voltage.
- the second voltage is a high-level voltage.
- the second electrode S8 of the eighth transistor M8 is connected to the first electrode D7 of the seventh transistor M7, the gate G7 of the seventh transistor M7 is connected to the gate G6 of the sixth transistor M6, and the second electrode S7 of the seventh transistor M7 is connected to
- the first voltage connection line CL2 is connected to receive a low-level first voltage.
- the gate G5 of the fifth transistor M5 is electrically connected to the second electrode S8 of the eighth transistor M8, the first electrode D5 of the fifth transistor M5 is electrically connected to the first electrode D6 of the sixth transistor M6, and the second electrode D6 of the fifth transistor M5 is electrically connected.
- the pole S5 is electrically connected to the first pole D8 of the eighth transistor M8, the gate G6 of the sixth transistor M6 is connected to the fourth transfer electrode TE4, and the second pole S6 of the sixth transistor M6 is connected to the first voltage connection line CL2 .
- the second node N2 is a junction point of the first electrode D5 of the fifth transistor M5 and the first electrode D6 of the sixth transistor M6.
- the shift register unit 200 further includes a sixth transfer electrode TE6 provided on the first conductive layer 601 and a seventh transfer electrode TE7 provided on the second conductive layer 604.
- the orthographic projections of the connecting electrode TE6 and the seventh connecting electrode TE7 on the base substrate 100 at least partially overlap, and the sixth connecting electrode TE6 is electrically connected to the seventh connecting electrode TE7.
- the sixth transfer electrode TE6 located on the first conductive layer 601 may be electrically connected to the seventh transfer electrode TE7 located on the second conductive layer 604 through the via holes VH9 and VH10.
- the sixth transfer electrode TE6 is in direct contact with the seventh transfer electrode TE7 through the via holes VH9 and VH10 to achieve electrical connection.
- the sixth transfer electrode TE6 is between the gate G5 of the fifth transistor M5 and the gate G8 of the eighth transistor M8, and is connected to the gate G8 of the eighth transistor M8.
- the seventh transfer electrode TE7 is between the second electrode S5 of the fifth transistor M5 and the first electrode D8 of the eighth transistor M8, and is connected to the second electrode S5 of the fifth transistor M5 and the first electrode D8 of the eighth transistor M8 Both are connected.
- the gate G8 of the eighth transistor M8 is electrically connected to the first electrode D8 of the eighth transistor M8 through the sixth transfer electrode TE6, the via holes VH9 and VH10, and the seventh transfer electrode TE7.
- Using the transfer electrode to realize the electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the number of masks required in the process. Therefore, the manufacturing cost of the display substrate 10 is reduced.
- the shift register unit 200 further includes an eighth transfer electrode TE8 provided on the first conductive layer 601 and a ninth transfer electrode TE9 provided on the second conductive layer 604.
- the orthographic projections of the connecting electrode TE8 and the ninth connecting electrode TE9 on the base substrate 100 at least partially overlap, and the eighth connecting electrode TE8 and the ninth connecting electrode TE9 are electrically connected.
- the eighth transfer electrode TE8 on the first conductive layer 601 may be electrically connected to the ninth transfer electrode TE9 on the second conductive layer 604 through the via holes VH11 and VH12.
- the eighth transfer electrode TE8 directly contacts the ninth transfer electrode TE9 through the via holes VH11 and VH12 to achieve electrical connection.
- the eighth transfer electrode TE8 is on the side of the sixth transfer electrode TE6 close to the display area 110, and the eighth transfer electrode TE8 and the sixth transfer electrode TE6 are opposite to each other along the second direction R2. Neighboring arrangement.
- the ninth transition electrode TE9 is on a side of the seventh transition electrode TE7 close to the display area 110, and the ninth transition electrode TE9 and the seventh transition electrode TE7 are adjacently arranged along the second direction R2.
- the eighth transfer electrode TE8 is connected to the gate G5 of the fifth transistor M5, and the ninth transfer electrode TE9 is connected to the second electrode S8 of the eighth transistor M8 and the first electrode D7 of the seventh transistor M7. That is, the gate G5 of the fifth transistor M5 is electrically connected to the second electrode S8 of the eighth transistor M8 through the eighth transfer electrode TE8, the via holes VH11 and VH12, and the ninth transfer electrode TE9.
- Using the transfer electrode to realize the electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the number of masks required in the process. Therefore, the manufacturing cost of the display substrate 10 is reduced.
- the shift register unit 200 further includes a second reset circuit 250 configured to control the level of the second node N2 in response to an input signal.
- a second reset circuit 250 configured to control the level of the second node N2 in response to an input signal.
- the second reset circuit 250 includes a ninth transistor M9. As shown in FIG. 8, the fifth transistor M5, the ninth transistor M9, and the third transistor M3 are sequentially arranged along the second direction R2, and the ninth transistor M9 and the seventh transistor M7 They are arranged adjacently along the first direction R1. In the embodiment of the present disclosure, the use of this arrangement can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10, thereby reducing the area including the display substrate 10. The size of the frame of the display device is beneficial to realize a display device with a narrow frame.
- the gate G9 of the ninth transistor M9 is disposed on the first conductive layer 601, and the first electrode D9 and the second electrode S9 of the ninth transistor M9 are disposed on the second conductive layer 604.
- the ninth transistor M9 further includes an active layer AC9 located on the semiconductor layer 603.
- the gate G9 of the ninth transistor M9 is connected to the second transfer electrode TE2
- the first electrode D9 of the ninth transistor M9 is connected to the first electrode D5 of the fifth transistor M5
- the ninth transistor M9 is connected to the first electrode D5 of the fifth transistor M5.
- the second pole S9 of M9 is connected to the second pole S7 of the seventh transistor M7.
- the second transfer electrode TE2 is located between the gate G9 of the ninth transistor M9 and the gate G3 of the third transistor M3.
- the shift register unit 200 further includes a second connection electrode CE2 provided on the second conductive layer 604. Both ends of the second connecting electrode CE2 are respectively connected to the first electrode D9 of the ninth transistor M9 and the first electrode D6 of the sixth transistor M6.
- the first electrode D5 of the fifth transistor M5 is electrically connected to the first electrode D6 of the sixth transistor M6 through the first electrode D9 of the ninth transistor M9 and the second connection electrode CE2.
- the shift register unit 200 further includes a third reset circuit 260 configured to perform control on the first node N1 and the output terminal OP under the control of the level of the second node N2. Reset.
- the third reset circuit 260 reference may be made to the above description of the shift register unit 200, which is not repeated here.
- the third reset circuit 260 includes a tenth transistor M10 and an eleventh transistor M11. As shown in FIG. 8, the tenth transistor M10 and the eleventh transistor M11 are arranged adjacent to each other along the second direction R2. The transistors M1 are arranged adjacently along the first direction R1, and the eleventh transistor M11 and the second transistor M2 are arranged adjacently along the first direction R1. In the embodiment of the present disclosure, the use of this arrangement can make the layout more compact and save layout space, thereby reducing the area occupied by the peripheral area of the display substrate 10, thereby reducing the area including the display substrate 10. The size of the frame of the display device is beneficial to realize a display device with a narrow frame.
- the length of the eleventh transistor M11 is equal to the length of the second transistor M2; for example, the length of the eleventh transistor M11 is also equal to the length of the first transistor M1; for example, , The width of the eleventh transistor M11 is greater than the width of the second transistor M2.
- the length of the tenth transistor M10 is smaller than the length of the eleventh transistor M11.
- the width of the tenth transistor M10 is equal to the width of the eleventh transistor M11.
- the layout can be made more compact, and the layout space can be saved, thereby reducing the size of the layout.
- the area occupied by the peripheral area of the display substrate 10 can thereby reduce the size of the frame of the display device including the display substrate 10, thereby facilitating the realization of a display device with a narrow frame.
- the gate G10 of the tenth transistor M10 and the gate G11 of the eleventh transistor M11 are arranged on the first conductive layer 601, and the first electrode D10 and the second electrode S10 of the tenth transistor M10, And the first electrode D11 and the second electrode S11 of the eleventh transistor M11 are arranged on the second conductive layer 604.
- the tenth transistor M10 further includes an active layer AC10 located on the semiconductor layer 603, and the eleventh transistor M11 further includes an active layer AC11 located on the semiconductor layer 603.
- the gate G10 of the tenth transistor M10 is connected to the gate G11 of the eleventh transistor M11, and the gate G10 of the tenth transistor M10 and the gate G11 of the eleventh transistor M11 are both connected to
- the second node N2 is electrically connected
- the first electrode D10 of the tenth transistor M10 is connected to the first electrode D1 of the first transistor M1
- the first electrode D11 of the eleventh transistor M11 is connected to the first electrode D2 of the second transistor M2
- the second pole S10 of the tenth transistor M10 and the second pole S11 of the eleventh transistor M11 are both electrically connected to the first voltage connection line CL2.
- the second pole S10 of the tenth transistor M10 and the second pole S11 of the eleventh transistor M11 are both connected to the branch wiring BL, thereby achieving electrical connection with the first voltage connection wiring CL2.
- the shift register unit 200 further includes a tenth transfer electrode TE10 arranged on the first conductive layer 601 and an eleventh transfer electrode TE11 arranged on the second conductive layer 604,
- the orthographic projections of the transfer electrode TE10 and the eleventh transfer electrode TE11 on the base substrate 100 at least partially overlap, and the tenth transfer electrode TE10 is electrically connected to the eleventh transfer electrode TE11.
- the tenth transfer electrode TE10 on the first conductive layer 601 may be electrically connected to the eleventh transfer electrode TE11 on the second conductive layer 604 through the via holes VH13 and VH14.
- the tenth transfer electrode TE10 is in direct contact with the eleventh transfer electrode TE11 through the via holes VH13 and VH14 to achieve electrical connection.
- the tenth transfer electrode TE10 is between the gate G6 of the sixth transistor M6 and the gate G10 of the tenth transistor M10, and is connected to the gate G10 of the tenth transistor M10.
- the eleventh transfer electrode T11 is connected to the first electrode D6 of the sixth transistor M6.
- the gate G10 of the tenth transistor M10 and the gate G11 of the eleventh transistor M11 are connected to the sixth transistor M6 through the tenth transfer electrode TE10, the via holes VH13 and VH14, and the eleventh transfer electrode TE11.
- the electrical connection of the first pole D6 is to realize the electrical connection with the second node N2.
- Using the transfer electrode to realize the electrical connection can not only make the layout of the transistors in the shift register unit 10 more compact, but also reduce the number of layers required for wiring jumpers, and reduce the number of masks required in the process. Therefore, the manufacturing cost of the display substrate 10 is reduced.
- the shift register unit 200 further includes a fourth reset circuit 270 configured to reset the first node N1 in response to a scan reset signal.
- a fourth reset circuit 270 configured to reset the first node N1 in response to a scan reset signal.
- the fourth reset circuit 270 includes a twelfth transistor M12. As shown in FIG. 8, the twelfth transistor M12 is located on the side of the first capacitor C1 close to the display area 110. That is, the twelfth transistor M12 is located between the first capacitor C1 and the display area 110. In this way, the twelfth transistor M12 can be more easily connected to the output terminals of other shift register units to receive the scan reset signal, namely , It is convenient for multiple shift register units to realize cascade connection.
- the gate G12 of the twelfth transistor M12 is disposed on the first conductive layer 601, and the first electrode D12 and the second electrode S12 of the twelfth transistor M12 are disposed on the second conductive layer 604.
- the twelfth transistor M12 further includes an active layer AC12 located on the semiconductor layer 603.
- the gate G12 of the twelfth transistor M12 is configured to receive a scan reset signal.
- the gate G12 of the twelfth transistor M12 in a certain stage of shift register unit 200 can be connected to the output terminal OP of another stage of shift register unit to receive scanning. Reset signal.
- the first electrode D12 of the twelfth transistor M12 is electrically connected to the first node N1, and the second electrode S12 of the twelfth transistor M12 is connected to the first voltage connection line CL2 to receive a low-level first voltage.
- the shift register unit 200 further includes a twelfth transfer electrode TE12 disposed on the second conductive layer 604, and the twelfth transfer electrode TE12 is connected to the first electrode D12 of the twelfth transistor M12.
- the orthographic projection of the twelfth transfer electrode TE12 and the first electrode 801 of the first capacitor C1 on the base substrate 100 at least partially overlap, and the twelfth transfer electrode TE12 is electrically connected to the first electrode 801 of the first capacitor C1 .
- the twelfth transfer electrode TE12 may be electrically connected to the first electrode 801 of the first capacitor C1 through the via holes VH15 and VH16.
- the twelfth transfer electrode TE12 is in direct contact with the first electrode 801 of the first capacitor C1 through the via holes VH15 and VH16 to achieve electrical connection.
- the first electrode D12 of the twelfth transistor M12 is electrically connected to the first node N1 through the twelfth transfer electrode TE12, the via holes VH15 and VH16, and the first electrode 801 of the first capacitor C1.
- the shift register unit 200 further includes a thirteenth transfer electrode TE13 provided on the first conductive layer 601 and a fourteenth transfer electrode TE14 provided on the second conductive layer 604 ,
- the orthographic projections of the thirteenth transfer electrode TE13 and the fourteenth transfer electrode TE14 on the base substrate 100 at least partially overlap, and the thirteenth transfer electrode TE13 and the fourteenth transfer electrode TE14 are electrically connected.
- the thirteenth transfer electrode TE13 on the first conductive layer 601 can be electrically connected to the fourteenth transfer electrode TE14 on the second conductive layer 604 through the via holes VH17 and VH18.
- the thirteenth transfer electrode TE13 is in direct contact with the fourteenth transfer electrode TE14 through the via holes VH17 and VH18 to achieve electrical connection.
- the fourteenth transition electrode TE14 is connected to the second electrode 802 (output terminal OP) of the first capacitor C1.
- the thirteenth transfer electrode TE13 in the shift register unit 200 of a certain stage can be connected to the gate G12 of the twelfth transistor M12 of the shift register unit of another stage. It is connected to provide a scanning reset signal, or connected to the input signal connection line CL3 of the shift register unit of other stages to provide an input signal; that is, it is convenient for multiple shift register units to realize cascade connection.
- the components located on the first conductive layer 601 for example, the gate of the transistor
- the components located on the second conductive layer 604 can be made by appropriately setting the transfer electrodes and the via holes. (For example, the first stage or the second pole of the transistor) is electrically connected, so as to realize the corresponding circuit structure.
- the layout of the display substrate 10 can be made more reasonable and compact.
- the number of layers required for wiring jumpers can be reduced, and the number of masks required in the process can be reduced, thereby reducing the manufacturing cost of the display substrate 10.
- the planar shape of the gates G1 to G12 of the respective transistors of the shift register unit 200 is a block shape, for example, all are substantially rectangular.
- the planar shapes of the active layers AC1 to AC12 of the respective transistors of the shift register unit 200 are block-shaped, for example, are substantially rectangular, and are arranged substantially uniformly, thereby facilitating contact with the block-shaped gate G1.
- ⁇ G12 corresponds to and facilitates the realization of the patterning process for the semiconductor layer and the maintenance of the etching uniformity during the etching process.
- each transistor of the shift register unit 200 has a block-like planar shape, for example, substantially uniform. It is rectangular, corresponding to the bulk active layers AC1 to AC12, and defines one or more U-shaped channel regions in combination, which increases the channel width while reducing the channel length, thereby increasing the channel length of each transistor.
- the width-to-length ratio of the channel area helps to improve the switching performance of each transistor.
- FIG. 1C is a layout diagram corresponding to the shift register unit shown in FIG. 1A. Comparing FIG. 1C and FIG. 8, it can be found that there is a large gap space between each transistor in the shift register unit shown in FIG. 1C, the layout is not compact, and a lot of layout space is wasted.
- the layout of the display substrate 10 can be made more compact by designing the layout of each transistor and wiring in the shift register unit. Therefore, the layout space is saved, so that the area occupied by the peripheral area of the display substrate 10 can be reduced, and the frame size of the display device including the display substrate 10 can be reduced, thereby facilitating the realization of a display device with a narrow frame.
- the shape of the orthographic projection of one of the first pole and the second pole (for example, the first stage) of any transistor in the shift register unit 200 on the base substrate 100 includes at least one U-shaped
- the shape of the orthographic projection of the other of the first electrode and the second electrode (for example, the second electrode) of the transistor on the base substrate 100 includes at least one I-shaped.
- the first electrode D1 of the first transistor M1, the first electrode D2 of the second transistor M2, the first electrode D5 of the fifth transistor M5, the first electrode D7 of the seventh transistor M7, and the first electrode of the eighth transistor M8 The shape of the orthographic projection of the first electrode D9 of the ninth transistor M9 and the first electrode D12 of the twelfth transistor M12 on the base substrate 100 is a U-shape, the second electrode S1 of the first transistor M1 and the second transistor The second pole S2 of M2, the second pole S5 of the fifth transistor M5, the second pole S7 of the seventh transistor M7, the second pole S8 of the eighth transistor M8, the second pole S9 of the ninth transistor M9, the twelfth pole
- the shape of the orthographic projection of the second pole S12 of the transistor M12 on the base substrate 100 is an I-shape, and the second pole pair of the above-mentioned transistor extends into the corresponding first pole.
- the first electrode D3 of the third transistor M3, the first electrode D4 of the fourth transistor M4, the first electrode D6 of the sixth transistor M6, the first electrode D10 of the tenth transistor M10, and the first electrode D10 of the eleventh transistor M11 The shape of the orthographic projection of one pole D11 on the base substrate 100 includes a plurality of U shapes, the second pole S3 of the third transistor M3, the second pole S4 of the fourth transistor M4, the second pole S6 of the sixth transistor M6, The shape of the orthographic projection of the second electrode S10 of the tenth transistor M10 and the second electrode S11 of the eleventh transistor M11 on the base substrate 100 includes a plurality of U shapes, and the first and second electrodes of the above-mentioned transistors cross each other .
- the orthographic projection of the gate of any transistor in the shift register unit 200 on the base substrate 100 covers the orthographic projection of the active layer of the transistor on the base substrate.
- the orthographic projection of the gate of any transistor on the base substrate 100 can be made to coincide with the orthographic projection of the active layer of the transistor on the base substrate.
- the material of the semiconductor layer 603 may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
- the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)).
- IGZO indium gallium zinc oxide
- polysilicon includes low-temperature polysilicon or high-temperature polysilicon, etc., which is not limited in the embodiments of the present disclosure.
- FIG. 12 is a layout diagram corresponding to the schematic diagram of cascading multiple shift register units shown in FIG. 6.
- 13A, 13B, and 13C are layout diagrams corresponding to the first conductive layer, the second conductive layer, and the semiconductor layer in FIG. 12, respectively.
- the multiple shift register units include a first shift register unit 200(1) and a second shift register unit 200(2) that are adjacently arranged in the first direction R1.
- the bit register unit 200(1) and the second shift register unit 200(2) share the same first voltage connection line CL2, and are distributed axisymmetrically with respect to the first voltage connection line CL2.
- the third shift register unit 200(3) and the fourth shift register unit 200(4) share the same first voltage connection line CL2, and are distributed axisymmetrically with respect to the first voltage connection line CL2;
- the five shift register unit 200(5) and the sixth shift register unit 200(6) share the same first voltage connection line CL2, and are distributed axisymmetrically with respect to the first voltage connection line CL2.
- two adjacent shift register units share the same first voltage connection trace, which can reduce the number of first voltage connection traces by half, thereby saving the first voltage connection trace.
- the layout space corresponding to the voltage connection traces makes the layout of the display substrate 10 more compact and saves layout space, so that the area occupied by the peripheral area of the display substrate 10 can be reduced, thereby reducing the size of the display substrate 10
- the size of the frame of the display device facilitates the realization of a display device with a narrow frame.
- the plurality of shift register units include a first shift register unit 200(1) and a second shift register unit 200 arranged adjacently in the first direction R1.
- the input circuit 210 (input signal connection line CL3) in the fourth shift register unit 200(4) is connected to the output circuit 220 (the thirteenth transfer electrode TE13) of the first shift register unit 200(1) to The output signal of the first shift register unit 200(1) is used as the input signal of the fourth shift register unit 200(4).
- At least one embodiment of the present disclosure further provides a display device 1.
- the display device 1 includes any display substrate 10 provided by the embodiment of the present disclosure.
- the display device 1 in this embodiment can be: LCD panel, LCD TV, display, OLED panel, OLED TV, QLED panel, QLED TV, electronic paper, mobile phone, tablet computer, notebook computer, digital photo frame, Any product or component with a display function, such as a navigator.
- the display device 1 may also include other conventional components such as a display panel, which is not limited in the embodiment of the present disclosure.
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Abstract
Description
Claims (30)
- 一种显示基板,包括:衬底基板以及设置在所述衬底基板上的多个移位寄存器单元,其中,所述多个移位寄存器单元沿第一方向并列排布;所述多个移位寄存器单元中的每个包括输入电路、输出电路、第一复位电路和帧复位信号连接走线;所述帧复位信号连接走线沿第二方向延伸,且被配置为向所述第一复位电路提供帧复位信号,所述第二方向与所述第一方向彼此交叉;所述输入电路被配置为响应于输入信号以控制第一节点的电平;所述输出电路被配置为接收时钟信号,并在所述第一节点的电平的控制下将所述时钟信号作为输出信号输出至输出端;所述第一复位电路被配置为响应于所述帧复位信号,以在所述显示基板的两个显示帧之间的时间段内对所述第一节点以及所述输出端进行复位;所述第一复位电路包括第一晶体管和第二晶体管,所述帧复位信号连接走线、所述第一晶体管的栅极以及所述第二晶体管的栅极设置在第一导电层;所述移位寄存器单元还包括设置在第二导电层的第一转接电极,所述第一晶体管的栅极与所述第二晶体管的栅极连接,且均通过所述第一转接电极与所述帧复位信号连接走线电连接。
- 根据权利要求1所述的显示基板,其中,所述第一晶体管与所述第二晶体管沿所述第二方向相邻排布;所述移位寄存器单元还包括沿所述第二方向延伸的第一电压连接走线,所述第一电压连接走线被配置为向所述移位寄存器单元提供第一电压,所述第一电压用于在所述显示基板的两个显示帧之间的时间段内对所述第一节点以及所述输出端进行复位;所述第一电压连接走线、所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极均设置在所述第二导电层;所述第一晶体管的第一极与所述第一节点电连接,所述第二晶体管的第一极与所述输出端电连接,所述第一晶体管的第二极以及所述第二晶体管的第二极均与所述第一电压连接走线电连接。
- 根据权利要求2所述的显示基板,其中,所述移位寄存器单元还包括设置在所述第二导电层且沿所述第一方向延伸的分支走线,所述分支走线与所述第一电压连接走线连接;所述第一晶体管的第二极和所述第二晶体管的第二极分别布置在所述分支走线的两侧,且均与所述分支走线连接。
- 根据权利要求1-3任一所述的显示基板,其中,所述第一晶体管与所述第二晶体管的尺寸相同。
- 根据权利要求2-4任一所述的显示基板,其中,所述多个移位寄存器单元包括在所述第一方向上相邻设置的第一移位寄存器单元和第二移位寄存器单元,所述第一移位寄存器单元与所述第二移位寄存器单元共用同一条所述第一电压连接走线,且相对于所述第一电压连接走线轴对称分布。
- 根据权利要求2-5任一所述的显示基板,其中,所述移位寄存器单元还包括沿所述第二方向延伸的输入信号连接走线,所述输入信号连接走线被配置为向所述输入电路提供所述输入信号;所述输入电路包括第三晶体管,所述输入信号连接走线以及所述第三晶体管的栅极均设置在所述第一导电层,所述第三晶体管的栅极与所述输入信号连接走线连接;所述第三晶体管的第一极和第二极均设置在所述第二导电层,所述第三晶体管的第一极与所述第三晶体管的栅极电连接,所述第三晶体管的第二极与所述第一晶体管的第一极连接,且所述第一节点为所述第三晶体管的第二极与所述第一晶体管的第一极的汇合点。
- 根据权利要求6所述的显示基板,其中,所述移位寄存器单元还包括设置在所述第一导电层的第二转接电极以及设置在所述第二导电层的第三转接电极,所述第二转接电极和所述第三转接电极在所述衬底基板上的正投影至少部分重叠;所述第二转接电极与所述第三晶体管的栅极连接,所述第三转接电极与所述第三晶体管的第一极连接,所述第二转接电极与所述第三转接电极电连接。
- 根据权利要求7所述的显示基板,其中,所述第三晶体管的第一极包括沿所述第一方向延伸的第一连接部以及多个沿所述第二方向延伸的第一突出部,所述第一连接部与所述第三转接电极连接,所述多个第一突出部分别与所述第一连接部连接,所述多个第一突出部之间形成多个第一凹陷部;所述第三晶体管的第二极包括沿所述第一方向延伸的第二连接部以及多个沿所述第二方向延伸的第二突出部,所述多个第二突出部分别与所述第二连接部连接,所述多个第二突出部之间形成多个第二凹陷部;所述多个第一突出部伸入所述多个第二凹陷部中,以使得所述多个第二突出部和所述多个第一突出部沿所述第一方向依次间隔排布。
- 根据权利要求7或8所述的显示基板,其中,所述移位寄存器单元还包括沿所述第二方向延伸的时钟信号连接走线,所述时钟信号连接走线被配置为向所述输出电路提供时钟信号;所述输出电路包括第四晶体管和第一电容;所述第四晶体管的栅极以及所述第一电容的第一极设置在所述第一导电层,且所述第一电容的第一极位于所述第四晶体管的栅极靠近所述显示基板的显示区域的一侧;所述第四晶体管的第一极和第二极、所述第一电容的第二极以及所述时钟信号连接走 线均设置在所述第二导电层;所述第四晶体管的栅极与所述第三晶体管的第二极电连接,所述第四晶体管的第一极与所述时钟信号连接走线连接以接收所述时钟信号,所述第四晶体管的第二极与所述第二晶体管的第一极连接;所述第一电容的第一极与所述第四晶体管的栅极连接,所述第一电容的第二极与所述第四晶体管的第二极连接。
- 根据权利要求9所述的显示基板,其中,所述第四晶体管包括多个沿所述第二方向并联的子晶体管,每个所述子晶体管包括设置在所述第一导电层的栅极、设置在所述第二导电层的第一极和第二极、以及设置在半导体层的有源层;多个所述子晶体管的栅极彼此连接,多个所述子晶体管的第一极彼此连接,多个所述子晶体管的第二极彼此连接,多个所述子晶体管的有源层沿所述第二方向依次排布,且彼此独立不连接。
- 根据权利要求9或10所述的显示基板,其中,所述时钟信号连接走线与所述输入信号连接走线在所述衬底基板上的正投影部分平行,且部分重叠。
- 根据权利要求9-11任一所述的显示基板,其中,所述移位寄存器单元还包括设置在所述第一导电层的第四转接电极和设置在所述第二导电层的第五转接电极,所述第四转接电极和所述第五转接电极在所述衬底基板上的正投影至少部分重叠,且所述第四转接电极与所述第五转接电极电连接;所述第四转接电极在所述第三晶体管的栅极与所述第一晶体管的栅极之间,所述第五转接电极在所述第三晶体管的第二极与所述第一晶体管的第一极之间;所述第四转接电极与所述第四晶体管的栅极电连接,所述第五转接电极与所述第一晶体管的第一极以及所述第三晶体管的第二极连接。
- 根据权利要求12所述的显示基板,其中,所述移位寄存器单元还包括设置在所述第一导电层的第一连接电极,所述第一连接电极的两端分别与所述第四晶体管的栅极以及所述第四转接电极连接;所述第一连接电极位于所述输入信号连接走线靠近所述第一晶体管的一侧,且所述第一连接电极与所述输入信号连接走线在所述衬底基板上的正投影部分平行。
- 根据权利要求12或13所述的显示基板,其中,所述移位寄存器单元还包括控制电路,所述控制电路配置为根据所述第一节点的电平控制第二节点的电平;所述控制电路包括第五晶体管、第六晶体管、第七晶体管以及第八晶体管,所述第五晶体管的栅极、所述第六晶体管的栅极、所述第七晶体管的栅极以及所述第八晶体管的栅极均设置在所述第一导电层,所述第五晶体管的第一极和第二极、所述第六晶体管的第一极和第二极、所述第七晶体管的第一极和第二极以及所述第八晶体管的第一极和第二极均设置在所述第二导电层;所述第八晶体管的栅极与所述第八晶体管的第一极电连接,且被配置为接收不同于所述第一电压的第二电压,所述第八晶体管的第二极与所述第七晶体管的第一极连接,所述第七晶体管的栅极与所述第六晶体管的栅极连接,所述第七晶体管的第二极与所述第一电压连接走线连接;所述第五晶体管的栅极与所述第八晶体管的第二极电连接,所述第五晶体管的第一极与所述第六晶体管的第一极电连接,所述第五晶体管的第二极与所述第八晶体管的第一极电连接,所述第六晶体管的栅极与所述第四转接电极连接,所述第六晶体管的第二极与所述第一电压连接走线连接;所述第二节点为所述第五晶体管的第一极与所述第六晶体管的第一极的汇合点。
- 根据权利要求14所述的显示基板,其中,所述第八晶体管、所述第七晶体管以及所述第六晶体管沿所述第二方向依次相邻排布,所述第五晶体管和所述第八晶体管沿所述第一方向相邻排布,所述第六晶体管和所述第三晶体管沿所述第一方向相邻排布。
- 根据权利要求14或15所述的显示基板,其中,所述移位寄存器单元还包括设置在所述第一导电层的第六转接电极和设置在所述第二导电层的第七转接电极,所述第六转接电极和所述第七转接电极在所述衬底基板上的正投影至少部分重叠,且所述第六转接电极与所述第七转接电极电连接;所述第六转接电极在所述第五晶体管的栅极与所述第八晶体管的栅极之间,且与所述第八晶体管的栅极连接;所述第七转接电极在所述第五晶体管的第二极与所述第八晶体管的第一极之间,且与所述第五晶体管的第二极以及所述第八晶体管的第一极均连接。
- 根据权利要求16所述的显示基板,其中,所述移位寄存器单元还包括设置在所述第一导电层的第八转接电极和设置在所述第二导电层的第九转接电极,所述第八转接电极和所述第九转接电极在所述衬底基板上的正投影至少部分重叠,且所述第八转接电极与所述第九转接电极电连接;所述第八转接电极在所述第六转接电极靠近所述显示区域的一侧,且所述第八转接电极与所述第六转接电极沿所述第二方向相邻排布;所述第九转接电极在所述第七转接电极靠近所述显示区域的一侧,且所述第九转接电极与所述第七转接电极沿所述第二方向相邻排布;所述第八转接电极与所述第五晶体管的栅极连接,所述第九转接电极与所述第八晶体管的第二极以及所述第七晶体管的第一极连接。
- 根据权利要求14-17任一所述的显示基板,其中,所述移位寄存器单元还包括第二复位电路,所述第二复位电路被配置为响应于所述输入信号以控制所述第二节点的电平;所述第二复位电路包括第九晶体管,所述第九晶体管的栅极设置在所述第一导电层,所述第九晶体管的第一极和第二极设置在所述第二导电层;所述第九晶体管的栅极与所述第二转接电极连接,所述第九晶体管的第一极与所述第 五晶体管的第一极连接,所述第九晶体管的第二极与所述第七晶体管的第二极连接。
- 根据权利要求18所述的显示基板,其中,所述第五晶体管、所述第九晶体管以及所述第三晶体管沿所述第二方向依次排布;所述第二转接电极位于所述第九晶体管的栅极与所述第三晶体管的栅极之间;所述第九晶体管与所述第七晶体管沿所述第一方向相邻排布。
- 根据权利要求19所述的显示基板,其中,所述移位寄存器单元还包括设置在第二导电层的第二连接电极,所述第二连接电极的两端分别与所述第九晶体管的第一极以及所述第六晶体管的第一极连接。
- 根据权利要求18-20任一所述的显示基板,其中,所述移位寄存器单元还包括第三复位电路,所述第三复位电路被配置为在所述第二节点的电平的控制下对所述第一节点以及所述输出端进行复位;所述第三复位电路包括第十晶体管和第十一晶体管;所述第十晶体管的栅极和所述第十一晶体管的栅极设置在所述第一导电层,所述第十晶体管的第一极和第二极、以及所述第十一晶体管的第一极和第二极设置在所述第二导电层;所述第十晶体管的栅极与所述第十一晶体管的栅极连接,且所述第十晶体管的栅极和所述第十一晶体管的栅极均与所述第二节点电连接,所述第十晶体管的第一极与所述第一晶体管的第一极连接,所述第十一晶体管的第一极与所述第二晶体管的第一极连接,所述第十晶体管的第二极和所述第十一晶体管的第二极均与所述第一电压连接走线电连接。
- 根据权利要求21所述的显示基板,其中,所述第十晶体管和所述第十一晶体管沿所述第二方向相邻排布,所述第十晶体管和所述第一晶体管沿所述第一方向相邻排布,所述第十一晶体管和所述第二晶体管沿所述第一方向相邻排布。
- 根据权利要求22所述的显示基板,其中,所述移位寄存器单元还包括设置在所述第一导电层的第十转接电极以及设置在所述第二导电层的第十一转接电极,所述第十转接电极和所述第十一转接电极在所述衬底基板上的正投影至少部分重叠,且所述第十转接电极与所述第十一转接电极电连接;所述第十转接电极在所述第六晶体管的栅极与所述第十晶体管的栅极之间,且与所述第十晶体管的栅极连接;所述第十一转接电极与所述第六晶体管的第一极连接。
- 根据权利要求21-23任一所述的显示基板,其中,所述第十一晶体管的长与所述第二晶体管的长相等,所述第十晶体管的长小于所述第十一晶体管的长,所述第十晶体管的宽与所述第十一晶体管的宽相等。
- 根据权利要求21-24任一所述的显示基板,其中,所述移位寄存器单元还包括第四复位电路,所述第四复位电路被配置为响应于扫描复位信号对所述第一节点进行复位;所述第四复位电路包括第十二晶体管,所述第十二晶体管位于所述第一电容靠近所述显示区域的一侧;所述第十二晶体管的栅极设置在所述第一导电层,所述第十二晶体管的第一极和第二极设置在所述第二导电层;所述第十二晶体管的栅极被配置为接收所述扫描复位信号,所述第十二晶体管的第一极与所述第一节点电连接,所述第十二晶体管的第二极与所述第一电压连接走线连接。
- 根据权利要求25所述的显示基板,其中,所述移位寄存器单元还包括设置在第二导电层的第十二转接电极,所述第十二转接电极与所述第十二晶体管的第一极连接,所述第十二转接电极和所述第一电容的第一极在所述衬底基板上的正投影至少部分重叠,且所述第十二转接电极与所述第一电容的第一极电连接。
- 根据权利要求25或26所述的显示基板,其中,所述移位寄存器单元中的任意一个晶体管的第一极和第二极中的一个在所述衬底基板上的正投影的形状包括至少一个U型,该晶体管的第一极和第二极中的另一个在所述衬底基板上的正投影的形状包括至少一个I型。
- 根据权利要求1-27任一所述的显示基板,其中,所述移位寄存器单元中的任意一个晶体管的栅极在所述衬底基板上的正投影覆盖该晶体管的有源层在所述衬底基板上的正投影。
- 根据权利要求1-28任一所述的显示基板,其中,所述多个移位寄存器单元包括在所述第一方向上依次相邻设置的第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元以及第四移位寄存器单元;所述第四移位寄存器单元中的输入电路与所述第一移位寄存器单元的输出电路连接,以将所述第一移位寄存器单元的输出信号作为所述第四移位寄存器单元的输入信号。
- 一种显示装置,包括如权利要求1-29任一所述的显示基板。
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