WO2021254368A1 - 一种内存条、计算机和服务器 - Google Patents

一种内存条、计算机和服务器 Download PDF

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Publication number
WO2021254368A1
WO2021254368A1 PCT/CN2021/100280 CN2021100280W WO2021254368A1 WO 2021254368 A1 WO2021254368 A1 WO 2021254368A1 CN 2021100280 W CN2021100280 W CN 2021100280W WO 2021254368 A1 WO2021254368 A1 WO 2021254368A1
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Prior art keywords
data
memory
chip
flash memory
volatile memory
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PCT/CN2021/100280
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English (en)
French (fr)
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郑晓刚
郑晓熙
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浙江绍兴青逸信息科技有限责任公司
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Publication of WO2021254368A1 publication Critical patent/WO2021254368A1/zh
Priority to US17/978,940 priority Critical patent/US20230050592A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1479—Generic software techniques for error detection or fault masking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of computer storage technology, in particular to a memory bar, a computer, and a server.
  • Memory also known as main memory, is a storage space that can be directly addressed by a central processing unit (CPU), and is made of semiconductor devices.
  • CPU central processing unit
  • Memory is the main component of the computer.
  • the programs that are usually used such as Windows operating system, typing software, game software, etc., are generally installed on external storage such as hard disks, but their functions cannot be used alone, and they must be installed. It can be used only when it is transferred to the memory to run. For example, inputting a paragraph of text or playing a game is actually done in memory.
  • a large amount of data to be stored permanently is stored on the external memory, and some temporary or a small amount of data and programs are stored on the memory. Therefore, the quality of the memory will directly affect the operating speed of the computer.
  • the memory generally uses semiconductor storage units, including random access memory (RAM), read-only memory (Read-Only Memory, ROM), and cache (CACHE). Just because RAM is the most important memory among them. Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) RAM.
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDR Double Data Rate
  • a non-volatile dual in-line memory module is a non-volatile memory that can be randomly accessed for use in computers.
  • Non-volatile memory is memory that retains its contents even if the power is interrupted. This includes unexpected power outages, system crashes, or graceful shutdowns.
  • NVDIMM can improve application performance, data security, and system crash recovery time. This enhances the durability and reliability of solid state disks (Solid State Disk, SSD).
  • NVDIMM-N memory module is a memory module that combines DDR4 DRAM memory and flash memory, and uses flash memory as data backup to prevent power failure.
  • FIG. 1 it is a structural structure diagram of a NVDIMM-N memory module in the prior art, and the NVDIMM-N memory module 1 is installed in a server memory slot.
  • NVDIMM-N memory module 1 is connected to the central processing unit (CPU) 2 and power supply 3 of the server.
  • NVDIMM-N memory module 1 includes NVDIMM controller 110 and multiple dynamic random access devices.
  • the NVDIMM controller 110 is respectively connected to the plurality of DRAM 111 and the flash memory 112, and the power adapter 113 is connected to the power supply of the server.
  • This kind of NVDIMM-N memory module can quickly write the data of the memory into the particles when the power is cut off unexpectedly to reduce data loss and other losses. It is very suitable for enterprise-level users or users with high data requirements.
  • the NVDMM-N controller and flash memory particles squeeze the space of the memory DRAM particles, so the capacity of the NVDIMM-N memory module will be small, and the memory DRAM particles can only occupy about half of the entire NVDIMM-N area. Therefore, the NVDIMM-N memory module There is an application problem with too small capacity.
  • the example of this application provides a memory bar, a computer and a server including the content bar, and the content bar can expand the capacity as much as possible in a limited space.
  • the first aspect of the present application provides a memory module, including: a control chip, at least one data flash memory chip, at least two memory particles, and at least one non-volatile memory particle, wherein each data flash memory chip is connected to at least one memory particle And connecting at least one non-volatile memory particle, the control chip is respectively connected to all data flash memory chips and all memory particles, and the memory bar is also connected to at least one capacitor;
  • the control chip is used to send control commands
  • Each of the data flash memory chips is used to perform data processing between the memory particles and the non-volatile memory connected respectively according to the control command of the control chip.
  • control command includes a data backup command and a data read command, where:
  • the control chip is configured to send the data backup command to each data flash memory chip and send a data read command to each memory particle under the power supply of the capacitor when the power is abnormally cut off;
  • Each memory particle is used to send its data to the data signal line according to the data read command under the power of the capacitor;
  • Each of the data flash memory chips is configured to obtain the data sent by the memory particles connected to it from the data signal line according to the data backup command under the power of the capacitor and write it to the at least one connected to it.
  • a non-volatile memory is configured to obtain the data sent by the memory particles connected to it from the data signal line according to the data backup command under the power of the capacitor and write it to the at least one connected to it.
  • each data flash memory chip is further configured to confirm whether the non-volatile memory connected to it can store data before the control chip sends the data read command; when each data flash memory chip When the flash memory chip confirms that the non-volatile memory connected to it can store data, it sends a backup preparation complete message to the control chip.
  • control command includes a data recovery command and a data write command, where:
  • the control chip is configured to send the data recovery command to each data flash memory chip and send the data write command to each memory particle when power is restored;
  • Each of the data flash memory chips is configured to read data from at least one non-volatile memory connected to it according to the data recovery command when power is restored and send the read data to the data signal line;
  • Each of the memory particles is used to obtain the data sent by the data flash memory chip connected to the data signal line from the data signal line according to the data write command in the case of power recovery, and write it into the data.
  • each data flash memory chip is further configured to determine whether the non-volatile memory connected to it is ready before the control chip sends the data write command to each memory particle After data recovery is completed, if the non-volatile memory is ready for data recovery, a data recovery preparation complete message is sent to the control chip.
  • control chip includes at least one control PIN pin
  • memory module further includes at least one multiplexer switch
  • control chip is connected to at least one multiplexer switch through the at least one control PIN pin
  • the at least one multiplexer The way selection switch connects all the memory particles, and the multiple way selection switch is used to select whether the CPU or the control chip is used to read the memory particle connections.
  • the location where the data of each memory particle is stored in the at least one non-volatile memory is corresponding; or, the data of each memory particle is stored in the at least one non-volatile memory The fixed position of the data sequence to be written.
  • control chip is further configured to determine the flow control rate according to the number and performance of all memory particles and the number and processing capacity of the data flash memory chip.
  • the storage capacity of each non-volatile memory is greater than the storage capacity of all memory particles connected to the data flash chip connected to it.
  • control chip is connected to each data flash memory chip through a serial-parallel SerDes bus.
  • control chip 101 is further configured to receive an abnormal power failure notification sent by the hardware of the CPU, and determine the current abnormal power failure according to the abnormal power failure notification.
  • each data flash memory chip is also used to determine whether the non-volatile memory connected to it is faulty, and when the non-volatile memory is not faulty, it is determined that the non-volatile memory can store data; or, each The data flash chip is also used to determine whether the remaining capacity of the non-volatile memory connected to it is greater than or equal to a threshold, and when it is greater than or equal to the threshold, it is determined that the non-volatile memory can store data.
  • the storage capacity of each non-volatile memory is 1.5, 2, 3, 4, or 5 times the storage capacity of all memory particles connected to the data flash chip connected to it.
  • a computer which includes the aforementioned memory module.
  • a server includes the aforementioned memory module.
  • the data signal and the control signal are separated and managed by two chips: the control chip is responsible for outputting control signals, and the data flash memory chip is responsible for data processing.
  • the data signals of the degenerate memory and the memory particles are no longer transmitted through the control chip, which greatly reduces the connection of the memory particles to the control chip, and also reduces the size of the control chip, thereby giving more area to the memory particles and improving the central
  • the wiring at the location is crowded, and the signal transmission speed is also increased.
  • FIG. 1 is a schematic diagram of the structure of a memory module in the prior art.
  • Figure 2 is a schematic structural diagram of a memory module according to an example of the application.
  • FIG. 3 is a schematic structural diagram of another memory module according to another example of the application.
  • FIG. 4 is a schematic structural diagram of another memory module according to another example of the application.
  • FIG. 2 it is a schematic structural diagram of a memory module according to an embodiment of this application.
  • the memory module 10 can be used in various computers or servers, for example, a notebook computer or a desktop computer, and the memory module 10 can be connected to a capacitor. 11 and CPU12, the capacitor 11 is used to supply power to the memory module 10 when the power is off.
  • the capacitor 11 can supply power to the memory module 10 to work for a period of time, and the working time depends on the The size of the capacitor 11 depends on the size. When the power is restored, the capacitor 11 can be charged by the power supply.
  • the memory module 10 may be a non-volatile memory (NVDIMM-N).
  • the memory module 10 includes a control chip 101, at least one data flash memory chip, at least two memory particles, and at least one non-volatile memory 106, wherein each data flash memory chip is connected to at least two memory particles At least one non-volatile memory 106 is connected, and the control chip 101 is connected to all data flash memory chips and all memory particles.
  • the control chip 101 is connected to all memory particles through a multiplexer (MUX) 108.
  • MUX multiplexer
  • control chip 101 may be referred to as a main control chip, for example, may be an NVDIMM control chip.
  • the data flash memory chip may be referred to as a data chip, for example, it may be an NVIDMM data flash memory chip.
  • the at least one data flash memory chip includes a first data flash memory chip 102 and a second data flash memory chip 103.
  • a data flash memory chip 102 is connected to four memory particles 104
  • the second data flash memory chip 103 is connected to four memory particles 105.
  • the memory particles 104 and 105 may be Memory particles, DDR particles, DRAM particles, or SDRAM particles, which is not limited in this example.
  • the non-volatile memory 106 may be called a Flash flash memory
  • the first non-volatile memory 106 may also be one or more
  • each data flash memory chip is also connected to at least one The first non-volatile memory 106.
  • the first data flash memory chip 102 is connected to at least one first non-volatile memory 106
  • the second data flash memory chip 103 is connected to at least one second non-volatile memory 107.
  • each non-volatile memory includes matrix-type non-volatile storage units, such as 2, 4, 8, n non-volatile storage units, and n is a power of 2.
  • the storage capacity of each non-volatile memory is greater than the storage capacity of all memory particles connected to the data flash chip connected to it.
  • the storage capacity of each non-volatile memory is The storage capacity of all the memory particles connected to the data flash chip connected to it is 1.5, 2, 3, 4 or 5 times.
  • the storage capacity of the first non-volatile memory 106 is greater than the storage capacity of all memory particles, for example, the storage capacity of the non-volatile memory 106 is all
  • the storage capacity of the memory particles is 1.5, 2, 3, 4 or 5 times.
  • the storage capacity of the first non-volatile memory 106 is greater than that connected to the first data flash memory chip 102
  • the storage capacity of all the memory particles of the second non-volatile memory 107 is greater than the storage capacity of all the memory particles connected to the second data flash memory chip 103, for example, the first non-volatile memory 106 and
  • the storage capacity of the second non-volatile memory 107 is 1.5, 2, 3, 4, or 5 times the storage capacity of all the memory particles connected to it, respectively.
  • control chip 101 is connected to each data flash memory chip via a serializer/deserializer (Serializer/Deserializer, SerDes) bus.
  • SerDes serializer/Deserializer
  • the control chip 101 is connected to each data flash memory chip via a SerDes bus.
  • the first data flash memory chip 102 and the second data flash memory chip 103 are connected.
  • the control chip 101 is used to send control commands, for example, to send a control command to each data flash memory chip and to send a data processing control command to each memory particle, for example, the control command includes a DDR address and/or a clock , A data backup command or a data recovery command, the data processing control command includes a data read command and a data write command.
  • Each of the data flash memory chips is used to perform data processing between the memory particles connected to the data flash memory chip and the non-volatile memory according to the control command of the control chip 101, for example, when the power is abnormally cut off,
  • each data flash chip backs up the data of its connected memory particles to its connected corresponding non-volatile memory to implement data backup processing.
  • the data recovery command issued by the control chip 101 restores the data of the non-volatile memory connected to it to the corresponding memory particle connected to it to implement data recovery processing.
  • control chip 101 is used to send a data read command (for example, a DDR read command) to the memory particle connected to it through the multiplex switch 108 when the power is abnormally cut off, so that the memory particle can send its data.
  • a data read command for example, a DDR read command
  • the control chip 101 is used to send a data read command (for example, a DDR read command) to the memory particle connected to it through the multiplex switch 108 when the power is abnormally cut off, so that the memory particle can send its data.
  • a data read command for example, a DDR read command
  • the control chip 101 is used to send data write commands (for example, DDR write commands) to the memory particles connected to it through the multiplex switch 108 when the power is restored, and when the data flash memory chip connects it to the nonvolatile When the data in the sexual memory is sent to the data signal line, the memory particle reads the data from the data signal line according to the data write command and writes it inside.
  • data write commands for example, DDR write commands
  • the data signal and the control signal are separated and managed by two chips: the control chip is responsible for outputting the control signal, and the data flash memory chip is responsible for data processing. Then through the control chip transmission, this greatly reduces the connection of the memory particles to the control chip, and also reduces the size of the control chip, thereby giving more area to the memory particles, also improving the congestion of the wiring at the central location, and increasing the signal transmission speed. .
  • the above-mentioned memory bar can also select the position of the data flash memory chip and the flash memory particles connected to it according to the placement position of the memory particles.
  • the position close to the Dual-Inline-Memory-Modules (DIMM) slot can be reserved for the memory particles, and the data flash memory chip and the flash memory particles connected to it can be placed far away from the DIMM slot.
  • the memory particles can have a larger area and can be placed in two rows, thereby increasing the capacity of the memory stick.
  • the data flash memory chip and the control chip bus use SerDes, so that the speed is faster, the number of signals is small and it is expandable.
  • the memory module of this embodiment can use flow control technology to achieve high bandwidth and low latency, thereby reducing the capacity requirements for the super capacitor.
  • each data flash memory chip is connected to multiple flash memory particles to achieve higher bandwidth and faster speed, thereby reducing the capacity requirements for the super capacitor.
  • the initialization process of the memory module 10 may be as follows.
  • the data flash memory chip and the control chip 101 are in a reset state.
  • the data flash chip and the control chip 101 leave the reset state, start self-initialization, set control parameters, and simulate and I/O initialization are in the ready state.
  • the control chip 101 is set to the write training state: the control chip 101 first informs the data flash memory chip to write training through the bus between the control chip 101 and the data flash memory chip, and then the DDR controller on the host (HOST) side drives the DDR control signal to send Write a command to the control chip 101, and then the control chip 101 informs the data flash chip that it is ready to accept data and sends a DDR read command to the memory particle.
  • the memory particle sends its data to the DDR data line according to the DDR read command.
  • the data is intercepted on the DDR data line and written into the corresponding non-volatile memory.
  • control chip 101 is set by the HOST to read the training state: the control chip 101 first informs the data flash memory chip to read training through the bus between the control chip 101 and the data flash memory chip. After the data flash chip receives the training command from the control chip 101, it reads data from the non-volatile memory and sends it to the DDR data line. The memory particles read data from the DDR data line according to the DDR write command issued by the control chip 101 And write it inside.
  • the Host side reads the DDR memory data to confirm.
  • the control chip 101 informs the data flash memory chip through the internal bus.
  • the control chip 101 is configured to receive an abnormal power failure notification sent by the device hardware connected to the memory module 10, and determine the abnormal power failure according to the abnormal power failure notification.
  • the control chip 101 is configured to receive an abnormal power failure notification sent by the hardware of the CPU 12, and the current abnormal power failure can be determined according to the abnormal power failure notification, and the memory module 10 needs to be powered by the capacitor 11.
  • the control chip 101 is configured to send a data backup command for reading the respective connected memory particles to each data flash memory chip under the power supply of the capacitor 11 when the power is abnormally cut off. For example, the control chip 101 sends a data backup command for reading the memory particles 104 connected to the first data flash memory chip 102 to the first data flash memory chip 102; the control chip 101 sends a data backup command to the second data flash memory chip 102 103 sends a data backup command for reading the memory particles 105 connected to the second data flash memory chip 103.
  • control chip 101 determines the flow control rate according to the number and performance of all memory particles and the number and processing capacity of the data flash memory chip.
  • the performance of the memory particles includes read/write The minimum and maximum data rate
  • the processing capability of the data flash chip includes the minimum and maximum rate of processing commands or data
  • the flow control rate includes the rate at which the control chip sends control commands and/or the data flash The rate at which the chip processes commands and/or data.
  • Each data flash memory chip is used to read data from its connected memory particles according to the data backup command under the power of the capacitor 11 and write it to the at least one connected non-volatile memory chip when the power is abnormally cut off.
  • Volatile memory For example, for the memory module of FIG. 2, the first data flash memory chip 102 is used to read data from the connected memory particles 104 under the power of the capacitor 11 when the power is abnormally cut off. And write it into the first non-volatile memory 106 connected to it.
  • the second data flash memory chip 103 is used for when the power is abnormally cut off, under the power of the capacitor 11, according to the data backup command Data is read from the connected memory particle 105 and written into the first non-volatile memory 106 connected to it.
  • the second data flash memory chip 103 is used to read and write data from the connected memory particles 105 according to the data backup command under the power of the capacitor 11 when the power is abnormally cut off.
  • each data flash memory chip for example, the first data flash memory chip 102 and the second data flash memory chip 103
  • each data flash memory chip confirms Whether the connected non-volatile memory can store data
  • each data flash chip determines whether the connected non-volatile memory is faulty, and when the non-volatile memory is not faulty, the non-volatile memory is determined
  • Data can be stored, or each data flash chip determines whether the remaining capacity of the non-volatile memory connected to it is greater than or equal to a threshold, and when it is greater than or equal to the threshold, it is determined that the non-volatile memory can store data.
  • the data flash memory chip When the data flash memory chip confirms that the connected non-volatile memory can store data, it sends a backup preparation complete message to the control chip 101, and then the control chip 101 sends a DDR read command to the memory connected to the data flash memory chip
  • the memory particle sends its data to the data signal line, and then the data flash memory chip intercepts the data of the memory particle from the data signal line and writes it to the data storage device connected to the data flash memory chip On non-volatile memory.
  • the control chip 101 sends a data backup command to the first data flash memory chip 102, and the first data flash memory chip 102 confirms its connection Whether the non-volatile memory 106 can store data, for example, the first data flash chip 102 determines whether the non-volatile memory 106 connected to it is faulty, and when the non-volatile memory 106 is not faulty, it is determined that the non-volatile memory 106 is not faulty.
  • the volatile memory 106 can store data, or the first data flash chip 102 determines whether the remaining capacity of the non-volatile memory 106 connected to it is greater than or equal to a threshold, and when greater than or equal to the threshold, the non-volatile memory is determined 106 can store data.
  • the first data flash chip 102 When the first data flash chip 102 confirms that the non-volatile memory 106 connected to it can store data, it sends a backup preparation complete message to the control chip 101, and then the control chip 101 passes through the multiplexer 108 Send a DDR read command to the memory particle 104 connected to the first data flash memory chip 102, the memory particle 104 sends its data to the data signal line, and then the first data flash memory chip 102 reads from the data signal line The data of the memory particle 104 is intercepted and written to the non-volatile memory 106 connected to the first data flash memory chip 102 and capable of receiving data.
  • control chip 101 further includes a sending unit and a command queue processing unit.
  • the sending unit is used to issue write commands to the command queue in a certain order;
  • the command queue processing unit is used to generate flash memory write commands according to the write command. Enter a command, and send the flash memory write command to each data flash memory chip through an internal bus (for example, a SerDes bus), where the flash memory write command is used to instruct data backup.
  • an internal bus for example, a SerDes bus
  • Each data flash memory chip includes a receiving unit, a sending unit, a data grabbing unit, a storage unit, and a flash memory controller connected to each other.
  • the receiving unit of the data flash memory chip is used to place the flash memory write command in its command queue after receiving the flash memory write command; the sending unit of the data flash memory chip is used to reply to the control chip 101 via the internal bus
  • the preparation completion confirmation information is used to indicate that the preparation of the data flash chip is completed, and subsequent operations can be performed.
  • the control chip 101 is configured to send a data backup command to the data flash memory chip and a DDR read command to the memory particles connected to the data flash memory chip after receiving the confirmation information of the completion of preparation.
  • the memory particle sends its data to the data signal line according to the DDR read command.
  • the receiving unit is also used to receive the data backup command;
  • the data capture unit is used to capture data from the memory particles connected to the data flash memory chip according to the data backup command, that is, to capture data from the data signal line, And placed in a storage unit;
  • the storage unit is used to store the captured data and send the captured data to the flash memory controller;
  • the sending unit is also used to send to the control chip 101 Capture completion command;
  • the flash memory controller is used to write the captured data to the non-volatile memory connected to the data flash memory chip, for example, the non-volatile memory is a flash memory.
  • the location where the data of each memory particle is stored in the non-volatile memory corresponds.
  • the data flash chip stores the data of each memory particle connected to it in a fixed position of each memory particle in the non-volatile memory. For example, there are 1, 2, 3, ..., k memory particles.
  • the storage location of the volatile memory has 232 bits, and each memory particle has a corresponding storage location in the non-volatile memory.
  • the specific physical address is managed by a mapping table, and will not be repeated.
  • the location where the data of each memory particle is stored in the non-volatile memory is distinguished according to the address of each memory particle or the serial number of the PIN pin of the data flash chip.
  • the first A data flash memory chip 102 is connected to four memory particles 104 respectively.
  • the storage location is connected to the first memory particle 104.
  • the serial number of the PIN pin of a data flash chip 102 corresponds.
  • the Host issues a command to the control chip 101, and the control chip 101 sends a data recovery command to each data flash memory chip and a DDR write command to the memory particles.
  • the control chip 101 is configured to send data recovery commands to the first data flash memory chip 102 and the second data flash memory chip 103, and to the memory particles 104 and all the memory particles connected to the first data flash memory chip 102.
  • the memory particle 105 connected to the second data flash memory chip 103 sends a DDR write command.
  • Each of the data flash memory chips is also used to read data from at least one non-volatile memory connected to it according to the data recovery command and write the read data to the connected memory particles when power is restored .
  • the first data flash memory chip 102 is used to read data from the first non-volatile memory 106 according to the data recovery command when power is restored, and to read data Data is written to the connected memory particles 104;
  • the second data flash chip 103 is used to read data from the first non-volatile memory 106 according to the data recovery command and read data from the first non-volatile memory 106 when power is restored The data is written to the connected memory particle 105.
  • the first data flash memory chip 102 is used to read data from the first non-volatile memory 106 according to the data recovery command and write the read data when power is restored
  • the second data flash memory chip 103 is used to read data from the second non-volatile memory 107 according to the data recovery command when power is restored, and the read data Write the connected memory particles 105.
  • the sending module of the control chip 101 sends a flash memory read command to each data flash memory chip through an internal bus, and the flash memory read command is used to instruct data recovery.
  • the receiving unit of the data flash memory chip is used to put the flash memory read command into its command queue after receiving the flash memory read command, and concurrently send the command queue.
  • the flash memory controller of the data flash chip determines whether the connected non-volatile memory is ready for data recovery according to the flash read command, for example, determines whether the non-volatile memory is faulty, and if there is no fault, determines the non-volatile memory
  • the volatile memory is ready for data recovery.
  • the non-volatile memory may be a flash memory.
  • the data flash chip determines that the non-volatile memory connected to it is ready for data recovery, it sends the control chip 101 an indication message indicating that the data recovery preparation is complete.
  • control chip 101 After receiving the instruction information, the control chip 101 sends a DDR write command to the memory particles connected to the data flash memory chip through the multiplex switch 108.
  • the data flash memory chip obtains data from the connected non-volatile memory according to the data recovery command and sends it to the data signal line.
  • the memory particle connected to the data flash memory chip acquires data from the data signal line according to a DDR write command and writes it into it. For example, the memory particle writes the acquired data to its internal storage unit.
  • the data flash chip sends a data recovery completion command to the control chip 101.
  • the data flash memory chip can write the data stored in the non-volatile memory until the abnormal power failure occurs.
  • the corresponding memory particle that is, the data of the memory particle can be restored.
  • each memory particle is no longer connected to a control chip, but the command and data are separated by the control chip and the data flash memory chip, so the connection between the memory particle and the control chip can be greatly reduced.
  • the memory module 30 can be connected to a capacitor 31 and a CPU 32, and the capacitor 31 is used to supply power to the memory module 30 when the power is off.
  • the capacitor 31 can supply power to the memory module 30 to work for a period of time. The working time depends on the size of the capacitor 31.
  • the capacitor 31 can be charged by the power supply. .
  • the memory module 30 may be a non-volatile memory (NVDIMM-N).
  • the memory module 30 includes a control chip 301, at least two data flash memory chips, at least one multiplexer (MUX) 306, at least two memory particles and at least two non-volatile memories, wherein each The data flash memory chip is connected to at least two memory particles and at least one non-volatile memory through a data link, and the control chip 301 is connected to each data flash memory chip. Each data flash memory chip is connected, and the control chip 301 also connects all memory particles through the multiplexer 306.
  • MUX multiplexer
  • the at least two data flash memory chips include: a first data flash memory chip 302, a second data flash memory chip 303, a third data flash memory chip 304, and a fourth data flash memory chip 305, and the non-volatile memory is a plurality of Flash.
  • the control chip 301 is respectively connected to the first data flash memory chip 302, the second data flash memory chip 303, the third data flash memory chip 304, and the fourth data flash memory chip 305 through a SerDes bus.
  • the control chip 301 also includes a control PIN pin through which the control chip 301 is connected to the multiplex switch 306, and the multiplex switch 306 is respectively connected to each memory particle, for example, the multiplexer
  • the way selection switch 306 connects a plurality of memory particles.
  • the first data flash memory chip 302, the second data flash memory chip 303, and the third data flash memory chip 304 are respectively connected to at least two memory particles and connected to at least one Flash, and the fourth data flash memory chip 305 is connected At least two memory particles and at least one Flash connected.
  • Each MUX is connected to at least two memory particles, the control chip 301 is connected to the memory particles through the MUX, and the number of memory particles connected to each MUX can be preset.
  • the memory particles may be RDIMM particles or SDRAM particles, which is not limited in this example.
  • the non-volatile memory may be referred to as a Flash flash memory, the non-volatile memory may also be one or more, and each data flash memory chip is connected to at least one of the non-volatile memory chips.
  • the storage capacity of each non-volatile memory is greater than the storage capacity of all memory particles connected to the data flash chip connected to it, for example, the storage capacity of each non-volatile memory is The storage capacity of all memory particles connected to the connected data flash chip is 1.5, 2, 3, 4 or 5 times.
  • the control chip 301 is configured to receive an abnormal power failure notification sent by the device hardware connected to the memory module 30, and determine the abnormal power failure according to the abnormal power failure notification.
  • the control chip 301 is configured to receive an abnormal power failure notification sent by the hardware of the CPU 32. According to the abnormal power failure notification, the current abnormal power failure can be determined, and the memory module 30 needs to be powered by the capacitor 31.
  • the control chip 301 is used to send a data backup command for reading the connected memory particles to each data flash memory chip and to each memory particle under the power supply of the capacitor 31 when the power is abnormally cut off. Data read command.
  • the control chip 301 sends data backup commands to the first data flash memory chip 302, the second data flash memory chip 303, the third data flash memory chip 304, and the fourth data flash memory chip 305, respectively.
  • the control chip 301 sends the data backup command according to the flow control rate.
  • the control chip 301 according to the number and performance of all memory particles and the number and processing of the data flash memory chip Ability to determine flow control rate.
  • Each memory particle is used to send its internal data to a data signal line, for example, a DDR data line, according to the data read command (for example, a DDR read command).
  • a data signal line for example, a DDR data line
  • the data read command for example, a DDR read command
  • Each data flash memory chip is used to read data from its connected memory particles according to the data backup command and write to the at least one non-connected memory chip under the power of the capacitor 31 when the power is abnormally cut off.
  • Volatile memory is the at least one non-volatile memory that intercepts data from the data signal line and writes it to the at least one non-volatile memory connected to it.
  • the first data flash memory chip 302, the second data flash memory chip 303, and/or the third data flash memory chip 304 are used to, when the power is abnormally cut off, under the power supply of the capacitor 31, according to the The data backup command respectively intercepts the data of at least two memory particles connected to the data signal line and writes the data into at least two flashes connected to each.
  • the fourth data flash memory chip 305 is used to intercept the data of at least the memory particles connected to it from the data signal line according to the data backup command under the power of the capacitor 31 when the power is abnormally cut off.
  • the fourth data flash memory chip 305 is connected to at least one Flash.
  • the location where the data of each memory particle is stored in the non-volatile memory corresponds.
  • the data flash chip stores the data of each memory particle connected to it in a fixed position of each memory particle in the non-volatile memory.
  • the storage location of the volatile memory has 232 bits, and each memory particle has a corresponding fixed storage location in the non-volatile memory.
  • the storage location of the first 1-32 bits of the non-volatile memory is used to store the first
  • the 33-64th bit storage location of the non-volatile memory is used to store the data of the second memory particle, etc., which will not be described in detail.
  • the data flash chip stores the data of each memory particle connected to it at a fixed position in the write data sequence of each memory particle in the non-volatile memory, for example, the The non-volatile memory uses a data sequence to write data when writing data.
  • the first 1-32 bits of the written data sequence of the non-volatile memory are used to write the data of the first memory particle.
  • the 33-64th bits of the write data sequence of the volatile memory are used to write the data of the second memory particle, etc., and will not be repeated.
  • the location where the data of each memory particle is stored in the non-volatile memory is distinguished according to the address of each memory particle or the serial number of the data flash memory chip, for example, the first data flash memory
  • the chip 302 is connected to four memory particles 304.
  • the connection serial number of the first data flash memory chip 302 whose storage location is connected to the memory particle correspond.
  • control chip 301 When power is restored, the control chip 301 is also used to send a data recovery command to each data flash memory chip and a data write command (for example, a DDR write command) to the memory particles.
  • a data recovery command for example, a DDR write command
  • the control chip 301 is configured to send data recovery commands to the first data flash memory chip 302, the second data flash memory chip 303, the third data flash memory chip 304, and the fourth data flash memory chip 305, respectively .
  • Each of the data flash memory chips is also used to read data from at least one non-volatile memory connected to it according to the data recovery command when power is restored and send the read data to the data signal line,
  • the memory particle reads data from the data signal line according to the data write command and writes it inside.
  • the first data flash memory chip 302, the second data flash memory chip 303, and/or the third data flash memory chip 304 are used for recovering power from at least two connected devices according to the data recovery command.
  • Each Flash reads data and sends it to the data signal line, and the memory particles connected to each read the data from the data signal line according to the data write command and writes it inside.
  • the fourth data flash memory chip 305 when the fourth data flash memory chip 305 is used to restore power, data is read from at least one Flash connected to it according to the data recovery command and sent to the data signal line.
  • the memory to which the fourth data flash memory chip 305 is connected The particle reads data from the data signal line according to the data write command and writes it inside.
  • the data flash chip can write the data stored in the non-volatile memory to The corresponding memory particle, that is, the data of the memory particle when a power failure occurs, is restored.
  • each memory particle is no longer connected to a control chip, but is shared by the data flash chip, so the connection between the memory particle and the control chip can be greatly reduced, and the control is also reduced.
  • the chip chip size which gives more area to the memory particles, also improves the congestion of the wiring in the central position, and the signal quality is also improved. Therefore, the capacity of the memory module can be greatly increased, and the signal transmission rate is not affected by the length of the connection.
  • control chip is responsible for outputting control commands, such as DDR commands, addresses, clocks and other DDR signals.
  • the data flash chip is responsible for DDR data, such as intercepting data when power is off abnormally, and recovering data when power is restored, so that the signal transmission speed is faster.
  • the communication bus between the control chip and the data flash memory chip is SerDes, so that the speed is faster, the number of signals is small, and it has scalability.
  • the flow control technology is adopted to achieve high bandwidth and low delay, thereby reducing the capacity requirement of the capacitor.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device examples described above are only illustrative.
  • the division of the modules or units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined. Or it can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution in this example.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code .

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Abstract

一种内存条，包括：控制芯片（301）、至少一个数据闪存芯片（302,303,304,305）、至少两个内存颗粒和至少一个非易失性存储器颗粒，其中，每个数据闪存芯片（302,303,304,305）连接至少一个内存颗粒和连接至少一个非易失性存储器颗粒，控制芯片（301）分别连接所有数据闪存芯片（302,303,304,305）和所有内存颗粒，内存条还连接至少一个电容（31）；控制芯片（301），用于发送控制命令；每个数据闪存芯片（302,303,304,305），用于根据控制芯片（301）的控制命令，进行各自连接的内存颗粒和非易失性存储器之间的数据处理。该内存条能在有限的空间下，尽可能大地扩展容量，处理速度更快。

Description

一种内存条、计算机和服务器
本申请要求于2020年6月19日提交中国专利局、申请号为202010566027.2、发明名称为“一种内存条”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机存储技术领域，尤其涉及一种内存条、计算机和服务器。
背景技术
内存(memory)又称主存，是中央处理器(Central Processing Unit，CPU)能直接寻址的存储空间，由半导体器件制成。
内存是计算机中的主要部件，平常使用的程序，如Windows操作系统、打字软件、游戏软件等，一般都是安装在硬盘等外存上的，但仅此是不能使用其功能的，必须把它们调入内存中运行，才能真正使用其功能。例如，平时输入一段文字，或玩一个游戏，其实都是在内存中进行的。通常把要永久保存的、大量的数据存储在外存上，而把一些临时的或少量的数据和程序放在内存上，因此，内存的好坏会直接影响计算机的运行速度。
内存一般采用半导体存储单元，包括随机存储器(random access memory，RAM)、只读存储器(Read-Only Memory，ROM)、高速缓存(CACHE)。只不过因为RAM是其中最重要的存储器。同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)、双倍速率(Double Data Rate，DDR)RAM。
非易失性双列直插式内存模块(non-volatile dual in-line memory  module，NVDIMM)是一种用于计算机的可随机存取的非易失性存储器。非易失性存储器是即使断电也能保留其内容的内存，这包括意外断电、系统崩溃或正常关机。NVDIMM在某些情况下可以改善应用程序的性能、数据安全性和系统崩溃恢复时间。这增强了固态硬盘(Solid State Disk，SSD)的耐用性和可靠性。
NVDIMM-N内存条，是一种将DDR4 DRAM内存与闪存融合在了一起的内存条，运用闪存做数据备份以防掉电。
如图1所示，为现有技术一种NVDIMM-N内存条的架构结构图，所述NVDIMM-N内存条1安装在服务器内存插槽中。从硬件角度来看，NVDIMM-N内存条1连接服务器的中央处理器(central processing unit，CPU)2和电源3，NVDIMM-N内存条1的内部包括NVDIMM控制器110、多个动态随机存取存储器(Dynamic Random Access Memory，DRAM)111、闪存112和电源适配器113，所述NVDIMM控制器110分别连接所述多个DRAM111和闪存112，电源适配器113连接服务器的供电电源。这种NVDIMM-N内存条，当意外断电能将内存的数据快速写入颗粒中，来降低数据丢失等损失，非常适合企业级或对数据有高要求的用户选择。
但是因为要断电保护，需要在断电时把内存DRAM的内容备份到闪存，在电力恢复时把闪存的内容复制到内存DRAM里。这样，NVDMM-N控制器和闪存颗粒挤占内存DRAM颗粒的空间，所以NVDIMM-N内存条的容量会小，内存DRAM颗粒只能占整个NVDIMM-N面积的大概一半，因此，NVDIMM-N内存条存在容量太小应用问题。
发明内容
本申请实例提供内存条以及包括该内容条的计算机和服务器，内容条能在有限的空间下，尽可能大的扩展容量。
本申请的第一方面提供一种内存条，包括：控制芯片、至少一个数据闪存芯片、至少两个内存颗粒和至少一个非易失性存储器颗粒，其中，每个数据闪存芯片连接至少一个内存颗粒和连接至少一个非易失性存储器颗粒，所述控制芯片分别连接所有数据闪存芯片和所有内存颗粒，所述内存条还连接至少一个电容；
所述控制芯片，用于发送控制命令；
所述每个数据闪存芯片，用于根据所述控制芯片的控制命令，进行各自连接的内存颗粒和非易失性存储器之间的数据处理。
可选地，所述控制命令包括数据备份命令和数据读取命令，其中，
所述控制芯片用于当异常断电时，在所述电容的供电下，向所述每个数据闪存芯片发送所述数据备份命令和向所述每个内存颗粒发送数据读取命令；
每个内存颗粒，用于在所述电容的供电下，根据所述数据读取命令将其数据发送至数据信号线上；
所述每个数据闪存芯片，用于在所述电容的供电下，根据所述数据备份命令从所述数据信号线上获取其连接的内存颗粒发送的数据并写入到其连接的所述至少一个非易失性存储器。
可选地，所述每个数据闪存芯片还用于在所述控制芯片发送所述数据读取命令之前，确认其连接的所述非易失性存储器是否能存储数据；当所述每个数据闪存芯片确认其连接的所述非易失性存储器能存储数据时，向所述控制芯片发送备份准备完成消息。
可选地，所述控制命令包括数据恢复命令和数据写入命令，其中，
所述控制芯片，用于当恢复电力时，向所述每个数据闪存芯片发送所述数据恢复命令和向所述每个内存颗粒发送所述数据写入命令；
所述每个数据闪存芯片，用于在恢复电力的情况下根据所述数据恢复命令从其连接的至少一个非易失性存储器读取数据并将读取的数据发送到数据信号线上；
所述每个内存颗粒，用于在恢复电力的情况下根据所述数据写入命令从所述数据信号线上获取其连接的数据闪存芯片发送的数据并写入其内部。
可选地，所述每个数据闪存芯片，还用于在所述控制芯片向所述每个内存颗粒发送所述数据写入命令之前，确定其连接的所述非易失性存储器是否已准备完数据恢复，如果所述非易失性存储器已准备完数据恢复，向所述控制芯片发送数据恢复准备完成消息。
可选地，所述控制芯片包括至少一个控制PIN脚，所述内存条还包括至少一个多路选择开关，控制芯片通过至少一个控制PIN脚与至少一个多路选择开关相连，所述至少一个多路选择开关连接所有内存颗粒，多路选择开关用于选择是CPU还是控制芯片来读取内存颗粒连接。
可选地，所述每个内存颗粒的数据存储到所述至少一个非易失性存储器的位置是对应的；或，所述每个内存颗粒的数据存储到所述至少一个非易失性存储器被写入数据序列的固定位置。
可选地，所述控制芯片还用于根据所有内存颗粒的数量和性能和所述数据闪存芯片的数量和处理能力确定流控速率。
可选地，每个非易失性存储器的存储容量大于其连接的数据闪存芯片所连接的所有内存颗粒的存储容量。
可选地，所述控制芯片通过串并SerDes总线与所述每个数据闪存芯片连接。
可选地，所述控制芯片101还用于接收CPU的硬件发送的异常断电通知，根据该异常断电通知确定当前异常断电。
可选地，每个数据闪存芯片还用于判断其连接的非易失性存储器是否故障，当该非易失性存储器未故障时，确定该非易失性存储器能存储数据；或者，每个数据闪存芯片还用于判断其连接的非易失性存储器的剩余容量是否大于等于阈值，当大于等于阈值时，确定该非易失性存储器能存储数据。
可选地，每个所述非易失性存储器的存储容量为其连接的数据闪存芯片所连接的所有内存颗粒的存储容量1.5，2、3、4或5倍。
本申请的第二方面，提供一种计算机，包括前述的内存条。
本申请的第三方面，一种服务器，包括前述的内存条。
上述描述的内存条以及包括该内存条的计算机和服务器，在内存条中，将数据信号和控制信号分开由两个芯片管理：控制芯片负责输出控制信号，数据闪存芯片负责数据处理，则非易失性存储器与内存颗粒的数据信号不再通过控制芯片传输，这大大减少内存颗粒到控制芯片的连线，也减小了控制芯片尺寸，从而给内存颗粒更多的面积，也改善了在中央位置的布线拥挤，信号传输速度也提高。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的一种内存条的结构示意图。
图2为本申请一个实例的一种内存条的结构示意图。
图3为本申请另一个实例的另一种内存条的结构示意图。
图4为本申请另一个实例的另一种内存条的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实例是本申请一部分实例，而不是全部的实例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
如图2所示，为本申请一个实施例的一种内存条的结构示意图，内存条10可以用于各种计算机或服务器，例如，笔记本计算机或台式机计算机，所述内存条10可以连接电容11和CPU12，所述电容11用于在断电时向所述内存条10供电，例如，当异常断电时，所述电容11可以供电所述内存条10工作一段时间，工作时间视所述电容11的大小而定，在恢复电力时，所述电容11可以利用电源进行充电。
所述内存条10可以是一种非易失性内存(NVDIMM-N)。
如图2所示，所述内存条10包括控制芯片101、至少一个数据闪存芯片、至少两个内存颗粒和至少一个非易失性存储器106，其中，每个数据闪存芯片连接至少两个内存颗粒和连接至少一个非易失性存储器106，所述控制芯片101连接所有数据闪存芯片和所有内存颗粒，例如，所述控制芯片101通过多路选择开关(multiplexer，MUX)108连接所有内存颗粒。
其中，所述控制芯片101可以称为主控制芯片，例如，可以为NVDIMM控制芯片。所述数据闪存芯片可以称为数据芯片，例如，可以为NVIDMM数 据闪存芯片。
例如，如图3所示，为本申请另一个实施例的另一种内存条的结构示意图，所述至少一个数据闪存芯片包括第一数据闪存芯片102和第二数据闪存芯片103，所述第一数据闪存芯片102连接四个内存颗粒104，所述第二数据闪存芯片103连接四个内存颗粒105。
在本申请的另一个实施例中，所述内存颗粒104、105可以为Memory颗粒或DDR颗粒或DRAM颗粒或SDRAM颗粒，本实例并不限定。
在本申请的另一实例中，所述非易失性存储器106可以称为Flash闪存，所述第一非易失性存储器106也可以为一个或多个，每个数据闪存芯片还连接至少一个所述第一非易失性存储器106。例如，如图3所示，所述第一数据闪存芯片102连接至少一个第一非易失性存储器106，所述第二数据闪存芯片103连接至少一个第二非易失性存储器107。
在本申请的另一实例中，每个非易失性存储器包括矩阵式的非易失性存储单元，例如2、4、8，n个非易失性存储单元，n为2的幂数。
在本申请的另一个实施例中，每个非易失性存储器的存储容量大于其连接的数据闪存芯片所连接的所有内存颗粒的存储容量，例如，每个非易失性存储器的存储容量为其连接的数据闪存芯片所连接的所有内存颗粒的存储容量1.5，2、3、4或5倍。
例如，当所述内存条10只有一个非易失性存储器106，所述第一非易失性存储器106存储容量大于所有内存颗粒的存储容量，例如，非易失性存储器106的存储容量是所有内存颗粒的存储容量1.5，2、3、4或5倍。当所述内存条10包括所述第一非易失性存储器106和第二非易失性存储器107，所述第一非易失性存储器106存储容量大于所述第一数据闪存芯片102所连接的所有内存颗粒的存储容量，所述第二非易失性存储器107存储容量大于所述第二数据闪存芯片103所连接的所有内存颗粒的存储容量，例如，第一 非易失性存储器106和所述第二非易失性存储器107的存储容量分别是其连接所有内存颗粒的存储容量1.5，2、3、4或5倍。
在本申请的另一个实施例中，所述控制芯片101通过串行并行(Serializer/Deserializer，SerDes)总线与所述每个数据闪存芯片连接，例如，所述控制芯片101通过SerDes总线分别与所述第一数据闪存芯片102和所述第二数据闪存芯片103连接。
所述控制芯片101，用于发送控制命令，例如，用于向每个数据闪存芯片发送控制命令和向每个内存颗粒发送数据处理控制命令，例如，所述控制命令包括DDR地址和/或时钟，数据备份命令或数据恢复命令，所述数据处理控制命令包括数据读取命令和数据写入命令。
所述每个数据闪存芯片，用于根据所述控制芯片101的控制命令，进行所述数据闪存芯片连接的内存颗粒和非易失性存储器之间的数据处理，例如，异常断电时，所述每个数据闪存芯片根据所述控制芯片101发布的数据备份命令将其连接的内存颗粒的数据备份到其连接的对应的非易失性存储器以实现数据备份处理，电力恢复时，根据所述控制芯片101发布的数据恢复命令将其连接的非易失性存储器的数据恢复到其连接的对应的内存颗粒以实现数据恢复处理。
例如，所述控制芯片101用于当异常断电时通过所述多路选择开关108向其连接的内存颗粒发送数据读取命令(例如，DDR读取命令)，以便该内存颗粒将其数据发送到数据信号线上，以便连接该数据颗粒的数据闪存芯片从该数据信号线上读取数据并写入到该数据闪存芯片连接的非易失性存储器中。
所述控制芯片101用于当电力恢复时通过所述多路选择开关108向其连接的内存颗粒发送数据写入命令(例如，DDR写入命令)，当数据闪存芯片将其连接的非易失性存储器中的数据发送到数据信号线上时，该内存颗粒 根据数据写入命令从该数据信号线上读取数据并写入其内部。
因此，上述实施例描述的内存条，将数据信号和控制信号分开由两个芯片管理：控制芯片负责输出控制信号，数据闪存芯片负责数据处理，则非易失性存储器与内存颗粒的数据信号不再通过控制芯片传输，这大大减少内存颗粒到控制芯片的连线，也减小了控制芯片尺寸，从而给内存颗粒更多的面积，也改善了在中央位置的布线拥挤，信号传输速度也提高。
而且，上述内存条还可以根据内存颗粒的摆放位置，选择数据闪存芯片和它所接的闪存颗粒的位置。这样可以把靠近双列直插式存储模块(Dual-Inline-Memory-Modules，DIMM)槽的位置留给内存颗粒，数据闪存芯片和它所接的闪存颗粒可以放在远离DIMM槽的地方。这样，内存颗粒可以有更大的面积，可以放两行，从而也增大了内存条的容量。
数据闪存芯片和控制芯片总线采用SerDes，从而速度更快，信号的数量也少并且具有扩展性。
本实施例的内存条可以采用流控技术，达到高带宽，低延迟，从而减少对超级电容的容量要求。
本实施例的内存条中，每个数据闪存芯片接多个闪存颗粒，达到更高的带宽，速度更快，从而减少对超级电容的容量要求。
在本申请的另一个实施例中，内存条10的初始化过程可以如下所述。
数据闪存芯片和控制芯片101处在复位状态。
数据闪存芯片和控制芯片101离开复位状态，开始自初始化，设置控制参数，模拟和I/O初始化在准备状态。
控制芯片101被设置成写入训练状态：控制芯片101先通过控制芯片101和数据闪存芯片之间的总线通知数据闪存芯片写入训练，然后主机(HOST)侧的DDR控制器驱动DDR控制信号发出写入命令给控制芯片101， 然后控制芯片101通知数据闪存芯片准备接受数据以及向内存颗粒发送DDR读取命令，内存颗粒根据DDR读取命令将其数据发送到DDR数据线上，数据闪存芯片从所述DDR数据线上截取数据并写入对应的非易失性存储器。
下一步控制芯片101被HOST设置成读取训练状态：控制芯片101先通过控制芯片101和数据闪存芯片之间的总线通知数据闪存芯片读取训练。数据闪存芯片收到控制芯片101的训练命令后，从非易失性存储器读取数据并发送到DDR数据线上，内存颗粒根据控制芯片101发出的DDR写入命令从DDR数据线上读取数据并写入其内部。
最后一步，Host端读取DDR内存数据来确认。
然后重复这过程，次数预先设定。期间，数据闪存芯片要设定不同的内部参数。HOST获得数据后，进行比较，最后设定控制芯片101最优数据参数，控制芯片101再通过内部总线告知数据闪存芯片。
当内存条异常断电时，数据断电时的备份过程可以如下所述。
所述控制芯片101，用于接收所述内存条10连接的设备硬件发送的异常断电通知，根据所述异常断电通知确定异常断电。例如，所述控制芯片101，用于接收CPU12的硬件发送的异常断电通知，根据该异常断电通知可以确定当前异常断电，则所述内存条10需要由所述电容11供电。
所述控制芯片101，用于当异常断电时，在所述电容11的供电下，向所述每个数据闪存芯片发送读取各自连接的内存颗粒的做数据备份命令。例如，所述控制芯片101向所述第一数据闪存芯片102发送读取所述第一数据闪存芯片102连接的内存颗粒104的数据备份命令；所述控制芯片101向所述第二数据闪存芯片103发送读取所述第二数据闪存芯片103连接的内存颗粒105的数据备份命令。
在本申请的另一实例中，所述控制芯片101根据所有内存颗粒的数量 和性能和所述数据闪存芯片的数量和处理能力确定流控速率，例如，所述内存颗粒的性能包括读/写数据的速率的最小值和最大值，所述数据闪存芯片的处理能力包括处理命令或数据的速率的最小值和最大值，所述流控速率包括控制芯片发送控制命令的速率和/或数据闪存芯片处理命令和/或数据的速率。
每个数据闪存芯片，用于当异常断电时，在所述电容11的供电下，根据所述数据备份命令从其连接的内存颗粒读取数据并写入到其连接的所述至少一个非易失性存储器。例如，对于图2的内存条，所述第一数据闪存芯片102用于当异常断电时，在所述电容11的供电下，根据所述数据备份命令从其连接的内存颗粒104读取数据并写入到其连接的所述第一非易失性存储器106中，所述第二数据闪存芯片103用于当异常断电时，在所述电容11的供电下，根据所述数据备份命令从其连接的内存颗粒105读取数据并写入到其连接的所述第一非易失性存储器106中。对于图3的内存条，所述第二数据闪存芯片103用于当异常断电时，在所述电容11的供电下，根据所述数据备份命令从其连接的内存颗粒105读取数据并写入到所述非易失性存储器107。
例如，当异常断电时，所述控制芯片101发送数据备份命令给每个数据闪存芯片(例如所述第一数据闪存芯片102和所述第二数据闪存芯片103)，每个数据闪存芯片确认其连接的非易失性存储器是否可以存储数据，例如，每个数据闪存芯片判断其连接的非易失性存储器是否故障，当该非易失性存储器未故障时，确定该非易失性存储器可以存储数据，或者，每个数据闪存芯片判断其连接的非易失性存储器的剩余容量是否大于等于阈值，当大于等于阈值时，确定该非易失性存储器可以存储数据。当数据闪存芯片确认其连接的非易失性存储器可以存储数据时，向所述控制芯片101发送备份准备完成消息，然后所述控制芯片101发送DDR读取命令给所述数据闪存芯片连接的内存颗粒，该内存颗粒将其数据发送到数据信号线上，然后所述数据闪存芯片从所述数据信号线上截取该内存颗粒的数据，并写到所述数据闪存芯片 连接的且可以存储数据的非易失性存储器上。
例如，以所述第一数据闪存芯片102为例，当异常断电时，所述控制芯片101发送数据备份命令给所述第一数据闪存芯片102，所述第一数据闪存芯片102确认其连接的非易失性存储器106是否可以存储数据，例如，所述第一数据闪存芯片102判断其连接的非易失性存储器106是否故障，当该非易失性存储器106未故障时，确定该非易失性存储器106可以存储数据，或者，所述第一数据闪存芯片102判断其连接的非易失性存储器106的剩余容量是否大于等于阈值，当大于等于阈值时，确定该非易失性存储器106可以存储数据。当所述第一数据闪存芯片102确认其连接的非易失性存储器106可以存储数据时，向所述控制芯片101发送备份准备完成消息，然后所述控制芯片101通过所述多路选择开关108发送DDR读取命令给所述第一数据闪存芯片102连接的内存颗粒104，该内存颗粒104将其数据发送到数据信号线上，然后所述第一数据闪存芯片102从所述数据信号线上截取该内存颗粒104的数据，并写到所述第一数据闪存芯片102连接的且可以接受数据的非易失性存储器106上。
例如，控制芯片101进一步包括发送单元和命令队列处理单元，所述发送单元用于以一定的顺序发出写入命令到命令队列；所述命令队列处理单元用于根据所述写入命令产生闪存写入命令，并通过内部总线(例如，SerDes总线)将所述闪存写入命令发到每个数据闪存芯片，其中，所述闪存写入命令用于指示进行数据备份。
每个数据闪存芯片包括相互连接的接收单元、发送单元、数据抓取单元、存储单元和闪存控制器。
数据闪存芯片的接收单元用于收到所述闪存写入命令后，将所述闪存写入命令放到其命令队列中；数据闪存芯片的发送单元用于通过内部总线向所述控制芯片101回复准备完成确定信息，所述准备完成确定信息用于指示 数据闪存芯片已经准备完成，可以执行后续操作。
所述控制芯片101用于在收到准备完成确定信息后，向数据闪存芯片发送数据备份命令和向所述数据闪存芯片连接的内存颗粒发送DDR读取命令。
所述内存颗粒根据所述DDR读取命令将其数据发送的数据信号线上。
所述接收单元还用于接收所述数据备份命令；所述数据抓取单元用于根据数据备份命令从数据闪存芯片连接的内存颗粒抓取数据，即从所述数据信号线上抓取数据，并放入于存储单元中；所述存储单元用于存储所抓取的数据，并将所抓取的数据发给所述闪存控制器；所述发送单元还用于向所述控制芯片101发送抓取完成命令；所述闪存控制器用于将所抓取的数据写入到所述数据闪存芯片连接的非易失性存储器，例如，所述非易失性存储器为闪存。
在本申请的另一实例中，每个内存颗粒的数据存储到非易失性存储器的位置是对应的。例如，数据闪存芯片将其连接的每个内存颗粒的数据存储到每个内存颗粒在所述非易失性存储器的固定位置，例如，有1、2、3、…、k个内存颗粒，非易失性存储器的存储位置有232位，每个内存颗粒在非易失性存储器有对应的存储位置，具体物理地址是个映射表管理的，不再赘述。
在本申请的另一实例中，每个内存颗粒的数据存储到非易失性存储器的位置是根据每个内存颗粒的地址或数据闪存芯片的PIN脚的序列号进行区分，例如，所述第一数据闪存芯片102分别连接4个内存颗粒104，所述第一数据闪存芯片102将每个内存颗粒104的数据存储到非易失性存储器106时，存储位置与该内存颗粒连接的所述第一数据闪存芯片102的PIN脚的序列号对应。
当恢复电力时，Host下命令给所述控制芯片101，所述控制芯片101向所述每个数据闪存芯片发送数据恢复命令和向内存颗粒发送DDR写入命 令。例如，所述控制芯片101用于分别向所述第一数据闪存芯片102和所述第二数据闪存芯片103发送数据恢复命令，以及向所述第一数据闪存芯片102连接的内存颗粒104和所述第二数据闪存芯片103连接的内存颗粒105发送DDR写入命令。
所述每个数据闪存芯片，还用于在恢复电力的情况下根据所述数据恢复命令从其连接的至少一个非易失性存储器读取数据并将读取的数据写入其连接的内存颗粒。
例如，对于图2的内存条，所述第一数据闪存芯片102用于在恢复电力的情况下根据所述数据恢复命令从所述第一非易失性存储器106读取数据并将读取的数据写入其连接的内存颗粒104；所述第二数据闪存芯片103用于在恢复电力的情况下根据所述数据恢复命令从所述第一非易失性存储器106读取数据并将读取的数据写入其连接的内存颗粒105。对于图3的内存条，所述第一数据闪存芯片102用于在恢复电力的情况下根据所述数据恢复命令从所述第一非易失性存储器106读取数据并将读取的数据写入其连接的内存颗粒104；所述第二数据闪存芯片103用于在恢复电力的情况下根据所述数据恢复命令从所述第二非易失性存储器107读取数据并将读取的数据写入其连接的内存颗粒105。
所述控制芯片101的所述发送模块通过内部总线向每个数据闪存芯片发送闪存读取命令，所述闪存读取命令用于指示进行数据恢复。
数据闪存芯片的接收单元用于在收到所述闪存读取命令后，将所述闪存读取命令放入其命令队列，并发所述命令队列。
数据闪存芯片的闪存控制器根据所述闪存读取命令确定其连接的非易失性存储器是否准备完数据恢复，例如，确定所述非易失性存储器是否故障，如果没有故障，确定所述非易失性存储器准备完数据恢复，例如，所述非易失性存储器可以为闪存。
所述数据闪存芯片确定其连接的非易失性存储器已准备完数据恢复时，向控制芯片101发送指示数据恢复准备完成消息的指示信息。
所述控制芯片101收到所述指示信息后，通过多路选择开关108向所述数据闪存芯片连接的内存颗粒发送DDR写入命令。
所述数据闪存芯片根据所述数据恢复命令从其连接的非易失性存储器获取数据并发送到数据信号线上。
所述数据闪存芯片连接的所述内存颗粒根据DDR写入命令从所述数据信号线上获取数据并写入其内部，例如，所述内存颗粒将获取的数据写入到其内部存储单元。
所述数据闪存芯片向所述控制芯片101发送数据恢复完成命令。
由于每个内存颗粒在非易失性存储器存储的位置是对应的，例如固定的，所以，在恢复电力时，数据闪存芯片能将非易失性存储器存储的数据写入到发生断电异常时对应的内存颗粒，即内存颗粒的数据得以恢复。
因此，上述实施例描述的内存条，每个内存颗粒不再都连接到一个控制芯片，而是通过控制芯片和数据闪存芯片将命令和数据分开，所以可以大大减少内存颗粒到控制芯片的连线，也减小了控制芯片芯片尺寸，从而给内存颗粒更多的面积，也改善了在中央位置的布线拥挤，信号质量也提高。因此，该内存条的容量可以大大提高，且信号传输速率不受连线长短的影响。
如图4所示，为本申请另一实例的一种内存条的结构示意图，所述内存条30可以连接电容31和CPU32，所述电容31用于在断电时向所述内存条30供电，例如，当异常断电时，所述电容31可以供电所述内存条30工作一段时间，工作时间视所述电容31的大小而定，在恢复电力时，所述电容31可以利用电源进行充电。
所述内存条30可以是一种非易失性内存(NVDIMM-N)。
所述内存条30包括一个控制芯片301、至少两个数据闪存芯片、至少一个多路选择开关(multiplexer，MUX)306、至少两个内存颗粒和至少两个非易失性存储器，其中，每个数据闪存芯片通过数据链路连接至少两个内存颗粒和连接至少一个非易失性存储器，所述控制芯片301与所述每个数据闪存芯片连接，例如，所述控制芯片301通过SerDes总线与所述每个数据闪存芯片连接，所述控制芯片301还通过所述多路选择开关306连接所有内存颗粒。
例如，所述至少两个数据闪存芯片包括：第一数据闪存芯片302、第二数据闪存芯片303、第三数据闪存芯片304和第四数据闪存芯片305，所述非易失性存储器为多个Flash。
所述控制芯片301通过SerDes总线分别与所述第一数据闪存芯片302、所述第二数据闪存芯片303、所述第三数据闪存芯片304和所述第四数据闪存芯片305连接。所述控制芯片301还包括控制PIN脚，所述控制芯片301通过该控制PIN脚与所述多路选择开关306连接，所述多路选择开关306分别连接每个内存颗粒，例如，所述多路选择开关306连接多个内存颗粒。
所述第一数据闪存芯片302、所述第二数据闪存芯片303和所述第三数据闪存芯片304均分别连接至少两个内存颗粒和连接至少一个的Flash，所述第四数据闪存芯片305连接至少两个内存颗粒和连接至少一个的Flash。
每个MUX连接至少两个内存颗粒，所述控制芯片301通过MUX与内存颗粒连接，每个MUX连接的内存颗粒数量可以预先设定。
在本申请的另一实例中，所述内存颗粒可以为RDIMM颗粒或SDRAM颗粒，本实例并不限定。
在本申请的另一实例中，所述非易失性存储器可以称为Flash闪存，所述非易失性存储器也可以为一个或多个，每个数据闪存芯片连接至少一个所述非易失性存储器。在本申请的另一实例中，每个非易失性存储器包括矩阵 式的非易失性存储单元，例如2、、4、…、n个非易失性存储单元，n为大于等于2的幂数，例如n＝8。
在本申请的另一实例中，每个非易失性存储器的存储容量大于其连接的数据闪存芯片所连接的所有内存颗粒的存储容量，例如，每个非易失性存储器的存储容量为其连接的数据闪存芯片所连接的所有内存颗粒的存储容量1.5，2、3、4或5倍。
所述控制芯片301，用于接收所述内存条30连接的设备硬件发送的异常断电通知，根据所述异常断电通知确定异常断电。例如，所述控制芯片301，用于接收CPU32的硬件发送的异常断电通知，根据该异常断电通知可以确定当前异常断电，则所述内存条30需要由所述电容31供电。
所述控制芯片301，用于当异常断电时，在所述电容31的供电下，向所述每个数据闪存芯片发送读取其连接的内存颗粒的数据备份命令和向每个内存颗粒发送数据读取命令。例如，所述控制芯片301分别向所述第一数据闪存芯片302、所述第二数据闪存芯片303、所述第三数据闪存芯片304和所述第四数据闪存芯片305发送数据备份命令。在本申请的另一实例中，所述控制芯片301按照流控速率发送所述数据备份命令，例如，所述控制芯片301根据所有内存颗粒的数量和性能和所述数据闪存芯片的数量和处理能力确定流控速率。
每个内存颗粒，用于根据所述数据读取命令(例如，DDR读取命令)将其内部的数据发送到数据信号线上，例如，DDR数据线上。
每个数据闪存芯片，用于当异常断电时，在所述电容31的供电下，根据所述数据备份命令从其连接的内存颗粒读取数据并写入到其连接的所述至少一个非易失性存储器，即从数据信号线上截取数据并写入到其连接的所述至少一个非易失性存储器。例如，所述第一数据闪存芯片302、所述第二数据闪存芯片303和/或所述第三数据闪存芯片304用于当异常断电时，在所述 电容31的供电下，根据所述数据备份命令分别从数据信号线上截取其连接的至少两个内存颗粒的数据并写入到各自连接的至少两个Flash中。例如所述第四数据闪存芯片305用于当异常断电时，在所述电容31的供电下，根据所述数据备份命令从数据信号线上截取其连接的至少内存颗粒的数据并写入到所述第四数据闪存芯片305连接的至少一个Flash中。
在本申请的另一实例中，每个内存颗粒的数据存储到非易失性存储器的位置是对应的。例如，数据闪存芯片将其连接的每个内存颗粒的数据存储到每个内存颗粒在所述非易失性存储器的固定位置，例如，有1、2、3、…、k个内存颗粒，非易失性存储器的存储位置有232位，每个内存颗粒在非易失性存储器有对应的固定存储位置，例如，所述非易失性存储器的第1-32位存储位置用于存储第1个内存颗粒的数据，所述非易失性存储器的第33-64位存储位置用于存储第2个内存颗粒的数据，等等，不再赘述。
在本申请的另一实例中，数据闪存芯片将其连接的每个内存颗粒的数据存储到所述每个内存颗粒在所述非易失性存储器的写入数据序列的固定位置，例如所述非易失性存储器在写入数据时是采用数据序列写入，所述非易失性存储器的写入数据序列的第1-32位用于写入第1个内存颗粒的数据，所述非易失性存储器的写入数据序列的第33-64位用于写入第2个内存颗粒的数据，等等，不再赘述。
在本申请的另一实例中，每个内存颗粒的数据存储到非易失性存储器的位置是根据每个内存颗粒的地址或数据闪存芯片的序列号进行区分，例如，所述第一数据闪存芯片302连接4个内存颗粒304，所述第一数据闪存芯片302将每个内存颗粒304的数据存储到Flash时，存储位置与该内存颗粒连接的所述第一数据闪存芯片302的连接序列号对应。
当恢复电力时，所述控制芯片301还用于向所述每个数据闪存芯片发送数据恢复命令和向内存颗粒发送数据写入命令(例如，DDR写入命令)。 例如，所述控制芯片301用于分别向所述第一数据闪存芯片302、所述第二数据闪存芯片303、所述第三数据闪存芯片304和所述第四数据闪存芯片305发送数据恢复命令。
所述每个数据闪存芯片，还用于在恢复电力的情况下根据所述数据恢复命令从其连接的至少一个非易失性存储器读取数据并将读取的数据发送到数据信号线上，内存颗粒根据所述数据写入命令从数据信号线上读取数据并写入其内部。例如，所述第一数据闪存芯片302、所述第二数据闪存芯片303和/或所述第三数据闪存芯片304用于当恢复电力时，根据所述数据恢复命令分别从各自连接的至少两个Flash读取数据并发送到数据信号线上，各自连接的内存颗粒根据所述数据写入命令从数据信号线上读取数据并写入其内部。例如所述第四数据闪存芯片305用于恢复电力时，根据所述数据恢复命令从其连接的至少一个Flash读取数据并发送到数据信号线上，所述第四数据闪存芯片305连接的内存颗粒根据所述数据写入命令从数据信号线上读取数据并写入其内部。
由于每个内存颗粒在非易失性存储器存储(例如Flash)的映射位置是对应的，例如固定的，所以，在恢复电力时，数据闪存芯片能将非易失性存储器存储的数据写入到发生断电异常时对应的内存颗粒，即内存颗粒的数据得以恢复。
因此，上述实施例描述的内存条，每个内存颗粒不再都连接到一个控制芯片，而是通过数据闪存芯片进行分担，所以可以大大减少内存颗粒到控制芯片的连线，也减小了控制芯片芯片尺寸，从而给内存颗粒更多的面积，也改善了在中央位置的布线拥挤，信号质量也提高。因此，该内存条的容量可以大大提高，且信号传输速率不受连线长短的影响。
进一步，数据信号和控制信号分开由两个芯片管理：控制芯片负责输出控制命令，例如DDR命令、地址、时钟等DDR信号。数据闪存芯片负责 DDR数据，例如异常断电时截取数据，电力恢复时恢复数据，从而信号传输速度更快。
进一步，所述控制芯片和所述数据闪存芯片的通讯总线是SerDes，从而速度更快，信号的数量也少并且具有扩展性。
上述实施例中，采用流控技术，达到高带宽，低延迟，从而减少对电容的容量要求。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一 个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实例技术方案的精神和范围。

Claims (15)

  1. 一种内存条，其特征在于，包括：控制芯片、至少一个数据闪存芯片、至少两个内存颗粒和至少一个非易失性存储器颗粒，其中，每个数据闪存芯片连接至少一个内存颗粒和连接至少一个非易失性存储器颗粒，所述控制芯片分别连接所有数据闪存芯片和所有内存颗粒，所述内存条还连接至少一个电容；
    所述控制芯片，用于发送控制命令；
    所述每个数据闪存芯片，用于根据所述控制芯片的控制命令，进行各自连接的内存颗粒和非易失性存储器之间的数据处理。
  2. 如权利要求1所述的内存条，其特征在于，所述控制命令包括数据备份命令和数据读取命令，其中，
    所述控制芯片用于当异常断电时，在所述电容的供电下，向所述每个数据闪存芯片发送所述数据备份命令和向所述每个内存颗粒发送数据读取命令；
    每个内存颗粒，用于在所述电容的供电下，根据所述数据读取命令将其数据发送至数据信号线上；
    所述每个数据闪存芯片，用于在所述电容的供电下，根据所述数据备份命令从所述数据信号线上获取其连接的内存颗粒发送的数据并写入到其连接的所述至少一个非易失性存储器。
  3. 如权利要求2所述的内存条，其特征在于，所述每个数据闪存芯片还用于在所述控制芯片发送所述数据读取命令之前，确认其连接的所述非易失性存储器是否能存储数据；当所述每个数据闪存芯片确认其连接的所述非易失性存储器能存储数据时，向所述控制芯片发送备份准备完成消息。
  4. 如权利要求1所述的内存条，其特征在于，所述控制命令包括数据恢 复命令和数据写入命令，其中，
    所述控制芯片，用于当恢复电力时，向所述每个数据闪存芯片发送所述数据恢复命令和向所述每个内存颗粒发送所述数据写入命令；
    所述每个数据闪存芯片，还用于在恢复电力的情况下根据所述数据恢复命令从其连接的至少一个非易失性存储器读取数据并将读取的数据发送到数据信号线上；
    所述每个内存颗粒，用于在恢复电力的情况下根据所述数据写入命令从所述数据信号线上获取其连接的数据闪存芯片发送的数据并写入其内部。
  5. 如权利要求1所述的内存条，其特征在于，所述每个数据闪存芯片，还用于在所述控制芯片向所述每个内存颗粒发送所述数据写入命令之前，确定其连接的所述非易失性存储器是否已准备完数据恢复，如果所述非易失性存储器已准备完数据恢复，向所述控制芯片发送数据恢复准备完成消息。
  6. 如权利要求1所述的内存条，其特征在于，所述控制芯片包括至少一个控制PIN脚，所述内存条还包括至少一个多路选择开关，所述至少一个控制芯片PIN脚通过所述至少一个多路选择开关与所述所有内存颗粒连接。
  7. 如权利要求1-6任意一项所述的内存条，其特征在于，所述每个内存颗粒的数据存储到所述至少一个非易失性存储器的位置是对应的；或，所述每个内存颗粒的数据存储到所述至少一个非易失性存储器的数据序列的固定位置。
  8. 如权利要求1-6任意一项所述的内存条，其特征在于，所述控制芯片还用于根据所有内存颗粒的数量和性能和所述数据闪存芯片的数量和处理能力确定流控速率。
  9. 如权利要求1-6任意一项所述的内存条，其特征在于，每个非易失性存储器的存储容量大于其连接的数据闪存芯片所连接的所有内存颗粒的存储 容量。
  10. 如权利要求1-6任意一项所述的内存条，其特征在于，所述控制芯片通过串并SerDes总线与所述每个数据闪存芯片连接。
  11. 如权利要求2所述的内存条，其特征在于，所述控制芯片101还用于接收CPU的硬件发送的异常断电通知，根据该异常断电通知确定当前异常断电。
  12. 如权利要求3所述的内存条，其特征在于，每个数据闪存芯片还用于判断其连接的非易失性存储器是否故障，当该非易失性存储器未故障时，确定该非易失性存储器能存储数据；或者，每个数据闪存芯片还用于判断其连接的非易失性存储器的剩余容量是否大于等于阈值，当大于等于阈值时，确定该非易失性存储器能存储数据。
  13. 如权利要求9所述的内存条，其特征在于，每个所述非易失性存储器的存储容量为其连接的数据闪存芯片所连接的所有内存颗粒的存储容量1.5，2、3、4或5倍。
  14. 一种计算机，包括如权利要求1-13任意一项的内存条。
  15. 一种服务器，包括如权利要求1-13任意一项的内存条。
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