WO2021253548A1 - 像素设计方法、像素设计装置及电子设备 - Google Patents

像素设计方法、像素设计装置及电子设备 Download PDF

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WO2021253548A1
WO2021253548A1 PCT/CN2020/101839 CN2020101839W WO2021253548A1 WO 2021253548 A1 WO2021253548 A1 WO 2021253548A1 CN 2020101839 W CN2020101839 W CN 2020101839W WO 2021253548 A1 WO2021253548 A1 WO 2021253548A1
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design
pixel
pattern
tft
display panel
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PCT/CN2020/101839
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English (en)
French (fr)
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刘洋
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/968,388 priority Critical patent/US11880641B2/en
Publication of WO2021253548A1 publication Critical patent/WO2021253548A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • This application relates to the field of display technology, in particular to a pixel design method, device and electronic equipment.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Display
  • the comparison analysis is mainly based on the existing product library, generally referring to the company's products of the same size or the same resolution or the same pixel size, and combining similar products in the market to formulate various specifications for new products Value, through manual design of pixel drawings, optical and electrical simulations, etc., repeated comparisons with the pixel design of mass-produced products, check the relevant specifications of the pixel design, and finally obtain a design drawing file that meets the product specifications.
  • the prior art pixel design mainly stays in the manual design, inspection, and iterative stages. It mainly relies on manpower to use design tools to design drawings step by step. It requires a lot of man-hours and requires repeated inspections. At the same time, there is a risk of missed inspections due to various design specifications. Many, strong dependence on design experience, easy for novices to make mistakes, need to manually calculate various design parameters, and the number of pixel design iterations is also large, which causes the design process to be extremely cumbersome/time-consuming, and the design phase takes a long time, which is not conducive to product launch .
  • the embodiments of the application provide a pixel design method, device and electronic equipment, which can intelligently perform pixel design drawing during the user’s pixel design process, reducing the dependence on the designer’s design experience, eliminating the need for the designer to manually calculate design parameters, and shortening the product Design time and evaluation time, quickly produce product pixel designs that meet the needs, improve research and development efficiency, and save human resources and costs.
  • the present application provides a pixel design method, the method includes:
  • the pixel design strategy information includes design transmittance information of the display panel
  • a pixel design drawing of a single pixel in the display panel is drawn.
  • the present application provides a pixel design device, the device includes:
  • the first obtaining module is used to obtain the design size information of the display panel configured by the user and the design resolution information of the display panel;
  • a calculation module for calculating the size of a single pixel of the display panel based on the design size information of the display panel and the design resolution information of the display panel;
  • the second acquisition module is configured to acquire preset pixel design strategy information, where the pixel design strategy information includes design transmittance information of the display panel;
  • the drawing module is used to draw a pixel design drawing of a single pixel in the display panel based on the size of a single pixel of the display panel and the pixel design strategy information.
  • the present application provides an electronic device, the electronic device includes: one or more processors;
  • One or more application programs wherein the one or more application programs are stored in the memory and configured to be executed by the processor to implement the pixel design method.
  • This application can calculate the size of a single pixel of the display panel based on the design size information of the display panel and the design resolution information of the display panel configured by the user in the pixel design stage of the display panel, based on the size and preset of the single pixel of the display panel
  • the pixel design strategy information of the display panel is drawn, and the pixel design drawing of a single pixel in the display panel is drawn.
  • the embodiment of this application is based on the design size information of the display panel configured by the user, the design resolution information of the display panel, and the preset pixel strategy information.
  • the user intelligently performs the pixel design drawing of a single pixel, reducing the dependence on the designer’s design experience, eliminating the need for the designer to manually calculate the design parameters, shortening the product design time and evaluation time, and quickly producing product pixel designs that meet the needs , Improve research and development efficiency, save human resources and costs.
  • FIG. 1 is a schematic flowchart of an embodiment of a pixel design method provided by an embodiment of the present application
  • FIG. 2 is a schematic flowchart of an embodiment of step 104 provided in an embodiment of the present application
  • FIG. 3 is a schematic diagram of the structure of a reference pattern of a single pixel size in an embodiment of the present application
  • FIG. 4 is a schematic flowchart of an embodiment of step 202 provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the structure of a pixel data line pattern in an embodiment of the present application
  • FIG. 6 is a schematic flowchart of an embodiment of drawing a TFT pattern in each pixel of a display panel in an embodiment of the present application
  • FIG. 7 is a schematic structural diagram of a storage capacitor pattern in a source and drain metal layer in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an embodiment of drawing related design patterns of TFT patterns in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the structure of the gate pattern in the gate metal layer in the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a common electrode pattern in a gate metal layer in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the structure of the shielding metal pattern in the embodiment of the present application.
  • FIG. 12 is a schematic diagram of the comparison of some parameters of the pixel structure of a new product and a benchmark product in an embodiment of the present application;
  • FIG. 13 is a schematic flowchart of an embodiment of a pixel design device provided by an embodiment of the present application.
  • FIG. 14 is a schematic flowchart of an embodiment of an electronic device provided by an embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, "a plurality of" means two or more than two, unless otherwise specifically defined.
  • the embodiments of the present application provide a pixel design method, device, and electronic equipment, which will be described in detail below.
  • the pixel design method in the embodiment of the present application is introduced, and the pixel design method is executed in an electronic device.
  • the electronic device may be a desktop terminal or a mobile terminal, and the electronic device may also be a mobile phone, a tablet computer, a notebook computer, and the like.
  • FIG. 1 it is a schematic diagram of an embodiment of a pixel design method in an embodiment of the application, and the method includes:
  • the design size information of the display panel to be designed and the design resolution of the display panel can be configured in advance.
  • the user configuration here can be user input. For example, when the user enters the program corresponding to the pixel design method, clicks the preset design menu or automatically pops up the input interface of the design size information of the display panel and the design resolution of the display panel. After the user inputs the relevant parameters, the acquisition is obtained. The design size information of the display panel and the design resolution information of the display panel configured by the user.
  • the design size of the display panel corresponding to the current pixel design is 55'UHD (Ultra High Definition)
  • the diagonal length of the effective display area is 138731.517152um
  • the design resolution of the display panel is 2160*3840.
  • the design size information of the display panel includes the diagonal length of the effective display area of the display panel, for example, the effective display of 55' UHD
  • the diagonal of the area is 138731.517152um long.
  • the calculation of the size of a single pixel of the display panel based on the design size of the display panel and the design resolution of the display panel may include: obtaining the aspect ratio of the display panel; according to the triangular Pythagorean theorem, according to the The aspect ratio of the display panel, the diagonal length of the effective display area in the display panel, calculate the length and width of the effective display area in the display panel; according to the length and width of the effective display area in the display panel, and the According to the design resolution information of the display panel, the size of a single pixel in the display panel is calculated respectively.
  • the aspect ratio (Style) of the display panel is generally fixed, such as 16:9, and individual design changes, such as 21:9, can obtain the aspect ratio of the display panel input by the user.
  • the following describes how to calculate the size of a single pixel of the display panel based on the design size of the display panel and the design resolution information of the display panel in conjunction with specific examples.
  • the design size of the display panel Size (diagonal length, unit: inch); the aspect ratio of the display panel: Style; the design resolution of the display panel: Reso (Resolution); the size of a single pixel: pixel length (A), pixel Wide (B)
  • the size of a single pixel can be obtained by dividing the value of the resolution respectively.
  • 55'UHD (diagonal 138731.517152um) aspect ratio 16:9 according to the triangle Pythagorean theorem, the length and width of the effective display area are 1209600um and 680400um respectively, and the design resolution is 2160*3840.
  • the size of a single pixel The calculation method can be as follows:
  • the pixel design strategy information of the display panel preset in the embodiment of the application is the preset pixel design specification or pixel design specification of the display panel, so that the designer can automatically based on the pixel data of the display panel configured by the user when designing Pixel design strategy information draws a pixel design drawing.
  • drawing a pixel design drawing of a single pixel in the display panel may be: based on the size of a single pixel of the display panel and the pixel design strategy Information, in a preset drawing space, draw a pixel design drawing of a single pixel in the display panel, where the preset drawing space may be the initial design space of the design program or design plug-in corresponding to the pixel design method, such as subsequent implementation
  • EDA Electronics Design Automation
  • each processing object exists in the form of data or information, such as pixel design strategy, which is essentially pixel design strategy information (for example, various subsequent forms in the form of a pixel).
  • Pixel strategy for example, the size of a single pixel of a display panel is essentially the size information of a single pixel of the display panel.
  • the line width, size, number, position, etc. mentioned in the subsequent embodiments are all corresponding data. In order to be processed by the electronic device, the details are not repeated here.
  • the embodiment of the present application may calculate the size of a single pixel of the display panel based on the design size information of the display panel and the design resolution information of the display panel configured by the user in the pixel design stage of the display panel, and calculate the size of a single pixel of the display panel and
  • the preset pixel design strategy information is to draw a pixel design drawing of a single pixel in the display panel.
  • the embodiment of the present application is based on the design size information of the display panel, the design resolution information of the display panel and the preset pixel strategy information configured by the user.
  • the pixel design drawing can be done intelligently during the user’s pixel design process, reducing the designer’s design experience dependence, eliminating the need for the designer to manually calculate design parameters, shortening product design time and evaluation time, and quickly producing product pixel designs that meet the needs. Improve research and development efficiency, save human resources and costs.
  • the execution flow of the pixel design method can be loaded into the display panel design program in the form of a plug-in, or it can be a pixel intelligent design program independent of the display panel design program, as long as it can be installed on the display panel.
  • the design program the design parameters of the display panel corresponding to the user's current design operation can be collected, and the details are not limited here.
  • the display panel design program may be an existing Electronic Design Automation (EDA) program for display panel design, such as Protel, Altium Designer, PSPICE, OrCAD, etc.
  • EDA Electronic Design Automation
  • the pixel design strategy information includes design transmittance information of the display panel.
  • the design transmittance can be configured by user input. Since the new product transmittance has many influencing factors, it is more complicated and specific.
  • the design transmittance can be predetermined by the user based on the same type of products, for example, the same display can be used.
  • the transmittance of the panel size is used as the design transmittance of the current display panel.
  • the design aperture rate of the pixel design of the current display panel can be determined.
  • the design transmittance is fixed, and a product B is used as an analogy.
  • the design aperture ratio of the pixel design of the display panel is determined, and it can be used to draw the pixel design drawing of a single pixel in the display panel later.
  • the display panels in the embodiments of the present application may be various types of display panels, such as liquid crystal display (LCD) panels, organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panels, etc., specifically , Such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and so on.
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the pixel The design strategy information may include the first design strategy information of the pixel-related structure in the array substrate and the second design strategy information of the pixel-related structure in the color filter substrate.
  • the step 104 is based on the The size of a single pixel of the display panel and the pixel design strategy information, drawing a pixel design drawing of a single pixel in the display panel may include steps 201 to 203, which are specifically as follows:
  • a reference pattern of a single pixel can be drawn with the size of a single pixel, and each layer of subsequent pixel design can be based on this reference pattern.
  • a reference pattern drawn with a single pixel size pixel length (A), pixel width (B).
  • the related structure pattern of the array substrate in the single pixel and the related structure pattern of the color filter substrate in the single pixel can be drawn respectively.
  • the array substrate may be a TFT array substrate
  • the first design strategy information includes TFT design strategy information of the display panel
  • the related structure pattern of the array substrate includes the related design pattern of the TFT pattern
  • the drawing of the related structure pattern of the array substrate in a single pixel based on the first design strategy information in step 202 may further include steps 401 to 403, which are specifically as follows:
  • the line width of the pixel data line and the distance between the pixel data line and the pixel (pixel) input by the user can be obtained, based on the line width of the pixel data line and the pixel between the pixel data line and the pixel Distance, the pixel data line pattern can be generated in the reference pattern, as shown in FIG. 5, C is the drawn Data line pattern.
  • the length and width parameters of the TFT in the display panel input by the user that is, the L value and W value of the TFT can be obtained.
  • drawing the relevant design pattern of the TFT pattern based on the length and width parameters of the TFT and the TFT design strategy information may further include the following steps (1) to (4):
  • the length and width parameters of the TFT are the channel length and channel width parameters of the TFT.
  • the drawing a TFT pattern in each pixel of the display panel based on the length and width parameters of the TFT and the TFT design strategy information may further include steps 601 to 603:
  • generating an initial TFT pattern that meets the length and width parameters of the TFT may be: calling a TFT pattern in a preset TFT pattern library, and generating based on the length and width parameters of the TFT The initial TFT pattern that meets the length and width parameters of the TFT. That is, because the shapes of the TFT patterns are basically similar, the main difference lies in the length and width parameters of the TFT. Based on the determined TFT length and width parameters, you can directly call the TFT patterns in the preset TFT pattern library to generate the length and width of the TFT. And the initial TFT pattern of the width parameter.
  • the TFT design strategy information includes the process parameter strategy information of the TFT, the design attribute strategy information of each layer of the TFT, and the design attribute strategy information between the layers of the TFT.
  • the process parameter strategy information of the TFT includes at least one of electron mobility requirements, cut-off current requirements, leakage current requirements, parasitic capacitance requirements, and TFT round corner design requirements, and the TFT design attribute strategy information for each layer includes each of the TFT At least one of layer material and thickness strategy information, and line width definition restriction strategy information of each layer.
  • the design attribute strategy information between each TFT layer includes the spacing strategy information between each TFT layer and the strategy information between each TFT layer. Alignment error limiting strategy information, etc.
  • the process parameters of the TFT include at least one of electron mobility parameters, cut-off current parameters, leakage current parameters, parasitic capacitance parameters, and TFT round corner design parameters.
  • the design attributes of each layer of the TFT include each layer in the TFT. At least one of the material and thickness parameters of each layer, and the line width parameters of each layer.
  • the design attributes between the layers of the TFT include the spacing parameters between the layers of the TFT and the alignment error limiting parameters between the layers of the TFT.
  • the following takes the TFT-LCD display panel as an example to introduce the design strategy information of the display panel.
  • TFT-LCD display panel For the TFT-LCD display panel, it contains a lot of professional knowledge, and naturally involves a lot of professional specifications. These professional specifications are not isolated from each other, and the display panel design is not a simple addition of all specifications. , But to coordinate with each other, clarify the design goals and positioning, in order to ensure the success of the final design of the product.
  • the TFT design strategy information may include material and thickness strategy information, line width definition restriction strategy information, alignment error restriction strategy information, and TFT process parameter strategy information.
  • the material and thickness strategy information may include the material and thickness information of at least one of the gate electrode, the gate insulating layer, the semiconductor layer, the doped semiconductor layer, the source/drain metal, and the transparent electrode,
  • the material and thickness strategy information may specifically include the content in Table 1 below. It is understandable that the material and thickness strategy information in Table 1 is only an example, and more or less material and thickness information may be included in actual applications, and the details are not limited here.
  • the line width definition restriction strategy information includes line width definition restriction information of at least one of a gate metal line, a semiconductor layer line, a source/drain metal line, a contact hole, and an ITO transparent electrode.
  • the line width definition restriction strategy information may specifically include the content in Table 2 below. It can be understood that the line width definition restriction strategy information in Table 2 is only an example, and more or less line width definition restriction information may be included in practical applications, and the specific restriction information is not limited here.
  • the alignment error limitation strategy information includes semiconductor layer and gate metal, source and drain metal and gate metal, source and drain metal and semiconductor layer, contact hole and gate metal, contact hole Alignment error limitation information with at least one of source and drain metals, transparent electrodes and source and drain metals, transparent electrodes and gate metals, transparent electrodes, and contact holes.
  • the alignment error restriction strategy information may specifically include the content in Table 3 below. It is understandable that the alignment error restriction strategy information in Table 3 is only an example, and more or less alignment error restriction information may be included in practical applications, which is not specifically limited here.
  • the process parameter strategy information of the TFT may include at least one process parameter of electron mobility, cut-off voltage, and leakage current parasitic capacitance.
  • the process parameter strategy information of the TFT may include the following Table 4 It can be understood that the process parameter strategy information of TFT in Table 4 is only an example, and more or less process parameters of TFT may be included in practical applications, and the specifics are not limited here.
  • the design concept adopted is "worst-case design", that is, it can be used under extreme conditions in the design, and then other situations no problem.
  • the frame frequency of the picture is 60-75 Hz
  • 75 Hz is used to consider the charging time
  • 60 Hz is used to consider the charge retention time.
  • the two extreme conditions can be met, it can certainly be met at other frequencies. Therefore, similar principles are also adopted in the embodiments of this application.
  • Tables 1 to 4 only a single value is listed, which means that the value in the single value is the worst-case design value, which is better than the design value.
  • the direction of TFT meets the design requirements.
  • the electron mobility of TFT in Table 4 the general value is the worst-case design value.
  • the higher the electron mobility of TFT it can indirectly help the display resolution. Therefore, the electron mobility is greater than the general value to meet the design specification.
  • Tables 1 to 4 are only examples of part of the strategy information in the TFT design strategy information. It is understandable that in addition to the TFT design strategy information mentioned above, in the embodiments of this application, it can also be based on The actual need to include any other more TFT design strategy information, such as the number of terminals, etc., will not be described in detail in the embodiment of this application. Any design strategy information based on design specifications can be adopted based on the inventive idea of this application, and will not be specifically described here. limited.
  • different display panel design strategy information can be set for different display panels, and in order to achieve the optimization of a certain characteristic of the display panel, the relevant display panel design strategy information can be set to change Many design parameters, such as the general value of the electron mobility of TFT in Table 4, are set to a larger electron mobility value to indirectly increase the display resolution and meet the design requirements for higher resolution of the display.
  • the two design values that are most closely related to all designs are the size of the storage capacitor and the channel width W of TFT.
  • Other designs are not unimportant, but will not change easily, such as the channel length of TFT. It is usually set at the minimum limit of the manufacturing capacity to obtain the maximum breaking current and the minimum gate load capacitance, such as the material and thickness of the gate insulating layer or the metal conductive layer.
  • the initial layout of the pixel can be performed.
  • the initial layout of the pixels can be drawn.
  • the layout method will be different for different people and different companies. For example, the same storage capacitor can be laid out in a U-shape, a straight-line shape, an H-shape, etc. surrounding the pixels, and the TFT will have different shapes with the same channel width. as the picture shows. Regardless of the change, the key parameters must be met, and the shape of the TFT or storage capacitor can often be adjusted for optical characteristics or process yield.
  • the drawing the storage capacitor pattern in the source-drain metal layer in each pixel area of the reference pattern based on the reference pattern and the TFT pattern includes: in each pixel area of the reference pattern When drawing the storage capacitor pattern in the source and drain metal layer in the, determine the upper edge of the storage capacitor pattern with the short side of the pixel in each pixel area as a reference; determine the outer edge of the left end of the storage capacitor pattern with the TFT pattern as a reference Along; with the pixel data line pattern as a reference, determine the right outer edge of the storage capacitor pattern; draw the storage capacitor pattern based on the upper outer edge, the left outer edge and the right outer edge of the storage capacitor pattern.
  • the drawing of the storage capacitor M2_Cst in the source and drain metal layer is drawn with reference to the TFT pattern and the pixel area. Specifically, as shown in FIG. 7:
  • the outer edge of the upper end of M2_Cst Refer to the distance L from the short side of the pixel area;
  • the outer edge of the left end of M2_Cst Refer to the distance M from the source and drain of the TFT pattern
  • the outer edge of the right end of M2_Cst Refer to the distance N from the pixel data line at the right end.
  • L, M, N can be preset and configured, which can be input by the user or automatically configured according to TFTs of different lengths and widths.
  • the drawing related design patterns of the TFT pattern based on the storage capacitor pattern and the pixel data line pattern, as shown in FIG. 8, may further include steps 801 to 804, which are specifically as follows:
  • the drawing the gate pattern in the gate metal layer of the TFT pattern based on the pixel data line pattern and the TFT design strategy information includes: determining the gate metal according to the pixel data line pattern Based on the TFT design strategy information, determine the value of the middle section of the gate in the gate metal layer; Based on the two ends of the gate in the gate metal layer and the gate Draw the gate pattern in the gate metal layer of the TFT pattern according to the value of the middle section of the gate in the polar metal layer.
  • the gate pattern M1-Gate in the gate metal layer is the gate pattern M1-Gate in the gate metal layer.
  • the alignment is drawn at the complementary value of the pixel data line, and the thickness is the same as the thickness P of the pixel data line;
  • Middle section value refer to the thickness of Q and R in the TFT pattern in Fig. 9 drawn.
  • P, Q, R are all preset size parameters.
  • the drawing the common electrode pattern in the gate metal layer of the TFT pattern based on the gate pattern in the gate metal layer and the storage capacitor pattern includes: determining the gate electrode based on the storage capacitor pattern The protruding position of the common electrode in the metal layer; based on the gate pattern in the gate metal layer, determine the horizontal position of the common electrode in the gate metal layer; based on the protruding position of the common electrode in the gate metal layer And horizontal position, drawing the common electrode pattern in the gate metal layer of the TFT pattern.
  • the common electrode patterns M1-Acom in the gate metal layer are shown in FIG. 10, the common electrode patterns M1-Acom in the gate metal layer:
  • T is a preset size parameter.
  • the pixel design strategy information includes the design line width of the vertical shielding metal, the design line width of the horizontal shielding metal, and the design line width of the intermediate shielding metal, based on the pixel data line pattern and the reference pattern
  • Drawing the shielding metal pattern in the gate metal layer of the TFT pattern includes: obtaining the design line width of the shielding metal in the vertical direction, the design line width of the shielding metal in the horizontal direction, and the design line width of the intermediate shielding metal in the pixel design strategy information; According to the design line width of the vertical shielding metal, the design line width of the horizontal shielding metal, and the design line width of the intermediate shielding metal, the TFT pattern gate metal layer is drawn with reference to the pixel data line pattern and the reference pattern The masking metal pattern in.
  • the shielding metal pattern M1-SM is drawn with reference to the data line pattern and the reference pattern, the line width of the mark position can be automatically selected whether to draw, and the width can be automatically adjusted.
  • V is the design line width of shielding metal (SM) in the vertical direction
  • X is the design line width of SM in the horizontal direction
  • W' is the design line width of the middle SM.
  • the pixel design strategy information includes the slit angle and the number of pixel partitions
  • the drawing of the ITO slit pattern in the display area includes: obtaining the slit angle and the number of pixel partitions in the pixel design strategy information; The slit angle and the number of pixel partitions are used to draw the ITO slit pattern in the display area.
  • the ITO slit in the display area including the selection of the slit angle and the number of domains), including the horizontal/vertical ITO trunk (ITO keel), whether it is a slit sealing design, and so on.
  • the current pixel design there are two mainstream types, one is 4-domain and the other is 8-domain.
  • the two pixel structures have their own advantages and disadvantages. Among them, the four-domain pixels It has a relatively high aperture ratio, but the viewing angle characteristics are much worse than that of the eight-zone pixels, and the eight-zone pixels have relatively better viewing angle characteristics.
  • different ITO slit patterns in the display area can be set in advance according to the slit angle and the number of pixel partitions. After the slit angle and the number of pixel partitions are determined, the slit angle and the number of pixel partitions can be determined according to the slit angle and the number of pixel partitions. , Automatically draw the ITO slit pattern in the display area.
  • the size of the glass substrate needs to be determined here.
  • some alignment marks are needed in the pixel design process. These marks are generally placed on the edge or corner of the glass. Therefore, if the size of the display area is 13 inches, consider the wiring and alignment marks outside the array. The size of the glass substrate should be More than 13 inches.
  • the above examples describe the specific implementation manners of drawing the relevant structural pattern of the array substrate in a single pixel based on the first design strategy information in the embodiment of the present application.
  • it further includes drawing a single pixel based on the second design strategy information.
  • the relevant structure pattern of the color filter substrate specifically, drawing the relevant structure pattern of the color filter substrate of a single pixel based on the second design strategy information may include:
  • the RGB color layer strategy information in advance to directly generate the corresponding RGB color layer pattern.
  • the preset value of shrinkage that is, the preset value of shrinkage of the outer edges of the four sides can be adjusted according to actual application scenarios.
  • the color resistance opening can refer to the distance from the edge of the pixel to the edge of the color resistance.
  • the PS size can refer to the preset PS size, and the distribution can refer to the preset CF open (color resist opening) and BM (Black Matrix, The relative distance of the black matrix).
  • PS size and distribution are determined according to the product, and generally refer to the PS size and distribution settings in similar size display panel products.
  • PS can be divided into Main PS and Sub PS. Which one to use can be determined according to the actual application scenario. After prompting the user to select, obtain the PS type to draw the PS of the corresponding type.
  • the pixel design strategy information may include the first design strategy information of the pixel-related structure in the array substrate and the second design strategy information of the pixel-related structure in the color filter substrate. It is understandable that the pixel The design strategy information may also include other additional structure design strategy information, such as a black matrix, etc., which can be automatically drawn with reference to the pre-black matrix strategy information.
  • an active area (AA) area of the entire display panel can be formed in an array.
  • input of the thickness of the liquid crystal cell, the materials of each layer in the array substrate, and the thickness parameters is specifically shown in FIG. 12, where cell gap is the thickness of the liquid crystal cell, and Tr% is the transmittance.
  • the method may further include an automatic inspection step.
  • the pixel design method further includes: Perform an overall inspection to determine whether the pixel design drawing complies with the pixel design strategy information; for drawing objects whose pixel design drawing does not meet the pixel design strategy information, based on the pixel design strategy information that the drawing object corresponds to The design strategy information of the drawing object is adjusted until it meets the design strategy information corresponding to the drawing object.
  • the simulation program SPICE, Simulation Program with Integrated Circuit Emphasis
  • the simulation program can also be called in the background to output different wrong charging voltages.
  • the charging rate data of the charging time, and output the feedthrough voltage (feeding voltage) at the same time.
  • manually determining whether it meets the requirements manually re-input the new adjusted pixel design parameters, update the pixel design strategy information, and redraw the new pixel design drawing.
  • the pixel design method may further include: performing a charging test on the pixel design drawing, outputting charging rate data with different charging voltages and charging times, and feeding voltage; if the charging rate data shows the charging rate If the charge uniformity is too low or the charging voltage is too large, the new pixel design parameter input by the user is obtained; based on the new pixel design parameter, the pixel design strategy information is adjusted to obtain the new pixel design strategy information; According to the new pixel design strategy information, a new pixel design drawing of the display panel is drawn.
  • the new pixel design parameter can be the associated design parameter corresponding to the problem. If the charging rate data shows that the charging rate is too low or the charging uniformity is poor, the new pixel design parameter is the associated design corresponding to the charging rate or the charging uniformity Parameters, if the feed-in voltage is too large, the new pixel design parameter is the associated design parameter of the feed-in voltage.
  • drawing the new pixel design drawing of the display panel can refer to the specific process of drawing the pixel design drawing of the display panel based on the pixel design strategy information in the above embodiment. I won't repeat it here.
  • the charging rate data can show that the charging rate is too low or the charging uniformity is poor, or the feeding voltage is too large, the user is prompted, and new pixel design parameters inputted by the user are obtained based on the new pixel design parameters.
  • Pixel design parameters, adjustment of pixel design strategy information, and adjustment of pixel design parameters for specific problems can draw a new pixel design drawing of the display panel faster without redrawing and adjusting, which improves research and development efficiency.
  • the pixel design method may further include: acquiring updated pixel design strategy information of the display panel, and the updated pixel design strategy information includes at least one structure of pixel design strategy information, or at least two Correspondence between pixel structures; based on the updated pixel design strategy information, update the pixel design strategy information of the display panel. Later, based on the updated pixel design strategy information of the display panel, a new pixel design drawing can be performed.
  • the pixel design device 1300 includes:
  • the first obtaining module 1301 is used to obtain the design size information of the display panel configured by the user and the design resolution information of the display panel;
  • the calculation module 1302 is configured to calculate the size of a single pixel of the display panel based on the design size information of the display panel and the design resolution information of the display panel;
  • the second obtaining module 1303 is configured to obtain preset pixel design strategy information, where the pixel design strategy information includes design transmittance information of the display panel;
  • the drawing module 1304 is configured to draw a pixel design drawing of a single pixel in the display panel based on the size of a single pixel of the display panel and the pixel design strategy information.
  • the embodiments of this application can intelligently perform pixel design drawing during the user’s pixel design process, reduce the designer’s design experience dependence, eliminate the need for the designer to manually calculate design parameters, shorten product design time and evaluation time, and quickly produce products that meet the needs
  • Product pixel design improves research and development efficiency, saves human resources and costs.
  • the design size information of the display panel includes the diagonal length of the effective display area of the display panel; the calculation module is specifically configured to:
  • the length and width of the effective display area of the display panel are calculated according to the aspect ratio of the display panel and the diagonal length of the effective display area of the display panel;
  • the size of a single pixel in the display panel is calculated respectively.
  • the display panel is a liquid crystal display panel
  • the pixel design strategy information includes the first design strategy information of the pixel-related structure in the array substrate and the second design strategy of the pixel-related structure in the color filter substrate information;
  • the drawing module is specifically used for:
  • the first design strategy information includes the TFT design strategy information of the display panel;
  • the related structure pattern of the array substrate includes the related design pattern of the TFT pattern, and the drawing module specifically uses At:
  • the relevant design pattern of the TFT pattern is drawn.
  • the drawing module is specifically used for:
  • the drawing module is specifically used for:
  • the drawing module is specifically used for:
  • the drawing module is specifically used for:
  • the common electrode pattern in the gate metal layer of the TFT pattern is drawn.
  • the pixel design strategy information includes a vertical shielding metal design line width, a horizontal shielding metal design line width, and an intermediate shielding metal design line width
  • the drawing module is specifically used for:
  • the TFT pattern gate metal layer is drawn with reference to the pixel data line pattern and the reference pattern The masking metal pattern in.
  • the drawing module is specifically used for:
  • the ITO slit pattern in the display area is drawn.
  • the drawing module is specifically used for:
  • Pattern adjustment is performed on the design attributes of each layer of the TFT and the design attributes between the various layers of the TFT that do not conform to the TFT design strategy information, until the TFT design strategy information is satisfied, and the TFT pattern is obtained;
  • the process parameters of the TFT include at least one of electron mobility parameters, cut-off current parameters, leakage current parameters, parasitic capacitance parameters, and TFT round corner design parameters
  • the design attributes of each layer of the TFT include the parameters of each layer in the TFT.
  • At least one of material and thickness parameters, and line width parameters of each layer, and the design attributes between the layers of the TFT include the spacing parameters between the layers of the TFT and the alignment error limiting parameters between the layers of the TFT.
  • the drawing module is specifically used for:
  • the device further includes an inspection and adjustment module, and the inspection and adjustment module is configured to:
  • the overall inspection of the pixel design drawing is performed to determine whether the pixel design drawing complies with the pixel design strategy information
  • the device further includes a test adjustment module, and the test adjustment module is configured to:
  • the charging rate data shows that the charging rate is too low or the charging uniformity is poor, or the feeding voltage is too large, obtain the new pixel design parameters input by the user;
  • a new pixel design drawing of the display panel is drawn.
  • An embodiment of the present invention also provides an electronic device that integrates any pixel design device provided in the embodiment of the present invention, and the electronic device includes:
  • One or more processors are One or more processors;
  • One or more application programs wherein the one or more application programs are stored in the memory and configured to be executed by the processor in the pixel design method described in any of the above pixel design methods A step of.
  • the embodiment of the present invention also provides an electronic device that integrates any pixel design device provided in the embodiment of the present invention.
  • FIG. 14 it shows a schematic structural diagram of an electronic device involved in an embodiment of the present invention, specifically:
  • the electronic device may include one or more processing core processors 1401, one or more computer-readable storage media storage 1402, power supply 1403, input unit 1404 and other components.
  • processing core processors 1401 one or more computer-readable storage media storage 1402, power supply 1403, input unit 1404 and other components.
  • FIG. 14 does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or a combination of certain components, or different component arrangements. in:
  • the processor 1401 is the control center of the electronic device. It uses various interfaces and lines to connect the various parts of the entire electronic device, runs or executes the software programs and/or modules stored in the memory 1402, and calls the Data, perform various functions of electronic equipment and process data, so as to monitor the electronic equipment as a whole.
  • the processor 1401 may include one or more processing cores; preferably, the processor 1401 may integrate an application processor and a modem processor, where the application processor mainly processes the operating system, user interface, application programs, etc. , The modem processor mainly deals with wireless communication. It can be understood that the foregoing modem processor may not be integrated into the processor 1401.
  • the memory 1402 may be used to store software programs and modules.
  • the processor 1401 executes various functional applications and data processing by running the software programs and modules stored in the memory 1402.
  • the memory 1402 may mainly include a program storage area and a data storage area.
  • the program storage area may store an operating system, an application program required by at least one function (such as a sound playback function, an image playback function, etc.), etc.; Data created by the use of electronic equipment, etc.
  • the memory 1402 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.
  • the memory 1402 may also include a memory controller to provide the processor 1401 with access to the memory 1402.
  • the electronic device also includes a power supply 1403 for supplying power to various components.
  • the power supply 1403 may be logically connected to the processor 1401 through a power management system, so that functions such as charging, discharging, and power consumption management can be managed through the power management system.
  • the power supply 1403 may also include any components such as one or more DC or AC power supplies, a recharging system, a power failure detection circuit, a power converter or inverter, and a power status indicator.
  • the electronic device may further include an input unit 1404, which can be used to receive input digital or character information, and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control.
  • an input unit 1404 can be used to receive input digital or character information, and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control.
  • the electronic device may also include a display unit, etc., which will not be repeated here.
  • the processor 1401 in the electronic device will load the executable file corresponding to the process of one or more application programs into the memory 1402 according to the following instructions, and the processor 1401 will run and store the executable file in the memory 1402.
  • the application programs in the storage 1402, thereby realizing various functions, are as follows:
  • the design size information of the display panel configured by the user and the design resolution information of the display panel; calculate the size of a single pixel of the display panel based on the design size information of the display panel and the design resolution information of the display panel; obtain the preset pixels
  • Design strategy information the pixel design strategy information includes the design transmittance information of the display panel; based on the size of a single pixel of the display panel and the pixel design strategy information, the pixels of a single pixel in the display panel are drawn design diagram.
  • an embodiment of the present invention provides a computer-readable storage medium, which may include: read only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks, etc. .
  • a computer program is stored thereon, and the computer program is loaded by the processor to execute the steps in any pixel design method provided by the embodiments of the present invention.
  • each embodiment has its own focus. For a part that is not described in detail in an embodiment, please refer to the detailed description of other embodiments above, which will not be repeated here.
  • each of the above units or structures can be implemented as independent entities, or can be combined arbitrarily, and implemented as the same or several entities, and the specifics are not limited.

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Abstract

本申请实施例公开了一种像素设计方法、装置及电子设备。该方法包括：获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息；基于显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸；基于显示面板单个像素的尺寸及像素设计策略信息，绘制显示面板中单个像素的像素设计图。

Description

像素设计方法、像素设计装置及电子设备 技术领域
本申请涉及显示技术领域，具体涉及一种像素设计方法、装置及电子设备。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)及有机发光二极管显示器(Organic Light Emitting Display，OLED)等各种平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
通常在显示面板的像素设计过程中，主要依据现有产品库进行对比分析，一般参考同尺寸或同分辨率或同像素尺寸的公司内产品，同时结合市场同类产品，制定新产品的各类规格值，通过人工设计像素图纸，经过光学及电学仿真等，与量产产品的像素设计进行反复对比，检查像素设计的相关规范，最终得到实现符合产品规范的设计图档。
技术问题
现有技术像素设计主要停留在人工设计、检查、迭代阶段，主要靠人力使用设计工具一步步设计图纸，需求工时较多，且需要重复多次检查，同时存在漏检风险，由于各种设计规范多，对设计经验依赖性强，新手易出错，需手动计算各种设计参数，像素设计迭代次数也较多，进而导致设计过程极为繁琐/耗时，设计阶段耗时较长，不利 于产品上市。
技术解决方案
本申请实施例提供一种像素设计方法、装置及电子设备，可以在用户进行像素设计过程中智能进行像素设计绘图，降低对设计人员的设计经验依赖性，无需设计人员手动计算设计参数，缩短产品设计时长和评估时间，快速产出符合需求的产品像素设计，提升研发效率，节省人力资源和成本。
为解决上述问题，一方面，本申请提供一种像素设计方法，所述方法包括：
获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息；
基于所述显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸；
获取预设的像素设计策略信息，所述像素设计策略信息中包括所述显示面板的设计透过率信息；
基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图。
另一方面，本申请提供一种像素设计装置，所述装置包括：
第一获取模块，用于获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息；
计算模块，用于基于所述显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸；
第二获取模块，用于获取预设的像素设计策略信息，所述像素设计策略信息中包括所述显示面板的设计透过率信息；
绘制模块，用于基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图。
另一方面，本申请提供一种电子设备，所述电子设备包括：一个 或多个处理器；
存储器；以及
一个或多个应用程序，其中所述一个或多个应用程序被存储于所述存储器中，并配置为由所述处理器执行以实现所述的像素设计方法。
有益效果
本申请可以在显示面板像素设计阶段，可以基于用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸，基于所述显示面板单个像素的尺寸及预设的像素设计策略信息，绘制所述显示面板中单个像素的像素设计图，本申请实施例基于用户配置的显示面板的设计尺寸信息、显示面板的设计分辨率信息及预设像素策略信息，可以在用户进行像素设计过程中智能进行单个像素的像素设计绘图，降低对设计人员的设计经验依赖性，无需设计人员手动计算设计参数，缩短产品设计时长和评估时间，快速产出符合需求的产品像素设计，提升研发效率，节省人力资源和成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供像素设计方法的一个实施例流程示意图；
图2是本申请实施例提供步骤104的一个实施例流程示意图；
图3是本申请实施例中单个像素尺寸的基准图案的结构示意图；
图4是本申请实施例提供步骤202的一个实施例流程示意图；
图5是本申请实施例中像素数据线图案的结构示意图
图6是本申请实施例中在显示面板各像素中绘制TFT图案的一个实施例流程示意图；
图7是本申请实施例中源漏极金属层中的存储电容图案的结构示意图；
图8是本申请实施例中绘制TFT图案的相关设计图案的一个实施例流程示意图；
图9是本申请实施例中栅极金属层中的栅极图案的结构示意图；
图10是本申请实施例中栅极金属层中的公共电极图案的结构示意图；
图11是本申请实施例中遮蔽金属图案的结构示意图；
图12是本申请实施例中新产品和对标产品像素结构部分参数对比示意图；
图13是本申请实施例提供像素设计装置的一个实施例流程示意图；
图14是本申请实施例提供电子设备的一个实施例流程示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化 描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本申请，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
本申请实施例提供一种像素设计方法、装置及电子设备，以下分别进行详细说明。
首先介绍本申请实施例中像素设计方法，该像素设计方法在电子设备中执行。电子设备可以是台式终端或移动终端，电子设备具体还可以是手机、平板电脑、笔记本电脑等中的一种。
如图1所示，为本申请实施例中像素设计方法的一个实施例示意图，该方法包括：
101、获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息。
本申请实施例中，当设计人员(用户)需要对单个像素进行像素设计的时候，可以预先配置好需要设计的显示面板的设计尺寸信息及显示面板的设计分辨率。具体的，此处用户配置可以是用户输入。例如可以是用户在进入像素设计方法对应的程序中，点击预设设计菜单 或者自动弹出显示面板的设计尺寸信息及显示面板的设计分辨率的输入界面，当用户输入相关参数之后，即获取到获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息。
例如，当前像素设计对应的显示面板的设计尺寸55’UHD(Ultra High Definition)，有效显示区域的对角线长138731.517152um，显示面板的设计分辨率为2160*3840。
102、基于所述显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸。
由于显示面板的设计尺寸一般为显示面板斜对角线的长度，此时，所述显示面板的设计尺寸信息包括所述显示面板中有效显示区域的对角线长，例如55’UHD的有效显示区域的对角线长138731.517152um。
步骤102中所述基于所述显示面板的设计尺寸及显示面板的设计分辨率，计算显示面板单个像素的尺寸，可以包括：获取所述显示面板长宽比；按照三角形勾股定理，根据所述显示面板长宽比、所述显示面板中有效显示区域的对角线长，计算所述显示面板中有效显示区域的长度和宽度；根据所述显示面板中有效显示区域的长度和宽度，以及所述显示面板的设计分辨率信息，分别计算所述显示面板中单个像素的尺寸。
其中，显示面板的长宽比(Style)一般是固定的，如16：9，也会有个别设计变动，如21：9，可以获取用户输入的显示面板长宽比。
下面结合具体示例说明一下如何基于所述显示面板的设计尺寸及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸。
显示面板的设计尺寸：Size(对角线长，单位：英寸)；显示面板的长宽比：Style；显示面板的设计分辨率：Reso(Resolution)；单个像素尺寸：pixel长(A)，pixel宽(B)
由如下公式计算可得到有效显示区域的长(Length)、宽(Width)：
Length 2+Width 2＝Size 2
Figure PCTCN2020101839-appb-000001
Length＝Width*Style
根据有效显示区域的长(Length)、宽(Width)，分别除以分辨率的值可得到单个像素的尺寸。例如：55’UHD(对角线138731.517152um)长宽比16：9，根据三角形勾股定理算出有效显示区域的长宽分别为1209600um和680400um，设计分辨率为2160*3840，此时单个像素尺寸的计算方式可以如下：
pixel长(A)＝680400/2160＝315um
pixel宽(B)＝1209600/3840/3(RGB)＝105um
103、获取预设的像素设计策略信息。
一般来说，显示面板的规格，很难有一个完全的定义，因为产品对于消费者而言更多的是主观的感觉，不同厂商提供的显示面板规格，也会有所差别，但是对设计者而言，需要把客户的要求、厂商的要求转化成客观量化的数据作为设计的目标，也就是要转化成可设计的规格，即设计规格(专业规格)。本申请实施例中预置的显示面板的像素设计策略信息，即为预先设置的显示面板的像素设计规范或像素设计规格，以便设计人员在设计时，基于用户配置的显示面板像素数据，自动根据像素设计策略信息绘制像素设计图。
104、基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图。
具体的，基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图可以是：基于所述显示面板单个像素的尺寸及所述像素设计策略信息，在预设的绘制空间中，绘制所述显示面板中单个像素的像素设计图，其中，预设的绘制空间可以是像素设计方法对应的设计程序或设计插件的初始设计空间，例如后续实施例中描述的电子设计自动化(Electronics Design Automation，EDA)中进行像素智能设计时的设计空间。
需要说明的是，本申请实施例中由于是电子设备中执行，各处理对象均为数据或信息的形式存在，例如像素设计策略，实质为像素设计策略信息(例如后续以表格形式存在的各种像素策略)，又例如显 示面板单个像素的尺寸实质是显示面板单个像素的尺寸信息，可以理解的是，后续实施例中提及的线宽、尺寸、数量、位置等均为对应的数据存在，以便电子设备进行处理，具体此处不作赘述。
本申请实施例可以在显示面板像素设计阶段，可以基于用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸，基于所述显示面板单个像素的尺寸及预设的像素设计策略信息，绘制所述显示面板中单个像素的像素设计图，本申请实施例基于用户配置的显示面板的设计尺寸信息、显示面板的设计分辨率信息及预设像素策略信息，可以在用户进行像素设计过程中智能进行像素设计绘图，降低对设计人员的设计经验依赖性，无需设计人员手动计算设计参数，缩短产品设计时长和评估时间，快速产出符合需求的产品像素设计，提升研发效率，节省人力资源和成本。
在本申请实施例中，该像素设计方法的执行流程可以是以插件的形式加载在显示面板设计程序中，也可以是独立于显示面板设计程序之外的像素智能设计程序，只要能在显示面板设计程序中采集用户当前设计操作对应的显示面板设计参数即可，具体此处不作限定。
其中，显示面板设计程序可以是现有的显示面板设计的电子设计自动化(Electronics Design Automation，EDA)程序，例如Protel、Altium Designer、PSPICE、OrCAD等。
所述像素设计策略信息中包括所述显示面板的设计透过率信息。所述设计透过率可以是用户输入配置的，由于新产品透过率影响因素很多，较为复杂，具体的，设计透过率可以是用户基于同类型产品预先确定的，例如，可以采用相同显示面板尺寸的透过率作为当前显示面板的设计透过率。
在确定显示面板的设计透过率之后，可以确定当前显示面板像素设计的设计开口率，例如设计透过率定了，采用一款产品B作为类比，材料和膜层选择相同，根据A穿透率*B开口率＝A开口率*B透过率，计算出A开口率，其中，产品A为当前显示面板。在显示面板像素设计的设计开口率确定了，后续可以用于绘制显示面板中单个像素的像 素设计图。
需要说明的是，本申请实施例中显示面板可以是各种类型的显示面板，例如液晶显示(Liquid Crystal Display，LCD)面板、有机发光二极管(OrganicLight-Emitting Diode，OLED)显示面板等，具体的，如薄膜晶体管液晶显示面板(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)等。
在本申请一些实施例中，由于当显示面板为LCD显示面板时，由于LCD显示面板中包括阵列基板、液晶盒、上偏光片、彩膜基板和下偏光片等基本结构，因此，所述像素设计策略信息中可以包括阵列基板中像素相关结构的第一设计策略信息以及彩膜基板中像素相关结构的第二设计策略信息，此时，如图2所示，步骤104中所述基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图，可以包括步骤201至203，具体如下：
201、基于所述显示面板单个像素的尺寸，绘制单个像素的基准图案。
在确定单个像素的尺寸之后，可以以单个像素的尺寸绘制单个像素的基准图案，后续像素设计的各层可以以此基准图形为基准。如图3所示，以单个像素尺寸：pixel长(A)，pixel宽(B)绘制的基准图案。
202、基于所述第一设计策略信息绘制单个像素中阵列基板相关结构图案。
203、基于所述第二设计策略信息绘制单个像素中彩膜基板相关结构图案。
本实施例中，在绘制单个像素的基准图案之后，可以分别绘制单个像素中阵列基板相关结构图案和单个像素中彩膜基板相关结构图案。
本申请实施例中，阵列基板可以是TFT阵列基板，所述第一设计策略信息中包括所述显示面板的TFT设计策略信息；所述阵列基板相关结构图案包括所述TFT图案的相关设计图案，此时，如图4所示， 步骤202中所述基于所述第一设计策略信息绘制单个像素中阵列基板相关结构图案，可以进一步包括步骤401～403，具体如下：
401、获取用户配置的像素数据线的线宽以及像素数据线和像素之间的像素距离，在所述基准图案中生成像素数据线图案。
本实施例中，可以获取用户输入像素数据线(Data line)的线宽以及像素数据线和像素(pixel)之间的距离，基于像素数据线的线宽以及像素数据线和像素之间的像素距离，可以在所述基准图案中生成像素数据线图案，如图5所示，C为绘制的Data line图案。
402、获取用户配置的显示面板中TFT的长和宽参数。
本步骤中，可以获取用户输入的显示面板中TFT的长和宽参数，即TFT的L值和W值。
403、基于所述TFT的长和宽参数，以及所述TFT设计策略信息，绘制所述TFT图案的相关设计图案。
具体的，步骤403中所述基于所述TFT的长和宽参数，以及所述TFT设计策略信息，绘制所述TFT图案的相关设计图案，可以进一步包括如下步骤(1)～(4)：
(1)基于所述TFT的长和宽参数，以及所述TFT设计策略信息，在所述显示面板各像素中绘制TFT图案。
其中，TFT的长和宽参数即为TFT的沟道长度和沟道宽度参数。如图6所示，所述基于所述TFT的长和宽参数，以及所述TFT设计策略信息，在所述显示面板各像素中绘制TFT图案，可以进一步包括步骤601～603：
601、基于所述TFT的长和宽参数，生成符合所述TFT的长和宽参数的初始TFT图案。
基于所述TFT的长和宽参数，生成符合所述TFT的长和宽参数的初始TFT图案可以是：调用预设的TFT图案库中的TFT图案，基于所述TFT的长和宽参数，生成符合所述TFT的长和宽参数的初始TFT图案。即由于TFT图案的形状都基本相似，主要差异在TFT的长和宽参数，基于确定的TFT长和宽参数，直接可以调用预设的TFT图案库中 的TFT图案，生成符合所述TFT的长和宽参数的初始TFT图案。
602、基于所述TFT设计策略信息，对所述初始TFT图案中TFT的工艺参数，TFT各层设计属性，以及TFT各层之间的设计属性进行检查。
其中，所述TFT设计策略信息包括TFT的工艺参数策略信息、所述TFT各层设计属性策略信息和所述TFT各层之间的设计属性策略信息。
所述TFT的工艺参数策略信息中包括电子迁移率要求、截至电流要求、漏电流要求、寄生电容要求和TFT圆角设计要求中至少一种，所述TFT各层设计属性策略信息包括TFT中各层的材料和厚度策略信息、各层的线宽定义限制策略信息中至少一种，所述TFT各层之间的设计属性策略信息包括TFT各层之间间距策略信息以及TFT各层之间的对准误差限制策略信息等。
此时，所述TFT的工艺参数中包括电子迁移率参数、截至电流参数、漏电流参数、寄生电容参数和TFT圆角设计参数中至少一种，所述TFT各层设计属性包括TFT中各层的材料和厚度参数、各层的线宽参数中至少一种，所述TFT各层之间的设计属性包括TFT各层之间间距参数以及TFT各层之间的对准误差限制参数。
下面以TFT-LCD显示面板为例，对显示面板的设计策略信息进行一下介绍。
对于TFT-LCD显示面板来说，包含很多的专业领域的知识，自然也就涉及很多的专业规格，这些专业规格彼此并不是孤立的，显示面板设计时也并不是所有规格的一个简单的加和，而是要互相协调，明确设计目标及定位，才能保证产品的最终设计成功。
对于TFT-LCD显示面板来说，所述TFT设计策略信息中可以包括材料和厚度策略信息，线宽定义限制策略信息，对准误差限制策略信息和TFT的工艺参数策略信息。
在一个具体实施方式中，所述材料和厚度策略信息中可以包括栅极、栅极绝缘层、半导体层、掺杂半导体层、源漏极金属以及透明电 极中至少一种的材料和厚度信息，材料和厚度策略信息具体可以包括如下表1中的内容。可以理解的是，表1中仅为材料和厚度策略信息中仅为举例，在实际应用中可以包括更多或更少的材料和厚度信息，具体此处不作限定。
表1
Figure PCTCN2020101839-appb-000002
在一个具体实施方式中，所述线宽定义限制策略信息包括栅极金属线、半导体层线、源漏极金属线、接触孔、ITO透明电极中至少一种的线宽定义限制信息。具体的，线宽定义限制策略信息具体可以包括如下表2中的内容。可以理解的是，表2中仅为线宽定义限制策略信息中仅为举例，在实际应用中可以包括更多或更少的线宽定义限制信息，具体此处不作限定。
表2
Figure PCTCN2020101839-appb-000003
Figure PCTCN2020101839-appb-000004
在一个具体实施方式中，所述对准误差限制策略信息中包括半导体层和栅极金属、源漏极金属和栅极金属、源漏极金属和半导体层、接触孔和栅极金属、接触孔和源漏极金属、透明电极和源漏极金属、透明电极和栅极金属、透明电极和接触孔中至少一种的对准误差限制信息。具体的，对准误差限制策略信息具体可以包括如下表3中的内容。可以理解的是，表3中仅为对准误差限制策略信息中仅为举例，在实际应用中可以包括更多或更少的对准误差限制信息，具体此处不作限定。
表3
Figure PCTCN2020101839-appb-000005
Figure PCTCN2020101839-appb-000006
在一个具体实施方式中，所述TFT的工艺参数策略信息中可以包括电子迁移率、截止电压、漏电流寄生电容中至少一种工艺参数，具体的，TFT的工艺参数策略信息可以包括如下表4中的内容，可以理解的是，表4中仅为TFT的工艺参数策略信息中仅为举例，在实际应用中可以包括更多或更少的TFT的工艺参数，具体此处不作限定。
表4
Figure PCTCN2020101839-appb-000007
通常，为了使得设计出来的显示面板在各种情况下都能够满足驱动原理的要求，采用的设计观念是“最坏情况设计”，即在设计时考虑 在极限情况下能够使用，那么其他情形就没有问题。比如画面的帧频在60～75Hz，则以75Hz考虑充电时间，而以60Hz考虑电荷保持时间，这样在两个极限条件下如果能够满足，其它频率下肯定能够满足。因此，在本申请实施例中也采用类似的原则，上述表1～表4中，仅列出单一数值的，表示该单一数值中的值为最坏情况的设计值，相对该设计值为好的方向即满足设计要求，例如表4中的TFT的电子迁移率，该一般值为最坏情况的设计值，一般情况下，TFT的电子迁移率越高，可以间接地帮助了显示器分辨率的提高，因此，电子迁移率大于该一般值即满足设计规范。
需要说明的是，上述表1～表4中仅为TFT设计策略信息中的部分策略信息举例，可以理解的是，除了上述举例的TFT设计策略信息之外，本申请实施例中，还可以根据实际需要包括任何其他更多的TFT设计策略信息，例如端子数量等，本申请实施例中不再详细赘述，任何基于设计规范的设计策略信息都可以基于本申请的发明思想采用，具体此处不作限定。
另外，在实际应用过程中可以针对不同的显示面板，设置不同的显示面板的设计策略信息，而为了达到显示面板的某一特性的最优，在相关显示面板设计策略信息上，可以采用设置更多的设计参数，例如表4中，TFT的电子迁移率中一般值，设置为更大的电子迁移率值，以间接提高显示器分辨率，满足显示器更高分辨率的设计要求。
在像素设计中，与所有设计关系最密切的两项设计值分别是存储电容的大小和TFT的沟道宽度W，其他设计并非不重要，而是轻易不会改变，比如TFT的沟道长度，通常会设定在制作能力的最小极限，以得到最大的开断电流和最小的栅极负载电容，又如栅极绝缘层或金属导电层的材料和厚度等。
603、对所述TFT各层设计属性，以及TFT各层之间的设计属性中 不符合所述TFT设计信息的设计属性进行图案调整，直至满足所述TFT设计策略信息为止，得到TFT图案。
(2)基于所述基准图案和所述TFT图案，在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案。
基于初始设计所决定的存储电容大小和TFT的尺寸，就可以进行像素的初始布局。在满足基本参数的前提下，在合乎TFT的设计准则下，便可绘制像素初始布局。布局的方式，不同的人，不同的公司都会有所不同。比如，同样的存储电容，可以布局成环绕像素的U字型或一字型，H型等，相同的沟道宽度，TFT也会有不同的形状。如图所示。无论如何改变，关键参数必需要满足，且常常为了光学特性或制程良好率，也可以调整TFT或存储电容的形状。
其中，所述基于所述基准图案和所述TFT图案，在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案，包括：在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案时，以每个像素区域的像素短边为参照，确定存储电容图案的上端外沿；以所述TFT图案为参照，确定存储电容图案的左端外沿；以所述像素数据线图案为参照，确定存储电容图案的右端外沿；基于所述存储电容图案的上端外沿、左端外沿和右端外沿，绘制所述存储电容图案。
在一个具体实施例中，源漏极金属层中的存储电容M2_Cst的绘制时，参照TFT图案和像素区域来绘制，具体的，如图7所示：
M2_Cst上端外沿：参照距像素区域短边的距离L；
M2_Cst左端外沿：参照距TFT图案源漏极的距离M；
M2_Cst右端外沿：参照距右端像素数据线的距离N。
其中，L、M、N可以预设配置好，可以是用户输入或者按照不同长宽的TFT自动配置好。
(3)基于所述存储电容图案和所述像素数据线图案，绘制所述TFT图案的相关设计图案。
具体的，所述基于所述存储电容图案和所述像素数据线图案，绘 制所述TFT图案的相关设计图案，如图8所示，可以进一步包括步骤801～804，具体如下：
801、基于所述像素数据线图案及所述TFT设计策略信息，绘制所述TFT图案栅极金属层中的栅极图案。
其中，所述基于所述像素数据线图案及所述TFT设计策略信息，绘制所述TFT图案栅极金属层中的栅极图案，包括：根据所述像素数据线图案，确定所述栅极金属层中的栅极的两端；基于所述TFT设计策略信息，确定所述栅极金属层中的栅极中间段数值；基于所述栅极金属层中的栅极的两端和所述栅极金属层中的栅极中间段数值，绘制所述TFT图案栅极金属层中的栅极图案。
具体的，如图9所示，栅极金属层中的栅极图案M1-Gate：
两端：对位参照像素数据线补值处绘制，厚度与像素数据线的厚度P相同；
中间段数值：参照图9中TFT图案中Q和R的厚度绘制。
P、Q、R均为预先设置的尺寸参数。
802、基于所述栅极金属层中的栅极图案和所述存储电容图案，绘制所述TFT图案栅极金属层中的公共电极图案。
其中，所述基于所述栅极金属层中的栅极图案和所述存储电容图案，绘制所述TFT图案栅极金属层中的公共电极图案，包括：基于所述存储电容图案，确定栅极金属层中的公共电极的突出位置；基于所述栅极金属层中的栅极图案，确定栅极金属层中的公共电极的水平位置；基于所述栅极金属层中的公共电极的突出位置和水平位置，绘制所述TFT图案栅极金属层中的公共电极图案。
具体的，如图10所示，栅极金属层中的公共电极图案M1-Acom：
突出位置(S)：参照存储电容图案绘制；
水平位置(T)：参照栅极金属层中的栅极图案M1_Gate绘制。
T为预先设置的尺寸参数。
803、基于所述像素数据线图案及所述基准图案，绘制所述TFT图案栅极金属层中的遮蔽金属图案。
其中，所述像素设计策略信息中包括垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽，所述基于所述像素数据线图案及所述基准图案，绘制所述TFT图案栅极金属层中的遮蔽金属图案，包括：获取所述像素设计策略信息中垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽；按照所述垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽，参照所述像素数据线图案及所述基准图案，绘制所述TFT图案栅极金属层中的遮蔽金属图案。
如图11所示，遮蔽金属图案M1-SM参照数据线图案和基准图案绘制，标记位置线宽可自动选择是否绘制，宽度均可自动调整。图11中，V为垂直方向遮蔽金属(Shielding metal，SM)设计线宽，X为水平方向SM设计线宽；W’为中间SM设计线宽。
804、绘制显示区ITO狭缝图案。
所述像素设计策略信息中包括狭缝角度及像素分区数量，所述绘制显示区ITO狭缝图案，包括：获取所述像素设计策略信息中所述狭缝角度及像素分区数量；根据所述狭缝角度及像素分区数量，绘制显示区ITO狭缝图案。
本实施例中，基于显示区ITO狭缝(ITO slit)的绘制(包括slit角度及domain数选择)，包括水平/垂直的ITO trunk(ITO龙骨)，是否为slit封口设计等。
当前的像素设计中，存在两种主流的类型，一种是四分区(4-domain)，另一种是八分区(8-domain)，两种像素结构各有优劣，其中四分区的像素具有相对较高的开口率，但是视角特性却相对八分区像素要差不少，而八分区的像素相对具备较好的视角特性。
本申请实施例中，可以预先根据狭缝角度及像素分区数量设定不同的显示区ITO狭缝图案，在确定狭缝角度及像素分区数量之后，即可根据所述狭缝角度及像素分区数量，自动绘制显示区ITO狭缝图案。
阵列基板的像素设计内容完成之后，所有这些图形最后都是要转 移到玻璃基板上，因此在这里还需要将玻璃基板的尺寸定下来，除了将阵列像素和阵列外布线能够放下以外，本申请实施例中像素设计过程中还需要一些对准标记，这些标记一般放在玻璃的边缘或角落处，所以，显示区的尺寸如果是13寸，考虑阵列外布线和对准标记，玻璃基板的尺寸应大于13寸。
上面举例描述了本申请实施例中基于所述第一设计策略信息绘制单个像素中阵列基板相关结构图案的具体实施方式，本申请实施例中，还包括基于所述第二设计策略信息绘制单个像素中彩膜基板相关结构图案，具体的，基于所述第二设计策略信息绘制单个像素中彩膜基板相关结构图案可以包括：
(1)绘制彩膜基板，其中，在绘制彩膜基板时，将所述彩膜基板四边外沿与所述阵列基板中各像素对应的像素区域对齐。
绘制彩膜基板时，可以预先设定彩膜基板策略信息，直接生成对应的彩膜基板图案，最基本的需要保证，在绘制彩膜基板时，将所述彩膜基板四边外沿与所述阵列基板中各像素对应的像素区域对齐。
(2)绘制RGB彩色层，在绘制RGB彩色层时，RGB彩色层四边外沿相对像素区域边缘分别内缩预设数值。
同样的，绘制RGB彩色层可以预先设定RGB彩色层策略信息，直接生成对应的RGB彩色层图案，最基本的需要保证，在绘制RGB彩色层时，RGB彩色层四边外沿相对像素区域边缘分别内缩预设数值，即四边外沿内缩的预设数值可以根据实际应用场景可调，此时，色阻开孔可以参照像素边缘到色阻边缘的距离。
(3)绘制感光间隙子(photo spacer，PS)，在绘制PS时，PS尺寸可以参照预先设定的PS尺寸，分布可以参照预设的CF open(色阻开孔)与BM(Black Matrix，黑色矩阵)的相对距离。
实际PS尺寸及分布根据产品确定，一般会参考相近尺寸显示面板产品中PS的尺寸及分布设定，PS分可以为Main PS，Sub PS两种，具体采用哪一种可以根据实际应用场景确定，可以提示用户选择之后，获取PS类型来绘制对应类型的PS。
上面实施例中描述了所述像素设计策略信息中可以包括阵列基板中像素相关结构的第一设计策略信息以及彩膜基板中像素相关结构的第二设计策略信息，可以理解的是，所述像素设计策略信息中还可以包括其他附加结构的设计策略信息，例如黑色矩阵等，可以参照预先的黑色矩阵策略信息自动进行绘制。
在完成设计单个像素的像素设计图绘制之后，可以阵列形成整个显示面板有效显示(Active Area，AA)区。此后可以进行液晶盒厚、阵列基板中各层材料和厚度参数的输入，具体如图12所示，其中，cell gap为液晶盒厚，Tr％为透过率。
在本申请一些实施例中，在绘制所述显示面板中单个像素的像素设计图之后，所述方法还可以包括自动检查的步骤，具体的，像素设计方法中还包括：对所述像素设计图进行整体检查，确定所述像素设计图是否符合所述像素设计策略信息；对所述像素设计图不符合所述像素设计策略信息的绘制对象，基于所述像素设计策略信息中所述绘制对象对应的设计策略信息进行调整，直至符合所述绘制对象对应的设计策略信息为止。
对所述像素设计图进行整体检查时，当像素设计参数其中一个参数不正常时，可以在像素设计程序中进行提示，提示的方式，可以是在像素设计程序中针对具体像素设计参数不正常进行报错。
在本申请另一些实施例中，在绘制所述显示面板中单个像素的像素设计图之后，还可以后台调用集成电路用模拟程式(SPICE,Simulation Program with Integrated Circuit Emphasis)模型，输出不同错充电压及充电时间的充电率数据，同时输出feedthrough电压(馈入电压)，待人工判断是否符合需求，人工重新输入新的调整的像素设计参数，更新像素设计策略信息，重新绘制新的像素设计图。
具体的，所述像素设计方法还可以包括：对所述像素设计图进行充电测试，输出不同错充电压和充电时间的充电率数据，以及馈入电压；若所述充电率数据中显示充电率过低或充电均匀性差，或者馈入电压过大，获取用户输入的新的像素设计参数；基于所述新的像素设 计参数，调整所述像素设计策略信息，得到新的像素设计策略信息；基于所述新的像素设计策略信息，绘制所述显示面板的新像素设计图。
其中，新的像素设计参数可以是对应问题的关联设计参数，若所述充电率数据中显示充电率过低或充电均匀性差，则新的像素设计参数为充电率或充电均匀性对应的关联设计参数，若馈入电压过大，则新的像素设计参数为馈入电压的关联设计参数。
本实施例中，基于所述新的像素设计策略信息，绘制所述显示面板的新像素设计图可以参照上述实施例中，基于像素设计策略信息，绘制显示面板的像素设计图的具体过程，此处不再赘述。
本实施例由于可以在所述充电率数据中显示充电率过低或充电均匀性差，或者馈入电压过大下，提示用户，并获取用户针对性的输入的新的像素设计参数，基于新的像素设计参数，调整像素设计策略信息，针对具体的问题调整像素设计参数，可以更快绘制所述显示面板的新像素设计图，无需重新绘制调整，提高了研发效率。
由于显示面板技术一直在进步，显示面板的设计规范也一直在更新，因此，后续由于制程精进和设计优化等原因，像素设计规范如果有更新，可以同步更新显示面板的像素设计策略信息，具体的，在本申请一些实施例中，所述像素设计方法还可以包括：获取显示面板更新的像素设计策略信息，所述更新的像素设计策略信息包括至少一结构的像素设计策略信息，或者至少两个像素结构之间的对应关系；基于所述更新的像素设计策略信息，更新所述显示面板的像素设计策略信息。后面可以基于更新后的显示面板的像素设计策略信息，进行新的像素设计绘图。
为了更好实施本申请实施例中像素设计方法，在像素设计方法基础之上，本申请实施例中还提供一种像素设计装置，如图13所示，所述像素设计装置1300包括：
第一获取模块1301，用于获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息；
计算模块1302，用于基于所述显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸；
第二获取模块1303，用于获取预设的像素设计策略信息，所述像素设计策略信息中包括所述显示面板的设计透过率信息；
绘制模块1304，用于基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图。
本申请实施例可以在用户进行像素设计过程中智能进行像素设计绘图，降低对设计人员的设计经验依赖性，无需设计人员手动计算设计参数，缩短产品设计时长和评估时间，快速产出符合需求的产品像素设计，提升研发效率，节省人力资源和成本。
在本申请一些实施例中，所述显示面板的设计尺寸信息包括所述显示面板中有效显示区域的对角线长；所述计算模块具体用于：
获取所述显示面板长宽比；
按照三角形勾股定理，根据所述显示面板长宽比、所述显示面板中有效显示区域的对角线长，计算所述显示面板中有效显示区域的长度和宽度；
根据所述显示面板中有效显示区域的长度和宽度，以及所述显示面板的设计分辨率信息，分别计算所述显示面板中单个像素的尺寸。
在本申请一些实施例中，所述显示面板为液晶显示面板，所述像素设计策略信息中包括阵列基板中像素相关结构的第一设计策略信息以及彩膜基板中像素相关结构的第二设计策略信息；
所述绘制模块具体用于：
基于所述显示面板单个像素的尺寸，绘制单个像素的基准图案；
基于所述第一设计策略信息绘制单个像素中阵列基板相关结构图案；
基于所述第二设计策略信息绘制单个像素中彩膜基板相关结构图案。
在本申请一些实施例中，所述第一设计策略信息中包括所述显示面板的TFT设计策略信息；所述阵列基板相关结构图案包括所述TFT 图案的相关设计图案，所述绘制模块具体用于：
获取用户配置的像素数据线的线宽以及像素数据线和像素之间的像素距离，在所述基准图案中生成像素数据线图案；
获取用户配置的显示面板中TFT的长和宽参数；
基于所述TFT的长和宽参数，以及所述TFT设计策略信息，绘制所述TFT图案的相关设计图案。
在本申请一些实施例中，所述绘制模块具体用于：
基于所述TFT的长和宽参数，以及所述TFT设计策略信息，在所述显示面板各像素中绘制TFT图案；
基于所述基准图案和所述TFT图案，在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案；
基于所述存储电容图案和所述像素数据线图案，绘制所述TFT图案的相关设计图案。
在本申请一些实施例中，所述绘制模块具体用于：
基于所述像素数据线图案及所述TFT设计策略信息，绘制所述TFT图案栅极金属层中的栅极图案；
基于所述栅极金属层中的栅极图案和所述存储电容图案，绘制所述TFT图案栅极金属层中的公共电极图案；
基于所述像素数据线图案及所述基准图案，绘制所述TFT图案栅极金属层中的遮蔽金属图案；
绘制显示区ITO狭缝图案。
在本申请一些实施例中，所述绘制模块具体用于：
根据所述像素数据线图案，确定所述栅极金属层中的栅极的两端；
基于所述TFT设计策略信息，确定所述栅极金属层中的栅极中间段数值；
基于所述栅极金属层中的栅极的两端和所述栅极金属层中的栅极中间段数值，绘制所述TFT图案栅极金属层中的栅极图案。
在本申请一些实施例中，所述绘制模块具体用于：
基于所述存储电容图案，确定栅极金属层中的公共电极的突出位置；
基于所述栅极金属层中的栅极图案，确定栅极金属层中的公共电极的水平位置；
基于所述栅极金属层中的公共电极的突出位置和水平位置，绘制所述TFT图案栅极金属层中的公共电极图案。
在本申请一些实施例中，所述像素设计策略信息中包括垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽，所述绘制模块具体用于：
获取所述像素设计策略信息中垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽；
按照所述垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽，参照所述像素数据线图案及所述基准图案，绘制所述TFT图案栅极金属层中的遮蔽金属图案。
在本申请一些实施例中，所述绘制模块具体用于：
获取所述像素设计策略信息中所述狭缝角度及像素分区数量；
根据所述狭缝角度及像素分区数量，绘制显示区ITO狭缝图案。
在本申请一些实施例中，所述绘制模块具体用于：
基于所述TFT的长和宽参数，生成符合所述TFT的长和宽参数的初始TFT图案；
基于所述TFT设计策略信息，对所述初始TFT图案中TFT的工艺参数，TFT各层设计属性，以及TFT各层之间的设计属性进行检查；
对所述TFT各层设计属性，以及TFT各层之间的设计属性中不符合所述TFT设计策略信息的设计属性进行图案调整，直至满足所述TFT设计策略信息为止，得到TFT图案；
其中，所述TFT的工艺参数中包括电子迁移率参数、截至电流参数、漏电流参数、寄生电容参数和TFT圆角设计参数中至少一种，所述TFT各层设计属性包括TFT中各层的材料和厚度参数、各层的线宽参数中至少一种，所述TFT各层之间的设计属性包括TFT各层之间间 距参数以及TFT各层之间的对准误差限制参数。
在本申请一些实施例中，所述绘制模块具体用于：
在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案时，以每个像素区域的像素短边为参照，确定存储电容图案的上端外沿；
以所述TFT图案为参照，确定存储电容图案的左端外沿；
以所述像素数据线图案为参照，确定存储电容图案的右端外沿；
基于所述存储电容图案的上端外沿、左端外沿和右端外沿，绘制所述存储电容图案。
在本申请一些实施例中，所述装置还包括检查调整模块，所述检查调整模块用于：
在绘制所述显示面板中单个像素的像素设计图之后，对所述像素设计图进行整体检查，确定所述像素设计图是否符合所述像素设计策略信息；
对所述像素设计图不符合所述像素设计策略信息的绘制对象，基于所述像素设计策略信息中所述绘制对象对应的设计策略进行调整，直至符合所述绘制对象对应的设计策略信息为止。
在本申请一些实施例中，所述装置还包括测试调整模块，所述测试调整模块用于：
在绘制所述显示面板中单个像素的像素设计图之后，对所述像素设计图进行充电测试，输出不同错充电压和充电时间的充电率数据，以及馈入电压；
若所述充电率数据中显示充电率过低或充电均匀性差，或者馈入电压过大，获取用户输入的新的像素设计参数；
基于所述新的像素设计参数，调整所述像素设计策略信息，得到新的像素设计策略信息；
基于所述新的像素设计策略信息，绘制所述显示面板的新像素设计图。
本发明实施例还提供一种电子设备，其集成了本发明实施例所提 供的任一种像素设计装置，所述电子设备包括：
一个或多个处理器；
存储器；以及
一个或多个应用程序，其中所述一个或多个应用程序被存储于所述存储器中，并配置为由所述处理器执行上述像素设计方法中任一实施例中所述的像素设计方法中的步骤。
本发明实施例还提供一种电子设备，其集成了本发明实施例所提供的任一种像素设计装置。如图14所示，其示出了本发明实施例所涉及的电子设备的结构示意图，具体来讲：
该电子设备可以包括一个或者一个以上处理核心的处理器1401、一个或一个以上计算机可读存储介质的存储器1402、电源1403和输入单元1404等部件。本领域技术人员可以理解，图14中示出的电子设备结构并不构成对电子设备的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。其中：
处理器1401是该电子设备的控制中心，利用各种接口和线路连接整个电子设备的各个部分，通过运行或执行存储在存储器1402内的软件程序和/或模块，以及调用存储在存储器1402内的数据，执行电子设备的各种功能和处理数据，从而对电子设备进行整体监控。可选的，处理器1401可包括一个或多个处理核心；优选的，处理器1401可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器1401中。
存储器1402可用于存储软件程序以及模块，处理器1401通过运行存储在存储器1402的软件程序以及模块，从而执行各种功能应用以及数据处理。存储器1402可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备的使用所创建的数据等。此外，存储器1402可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。相应地，存储器1402还可以包 括存储器控制器，以提供处理器1401对存储器1402的访问。
电子设备还包括给各个部件供电的电源1403，优选的，电源1403可以通过电源管理系统与处理器1401逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。电源1403还可以包括一个或一个以上的直流或交流电源、再充电系统、电源故障检测电路、电源转换器或者逆变器、电源状态指示器等任意组件。
该电子设备还可包括输入单元1404，该输入单元1404可用于接收输入的数字或字符信息，以及产生与用户设置以及功能控制有关的键盘、鼠标、操作杆、光学或者轨迹球信号输入。
尽管未示出，电子设备还可以包括显示单元等，在此不再赘述。具体在本实施例中，电子设备中的处理器1401会按照如下的指令，将一个或一个以上的应用程序的进程对应的可执行文件加载到存储器1402中，并由处理器1401来运行存储在存储器1402中的应用程序，从而实现各种功能，如下：
获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息；基于所述显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸；获取预设的像素设计策略信息，所述像素设计策略信息中包括所述显示面板的设计透过率信息；基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图。
本领域普通技术人员可以理解，上述实施例的各种方法中的全部或部分步骤可以通过指令来完成，或通过指令控制相关的硬件来完成，该指令可以存储于一计算机可读存储介质中，并由处理器进行加载和执行。
为此，本发明实施例提供一种计算机可读存储介质，该存储介质可以包括：只读存储器(ROM，Read Only Memory)、随机存取记忆体(RAM，Random Access Memory)、磁盘或光盘等。其上存储有计算机程序，所述计算机程序被处理器进行加载，以执行本发明实施例所提供的任一种像素设计方法中的步骤。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文针对其他实施例的详细描述，此处不再赘述。具体实施时，以上各个单元或结构可以作为独立的实体来实现，也可以进行任意组合，作为同一或若干个实体来实现，具体不作限定。
以上对本申请实施例所提供的一种像素设计方法、装置及电子设备进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种像素设计方法，其中，所述方法包括：
    获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息；
    基于所述显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸；
    获取预设的像素设计策略信息，所述像素设计策略信息中包括所述显示面板的设计透过率信息；
    基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图。
  2. 根据权利要求1所述的像素设计方法，其中，所述显示面板的设计尺寸信息包括所述显示面板中有效显示区域的对角线长；所述基于所述显示面板的设计尺寸及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸，包括：
    获取所述显示面板长宽比；
    按照三角形勾股定理，根据所述显示面板长宽比、所述显示面板中有效显示区域的对角线长，计算所述显示面板中有效显示区域的长度和宽度；
    根据所述显示面板中有效显示区域的长度和宽度，以及所述显示面板的设计分辨率信息，计算所述显示面板中单个像素的尺寸。
  3. 根据权利要求1所述的像素设计方法，其中，所述显示面板为液晶显示面板，所述像素设计策略信息中包括阵列基板中像素相关结构的第一设计策略信息以及彩膜基板中像素相关结构的第二设计策略信息；
    所述基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图，包括：
    基于所述显示面板单个像素的尺寸，绘制单个像素的基准图案；
    基于所述第一设计策略信息绘制单个像素中阵列基板相关结构 图案；
    基于所述第二设计策略信息绘制单个像素中彩膜基板相关结构图案。
  4. 根据权利要求3所述的像素设计方法，其中，所述第一设计策略信息中包括所述显示面板的TFT设计策略信息；所述阵列基板相关结构图案包括TFT图案的相关设计图案，所述基于所述第一设计策略信息绘制单个像素中阵列基板相关结构图案，包括：
    获取用户配置的像素数据线的线宽以及像素数据线和像素之间的像素距离，在所述基准图案中生成像素数据线图案；
    获取用户配置的显示面板中TFT的长和宽参数；
    基于所述TFT的长和宽参数，以及所述TFT设计策略信息，绘制所述TFT图案的相关设计图案。
  5. 根据权利要求4所述的像素设计方法，其中，所述基于所述TFT的长和宽参数，以及所述TFT设计策略信息，绘制所述TFT图案的相关设计图案，包括：
    基于所述TFT的长和宽参数，以及所述TFT设计策略信息，在所述显示面板各像素中绘制TFT图案；
    基于所述基准图案和所述TFT图案，在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案；
    基于所述存储电容图案和所述像素数据线图案，绘制所述TFT图案的相关设计图案。
  6. 根据权利要求5所述的像素设计方法，其中，所述基于所述存储电容图案和所述像素数据线图案，绘制所述TFT图案的相关设计图案，包括：
    基于所述像素数据线图案及所述TFT设计策略信息，绘制所述TFT图案栅极金属层中的栅极图案；
    基于所述栅极金属层中的栅极图案和所述存储电容图案，绘制所述TFT图案栅极金属层中的公共电极图案；
    基于所述像素数据线图案及所述基准图案，绘制所述TFT图案栅 极金属层中的遮蔽金属图案；
    绘制显示区ITO狭缝图案。
  7. 根据权利要求6所述的像素设计方法，其中，所述基于所述像素数据线图案及所述TFT设计策略信息，绘制所述TFT图案栅极金属层中的栅极图案，包括：
    根据所述像素数据线图案，确定所述栅极金属层中的栅极的两端；
    基于所述TFT设计策略信息，确定所述栅极金属层中的栅极中间段数值；
    基于所述栅极金属层中的栅极的两端和所述栅极金属层中的栅极中间段数值，绘制所述TFT图案栅极金属层中的栅极图案。
  8. 根据权利要求6所述的像素设计方法，其中，所述基于所述栅极金属层中的栅极图案和所述存储电容图案，绘制所述TFT图案栅极金属层中的公共电极图案，包括：
    基于所述存储电容图案，确定栅极金属层中的公共电极的突出位置；
    基于所述栅极金属层中的栅极图案，确定栅极金属层中的公共电极的水平位置；
    基于所述栅极金属层中的公共电极的突出位置和水平位置，绘制所述TFT图案栅极金属层中的公共电极图案。
  9. 根据权利要求6所述的像素设计方法，其中，所述像素设计策略信息中包括垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽，所述基于所述像素数据线图案及所述基准图案，绘制所述TFT图案栅极金属层中的遮蔽金属图案，包括：
    获取所述像素设计策略信息中垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽；
    按照所述垂直方向遮蔽金属的设计线宽、水平方向遮蔽金属的设计线宽以及中间遮蔽金属设计线宽，参照所述像素数据线图案及所述 基准图案，绘制所述TFT图案栅极金属层中的遮蔽金属图案。
  10. 根据权利要求5所述的像素设计方法，其中，所述像素设计策略信息中包括狭缝角度及像素分区数量，所述绘制显示区ITO狭缝图案，包括：
    获取所述像素设计策略信息中所述狭缝角度及像素分区数量；
    根据所述狭缝角度及像素分区数量，绘制显示区ITO狭缝图案。
  11. 根据权利要求5所述的像素设计方法，其中，所述基于所述TFT的长和宽参数，以及所述TFT设计策略信息，在所述显示面板各像素中绘制TFT图案，包括：
    基于所述TFT的长和宽参数，生成符合所述TFT的长和宽参数的初始TFT图案；
    基于所述TFT设计策略信息，对所述初始TFT图案中TFT的工艺参数，TFT各层设计属性，以及TFT各层之间的设计属性进行检查；
    对所述TFT各层设计属性，以及TFT各层之间的设计属性中不符合所述TFT设计策略信息的设计属性进行图案调整，直至满足所述TFT设计策略信息为止，得到TFT图案；
    其中，所述TFT的工艺参数中包括电子迁移率参数、截至电流参数、漏电流参数、寄生电容参数和TFT圆角设计参数中至少一种，所述TFT各层设计属性包括TFT中各层的材料和厚度参数、各层的线宽参数中至少一种，所述TFT各层之间的设计属性包括TFT各层之间间距参数以及TFT各层之间的对准误差限制参数。
  12. 根据权利要求5所述的像素设计方法，其中，所述基于所述基准图案和所述TFT图案，在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案，包括：
    在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案时，以每个像素区域的像素短边为参照，确定存储电容图案的上端外沿；
    以所述TFT图案为参照，确定存储电容图案的左端外沿；
    以所述像素数据线图案为参照，确定存储电容图案的右端外沿；
    基于所述存储电容图案的上端外沿、左端外沿和右端外沿，绘制所述存储电容图案。
  13. 根据权利要求1所述的像素设计方法，其中，在绘制所述显示面板中单个像素的像素设计图之后，所述方法还包括：
    对所述像素设计图进行整体检查，确定所述像素设计图是否符合所述像素设计策略信息；
    对所述像素设计图不符合所述像素设计策略信息的绘制对象，基于所述像素设计策略信息中所述绘制对象对应的设计策略信息进行调整，直至符合所述绘制对象对应的设计策略信息为止。
  14. 根据权利要求1所述的像素设计方法，其中，在绘制所述显示面板中单个像素的像素设计图之后，所述方法还包括：
    对所述像素设计图进行充电测试，输出不同错充电压和充电时间的充电率数据，以及馈入电压；
    若所述充电率数据中显示充电率过低或充电均匀性差，或者馈入电压过大，获取用户输入的新的像素设计参数；
    基于所述新的像素设计参数，调整所述像素设计策略信息，得到新的像素设计策略信息；
    基于所述新的像素设计策略信息，绘制所述显示面板的新像素设计图。
  15. 一种像素设计装置，其中，所述装置包括：
    第一获取模块，用于获取用户配置的显示面板的设计尺寸信息及显示面板的设计分辨率信息；
    计算模块，用于基于所述显示面板的设计尺寸信息及显示面板的设计分辨率信息，计算显示面板单个像素的尺寸；
    第二获取模块，用于获取预设的像素设计策略信息，所述像素设计策略信息中包括所述显示面板的设计透过率信息；
    绘制模块，用于基于所述显示面板单个像素的尺寸及所述像素设计策略信息，绘制所述显示面板中单个像素的像素设计图。
  16. 根据权利要求15所述的像素设计装置，其中，所述显示面板 的设计尺寸信息包括所述显示面板中有效显示区域的对角线长；所述计算模块具体用于：
    获取所述显示面板长宽比；
    按照三角形勾股定理，根据所述显示面板长宽比、所述显示面板中有效显示区域的对角线长，计算所述显示面板中有效显示区域的长度和宽度；
    根据所述显示面板中有效显示区域的长度和宽度，以及所述显示面板的设计分辨率信息，计算所述显示面板中单个像素的尺寸。
  17. 根据权利要求15所述的像素设计装置，其中，所述显示面板为液晶显示面板，所述像素设计策略信息中包括阵列基板中像素相关结构的第一设计策略信息以及彩膜基板中像素相关结构的第二设计策略信息；
    所述绘制模块具体用于：
    基于所述显示面板单个像素的尺寸，绘制单个像素的基准图案；
    基于所述第一设计策略信息绘制单个像素中阵列基板相关结构图案；
    基于所述第二设计策略信息绘制单个像素中彩膜基板相关结构图案。
  18. 根据权利要求17所述的像素设计装置，其中，所述第一设计策略信息中包括所述显示面板的TFT设计策略信息；所述阵列基板相关结构图案包括所述TFT图案的相关设计图案，所述绘制模块具体用于：
    获取用户配置的像素数据线的线宽以及像素数据线和像素之间的像素距离，在所述基准图案中生成像素数据线图案；
    获取用户配置的显示面板中TFT的长和宽参数；
    基于所述TFT的长和宽参数，以及所述TFT设计策略信息，绘制所述TFT图案的相关设计图案。
  19. 根据权利要求18所述的像素设计装置，其中，所述绘制模块具体用于：
    基于所述TFT的长和宽参数，以及所述TFT设计策略信息，在所述显示面板各像素中绘制TFT图案；
    基于所述基准图案和所述TFT图案，在所述基准图案的每个像素区域中绘制源漏极金属层中的存储电容图案；
    基于所述存储电容图案和所述像素数据线图案，绘制所述TFT图案的相关设计图案。
  20. 一种电子设备，其中，所述电子设备包括：一个或多个处理器；
    存储器；以及
    一个或多个应用程序，其中所述一个或多个应用程序被存储于所述存储器中，并配置为由所述处理器执行以实现权利要求1所述的像素设计方法。
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