WO2021253542A1 - 一种衬底加工方法及半导体器件制造方法 - Google Patents

一种衬底加工方法及半导体器件制造方法 Download PDF

Info

Publication number
WO2021253542A1
WO2021253542A1 PCT/CN2020/101293 CN2020101293W WO2021253542A1 WO 2021253542 A1 WO2021253542 A1 WO 2021253542A1 CN 2020101293 W CN2020101293 W CN 2020101293W WO 2021253542 A1 WO2021253542 A1 WO 2021253542A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
surface treatment
semiconductor layer
processing method
annealing
Prior art date
Application number
PCT/CN2020/101293
Other languages
English (en)
French (fr)
Inventor
李瑞评
曾柏翔
张佳浩
刘增伟
陈铭欣
Original Assignee
福建晶安光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 福建晶安光电有限公司 filed Critical 福建晶安光电有限公司
Priority to CN202080004967.0A priority Critical patent/CN112689886B/zh
Priority to US17/494,191 priority patent/US20220028698A1/en
Publication of WO2021253542A1 publication Critical patent/WO2021253542A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

Definitions

  • the present invention relates to the technical field of semiconductor manufacturing, in particular to a substrate processing method and a semiconductor device manufacturing method.
  • the main processing processes of the substrate include: crystal growth, cutting, grinding, annealing and polishing.
  • the hardness of the substrate is a significant factor that affects the processing quality of the substrate.
  • most of the substrate materials used for the preparation of semiconductor devices have a relatively high Mohs hardness.
  • sapphire has a Mohs hardness of 9.
  • High-hardness materials cause difficulties in substrate processing.
  • the cutting and grinding of the substrate is difficult and time-consuming, and the damage to the machine is large, which increases the cost of substrate processing invisibly.
  • too high substrate hardness directly affects the quality of the final substrate, resulting in poor substrate quality, which in turn affects the performance of subsequent semiconductor devices.
  • the purpose of the present invention is to provide a substrate processing method and a semiconductor device manufacturing method.
  • the substrate is first subjected to single-sided or double-sided surface treatment, so that the substrate reacts with the surface treatment agent during the annealing process to be softened, thereby reducing the processing difficulty of the substrate.
  • the processing quality of the substrate is improved, the quality of the substrate is improved, and the substrate processing efficiency can also be improved.
  • an embodiment of the present invention provides a substrate processing method, which includes the following steps:
  • the annealed substrate is polished.
  • performing surface treatment on the substrate includes:
  • the substrate is baked at a temperature of 100° C. to 200° C. for 0 to 2 hours.
  • the softening agent, the catalyst and the anti-sticking agent are uniformly mixed to obtain a surface treatment agent.
  • annealing the substrate after the surface treatment further includes the following steps:
  • the substrate is annealed in a temperature range of 30°C to 3000°C, and the annealing time is 0.1 h to 30 days.
  • annealing the substrate after the surface treatment further includes the following steps:
  • Heating up heating the furnace to 100°C ⁇ 2000°C at a heating rate of 0.5 ⁇ 200°C/min;
  • Insulation In the temperature range of 100 ⁇ 2000°C, keep for 0.1h ⁇ 500h;
  • Cooling down Cool down the heating furnace to room temperature at a cooling rate of 0.5 ⁇ 200°C/min.
  • the thickness of the modified layer is 0-100% of the thickness of the substrate.
  • the substrate processing method further includes the following steps:
  • Copper polishing and polishing are performed on the cleaned substrate.
  • Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including the following steps:
  • the semiconductor layer is etched.
  • forming at least one semiconductor layer on the first surface and/or the second surface of the substrate further includes the following steps:
  • a second semiconductor layer having a conductivity opposite to that of the first semiconductor layer is formed over the active layer.
  • the semiconductor device manufacturing method further includes:
  • a first electrode and a second electrode communicating with the first semiconductor layer and the second semiconductor layer are respectively formed.
  • the substrate processing method and semiconductor device manufacturing method provided by the present invention have at least the following beneficial technical effects:
  • the substrate is subjected to surface treatment, one or both sides of the substrate can be surface treated, and then the substrate is annealed .
  • the surface treatment agent includes a softening agent, a catalyst and a release agent.
  • the softening agent in the surface treatment agent reacts with the substrate to form a modified layer on the surface of the substrate.
  • the layer has a loose structure, which can soften the substrate and reduce the strength of the substrate surface.
  • the surface treatment and annealing of the substrate can significantly improve the grinding and polishing efficiency in the subsequent grinding, copper polishing, and polishing process, and reduce the processing difficulty of the substrate.
  • the substrate removal rate during grinding can reach 6.20 ⁇ m/min, and the polishing removal rate can reach 15.67 ⁇ m/h.
  • the substrate removal rate is greatly improved, which is conducive to improving production efficiency and reducing costs.
  • the degree of reaction between the surface treatment agent and the substrate can be controlled, that is, the thickness of the softened substrate (modified layer) can be controlled.
  • the polishing efficiency is higher, so it is helpful to reduce the difficulty of subsequent grinding and polishing, improve the processing efficiency, and can improve the processing quality of the substrate.
  • the lattice parameters of the substrate and the thermal stress of epitaxial growth can be adjusted, so that the substrate and the epitaxial layer are more matched, and the lattice mismatch rate and thermal stress can be reduced.
  • the mismatch rate is conducive to improving the quality of the epitaxy.
  • a suitable surface treatment agent can be selected according to the properties of the epitaxial layer, so that the properties of the modified layer formed on the surface of the substrate are closer to those of the epitaxial layer.
  • the thickness of the removed substrate is controlled to be less than the thickness of the modified layer, ensuring that there is a thin layer of the modified layer on the surface of the substrate, so as to effectively adjust the properties of the substrate to better match the needs of epitaxy.
  • FIG. 1 shows a flowchart of a substrate processing method provided by an embodiment of the present invention.
  • Figure 2 shows a schematic diagram of the substrate obtained by wire cutting from the ingot.
  • FIG. 3 shows the stacking method of the substrate when the substrate is subjected to surface treatment in an alternative embodiment.
  • FIG. 4 shows the stacking method of the substrate when the substrate is surface-treated in another alternative embodiment.
  • FIG. 5 shows a schematic diagram of the structure of the modified layer formed by the reaction between the substrate and the surface treatment agent.
  • Fig. 6a shows a schematic diagram of the substrate before the annealing treatment.
  • Figure 6b shows a schematic diagram of the substrate after annealing.
  • FIG. 7 shows a comparison graph of the removal rate with time during the polishing process of the surface-treated substrate of the present invention and the unsurface-treated control substrate.
  • Fig. 8 shows a comparison graph of the removal rate with time during the polishing process of the surface-treated substrate of the present invention and the unsurface-treated control substrate.
  • FIG. 9 shows a schematic diagram of a patterned surface pattern of a substrate without surface treatment.
  • FIG. 10 is a schematic diagram of the patterned surface pattern of the substrate after surface treatment in the present invention.
  • FIG. 11 is a schematic flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present invention.
  • the preparation of the substrate is a very important part of the semiconductor device manufacturing process, and the quality or quality of the substrate directly affects the performance of the device.
  • Substrate processing generally requires a series of complex processes such as crystal growth, cutting, grinding, annealing, polishing, and cleaning.
  • Most of the substrate materials have a relatively high Mohs hardness.
  • the sapphire substrate has a Mohs hardness of 9, which makes the grinding and polishing process more difficult, the processing time is long, the processing quality of the substrate is poor, and the material The loss is also great, and the depreciation of the machine is very fast, which causes the processing cost of the substrate to increase greatly.
  • the present invention provides a substrate processing method and a semiconductor device preparation method.
  • the substrate processing method of the present invention includes the following steps:
  • the above-mentioned substrate may be any substrate used in the manufacture of semiconductor devices.
  • the substrate 100 in this embodiment has a first surface 101 and a second surface 102.
  • the crystal growth process is usually: first put the raw material aluminum oxide in the crucible, heat the crucible and the aluminum oxide in the crucible, and heat the temperature to above 2000 °C to melt the aluminum oxide It is the melt in the molten state; then seeding is carried out, the temperature of the melt surface is stabilized between 2050 °C and 2060 °C, the sapphire seed crystal is placed directly above the liquid surface, and the seed crystal is in contact with the liquid surface of the solution; then Shoulder rest: slowly pull the seed crystal, the weight of the crystal will increase uniformly, so that the crystal diameter will increase to a predetermined diameter; isodiameter growth: pull the crystal at a constant speed and make it grow with the same diameter; cut away: the crystal diameter will shrink until it is formed The sharp point is completely separated from the molten liquid, and the temperature of the crystal after being separated from the solution is cooled, so that a sapphire crystal is obtained.
  • the sapphire crystal obtained by crystal growth is subjected to multi
  • a single-sided surface treatment method can be adopted for the substrate, or a double-sided surface treatment method can also be adopted for the substrate. It mainly includes coating a surface treatment agent on the first surface 101 and/or the second surface 102 of the substrate 100.
  • the treatment agent includes softener: aluminate, silicate, carbonate, hydroxide, oxide or halide, etc., catalyst: reducing material (carbon, silicon, sulfide, metal element, iodide, two Low-valent iron salts and other low-valent compounds), oxidizing materials (high-valence compounds such as potassium permanganate, dichromate, chlorate, nitrate, ferric salt, and bivalent copper salt), acids, alkalis, or ions Salt, anti-sticking agent: oxide, etc.
  • the softener, catalyst and release agent are uniformly mixed and coated on the surface of the substrate.
  • the thickness of the surface treatment agent can be determined according to the requirements of substrate removal rate and annealing parameters in the subsequent substrate grinding and polishing process.
  • a substrate stacking method for single-sided processing of the substrate is shown.
  • the surface treatment agent 200 is first coated on the first surface 101 of the first substrate 100, and then the second substrate 100 is stacked on the surface treatment agent 200.
  • the first surface 101 of the second substrate 100 is in contact with the surface treatment agent 200;
  • the third substrate 100 is placed on the second substrate 100, and the second surface 102 of the third substrate 100 is in contact with the second substrate 100.
  • the second surface 102 of the substrate 100 contacts; then the surface treatment agent 200 is coated on the first surface 100 of the third substrate 100.
  • the substrate and the surface treatment agent are sequentially stacked in this way to form a laminated structure of "substrate-surface treatment agent-substrate" shown in FIG. 3.
  • FIG. 4 a substrate stacking method in which the substrate is subjected to double-sided surface treatment is shown.
  • the first surface 101 and the second surface 102 of the first substrate 100 are respectively coated with the surface treatment agent 200, and then the second substrate 100 is placed on the surface treatment agent 200 above the first surface 101 so that the second The first surface 101 (or the second surface 102) of the substrate is in contact with the surface treatment agent 200, and then the surface treatment agent 200 is coated on the second surface 102 (or the first surface 101) of the second substrate 100;
  • the substrate is repeatedly placed and the surface treatment agent is applied to form a layered structure of "surface treatment agent-substrate-surface treatment agent" shown in FIG. 4.
  • the above-mentioned stacked structure is baked, for example, in a temperature range of 100°C to 200°C for 0 to 2 hours.
  • the surface treatment agent hardly reacts with the substrate, or the degree of reaction is very small.
  • the surface treatment agent is initially dried, so that it can be closely attached to the substrate, which facilitates the reaction with the substrate in the subsequent annealing process.
  • the stacked substrates with surface treatment agents are placed in a heating furnace, and an annealing process is performed.
  • the annealing temperature is between 30° C. and 3000° C.
  • the annealing time is approximately 0.1 hour to 30 days.
  • the annealing process mainly includes: a heating stage, in this stage, the heating furnace is heated to 100° C. to 2000° C. at a heating rate of 0.5 to 200° C./min. Insulation stage: in the temperature range of 100°C to 2000°C, keep for 0.1 hour to 500 hours; cooling stage: cool down at a cooling rate of 0.5 to 200°C/min until the heating furnace is cooled to room temperature.
  • the heating furnace is heated to 1300 ⁇ 1800°C at a heating rate of 1 ⁇ 20°C/min, kept at 1300 ⁇ 1800°C for 1 ⁇ 100 hours, and then cooled at a rate of 1 ⁇ 20°C/min Rate to cool room temperature.
  • the surface treatment agent fully reacts with the substrate.
  • the softening agent in the surface treatment agent is calcium carbonate as an example.
  • the calcium carbonate undergoes a decomposition reaction:
  • the reaction product CaO of the above decomposition reaction has high reactivity and will react with the substrate under high temperature conditions. Taking the sapphire substrate as an example, the following reaction occurs:
  • the values of x and y are all greater than zero, and different combinations of x and y represent different reaction products. Under the high temperature conditions of the holding stage described in this embodiment, there will be multiple reaction products. .
  • the softening agent in the surface treatment agent reacts from the surface of the substrate under the action of the catalyst, as shown in Figure 5, forming a modified layer 103.
  • the softening agent continues to diffuse into the substrate, gradually It reacts with the substrate, and the thickness of the modified layer 103 continues to increase.
  • the thickness of the modified layer 103 can be controlled. For example, according to the requirements of the substrate removal rate in the subsequent grinding and polishing process, the The thickness of the modified layer 103 is controlled within the range of 0-100% of the thickness of the substrate.
  • the Mohs hardness of the modified layer 103 containing the above-mentioned reaction product is about 6-7, which is relatively low.
  • the surface structure of the substrate without surface treatment and annealing is dense and smooth. After the above surface treatment and annealing, the substrate surface becomes rough and loose. Such a loose structure is relatively dense and smooth. It is easier to remove.
  • the lattice parameters of the sapphire substrate and the thermal stress of the epitaxial growth can be adjusted, so that the sapphire substrate and the epitaxial layer are more matched and the lattice mismatch is reduced.
  • the rate and thermal mismatch rate are conducive to improving the quality of the epitaxy.
  • the substrate After annealing, the substrate is polished.
  • the above-mentioned treated substrate and the untreated control substrate were polished under the same polishing process conditions.
  • the parameters such as time are also the same.
  • FIG. 7 shows the removal rate of the two groups of substrates at different polishing stages and the total removal rate of the two groups of substrates after the polishing is completed in the same polishing time. It can be seen from FIG. 7 that compared to the control substrate without surface treatment, the substrate removal rate of the substrate after the above-mentioned treatment of the present invention is significantly improved during the polishing process.
  • the substrate removal rate The removal rate of the substrate after the surface treatment of the invention reached 7.52 ⁇ m/min, while the removal rate of the untreated control substrate was only 4.37 ⁇ m/min; during the 5th to 10th minute grinding process, The removal rate of the substrate after the surface treatment of the present invention is reduced from 7.52 ⁇ m/min to 5.0 ⁇ m/min, while the removal rate of the untreated control substrate is reduced from 4.37 ⁇ m/min to 2.90 ⁇ m/min; From 10 minutes to 12 minutes, the removal rate of the substrate after the surface treatment of the present invention was maintained at 5.0 ⁇ m/min, while the removal rate of the untreated control substrate was maintained at 2.90 ⁇ m/min.
  • the total removal rate of the substrate after the surface treatment of the present invention is as high as 6.20 ⁇ m/min, while the removal rate of the untreated control substrate is only 3.60 ⁇ m/min. It can be seen that the substrate removal rate of the substrate after the surface treatment of the present invention is significantly improved during the grinding process after annealing. That is, the above-mentioned treatment process of the present invention significantly reduces the processing difficulty of the substrate. It is helpful to save grinding time and improve production efficiency.
  • the above-mentioned polishing after the above-mentioned polishing, it further includes cleaning the substrate to remove impurities remaining on the surface of the substrate after polishing. Then the substrate is polished.
  • the above-mentioned processed substrate and the unprocessed control substrate are also polished at the same time under the same polishing process conditions, and the polishing time and other parameters are also the same.
  • the removal rate of the two groups of substrates at different polishing stages and the total removal rate of the two groups of substrates after polishing are shown in the same polishing time. It can be seen from FIG. 8 that, compared with the substrate without surface treatment, the substrate removal rate of the substrate after the surface treatment of the present invention is significantly improved during the polishing process.
  • the substrate removal rate of the present invention is The removal rate of the substrate after surface treatment reached 48 ⁇ m/h, while the removal rate of the untreated control substrate was only 20 ⁇ m/h; during the grinding process from 0.25 hour to 1.5 hour, the present invention The removal rate of the substrate after surface treatment decreased from 48 ⁇ m/h to 17.14 ⁇ m/h, while the removal rate of the untreated control substrate decreased from 20 ⁇ m/h to 14 ⁇ m/h; From h to 2.5 h and 3 h, the removal rate of the substrate after the surface treatment of the present invention is basically the same as that of the control substrate.
  • the total removal rate of the substrate after the surface treatment of the present invention reached 15.67 ⁇ m/h, and the removal rate of the untreated control substrate is 12.33 ⁇ m/h. It can be seen that the substrate removal rate of the substrate after the surface treatment of the present invention is also significantly improved during the polishing process after annealing, that is, the processing difficulty of the substrate is significantly reduced, which is conducive to saving polishing time and improving production. efficient.
  • a suitable surface treatment agent can be selected according to the properties of the epitaxial layer, so that the properties of the modified layer formed on the surface of the substrate are closer to those of the epitaxial layer.
  • the thickness of the removed substrate is controlled to be less than the thickness of the modified layer, ensuring that there is a thin layer of the modified layer on the surface of the substrate, so as to effectively adjust the properties of the substrate to better match the needs of epitaxy.
  • the substrate after the above surface treatment and annealing is patterned to Conducive to the formation of subsequent epitaxial layers.
  • a convex structure 300 is formed on the surface of the substrate 100.
  • FIG. 10 it can be seen from the thickness direction of the substrate that there is still a very thin surface modification layer 103 on the surface of the substrate. Ca 2+ ions remain in the convex structure 300 and the modified layer 103, and the remaining Ca The 2+ ions are 25% higher than the control substrate without surface treatment.
  • the infiltration of Ca 2+ ions can adjust the lattice parameters of the sapphire substrate, so that the sapphire substrate and the epitaxial layer are more matched, and the lattice mismatch rate is reduced, which is beneficial to Improve the quality of epitaxy.
  • the total thickness of the remaining modified layer 103 and the raised structure 300 is basically in the range of 3 ⁇ m to 30 ⁇ m. This thickness range will not affect the formation of the subsequent epitaxial layer, nor will it affect the quality of the epitaxial layer. .
  • a method for manufacturing a semiconductor device includes the following steps:
  • surface treatment is performed on the first surface and/or the second surface of the substrate, the substrate after the surface treatment is annealed, and the annealed substrate is polished. It also includes processes such as cleaning the polished substrate and copper polishing and polishing. The above-mentioned process can be referred to the above-mentioned embodiment, which will not be repeated here.
  • the aforementioned substrate can also be any substrate suitable for semiconductor manufacturing, for example, it can be glass, compound semiconductors and insulators, metals and alloys, oxides, nitrides, compounds of three and five groups, two and six compounds, and four main groups. Elements and compounds, halides, perovskite-type materials, silicates, carbonates, aluminates, etc.
  • S002 forming at least one semiconductor layer on the first surface and/or the second surface of the substrate;
  • forming the above-mentioned at least one semiconductor layer includes: first forming a first semiconductor layer on the substrate, and then forming an active layer on the first semiconductor layer. Then, a second semiconductor layer is formed above the active layer, and the conductivity of the second semiconductor layer is opposite to that of the first semiconductor layer.
  • the method further includes forming a first electrode and a second electrode that communicate with the first semiconductor layer and the second semiconductor layer, respectively.
  • the first semiconductor layer may be an N-type semiconductor layer, and the second semiconductor layer may be a P-type semiconductor layer; the first semiconductor layer may be a P-type semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer.
  • the above-mentioned active layer may be It is a multiple quantum well.
  • the at least one semiconductor layer is etched to form a semiconductor light emitting structure in the at least one semiconductor layer.
  • the substrate processing method of the present invention is also used to process the substrate, which can also save the manufacturing time of the semiconductor device and improve the yield of the semiconductor device.
  • the substrate processing method and semiconductor device manufacturing method provided by the present invention have at least the following beneficial technical effects:
  • the substrate is subjected to surface treatment, one or both sides of the substrate can be surface treated, and then the substrate is annealed .
  • the surface treatment agent includes a softening agent, a catalyst and a release agent.
  • the softening agent in the surface treatment agent reacts with the substrate to form a modified layer on the surface of the substrate.
  • the layer has a loose structure, which can soften the substrate and reduce the strength of the substrate surface.
  • the surface treatment and annealing of the substrate can significantly improve the grinding and polishing efficiency in the subsequent grinding, copper polishing, and polishing process, and reduce the processing difficulty of the substrate.
  • the substrate removal rate during grinding can reach 6.20 ⁇ m/min, and the polishing removal rate can reach 15.67 ⁇ m/h.
  • the substrate removal rate is greatly improved, which is conducive to improving production efficiency and reducing costs.
  • the degree of reaction between the surface treatment agent and the substrate can be controlled, that is, the thickness of the softened substrate (modified layer) can be controlled.
  • the polishing efficiency is higher, so it is helpful to reduce the processing difficulty of the substrate, improve the processing efficiency, and at the same time improve the processing quality of the substrate.
  • the lattice parameters of the substrate and the thermal stress of epitaxial growth can be adjusted, so that the substrate and the epitaxial layer are more matched, and the lattice mismatch rate and thermal stress can be reduced.
  • the mismatch rate is conducive to improving the quality of the epitaxy.
  • a suitable surface treatment agent can be selected according to the properties of the epitaxial layer, so that the properties of the modified layer formed on the surface of the substrate are closer to those of the epitaxial layer.
  • the thickness of the removed substrate is controlled to be less than the thickness of the modified layer, ensuring that there is a thin layer of the modified layer on the surface of the substrate, so as to effectively adjust the properties of the substrate to better match the needs of epitaxy.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本发明提供一种衬底加工方法以及半导体器件制造方法，衬底加工过程中，自晶棒切割得到多个衬底之后，对衬底的表面进行处理，可以是衬底的单面或者双面，然后对衬底进行退火。在退火过程中，在催化剂的作用下，表面处理剂中的软化剂与衬底发生反应，形成一层较软材料的改性层，该改性层为疏松结构，起到软化衬底的作用，降低了衬底表面的硬度。在后续的研磨及抛光过程中，能够显著提高研磨和抛光效率，降低衬底的加工难度。通过调整退火工序的温度及时间，控制表面处理剂与衬底的反应程度，控制被软化的衬底的厚度，进而降低后续机械加工的难度，提高衬底的加工质量。

Description

一种衬底加工方法及半导体器件制造方法 技术领域
本发明涉及半导体制造技术领域，特别涉及一种衬底加工方法及半导体器件制造方法。
 背景技术
在半导体器件的制造过程中，通常需要借助生长衬底进行外延层的生长，因此衬底的加工及制造尤其重要。通常，衬底主要加工过程包括：长晶、切割、研磨、退火和抛光等。衬底的硬度是影响衬底加工质量的一个显著因素。目前用于半导体器件制备的衬底的材料大多莫氏硬度较大，例如蓝宝石，其莫氏硬度达9。高硬度的材料导致衬底加工存在困难，例如衬底的切割、研磨难度大并且耗时长，并且对机台的损伤较大，隐形中增加了衬底加工成本。另外，衬底硬度过高直接影响最终衬底的品质，造成衬底品质差，进而影响后续半导体器件的性能。
基于上述问题及缺陷，有必要提供一种衬底加工方法，以降低衬底的加工难度，提高衬底品质。
 技术解决方案
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种衬底加工方法及半导体器件制造方法。本发明中在对衬底进行退火之前，首先对衬底进行单面或双面表面处理，使得衬底在退火过程中与表面处理剂发生反应而被软化，由此降低衬底的加工难度，由此提高衬底的加工质量，提高衬底的品质，同时也能够提高衬底加工效率。
为实现上述目的及其它相关目的，本发明的一实施例提供了一种衬底加工方法，该方法包括以下步骤：
对长晶形成的晶棒进行切割，得到多个衬底，每一个所述衬底均包括第一表面和第二表面；
对所述衬底进行表面处理；
对表面处理后的所述衬底进行退火，使所述衬底与所述表面处理剂反应，以在所述衬底表面形成改性层；
对退火后的所述衬底进行研磨。
可选地，对所述衬底进行表面处理包括：
在所述衬底的第一表面和/或第二表面涂覆表面处理剂；
将涂覆有表面处理剂的所述衬底依次堆叠放置；
经所述衬底在100℃~200℃的温度下烘烤0~2h。
可选地，对所述衬底进行表面处理之前，还包括以下步骤：
提供软化剂、催化剂以及防粘剂；
将所述软化剂、催化剂以及防粘剂混合均匀得到表面处理剂。
可选地，对表面处理后的所述衬底进行退火还包括以下步骤：
将涂覆有表面处理剂的所述衬底放入加热炉；
在30℃~3000℃的温度范围内对所述衬底进行退火，退火时间为0.1 h~30天。
可选地，对表面处理后的所述衬底进行退火还包括以下步骤：
升温：以0.5~200℃/min的升温速率，将加热炉升温至100℃~2000℃；
保温：在100~2000℃的温度范围内，保温0.1h~500 h；
降温：以0.5~200℃/min的降温速率将加热炉降温至室温。
可选地，所述改性层的厚度为所述衬底厚度的0~100%。
可选地，该衬底加工方法还包括以下步骤：
对研磨后的所述衬底进行清洗；
对清洗后的所述衬底进行铜抛和抛光。
本发明的又一实施例提供了一种半导体器件制备方法，该方法包括以下步骤：
提供衬底，采用本发明所述的衬底加工方法对所述衬底进行加工；
在所述衬底的第一表面和/或第二表面形成至少一层半导体层；
对所述半导体层进行蚀刻。
可选地，在所述衬底的所述第一表面和/或所述第二表面形成至少一层半导体层还包括以下步骤：
在所述衬底上形成第一半导体层；
在所述第一半导体层上方形成有源层；
在所述有源层上方形成与所述第一半导体层的导电性相反的第二半导体层。
可选地，该半导体器件制造方法还包括：
分别形成与所述第一半导体层和所述第二半导体层连通的第一电极和第二电极。
 有益效果
如上所述，本发明提供的衬底加工方法以及半导体器件制造方法，至少具备如下有益技术效果：
本发明的方法中，衬底加工过程中，自晶棒切割得到多个衬底之后，对衬底进行表面处理，可以对衬底的单面或者双面进行表面处理，然后对衬底进行退火。该表面处理剂包括软化剂、催化剂以及防粘剂，在退火过程中，在催化剂的作用下，表面处理剂中的软化剂与衬底发生反应，在衬底表面形成改性层，该改性层为疏松结构，能够起到软化衬底的作用，降低了衬底表面的强度。经表面处理及退火后的衬底在后续的研磨及铜抛、抛光过程中，能够显著提高研磨和抛光效率，降低衬底的加工难度。例如，对于蓝宝石衬底，经上述表面处理及退火后，研磨时衬底移除率可达6.20 μm/min，抛光移除率可达15.67 μm/h。衬底移除率大幅提高，有利于提高生产效率、降低成本。
本发明的方法中，通过调整退火工序的温度及时间，可以控制表面处理剂与衬底的反应程度，即控制被软化的衬底（改性层）的厚度，由于软化后的衬底的研磨及抛光效率更高，因此有利于降低后续研磨和抛光的难度，提高加工效率，并且可以提高衬底的加工质量。
另外，由于改性层与衬底的晶格和热力学性质的差别，可以调整衬底的晶格参数及外延生长的热应力，使衬底与外延层更加匹配，降低晶格失配率及热失配率，有利于提高外延质量。同时还可以根据外延层的性质，选择合适的表面处理剂，使得在衬底表面形成的改性层的性质更加接近外延层的性质。在研磨和抛光过程中，控制去除的衬底的厚度小于改性层的厚度，保证在衬底表面存在一改性层薄层，从而有效调整衬底的性质，更加匹配外延的需求。
 附图说明
图1显示为本发明一实施例提供的衬底加工方法的流程图。
图2显示为自晶棒线切得到的衬底的示意图。
图3显示为一可选实施例中对衬底进行表面处理时衬底的堆叠方式。
图4显示为另一可选实施例中对衬底进行表面处理时衬底的堆叠方式。
图5显示为衬底与表面处理剂发生反应形成改性层的结构示意图。
图6a显示为进行退火处理前的衬底的示意图。
图6b显示为经退火处理之后的衬底的示意图。
图7显示为经表面处理的本发明的衬底与未经表面处理的对照组衬底在研磨过程中移除率随时间变化的对比图。
图8显示为经表面处理的本发明的衬底与未经表面处理的对照组衬底在抛光过程中移除率随时间变化的对比图。
图9显示为未经表面处理的衬底的图形化后的表面图形的示意图。
图10显示为本发明中经表面处理后的衬底的图形化后的表面图形的示意图。
图11显示为本发明另一实施例提供的半导体器件制造方法的流程示意图。
 本发明的实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其它优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量、位置关系及比例可在实现本方技术方案的前提下随意改变，且其组件布局形态也可能更为复杂。
衬底的制备是半导体器件制造过程中非常重要的一个环节，衬底的质量或品质直接影响着器件的性能。衬底加工一般需要经过长晶、切割、研磨、退火、抛光、清洗等一系列复杂的过程。大多数的衬底材料的莫氏硬度较大，例如蓝宝石衬底，其莫氏硬度为9，导致其研磨、抛光等加工过程较为困难，加工耗时长，衬底的加工品质较差，并且物料损耗也很大，机台的折旧很快，这就造成衬底的加工成本大大增加。
为了降低衬底加工难度，提高加工效率，降低衬底加工成本，同时保证甚至提高衬底的加工品质，本发明提供一种衬底加工方法及半导体器件制备方法。
如图1所示，在本发明的一实施例中，本发明的衬底加工方法包括如下步骤：
S01：对长晶形成的晶棒进行切割，得到多个衬底，每一个所述衬底均包括第一表面和第二表面；
本实施例中，上述衬底可以是用于半导体器件制造的任意衬底，例如，可以是玻璃、化合物半导体、金属以及合金、氧化物、氮化物、三五族化合物、二六族化合物、第四主族单质及化合物、卤化物、硅酸盐、碳酸盐等。如图2所示，本实施例中的衬底100具有第一表面101和第二表面102。
以蓝宝石衬底为例，其长晶过程通常为，首先将原料三氧化二铝至于坩埚中，对坩埚及其中的三氧化二铝进行加热，温度加热到2000℃以上，使得三氧化二铝熔化为熔融状态的熔体；然后进行引晶，将熔体液面温度稳定在2050℃~2060℃之间，从液面正上方放入蓝宝石籽晶，并使籽晶与溶体液面接触；然后放肩：缓慢提拉籽晶，晶体重量均匀增加，使晶体直径增大至预定直径；等径生长：匀速提拉晶体，并使其以相等的直径生长；切离：晶体直径缩小，直到形成尖点而与熔液完全脱离，并对脱离溶液后的晶体进行降温，至此得到蓝宝石晶体。对长晶得到的蓝宝石晶体，在线切割机上进行多线切割，得到蓝宝石衬底。
S02：对所述衬底进行表面处理；
在本实施例中，可以对衬底采取单面表面处理的方式，也可以采用双面表面处理的方式。主要包括在衬底100的第一表面101和/或第二表面102上涂覆表面处理剂。该处理剂包括软化剂：铝酸盐、硅酸盐、碳酸盐、氢氧化物、氧化物或卤化物等，催化剂：还原性材料（碳、硅、硫化物、金属单质、碘化物、二价铁盐等低价化合物）、氧化性材料（高锰酸钾、重铬酸盐、氯酸盐、硝酸盐、三价铁盐、二价铜盐等高价态化合物）、酸、碱或离子盐，防粘剂：氧化物等。将上述软化剂、催化剂及防粘剂均匀混合后涂覆在衬底的表面，表面处理剂的厚度可以根据后续衬底研磨和抛光过程中衬底移除率的要求以及退火参数来确定。
在本实施例的一可选实施例中，如图3所示，示出了对衬底进行单面处理的衬底堆放方式。以对衬底100的第一表面102进行表面处理为例，首先在第一衬底100的第一表面101上涂覆表面处理剂200，然后在表面处理剂200上方堆叠放置第二衬底100，并且该第二衬底100的第一表面101与表面处理剂200接触；然后在第二衬底100上方放置第三衬底100，此时第三衬底100的第二表面102与第二衬底100的第二表面102接触；然后在第三衬底100的第一表面100上涂覆表面处理剂200。如此依次堆叠衬底和表面处理剂，形成图3所示的“衬底-表面处理剂-衬底”这样的层叠结构。
在本发明的另一可选实施例中，如图4所示，示出了对衬底进行双面表面处理的衬底堆放方式。首先，在第一衬底100的第一表面101和第二表面102上分别涂覆表面处理剂200，然后在第一表面101上方的表面处理剂200上放置第二衬底100，使得第二衬底的第一表面101（或者第二表面102）与表面处理剂200接触，然后在第二衬底100的第二表面102（或者第一表面101）上涂覆表面处理剂200；如此依次循环放置衬底、涂覆表面处理剂，形成图4所示的“表面处理剂-衬底-表面处理剂”这样的层叠结构。
如图3或图4所示，将衬底表面涂覆表面处理剂之后，对上述堆叠结构进行烘烤，例如在100℃~200℃的温度范围内，烘烤0~2 h。在此烘烤过程中，表面处理剂几乎不与衬底发生反应，或者反应程度非常小。但是在此过程中，表面处理剂被初步烘干，使得其与衬底能够紧密贴合在一起，便于后续退火过程中与衬底反应。
S02：对表面处理后的所述衬底进退火，使所述衬底与所述表面处理剂反应，以在所述衬底表面形成改性层；
经上述表面处理后，将堆叠放置的带有表面处理剂的衬底放入加热炉中，进行退火工序。在本实施例中，退火温度介于30℃~3000℃，退火时间大约为0.1小时~30天。
在可选实施例中，退火过程主要包括：升温阶段，在此阶段，以0.5~200℃/min的升温速率，将加热炉升温至100℃~2000℃。保温阶段：在100℃~2000℃的温度范围内，保温0.1小时~500小时；降温阶段：以0.5~200℃/min的降温速率进行降温，直至加热炉降温至室温。在更加优选的实施例中，以1~20℃/min的升温速率将加热炉升温至1300~1800℃，在1300~1800℃下保温1~100小时，然后以1~20℃/min的降温速率降温室温。
在上述保温阶段，表面处理剂与衬底充分反应。本实施例中，表面处理剂中的软化剂以碳酸钙为例，在保温阶段，碳酸钙发生分解反应：
 
Figure 138455dest_path_image001
上述分解反应的反应产物CaO的反应活性较高，在高温条件下，会与衬底反应，以蓝宝石衬底为例，发生如下反应：
 
Figure 524437dest_path_image002
 
上述反应式中x、y的取值均大于零，并且不同的x、y取值组合代表着不同的反应产物，在本实施例所述的保温阶段的高温条件下，会存在多个反应产物。
在退火过程中，表面处理剂中的软化剂在催化剂的作用下，自衬底表面开始反应，如图5形成改性层103，随着时间的推移，软化剂不断向衬底内部扩散，逐步与衬底发生反应，改性层103的厚度不断增加，通过控制保温温度及保温时间，可以控制改性层103的厚度，例如根据后续研磨、抛光过程中衬底移除率的要求，可以将改性层103的厚度控制在衬底厚度的0~100%范围内。
相比于蓝宝石衬底本身，包含上述反应产物的改性层103的莫氏硬度大约为6~7，相对较低。另外，如图6a和图6b所示，未经表面处理及退火的衬底表面结构致密光滑，经上述表面处理及退火之后，衬底表面变得粗糙疏松，这样的疏松结构相对致密光滑的结构更加易于移除。同时，由于改性层与蓝宝石衬底的晶格和热力学性质的差别，可以调整蓝宝石衬底的晶格参数和外延生长的热应力，使得蓝宝石衬底与外延层更加匹配，降低晶格失配率及热失配率，有利于提高外延质量。
S03：对退火后的所述衬底进行研磨。
退火结束后，对衬底进行研磨。为了验证经上述表面处理及退火后的衬底的研磨的移除率，本实施例中，对经上述处理的衬底以及未经处理的对照组衬底以相同的研磨工艺条件进行研磨，研磨时间等参数也相同。
如图7所示，示出了在相同的研磨时间内，不同研磨阶段两组衬底的移除率、以及研磨结束后两组衬底的总的移除率。由图7可以看出，相对未经表面处理的对照组衬底，经本发明的上述处理后的衬底在研磨过程中，衬底移除率显著提高，例如在研磨的前5分钟，本发明的表面处理后的衬底的移除率达到7.52μm/min，而未经处理的对照组衬底的移除率仅为4.37μm/min；在研磨第5分钟至第10分钟过程中，本发明的表面处理后的衬底的移除率由7.52μm/min降至5.0μm/min，而未经处理的对照组衬底的移除率由4.37μm/min降至2.90μm/min；第10分钟至第12分钟，本发明的表面处理后的衬底的移除率保持为5.0μm/min，而未经处理的对照组衬底的移除率保持为2.90μm/min。整个研磨阶段，本发明的表面处理后的衬底的总移除率高达6.20μm/min，而未经处理的对照组衬底的移除率仅为3.60μm/min。由此可见，经本发明的表面处理后的衬底在退火之后的研磨过程中，衬底移除率显著提高，即，本发明的上述处理过程显著降低了衬底的加工难度，这就有利于节约研磨时间，提高生产效率。
在本实施例的一可选实施例中，经上述研磨之后，还包括对衬底进行清洗，以除去研磨之后衬底表面留存的杂质。然后对衬底进行抛光，本实施例中，同样对经上述处理的衬底以及未经处理的对照组衬底同时以相同的抛光工艺条件进行抛光，抛光时间等参数也相同。
如图8所示，示出了在相同的抛光时间内，不同抛光阶段两组衬底的移除率、以及抛光结束后两组衬底的总的移除率。由图8可以看出，相对未经表面处理的衬底，经本发明的表面处理后的衬底在抛光过程中，衬底移除率显著提高，例如在研磨的前0.25小时，本发明的表面处理后的衬底的移除率达到48 μm/h，而未经处理的对照组衬底的移除率仅为20 μm/h；在研磨第0.25小时至第1.5小时过程中，本发明的表面处理后的衬底的移除率由48 μm/h降至17.14 μm/h，而未经处理的对照组衬底的移除率由20 μm/h降至14 μm/h；第1.5 h至第2.5 h、第3h过程中，本发明的表面处理后的衬底与对照组衬底的移除率基本相同。整个抛光阶段，本发明的表面处理后的衬底的总移除率达15.67 μm/h，而未经处理的对照组衬底的移除率为12.33 μm/h。由此可见，经本发明的表面处理后的衬底在退火之后的抛光过程中，衬底移除率同样显著提高，即，衬底的加工难度显著降低，这有利于节约抛光时间，提高生产效率。
由上述可见，经上述表面处理及退火之后的衬底在研磨和抛光过程中的衬底移除率均有明显提高，衬底的加工难度显著降低，有利于节约衬底的加工时间，提高生产效率。同时还可以根据外延层的性质，选择合适的表面处理剂，使得在衬底表面形成的改性层的性质更加接近外延层的性质。在研磨和抛光过程中，控制去除的衬底的厚度小于改性层的厚度，保证在衬底表面存在一改性层薄层，从而有效调整衬底的性质，更加匹配外延的需求。
本实施例的另一可选实施例中，如图9所示，以图案化蓝宝石衬底（pattern sapphire substrate，PPS）为例，对经上述表面处理和退火后的衬底进行图案化，以利于后续外延层的形成。衬底100的表面形成凸起结构300。如图10所示，自衬底的厚度方向可见，衬底的表面仍然存在很薄的表面改性层103，凸起结构300及改性层103中均有Ca 2+离子残留，存留的Ca 2+离子相对未经表面处理的对照组衬底高出25%。由于Ca 2+离子的半径比Al 3+半径大，因此Ca 2+离子的渗入可以调节蓝宝石衬底的晶格参数，使蓝宝石衬底与外延层更加匹配，降低晶格失配率，有利于提高外延质量。另外，实验证实，存留的改性层103及凸起结构300的总厚度基本介于3 μm~30 μm范围内，该厚度范围不会影响后续外延层的形成，也不会影响外延层的质量。
本发明的另一实施例中，提供一种半导体器件制造方法，如图11所示，该方法包括如下步骤：
S001：提供衬底，采用本发明上述实施例所述的衬底加工方法对所述衬底进行加工；
如上面实施例所述，对衬底的第一表面和/或第二表面进行表面处理，并对表面处理后的衬底进行退火，对退火后的衬底进行研磨。同样还包括，对研磨后的衬底进行清洗以及铜抛和抛光等过程。上述工艺过程可参照上述实施例所述，在此不再赘述。
上述衬底同样可以是任意适用于半导体制造的衬底，例如，可以是玻璃、化合物半导体和绝缘体、金属以及合金、氧化物、氮化物、三五族化合物、二六族化合物、第四主族单质及化合物、卤化物、钙钛矿型材料、硅酸盐、碳酸盐、铝酸盐等。
S002：在所述衬底的第一表面和/或第二表面形成至少一层半导体层；
在本实施例中，以在蓝宝上衬底上形成半导体层为例，形成上述至少一层半导体层包括：首先在衬底上形成第一半导体层，然后在第一半导体层上方形成有源层，之后在上述有源层上方形成第二半导体层，该第二半导体层的导电性与第一半导体层的导电性相反。另外还包括分别形成与第一半导体层和第二半导体层连通的第一电极和第二电极。
S003：对所述半导体层进行蚀刻。
该第一半导体层可以是N型半导体层，第二半导体层则为P型半导体层；第一半导体层可以是P型半导体层，第二半导体层则为N型半导体层，上述有源层可以是多重量子阱。对上述至少一层半导体层进行蚀刻，在上述至少一层半导体层中形成半导体发光结构。
本发明的上述半导体器件制备方法中，同样采用本发明上述的衬底加工方法对衬底进行加工，同样能够节约半导体器件的制造时间，同时提高半导体器件的良率。
如上所述，本发明提供的衬底加工方法以及半导体器件制造方法，至少具备如下有益技术效果：
本发明的方法中，衬底加工过程中，自晶棒切割得到多个衬底之后，对衬底进行表面处理，可以对衬底的单面或者双面进行表面处理，然后对衬底进行退火。该表面处理剂包括软化剂、催化剂以及防粘剂，在退火过程中，在催化剂的作用下，表面处理剂中的软化剂与衬底发生反应，在衬底表面形成改性层，该改性层为疏松结构，能够起到软化衬底的作用，降低了衬底表面的强度。经表面处理及退火后的衬底在后续的研磨及铜抛、抛光过程中，能够显著提高研磨和抛光效率，降低衬底的加工难度。例如，对于蓝宝石衬底，经上述表面处理及退火后，研磨时衬底移除率可达6.20 μm/min，抛光移除率可达15.67 μm/h。衬底移除率大幅提高，有利于提高生产效率、降低成本。
本发明的方法中，通过调整退火工序的温度及时间，可以控制表面处理剂与衬底的反应程度，即控制被软化的衬底（改性层）的厚度，由于软化后的衬底的研磨及抛光效率更高，因此有利于降低衬底的加工难度，提高加工效率，同时提高衬底的加工质量。
另外，由于改性层与衬底的晶格和热力学性质的差别，可以调整衬底的晶格参数及外延生长的热应力，使衬底与外延层更加匹配，降低晶格失配率及热失配率，有利于提高外延质量。同时还可以根据外延层的性质，选择合适的表面处理剂，使得在衬底表面形成的改性层的性质更加接近外延层的性质。在研磨和抛光过程中，控制去除的衬底的厚度小于改性层的厚度，保证在衬底表面存在一改性层薄层，从而有效调整衬底的性质，更加匹配外延的需求。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种衬底加工方法，其特征在于，包括如下步骤：
    对长晶形成的晶棒进行切割，得到多个衬底，每一个所述衬底均包括第一表面和第二表面；
    对所述衬底进行表面处理；
    对表面处理后的所述衬底进行退火，使所述衬底与所述表面处理剂反应，以在所述衬底表面形成改性层；
    对退火后的所述衬底进行研磨。
  2. 根据权利要求1所述的衬底加工方法，其特征在于，对所述衬底进行表面处理包括：
    在所述衬底的第一表面和/或第二表面涂覆表面处理剂；
    将涂覆有表面处理剂的所述衬底依次堆叠放置；
    经所述衬底在100℃~200℃的温度下烘烤0~2 h。
  3. 根据权利要求1所述的衬底加工方法，其特征在于，对所述衬底进行表面处理之前，还包括以下步骤：
    提供软化剂、催化剂以及防粘剂；
    将所述软化剂、催化剂以及防粘剂混合均匀得到表面处理剂。
  4. 根据权利要求1述的衬底加工方法，其特征在于，对表面处理后的所述衬底进行退火还包括以下步骤：
    将涂覆有表面处理剂的所述衬底放入加热炉；
    在30℃~3000℃的温度范围内对所述衬底进行退火，退火时间为0.1h~30天。
  5. 根据权利要求4所述的衬底加工方法，其特征在于，对表面处理后的所述衬底进行退火还包括以下步骤：
    升温：以0.5~200℃/min的升温速率，将加热炉升温至100℃~2000℃；
    保温：在100~2000℃的温度范围内，保温0.1 h~500 h；
    降温：以0.5~200℃/min的降温速率将加热炉降温至室温。
  6. 根据权利要求1或5所述的衬底加工方法，其特征在于，所述改性层的厚度为所述衬底厚度的0~100%。
  7. 根据权利要求1所述的衬底加工方法，其特征在于，还包括以下步骤：
    对研磨后的所述衬底进行清洗；
    对清洗后的所述衬底进行铜抛和抛光。
  8. 一种半导体器件制造方法，其特征在于，包括以下步骤：
    提供衬底，采用权利要求1-7中任意一项所述的衬底加工方法对所述衬底进行加工；
    在所述衬底的第一表面和/或第二表面形成至少一层半导体层；
    对所述半导体层进行蚀刻。
  9. 根据权利要求8所述的半导体器件制造方法，其特征在于，在所述衬底的所述第一表面和/或所述第二表面形成至少一层半导体层还包括以下步骤：
    在所述衬底上形成第一半导体层；
    在所述第一半导体层上方形成有源层；
    在所述有源层上方形成与所述第一半导体层的导电性相反的第二半导体层。
  10. 根据权利要求9所述的半导体器件制造方法，其特征在于，还包括：
    分别形成与所述第一半导体层和所述第二半导体层连通的第一电极和第二电极。
PCT/CN2020/101293 2020-06-16 2020-07-10 一种衬底加工方法及半导体器件制造方法 WO2021253542A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202080004967.0A CN112689886B (zh) 2020-06-16 2020-07-10 一种衬底加工方法及半导体器件制造方法
US17/494,191 US20220028698A1 (en) 2020-06-16 2021-10-05 Method for making semiconductor substrate and method for making semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010547979 2020-06-16
CN202010547979.X 2020-06-16

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/494,191 Continuation-In-Part US20220028698A1 (en) 2020-06-16 2021-10-05 Method for making semiconductor substrate and method for making semiconductor device

Publications (1)

Publication Number Publication Date
WO2021253542A1 true WO2021253542A1 (zh) 2021-12-23

Family

ID=79269093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/101293 WO2021253542A1 (zh) 2020-06-16 2020-07-10 一种衬底加工方法及半导体器件制造方法

Country Status (2)

Country Link
TW (1) TWI774380B (zh)
WO (1) WO2021253542A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115341282A (zh) * 2022-09-15 2022-11-15 福建晶安光电有限公司 一种衬底改性处理方法及半导体发光器件的制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104842225A (zh) * 2015-04-22 2015-08-19 苏州爱彼光电材料有限公司 大尺寸蓝宝石衬底片表面的湿法处理方法
CN105655240A (zh) * 2016-04-05 2016-06-08 福建晶安光电有限公司 一种蓝宝石晶片的加工方法
CN106057647A (zh) * 2016-07-07 2016-10-26 浙江水晶光电科技股份有限公司 一种蓝宝石加工方法
US9650723B1 (en) * 2013-04-11 2017-05-16 Soraa, Inc. Large area seed crystal for ammonothermal crystal growth and method of making
CN110744732A (zh) * 2019-09-03 2020-02-04 福建晶安光电有限公司 一种高性能衬底的制作工艺
CN110846720A (zh) * 2019-10-07 2020-02-28 淮安澳洋顺昌集成电路股份有限公司 一种蓝宝石晶片退火工艺

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017201151B4 (de) * 2016-02-01 2024-05-08 Disco Corporation Verfahren zum Bearbeiten eines Substrats

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9650723B1 (en) * 2013-04-11 2017-05-16 Soraa, Inc. Large area seed crystal for ammonothermal crystal growth and method of making
CN104842225A (zh) * 2015-04-22 2015-08-19 苏州爱彼光电材料有限公司 大尺寸蓝宝石衬底片表面的湿法处理方法
CN105655240A (zh) * 2016-04-05 2016-06-08 福建晶安光电有限公司 一种蓝宝石晶片的加工方法
CN106057647A (zh) * 2016-07-07 2016-10-26 浙江水晶光电科技股份有限公司 一种蓝宝石加工方法
CN110744732A (zh) * 2019-09-03 2020-02-04 福建晶安光电有限公司 一种高性能衬底的制作工艺
CN110846720A (zh) * 2019-10-07 2020-02-28 淮安澳洋顺昌集成电路股份有限公司 一种蓝宝石晶片退火工艺

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115341282A (zh) * 2022-09-15 2022-11-15 福建晶安光电有限公司 一种衬底改性处理方法及半导体发光器件的制造方法

Also Published As

Publication number Publication date
TW202200859A (zh) 2022-01-01
TWI774380B (zh) 2022-08-11

Similar Documents

Publication Publication Date Title
CN107533959B (zh) 外延硅晶片的制造方法
US20220028698A1 (en) Method for making semiconductor substrate and method for making semiconductor device
JP2008153545A (ja) 歪Ｓｉ基板の製造方法
JP7412808B2 (ja) ＳｃＡｌＭｇＯ４基板に基づく窒化ガリウム単結晶及びその製造方法
JP2019186449A (ja) エピタキシャルウェーハの製造方法
WO2018076902A1 (zh) 晶棒的制作方法
JP2010517286A (ja) 複合材料ウェハの製造方法および対応する複合材料ウェハ
CN106868469A (zh) 一种在硅基上无金属催化剂制备石墨烯的方法
WO2021253542A1 (zh) 一种衬底加工方法及半导体器件制造方法
WO2005014898A1 (ja) ウエーハの製造方法
JP2006228763A (ja) 単結晶ＳｉＣ基板の製造方法
CN116646237A (zh) 一种背封硅片结构及其制备方法
CN115246091A (zh) 一种衬底加工方法及半导体器件制造方法
EP3220414B1 (en) Method for polycrystalline oxide thin-film transistor array substrate
CN111826712A (zh) 一种制备晶片级均匀六方氮化硼薄膜的方法
CN112746263B (zh) 一种常压化学气相沉积制备少层石墨烯膜的方法
CN108447772A (zh) 一种coolmos用硅外延片的制造方法
CN115763220A (zh) 一种衬底加工方法及半导体器件制造方法
CN115613130B (zh) 一种在常压下化学气相沉积制备六方氮化硼薄膜的方法
WO2022202767A1 (ja) Ｇａ２Ｏ３系単結晶基板と、Ｇａ２Ｏ３系単結晶基板の製造方法
CN118241309B (zh) 一种极厚膜硅外延片的制备方法
CN113517173B (zh) 一种同质外延β-Ga2O3薄膜及其制备方法
JP2003160395A (ja) 耐反りシリコンウエハ
JP4614616B2 (ja) ＺｎＴｅ単結晶及びその製造方法
JP2022182494A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20940908

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20940908

Country of ref document: EP

Kind code of ref document: A1