WO2021253345A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2021253345A1
WO2021253345A1 PCT/CN2020/096877 CN2020096877W WO2021253345A1 WO 2021253345 A1 WO2021253345 A1 WO 2021253345A1 CN 2020096877 W CN2020096877 W CN 2020096877W WO 2021253345 A1 WO2021253345 A1 WO 2021253345A1
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Prior art keywords
sub
group
circuit
pixels
gate
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PCT/CN2020/096877
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English (en)
French (fr)
Inventor
王丽
王博
王景泉
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20941452.3A priority Critical patent/EP4033479A4/en
Priority to PCT/CN2020/096877 priority patent/WO2021253345A1/zh
Priority to CN202080001029.5A priority patent/CN114207699B/zh
Priority to US17/279,636 priority patent/US11581391B2/en
Publication of WO2021253345A1 publication Critical patent/WO2021253345A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • OLED organic light emitting diode
  • a display panel including: a base substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first peripheral area, the first peripheral area An edge away from the display area has a first curvature, and the first curvature is greater than 0; a plurality of sub-pixels are located in the display area, and each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element; A plurality of data lines are located in the display area and are electrically connected to the plurality of sub-pixels; a plurality of gate lines are located in the display area and are electrically connected to the plurality of sub-pixels; a gate driving circuit is located in the The display area includes a cascaded multi-level gate driving unit, the multi-level gate driving unit is electrically connected to the plurality of gate lines, and one or more gates in the multi-level gate driving circuit The pole driving unit includes a plurality of gate driving sub-
  • the peripheral area is located between the multiple control signal lines and the display area, the multiplexing circuit includes multiple multiplexing units, and each of the multiple multiplexing units is electrically Connected to the plurality of control signal lines, one data signal input line of the plurality of data signal input lines, and at least two data lines of the plurality of data lines.
  • the plurality of sub-pixels includes a first row of sub-pixels and a second row of sub-pixels that are arranged in a first direction and are adjacent to each other, and the number of the first row of sub-pixels is greater than that of the second row The number of sub-pixels; at least one of the multiple multiplexing units is at least partially located in the first area of the first peripheral area, and the first area is located in the second row in the first direction One side of the pixel is away from the side of the display area, and is located on the side of the first row of sub-pixels away from the display area in a second direction perpendicular to the first direction.
  • the display panel further includes: a plurality of control signal connection lines, and the plurality of control signal lines are electrically connected to the plurality of multiplexing units via the plurality of control signal connection lines.
  • the extension direction of the plurality of control signal connection lines is the same as the extension direction of the plurality of data lines.
  • each of the plurality of multiplexing units includes a plurality of switching transistors corresponding to the plurality of control signal lines and the at least two data lines one-to-one, and the plurality of switches
  • the gate of each of the transistors is electrically connected to a corresponding one of the plurality of control signal lines
  • the first electrode of each of the plurality of switching transistors is electrically connected to the plurality of data signals
  • One of the input lines corresponds to a data signal input line
  • the second electrode of each of the plurality of switching transistors is electrically connected to one corresponding data line of the at least two data lines.
  • each of the plurality of control signal lines has the second curvature.
  • the second curvature is the same as the first curvature.
  • the first group of sub-pixels includes: a first sub-group of sub-pixels configured to emit light of a first color, and the pixel driving circuit of the first sub-group of sub-pixels passes through the first group
  • the anode connection line is electrically connected to the anode of the light-emitting element of the first sub-group of sub-pixels;
  • the second sub-group of sub-pixels is configured to emit light of a second color, and the second sub-group of sub-pixels
  • the pixel driving circuit is electrically connected to the anode of the light-emitting element of the second sub-group of sub-pixels via a second group of anode connecting lines;
  • the third sub-group of sub-pixels is configured to emit light of a third color, the first
  • the pixel driving circuits of the three sub-groups of sub-pixels are electrically connected to the anodes of the light-emitting elements of the third sub-groups of sub-pixels via a third group of anode
  • At least one of the first group of anode connection wires, the second group of anode connection wires, and the third group of anode connection wires includes a plurality of first anode connection wires, and the plurality of first anode connection wires includes two The first anode connection line, the length of the first anode connection line closer to the first gate driving sub-circuit among the two first anode connection lines is greater.
  • the length of the first anode connection line closer to the first gate driving sub-circuit among the plurality of first anode connection lines is greater.
  • At least one of the first group of anode connection wires, the second group of anode connection wires, and the third group of anode connection wires is located on the same layer as the anode of the light-emitting element.
  • the first group of anode connection lines are integrally arranged with the anodes of the light-emitting elements of the first sub-group of sub-pixels; the second group of anode connection lines are connected to the second sub-group of sub-pixels The anodes of the light-emitting elements are integrally arranged; the third group of anode connection wires are integrally arranged with the anodes of the light-emitting elements of the third sub-group of sub-pixels.
  • the first group of anode connection lines are electrically connected to the pixel driving circuit of the first sub-group of sub-pixels through a first group of vias; the second group of anode connection lines are electrically connected to the pixel drive circuit of the first sub-group of Via holes are electrically connected to the pixel driving circuit of the second sub-group of sub-pixels; the third group of anode connection lines are electrically connected to the pixel driving circuit of the third sub-group of sub-pixels through a third group of vias Circuit.
  • the plurality of sub-pixels further include a second group of sub-pixels, and the pixel driving circuit of the second group of sub-pixels is located at a distance from the first gate driving sub-circuit to the second gate driving circuit.
  • the second group of sub-pixels includes: a fourth sub-group of sub-pixels configured to emit light of the first color, and the pixel driving circuit of the fourth sub-group of sub-pixels is electrically connected via a fourth group of anode connection lines.
  • the anode of the light-emitting element connected to the fourth sub-group of sub-pixels; a fifth sub-group of sub-pixels configured to emit light of the second color, and the pixels of the fifth sub-group of sub-pixels drive
  • the circuit is electrically connected to the anode of the light-emitting element of the fifth sub-group of sub-pixels via the fifth group of anode connecting lines; and the sixth sub-group of sub-pixels is configured to emit light of the third color, and the first
  • the pixel drive circuits of the six sub-groups of sub-pixels are electrically connected to the anodes of the light-emitting elements of the sixth sub-groups of sub-pixels via a sixth group of anode connection lines.
  • At least one of the fourth group of anode connection wires, the fifth group of anode connection wires, and the sixth group of anode connection wires includes a plurality of second anode connection wires, and the plurality of second anode connection wires The length of the second anode connection line close to the first gate driving sub-circuit is greater.
  • the plurality of sub-pixels further include a third group of sub-pixels and a fourth group of sub-pixels, and the pixels of a group of sub-pixels in the third group of sub-pixels and the fourth group of sub-pixels
  • the driving circuit is located on the side of the second gate driving sub-circuit close to the first gate driving sub-circuit, the first group of sub-pixels and the second group of sub-pixels, and the other group of sub-pixels
  • the pixel driving circuit is located on a side of the second gate driving sub-circuit away from the first gate driving sub-circuit.
  • the third group of sub-pixels includes: a seventh sub-group of sub-pixels configured to emit light of the first color, and the pixel driving circuit of the seventh sub-group of sub-pixels is electrically connected via a seventh group of anode connection lines.
  • the anode of the light-emitting element connected to the seventh sub-group of sub-pixels; an eighth sub-group of sub-pixels configured to emit light of the second color, and the pixels of the eighth sub-group of sub-pixels drive The circuit is electrically connected to the anode of the light-emitting element of the eighth sub-group of sub-pixels via the eighth group of anode connecting lines; and the ninth sub-group of sub-pixels is configured to emit light of the third color, and the first
  • the pixel driving circuits of the nine sub-groups of sub-pixels are electrically connected to the anodes of the light-emitting elements of the ninth sub-groups of sub-pixels via a ninth group of anode connection lines.
  • At least one of the seventh group of anode connection wires, the eighth group of anode connection wires, and the ninth group of anode connection wires includes a plurality of third anode connection wires. The length of the third anode connection line of the second gate driving sub-circuit is greater.
  • the fourth group of sub-pixels includes: a tenth sub-group of sub-pixels configured to emit light of the first color, and the pixel driving circuit of the tenth sub-group of sub-pixels passes through a first Ten groups of anode connecting lines are electrically connected to the anodes of the light-emitting elements of the tenth sub-group of sub-pixels; the eleventh sub-group of sub-pixels are configured to emit light of the second color, and the eleventh sub-group is configured to emit light of the second color.
  • the pixel driving circuit of the group of sub-pixels is electrically connected to the anode of the light-emitting element of the eleventh sub-group of sub-pixels via an eleventh group of anode connection lines; and the twelfth sub-group of sub-pixels is configured to emit For the light of the third color, the pixel driving circuit of the twelfth sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the twelfth sub-group of sub-pixels via the twelfth group of anode connection lines .
  • At least one of the tenth group of anode connection wires, the eleventh group of anode connection wires, and the twelfth group of anode connection wires includes a plurality of fourth anode connection wires, and the plurality of fourth anode connection wires
  • the anode connecting line closer to the second gate driving sub-circuit has a greater length.
  • the plurality of sub-pixels further include a fifth group of sub-pixels, and the pixel driving circuit of the fifth group of sub-pixels is located between the pixel driving circuit of the first group of sub-pixels and the first group of sub-pixels.
  • the pixel driving circuit of the first group of sub-pixels is located between the first gate driving sub-circuit and the pixel driving circuit of the fifth group of sub-pixels In between, the pixel driving circuit of the fourth group of sub-pixels is located between the pixel driving circuit of the fifth group of sub-pixels and the second gate driving sub-circuit.
  • the fifth group of sub-pixels includes: a thirteenth sub-group of sub-pixels configured to emit light of the first color, and the pixel driving circuit of the thirteenth sub-group of sub-pixels passes through the thirteenth group of anodes.
  • the connecting line is electrically connected to the anode of the light-emitting element of the thirteenth sub-group of sub-pixels; the fourteenth sub-group of sub-pixels is configured to emit light of the second color, and the fourteenth sub-group of sub-pixels is configured to emit light of the second color.
  • the pixel drive circuit of the pixel is electrically connected to the anode of the light-emitting element of the fourteenth sub-group of sub-pixels via a fourteenth group of anode connection lines; and the fifteenth sub-group of sub-pixels is configured to emit the For the light of the third color, the pixel driving circuit of the fifteenth sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the fifteenth sub-group of sub-pixels via the fifteenth group of anode connection lines.
  • the lengths of the thirteenth group of anode connecting wires are the same, the lengths of the fourteenth group of anode connecting wires are the same, and the lengths of the fifteenth group of anode connecting wires are the same.
  • the display panel further includes: a first circuit connection line located in the display area, one end of the first circuit connection line is electrically connected to the first gate driving sub-circuit, and the second The other end of a circuit connection line is electrically connected to the second gate driving sub-circuit.
  • the first group of sub-pixels are located between the first gate driving sub-circuit and the second gate driving sub-circuit, and the pixel driving circuit of at least one sub-pixel in the first group of sub-pixels includes : A first pixel driving sub-circuit, located on one side of the first circuit connection line, including a driving transistor, the driving transistor including a first active layer located on one side of the base substrate; a second pixel driving sub-circuit , Located on the side of the first circuit connecting line away from the first pixel driving sub-circuit; and a connecting piece, one end of the connecting piece is electrically connected to the first pixel driving sub-circuit, and another part of the connecting piece One end is electrically connected to the second pixel driving sub-circuit, the orthographic projection of the connector on the base substrate overlaps the orthographic projection of the first circuit connection line on the base substrate, and
  • the connecting member and the driving active layer are located on different layers.
  • the driving transistor further includes: a first gate located on a side of the first active layer away from the base substrate; and located on a side of the first gate away from the base substrate
  • the first pixel driving sub-circuit further includes a storage capacitor, including: a first electrode plate located on the same layer as the first gate; and a second electrode plate located on the first insulating layer and the second insulating layer Between layers. The first circuit connection line and the first gate are located on the same layer, and at least one of the second electrode plate, the first electrode, and the second electrode is located on the same layer as the connecting member.
  • the first electrode, the second electrode and the connecting member are located on the same layer.
  • the one-stage or multi-stage gate drive unit includes a previous-stage gate drive unit and a subsequent-stage gate drive unit that are cascaded, wherein: all the gate drive units of the previous-stage gate drive unit
  • the first gate drive sub-circuit includes a first input terminal of the previous-stage gate drive unit
  • the second gate drive sub-circuit of the previous-stage gate drive unit includes the previous-stage gate drive unit.
  • the first gate driving sub-circuit of the next-stage gate driving unit includes the first input terminal of the next-stage gate driving unit, and the next-stage gate driving unit
  • the second gate driving sub-circuit of the pole driving unit includes a first output terminal of the next-stage gate driving unit.
  • the first output terminal of the previous-stage gate driving unit is electrically connected to a first gate line of the plurality of gate lines;
  • the display panel further includes: a first cascade connection line , The pixel driving circuit located at the side of the first group of sub-pixels away from the second gate driving sub-circuit, and one end of the first cascade connection line is electrically connected to the first gate line, The other end of the first cascade connection line is electrically connected to the first input end of the next-stage gate driving unit.
  • the display panel further includes: a plurality of reset lines located in the display area and electrically connected to the plurality of sub-pixels; and the first gate of the second-stage gate driving unit
  • the pixel driving circuit of the first group of sub-pixels between the driving sub-circuit and the second gate driving sub-circuit is electrically connected to a first reset line of the plurality of reset lines, and the first reset The line is electrically connected to the first gate line via the first cascade connection line.
  • the first cascade connection line is electrically connected to the first gate line through a first via hole, and is electrically connected to the first gate driving unit of the latter stage through a second via hole.
  • the input terminal is electrically connected to the first reset line through the third via.
  • the display panel further includes: a second cascade connection line located on a side of the first group of sub-pixels away from the first gate driving sub-circuit, the second cascade connection line One end of is electrically connected to the first gate line, and the other end of the second cascade connection line is electrically connected to the first reset line.
  • the display panel further includes: multiple light-emitting control lines located in the display area and electrically connected to the multiple sub-pixels; light-emitting control driving circuits located in the display area, including cascaded A multi-level light-emission control driving unit, the multi-level light-emission control driving unit is electrically connected to the plurality of light-emission control lines, and one or multi-level light-emission control driving unit in the multi-level light-emission control driving unit includes a plurality of light-emission control A driving sub-circuit, the plurality of light-emitting control driving sub-circuits include a first light-emitting control driving sub-circuit and a second light-emitting control driving sub-circuit, the first light-emitting control driving sub-circuit and the second light-emitting control driving sub-circuit
  • the pixel driving circuits of the sixth group of sub-pixels in the plurality of sub-pixels are spaced apart.
  • a display device including: the display panel described in any one of the foregoing embodiments.
  • a method for manufacturing a display panel including: providing a base substrate, the base substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first A peripheral area, the edge of the first peripheral area away from the display area has a first curvature, and the first curvature is greater than 0; and forming a plurality of sub-pixels, a plurality of data lines, a plurality of gate lines, and a gate drive Circuits, multiple control signal lines, multiple data signal input lines, and multiplexing circuits.
  • Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element
  • the plurality of data lines are located in the display area and are electrically connected to the plurality of sub-pixels
  • the plurality of gate lines are located in The display area is electrically connected to the plurality of sub-pixels.
  • the gate driving circuit is located in the display area and includes a cascaded multi-level gate driving unit, the multi-level gate driving unit is electrically connected to the plurality of gate lines, and the multi-level gate driving
  • the one-stage or multi-stage gate driving unit in the circuit includes a plurality of gate driving sub-circuits, and the plurality of gate driving sub-circuits includes a first gate driving sub-circuit and a second gate driving sub-circuit.
  • a gate driving sub-circuit and the second gate driving sub-circuit are separated by the pixel driving circuit of the first group of sub-pixels in the plurality of sub-pixels.
  • the plurality of control signal lines are located at least in the first peripheral area, and at least a part of at least one of the plurality of control signal lines has a second curvature, and the second curvature is greater than zero.
  • the plurality of data signal input lines are located at least in the first peripheral area.
  • the multiplexing circuit is located at least in the first peripheral area and between the plurality of control signal lines and the display area, the multiplexing circuit includes a plurality of multiplexing units, so Each of the multiple multiplexing units is electrically connected to the multiple control signal lines, one data signal input line of the multiple data signal input lines, and at least two of the multiple data lines Data line.
  • FIG. 1A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • Fig. 1B is a schematic circuit diagram of a sub-pixel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the structure of a display panel according to another embodiment of the present disclosure.
  • 3A is a schematic diagram showing the distribution of multiple gate driving sub-circuits according to an embodiment of the present disclosure
  • 3B is a schematic diagram showing the distribution of multiple light-emitting control driving sub-circuits according to an embodiment of the present disclosure
  • 4A-4F are schematic diagrams showing the layout of different layers in a gate driving unit according to some implementations of the present disclosure
  • FIG. 5A is an enlarged schematic diagram of 211A1 shown in FIG. 4A;
  • FIG. 5B is an enlarged schematic diagram of 211A2 shown in FIG. 4A;
  • FIG. 6 is a schematic circuit diagram showing a gate driving unit according to an embodiment of the present disclosure.
  • FIGS. 7A-7F are schematic diagrams showing the layout of different layers in a gate driving unit according to other implementations of the present disclosure.
  • FIG. 8A is an enlarged schematic diagram of 211A1 shown in FIG. 7A;
  • FIG. 8B is an enlarged schematic diagram of 211A2 shown in FIG. 7A;
  • FIG. 8C is an enlarged schematic diagram of 211A3 shown in FIG. 7A;
  • FIG. 9 is a schematic circuit diagram showing a gate driving unit according to another embodiment of the present disclosure.
  • 10A-10F are schematic diagrams showing the layout of different layers in a light-emitting control driving unit according to some implementations of the present disclosure
  • FIG. 11A is an enlarged schematic diagram of 221A2 shown in FIG. 10A;
  • FIG. 11B is an enlarged schematic diagram of 221A1 shown in FIG. 10A;
  • FIG. 12 is a schematic circuit diagram showing a light emission control driving unit according to an embodiment of the present disclosure.
  • FIGS. 13A-13F are schematic diagrams showing the layout of different layers in a light-emitting control driving unit according to other implementations of the present disclosure.
  • FIG. 14A is an enlarged schematic diagram of 221A2 shown in FIG. 13A;
  • FIG. 14B is an enlarged schematic diagram of 221A1 shown in FIG. 13A;
  • 15 is a schematic circuit diagram showing a light emission control driving unit according to another embodiment of the present disclosure.
  • 16A is a schematic diagram showing the distribution of multiple gate driving sub-circuits according to another embodiment of the present disclosure.
  • FIG. 16B is a schematic partial cross-sectional view showing a sub-pixel according to an embodiment of the present disclosure
  • FIG. 17A is a schematic diagram showing the layout of the gate driving sub-circuit connection line and the connection member overlapped according to an embodiment of the present disclosure
  • Fig. 17B is a schematic cross-sectional view taken along A-A' shown in Fig. 17A;
  • FIG. 18 is a schematic diagram showing the distribution of multiple light-emitting control driving sub-circuits according to another embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram showing the layout of some layers in a sub-pixel according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram showing a cascaded two-stage gate driving unit according to an embodiment of the present disclosure
  • FIG. 21 is a schematic diagram showing the distribution of multiple gate driving sub-circuits according to another embodiment of the present disclosure.
  • 22A-22E are schematic diagrams showing different groups of anode connection wires according to some embodiments of the present disclosure.
  • FIG. 23A is a schematic diagram showing the structure of a display panel according to another embodiment of the present disclosure.
  • FIG. 23B is an enlarged schematic diagram of circle B shown in FIG. 23A;
  • FIG. 24 is a partial schematic diagram showing FIG. 23B
  • 25 is a schematic flowchart showing a method of manufacturing a display panel according to an embodiment of the present disclosure
  • FIG. 26 is a schematic flowchart showing a method of manufacturing a display panel according to another embodiment of the present disclosure.
  • FIG. 27 is a schematic flowchart showing a manufacturing method of a display panel according to another embodiment of the present disclosure.
  • FIG. 28 is a schematic flowchart showing a manufacturing method of a display panel according to still another embodiment of the present disclosure.
  • a specific component when it is described that a specific component is located between the first component and the second component, there may or may not be an intermediate component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to another component, the specific component may be directly connected to the other component without an intervening component, or may not be directly connected to the other component but with an intervening component.
  • a driving circuit such as a gate driving circuit or a light emitting control driving circuit, is provided in the peripheral area of the display panel.
  • a driving circuit such as a gate driving circuit or a light emitting control driving circuit.
  • FIG. 1A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 1B is a schematic diagram of a circuit of a sub-pixel according to an embodiment of the present disclosure.
  • the display panel includes a base substrate 11 and a plurality of sub-pixels 12.
  • the base substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111.
  • the display area 111 is schematically shown as being substantially circular
  • the peripheral area 112 is schematically shown as being substantially circular. It should be understood that the embodiments of the present disclosure are not limited thereto.
  • the display area 111 may be approximately rectangular
  • the peripheral area 112 may be approximately a rectangular ring.
  • the base substrate 11 may include a flexible substrate, such as a polyimide (PI) substrate or the like.
  • PI polyimide
  • a plurality of sub-pixels 12 are located in the display area 111.
  • the plurality of sub-pixels 12 may include red sub-pixels, green sub-pixels, blue sub-pixels, or the like.
  • each sub-pixel 12 includes a light-emitting element 121 and a pixel driving circuit 122 configured to drive the light-emitting element 121.
  • the light emitting element 121 may include an organic light emitting diode (OLED) or the like.
  • the pixel driving circuit 122 may include 7 transistors and 1 capacitor (7T1C).
  • the seven transistors may be PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistors.
  • some of the seven transistors are PMOS transistors, and the other transistors are N-channel metal oxide semiconductor (N-channel metal oxide semiconductor) transistors.
  • the pixel driving circuit 122 may include 6 transistors and 1 capacitor (6T1C).
  • the base substrate 11 and the plurality of sub-pixels 12 can refer to the above description, and the detailed description will not be repeated in the following description.
  • FIG. 2 is a schematic diagram showing the structure of a display panel according to another embodiment of the present disclosure.
  • FIG. 3A is a schematic diagram showing the distribution of multiple gate driving sub-circuits according to an embodiment of the present disclosure.
  • FIG. 3B is a schematic diagram showing the distribution of multiple light emission control driving sub-circuits according to an embodiment of the present disclosure.
  • the display panel includes a base substrate 11, a plurality of sub-pixels 12, a plurality of gate lines 13, a plurality of light emission control lines 14, a gate driving circuit 21 and a light emission control driving circuit 22.
  • the base substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111.
  • a plurality of sub-pixels 12 are located in the display area 111.
  • the plurality of gate lines 13 are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12.
  • the plurality of gate lines 13 are configured to provide gate driving signals to the plurality of sub-pixels 12.
  • the multiple light-emitting control lines 14 are located in the display area 111 and are electrically connected to the multiple sub-pixels 12.
  • the plurality of emission control lines 14 are configured to provide emission control signals to the plurality of sub-pixels 12.
  • the gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211.
  • the multi-stage gate driving unit 211 is electrically connected to the plurality of gate lines 13.
  • the multi-stage gate driving unit 211 is electrically connected to the plurality of gate lines 13 in a one-to-one correspondence.
  • the gate driving unit 211 may be a shift register.
  • the one-stage or multi-stage gate driving unit 211 in the multi-stage gate driving circuit 211 may include a plurality of gate driving sub-circuits 211A.
  • the plurality of gate driving sub-circuits 211A may include a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2.
  • the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are separated by the pixel driving circuit 122 of the first group of sub-pixels P1 among the plurality of sub-pixels 12.
  • the light emitting control driving circuit 22 is located in the display area 111 and includes a cascaded multi-level light emitting control driving unit 221.
  • the multi-level lighting control driving unit 221 is electrically connected to a plurality of lighting control lines 14.
  • the primary lighting control driving unit 221 is electrically connected to two lighting control lines 14.
  • the light emission control driving unit 221 may be a shift register.
  • the one-stage or multi-stage lighting control driving unit 221 in the multi-stage lighting control driving unit 221 includes a plurality of lighting control driving sub-circuits 221A.
  • the plurality of light-emission control driving sub-circuits 221A include a first light-emission control driving sub-circuit 221A1 and a second light-emission control driving sub-circuit 221A2.
  • the first light-emission control driving sub-circuit 221A1 and the second light-emission control driving sub-circuit 221A2 are driven by pixels of the second group of sub-pixels P2 (in some embodiments, the sixth group of sub-pixels P6) among the plurality of sub-pixels 12
  • the circuits 122 are spaced apart.
  • the gate driving circuit 21 and the light emission control driving circuit 22 are both located in the display area 111. At least one stage of the gate drive unit 211 of the gate drive circuit 21 includes a plurality of gate drive sub-circuits 211A distributed in the pixel drive circuits 122 of the multiple sub-pixels 12, and at least one stage of the light emission control drive unit of the light emission control drive circuit 22 221 includes a plurality of light emission control driving sub-circuits 221A distributed in the pixel driving circuit 122 of the plurality of sub-pixels 12.
  • Such a structure is beneficial to reduce the frame size of the display panel.
  • the gate driving unit 211 of the gate driving circuit 21 can be split in different ways to obtain a plurality of corresponding gate driving sub-circuits 211A.
  • FIGS. 2, 4A-4F are schematic diagrams showing the layout of different layers in a gate driving unit according to some implementations of the present disclosure.
  • FIG. 5A is an enlarged schematic diagram of 211A1 shown in FIG. 4A.
  • FIG. 5B is an enlarged schematic diagram of 211A2 shown in FIG. 4A.
  • some splitting methods of the gate driving unit 211 of the gate driving circuit 21 will be introduced with reference to FIGS. 2, 4A-4F, and 5A-5B.
  • the display panel further includes a plurality of initialization lines 17 and a plurality of reset lines 18.
  • a plurality of initialization lines 17 are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12.
  • the plurality of initialization lines 17 are configured to provide initialization signals to the plurality of sub-pixels 12.
  • the multiple reset lines 18 are located in the display area 111 and are electrically connected to the multiple sub-pixels 12.
  • the plurality of reset lines 18 are configured to provide reset signals to the plurality of sub-pixels 12.
  • the first group of sub-pixels P1 are electrically connected to the first initialization line 171 of the plurality of initialization lines 17, the first reset line 181 of the plurality of reset lines 18, and the first reset line 181 of the plurality of gate lines 13
  • the first initialization line 171 and the first reset line 181 are located at one side of the plurality of gate driving sub-circuits 211A
  • the first gate line 131 and the first light-emitting control line 141 are located far away from the plurality of gate driving sub-circuits 211A.
  • Such a structure helps to reduce the space occupied by the signal line, thereby helping to improve the resolution of the display panel.
  • the orthographic projection of at least one gate driving sub-circuit 211A of the plurality of gate driving sub-circuits 211A on the base substrate 11 and the first part of the sub-pixels 12 of the plurality of sub-pixels 12 The orthographic projection of the anode 1211 of the light-emitting element 121 on the base substrate 11 overlaps, and does not overlap with the orthographic projection of the anode 1211 of the light-emitting element 121 of the remaining sub-pixels 12 of the plurality of sub-pixels 12 on the base substrate 11. In this way, the frame size of the display panel can be reduced without affecting the display uniformity as much as possible.
  • the first group of sub-pixels P1 are electrically connected to the first gate line 131 of the plurality of gate lines 13.
  • the first gate drive sub-circuit 211A1 of each stage of the gate drive unit 211 in the one or multiple stages of the gate drive unit 211 includes a first input terminal IN1 of each stage of the gate drive unit 211, configured to receive the first input Signal.
  • the second gate drive sub-circuit 211A2 of each stage of the gate drive unit 211 of the one or multiple stages of the gate drive unit 211 includes a first output terminal OUT1 of each stage of the gate drive unit 211, which is configured to The pole line 131 outputs a gate drive signal.
  • the first input terminal IN1 of the gate driving unit 211 of the first stage can receive a signal from outside the gate driving circuit 21 as the first input signal, and the first input terminal IN1 of the gate driving unit 211 of other stages can receive The gate driving signal from the upper-level gate driving unit 211 serves as the first input signal.
  • any one-stage gate driving unit 211 in the multi-stage gate driving unit 211 includes a plurality of gate driving sub-circuits 211A, a first gate driving sub-circuit 211A1 and The second gate driving sub-circuit 211A2 is separated in the first direction by the pixel driving circuit 122 of the first group of sub-pixels P1.
  • the first gate driving sub-circuit 211A1 in any one-stage gate driving unit 211 is located in the first gate driving unit 211 of any one-stage gate driving unit 211 in a second direction different from the first direction.
  • the second gate drive sub-circuit 211A2 in any one-stage gate drive unit 211 is located in the second direction.
  • the second gate drive sub-circuit in the previous gate drive unit 211 of any one-stage gate drive unit 211 Between 211A2 and the second gate driving sub-circuit 211A2 in the next-stage gate driving unit 211 of any one-stage gate driving unit 211.
  • the second direction is perpendicular to the first direction.
  • the first direction is the row direction in which the plurality of sub-pixels 12 are arranged
  • the second direction is the column direction in which the plurality of sub-pixels 12 are arranged.
  • the display panel further includes a first set of circuit connection lines.
  • the first group of circuit connection lines includes a first circuit connection line N1 and a second circuit connection line N2.
  • the second gate driving sub-circuit 211A2 is electrically connected to the first gate driving sub-circuit 211A1 via the first circuit connection line N1 and the second circuit connection line N2.
  • the orthographic projection of one of the first circuit connection line N1 and the second circuit connection line N2 on the base substrate 11 and the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 on the base substrate 11 do not overlap,
  • the other orthographic projection on the base substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of at least one sub-pixel 12 in the first group of sub-pixels P1 on the base substrate 11.
  • the orthographic projection of the first circuit connection line N1 on the base substrate 11 and the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 on the base substrate 11 do not overlap, and the second circuit is connected
  • the orthographic projection of the line N2 on the base substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of at least one sub-pixel in the first group of sub-pixels P1 on the base substrate 11. It should be understood that the orthographic projection of the first circuit connection line N1 on the base substrate 11 is between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 in the upper-level gate driving unit 211.
  • the orthographic projections of the pixel driving circuit 122 of the first group of sub-pixels P1 on the base substrate 11 overlap.
  • the pixel driving circuit 122 of at least one sub-pixel 12 in the first group of sub-pixels P1 includes a first pixel driving sub-circuit 122A, a second pixel driving sub-circuit 122B, and a connector 122C.
  • the first pixel driving sub-circuit 122A is located between the first circuit connection line N1 and the second circuit connection line N2, and the second pixel driving sub-circuit 122B is located on the side of the second circuit connection line N2 away from the first pixel driving sub-circuit 122A,
  • the connector 122C is electrically connected to the first pixel driving sub-circuit 122A and the second pixel driving sub-circuit 122B.
  • one end of the connector 122C is electrically connected to the first pixel driving sub-circuit 122A via a via hole, and the other end of the connector 122C is electrically connected to the second pixel driving sub-circuit 122B via a via hole.
  • the orthographic projection of the connector 122C on the base substrate 11 overlaps the orthographic projection of the second circuit connection line N2 on the base substrate 11.
  • the first gate driving sub-circuit 211A1 includes a first group of transistors GT1 and a second capacitor C2
  • the second gate driving sub-circuit 211A2 includes a second group of transistors GT2 and a first capacitor C1.
  • the number of transistors GT2 of the second group is smaller than the number of transistors GT1 of the first group, and the aspect ratio of the channel of at least one transistor in the second group of transistors GT2 is greater than that of the channel of each transistor in the first group of transistors GT1. Aspect ratio.
  • the number and size of the transistors in the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are comprehensively considered, so that the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit The space occupied by 211A2 is relatively close.
  • the first gate driving sub-circuit 211A1 further includes a first clock signal line CK configured to receive a first clock signal, and a second clock signal line configured to receive a second clock signal.
  • CB a first power supply line VGL configured to receive a first power supply voltage
  • VGH configured to receive a second power supply voltage.
  • the second gate driving sub-circuit 211A2 also includes a third clock signal line CK' configured to receive the first clock signal, a fourth clock signal line CB' configured to receive the second clock signal, and a fourth clock signal line CB' configured to receive the second clock signal.
  • the fourth power line VGH' of the power supply voltage For example, the first power supply voltage is less than the second power supply voltage.
  • the first power line VGL is located at the side of the first group of transistors GT1 close to the second gate driving sub-circuit 211A2; the second power line VGH is located at the side of the first group of transistors GT1 away from the second gate driving sub-circuit 211A2 One side; the first clock signal line CK and the second clock signal line CB are located on the side of the second power line VGH away from the second gate driving sub-circuit 211A2; the fourth power line VGH' is located on the second group of transistors GT2 and the second The capacitor C2 is away from the side of the first gate driving sub-circuit 211A1; the third clock signal line CK' and the fourth clock signal line CB' are located in the second group of transistors GT2 and the second capacitor C2 is close to the first gate driving sub-circuit 211A1 On the side.
  • FIG. 6 is a schematic circuit diagram showing a gate driving unit according to an embodiment of the present disclosure.
  • the first group of transistors GT1 is located on the left side of the line L, and the second group of transistors GT2 is located on the right side of the line L.
  • the first group of transistors GT1 includes a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7.
  • the second group of transistors GT2 includes a fourth transistor T4 and a fifth transistor T5.
  • Each transistor in the first group of transistors GT1 and the second group of transistors GT2 includes a gate and an active layer.
  • the active layer includes a first electrode area, a second electrode area, and a channel between the first electrode area and the second electrode area. It should be understood that the area of the active layer of each transistor covered by the gate is the channel, and the area not covered by the gate is the first electrode area and the second electrode area.
  • the material of the active layer may include, for example, polysilicon, such as low temperature polysilicon (LTPS) and the like.
  • the first transistor T1 includes a gate electrode T10 and an active layer
  • the active layer includes a first electrode region T11, a second electrode region T12, and a channel T13 between the first electrode region T11 and the second electrode region T12.
  • the active layer of the transistors T2-T7 includes a channel T23, a channel T33, a channel T43, a channel T53, a channel T63, and a channel T73 in this order.
  • the gate T10 of the first transistor T1 is electrically connected to the first clock signal line CK, and the first electrode region T11 of the first transistor T1 serves as the first input terminal IN1.
  • the first electrode region T11 of the first transistor T1 may be electrically connected to the input electrode 31 to receive the first input signal.
  • the gate T20 of the second transistor T2 is electrically connected to the second electrode area T12 of the first transistor T1, and the first electrode area T21 of the second transistor T2 is electrically connected to the gate of the first transistor T1.
  • the gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1 via the first connection electrode 41.
  • the first electrode region T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1 via the second connection electrode 42.
  • one component or region is connected to another component or region via a connecting electrode can be understood as: one component or region is electrically connected to one end of the connecting electrode via a via hole, and another component or region is electrically connected to one end of the connecting electrode via another A via is electrically connected to the other end of the connecting electrode.
  • the gate of the third transistor T3 is electrically connected to the gate T10 of the first transistor T1
  • the first electrode area T31 of the third transistor T3 is electrically connected to the first power line VGL
  • the second electrode area T32 of the third transistor T3 is electrically connected To the second electrode area T22 of the second transistor T2.
  • the gate T30 of the third transistor T3 and the gate T10 of the first transistor T1 are integrally provided.
  • the gate T60 of the sixth transistor T6 is electrically connected to the second electrode area T32 of the third transistor T3, and the first electrode area T31 of the sixth transistor T6 is electrically connected to the second power line VGH.
  • the gate T60 of the sixth transistor T6 is electrically connected to the second electrode region T32 of the third transistor T3 via the third connection electrode 43.
  • the gate T70 of the seventh transistor T7 is electrically connected to the second clock signal line CB, the first electrode area T71 of the seventh transistor T7 is electrically connected to the second electrode area T72 of the sixth transistor T6, and the second electrode of the seventh transistor T7 The area T72 is electrically connected to the second electrode area T12 of the first transistor T1.
  • the gate T40 of the fourth transistor T4 is electrically connected to the gate T60 of the sixth transistor T6 via the second circuit connection line N2, and the first electrode area T41 of the fourth transistor T4 is electrically connected to The third power line VGL' and the second electrode area T42 of the fourth transistor T4 serve as the first output terminal OUT1.
  • the second electrode region T42 of the fourth transistor T4 may be electrically connected to the first gate line 13 via the output electrode 32 (see FIG. 4C).
  • the gate T40 of the fourth transistor T4 is electrically connected to the second circuit connection line N2 via the fourth connection electrode 44.
  • the first electrode region 41 of the fourth transistor T4 is electrically connected to the third power supply line VGL' via the fifth connection electrode 45.
  • the gate T50 of the fifth transistor T5 is electrically connected to the second electrode area T12 of the first transistor T1 via the first circuit connection line N1, the first electrode area T51 of the fifth transistor T5 is electrically connected to the output electrode 32, and the fifth transistor T5
  • the second electrode area T52 is electrically connected to the third clock signal line CK'.
  • the gate T50 of the fifth transistor T5 is electrically connected to the first circuit connection line N1 via the sixth connection electrode 46.
  • the second electrode region of the fifth transistor T5 is electrically connected to the fourth clock signal line CB' via the seventh connection electrode 47.
  • the first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T50 of the fifth transistor T5, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the output electrode 32.
  • the first electrode plate C11 of the first capacitor C1 and the gate T50 of the fifth transistor T5 are integrally provided.
  • the first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T60 of the sixth transistor T6, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power line VGH.
  • the first electrode plate C21 of the second capacitor C2 and the gate T60 of the sixth transistor T6 are integrally provided.
  • FIG. 7A-7F are schematic diagrams showing the layout of different layers in the gate driving unit according to other implementations of the present disclosure.
  • FIG. 8A is an enlarged schematic diagram of 211A1 shown in FIG. 7A.
  • FIG. 8B is an enlarged schematic diagram of 211A2 shown in FIG. 7A.
  • FIG. 8C is an enlarged schematic diagram of 211A3 shown in FIG. 7A.
  • the first group of circuit connection lines includes a first circuit connection line N1, a second circuit connection line N2, and a third circuit connection line N3.
  • the orthographic projection of the third circuit connection line N3 and the second circuit connection line N2 on the base substrate 11 and the orthographic projection of the pixel drive circuit 122 of the first group of sub-pixels P1 on the base substrate 11 do not overlap, and the first circuit
  • the orthographic projection of the connecting line N1 on the base substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 on the base substrate 11.
  • the orthographic projection of the third circuit connection line N3 and the second circuit connection line N2 on the base substrate 11 is consistent with the first gate driving sub-circuit 211A1 and the second gate located in the upper-level gate driving unit 211.
  • the plurality of gate driving sub-circuits 211A further includes a third gate driving sub-circuit 211A3.
  • the third gate driving sub-circuit 211A3 is located on the side of the second gate driving sub-circuit 211A2 away from the first gate driving sub-circuit 211A1.
  • the third gate driving sub-circuit 211A3 is electrically connected to the second gate driving sub-circuit 211A2 via the third circuit connection line N3.
  • the third gate driving sub-circuit 211A3 is electrically connected to the first gate via the first circuit connection line N1.
  • the third gate driving sub-circuit 211A3 and the second gate driving sub-circuit 211A2 are separated by another first group of sub-pixels P1.
  • the first gate driving sub-circuit 211A1 includes a third group of transistors GT3, a first clock signal line CK configured to receive a first clock signal, and a second clock signal configured to receive a second clock signal.
  • the line CB and the first power supply line VGL configured to receive the first power supply voltage.
  • the second gate driving sub-circuit 211A2 includes at least one capacitor, a fourth group of transistors GT4, and a second power supply line VGH configured to receive the second power supply voltage.
  • the aspect ratio of the channel of one transistor in the fourth group of transistors GT4 is It is larger than the width-to-length ratio of the channel of each transistor in the third group of transistors GT3.
  • the third gate driving sub-circuit 211A3 includes a fifth group of transistors GT5, a third clock signal line CK' configured to receive a first clock signal, and a fourth clock signal line CB' configured to receive a second clock signal.
  • the aspect ratio of the channel of one transistor in the five sets of transistors GT5 is greater than the aspect ratio of the channel of each transistor in the third set of transistors GT3.
  • the first power line VGL is located on the side of the third group of transistors GT3 close to the second gate driving sub-circuit 211A2.
  • the first clock signal line CK and the second clock signal line CB are located on the side of the third group of transistors GT3 away from the second gate driving sub-circuit 211A2.
  • the third clock signal line CK' and the fourth clock signal line CB' are located on the side of the fifth group of transistors GT5 away from the second gate driving sub-circuit 211A2.
  • FIG. 9 is a schematic circuit diagram showing a gate driving unit according to another embodiment of the present disclosure.
  • the third group of transistors GT3 is located on the left side of the line L1
  • the fourth group of transistors GT4 is located on the right side of the line L1 and the upper side of the line L2
  • the fifth group of transistors GT5 is located on the right side of the line L1 and below the line L2. side.
  • the third group of transistors GT3 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the fourth group of transistors GT4 includes a fourth transistor T4 and a sixth transistor T6.
  • the fifth group of transistors GT5 includes a fifth transistor T5 and a seventh transistor T7.
  • at least one capacitor in the second gate driving sub-circuit 211A2 includes a first capacitor C1 and a second capacitor C2.
  • Each of the third group of transistors GT3, the fourth group of transistors GT4, and the fifth group of transistors GT5 includes a gate and an active layer.
  • the active layer includes a first electrode area, a second electrode area, and a channel between the first electrode area and the second electrode area.
  • the material of the active layer may include, for example, polysilicon, such as low-temperature polysilicon.
  • the first transistor T1 includes a gate electrode T10 and an active layer, and the active layer includes a first electrode region T11, a second electrode region T12, and a channel T13 between the first electrode region T11 and the second electrode region T12. , And so on.
  • the active layer of the transistors T2-T7 includes a channel T23, a channel T33, a channel T43, a channel T53, a channel T63, and a channel T73 in this order.
  • the gate T10 of the first transistor T1 is electrically connected to the first clock signal line CK, and the first electrode region T11 of the first transistor T1 serves as the first input terminal IN1.
  • the first electrode region T11 of the first transistor T1 may be electrically connected to the input electrode 31 to receive the first input signal.
  • the gate T20 of the second transistor T2 is electrically connected to the second electrode area T12 of the first transistor T1, and the first electrode area T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1.
  • the gate electrode T20 of the second transistor T2 is electrically connected to the second electrode area T12 of the first transistor T1 via the connecting electrode 51 shown in FIG. 7C
  • the first electrode area T21 of the second transistor T2 is connected via the connection electrode 51 shown in FIG. 7C.
  • the electrode 52 is electrically connected to the gate T10 of the first transistor T1.
  • the gate T30 of the third transistor T3 is electrically connected to the gate T10 of the first transistor T1, the first electrode area T31 of the third transistor T3 is electrically connected to the first power line VGL, and the second electrode area T32 of the third transistor T3 is electrically connected. Connected to the second electrode region T22 of the second transistor T2.
  • the gate T30 of the third transistor T3 and the gate T10 of the first transistor T1 are integrally provided.
  • the second electrode region T32 of the third transistor T3 is electrically connected to the second electrode region T22 of the second transistor T2 via the connection electrode 53 shown in FIG. 7C.
  • the gate of the fourth transistor T4 is electrically connected to the second electrode area T21 of the second transistor T2 via the second circuit connection line N2, and the first electrode area T41 of the fourth transistor T4 is electrically connected to the second power line VGH ,
  • the second electrode area T42 of the fourth transistor T4 is electrically connected to the first gate line 13 via the first output electrode 32.
  • the gate of the fourth transistor T4 is electrically connected to the second circuit connection line N2 via the connection electrode 54 shown in FIG. 7C
  • the second circuit connection line N2 is via the connection electrode 55 shown in FIG. 7C and via the connection electrode 55 shown in FIG.
  • the connection electrode 56 is electrically connected to the second electrode region T21 of the second transistor T2.
  • the gate T60 of the sixth transistor T6 is electrically connected to the gate T40 of the fourth transistor T4, and the first electrode region T61 of the sixth transistor T6 is electrically connected to the second power line VGH.
  • the gate T60 of the sixth transistor T6 and the gate T40 of the fourth transistor T4 are integrally provided.
  • the first electrode region T61 of the sixth transistor T6 is electrically connected to the second power supply line VGH via a via hole.
  • the first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T20 of the second transistor T2 via the first circuit connection line N1, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the first output electrode 32.
  • the first electrode plate C11 of the first capacitor C1 is electrically connected to the first circuit connection line N1 via the connection electrode 57 shown in FIG. 7C
  • the first circuit connection line N1 is electrically connected to the first circuit connection line N1 via the connection electrode 58 shown in FIG. 7C.
  • the second electrode plate C12 of the first capacitor C1 is electrically connected to the first output electrode 32 via a via hole.
  • the first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T40 of the fourth transistor T4, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power line VGH.
  • the first electrode plate C21 of the second capacitor C2 and the gate T40 of the fourth transistor T4 are integrally provided.
  • the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power supply line VGH via a via hole.
  • the gate T50 of the fifth transistor T5 is electrically connected to the gate T20 of the second transistor T2 via the first circuit connection line N1, and the first electrode area T51 of the fifth transistor T5 is electrically connected to the second output electrode 32' ,
  • the second electrode area T52 of the fifth transistor T5 is electrically connected to the fourth clock signal line CB'.
  • the gate T50 of the fifth transistor T5 is electrically connected to the first circuit connection line N1 via the connection electrode 59 shown in FIG. 7C.
  • the second electrode region T52 of the fifth transistor T5 is electrically connected to the fourth clock signal line CB' via the connection electrode 60 shown in FIG. 7C and the connection electrode 61 shown in FIG. 7B.
  • the gate T70 of the seventh transistor T7 is electrically connected to the fourth clock signal line CB′, the first electrode T71 area of the seventh transistor T7 is electrically connected to the second electrode area T62 of the sixth transistor T6 via the third circuit connection line N3, The second electrode region T21 of the seventh transistor T7 is electrically connected to the gate T50 of the fifth transistor T5.
  • the first electrode T71 area of the seventh transistor T7 is electrically connected to the third circuit connection line N3 via the connection electrode 62 shown in FIG. 7C
  • the second electrode area T21 of the seventh transistor T7 is electrically connected to the third circuit connection line N3 via the connection electrode 63 shown in FIG. 7C. It is electrically connected to the gate T50 of the fifth transistor T5.
  • One of the second electrode area T42 of the fourth transistor T4 and the first electrode area T51 of the fifth transistor T5 in FIG. 8A may be used as the first output terminal OUT1 shown in FIG. 9.
  • the light-emission control driving unit 221 of the light-emission control driving circuit 22 can also be split in different ways to obtain a plurality of corresponding light-emission control driving sub-circuits 221A. The following describes in combination with different embodiments.
  • FIG. 10A-10F are schematic diagrams showing the layout of different layers in a light emission control driving unit according to some implementations of the present disclosure.
  • FIG. 11A is an enlarged schematic diagram of 221A2 shown in FIG. 10A.
  • FIG. 11B is an enlarged schematic diagram of 221A1 shown in FIG. 10A.
  • the second group of sub-pixels P2 includes a plurality of first sub-pixels P21 and a plurality of second sub-pixels P22.
  • the plurality of first sub-pixels P21 are electrically connected to the first emission control line 141 of the plurality of emission control lines 14, and the plurality of second sub-pixels P22 are electrically connected to the second emission control line 142 of the plurality of emission control lines 14.
  • the first lighting control driving sub-circuit 221A1 of each lighting control driving unit 221 in the one or multi-level lighting control driving unit 221 includes a second input terminal IN2 of each lighting control driving unit 221.
  • the second input terminal IN2 is configured to receive a second input signal.
  • the second light emission control driving sub-circuit 221A2 of each light emission control driving unit 221 in the one or multi-level light emission control driving unit 221 includes a second output terminal OUT2 of each light emission control driving unit 221.
  • the second output terminal OUT2 is configured to output light emission control signals to the first light emission control line 141 and the second light emission control line 142.
  • the orthographic projection of at least one of the plurality of emission control driving sub-circuits 221A on the base substrate 11 and the second part of the plurality of sub-pixels 12 of the plurality of sub-pixels 12 The orthographic projection of the anode 1211 of the light-emitting element 121 on the base substrate 11 overlaps, and the orthographic projection of the anode 1211 of the light-emitting element 121 of the remaining sub-pixels of the plurality of sub-pixels 12 on the base substrate 11 does not overlap. In this way, the frame size of the display panel can be reduced without affecting the display uniformity as much as possible.
  • any one of the multi-level lighting control driving units 221 includes a plurality of lighting control driving sub-circuits 221A, the first lighting control driving sub-circuit 221A1 and The second light emission control driving sub-circuit 221A2 is separated in the first direction by the pixel driving circuit 122 of the second group of sub-pixels P2.
  • the first light-emission control driving sub-circuit 221A1 in any one-level light-emission control driving unit 221 is located in the first light-emission control driving unit 221 of the previous-level light-emission control driving unit 221 in a second direction different from the first direction.
  • the second light-emission control driving sub-circuit 221A2 in any one-level light-emission control driving unit 221 is located in the second direction in the second direction Between 221A2 and the second light-emission control driving sub-circuit 221A2 in the subsequent light-emission control driving unit 221 of any one-level light-emission control driving unit 221.
  • the second direction is perpendicular to the first direction.
  • the display panel further includes a second set of circuit connection lines.
  • the second group of circuit connection lines includes a fourth circuit connection line N4 and a fifth circuit connection line N5.
  • the second light-emission control driving sub-circuit 221A2 is electrically connected to the first light-emission control driving sub-circuit 221A1 via the fourth circuit connection line N4 and the fifth circuit connection line N5.
  • the orthographic projection of the fourth circuit connection line N4 and the fifth circuit connection line N5 on the base substrate 11 overlaps the orthographic projection of the pixel driving circuit 122 of the second group of sub-pixels P2 on the base substrate 11.
  • the first light emission control driving sub-circuit 221A1 includes a first group of transistors GT1, a second capacitor C2, a first power line VGL configured to receive a first power voltage, and a first power line VGL configured to receive a second power voltage.
  • the second power supply line VGH, the second light emission control driving sub-circuit 221A2 includes a second group of transistors GT2, a first capacitor C1, a third capacitor C3, a first clock signal line ECK configured to receive the first clock signal, and a first clock signal line ECK configured to receive the first clock signal.
  • the second clock signal line ECB that receives the second clock signal.
  • the number of the first group of transistors GT1 is smaller than the number of the second group of transistors GT2, and the aspect ratio of the channel of at least one transistor in the first group of transistors GT1 is larger than the channel of each transistor in the second group of transistors GT2.
  • the width to length ratio of the road In some embodiments, the aspect ratio of the channel of each transistor in the first group of transistors GT1 is greater than the aspect ratio of the channel of each transistor in the second group of transistors GT2.
  • the number and size of the transistors in the first light-emission control driving sub-circuit 221A1 and the second light-emission control driving sub-circuit 221A2 are comprehensively considered, so that the first light-emission control driving sub-circuit 221A1 and the second light-emission control driving sub-circuit 221A2
  • the occupied space is relatively close.
  • the second light emission control driving sub-circuit 221A2 may further include a power supply line configured to receive the first power supply voltage and the second power supply voltage.
  • the second light emission control driving sub-circuit 221A2 may further include a third power supply line VGL' configured to receive the first power supply voltage and a fourth power supply line VGH' configured to receive the second power supply voltage.
  • the second light emission control driving sub-circuit 221A2 may not include a power supply line configured to receive the first power supply voltage and the second power supply voltage.
  • the second light-emission control driving sub-circuit 221A2 may be electrically connected to the first power line VGL and the second power line VGH in the first light-emission control driving sub-circuit 221A1 through a circuit connection line.
  • the first light-emission control driving sub-circuit 221A1 includes a first sub-circuit 221A11 and a second sub-circuit 221A12
  • the second light-emission control driving sub-circuit 221A2 includes a third sub-circuit 221A21 and a fourth sub-circuit 221A22.
  • the following describes some specific implementations of the first sub-circuit 221A11, the second sub-circuit 221A12, the third sub-circuit 221A21, and the fourth sub-circuit 221A22.
  • the first sub-circuit 221A11 is located on the side of the first light-emitting control line 141 away from the second light-emitting control line 142, and the second sub-circuit 221A12 is located between the first light-emitting control line 141 and the second light-emitting control line 142 .
  • the first sub-circuit 221A11 includes a first sub-group of transistors GT11, and the first sub-group of transistors GT11 includes at least one transistor in the first group of transistors GT1.
  • the second sub-circuit 221A12 includes a second sub-group of transistors GT12 and a second capacitor C2, and the second sub-group of transistors GT12 includes other transistors in the first group of transistors GT1 except for the first sub-group of transistors GT11.
  • the third sub-circuit 221A21 is located on a side of the first light-emitting control line 141 away from the second light-emitting control line 142, and is electrically connected to the first sub-circuit 221A11 via the fourth circuit connection line N4.
  • the fourth sub-circuit 221A22 is located between the first light-emitting control line 141 and the second light-emitting control line 142, and is electrically connected to the second sub-circuit 221A12 via the fifth circuit connection line N5.
  • the third sub-circuit 221A21 includes a third sub-group of transistors GT21, and the third sub-group of transistors GT21 includes at least one transistor in the second group of transistors GT2.
  • the fourth sub-circuit 221A22 includes a fourth sub-group of transistors GT22 and a first capacitor C1, and the fourth sub-group of transistors GT22 includes other transistors in the second group of transistors GT2 except for the first sub-group of transistors GT11.
  • one of the third sub-circuit 221A21 and the fourth sub-circuit 221A22 further includes a third capacitor C3.
  • a third capacitor C3 the following will be introduced in combination with different embodiments.
  • FIG. 12 is a schematic circuit diagram showing a light emission control driving unit according to an embodiment of the present disclosure.
  • the third sub-circuit 221A21 further includes a third capacitor C3.
  • the second light emission control driving sub-circuit 221A2 further includes a third power supply line VGL' configured to receive the first power supply voltage and a fourth power supply line VGH' configured to receive the second power supply voltage.
  • the second group of transistors GT2 is located on the left side of the line L1, and the first group of transistors GT1 is located on the right side of the line L1.
  • the second group of transistors GT2 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • the first group of transistors GT1 includes a ninth transistor T9 and a tenth transistor T10.
  • the first sub-group of transistors GT11 is located on the right side of line L1 and the lower side of line L2
  • the second sub-group of transistors GT12 is located on the right side of line L1 and the upper side of line L2
  • the third sub-group of transistors GT21 is located on the left side of line L1.
  • the fourth sub-group transistor GT22 is located on the left side of the line L1 and on the right side of the line L2.
  • the first sub-group of transistors GT11 includes a tenth transistor T10
  • the second sub-group of transistors GT12 includes a ninth transistor T9
  • the third sub-group of transistors GT21 includes a first transistor T1, a second transistor T2, and a fifth transistor T5.
  • the fourth sub-group The transistor GT22 includes a third transistor T3, a fourth transistor T4, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • Each transistor in the first group of transistors GT1 and the second group of transistors GT2 includes a gate and an active layer.
  • the active layer includes a first electrode area, a second electrode area, and a second electrode area located between the first electrode area and the second electrode area. Between the channels.
  • the material of the active layer may include, for example, polysilicon, such as low-temperature polysilicon.
  • the first transistor T1 includes a gate electrode T10 and an active layer, and the active layer includes a first electrode region T11, a second electrode region T12, and a channel T13 between the first electrode region T11 and the second electrode region T12. , And so on.
  • the active layer of the transistors T2-T10 sequentially includes a channel T23, a channel T33, a channel T43, a channel T53, a channel T63, a channel T73, a channel T83, a channel T93, and a channel T103.
  • the gate T10 of the first transistor T1 is electrically connected to the first clock signal line CK, and the first electrode area T11 of the first transistor T1 serves as the second input terminal IN2.
  • the first electrode area T11 of the first transistor T1 may be electrically connected to the second input electrode 33 to receive the second input signal.
  • the gate T20 of the second transistor T2 is electrically connected to the second electrode area T12 of the first transistor T1, and the first electrode area T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1.
  • the gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1 via the connection electrode 64 shown in FIG. 10C.
  • the first electrode region T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1 via the connection electrode 65 shown in FIG. 10C.
  • the gate T30 of the third transistor T3 is electrically connected to the second electrode area T22 of the second transistor T2, and the first electrode area T31 of the third transistor T3 is electrically connected to the fourth power line VGH'.
  • the gate T30 of the third transistor T3 is electrically connected to the second electrode region T22 of the second transistor T2 via the connection electrode 66 shown in FIG. 10C.
  • the gate T40 of the fourth transistor T4 is electrically connected to the second clock signal line ECB
  • the first electrode area T41 of the fourth transistor T4 is electrically connected to the second electrode area T32 of the third transistor T3
  • the region T42 is electrically connected to the gate T20 of the second transistor T2.
  • the second electrode region T42 of the fourth transistor T4 is electrically connected to the gate T20 of the second transistor T2 via the connection electrode 64 shown in FIG. 10C.
  • the gate T50 of the fifth transistor T5 is electrically connected to the gate T10 of the first transistor T1, the first electrode area T51 of the fifth transistor T5 is electrically connected to the third power line VGL′, and the second electrode area T52 of the fifth transistor T5 It is electrically connected to the second electrode region T22 of the second transistor T2.
  • the gate T50 of the fifth transistor T5 and the gate T10 of the first transistor T1 are integrally provided.
  • the second electrode region T52 of the fifth transistor T5 is electrically connected to the second electrode region T22 of the second transistor T2 via the connection electrode 66 shown in FIG. 10C.
  • the gate T60 of the sixth transistor T6 is electrically connected to the gate T30 of the third transistor T3, and the first electrode region T61 of the sixth transistor T6 is electrically connected to the gate T40 of the fourth transistor T4.
  • the gate T60 of the sixth transistor T6 and the gate T30 of the third transistor T3 are integrally provided.
  • the first electrode region T61 of the sixth transistor T6 is electrically connected to the gate T40 of the fourth transistor T4 via the connection electrode 67 shown in FIG. 10C.
  • the gate T70 of the seventh transistor T7 is electrically connected to the gate T40 of the fourth transistor T4.
  • the gate T70 of the seventh transistor T7 and the gate T40 of the fourth transistor T4 are integrally provided.
  • the first electrode area T81 of the eighth transistor T8 is electrically connected to the fourth power line VGH', and the second electrode area T82 of the eighth transistor T8 is electrically connected to the second electrode area T72 of the seventh transistor T7.
  • the second electrode region T82 of the eighth transistor T8 is electrically connected to the second electrode region T72 of the seventh transistor T7 via the connection electrode 68 shown in FIG. 10C.
  • the gate T90 of the ninth transistor T9 is electrically connected to the second electrode area T72 of the seventh transistor T7 via the fifth circuit connection line N5, and the first electrode area T91 of the ninth transistor T9 is electrically connected to the second power line VGH.
  • the second electrode area T92 of the transistor T9 serves as the second output terminal OUT2.
  • the second electrode area T92 of the ninth transistor T9 is electrically connected to the first light emitting control line 141 and the second light emitting control line 142 via the second output electrode 34.
  • the gate T90 of the ninth transistor T9 is electrically connected to the fifth circuit connection line N5 via the connection electrode 69 shown in FIG. 10C, and the fifth circuit connection line N5 is electrically connected to the seventh transistor via the connection electrode 68 shown in FIG. 10C.
  • the second electrode area T72 of T7 is electrically connected to the second electrode area T72 of the seventh transistor T7 via the fifth circuit connection line N5, and the first electrode area T91 of the ninth transistor T9 is electrically connected to the second power line VGH.
  • the first electrode area T101 of the tenth transistor T10 is electrically connected to the second output electrode 34, and the second electrode area T102 of the tenth transistor T10 is electrically connected to the first power line VGL.
  • the first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T30 of the third transistor T3 and the gate T60 of the sixth transistor T6, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the second electrode of the sixth transistor T6.
  • the first electrode plate C11 of the first capacitor C1, the gate T30 of the third transistor T3 and the gate T60 of the sixth transistor T6 are integrally arranged.
  • the second electrode plate C12 of the first capacitor C1 is electrically connected to the second electrode region T62 of the sixth transistor T6 via the connection electrode 70 shown in FIG. 10C, and is electrically connected to the seventh electrode region T6 via the connection electrode 71 shown in FIG.
  • the first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T90 of the ninth transistor T9, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power line VGH.
  • the first electrode plate C21 of the second capacitor C2 and the gate T90 of the ninth transistor T9 are integrally provided.
  • the first electrode plate C31 of the third capacitor C3 is electrically connected to the gate T20 of the second transistor T2, the gate T80 of the eighth transistor T8 and the gate T100 of the tenth transistor T10, and the second electrode plate C32 of the third capacitor C3 It is electrically connected to the gate T40 of the fourth transistor T4.
  • the first electrode plate C31 of the third capacitor C3 and the gate T20 of the second transistor T2 are integrally provided.
  • the first electrode plate C31 of the third capacitor C3 is electrically connected to the fourth circuit connection line N4 and the gate T80 of the eighth transistor T8 via the connection electrode 72 shown in FIG. 10C, and the fourth circuit connection line N4 is via the connection electrode 72 shown in FIG.
  • the illustrated connecting electrode 73 is electrically connected to the gate T100 of the tenth transistor T10.
  • the second electrode plate C32 of the third capacitor C3 is electrically connected to the gate T40 of the fourth transistor T4 via the connection electrode 67 shown in FIG. 10C.
  • FIG. 13A to 13F are schematic diagrams showing the layout of different layers in the light emission control driving unit according to other implementations of the present disclosure.
  • FIG. 14A is an enlarged schematic diagram of 221A2 shown in FIG. 13A.
  • FIG. 14B is an enlarged schematic diagram of 221A1 shown in FIG. 13A.
  • the second group of circuit connection lines includes a fourth circuit connection line N4 and a fifth circuit connection line N5, a sixth circuit connection line N6, and a seventh circuit connection line N7.
  • the first light-emission control driving sub-circuit 221A1 includes a first sub-circuit 221A11 and a second sub-circuit 221A12
  • the second light-emission control driving sub-circuit 221A2 includes a third sub-circuit 221A21 and a fourth sub-circuit 221A22.
  • the third sub-circuit 221A21 is electrically connected to the first power supply line VGL via the sixth circuit connection line N6, and the third sub-circuit 221A21 is electrically connected to the second power supply line VGH via the seventh circuit connection line N7.
  • the second light-emitting control driving sub-circuit 221A2 may not include the third power line VGL' and the fourth power line VGH', thereby reducing the space occupied by the second light-emitting control driving sub-circuit 221A2, thereby reducing the light emission control Space occupied by the drive unit 221.
  • FIG. 15 is a schematic circuit diagram showing a light emission control driving unit according to another embodiment of the present disclosure.
  • the fourth sub-circuit 221A22 further includes a third capacitor C3.
  • the second group of transistors GT2 is located on the left side of the line L1, and the first group of transistors GT1 is located on the right side of the line L1.
  • the second group of transistors GT2 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • the first group of transistors GT1 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10
  • the first sub-group of transistors GT11 is located on the right side of line L1 and the lower side of line L2
  • the second sub-group of transistors GT12 is located on the right side of line L1 and the upper side of line L2
  • the third sub-group of transistors GT21 is located on the left side of line L1
  • the fourth sub-group transistor GT22 is located on the left side of the line L1 and on the right side of the line L2.
  • the first sub-group of transistors GT11 includes a tenth transistor T10
  • the second sub-group of transistors GT12 includes an eighth transistor T8 and a ninth transistor T9
  • the third sub-group of transistors GT21 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the fourth transistor T4 and the fifth transistor T5 the fourth sub-group of transistors GT22 includes a sixth transistor T6 and a seventh transistor T7.
  • each transistor in the first group of transistors GT1 and the second group of transistors GT2 includes a gate and an active layer.
  • the active layer includes a first electrode area, a second electrode area, and a channel located between the first electrode area and the second electrode area.
  • the first transistor T1 includes a gate electrode T10 and an active layer
  • the active layer includes a first electrode region T11, a second electrode region T12, and a channel T13 between the first electrode region T11 and the second electrode region T12. , And so on.
  • the active layer of the transistors T2-T10 sequentially includes a channel T23, a channel T33, a channel T43, a channel T53, a channel T63, a channel T73, a channel T83, a channel T93, and a channel T103.
  • the gate T10 of the first transistor T1 is electrically connected to the first clock signal line ECK, and the first electrode area T11 of the first transistor T1 serves as the second input terminal IN2.
  • the second input terminal IN2 is electrically connected to the second input electrode 35 to receive the second input signal.
  • the gate T20 of the second transistor T2 is electrically connected to the second electrode area T12 of the first transistor T1, and the first electrode area T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1.
  • the gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1 via the connection electrode 74 shown in FIG. 13C.
  • the first electrode region T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1 via the connection electrode 75 shown in FIG. 13C.
  • the gate of the third transistor T3 is electrically connected to the second electrode area T22 of the second transistor T2, and the first electrode area T31 of the third transistor T3 is electrically connected to the second power supply line VGH via the seventh circuit connection line N7.
  • the gate of the third transistor T3 is electrically connected to the second electrode region T22 of the second transistor T2 via the connection electrode 76 shown in FIG. 13C.
  • the first electrode region T31 of the third transistor T3 is electrically connected to the seventh circuit connection line N7 via the connection electrode 77 shown in FIG. 13C, and the seventh circuit connection line N7 is electrically connected to the second power supply line VGH via a via hole.
  • the gate T40 of the fourth transistor T4 is electrically connected to the second clock signal line ECB
  • the first electrode area T41 of the fourth transistor T4 is electrically connected to the second electrode area T32 of the third transistor T3
  • the second electrode of the fourth transistor T4 The region T42 is electrically connected to the gate T20 of the second transistor T2.
  • the first electrode area T41 of the fourth transistor T4 and the second electrode area T32 of the third transistor T3 are integrally provided.
  • the second electrode area T42 of the fourth transistor T4 is electrically connected to the gate T20 of the second transistor T2 via the connection electrode 78 shown in FIG. 13C.
  • the gate T50 of the fifth transistor T5 is electrically connected to the gate T10 of the first transistor T1, the first electrode area T51 of the fifth transistor T5 is electrically connected to the first power line VGL via the sixth circuit connection line N6, and the fifth transistor T5
  • the second electrode area T52 of the second transistor is electrically connected to the second electrode area T22 of the second transistor T2.
  • the gate T50 of the fifth transistor T5 and the gate T10 of the first transistor T1 are integrally provided.
  • the first electrode area T51 of the fifth transistor T5 is electrically connected to the sixth circuit connection line N6 via the connection electrode 79 shown in FIG. 13C
  • the sixth circuit connection line N6 is electrically connected to the first power supply line VGL via a via hole.
  • the second electrode region T52 of the fifth transistor T5 is electrically connected to the second electrode region T22 of the second transistor T2 via the connection electrode 76 shown in FIG. 13C.
  • the gate T60 of the sixth transistor T6 is electrically connected to the gate T30 of the third transistor T3.
  • the gate T60 of the sixth transistor T6 is electrically connected to the gate T30 of the third transistor T3 via the connection electrode 76 shown in FIG. 13C.
  • the gate T70 of the seventh transistor T7 is electrically connected to the first electrode area T61 of the sixth transistor T6 and the second clock signal line ECB, and the first electrode area T61 of the seventh transistor T7 is electrically connected to the second electrode of the sixth transistor T6 Area T61.
  • the gate T70 of the seventh transistor T7 is electrically connected to the first electrode region T61 of the sixth transistor T6 via the connection electrode 84 shown in FIG. 13C.
  • the second electrode region T71 of the seventh transistor T7 is electrically connected to the first electrode region T61 of the sixth transistor T6 via the connection electrode 80 shown in FIG. 13C.
  • the gate T80 of the eighth transistor T8 is electrically connected to the gate T20 of the second transistor T2 via the fourth circuit connection line N4, the first electrode area T81 of the eighth transistor T8 is electrically connected to the second power supply line VGH, and the eighth transistor T8
  • the second electrode area T82 of the T82 is electrically connected to the second electrode area T72 of the seventh transistor T7 via the fifth circuit connection line N5.
  • the gate T80 of the eighth transistor T8 and the fourth circuit connection line N4 are integrally provided.
  • the fourth circuit connection line N4 is electrically connected to the gate T20 of the second transistor T2 via the connection electrode 78 shown in FIG. 13C.
  • the second electrode area T82 of the eighth transistor T8 is electrically connected to the fifth circuit connection line N5 via the connection electrode 81 shown in FIG. 13C
  • the fifth circuit connection line N5 is electrically connected to the fifth circuit connection line N5 via the connection electrode 82 shown in FIG. 13C.
  • the second electrode area T72 of the seven transistor T7 is electrically connected to the fifth circuit connection line N5 via the connection electrode 82 shown in FIG. 13C.
  • the gate T90 of the ninth transistor T9 is electrically connected to the second electrode area T72 of the seventh transistor T7 via the fifth circuit connection line N5, and the first electrode area T91 of the ninth transistor T9 is electrically connected to the second power line VGH.
  • the second electrode area T92 of the transistor T9 is electrically connected to the first light emission control line 141 and the second light emission control line 142 via the second output electrode 36.
  • the gate T100 of the tenth transistor T10 is electrically connected to the gate T20 of the second transistor T2 via the fourth circuit connection line N4, the first electrode area T11 of the tenth transistor T10 is electrically connected to the second output electrode 36, and the tenth transistor T10
  • the second electrode area T12 is electrically connected to the first power line VGL.
  • the gate T100 of the tenth transistor T10 is electrically connected to the fourth circuit connection line N4 via the connection electrode 83 shown in FIG. 13C.
  • the first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T60 of the sixth transistor T6, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the first electrode area T61 of the sixth transistor T6 and the seventh transistor T7
  • the first electrode area T71 For example, the first electrode plate C11 of the first capacitor C1 and the gate T60 of the sixth transistor T6 are integrally provided.
  • the second electrode plate C12 of the first capacitor C1 is electrically connected to the first electrode region T61 of the sixth transistor T6 and the first electrode region T71 of the seventh transistor T7 via the connection electrode 80 shown in FIG. 13C.
  • the first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T90 of the ninth transistor T9, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power line VGH.
  • the first electrode plate C21 of the second capacitor C2 and the gate T90 of the ninth transistor T9 are integrally provided.
  • the first electrode plate C31 of the third capacitor C3 is electrically connected to the gate T70 of the seventh transistor T7, and the second electrode plate C32 of the third capacitor C3 is electrically connected to the fourth circuit connection line N4.
  • the first electrode plate C31 of the third capacitor C3 and the gate T70 of the seventh transistor T7 are integrally provided.
  • the second electrode plate C32 of the third capacitor C3 is electrically connected to the fourth circuit connection line N4 via the connection electrode 78 shown in FIG. 13C.
  • the gate driving unit 211 and the light emission control driving unit 221 can be split in the manner described above.
  • circuit connection lines between different sub-circuits may adversely affect the sub-pixel 12.
  • the circuit connection line may overlap with the active layer in the pixel driving circuit 122 to form a transistor, thereby affecting the normal display of the sub-pixel 12 and further affecting the display effect of the display panel.
  • FIG. 16A is a schematic diagram showing the distribution of multiple gate driving sub-circuits according to another embodiment of the present disclosure.
  • FIG. 16B is a schematic partial cross-sectional view showing a sub-pixel according to an embodiment of the present disclosure.
  • the display panel includes a base substrate 11, a plurality of sub-pixels 12, a plurality of gate lines 13, a plurality of light-emitting control lines 14, a gate driving circuit 21 and a gate driver Circuit connection line 23.
  • the base substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111.
  • a plurality of sub-pixels 12 are located in the display area 111.
  • Each sub-pixel 12 includes a light-emitting element 121 and a pixel driving circuit 122 configured to drive the light-emitting element 121.
  • the plurality of gate lines 13 are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12.
  • the gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211.
  • the multi-stage gate driving unit 211 is electrically connected to the plurality of gate lines 13.
  • the multi-stage gate driving unit 211 is electrically connected to the plurality of gate lines 13 in a one-to-one correspondence.
  • the one-stage or multi-stage gate drive unit 211 in the multi-stage gate drive circuit 211 includes a plurality of gate drive sub-circuits 211A.
  • the plurality of gate driving sub-circuits 211A includes a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2.
  • the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are composed of a plurality of sub-pixels 12
  • the pixel driving circuits 122 of the first group of sub-pixels P1 are spaced apart.
  • the gate driving sub-circuit connection line 23 is located in the display area 111. One end of the gate driving sub-circuit connection line 23 is electrically connected to the first gate driving sub-circuit 211A1, and the other end of the gate driving sub-circuit connection line 23 is electrically connected to the second gate driving sub-circuit 211A2.
  • the pixel driving circuit 122 of at least one sub-pixel 12 in the first group of sub-pixels P1 includes a first pixel driving sub-circuit 122A and a second pixel driving sub-circuit 122B.
  • the first pixel driving sub-circuit 122A is located on the side of the gate driving sub-circuit connecting line 23, and the second pixel driving sub-circuit 122B is located on the side of the gate driving sub-circuit connecting line 23 away from the first pixel driving sub-circuit 122A.
  • the first pixel driving sub-circuit 122A includes a driving transistor M3, such as the driving transistor M3 shown in FIG. 1B.
  • the driving transistor M3 includes a first active layer M34 on one side of the base substrate 11.
  • the material of the first active layer M34 includes semiconductor materials such as polysilicon.
  • One end of the connecting member 122C is electrically connected to the first pixel driving sub-circuit 122A, and the other end of the connecting member 122C is electrically connected to the second pixel driving sub-circuit 122A2.
  • the orthographic projection of the connecting member 122C on the base substrate 11 overlaps the orthographic projection of the gate driving sub-circuit connection line 23 on the base substrate 11, and the connecting member 122C and the first active layer T14 are located on different layers.
  • connection member 122C is different from the material of the first active layer M34.
  • the connecting member 122C and the first active layer M34 are located in different layers, and no transistor is formed between the gate driving sub-circuit connecting line 23 and the connecting member 122C. Therefore, at least the problem of a decrease in the display effect of the display panel caused by the formation of a transistor between the gate driving sub-circuit connecting line 23 and the connecting member 122C is alleviated.
  • the driving transistor M3 further includes a first gate M30 located on the side of the first active layer M34 away from the base substrate 11, and a first gate M30 located at the side of the first gate M30 away from the base substrate 11.
  • the driving transistor M3 further includes a gate dielectric layer 122 located on a side of the first active layer M34 away from the base substrate 11, and the first gate M30 is located on a side of the gate dielectric layer 122 away from the base substrate 11. side.
  • the first electrode M3A and the second electrode M3B are electrically connected to the first active layer M34 through via holes penetrating the second insulating layer 124, the first insulating layer 123, and the gate dielectric layer 122, respectively.
  • FIG. 16B also shows the light-emitting element 121.
  • the light emitting element 121 includes an anode 1211, a functional layer 1212 located on the side of the anode 1211 away from the base substrate 11, and a cathode 1213 located on the side of the functional layer 1212 away from the base substrate 11.
  • the anode 1211 of the light emitting element 121 is electrically connected to the first electrode M3A of the driving transistor M3.
  • the functional layer 1212 includes at least a light-emitting layer, for example, an organic light-emitting layer.
  • the functional layer 1212 may further include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.
  • the sub-pixel 12 may further include a buffer layer 120 between the base substrate 11 and the first active layer M34, and a planarization layer 125 covering the first electrode M3A and the second electrode M3B.
  • the anode 1211 of the light emitting element 121 may be electrically connected to the first electrode M3A of the driving transistor M3 through a via hole penetrating the planarization layer 125.
  • the pixel defining layer 126 has a plurality of openings corresponding to the plurality of sub-pixels 12, and the light-emitting elements 121 of the plurality of sub-pixels 12 are located in the plurality of openings.
  • the encapsulation layer 128 may include a thin film encapsulation layer.
  • the encapsulation layer 128 may include a first inorganic layer 1281, a second inorganic layer 1282, and an organic layer 1283 located between the first inorganic layer 1281 and the second inorganic layer 1282.
  • one or more of the second insulating layer 125, the first insulating layer 124, the gate dielectric layer 122, the buffer layer 120, the planarization layer 125, the pixel defining layer 126, and the support layer 127 may include, for example, Organic insulating materials such as polyimide and resin materials, or inorganic insulating materials including silicon oxide, silicon nitride, and silicon oxynitride.
  • the first pixel driving sub-circuit 122A further includes a storage capacitor Cst.
  • the storage capacitor Cst includes a first electrode plate Cst1 located on the same layer as the first gate electrode M30, and a second electrode plate Cst2 located between the first insulating layer 123 and the second insulating layer 124. It should be understood that the storage capacitor Cst further includes a first insulating layer 123 located between the first electrode plate Cst1 and the second electrode plate Cst2.
  • the gate driving sub-circuit connection line 23 and the first gate M30 are located on the same layer, and at least one of the second electrode plate Cst2, the first electrode M3A, and the second electrode M3B is located on the same layer as the connecting member 122C.
  • at least the first insulating layer 123 is provided between the gate driving sub-circuit connecting wire 23 and the connecting member 122C.
  • the gate driving sub-circuit connection line 23 and the first gate M30 are located on the same layer, and the second electrode plate Cst2 and the connecting member 122C are located on the same layer.
  • the first insulating layer 123 is provided between the gate driving sub-circuit connection line 23 and the connecting member 122C, which reduces the adverse effect of the gate driving sub-circuit connection line 23 on the sub-pixel 12.
  • the gate driving sub-circuit connection line 23 and the first gate M30 are located on the same layer, and the first electrode M3A, the second electrode M3B, and the connecting member 122C are located on the same layer.
  • the first insulating layer 123 and the second insulating layer 124 are arranged between the gate driving sub-circuit connecting line 23 and the connecting member 122C, which further reduces the impact of the gate driving sub-circuit connecting line 23 on the sub-pixel 12 Negative Effects.
  • the gate driving sub-circuit connection line 23 may be the second circuit connection line shown in FIG. 4A N2.
  • the second circuit connection line N2 shown in FIG. 4A is located on the same layer as the first gate M30 shown in FIG. 16B, the connection member 122C shown in FIG.
  • the electrode M3B is located on the same layer.
  • the first circuit connection line N1 shown in FIG. 4A is located on the same layer as the first gate M30 shown in FIG.
  • the first electrode M3A and the second electrode M3B shown in 16B are located on the same layer.
  • the gate driving sub-circuit connection line 23 may be the first circuit connection line shown in FIG. 7A N1.
  • the first circuit connection line N1 shown in FIG. 7A is located on the same layer as the first gate M30 shown in FIG. 16B
  • the electrode M3B is located on the same layer.
  • the second circuit connection line N2 and the third circuit connection line N3 shown in FIG. 7A are located on the same layer as the first gate M30 shown in FIG. 16B, and cross the second circuit connection line N2.
  • the overlapping connecting member 122C and the connecting member 122C overlapping the third circuit connecting line N3 are located on the same layer as the first electrode M3A and the second electrode M3B shown in FIG. 16B.
  • FIG. 17A is a schematic diagram showing the layout of the gate driving sub-circuit connection line and the connection member overlapped according to an embodiment of the present disclosure.
  • Fig. 17B is a schematic cross-sectional view taken along A-A' shown in Fig. 17A.
  • the first pixel driving sub-circuit 122A, the second pixel driving sub-circuit 122B, and the connector 122C form a certain sub-pixel 12 in the first group of sub-pixels P1.
  • One end of the connector 122C is electrically connected to the first pixel driving sub-circuit 122A through the via VC1
  • the other end of the connector 122C is electrically connected to the second pixel driving sub-circuit 122B through the via VC2.
  • the gate driving sub-circuit connection line 23 is located on the same layer as the first gate electrode T10 shown in FIG. 16B, and the connecting member 122C is located on the same layer as the first electrode T1A and the second electrode T1B shown in FIG. 16B .
  • At least one sub-pixel 12 further includes a shielding layer 129.
  • the shielding layer 129 may be electrically connected to the power line 16 via a via V161.
  • the shielding layer 129 may be located on the same layer as the second electrode plate Cst2 shown in FIG. 16B.
  • the orthographic projection of the connecting member 122C and the gate driving sub-circuit connection line 23 on the base substrate 11 and the orthographic projection of the shielding layer 129 on the base substrate 11 at least partially overlap. In this manner, the shielding layer 129 can reduce the mutual influence between the gate driving sub-circuit connecting line 23 and the connecting member 122C.
  • the overlapping part of the orthographic projection of the connector 122C on the base substrate 11 and the orthographic projection of the gate drive sub-circuit connection line 23 on the base substrate 11 is located on the shielding layer 129 on the base substrate 11. Within the orthographic projection. In this manner, the shielding layer 129 can more effectively reduce the mutual influence between the gate driving sub-circuit connecting line 23 and the connecting member 122C.
  • FIG. 18 is a schematic diagram showing the distribution of multiple light emission control driving sub-circuits according to another embodiment of the present disclosure.
  • the display panel further includes a light-emission control driving circuit 22 and a light-emission control driving sub-circuit connection line 24 located in the display area 111.
  • the light emitting control driving circuit 22 includes a cascaded multi-level light emitting control driving unit 221 electrically connected to a plurality of light emitting control lines 14. As shown in FIG. 18, the one-stage or multi-stage lighting control driving unit 221 in the multi-stage lighting control driving unit 221 includes a plurality of lighting control driving sub-circuits 221A.
  • the plurality of emission control driving sub-circuits 221A includes a first emission control driving sub-circuit 221A1 and a second emission control driving sub-circuit 221A2.
  • the first emission control driving sub-circuit 221A1 and the second emission control driving sub-circuit 221A2 are composed of a plurality of sub-pixels 12
  • the pixel driving circuits 122 of the second group of sub-pixels P2 are spaced apart.
  • One end of the lighting control driving sub-circuit connection line 24 is electrically connected to the first lighting control driving sub-circuit 221A1, and the other end of the lighting control driving sub-circuit connection line 24 is electrically connected to the second lighting control driving sub-circuit 221A2.
  • the pixel driving circuit 122 of at least one sub-pixel 12 in the second group of sub-pixels P2 includes a first pixel driving sub-circuit 122A and a second pixel driving sub-circuit 122B.
  • the first pixel driving sub-circuit 122A is located on the side of the light-emission control driving sub-circuit connecting line 24, and the second pixel driving sub-circuit 122B is located on the side of the light-emitting control driving sub-circuit connecting line 24 away from the first pixel driving sub-circuit 122A.
  • One end of the connecting member 122C is electrically connected to the first pixel driving sub-circuit 122A, and the other end of the connecting member 122C is electrically connected to the second pixel driving sub-circuit 122B.
  • the orthographic projection of the connector 122C on the base substrate 11 overlaps the orthographic projection of the light-emitting control driving sub-circuit connection line 24 on the base substrate 11, and the connector 122C and the first active layer M34 are located on different layers.
  • the light-emission control driving sub-circuit connection line 24 is located on the same layer as the first gate M30 shown in FIG. 16B
  • the connecting member 122C is located on the same layer as the first electrode M3A and the second electrode M3B shown in FIG. 16B.
  • the foregoing embodiment can reduce the adverse effect of the light-emission control driving sub-circuit connection line 24 on the sub-pixel 12, and improve the display effect of the display panel.
  • the above-mentioned shielding layer 129 may be provided between the light-emission control driving sub-circuit connection line 24 and the connection member 122C to reduce the mutual influence between the light-emission control driving sub-circuit connection line 24 and the connection member 122C.
  • FIG. 19 is a schematic diagram showing the layout of some layers in a sub-pixel according to an embodiment of the present disclosure.
  • first pixel driving sub-circuit 122A and the second pixel driving sub-circuit 122B will be introduced in conjunction with FIG. 1B, FIG. 2 and FIG. 19.
  • the display panel further includes a plurality of light-emitting control lines 14, a plurality of power lines 16, a plurality of initialization lines 17, and a plurality of reset lines 18.
  • the multiple light-emitting control lines 14, the multiple power lines 16, the multiple initialization lines 17 and the multiple reset lines 18 are all located in the display area 111 and are electrically connected to the multiple sub-pixels 12.
  • the first pixel driving sub-circuit 122A is located on the right side of the line L
  • the second pixel driving sub-circuit 122B is located on the left side of the line L.
  • the first pixel driving sub-circuit 122A includes a driving transistor M3, a plurality of transistors MT, and a storage capacitor Cst, and the plurality of transistors MT includes a first light emission control transistor M6.
  • the driving transistor M3 includes a first gate M30 and a first active layer M34.
  • the storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2, and the first electrode plate Cst1 is electrically connected to one of the plurality of power lines 16.
  • the second pixel driving sub-circuit 122B includes a first reset transistor M7.
  • Each of the first reset transistor M7 and the plurality of transistors MT includes a second gate and a second active layer.
  • Each of the second active layer and the first active layer M34 includes a first electrode region, a second electrode region, and a channel between the first electrode region and the second electrode region.
  • the first active layer M34 of the driving transistor M3 includes a first electrode region M31, a second electrode region M32, and a channel M33 between the first electrode region M31 and the second electrode region M32.
  • the second active layer M64 of the first light emission control transistor M6 includes a first electrode region M61, a second electrode region M62, and a channel M63 between the first electrode region M61 and the second electrode region M62.
  • the second active layer M74 of the first reset transistor M7 includes a first electrode region M71, a second electrode region M72, and a channel M73 between the first electrode region M71 and the second electrode region M72.
  • the first gate M30 of the driving transistor M3 is electrically connected to the second electrode plate Cst2 of the storage capacitor Cst, and the first electrode area M31 of the driving transistor M3 is electrically connected to one of the plurality of power lines 16.
  • the second gate M60 of the first light emission control transistor M6 is electrically connected to one of the plurality of light emission control lines 14, and the first electrode area M61 of the first light emission control transistor M6 is electrically connected to the second electrode area M32 of the driving transistor M3.
  • the second electrode area M62 of a light emitting control transistor M6 is electrically connected to one end of the connector 122C.
  • the second gate M70 of the first reset transistor M7 is electrically connected to one of the plurality of reset lines 18, the first electrode region M71 of the first reset transistor M7 is electrically connected to one of the plurality of initialization lines 17, and the first reset transistor M7
  • the second electrode region M72 is electrically connected to the other end of the connector 122C.
  • the anode 1211 of the light-emitting element 121 of at least one sub-pixel 12 is electrically connected to one end of the connector 122C.
  • the display panel further includes a plurality of data lines 15.
  • the plurality of data lines 15 are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12. 1B, the plurality of transistors MT further include a data writing transistor M4, a second reset transistor M1, a second light emission control transistor M5, and a threshold compensation transistor M2.
  • the second gate M40 of the data writing transistor M4 is electrically connected to one of the plurality of gate lines 13 and the first electrode region M41 of the data writing transistor M4 is electrically connected to one of the plurality of data lines 15.
  • the second electrode region M42 of the writing transistor M4 is electrically connected to the first electrode region M31 of the driving transistor M3.
  • the second gate M10 of the second reset transistor M1 is electrically connected to the other one of the reset lines 18, the first electrode region M10 of the second reset transistor M1 is electrically connected to the second electrode plate Cst2 of the storage capacitor Cst, and the second reset The second electrode region M20 of the transistor M1 is electrically connected to another one of the plurality of initialization lines 17.
  • the second gate M10 of the second reset transistor M1 and the second gate M70 of the first reset transistor M7 are electrically connected to different reset lines 18.
  • the second electrode region M20 of the second reset transistor M1 and the first electrode region M71 of the first reset transistor M7 are electrically connected to different initialization lines 17.
  • the second gate M50 of the second light-emitting control transistor M5 is electrically connected to one of the multiple light-emitting control lines 14, the first electrode area M51 of the second light-emitting control transistor M5 is electrically connected to one of the multiple power lines 16, and the second light-emitting The second electrode region M52 of the control transistor M5 is electrically connected to the first electrode region M31 of the driving transistor M3.
  • the second gate M50 of the second light emission control transistor M5 and the second gate M60 of the first light emission control transistor M6 are electrically connected to the same light emission control line 14.
  • the second gate M20 of the threshold compensation transistor M2 is electrically connected to one of the plurality of gate lines 13
  • the first electrode region M21 of the threshold compensation transistor M2 is electrically connected to the first electrode region M11 of the second reset transistor M1
  • the second electrode region M22 of M2 is electrically connected to the second electrode region M32 of the driving transistor M3.
  • the second gate M20 of the threshold compensation transistor M2 and the second gate M40 of the data writing transistor M4 are electrically connected to the same gate line 13.
  • FIG. 20 is a schematic diagram showing cascaded two-stage gate driving units according to an embodiment of the present disclosure.
  • the one-stage or multi-stage gate driving unit 211 includes a previous-stage gate driving unit 211-1 and a subsequent-stage gate driving unit 211-2 that are cascaded.
  • the first gate driving sub-circuit 211A1 of the previous-stage gate driving unit 211-1 includes the first input terminal IN1 of the previous-stage gate driving unit 211-1, and the second input terminal IN1 of the previous-stage gate driving unit 211-1.
  • the gate driving sub-circuit 211A2 includes the first output terminal OUT1 of the gate driving unit 211-1 of the previous stage.
  • the first gate driving sub-circuit 211A1 of the latter-stage gate driving unit 211-2 includes the first input terminal IN1 of the latter-stage gate driving unit 211-2, and the second-stage gate driving unit 211-2.
  • the gate driving sub-circuit 211A2 includes the first output terminal OUT1 of the next-stage gate driving unit 211-2.
  • connection mode of the cascaded previous-stage gate driving unit 211-1 and the latter-stage gate driving unit 211-2 will be described below in conjunction with FIGS. 4A-4F.
  • the relatively upper gate driving unit is the previous-stage gate driving unit 211-1
  • the relatively lower gate driving unit is the next-stage gate driving unit 211-2.
  • the first output terminal OUT1 of the gate driving unit 211-1 of the previous stage is electrically connected to the first gate line 131 of the plurality of gate lines 13.
  • the first output terminal OUT1 of the gate driving unit 211-1 of the previous stage is electrically connected to the first gate line 131 via the output electrode 32.
  • the display panel further includes a first cascade connection line CC1, which is located on the side of the pixel driving circuit 122 of the first group of sub-pixels P1 away from the second gate driving sub-circuit 211A2.
  • One end of the first cascade connection line CC1 is electrically connected to the first gate line 131, and the other end of the first cascade connection line CC1 is electrically connected to the first input terminal IN1 of the next-stage gate driving unit 211-2.
  • one end of the first cascade connection line CC1 is electrically connected to the first gate line 131 through the first via VC1, and the other end of the first cascade connection line CC1 is electrically connected to the next level of gate line through the second via VC2.
  • the first input terminal IN1 of the pole driving unit 211-2 is electrically connected to the first gate line 131 through the first via VC1, and the other end of the first cascade connection line CC1 is electrically connected to the next level of gate line through the second via VC2.
  • the first gate line 131 laterally passes through the pixel driving circuit 122 of the first group of sub-pixels P1, and the first cascade connection line CC1 is electrically connected to the first gate line 131 and the next-stage gate driving unit The first input terminal IN1 of 211-2.
  • the space occupied by the gate drive circuit is reduced, which helps to improve the resolution of the display panel.
  • the display panel further includes a plurality of reset lines 18.
  • the multiple reset lines 18 are located in the display area 111 and are electrically connected to the multiple sub-pixels 12. 4B, the pixel driving circuit 122 of the first group of sub-pixels P1 between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 of the next-stage gate driving unit 121-2 is electrically connected to a plurality of
  • the first reset line 181 of the reset lines 18 is electrically connected to the first gate line 131 via the first cascade connection line CC1.
  • the first reset line 181 is electrically connected to the first cascade connection line CC1 via the third via VC3.
  • the display panel further includes a second cascade connection line CC2, which is located on the side of the first group of sub-pixels P1 away from the first gate driving sub-circuit 211A1.
  • One end of the second cascade connection line CC2 is electrically connected to the first gate line 131, and the other end of the second cascade connection line CC2 is electrically connected to the first reset line 181.
  • one end of the second cascade connection line CC2 is electrically connected to the first gate line 131 via a via VC4, and the other end of the second cascade connection line CC2 is electrically connected to the first reset line 181 via a via VC5.
  • the second cascade connection line CC2 and the first output electrode 32 are integrally provided. In this manner, it can be ensured that the gate driving signal on the first gate line 131 is input as the first input signal to the first input terminal IN1 of the gate driving unit 211-2 of the subsequent stage.
  • At least one of the first electrode M3A and the second electrode M3B of the driving transistor M3 and the first cascade connection line CC1 are located on the same layer. In some embodiments, at least one of the first electrode M3A and the second electrode M3B of the driving transistor M3 and the second cascade connection line CC2 are located on the same layer.
  • the inventor also noticed that when the multiple gate driving sub-circuits 211A are dispersed into the multiple sub-pixels 12, the space occupied by some sub-pixels 12 on both sides of the gate driving sub-circuit 211A needs to be compressed. In this case, some sub-pixels (such as multiple red sub-pixels, multiple green sub-pixels, or multiple blue sub-pixels) that are compressed in space and emit the same color have the problem of uneven display, which affects the display panel's performance. display effect.
  • some sub-pixels such as multiple red sub-pixels, multiple green sub-pixels, or multiple blue sub-pixels
  • FIG. 21 is a schematic diagram showing the distribution of multiple gate driving sub-circuits according to another embodiment of the present disclosure.
  • 22A-22E are schematic diagrams showing different sets of anode connection wires according to some embodiments of the present disclosure.
  • FIGS. 2, 21, and 22A-22E a display panel according to some embodiments of the present disclosure will be introduced with reference to FIGS. 2, 21, and 22A-22E.
  • the display panel includes a base substrate 11, a plurality of sub-pixels 12, a plurality of gate lines 13 and a gate driving circuit 21.
  • the base substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111.
  • a plurality of sub-pixels 12 are located in the display area 111.
  • the plurality of gate lines 13 are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12.
  • the gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211.
  • the multi-stage gate driving unit 211 is electrically connected to the plurality of gate lines 13.
  • the one-stage or multi-stage gate driving unit 211 in the multi-stage gate driving circuit 211 includes a plurality of gate driving sub-circuits 211A.
  • the plurality of gate driving sub-circuits 211A includes a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2.
  • the plurality of sub-pixels 12 includes a first group of sub-pixels P1 and a second group of sub-pixels P2.
  • the pixel driving circuit 122 of a group of sub-pixels in the first group of sub-pixels P1 and the second group of sub-pixels P2 is located between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2, and the first group of sub-pixels P1 and the pixel driving circuit 122 of the other group of sub-pixels in the second group of sub-pixels P2 are located on the side of the first gate driving sub-circuit 211A1 away from the second gate driving sub-circuit 211A2. It should be noted that FIG.
  • FIG. 21 schematically shows that the first group of sub-pixels P1 is located between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2, and the pixel driving in the second group of sub-pixels P2
  • the circuit 122 is located on the side of the first gate driving sub-circuit 211A1 away from the second gate driving sub-circuit 211A2.
  • the first group of sub-pixels P1 includes a first sub-group of sub-pixels P11 configured to emit light of a first color, a second sub-group of sub-pixels P12 configured to emit light of a second color, and The third sub-group of sub-pixels P13 emitting light of the third color.
  • the first color, the second color, and the third color are different from each other. For example, the first color is red, the second color is green, and the third color is blue.
  • the pixel driving circuit 122 of the first sub-group of sub-pixels P11 is electrically connected to the anodes P11-1211 of the light-emitting element 121 of the first sub-group of sub-pixels P11 via the first group of anode connection lines GC1, and the second sub-group of sub-pixels P12 is driven
  • the circuit 122 is electrically connected to the anodes P12-1211 of the light-emitting element 121 of the second sub-pixel P12 through the second group of anode connecting lines GC2, and the pixel driving circuit 122 of the third sub-group of sub-pixels P13 is electrically connected through the third group of anode connecting lines GC3.
  • the anode electrodes P13-1211 of the light-emitting element 121 of the third sub-group sub-pixel P13 are electrically connected.
  • At least one of the first group of anode connection wires GC1, the second group of anode connection wires GC2, and the third group of anode connection wires GC3 includes a plurality of first anode connection wires AC1.
  • each of the first group of anode connection wires GC1, the second group of anode connection wires GC2, and the third group of anode connection wires GC3 includes a plurality of first anode connection wires AC1.
  • the plurality of first anode connection lines AC1 includes two first anode connection lines AC1, and the closer to the first gate driving sub-circuit 211A1 of the two first anode connection lines AC1, the greater the length of the first anode connection line AC1 .
  • the closer to the first gate driving sub-circuit 211A1 the longer the length of the first anode connection line AC1. big.
  • the two first anode connection lines AC1 in at least one of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3 are closer to the first gate drive
  • the length of the first anode connection line AC1 of the sub-circuit 211A1 is greater.
  • At least one of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3 is closer to the first grid of the first anode connection lines AC1.
  • the length of the first anode connection line AC1 of the driving sub-circuit 211A1 is greater.
  • all of the first anode connection lines AC1 in at least one of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3 are closer to the first gate drive sub-circuit 211A1.
  • Such a structure helps to further improve the display uniformity of the first group of sub-pixels P1, thereby improving the display effect of the display panel.
  • At least one of the first group of anode connection wires GC1, the second group of anode connection wires GC2, and the third group of anode connection wires GC3 is located on the same layer as the anode 1211 of the light-emitting element 121.
  • Such a structure facilitates process realization and reduces process complexity.
  • the first group of anode connection lines GC1 and the anodes P11-1211 of the light-emitting elements 121 of the first sub-group of sub-pixels P11 are integrally arranged.
  • the second group of anode connection lines GC2 are integrally arranged with the anodes P12-1211 of the light-emitting elements 121 of the second sub-group of sub-pixels P12.
  • the third group of anode connection lines GC3 are integrally arranged with the anodes P13-1211 of the light-emitting element 121 of the third sub-group of sub-pixels P13.
  • the first group of anode connection lines GC1 are electrically connected to the pixel driving circuit 122 of the first sub-group of sub-pixels P11 via the first group of via holes VP1; the second group of anode connection lines GC2 are via the second group of via holes VP2.
  • the pixel driving circuit 122 of the second sub-group of sub-pixels P12 is electrically connected;
  • the third group anode connection line GC3 is electrically connected to the pixel driving circuit 122 of the third sub-group of sub-pixels P13 via the third group of via holes VP3.
  • the second group of sub-pixels P2 includes a fourth sub-group of sub-pixels P21 configured to emit light of a first color, a fifth sub-group of sub-pixels P22 configured to emit light of a second color, and The sixth sub-group of sub-pixels P23 that emit light of the third color.
  • the pixel driving circuit 122 of the fourth sub-group sub-pixel P21 is electrically connected to the anodes P21-1211 of the light-emitting element 121 of the fourth sub-group sub-pixel P21 via the fourth-group anode connection line GC4, and the pixel driving of the fifth sub-group sub-pixel P22
  • the circuit 122 is electrically connected to the anodes P22-1211 of the light-emitting element 121 of the fifth sub-pixel P22 through the fifth group of anode connection lines GC5, and the pixel driving circuit 122 of the sixth sub-group of sub-pixels P23 is electrically connected through the sixth group of anode connection lines GC6.
  • the anode electrodes P23-1211 of the light-emitting element 121 of the sixth sub-group sub-pixel P23 are electrically connected.
  • At least one of the fourth group of anode connection wires GC4, the fifth group of anode connection wires GC5, and the sixth group of anode connection wires GC6 includes a plurality of second anode connection wires AC2, and the closer the plurality of second anode connection wires AC2 are to the first The length of the second anode connection line of the gate driving sub-circuit 211A1 is greater.
  • each of the fourth group of anode connection wires GC4, the fifth group of anode connection wires GC5, and the sixth group of anode connection wires GC6 includes a plurality of second anode connection wires AC2, and the plurality of second anode connection wires AC2
  • the length of the second anode connection line closer to the first gate driving sub-circuit 211A1 is greater.
  • the plurality of sub-pixels 12 further include a third group of sub-pixels P3 and a fourth group of sub-pixels P4.
  • the pixel driving circuit 122 of a group of sub-pixels in the third group of sub-pixels P3 and the fourth group of sub-pixels P4 is located in the second gate driving sub-circuit 211A2 close to the first gate driving sub-circuit 211A1, the first group of sub-pixels P1 and On one side of the second group of sub-pixels P2, the pixel driving circuit 122 of the other group of sub-pixels is located on the side of the second gate driving sub-circuit 211A2 away from the first gate driving sub-circuit 211A1.
  • the pixel driving circuit 122 of the fourth group of sub-pixels P4 is located in the second gate driving sub-circuit 211A2 close to the first gate driving sub-circuit 211A1, the first group of sub-pixels P1, and the second group of sub-pixels P1.
  • the pixel driving circuit 122 of the third group of sub-pixels P3 is located on the side of the second gate driving sub-circuit 211A2 away from the first gate driving sub-circuit 211A1.
  • the third group of sub-pixels P3 includes a seventh sub-group of sub-pixels P31 configured to emit light of a first color, an eighth sub-group of sub-pixels P32 configured to emit light of a second color, and The ninth sub-group of sub-pixels P33 that emit light of the third color.
  • the pixel driving circuit 122 of the seventh sub-group of sub-pixels P31 is electrically connected to the anodes P31-1211 of the light-emitting element 121 of the seventh sub-group of sub-pixels P31 via the seventh-group anode connection line GC7, and the pixel driving of the eighth sub-group of sub-pixels P32
  • the circuit 122 is electrically connected to the anodes P32-1211 of the light-emitting element 121 of the eighth sub-pixel P32 through the eighth group of anode connection lines GC8, and the pixel driving circuit 122 of the ninth sub-group of sub-pixels P33 is electrically connected through the ninth group of anode connection lines GC9
  • the anode electrodes P33-1211 of the light-emitting element 121 of the ninth sub-group of sub-pixels P33 are electrically connected.
  • At least one of the seventh group of anode connecting wires GC7, the eighth group of anode connecting wires GC8, and the ninth group of anode connecting wires GC9 includes a plurality of third anode connecting wires AC3, the closer the third anode connecting wires AC3 are to the second
  • the length of the anode connection line of the gate driving sub-circuit 211A2 is larger.
  • each of the seventh group of anode connection wires GC7, the eighth group of anode connection wires GC8, and the ninth group of anode connection wires GC9 includes a plurality of third anode connection wires AC3, and the plurality of third anode connection wires AC3 are in the middle of the The length of the anode connection line closer to the second gate driving sub-circuit 211A2 is greater.
  • Such a structure helps to improve the display uniformity of the third group of sub-pixels P3, thereby further improving the display effect of the display panel.
  • the fourth group of sub-pixels P4 includes a tenth sub-group of sub-pixels P41 configured to emit light of a first color, an eleventh sub-group of sub-pixels P42 configured to emit light of a second color, and This is the twelfth sub-pixel P43 that emits light of the third color.
  • the pixel driving circuit 122 of the tenth sub-group of sub-pixel P41 is electrically connected to the anodes P41-1211 of the light-emitting element 121 of the tenth sub-group of sub-pixels P41 via the tenth-group anode connection line GC10, and the pixels of the eleventh sub-group of sub-pixels P42
  • the driving circuit 122 is electrically connected to the anodes P42-1211 of the light-emitting element 121 of the eleventh sub-pixel P42 through the eleventh group of anode connection lines GC11, and the pixel driving circuit 122 of the twelfth sub-group of sub-pixel P43 is electrically connected through the twelfth sub-pixel P43.
  • the group anode connection line GC12 is electrically connected to the anodes P43-1211 of the light-emitting elements 121 of the twelfth sub-group sub-pixel P43.
  • At least one of the tenth group of anode connecting wires GC10, the eleventh group of anode connecting wires GC11, and the twelfth group of anode connecting wires GC12 includes a plurality of fourth anode connecting wires AC4, and the closer the plurality of fourth anode connecting wires AC4 are
  • the length of the anode connection line of the second gate driving sub-circuit 211A2 is larger.
  • each of the tenth group of anode connecting wires GC10, the eleventh group of anode connecting wires GC11, and the twelfth group of anode connecting wires GC12 includes a plurality of fourth anode connecting wires AC4, and a plurality of fourth anode connecting wires
  • the length of the anode connection line closer to the second gate driving sub-circuit 211A2 in AC4 is greater.
  • Such a structure helps to improve the display uniformity of the fourth group of sub-pixels P4, thereby further improving the display effect of the display panel.
  • the plurality of sub-pixels 12 of the display panel further includes a fifth group of sub-pixels P5.
  • the pixel drive circuit 122 of the fifth group of sub-pixels P5 is located between the pixel drive circuit 122 of the first group of sub-pixels P1 and the pixel drive circuit 122 of the fourth group of sub-pixels P4, and the pixel drive circuit 122 of the first group of sub-pixels P1 is located Between the first gate driving sub-circuit 211A1 and the pixel driving circuit 122 of the fifth group of sub-pixels P5, the pixel driving circuit 122 of the fourth group of sub-pixels P4 is located between the pixel driving circuit 122 and the second gate of the fifth group of sub-pixels P5. Between the pole driving sub-circuit 211A2.
  • the fifth group of sub-pixels P5 includes a thirteenth sub-pixel P51 configured to emit light of a first color, a fourteenth sub-pixel P52 configured to emit light of a second color, and a sub-pixel P52 configured to emit light of a second color.
  • the fifteenth sub-group of sub-pixels P53 configured to emit light of the third color.
  • the pixel driving circuit 122 of the thirteenth sub-pixel P51 is electrically connected to the anode P51-1211 of the light-emitting element 121 of the thirteenth sub-pixel P51 via the thirteenth-group anode connection line GC13, and the fourteenth sub-pixel
  • the pixel drive circuit 122 of P52 is electrically connected to the anodes P52-1211 of the light-emitting element 121 of the fourteenth sub-pixel P52 via the fourteenth group of anode connection lines GC14
  • the pixel drive circuit 122 of the fifteenth sub-pixel P53 is electrically connected via
  • the fifteenth group anode connection line GC15 is electrically connected to the anode electrodes P53-1211 of the light-emitting element 121 of the fifteenth sub-pixel P53.
  • the length of the anode connecting wire GC13 of the thirteenth group is the same
  • the length of the anode connecting wire GC14 of the fourteenth group is the same
  • the length of the anode connecting wire GC15 of the fifteenth group is the same.
  • the display panel includes the above-mentioned first group of sub-pixels P1, second group of sub-pixels P2, third group of sub-pixels P3, fourth group of sub-pixels P4, and fifth group of sub-pixels P5, the first group of sub-pixels P1,
  • the size of the pixel driving circuits of the second group of sub-pixels P2, the third group of sub-pixels P3, and the fourth group of sub-pixels P4 in the first direction are compressed.
  • the size of the sub-pixels on both sides of the first gate driving sub-circuit 211A1 in the first direction is compressed
  • the size of the sub-pixels on both sides of the second gate driving sub-circuit 211A2 in the first direction is compressed.
  • Such a structure is beneficial to improve the display uniformity of the display panel, thereby improving the display effect of the display panel.
  • the display panel may have a problem of poor display uniformity.
  • the control signal line that provides the control signal to the multiplexing circuit has a similar shape to the edge of the display area.
  • the display area has a step-like edge
  • the control signal line also has a step-like edge.
  • the length of such a control signal line is relatively large, which results in a large resistance of the control signal line, which causes a large voltage drop on the control signal line, which in turn prevents the sub-pixels from being turned on or off normally, and affects the display effect of the display panel.
  • FIG. 23A is a schematic diagram showing the structure of a display panel according to another embodiment of the present disclosure.
  • Fig. 23B is an enlarged schematic view of the circle B shown in Fig. 23A.
  • FIG. 23A a display panel according to some embodiments of the present disclosure will be introduced in conjunction with FIG. 23A, FIG. 23B, and FIG. 3A.
  • the display panel includes a base substrate 11, a plurality of sub-pixels 12, a plurality of gate lines 13, a gate driving circuit 21, a plurality of control signal lines 19, a plurality of data signal input lines 20, and a multiplexing circuit MX.
  • the base substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111.
  • the peripheral area 112 includes a first peripheral area 112A, and an edge of the first peripheral area 112A away from the display area 11 has a first curvature greater than zero.
  • the edge of the first peripheral area 112A away from the display area 11 has an arc, such as a circular arc.
  • the first peripheral area 112A may be any part of the peripheral area 112; in the peripheral area 112 away from the display area In the case where the edge portion of 11 has a curvature (such as a corner portion) greater than 0, the first peripheral area 112A may be a corner portion of the peripheral area 112, for example, one of the four corner areas.
  • a plurality of sub-pixels 12 are located in the display area 111.
  • the plurality of gate lines 13 are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12.
  • the gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211.
  • the multi-stage gate driving unit 211 is electrically connected to the plurality of gate lines 13.
  • one or more stages of the gate driving unit 211 in the multistage gate driving circuit 211 includes a plurality of gate driving sub-circuits 211A.
  • the plurality of gate driving sub-circuits 211A includes a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2.
  • the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are separated by the pixel driving circuit 122 of the first group of sub-pixels P1 among the plurality of sub-pixels 12.
  • a plurality of control signal lines 19, a plurality of data signal input lines 20, and a multiplexing circuit MX are located at least in the first peripheral area 112A. At least part of at least one of the plurality of control signal lines 19 has a second curvature greater than zero. For example, each of the plurality of control signal lines 19 has a second curvature greater than zero. In some embodiments, the second curvature is the same as the first curvature. As some implementations, each control signal line 19 has a circular arc shape.
  • the multiplexing circuit MX is located between the plurality of control signal lines 19 and the display area 111.
  • the multiplexing circuit MX includes a plurality of multiplexing units MX1, and each of the multiple multiplexing units MX1 is electrically connected to a plurality of control signal lines 19 and a data signal input of a plurality of data signal input lines 20.
  • At least part of at least one of the plurality of control signal lines 19 has a second curvature greater than zero. Such a structure helps to reduce the length of the control signal line 19 and reduce the resistance of the control signal line 19, thereby improving the display uniformity of the display panel.
  • the display panel further includes a power supply bus VDD configured to provide a power supply voltage to the power supply line 16 of the display area 111.
  • the power bus VDD is located on the side of the plurality of control signal lines 19 away from the display area 111.
  • the plurality of sub-pixels 12 includes a first row of sub-pixels C1 and a second row of sub-pixels C2 that are arranged in a first direction and are adjacent to each other.
  • the number of sub-pixels C2 in two rows.
  • At least one of the multiple multiplexing units MX is at least partially located in the first area 112A1 of the first peripheral area 112A.
  • the first area 112A1 is located at the side of the second row of sub-pixels C2 away from the display area 111 in the first direction
  • the first area 112A1 is located at the first row of sub-pixels C1 away from the display area 111 in the second direction perpendicular to the first direction.
  • the first area 112A1 is located on the left side of the second row of sub-pixels C2 in the first direction, and the first area 112A1 is located on the lower side of the first row of sub-pixels C1 in the second direction.
  • the first straight line where the left edge of the sub-pixel C1 in the first row is located, the second straight line where the lower edge of the sub-pixel C1 in the first row is located, the third straight line where the left edge of the sub-pixel C2 in the second row is located, and the The closed space enclosed by the fourth straight line where the lower edge of the two rows of sub-pixels C2 is located can be regarded as the first area 112A1.
  • the first peripheral area 112A may include a plurality of first areas 112A1.
  • the display panel further includes a plurality of control signal connection lines 19A, and the plurality of control signal lines 19 are electrically connected to the plurality of multiplexing units MX via the plurality of control signal connection lines 19A.
  • the multiple control signal wires 19 are electrically connected to the multiple control signal connection wires 19A in a one-to-one correspondence
  • the multiple control signal connection wires 19A are electrically connected to the multiple multiplexing units MX in a one-to-one correspondence.
  • the extension direction of the multiple control signal connection lines 19A is the same as the extension direction of the multiple data lines 15 (see FIG. 23A), that is, they extend along the second direction. In this manner, it is helpful to reduce the length of the control signal connection line 19A and reduce the resistance of the control signal connection line 19A, thereby helping to improve the display uniformity of the display panel.
  • Fig. 24 is a partial schematic diagram showing Fig. 23B. The structure diagram of the multiplexing unit MX is described below in conjunction with FIG. 24.
  • each of the plurality of multiplexing units MX includes a plurality of switching transistors SW corresponding to a plurality of control signal lines 19 and at least two data lines 15 in a one-to-one correspondence.
  • each of the multiple multiplexing units MX includes six switching transistors, the number of the multiple control signal lines 19 is six, and the number of at least two data lines 15 is six.
  • three of the six switching transistors are located in a certain first area 112A1, and the other three switching transistors are located in another first area 112A1.
  • the gate SW0 of each of the plurality of switching transistors SW is electrically connected to a corresponding one of the plurality of control signal lines 19, and the first electrode SW1 of each of the plurality of switching transistors SW is electrically connected to the plurality of data
  • One of the signal input lines 20 corresponds to the data signal input line 20
  • the second electrode SW2 of each of the plurality of switching transistors SW is electrically connected to one of the at least two data lines 15 corresponding to the data line 15.
  • the gate SW0 of each switching transistor SW is electrically connected to a corresponding control signal line 19 via a corresponding control signal connection line 19.
  • the embodiments of the present disclosure also provide methods for manufacturing various display panels.
  • FIG. 25 is a schematic flowchart showing a method of manufacturing a display panel according to an embodiment of the present disclosure.
  • a base substrate is provided.
  • the base substrate includes a display area and a peripheral area surrounding the display area.
  • step 254 a plurality of sub-pixels, a plurality of gate lines, a plurality of light-emitting control lines, a gate driving circuit, and a light-emitting control driving circuit are formed in the display area.
  • Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element.
  • the multiple gate lines are electrically connected to the multiple sub-pixels, and the multiple light-emitting control lines are electrically connected to the multiple sub-pixels.
  • the gate driving circuit includes a cascaded multi-level gate driving unit, the multi-level gate driving unit is electrically connected to a plurality of gate lines, and the one or multi-level gate driving unit in the multi-level gate driving circuit includes a plurality of gates.
  • the multiple gate driving sub-circuits include a first gate driving sub-circuit and a second gate driving sub-circuit.
  • the first gate driving sub-circuit and the second gate driving sub-circuit are composed of The pixel driving circuits of the first group of sub-pixels are spaced apart.
  • the light emission control driving circuit includes a cascaded multi-level light emission control driving unit, the multi-level light emission control driving unit is electrically connected to a plurality of light emission control lines, and one or multi-level light emission control driving unit in the multi-level light emission control driving unit includes a plurality of light emission Control and drive sub-circuits.
  • the multiple light-emission control drive sub-circuits include a first light-emission control drive sub-circuit and a second light-emission control drive sub-circuit.
  • the first light-emission control drive sub-circuit and the second light-emission control drive sub-circuit consist of The pixel driving circuits of the second group of sub-pixels are spaced apart.
  • the gate drive circuit and the light emission control drive circuit are both located in the display area. At least one stage of the gate drive unit of the gate drive circuit includes multiple gate drive sub-circuits distributed in the pixel drive circuit of the multiple sub-pixels, and at least one stage of light emission control drive unit of the light-emission control drive circuit includes multiple sub-pixels. Multiple light-emitting control drive sub-circuits in the pixel drive circuit. Such a structure is beneficial to reduce the frame size of the display panel.
  • FIG. 26 is a schematic flowchart showing a method of manufacturing a display panel according to another embodiment of the present disclosure.
  • a base substrate is provided.
  • the base substrate includes a display area and a peripheral area surrounding the display area.
  • step 264 a plurality of sub-pixels, a plurality of gate lines, a gate driving circuit, and a gate driving sub-circuit connection line are formed in the display area.
  • Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element, a plurality of gate lines are electrically connected to the plurality of sub-pixels, and the gate driving circuit includes a cascaded multi-stage gate driving unit.
  • the multi-stage gate driving unit is electrically connected to a plurality of gate lines.
  • the one or multi-stage gate driving unit in the multi-stage gate driving circuit includes a plurality of gate driving sub-circuits, and the plurality of gate driving sub-circuits includes a first The gate driving sub-circuit and the second gate driving sub-circuit, the first gate driving sub-circuit and the second gate driving sub-circuit are separated by the pixel driving circuit of the first group of the sub-pixels among the plurality of sub-pixels.
  • One end of the gate driving sub-circuit connecting line is electrically connected to the first gate driving sub-circuit, and the other end of the gate driving sub-circuit connecting line is electrically connected to the second gate driving sub-circuit.
  • the pixel driving circuit of at least one sub-pixel in the first group of sub-pixels includes a first pixel driving sub-circuit, a second pixel driving sub-circuit, and a connector.
  • the first pixel driving sub-circuit is located on one side of the connecting line of the gate driving sub-circuit, and includes a driving transistor, and the driving transistor includes a first active layer located on one side of the base substrate.
  • the second pixel driving sub-circuit is located on the side of the gate driving sub-circuit connecting line away from the first pixel driving sub-circuit.
  • One end of the connector is electrically connected to the first pixel driving sub-circuit, and the other end of the connector is electrically connected to the second pixel driving sub-circuit.
  • the orthographic projections on the substrate overlap, and the connector and the first active layer are located on different layers.
  • the connecting member and the first active layer are located on different layers, and no transistor is formed between the gate driving sub-circuit connecting line and the connecting member. Therefore, at least the problem of a decrease in the display effect of the display panel caused by the formation of transistors between the gate driving sub-circuit connection line and the connection member is alleviated.
  • FIG. 27 is a schematic flowchart showing a method of manufacturing a display panel according to another embodiment of the present disclosure.
  • a base substrate is provided.
  • the base substrate includes a display area and a peripheral area surrounding the display area.
  • step 274 a plurality of sub-pixels, a plurality of gate lines, and a gate driving circuit are formed in the display area.
  • Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element, and a plurality of gate lines are electrically connected to the plurality of sub-pixels.
  • the gate driving circuit includes a cascaded multi-level gate driving unit, the multi-level gate driving unit is electrically connected to a plurality of gate lines, and the one or multi-level gate driving unit in the multi-level gate driving circuit includes a plurality of gates.
  • the multiple gate driving sub-circuits include a first gate driving sub-circuit and a second gate driving sub-circuit.
  • the plurality of sub-pixels includes a first group of sub-pixels and a second group of sub-pixels.
  • the pixel driving circuits of a group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels are located in the first gate driving sub-circuit and the second gate. Between the driving sub-circuits, the pixel driving circuit of the other group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels is located on the side of the first gate driving sub-circuit away from the second gate driving sub-circuit.
  • the first group of sub-pixels includes: a first sub-group of sub-pixels configured to emit light of a first color, and the pixel driving circuit of the first sub-group of sub-pixels is electrically connected to the first sub-group of sub-pixels via the first group of anode connection lines
  • the anode of the light-emitting element; the second sub-group of sub-pixels are configured to emit light of the second color, and the pixel driving circuit of the second sub-group of sub-pixels is electrically connected to the second sub-group of sub-pixels via the second group of anode connection lines
  • the anode of the light-emitting element; and the third sub-group of sub-pixels are configured to emit light of the third color, and the pixel driving circuit of the third sub-group of sub-pixels is electrically connected to the third sub-group of sub-pixels via the third group of anode connection lines
  • At least one of the first group of anode connection wires, the second group of anode connection wires, and the third group of anode connection wires includes a plurality of first anode connection wires, and the plurality of first anode connection wires include two first anode connection wires, The length of the first anode connecting line closer to the first gate driving sub-circuit among the two first anode connecting lines is greater.
  • FIG. 28 is a schematic flowchart showing a manufacturing method of a display panel according to still another embodiment of the present disclosure.
  • a base substrate is provided.
  • the base substrate includes a display area and a peripheral area surrounding the display area, the peripheral area includes a first peripheral area, and an edge of the first peripheral area away from the display area has a first curvature greater than zero.
  • step 284 a plurality of sub-pixels, a plurality of data lines, a plurality of gate lines, a gate driving circuit, a plurality of control signal lines, a plurality of data signal input lines, and a multiplexing circuit are formed.
  • Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element.
  • a plurality of data lines are located in the display area and are electrically connected to a plurality of sub-pixels.
  • a plurality of gate lines are located in the display area and are electrically connected to a plurality of sub-pixels.
  • the gate driving circuit is located in the display area and includes cascaded multi-stage gate driving units. The multi-stage gate driving unit is electrically connected to a plurality of gate lines.
  • the one or multi-stage gate driving unit in the multi-stage gate driving circuit includes a plurality of gate driving sub-circuits, and the plurality of gate driving sub-circuits includes a first The gate driving sub-circuit and the second gate driving sub-circuit, the first gate driving sub-circuit and the second gate driving sub-circuit are separated by the pixel driving circuit of the first group of the sub-pixels among the plurality of sub-pixels.
  • the plurality of control signal lines are located at least in the first peripheral area, and at least part of at least one of the plurality of control signal lines has a second curvature greater than zero.
  • the multiple data signal input lines are located at least in the first peripheral area.
  • the multiplexing circuit is located at least in the first peripheral area and between the plurality of control signal lines and the display area.
  • the multiplexing circuit includes a plurality of multiplexing units, and each of the multiple multiplexing units is electrically connected to a plurality of control signal lines, one data signal input line among the plurality of data signal input lines, and a plurality of data At least two data lines in the line.
  • At least part of at least one of the plurality of control signal lines has a second curvature greater than zero.
  • Such a structure helps to reduce the length of the control signal line and reduce the resistance of the control signal line, thereby improving the display uniformity of the display panel.
  • the present disclosure also provides a display device, which may include the display panel of any one of the above embodiments.
  • the display device may be, for example, a wearable device (such as a watch), a mobile terminal, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic paper, or any product or component that has a display function.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板及其制造方法、显示装置。显示面板包括：衬底基板（11），包括显示区（111）和周边区（112），周边区（112）包括第一周边区（112A），第一周边区（112A）远离显示区（111）的边缘具有大于0的第一曲率；多个子像素（12）；多条数据线（15）；多条栅极线（13）；栅极驱动电路（21），位于显示区（111），包括级联的多级栅极驱动单元（211），一级或多级栅极驱动单元（211）包括间隔开的第一和第二栅极驱动子电路（211A）；多条控制信号线（19），至少位于第一周边区（112A），至少一条控制信号线（19）的至少部分具有大于0的第二曲率；多条数据信号输入线（20），至少位于第一周边区（112A）；多路复用电路（MX），至少位于第一周边区（112A）以及多条控制信号线（19）和显示区（111）之间，包括多个多路复用单元（MX1），每个多路复用单元（MX1）电连接至多条控制信号线（19）、一条数据信号输入线（20）和至少两条数据线（15）。

Description

显示面板及其制造方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制造方法、显示装置。
背景技术
近年来，由于具有自发光、可柔性化、制程简单等特性，有机发光二极管(organic light emitting diode，OLED)显示器被广泛应用。穿戴类、移动类的显示器向更小边框以及更大的屏占比方向发展。
发明内容
根据本公开实施例的一方面，提供一种显示面板，包括：衬底基板，包括显示区和围绕所述显示区的周边区，所述周边区包括第一周边区，所述第一周边区远离所述显示区的边缘具有第一曲率，所述第一曲率大于0；多个子像素，位于所述显示区，每个子像素包括发光元件和被配置为驱动所述发光元件的像素驱动电路；多条数据线，位于所述显示区，且电连接至所述多个子像素；多条栅极线，位于所述显示区，且电连接至所述多个子像素；栅极驱动电路，位于所述显示区，包括级联的多级栅极驱动单元，所述多级栅极驱动单元电连接至所述多条栅极线，所述多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，所述多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路，所述第一栅极驱动子电路和所述第二栅极驱动子电路由所述多个子像素中的第一组子像素的所述像素驱动电路间隔开；多条控制信号线，至少位于所述第一周边区，所述多条控制信号线中的至少一条的至少部分具有第二曲率，所述第二曲率大于0；多条数据信号输入线，至少位于所述第一周边区；和多路复用电路，至少位于所述第一周边区，且位于所述多条控制信号线和所述显示区之间，所述多路复用电路包括多个多路复用单元，所述多个多路复用单元中的每一个电连接至所述多条控制信号线、所述多条数据信号输入线中的一条数据信号输入线和所述多条数据线中的至少两条数据线。
在一些实施例中，所述多个子像素包括在第一方向上排布且相邻的第一行子像素和第二行子像素，所述第一行子像素的数量大于所述第二行子像素的数量；所述多个多路复用单元中的至少一个至少部分地位于所述第一周边区的第一区域，所述第一区 域在第一方向上位于所述第二行子像素的一侧远离所述显示区的一侧，并且在与所述第一方向垂直的第二方向上位于所述第一行子像素远离所述显示区的一侧。
在一些实施例中，所述显示面板还包括：多条控制信号连接线，所述多条控制信号线经由所述多条控制信号连接线电连接至所述多个多路复用单元。
在一些实施例中，所述多条控制信号连接线的延伸方向和所述多条数据线的延伸方向相同。
在一些实施例中，所述多个多路复用单元中的每一个包括与所述多条控制信号线和所述至少两条数据线一一对应的多个开关晶体管，所述多个开关晶体管中的每一个的栅极电连接至所述多条控制信号线中的一条对应的控制信号线，所述多个开关晶体管中的每一个的第一电极电连接至所述多条数据信号输入线中的一条对应的数据信号输入线，所述多个开关晶体管中的每一个的第二电极电连接至所述至少两条数据线中的一条对应的数据线。
在一些实施例中，所述多条控制信号线的每一条具有所述第二曲率。
在一些实施例中，所述第二曲率与所述第一曲率相同。
在一些实施例中，所述第一组子像素包括：第一子组子像素，被配置为发出第一颜色的光，所述第一子组子像素的所述像素驱动电路经由第一组阳极连接线电连接至所述第一子组子像素的所述发光元件的阳极；第二子组子像素，被配置为发出第二颜色的光，所述第二子组子像素的所述像素驱动电路经由第二组阳极连接线电连接至所述第二子组子像素的所述发光元件的阳极；和第三子组子像素，被配置为发出第三颜色的光，所述第三子组子像素的所述像素驱动电路经由第三组阳极连接线电连接至所述第三子组子像素的所述发光元件的阳极。所述第一组阳极连接线、所述第二组阳极连接线和第三组阳极连接线中的至少一组包括多条第一阳极连接线，所述多条第一阳极连接线包括两条第一阳极连接线，所述两条第一阳极连接线中越靠近所述第一栅极驱动子电路的第一阳极连接线的长度越大。
在一些实施例中，所述多条第一阳极连接线中越靠近所述第一栅极驱动子电路的第一阳极连接线的长度越大。
在一些实施例中，所述第一组阳极连接线、所述第二组阳极连接线、所述第三组阳极连接线中的至少一组与所述发光元件的阳极位于同一层。
在一些实施例中，所述第一组阳极连接线与所述第一子组子像素的所述发光元件的阳极一体设置；所述第二组阳极连接线与所述第二子组子像素的所述发光元件的阳 极一体设置；所述第三组阳极连接线与所述第三子组子像素的所述发光元件的阳极一体设置。
在一些实施例中，所述第一组阳极连接线经由第一组过孔电连接至所述第一子组子像素的所述像素驱动电路；所述第二组阳极连接线经由第二组过孔电连接至所述第二子组子像素的所述像素驱动电路；所述第三组阳极连接线经由第三组过孔电连接至所述第三子组子像素的所述像素驱动电路。
在一些实施例中，所述多个子像素还包括第二组子像素，所述第二组子像素的所述像素驱动电路位于所述第一栅极驱动子电路远离所述第二栅极驱动子电路的一侧。所述第二组子像素包括：第四子组子像素，被配置为发出所述第一颜色的光，所述第四子组子像素的所述像素驱动电路经由第四组阳极连接线电连接至所述第四子组子像素的所述发光元件的阳极；第五子组子像素，被配置为发出所述第二颜色的光，所述第五子组子像素的所述像素驱动电路经由第五组阳极连接线电连接至所述第五子组子像素的所述发光元件的阳极；和第六子组子像素，被配置为发出所述第三颜色的光，所述第六子组子像素的所述像素驱动电路经由第六组阳极连接线电连接至所述第六子组子像素的所述发光元件的阳极。所述第四组阳极连接线、所述第五组阳极连接线和所述第六组阳极连接线中的至少一组包括多条第二阳极连接线，所述多条第二阳极连接线中越靠近所述第一栅极驱动子电路的第二阳极连接线的长度越大。
在一些实施例中，所述多个子像素还包括第三组子像素和第四组子像素，所述第三组子像素和所述第四组子像素中的一组子像素的所述像素驱动电路位于所述第二栅极驱动子电路靠近所述第一栅极驱动子电路、所述第一组子像素和所述第二组子像素的一侧，另一组子像素的所述像素驱动电路位于所述第二栅极驱动子电路远离所述第一栅极驱动子电路的一侧。所述第三组子像素包括：第七子组子像素，被配置为发出所述第一颜色的光，所述第七子组子像素的所述像素驱动电路经由第七组阳极连接线电连接至所述第七子组子像素的所述发光元件的阳极；第八子组子像素，被配置为发出所述第二颜色的光，所述第八子组子像素的所述像素驱动电路经由第八组阳极连接线电连接至所述第八子组子像素的所述发光元件的阳极；和第九子组子像素，被配置为发出所述第三颜色的光，所述第九子组子像素的所述像素驱动电路经由第九组阳极连接线电连接至所述第九子组子像素的所述发光元件的阳极。所述第七组阳极连接线、所述第八组阳极连接线和第九组阳极连接线中的至少一组包括多条第三阳极连接线，所述多条第三阳极连接线中越靠近所述第二栅极驱动子电路的第三阳极连接线的 长度越大。
在一些实施例中，所述第四组子像素包括：第十子组子像素，被配置为发出所述第一颜色的光，所述第十子组子像素的所述像素驱动电路经由第十组阳极连接线电连接至所述第十子组子像素的所述发光元件的阳极；第十一子组子像素，被配置为发出所述第二颜色的光，所述第十一子组子像素的所述像素驱动电路经由第十一组阳极连接线电连接至所述第十一子组子像素的所述发光元件的阳极；和第十二子组子像素，被配置为发出所述第三颜色的光，所述第十二子组子像素的所述像素驱动电路经由第十二组阳极连接线电连接至所述第十二子组子像素的所述发光元件的阳极。所述第十组阳极连接线、所述第十一组阳极连接线和第十二组阳极连接线中的至少一组包括多条第四阳极连接线，所述多条第四阳极连接线中越靠近所述第二栅极驱动子电路的阳极连接线的长度越大。
在一些实施例中，所述多个子像素还包括第五组子像素，所述第五组子像素的所述像素驱动电路位于所述第一组子像素的所述像素驱动电路和所述第四组子像素的所述像素驱动电路之间，所述第一组子像素的所述像素驱动电路位于所述第一栅极驱动子电路和所述第五组子像素的所述像素驱动电路之间，所述第四组子像素的所述像素驱动电路位于所述第五组子像素的所述像素驱动电路和所述第二栅极驱动子电路之间。所述第五组子像素包括：第十三子组子像素，被配置为发出所述第一颜色的光，所述第十三子组子像素的所述像素驱动电路经由第十三组阳极连接线电连接至所述第十三子组子像素的所述发光元件的阳极；第十四子组子像素，被配置为发出所述第二颜色的光，所述第十四子组子像素的所述像素驱动电路经由第十四组阳极连接线电连接至所述第十四子组子像素的所述发光元件的阳极；和第十五子组子像素，被配置为发出所述第三颜色的光，所述第十五子组子像素的所述像素驱动电路经由第十五组阳极连接线电连接至所述第十五子组子像素的所述发光元件的阳极。所述第十三组阳极连接线的长度相同，所述第十四组阳极连接线的长度相同，所述第十五组阳极连接线的长度相同。
在一些实施例中，所述显示面板还包括：第一电路连接线，位于所述显示区，所述第一电路连接线的一端电连接至所述第一栅极驱动子电路，所述第一电路连接线的另一端电连接至所述第二栅极驱动子电路。所述第一组子像素位于所述第一栅极驱动子电路和所述第二栅极驱动子电路之间，所述第一组子像素中的至少一个子像素的所述像素驱动电路包括：第一像素驱动子电路，位于所述第一电路连接线的一侧，包括 驱动晶体管，所述驱动晶体管包括位于所述衬底基板一侧的第一有源层；第二像素驱动子电路，位于所述第一电路连接线远离所述第一像素驱动子电路的一侧；和连接件，所述连接件的一端电连接至所述第一像素驱动子电路，所述连接件的另一端电连接至所述第二像素驱动子电路，所述连接件在所述衬底基板上的正投影与所述第一电路连接线在所述衬底基板上的正投影交叠，所述连接件与所述驱动有源层位于不同层。
在一些实施例中，所述驱动晶体管还包括：位于所述第一有源层远离所述衬底基板一侧的第一栅极；位于所述第一栅极远离所述衬底基板一侧的第一绝缘层；位于所述第一绝缘层远离所述衬底基板一侧的第二绝缘层；和位于所述第二绝缘层远离所述衬底基板一侧、且电连接至所述第一有源层的第一电极和第二电极。所述第一像素驱动子电路还包括存储电容，包括：第一电极板，与所述第一栅极位于同一层；和第二电极板，位于所述第一绝缘层和所述第二绝缘层之间。所述第一电路连接线与所述第一栅极位于同一层，所述第二电极板、所述第一电极和所述第二电极中的至少一个与所述连接件位于同一层。
在一些实施例中，所述第一电极、所述第二电极和所述连接件位于同一层。
在一些实施例中，所述一级或多级栅极驱动单元包括级联的前一级栅极驱动单元和后一级栅极驱动单元，其中：所述前一级栅极驱动单元的所述第一栅极驱动子电路包括所述前一级栅极驱动单元的第一输入端，所述前一级栅极驱动单元的所述第二栅极驱动子电路包括所述前一级栅极驱动单元的第一输出端；所述后一级栅极驱动单元的所述第一栅极驱动子电路包括所述后一级栅极驱动单元的第一输入端，所述后一级栅极驱动单元的所述第二栅极驱动子电路包括所述后一级栅极驱动单元的第一输出端。
在一些实施例中，所述前一级栅极驱动单元的第一输出端电连接至所述多条栅极线的第一栅极线；所述显示面板还包括：第一级联连接线，位于所述第一组子像素的所述像素驱动电路远离所述第二栅极驱动子电路的一侧，所述第一级联连接线的一端电连接至所述第一栅极线，所述第一级联连接线的另一端电连接至所述后一级栅极驱动单元的第一输入端。
在一些实施例中，所述显示面板还包括：多条复位线，位于所述显示区，且电连接至所述多个子像素；所述后一级栅极驱动单元的所述第一栅极驱动子电路和所述第二栅极驱动子电路之间的所述第一组子像素的所述像素驱动电路电连接至所述多条复位线中的第一复位线，所述第一复位线经由所述第一级联连接线电连接至所述第一 栅极线。
在一些实施例中，所述第一级联连接线经由第一过孔电连接至所述第一栅极线，经由第二过孔电连接至所述后一级栅极驱动单元的第一输入端，经由第三过孔电连接至所述第一复位线。
在一些实施例中，所述显示面板还包括：第二级联连接线，位于所述第一组子像素远离所述第一栅极驱动子电路的一侧，所述第二级联连接线的一端电连接至所述第一栅极线，所述第二级联连接线的另一端电连接至所述第一复位线。
在一些实施例中，所述显示面板还包括：多条发光控制线，位于所述显示区，且电连接至所述多个子像素；发光控制驱动电路，位于所述显示区，包括级联的多级发光控制驱动单元，所述多级发光控制驱动单元电连接至所述多条发光控制线，所述多级发光控制驱动单元中的一级或多级发光控制驱动单元包括多个发光控制驱动子电路，所述多个发光控制驱动子电路包括第一发光控制驱动子电路和第二发光控制驱动子电路，所述第一发光控制驱动子电路和所述第二发光控制驱动子电路由所述多个子像素中的第六组子像素的所述像素驱动电路间隔开。
根据本公开实施例的另一方面，提供一种显示装置，包括：上述任意一个实施例所述的显示面板。
根据本公开实施例的又一方面，提供一种显示面板的制造方法，包括：提供衬底基板，所述衬底基板包括显示区和围绕所述显示区的周边区，所述周边区包括第一周边区，所述第一周边区远离所述显示区的边缘具有第一曲率，所述第一曲率大于0；和形成多个子像素、多条数据线、多条栅极线、栅极驱动电路、多条控制信号线、多条数据信号输入线和多路复用电路。每个子像素包括发光元件和被配置为驱动所述发光元件的像素驱动电路，所述多条数据线位于所述显示区，且电连接至所述多个子像素，所述多条栅极线位于所述显示区，且电连接至所述多个子像素。所述栅极驱动电路位于所述显示区，且包括级联的多级栅极驱动单元，所述多级栅极驱动单元电连接至所述多条栅极线，所述多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，所述多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路，所述第一栅极驱动子电路和所述第二栅极驱动子电路由所述多个子像素中的第一组子像素的所述像素驱动电路间隔开。所述多条控制信号线至少位于所述第一周边区，所述多条控制信号线中的至少一条的至少部分具有第二曲率，所述第二曲率大于0。所述多条数据信号输入线至少位于所述第一周边区。所述多路复用电路至少位于 所述第一周边区，且位于所述多条控制信号线和所述显示区之间，所述多路复用电路包括多个多路复用单元，所述多个多路复用单元中的每一个电连接至所述多条控制信号线、所述多条数据信号输入线中的一条数据信号输入线和所述多条数据线中的至少两条数据线。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1A是根据本公开一个实施例的显示面板的结构示意图；
图1B是根据本公开一个实施例的子像素的电路示意图；
图2是示出根据本公开另一个实施例的显示面板的结构示意图；
图3A是示出根据本公开一个实施例的多个栅极驱动子电路的分布示意图；
图3B是示出根据本公开一个实施例的多个发光控制驱动子电路的分布示意图；
图4A-图4F是示出根据本公开一些实现方式的栅极驱动单元中的不同层的布局示意图；
图5A是图4A所示的211A1的放大示意图；
图5B是图4A所示的211A2的放大示意图；
图6是示出根据本公开一个实施例的栅极驱动单元的电路示意图；
图7A-图7F是示出根据本公开另一些实现方式的栅极驱动单元中的不同层的布局示意图；
图8A是图7A所示的211A1的放大示意图；
图8B是图7A所示的211A2的放大示意图；
图8C是图7A所示的211A3的放大示意图；
图9是示出根据本公开另一个实施例的栅极驱动单元的电路示意图；
图10A-图10F是示出根据本公开一些实现方式的发光控制驱动单元中的不同层的布局示意图；
图11A是图10A所示的221A2的放大示意图；
图11B是图10A所示的221A1的放大示意图；
图12是示出根据本公开一个实施例的发光控制驱动单元的电路示意图；
图13A-图13F是示出根据本公开另一些实现方式的发光控制驱动单元中的不同层的布局示意图；
图14A是图13A所示的221A2的放大示意图；
图14B是图13A所示的221A1的放大示意图；
图15是示出根据本公开另一个实施例的发光控制驱动单元的电路示意图；
图16A是示出根据本公开另一个实施例的多个栅极驱动子电路的分布示意图；
图16B是示出根据本公开一个实施例的子像素的局部截面示意图；
图17A是示出根据本公开一个实施例的栅极驱动子电路连接线与连接件交叠的布局示意图；
图17B是沿着图17A所示的A-A’截取的截面示意图；
图18是示出根据本公开另一个实施例的多个发光控制驱动子电路的分布示意图；
图19是示出根据本公开一个实施例的子像素中的部分层的布局示意图；
图20是示出根据本公开一个实施例的级联的两级栅极驱动单元的示意图；
图21是示出根据本公开又一个实施例的多个栅极驱动子电路的分布示意图；
图22A-22E是示出根据本公开一些实施例的不同组阳极连接线的示意图；
图23A是示出根据本公开又一个实施例的显示面板的结构示意图；
图23B是图23A所示圈B的放大示意图；
图24是示出图23B的局部示意图；
图25是示出根据本公开一个实施例的显示面板的制造方法的流程示意图；
图26是示出根据本公开另一个实施例的显示面板的制造方法的流程示意图；
图27是示出根据本公开又一个实施例的显示面板的制造方法的流程示意图；
图28是示出根据本公开再一个实施例的显示面板的制造方法的流程示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明， 否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
相关技术中，为了驱动显示面板的子像素发光，在显示面板的周边区设置驱动电路，例如栅极驱动电路或发光控制驱动电路。发明人注意到，对于某些小尺寸的可穿戴设备，例如圆形手表等，需要更小的边框尺寸。
有鉴于此，本公开实施例提供了如下技术方案。
图1A是根据本公开一个实施例的显示面板的结构示意图。图1B是根据本公开一个实施例的子像素的电路示意图。
如图1A所示，显示面板包括衬底基板11和多个子像素12。
衬底基板11包括显示区111和围绕显示区111的周边区112。这里，显示区111被示意性地示出为大致呈圆形，周边区112被示意性地示出为大致呈圆环形。应理解，本公开实施例并不限于此。例如，在其他地实施例中，显示区111可以大致呈矩形，而周边区112可以大致呈矩形环。在一些实施例中，衬底基板11可以包括柔性基板，例如聚酰亚胺(PI)基板等。
多个子像素12位于显示区111。例如，多个子像素12可以包括红色子像素、绿 色子像素或蓝色子像素等。
如图1B所示，每个子像素12包括发光元件121和被配置为驱动发光元件121的像素驱动电路122。例如，发光元件121可以包括有机发光二极管(OLED)等。例如，参见图1B，像素驱动电路122可以包括7个晶体管和1个电容器(7T1C)。例如，7个晶体管可以为PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)晶体管。又例如，7个晶体管中的一些晶体管为PMOS晶体管，其他晶体管为NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)晶体管。在其他的实施例中，像素驱动电路122可以包括6个晶体管和1个电容器(6T1C)。
需要说明的是，对于下面介绍的不同实施例的显示面板，衬底基板11和多个子像素12均可以参照上面的描述，在后面的描述中不再重复详细介绍。
图2是示出根据本公开另一个实施例的显示面板的结构示意图。图3A是示出根据本公开一个实施例的多个栅极驱动子电路的分布示意图。图3B是示出根据本公开一个实施例的多个发光控制驱动子电路的分布示意图。
如图2所示，显示面板包括衬底基板11、多个子像素12、多条栅极线13、多条发光控制线14、栅极驱动电路21和发光控制驱动电路22。
衬底基板11包括显示区111和围绕显示区111的周边区112。多个子像素12位于显示区111。多条栅极线13位于显示区111，并且电连接至多个子像素12。多条栅极线13被配置为向多个子像素12提供栅极驱动信号。多条发光控制线14位于显示区111，并且电连接至多个子像素12。多条发光控制线14被配置为向多个子像素12提供发光控制信号。
栅极驱动电路21位于显示区111，并且包括级联的多级栅极驱动单元211。多级栅极驱动单元211电连接至多条栅极线13。例如，多级栅极驱动单元211一一对应地电连接至多条栅极线13。例如，栅极驱动单元211可以是移位寄存器。
如图3A所示，多级栅极驱动电路211中的一级或多级栅极驱动单元211可以包括多个栅极驱动子电路211A。多个栅极驱动子电路211A可以包括第一栅极驱动子电路211A1和第二栅极驱动子电路211A2。这里，第一栅极驱动子电路211A1和第二栅极驱动子电路211A2由多个子像素12中的第一组子像素P1的像素驱动电路122间隔开。
发光控制驱动电路22位于显示区111，并且包括级联的多级发光控制驱动单元221。多级发光控制驱动单元221电连接至多条发光控制线14。例如，一级发光控制 驱动单元221电连接至两条发光控制线14。例如，发光控制驱动单元221可以是移位寄存器。
如图3B所示，多级发光控制驱动单元221中的一级或多级发光控制驱动单元221包括多个发光控制驱动子电路221A。多个发光控制驱动子电路221A包括第一发光控制驱动子电路221A1和第二发光控制驱动子电路221A2。这里，第一发光控制驱动子电路221A1和第二发光控制驱动子电路221A2由多个子像素12中的第二组子像素P2(在某些实施例中为第六组子像素P6)的像素驱动电路122间隔开。
上述实施例中，栅极驱动电路21和发光控制驱动电路22均位于显示区111。栅极驱动电路21的至少一级栅极驱动单元211包括分布在多个子像素12的像素驱动电路122中的多个栅极驱动子电路211A，发光控制驱动电路22的至少一级发光控制驱动单元221包括分布在多个子像素12的像素驱动电路122中的多个发光控制驱动子电路221A。这样的结构有利于减小显示面板的边框尺寸。
栅极驱动电路21的栅极驱动单元211可以通过不同的方式来拆分，以得到对应的多个栅极驱动子电路211A。下面结合不同的实施例进行介绍。
图4A-图4F是示出根据本公开一些实现方式的栅极驱动单元中的不同层的布局示意图。图5A是图4A所示的211A1的放大示意图。图5B是图4A所示的211A2的放大示意图。下面结合图2、图4A-图4F、以及图5A-图5B对栅极驱动电路21的栅极驱动单元211的一些拆分方式进行介绍。
在一些实施例中，参见图2，显示面板还包括多条初始化线17和多条复位线18。多条初始化线17位于显示区111，并且电连接至多个子像素12。多条初始化线17被配置为向多个子像素12提供初始化信号。多条复位线18位于显示区111，并且电连接至多个子像素12。多条复位线18被配置为向多个子像素12提供复位信号。
参见图4A和图4B，第一组子像素P1电连接至多条初始化线17中的第一初始化线171、多条复位线18中的第一复位线181、多条栅极线13中的第一栅极线131和多条发光控制线14中的第一发光控制线141。这里，第一初始化线171和第一复位线181位于多个栅极驱动子电路211A的一侧，第一栅极线131和第一发光控制线141位于多个栅极驱动子电路211A远离第一初始化线171和第一复位线181的一侧。这样的结构有利于减小信号线占用的空间，从而有助于提高显示面板的分辨率。
在一些实施例中，参见图4F，多个栅极驱动子电路211A中的至少一个栅极驱动子电路211A在衬底基板11上的正投影与多个子像素12中的第一部分子像素12的发 光元件121的阳极1211在衬底基板11上的正投影交叠，与多个子像素12中的其余子像素12的发光元件121的阳极1211在衬底基板11上的正投影不交叠。这样的方式下，可以在尽量不影响显示均一性的情况下，减小显示面板的边框尺寸。
在一些实施例中，第一组子像素P1电连接至多条栅极线13中的第一栅极线131。一级或多级栅极驱动单元211中的每级栅极驱动单元211的第一栅极驱动子电路211A1包括每级栅极驱动单元211的第一输入端IN1，被配置为接收第一输入信号。一级或多级栅极驱动单元211中的每级栅极驱动单元211的第二栅极驱动子电路211A2包括每级栅极驱动单元211的第一输出端OUT1，被配置为向第一栅极线131输出栅极驱动信号。应理解，第一级栅极驱动单元211的第一输入端IN1可以接收来自栅极驱动电路21外部的信号作为第一输入信号，其他各级栅极驱动单元211的第一输入端IN1可以接收来自上一级栅极驱动单元211的栅极驱动信号作为第一输入信号。
在一些实施例中，参见图4A-图4F，多级栅极驱动单元211中的任意一级栅极驱动单元211均包括多个栅极驱动子电路211A，第一栅极驱动子电路211A1和第二栅极驱动子电路211A2在第一方向上由第一组子像素P1的像素驱动电路122间隔开。任意一级栅极驱动单元211中的第一栅极驱动子电路211A1在与第一方向不同的第二方向上位于任意一级栅极驱动单元211的前一级栅极驱动单元211中的第一栅极驱动子电路211A1与任意一级栅极驱动单元211的后一级栅极驱动单元211中的第一栅极驱动子电路211A1之间。任意一级栅极驱动单元211中的第二栅极驱动子电路211A2在第二方向上位于任意一级栅极驱动单元211的前一级栅极驱动单元211中的第二栅极驱动子电路211A2与任意一级栅极驱动单元211的后一级栅极驱动单元211中的第二栅极驱动子电路211A2之间。例如，第二方向垂直于第一方向。例如，第一方向为多个子像素12排列的行方向，第二方向为多个子像素12排列的列方向。
在一些实施例中，显示面板还包括第一组电路连接线。参见图4A，第一组电路连接线包括第一电路连接线N1和第二电路连接线N2。第二栅极驱动子电路211A2经由第一电路连接线N1和第二电路连接线N2电连接至第一栅极驱动子电路211A1。第一电路连接线N1和第二电路连接线N2中的一个在衬底基板11上的正投影与第一组子像素P1的像素驱动电路122在衬底基板11上的正投影不交叠，另一个在衬底基板11上的正投影与第一组子像素P1中的至少一个子像素12的像素驱动电路122在衬底基板11上的正投影交叠。例如，参见图4A，第一电路连接线N1在衬底基板11上的正 投影与第一组子像素P1的像素驱动电路122在衬底基板11上的正投影不交叠，第二电路连接线N2在衬底基板11上的正投影与第一组子像素P1中的至少一个子像素的像素驱动电路122在衬底基板11上的正投影交叠。应理解，第一电路连接线N1在衬底基板11上的正投影与位于上一级栅极驱动单元211中的第一栅极驱动子电路211A1和第二栅极驱动子电路211A2之间的第一组子像素P1的像素驱动电路122在衬底基板11上的正投影交叠。
在一些实施例中，参见图4A和图4C，第一组子像素P1中的至少一个子像素12的像素驱动电路122包括第一像素驱动子电路122A、第二像素驱动子电路122B和连接件122C。第一像素驱动子电路122A位于第一电路连接线N1与第二电路连接线N2之间，第二像素驱动子电路122B位于第二电路连接线N2远离第一像素驱动子电路122A的一侧，连接件122C电连接至第一像素驱动子电路122A和第二像素驱动子电路122B。例如，连接件122C的一端经由过孔电连接至第一像素驱动子电路122A，连接件122C的另一端经由过孔电连接至第二像素驱动子电路122B。这里，连接件122C在衬底基板11上的正投影与第二电路连接线N2在衬底基板11上的正投影交叠。
在一些实施例中，第一栅极驱动子电路211A1包括第一组晶体管GT1和第二电容器C2，第二栅极驱动子电路211A2包括第二组晶体管GT2和第一电容器C1。第二组晶体管GT2的数量小于第一组晶体管GT1的数量，并且，第二组晶体管GT2中的至少一个晶体管的沟道的宽长比大于第一组晶体管GT1中的每个晶体管的沟道的宽长比。这样的方式下，综合考虑了第一栅极驱动子电路211A1和第二栅极驱动子电路211A2中晶体管的数量和尺寸，从而使得第一栅极驱动子电路211A1和第二栅极驱动子电路211A2占用的空间比较接近。
在一些实施例中，参见图4C，第一栅极驱动子电路211A1还包括被配置为接收第一时钟信号的第一时钟信号线CK、被配置为接收第二时钟信号的第二时钟信号线CB、被配置为接收第一电源电压的第一电源线VGL和被配置为接收第二电源电压的第二电源线VGH。第二栅极驱动子电路211A2还包括被配置为接收第一时钟信号的第三时钟信号线CK’、被配置为接收第二时钟信号的第四时钟信号线CB’和被配置为接收第二电源电压的第四电源线VGH’。例如，第一电源电压小于第二电源电压。
作为一些实现方式，第一电源线VGL位于第一组晶体管GT1靠近第二栅极驱动子电路211A2的一侧；第二电源线VGH位于第一组晶体管GT1远离第二栅极驱动子电路211A2的一侧；第一时钟信号线CK和第二时钟信号线CB位于第二电源线VGH 远离第二栅极驱动子电路211A2的一侧；第四电源线VGH’位于第二组晶体管GT2和第二电容器C2远离第一栅极驱动子电路211A1的一侧；第三时钟信号线CK’和第四时钟信号线CB’位于第二组晶体管GT2和第二电容器C2靠近第一栅极驱动子电路211A1的一侧。
图6是示出根据本公开一个实施例的栅极驱动单元的电路示意图。
下面结合图6介绍第一组晶体管GT1和第二组晶体管GT2的一些具体实现方式。
参见图6，第一组晶体管GT1位于线L左侧，第二组晶体管GT2位于线L的右侧。例如，第一组晶体管GT1包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7。例如，第二组晶体管GT2包括第四晶体管T4和第五晶体管T5。
第一组晶体管GT1和第二组晶体管GT2中的每个晶体管包括栅极和有源层。这里，有源层包括第一电极区、第二电极区、以及位于第一电极区和第二电极区之间的沟道。应理解，每个晶体管的有源层被栅极覆盖的区域为沟道，未被栅极覆盖的区域为第一电极区和第二电极区。作为一些实现方式，有源层的材料例如可以包括多晶硅，例如低温多晶硅(LTPS)等。例如，第一晶体管T1包括栅极T10和有源层，有源层包括第一电极区T11、第二电极区T12、以及位于第一电极区T11和第二电极区T12之间的沟道T13，以此类推。晶体管T2-T7的有源层依次包括沟道T23、沟道T33、沟道T43、沟道T53、沟道T63和沟道T73。
参见图5A、图4A-图4C，第一晶体管T1的栅极T10电连接至第一时钟信号线CK，第一晶体管T1的第一电极区T11作为第一输入端IN1。例如，第一晶体管T1的第一电极区T11可以电连接至输入电极31，以接收第一输入信号。
第二晶体管T2的栅极T20电连接至第一晶体管T1的第二电极区T12，第二晶体管T2的第一电极区T21电连接至第一晶体管T1的栅极。例如，第二晶体管T2的栅极T20经由第一连接电极41电连接至第一晶体管T1的第二电极区T12。例如，第二晶体管T2的第一电极区T21经由第二连接电极42电连接至第一晶体管T1的栅极T10。需要说明的是，在本文中，一个部件或区域经由连接电极连接至另一个部件或区域可以理解为：一个部件或区域经由一个过孔电连接至连接电极的一端，另一个部件或区域经由另一个过孔电连接该连接电极的另一端。
第三晶体管T3的栅极电连接至第一晶体管T1的栅极T10，第三晶体管T3的第一电极区T31电连接至第一电源线VGL，第三晶体管T3的第二电极区T32电连接至 第二晶体管T2的第二电极区T22。例如，第三晶体管T3的栅极T30与第一晶体管T1的栅极T10一体设置。
第六晶体管T6的栅极T60电连接至第三晶体管T3的第二电极区T32，第六晶体管T6的第一电极区T31电连接至第二电源线VGH。例如，第六晶体管T6的栅极T60经由第三连接电极43电连接至第三晶体管T3的第二电极区T32。
第七晶体管T7的栅极T70电连接至第二时钟信号线CB，第七晶体管T7的第一电极区T71电连接至第六晶体管T6的第二电极区T72，第七晶体管T7的第二电极区T72电连接至第一晶体管T1的第二电极区T12。
参见图5B、图4A-图4C，第四晶体管T4的栅极T40经由第二电路连接线N2电连接至第六晶体管T6的栅极T60，第四晶体管T4的第一电极区T41电连接至第三电源线VGL’，第四晶体管T4的第二电极区T42作为第一输出端OUT1。例如，第四晶体管T4的第二电极区T42可以经由输出电极32(参见图4C)电连接至第一栅极线13。例如，第四晶体管T4的栅极T40经由第四连接电极44电连接至第二电路连接线N2。例如，第四晶体管T4的第一电极区41经由第五连接电极45电连接至第三电源线VGL’。
第五晶体管T5的栅极T50经由第一电路连接线N1电连接至第一晶体管T1的第二电极区T12，第五晶体管T5的第一电极区T51电连接至输出电极32，第五晶体管T5的第二电极区T52电连接至第三时钟信号线CK’。例如，第五晶体管T5的栅极T50经由第六连接电极46电连接至第一电路连接线N1。例如，第五晶体管T5的第二电极区经由第七连接电极47电连接至第四时钟信号线CB’。
第一电容器C1的第一电极板C11电连接至第五晶体管T5的栅极T50，第一电容器C1的第二电极板C12电连接至输出电极32。例如，第一电容器C1的第一电极板C11与第五晶体管T5的栅极T50一体设置。第二电容器C2的第一电极板C21电连接至第六晶体管T6的栅极T60，第二电容器C2的第二电极板C22电连接至第二电源线VGH。例如，第二电容器C2的第一电极板C21与第六晶体管T6的栅极T60一体设置。
图7A-图7F是示出根据本公开另一些实现方式的栅极驱动单元中的不同层的布局示意图。图8A是图7A所示的211A1的放大示意图。图8B是图7A所示的211A2的放大示意图。图8C是图7A所示的211A3的放大示意图。
下面结合图7A-图7F、以及图8A-图8C对栅极驱动电路21的栅极驱动单元211 的另一些拆分方式进行介绍。
在一些实施例中，参见图7A，第一组电路连接线包括第一电路连接线N1、第二电路连接线N2和第三电路连接线N3。第三电路连接线N3和第二电路连接线N2在衬底基板11上的正投影与第一组子像素P1的像素驱动电路122在衬底基板11上的正投影不交叠，第一电路连接线N1在衬底基板11上的正投影与第一组子像素P1的像素驱动电路122在衬底基板11上的正投影交叠。应理解，第三电路连接线N3和第二电路连接线N2在衬底基板11上的正投影与位于上一级栅极驱动单元211中的第一栅极驱动子电路211A1和第二栅极驱动子电路211A2之间的第一组子像素P1的像素驱动电路122在衬底基板11上的正投影交叠。
多个栅极驱动子电路211A还包括第三栅极驱动子电路211A3。第三栅极驱动子电路211A3位于第二栅极驱动子电路211A2远离第一栅极驱动子电路211A1的一侧。第三栅极驱动子电路211A3经由第三电路连接线N3电连接至第二栅极驱动子电路211A2，另外，第三栅极驱动子电路211A3经由第一电路连接线N1电连接至第一栅极驱动子电路211A1。这里，第三栅极驱动子电路211A3和第二栅极驱动子电路211A2由另一第一组子像素P1间隔开。
在一些实施例中，第一栅极驱动子电路211A1包括第三组晶体管GT3、被配置为接收第一时钟信号的第一时钟信号线CK、被配置为接收第二时钟信号的第二时钟信号线CB和被配置为接收第一电源电压的第一电源线VGL。第二栅极驱动子电路211A2包括至少一个电容器、第四组晶体管GT4和被配置为接收第二电源电压的第二电源线VGH，第四组晶体管GT4中的一个晶体管的沟道的宽长比大于第三组晶体管GT3中的每个晶体管的沟道的宽长比。第三栅极驱动子电路211A3包括第五组晶体管GT5、被配置为接收第一时钟信号的第三时钟信号线CK’和被配置为接收第二时钟信号的第四时钟信号线CB’，第五组晶体管GT5中的一个晶体管的沟道的宽长比大于第三组晶体管GT3中的每个晶体管的沟道的宽长比。
作为一些实现方式，第一电源线VGL位于第三组晶体管GT3靠近第二栅极驱动子电路211A2的一侧。作为一些实现方式，第一时钟信号线CK和第二时钟信号线CB位于第三组晶体管GT3远离第二栅极驱动子电路211A2的一侧。作为一些实现方式，第三时钟信号线CK’和第四时钟信号线CB’位于第五组晶体管GT5远离第二栅极驱动子电路211A2的一侧。
图9是示出根据本公开另一个实施例的栅极驱动单元的电路示意图。
下面结合图9介绍第三组晶体管GT3、第四组晶体管GT4、第五组晶体管GT5和第二栅极驱动子电路211A2中的至少一个电容器的一些具体实现方式。
参见图9，第三组晶体管GT3位于线L1的左侧，第四组晶体管GT4位于线L1的右侧和线L2的上侧，第五组晶体管GT5位于线L1的右侧和线L2的下侧。例如，第三组晶体管GT3包括第一晶体管T1、第二晶体管T2和第三晶体管T3。例如，第四组晶体管GT4包括第四晶体管T4和第六晶体管T6。例如，第五组晶体管GT5包括第五晶体管T5和第七晶体管T7。例如，第二栅极驱动子电路211A2中的至少一个电容器包括第一电容器C1和第二电容器C2。
第三组晶体管GT3、第四组晶体管GT4和第五组晶体管GT5中的每个晶体管包括栅极和有源层。这里，有源层包括第一电极区、第二电极区、以及位于第一电极区和第二电极区之间的沟道。作为一些实现方式，有源层的材料例如可以包括多晶硅，例如低温多晶硅等。例如，第一晶体管T1包括栅极T10和有源层，有源层包括第一电极区T11、第二电极区T12、以及位于第一电极区T11和第二电极区T12之间的沟道T13，以此类推。晶体管T2-T7的有源层依次包括沟道T23、沟道T33、沟道T43、沟道T53、沟道T63和沟道T73。
参见图8A，第一晶体管T1的栅极T10电连接至第一时钟信号线CK，第一晶体管T1的第一电极区T11作为第一输入端IN1。例如，第一晶体管T1的第一电极区T11可以电连接至输入电极31，以接收第一输入信号。
第二晶体管T2的栅极T20电连接至第一晶体管T1的第二电极区T12，第二晶体管T2的第一电极区T21电连接至第一晶体管T1的栅极T10。例如，第二晶体管T2的栅极T20经由图7C所示的连接电极51电连接至第一晶体管T1的第二电极区T12，第二晶体管T2的第一电极区T21经由图7C所示的连接电极52电连接至第一晶体管T1的栅极T10。
第三晶体管T3的栅极T30电连接至第一晶体管T1的栅极T10，第三晶体管T3的第一电极区T31电连接至第一电源线VGL，第三晶体管T3的第二电极区T32电连接至第二晶体管T2的第二电极区T22。例如，第三晶体管T3的栅极T30和第一晶体管T1的栅极T10一体设置。例如，第三晶体管T3的第二电极区T32经由图7C所示的连接电极53电连接至第二晶体管T2的第二电极区T22。
参见图8B，第四晶体管T4的栅极经由第二电路连接线N2电连接至第二晶体管T2的第二电极区T21，第四晶体管T4的第一电极区T41电连接至第二电源线VGH， 第四晶体管T4的第二电极区T42经由第一输出电极32电连接至第一栅极线13。例如，第四晶体管T4的栅极经由图7C所示的连接电极54电连接至第二电路连接线N2，第二电路连接线N2经由图7C所示的连接电极55和经由图7B所示的连接电极56电连接至第二晶体管T2的第二电极区T21。
第六晶体管T6的栅极T60电连接至第四晶体管T4的栅极T40，第六晶体管T6的第一电极区T61电连接至第二电源线VGH。例如，第六晶体管T6的栅极T60和第四晶体管T4的栅极T40一体设置。例如，第六晶体管T6的第一电极区T61经由过孔电连接至第二电源线VGH。
第一电容器C1的第一电极板C11经由第一电路连接线N1电连接至第二晶体管T2的栅极T20，第一电容器C1的第二电极板C12电连接至第一输出电极32。例如，第一电容器C1的第一电极板C11经由图7C所示的连接电极57电连接至第一电路连接线N1，第一电路连接线N1经由图7C所示的连接电极58电连接至第二晶体管T2的栅极T20。例如，第一电容器C1的第二电极板C12经由过孔电连接至第一输出电极32。
第二电容器C2的第一电极板C21电连接至第四晶体管T4的栅极T40，第二电容器C2的第二电极板C22电连接至第二电源线VGH。例如，第二电容器C2的第一电极板C21和第四晶体管T4的栅极T40一体设置。例如，第二电容器C2的第二电极板C22经由过孔电连接至第二电源线VGH。
参见图8C，第五晶体管T5的栅极T50经由第一电路连接线N1电连接至第二晶体管T2的栅极T20，第五晶体管T5的第一电极区T51电连接至第二输出电极32’，第五晶体管T5的第二电极区T52电连接至第四时钟信号线CB’。例如，第五晶体管T5的栅极T50经由图7C所示的连接电极59电连接至第一电路连接线N1。例如，第五晶体管T5的第二电极区T52经由图7C所示的连接电极60和图7B所示的连接电极61电连接至第四时钟信号线CB’。
第七晶体管T7的栅极T70电连接至第四时钟信号线CB’，第七晶体管T7的第一电极T71区经由第三电路连接线N3电连接至第六晶体管T6的第二电极区T62，第七晶体管T7的第二电极区T21电连接至第五晶体管T5的栅极T50。例如，第七晶体管T7的第一电极T71区经由图7C所示的连接电极62电连接至第三电路连接线N3，第七晶体管T7的第二电极区T21经由图7C所示的连接电极63电连接至第五晶体管T5的栅极T50。
图8A中第四晶体管T4的第二电极区T42和第五晶体管T5的第一电极区T51中的一个可以作为图9所示的第一输出端OUT1。
发光控制驱动电路22的发光控制驱动单元221也可以通过不同的方式来拆分，以得到对应的多个发光控制驱动子电路221A。下面结合不同的实施例进行介绍。
图10A-图10F是示出根据本公开一些实现方式的发光控制驱动单元中的不同层的布局示意图。图11A是图10A所示的221A2的放大示意图。图11B是图10A所示的221A1的放大示意图。
下面结合图10A-图10F、以及图11A-图11B对发光控制驱动电路22的发光控制驱动单元221的一些拆分方式进行介绍。
在一些实施例中，参见图10A，第二组子像素P2包括多个第一子像素P21和多个第二子像素P22。多个第一子像素P21电连接至多条发光控制线14中的第一发光控制线141，多个第二子像素P22电连接至多条发光控制线14中的第二发光控制线142。一级或多级发光控制驱动单元221中的每级发光控制驱动单元221的第一发光控制驱动子电路221A1包括每级发光控制驱动单元221的第二输入端IN2。第二输入端IN2被配置为接收第二输入信号。一级或多级发光控制驱动单元221中的每级发光控制驱动单元221的第二发光控制驱动子电路221A2包括每级发光控制驱动单元221的第二输出端OUT2。第二输出端OUT2被配置为向第一发光控制线141和第二发光控制线142输出发光控制信号。
在一些实施例中，参见图10F，多个发光控制驱动子电路221A中的至少一个发光控制驱动子电路221A在衬底基板11上的正投影与多个子像素12中的第二部分子像素12的发光元件121的阳极1211在衬底基板11上的正投影交叠，与多个子像素12中的其余子像素的发光元件121的阳极1211在衬底基板11上的正投影不交叠。这样的方式下，可以在尽量不影响显示均一性的情况下，减小显示面板的边框尺寸。
在一些实施例中，参见图10A-图10F，多级发光控制驱动单元221中的任意一级发光控制驱动单元221均包括多个发光控制驱动子电路221A，第一发光控制驱动子电路221A1和第二发光控制驱动子电路221A2在第一方向上由第二组子像素P2的像素驱动电路122间隔开。任意一级发光控制驱动单元221中的第一发光控制驱动子电路221A1在与第一方向不同的第二方向上位于任意一级发光控制驱动单元221的前一级发光控制驱动单元221中的第一发光控制驱动子电路221A1与任意一级发光控制驱动单元221的后一级发光控制驱动单元221中的第一发光控制驱动子电路221A1之间。 任意一级发光控制驱动单元221中的第二发光控制驱动子电路221A2在第二方向上位于任意一级发光控制驱动单元221的前一级发光控制驱动单元221中的第二发光控制驱动子电路221A2与任意一级发光控制驱动单元221的后一级发光控制驱动单元221中的第二发光控制驱动子电路221A2之间。例如，第二方向垂直于第一方向。
在一些实施例中，显示面板还包括第二组电路连接线。参见图10A，第二组电路连接线包括第四电路连接线N4和第五电路连接线N5。第二发光控制驱动子电路221A2经由第四电路连接线N4和第五电路连接线N5电连接至第一发光控制驱动子电路221A1。这里，第四电路连接线N4和第五电路连接线N5在衬底基板11上的正投影与第二组子像素P2的像素驱动电路122在衬底基板11上的正投影交叠。
在一些实施例中，第一发光控制驱动子电路221A1包括第一组晶体管GT1、第二电容器C2、被配置为接收第一电源电压的第一电源线VGL和被配置为接收第二电源电压的第二电源线VGH，第二发光控制驱动子电路221A2包括第二组晶体管GT2、第一电容器C1、第三电容器C3、被配置为接收第一时钟信号的第一时钟信号线ECK和被配置为接收第二时钟信号的第二时钟信号线ECB。这里，第一组晶体管GT1的数量小于第二组晶体管GT2的数量，并且，第一组晶体管GT1中的至少一个晶体管的沟道的宽长比大于第二组晶体管GT2中的每个晶体管的沟道的宽长比。在一些实施例中，第一组晶体管GT1中的每个晶体管的沟道的宽长比均大于第二组晶体管GT2中的每个晶体管的沟道的宽长比。
上述实施例中，综合考虑了第一发光控制驱动子电路221A1和第二发光控制驱动子电路221A2中晶体管的数量和尺寸，使得第一发光控制驱动子电路221A1和第二发光控制驱动子电路221A2占用的空间比较接近。
在一些实施例中，第二发光控制驱动子电路221A2还可以包括被配置为接收第一电源电压和第二电源电压的电源线。例如，参见图10C，第二发光控制驱动子电路221A2还可以包括被配置为接收第一电源电压的第三电源线VGL’和被配置为接收第二电源电压的第四电源线VGH’。在另一些实施例中，第二发光控制驱动子电路221A2可以不包括被配置为接收第一电源电压和第二电源电压的电源线。这种情况下，第二发光控制驱动子电路221A2可以通过电路连接线电连接至第一发光控制驱动子电路221A1中的第一电源线VGL和第二电源线VGH。
在一些实施例中，参见图10A，第一发光控制驱动子电路221A1包括第一子电路221A11和第二子电路221A12，第二发光控制驱动子电路221A2包括第三子电路 221A21和第四子电路221A22。
下面介绍第一子电路221A11、第二子电路221A12、第三子电路221A21和第四子电路221A22的一些具体实现方式。
在一些实现方式中，第一子电路221A11位于第一发光控制线141远离第二发光控制线142的一侧，第二子电路221A12位于第一发光控制线141和第二发光控制线142之间。第一子电路221A11包括第一子组晶体管GT11，第一子组晶体管GT11包括第一组晶体管GT1中的至少一个晶体管。第二子电路221A12包括第二子组晶体管GT12和第二电容器C2，第二子组晶体管GT12包括第一组晶体管GT1中除第一子组晶体管GT11之外的其他晶体管。
在一些实现方式中，第三子电路221A21位于第一发光控制线141远离第二发光控制线142的一侧，并且经由第四电路连接线N4电连接至第一子电路221A11。第四子电路221A22位于第一发光控制线141和第二发光控制线142之间，并且经由第五电路连接线N5电连接至第二子电路221A12。第三子电路221A21包括第三子组晶体管GT21，第三子组晶体管GT21包括第二组晶体管GT2中的至少一个晶体管。第四子电路221A22包括第四子组晶体管GT22和第一电容器C1，第四子组晶体管GT22包括第二组晶体管GT2中除第一子组晶体管GT11之外的其他晶体管。
根据本公开不同的实施例，第三子电路221A21和第四子电路221A22中的一个还包括第三电容器C3。下面将结合不同实施例进行介绍。
图12是示出根据本公开一个实施例的发光控制驱动单元的电路示意图。
下面结合图12、图10A-图10F、以及图11A-图11B介绍第一组晶体管GT1和第二组晶体管GT2一些具体实现方式。在这些实现方式中，第三子电路221A21还包括第三电容器C3。另外，第二发光控制驱动子电路221A2还包括被配置为接收第一电源电压的第三电源线VGL’和被配置为接收第二电源电压的第四电源线VGH’。
参见图12，第二组晶体管GT2位于线L1的左侧，第一组晶体管GT1位于线L1的右侧。第二组晶体管GT2包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8，第一组晶体管GT1包括第九晶体管T9和第十晶体管T10。
第一子组晶体管GT11位于线L1的右侧和线L2的下侧，第二子组晶体管GT12位于线L1的右侧和线L2的上侧，第三子组晶体管GT21位于线L1的左侧和线L2的左侧，第四子组晶体管GT22位于线L1的左侧和线L2的右侧。第一子组晶体管 GT11包括第十晶体管T10，第二子组晶体管GT12包括第九晶体管T9，第三子组晶体管GT21包括第一晶体管T1、第二晶体管T2和第五晶体管T5，第四子组晶体管GT22包括第三晶体管T3、第四晶体管T4、第六晶体管T6、第七晶体管T7和第八晶体管T8。
第一组晶体管GT1和第二组晶体管GT2中的每个晶体管包括栅极和有源层，有源层包括第一电极区、第二电极区、以及位于第一电极区和第二电极区之间的沟道。有源层的材料例如可以包括多晶硅，例如低温多晶硅等。例如，第一晶体管T1包括栅极T10和有源层，有源层包括第一电极区T11、第二电极区T12、以及位于第一电极区T11和第二电极区T12之间的沟道T13，以此类推。晶体管T2-T10的有源层依次包括沟道T23、沟道T33、沟道T43、沟道T53、沟道T63、沟道T73、沟道T83、沟道T93和沟道T103。
第一晶体管T1的栅极T10电连接至第一时钟信号线CK，第一晶体管T1的第一电极区T11作为第二输入端IN2。例如，第一晶体管T1的第一电极区T11可以电连接至第二输入电极33，以接收第二输入信号。
第二晶体管T2的栅极T20电连接至第一晶体管T1的第二电极区T12，第二晶体管T2的第一电极区T21电连接至第一晶体管T1的栅极T10。第二晶体管T2的栅极T20经由图10C所示的连接电极64电连接至第一晶体管T1的第二电极区T12。例如，第二晶体管T2的第一电极区T21经由图10C所示的连接电极65电连接至第一晶体管T1的栅极T10。
第三晶体管T3的栅极T30电连接至第二晶体管T2的第二电极区T22，第三晶体管T3的第一电极区T31电连接至第四电源线VGH’。例如，第三晶体管T3的栅极T30经由图10C所示的连接电极66电连接至第二晶体管T2的第二电极区T22。
第四晶体管T4的栅极T40电连接至第二时钟信号线ECB，第四晶体管T4的第一电极区T41电连接至第三晶体管T3的第二电极区T32，第四晶体管T4的第二电极区T42电连接至第二晶体管T2的栅极T20。例如，第四晶体管T4的第二电极区T42经由图10C所示的连接电极64电连接至第二晶体管T2的栅极T20。
第五晶体管T5的栅极T50电连接至第一晶体管T1的栅极T10，第五晶体管T5的第一电极区T51电连接至第三电源线VGL’，第五晶体管T5的第二电极区T52电连接至第二晶体管T2的第二电极区T22。例如，第五晶体管T5的栅极T50和第一晶体管T1的栅极T10一体设置。例如，第五晶体管T5的第二电极区T52经由图10C 所示的连接电极66电连接至第二晶体管T2的第二电极区T22。
第六晶体管T6的栅极T60电连接至第三晶体管T3的栅极T30，第六晶体管T6的第一电极区T61电连接至第四晶体管T4的栅极T40。例如，第六晶体管T6的栅极T60和第三晶体管T3的栅极T30一体设置。例如，第六晶体管T6的第一电极区T61经由图10C所示的连接电极67电连接至第四晶体管T4的栅极T40。
第七晶体管T7的栅极T70电连接至第四晶体管T4的栅极T40。例如，第七晶体管T7的栅极T70和第四晶体管T4的栅极T40一体设置。
第八晶体管T8的第一电极区T81电连接至第四电源线VGH’，第八晶体管T8的第二电极区T82电连接至第七晶体管T7的第二电极区T72。例如，第八晶体管T8的第二电极区T82经由图10C所示的连接电极68电连接至第七晶体管T7的第二电极区T72。
第九晶体管T9的栅极T90经由第五电路连接线N5电连接至第七晶体管T7的第二电极区T72，第九晶体管T9的第一电极区T91电连接至第二电源线VGH，第九晶体管T9的第二电极区T92作为第二输出端OUT2。例如，第九晶体管T9的第二电极区T92经由第二输出电极34电连接至第一发光控制线141和第二发光控制线142。例如，第九晶体管T9的栅极T90经由图10C所示的连接电极69电连接至第五电路连接线N5，第五电路连接线N5经由图10C所示的连接电极68电连接至第七晶体管T7的第二电极区T72。
第十晶体管T10的第一电极区T101电连接至第二输出电极34，第十晶体管T10的第二电极区T102电连接至第一电源线VGL。
第一电容器C1的第一电极板C11电连接至第三晶体管T3的栅极T30和第六晶体管T6的栅极T60，第一电容器C1的第二电极板C12电连接至第六晶体管T6的第二电极区T62和第七晶体管T7的第一电极区T71。第一电容器C1的第一电极板C11、第三晶体管T3的栅极T30和第六晶体管T6的栅极T60一体设置。例如，第一电容器C1的第二电极板C12经由图10C所示的连接电极70电连接至第六晶体管T6的第二电极区T62，并且经由图10C所示的连接电极71电连接至第七晶体管T7的第一电极区T71。
第二电容器C2的第一电极板C21电连接至第九晶体管T9的栅极T90，第二电容器C2的第二电极板C22电连接至第二电源线VGH。例如，第二电容器C2的第一电极板C21和第九晶体管T9的栅极T90一体设置。
第三电容器C3的第一电极板C31电连接至第二晶体管T2的栅极T20、第八晶体管T8的栅极T80和第十晶体管T10的栅极T100，第三电容器C3的第二电极板C32电连接至第四晶体管T4的栅极T40。例如，第三电容器C3的第一电极板C31和第二晶体管T2的栅极T20一体设置。例如，第三电容器C3的第一电极板C31经由图10C所示的连接电极72电连接至第四电路连接线N4和第八晶体管T8的栅极T80，第四电路连接线N4经由图10C所示的连接电极73电连接至第十晶体管T10的栅极T100。例如，第三电容器C3的第二电极板C32经由图10C所示的连接电极67电连接至第四晶体管T4的栅极T40。
图13A-图13F是示出根据本公开另一些实现方式的发光控制驱动单元中的不同层的布局示意图。图14A是图13A所示的221A2的放大示意图。图14B是图13A所示的221A1的放大示意图。
下面结合图13A-图13F、以及图14A-图14B对发光控制驱动电路22的发光控制驱动单元221的另一些拆分方式进行介绍。
参见图13A，第二组电路连接线包括第四电路连接线N4和第五电路连接线N5、第六电路连接线N6和第七电路连接线N7。第一发光控制驱动子电路221A1包括第一子电路221A11和第二子电路221A12，第二发光控制驱动子电路221A2包括第三子电路221A21和第四子电路221A22。第三子电路221A21经由第六电路连接线N6电连接至第一电源线VGL，第三子电路221A21经由第七电路连接线N7电连接至第二电源线VGH。这种情况下，第二发光控制驱动子电路221A2可以不包括第三电源线VGL’和第四电源线VGH’，从而减小第二发光控制驱动子电路221A2占用的空间，进而减小发光控制驱动单元221占用的空间。
图15是示出根据本公开另一个实施例的发光控制驱动单元的电路示意图。
下面结合图15、图13A-图13F、以及图14A-图14B介绍第一组晶体管GT1和第二组晶体管GT2另一些具体实现方式。在这些实现方式中，第四子电路221A22还包括第三电容器C3。
参见图15，第二组晶体管GT2位于线L1的左侧，第一组晶体管GT1位于线L1的右侧。第二组晶体管GT2包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。第一组晶体管GT1包括第八晶体管T8、第九晶体管T9和第十晶体管T10
第一子组晶体管GT11位于线L1的右侧和线L2的下侧，第二子组晶体管GT12 位于线L1的右侧和线L2的上侧，第三子组晶体管GT21位于线L1的左侧和线L2的左侧，第四子组晶体管GT22位于线L1的左侧和线L2的右侧。第一子组晶体管GT11包括第十晶体管T10，第二子组晶体管GT12包括第八晶体管T8和第九晶体管T9，第三子组晶体管GT21包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5，第四子组晶体管GT22包括第六晶体管T6和第七晶体管T7。
类似地，第一组晶体管GT1和第二组晶体管GT2中的每个晶体管包括栅极和有源层。有源层包括第一电极区、第二电极区和位于第一电极区和第二电极区之间的沟道。例如，第一晶体管T1包括栅极T10和有源层，有源层包括第一电极区T11、第二电极区T12、以及位于第一电极区T11和第二电极区T12之间的沟道T13，以此类推。晶体管T2-T10的有源层依次包括沟道T23、沟道T33、沟道T43、沟道T53、沟道T63、沟道T73、沟道T83、沟道T93和沟道T103。
第一晶体管T1的栅极T10电连接至第一时钟信号线ECK，第一晶体管T1的第一电极区T11作为第二输入端IN2。例如，第二输入端IN2电连接至第二输入电极35，以接收第二输入信号。
第二晶体管T2的栅极T20电连接至第一晶体管T1的第二电极区T12，第二晶体管T2的第一电极区T21电连接至第一晶体管T1的栅极T10。例如，第二晶体管T2的栅极T20经由图13C所示的连接电极74电连接至第一晶体管T1的第二电极区T12。例如，第二晶体管T2的第一电极区T21经由图13C所示的连接电极75电连接至第一晶体管T1的栅极T10。
第三晶体管T3的栅极电连接至第二晶体管T2的第二电极区T22，第三晶体管T3的第一电极区T31经由第七电路连接线N7电连接至第二电源线VGH。例如，第三晶体管T3的栅极经由图13C所示的连接电极76电连接至第二晶体管T2的第二电极区T22。例如，第三晶体管T3的第一电极区T31经由图13C所示的连接电极77电连接至第七电路连接线N7，第七电路连接线N7经由过孔电连接至第二电源线VGH。
第四晶体管T4的栅极T40电连接至第二时钟信号线ECB，第四晶体管T4的第一电极区T41电连接至第三晶体管T3的第二电极区T32，第四晶体管T4的第二电极区T42电连接至第二晶体管T2的栅极T20。例如，第四晶体管T4的第一电极区T41和第三晶体管T3的第二电极区T32一体设置。例如，第四晶体管T4的第二电极区T42经由图13C所示的连接电极78电连接至第二晶体管T2的栅极T20。
第五晶体管T5的栅极T50电连接至第一晶体管T1的栅极T10，第五晶体管T5的第一电极区T51经由第六电路连接线N6电连接至第一电源线VGL，第五晶体管T5的第二电极区T52电连接至第二晶体管T2的第二电极区T22。例如，第五晶体管T5的栅极T50和第一晶体管T1的栅极T10一体设置。例如，第五晶体管T5的第一电极区T51经由图13C所示的连接电极79电连接至第六电路连接线N6，第六电路连接线N6经由过孔电连接至第一电源线VGL。例如，第五晶体管T5的第二电极区T52经由图13C所示的连接电极76电连接至第二晶体管T2的第二电极区T22。
第六晶体管T6的栅极T60电连接至第三晶体管T3的栅极T30。例如，第六晶体管T6的栅极T60经由图13C所示的连接电极76电连接至第三晶体管T3的栅极T30。
第七晶体管T7的栅极T70电连接至第六晶体管T6的第一电极区T61和第二时钟信号线ECB，第七晶体管T7的第一电极区T61电连接至第六晶体管T6的第二电极区T61。例如，第七晶体管T7的栅极T70经由图13C所示的连接电极84电连接至第六晶体管T6的第一电极区T61。例如，第七晶体管T7的第二电极区T71经由图13C所示的连接电极80电连接至第六晶体管T6的第一电极区T61。
第八晶体管T8的栅极T80经由第四电路连接线N4电连接至第二晶体管T2的栅极T20，第八晶体管T8的第一电极区T81电连接至第二电源线VGH，第八晶体管T8的第二电极区T82经由第五电路连接线N5电连接至第七晶体管T7的第二电极区T72。例如，第八晶体管T8的栅极T80和第四电路连接线N4一体设置。例如，第四电路连接线N4经由图13C所示的连接电极78电连接至第二晶体管T2的栅极T20。例如，第八晶体管T8的第二电极区T82经由图13C所示的连接电极81电连接至第五电路连接线N5，第五电路连接线N5经由图13C所示的连接电极82电连接至第七晶体管T7的第二电极区T72。
第九晶体管T9的栅极T90经由第五电路连接线N5电连接至第七晶体管T7的第二电极区T72，第九晶体管T9的第一电极区T91电连接至第二电源线VGH，第九晶体管T9的第二电极区T92经由第二输出电极36电连接至第一发光控制线141和第二发光控制线142。
第十晶体管T10的栅极T100经由第四电路连接线N4电连接至第二晶体管T2的栅极T20，第十晶体管T10的第一电极区T11电连接至第二输出电极36，第十晶体管T10的第二电极区T12电连接至第一电源线VGL。例如，第十晶体管T10的栅极T100经由图13C所示的连接电极83电连接至第四电路连接线N4。
第一电容器C1的第一电极板C11电连接至第六晶体管T6的栅极T60，第一电容器C1的第二电极板C12电连接至第六晶体管T6的第一电极区T61和第七晶体管T7的第一电极区T71。例如，第一电容器C1的第一电极板C11和第六晶体管T6的栅极T60一体设置。例如，第一电容器C1的第二电极板C12经由图13C所示的连接电极80电连接至第六晶体管T6的第一电极区T61和第七晶体管T7的第一电极区T71。
第二电容器C2的第一电极板C21电连接至第九晶体管T9的栅极T90，第二电容器C2的第二电极板C22电连接至第二电源线VGH。例如，第二电容器C2的第一电极板C21和第九晶体管T9的栅极T90一体设置。
第三电容器C3的第一电极板C31电连接至第七晶体管T7的栅极T70，第三电容器C3的第二电极板C32电连接至第四电路连接线N4。例如，第三电容器C3的第一电极板C31和第七晶体管T7的栅极T70一体设置。例如，第三电容器C3的第二电极板C32经由图13C所示的连接电极78电连接至第四电路连接线N4。
如上介绍了根据本公开不同实施例的栅极驱动单元211和发光控制驱动单元221的多种拆分方式。在后面的介绍中，栅极驱动单元211和发光控制驱动单元221可以通过上文介绍的方式进行拆分。
发明人还注意到，在将栅极驱动单元211和发光控制驱动单元221拆分为多个子电路的情况下，不同子电路之间的电路连接线可能会对子像素12造成不利影响。相关技术中，电路连接线可能会与像素驱动电路122中的有源层交叠以形成晶体管，从而影响子像素12的正常显示，进而影响显示面板的显示效果。
有鉴于此，本公开实施例还提供了如下技术方案。
图16A是示出根据本公开另一个实施例的多个栅极驱动子电路的分布示意图。图16B是示出根据本公开一个实施例的子像素的局部截面示意图。
参见图1B、图2和图16A和图16B，显示面板包括衬底基板11、多个子像素12、多条栅极线13、多条发光控制线14、栅极驱动电路21和栅极驱动子电路连接线23。
衬底基板11包括显示区111和围绕显示区111的周边区112。多个子像素12位于显示区111。每个子像素12包括发光元件121和被配置为驱动发光元件121的像素驱动电路122。多条栅极线13位于显示区111，并且电连接至多个子像素12。
栅极驱动电路21位于显示区111，并且包括级联的多级栅极驱动单元211。多级栅极驱动单元211电连接至多条栅极线13。例如，多级栅极驱动单元211一一对应地电连接至多条栅极线13。
如图16A所示，多级栅极驱动电路211中的一级或多级栅极驱动单元211包括多个栅极驱动子电路211A。多个栅极驱动子电路211A包括第一栅极驱动子电路211A1和第二栅极驱动子电路211A2，第一栅极驱动子电路211A1和第二栅极驱动子电路211A2由多个子像素12中的第一组子像素P1的像素驱动电路122间隔开。
栅极驱动子电路连接线23位于显示区111。栅极驱动子电路连接线23的一端电连接至第一栅极驱动子电路211A1，栅极驱动子电路连接线23的另一端电连接至第二栅极驱动子电路211A2。
第一组子像素P1中的至少一个子像素12的像素驱动电路122包括第一像素驱动子电路122A和第二像素驱动子电路122B。第一像素驱动子电路122A位于栅极驱动子电路连接线23的一侧，第二像素驱动子电路122B位于栅极驱动子电路连接线23远离第一像素驱动子电路122A的一侧。
第一像素驱动子电路122A包括驱动晶体管M3，例如图1B所示的驱动晶体管M3。参见图16B，驱动晶体管M3包括位于衬底基板11一侧的第一有源层M34。例如，第一有源层M34的材料包括多晶硅等半导体材料。
连接件122C的一端电连接至第一像素驱动子电路122A，连接件122C的另一端电连接至第二像素驱动子电路122A2。连接件122C在衬底基板11上的正投影与栅极驱动子电路连接线23在衬底基板11上的正投影交叠，并且，连接件122C与第一有源层T14位于不同层。
需要说明的是，在本公开实施例中，多个部件位于不同层是指多个部件是通过对不同材料层进行多次构图工艺而形成的，多个部件位于同一层是指多个部件是通过对同一材料层进行一次构图工艺而形成的。因此，连接件122C的材料与第一有源层M34的材料不同。
上述实施例中，连接件122C与第一有源层M34位于不同层，栅极驱动子电路连接线23与连接件122C之间不会形成晶体管。因此，至少减轻了由于栅极驱动子电路连接线23与连接件122C之间形成晶体管导致的显示面板的显示效果下降的问题。
在一些实施例中，参见图16B，驱动晶体管M3还包括位于第一有源层M34远离衬底基板11一侧的第一栅极M30、位于第一栅极M30远离衬底基板11一侧的第一绝缘层123、位于第一绝缘层123远离衬底基板11一侧的第二绝缘层124、以及位于第二绝缘层124远离衬底基板11一侧且电连接至第一有源层M34的第一电极M3A(例如漏极)和第二电极M3B(例如源极)。在一些实施例中，驱动晶体管M3还包括位 于第一有源层M34远离衬底基板11一侧的栅极电介质层122，第一栅极M30位于栅极电介质层122远离衬底基板11的一侧。例如，第一电极M3A和第二电极M3B分别通过贯穿第二绝缘层124、第一绝缘层123和栅极电介质层122的过孔电连接至第一有源层M34。
图16B还示出了发光元件121。例如，发光元件121包括阳极1211、位于阳极1211远离衬底基板11一侧的功能层1212和位于功能层1212远离衬底基板11一侧的阴极1213。例如，发光元件121的阳极1211与驱动晶体管M3的第一电极M3A电连接。这里，功能层1212至少包括发光层，例如有机发光层。在某些实施例中，功能层1212还可以包括电子传输层、电子注入层、空穴传输层和空穴注入层中的一层或多层。
在一些实施例中，参见图16B，子像素12还可以包括位于衬底基板11与第一有源层M34之间的缓冲层120、覆盖第一电极M3A和第二电极M3B的平坦化层125、用于限定多个子像素12的像素界定层126、支撑层127及封装层128。例如，发光元件121的阳极1211可以通过贯穿平坦化层125的过孔与驱动晶体管M3的第一电极M3A电连接。例如，像素界定层126具有对应多个子像素12的多个开口，多个子像素12的发光元件121位于多个开口中。例如，封装层128可以包括薄膜封装层。在一些实施例中，封装层128可以包括第一无机层1281、第二无机层1282、以及位于第一无机层1281和第二无机层1282之间的有机层1283。
作为一些实现方式，第二绝缘层125、第一绝缘层124、栅极电介质层122、缓冲层120、平坦化层125、像素界定层126、支撑层127中的一层或多层可以包括诸如聚酰亚胺、树脂材料等的有机绝缘材料，或者，包括硅的氧化物、硅的氮化物、硅的氮氧化物等的无机绝缘材料。
参见图16B，第一像素驱动子电路122A还包括存储电容Cst。存储电容Cst包括与第一栅极M30位于同一层的第一电极板Cst1、以及位于第一绝缘层123和第二绝缘层124之间的第二电极板Cst2。应理解，存储电容Cst还包括位于第一电极板Cst1和第二电极板Cst2之间的第一绝缘层123。
例如，栅极驱动子电路连接线23与第一栅极M30位于同一层，第二电极板Cst2、第一电极M3A和第二电极M3B中的至少一个与连接件122C位于同一层。换言之，栅极驱动子电路连接线23和连接件122C之间至少设置有第一绝缘层123。
在一些实现方式中，栅极驱动子电路连接线23与第一栅极M30位于同一层，第二电极板Cst2和连接件122C位于同一层。这种情况下，栅极驱动子电路连接线23 和连接件122C之间设置有第一绝缘层123，减小了栅极驱动子电路连接线23对子像素12的不利影响。
在另一些实现方式中，栅极驱动子电路连接线23与第一栅极M30位于同一层，第一电极M3A、第二电极M3B和连接件122C位于同一层。这种情况下，栅极驱动子电路连接线23和连接件122C之间设置有第一绝缘层123和第二绝缘层124，进一步减小了栅极驱动子电路连接线23对子像素12的不利影响。
在栅极驱动单元211通过图4A-图4F所示方式拆分为多个栅极驱动子电路211A的情况下，栅极驱动子电路连接线23可以是图4A所示的第二电路连接线N2。换言之，图4A所示的第二电路连接线N2与图16B所示的第一栅极M30位于同一层，图4C所示的连接件122C、以及图16B所示的第一电极M3A和第二电极M3B位于同一层。另外，在某些实施例中，图4A所示的第一电路连接线N1与图16B所示的第一栅极M30位于同一层，与第一电路连接线N1交叠的连接件122C、图16B所示的第一电极M3A和第二电极M3B位于同一层。
在栅极驱动单元211通过图7A-图7F所示方式拆分为多个栅极驱动子电路211A的情况下，栅极驱动子电路连接线23可以是图7A所示的第一电路连接线N1。换言之，图7A所示的第一电路连接线N1与图16B所示的第一栅极M30位于同一层，图7C所示的连接件122C、以及图16B所示的第一电极M3A和第二电极M3B位于同一层。另外，在某些实施例中，图7A所示的第二电路连接线N2、第三电路连接线N3与图16B所示的第一栅极M30位于同一层，与第二电路连接线N2交叠的连接件122C、与第三电路连接线N3交叠的连接件122C与图16B所示的第一电极M3A和第二电极M3B位于同一层。
图17A是示出根据本公开一个实施例的栅极驱动子电路连接线与连接件交叠的布局示意图。图17B是沿着图17A所示的A-A’截取的截面示意图。
如图17A所示，第一像素驱动子电路122A、第二像素驱动子电路122B和连接件122C组成第一组子像素P1中的某个子像素12。连接件122C的一端经由过孔VC1电连接至第一像素驱动子电路122A，连接件122C的另一端经由过孔VC2电连接至第二像素驱动子电路122B。
如图17B所示，栅极驱动子电路连接线23与图16B所示的第一栅极T10位于同一层，连接件122C与图16B所示的第一电极T1A和第二电极T1B位于同一层。
在一些实施例中，参见图17A和图17B，至少一个子像素12还包括屏蔽层129。 例如，如图17A所示，屏蔽层129可以经由过孔V161电连接至电源线16。例如，如图17B所示，屏蔽层129可以与图16B所示的第二电极板Cst2位于同一层。另外，连接件122C和栅极驱动子电路连接线23在衬底基板11上的正投影与屏蔽层129在衬底基板11上的正投影至少部分交叠。这样的方式下，屏蔽层129可以减小栅极驱动子电路连接线23和连接件122C之间的相互影响。
在一些实施例中，连接件122C在衬底基板11上的正投影和栅极驱动子电路连接线23在衬底基板11上的正投影重叠的部分位于屏蔽层129在衬底基板11上的正投影之内。这样的方式下，屏蔽层129可以更有效地减小栅极驱动子电路连接线23和连接件122C之间的相互影响。
图18是示出根据本公开另一个实施例的多个发光控制驱动子电路的分布示意图。
在一些实施例中，参见图2和图18，显示面板还包括位于显示区111的发光控制驱动电路22和发光控制驱动子电路连接线24。
发光控制驱动电路22包括电连接至多条发光控制线14的级联的多级发光控制驱动单元221。如图18所示，多级发光控制驱动单元221中的一级或多级发光控制驱动单元221包括多个发光控制驱动子电路221A。多个发光控制驱动子电路221A包括第一发光控制驱动子电路221A1和第二发光控制驱动子电路221A2，第一发光控制驱动子电路221A1和第二发光控制驱动子电路221A2由多个子像素12中的第二组子像素P2的像素驱动电路122间隔开。发光控制驱动子电路连接线24的一端电连接至第一发光控制驱动子电路221A1，发光控制驱动子电路连接线24的另一端电连接至第二发光控制驱动子电路221A2。
第二组子像素P2中的至少一个子像素12的像素驱动电路122包括第一像素驱动子电路122A和第二像素驱动子电路122B。第一像素驱动子电路122A位于发光控制驱动子电路连接线24的一侧，第二像素驱动子电路122B位于发光控制驱动子电路连接线24远离第一像素驱动子电路122A的一侧。连接件122C的一端电连接至第一像素驱动子电路122A，连接件122C的另一端电连接至第二像素驱动子电路122B。
连接件122C在衬底基板11上的正投影与发光控制驱动子电路连接线24在衬底基板11上的正投影交叠，并且，连接件122C与第一有源层M34位于不同层。例如，发光控制驱动子电路连接线24与图16B所示的第一栅极M30位于同一层，连接件122C与图16B所示的第一电极M3A和第二电极M3B位于同一层。
上述实施例可以减小发光控制驱动子电路连接线24对子像素12的不利影响，提 高显示面板的显示效果。
与上类似地，发光控制驱动子电路连接线24和连接件122C之间可以设置有上述屏蔽层129，以减小发光控制驱动子电路连接线24和连接件122C之间的相互影响。
图19是示出根据本公开一个实施例的子像素中的部分层的布局示意图。
下面结合图1B、图2和图19介绍第一像素驱动子电路122A和第二像素驱动子电路122B的一些具体实现方式。
参见图2，显示面板还包括多条发光控制线14、多条电源线16、多条初始化线17和多条复位线18。多条发光控制线14、多条电源线16、多条初始化线17和多条复位线18均位于显示区111，并且电连接至多个子像素12。
参见图1B，第一像素驱动子电路122A位于线L的右侧，第二像素驱动子电路122B位于线L的左侧。
第一像素驱动子电路122A包括驱动晶体管M3、多个晶体管MT和存储电容Cst，多个晶体管MT包括第一发光控制晶体管M6。驱动晶体管M3包括第一栅极M30和第一有源层M34。存储电容Cst包括第一电极板Cst1和第二电极板Cst2，第一电极板Cst1电连接至多条电源线16中的一条。
第二像素驱动子电路122B包括第一复位晶体管M7。第一复位晶体管M7和多个晶体管MT中的每一个包括第二栅极和第二有源层。第二有源层和第一有源层M34中每一个均包括第一电极区、第二电极区、以及位于第一电极区和第二电极区之间的沟道。例如，驱动晶体管M3的第一有源层M34包括第一电极区M31、第二电极区M32、以及位于第一电极区M31和第二电极区M32之间的沟道M33。例如，第一发光控制晶体管M6的第二有源层M64包括第一电极区M61、第二电极区M62、以及位于第一电极区M61和第二电极区M62之间的沟道M63。例如，第一复位晶体管M7的第二有源层M74包括第一电极区M71、第二电极区M72、以及位于第一电极区M71和第二电极区M72之间的沟道M73。
驱动晶体管M3的第一栅极M30电连接至存储电容Cst的第二电极板Cst2，驱动晶体管M3的第一电极区M31电连接至多条电源线16中的一条。第一发光控制晶体管M6的第二栅极M60电连接至多条发光控制线14中的一条，第一发光控制晶体管M6的第一电极区M61电连接至驱动晶体管M3的第二电极区M32，第一发光控制晶体管M6的第二电极区M62电连接至连接件122C的一端。第一复位晶体管M7的第二栅极M70电连接至多条复位线18中的一条，第一复位晶体管M7的第一电极区 M71电连接至多条初始化线17中的一条，第一复位晶体管M7的第二电极区M72电连接至连接件122C的另一端。
另外，至少一个子像素12的发光元件121的阳极1211电连接至连接件122C的一端。
下面结合图1B、图2和图19介绍多个晶体管MT的一些具体实现方式。
在一些实施例中，参见图2，显示面板还包括多条数据线15。多条数据线15位于显示区111，并且电连接至多个子像素12。参见图1B，多个晶体管MT还包括数据写入晶体管M4、第二复位晶体管M1、第二发光控制晶体管M5和阈值补偿晶体管M2。
参见图19，数据写入晶体管M4的第二栅极M40电连接至多条栅极线13中的一条，数据写入晶体管M4的第一电极区M41电连接至多条数据线15中的一条，数据写入晶体管M4的第二电极区M42电连接至驱动晶体管M3的第一电极区M31。
第二复位晶体管M1的第二栅极M10电连接至多条复位线18中的另一条，第二复位晶体管M1的第一电极区M10电连接至存储电容Cst的第二电极板Cst2，第二复位晶体管M1的第二电极区M20电连接至多条初始化线17中的另一条。换言之，第二复位晶体管M1的第二栅极M10和第一复位晶体管M7的第二栅极M70电连接至不同的复位线18。第二复位晶体管M1的第二电极区M20和第一复位晶体管M7的第一电极区M71电连接至不同的初始化线17。
第二发光控制晶体管M5的第二栅极M50电连接至多条发光控制线14中的一条，第二发光控制晶体管M5的第一电极区M51电连接至多条电源线16中的一条，第二发光控制晶体管M5的第二电极区M52电连接至驱动晶体管M3的第一电极区M31。例如，第二发光控制晶体管M5的第二栅极M50和第一发光控制晶体管M6的第二栅极M60电连接至同一条发光控制线14。
阈值补偿晶体管M2的第二栅极M20电连接至多条栅极线13中的一条，阈值补偿晶体管M2的第一电极区M21电连接至第二复位晶体管M1的第一电极区M11，阈值补偿晶体管M2的第二电极区M22电连接至驱动晶体管M3的第二电极区M32。例如，阈值补偿晶体管M2的第二栅极M20和数据写入晶体管M4的第二栅极M40电连接至同一条栅极线13。
图20是示出根据本公开一个实施例的级联的两级栅极驱动单元的示意图。
如图20所示，一级或多级栅极驱动单元211包括级联的前一级栅极驱动单元211-1 和后一级栅极驱动单元211-2。前一级栅极驱动单元211-1的第一栅极驱动子电路211A1包括前一级栅极驱动单元211-1的第一输入端IN1，前一级栅极驱动单元211-1的第二栅极驱动子电路211A2包括前一级栅极驱动单元211-1的第一输出端OUT1。后一级栅极驱动单元211-2的第一栅极驱动子电路211A1包括后一级栅极驱动单元211-2的第一输入端IN1，后一级栅极驱动单元211-2的第二栅极驱动子电路211A2包括后一级栅极驱动单元211-2的第一输出端OUT1。
下面结合图4A-图4F介绍级联的前一级栅极驱动单元211-1和后一级栅极驱动单元211-2的连接方式。
如图4A所示，相对靠上的栅极驱动单元为前一级栅极驱动单元211-1，相对靠下的栅极驱动单元为后一级栅极驱动单元211-2。前一级栅极驱动单元211-1的第一输出端OUT1电连接至多条栅极线13的第一栅极线131。例如，前一级栅极驱动单元211-1的第一输出端OUT1经由输出电极32电连接至第一栅极线131。
如图4C所示，显示面板还包括第一级联连接线CC1，位于第一组子像素P1的像素驱动电路122远离第二栅极驱动子电路211A2的一侧。第一级联连接线CC1的一端电连接至第一栅极线131，第一级联连接线CC1的另一端电连接至后一级栅极驱动单元211-2的第一输入端IN1。例如，第一级联连接线CC1的一端经由第一过孔VC1电连接至第一栅极线131，第一级联连接线CC1的另一端经由第二过孔VC2电连接至后一级栅极驱动单元211-2的第一输入端IN1。
上述实施例中，第一栅极线131横向穿过第一组子像素P1的像素驱动电路122，第一级联连接线CC1电连接至第一栅极线131和后一级栅极驱动单元211-2的第一输入端IN1。这样的方式下，无需通过额外的横向连接线将前一级栅极驱动单元211-1的第一输出端OUT1和后一级栅极驱动单元211-2的第一输入端IN1电连接，减小了栅极驱动电路占用的空间，有助于提高显示面板的分辨率。
在一些实施例中，参见图2，显示面板还包括多条复位线18。多条复位线18位于显示区111，并且电连接至多个子像素12。参见图4B，后一级栅极驱动单元121-2的第一栅极驱动子电路211A1和第二栅极驱动子电路211A2之间的第一组子像素P1的像素驱动电路122电连接至多条复位线18中的第一复位线181，第一复位线181经由第一级联连接线CC1电连接至第一栅极线131。例如，第一复位线181经由第三过孔VC3电连接至第一级联连接线CC1。
在一些实施例中，参见图4C，显示面板还包括第二级联连接线CC2，位于第一 组子像素P1远离第一栅极驱动子电路211A1的一侧。第二级联连接线CC2的一端电连接至第一栅极线131，第二级联连接线CC2的另一端电连接至第一复位线181。例如，第二级联连接线CC2的一端经由过孔VC4电连接至第一栅极线131，第二级联连接线CC2的另一端经由过孔VC5电连接至第一复位线181。在一些实施例中，第二级联连接线CC2和第一输出电极32一体设置。这样的方式下，可以确保第一栅极线131上的栅极驱动信号作为第一输入信号被输入到后一级栅极驱动单元211-2的第一输入端IN1。
在一些实施例中，驱动晶体管M3的第一电极M3A和第二电极M3B中的至少一个与第一级联连接线CC1位于同一层。在一些实施例中，驱动晶体管M3的第一电极M3A和第二电极M3B中的至少一个与第二级联连接线CC2位于同一层。
发明人还注意到，在将多个栅极驱动子电路211A分散到多个子像素12中时，栅极驱动子电路211A两侧的某些子像素12占用的空间需要被压缩。这种情况下，被压缩空间且发出同一颜色的某些子像素(例如多个红色子像素、多个绿色子像素或多个蓝色子像素)存在显示不均匀的问题，从而影响显示面板的显示效果。
有鉴于此，本公开实施例还提供了如下技术方案。
图21是示出根据本公开又一个实施例的多个栅极驱动子电路的分布示意图。图22A-22E是示出根据本公开一些实施例的不同组阳极连接线的示意图。
下面结合图2、图21、图22A-22E对根据本公开一些实施例的显示面板进行介绍。
参见图2，显示面板包括衬底基板11、多个子像素12、多条栅极线13和栅极驱动电路21。
衬底基板11包括显示区111和围绕显示区111的周边区112。多个子像素12位于显示区111。多条栅极线13位于显示区111，并且电连接至多个子像素12。栅极驱动电路21位于显示区111，并且包括级联的多级栅极驱动单元211。多级栅极驱动单元211电连接至多条栅极线13。
如图21所示，多级栅极驱动电路211中的一级或多级栅极驱动单元211包括多个栅极驱动子电路211A。多个栅极驱动子电路211A包括第一栅极驱动子电路211A1和第二栅极驱动子电路211A2。
多个子像素12包括第一组子像素P1和第二组子像素P2。第一组子像素P1和第二组子像素P2中的一组子像素的像素驱动电路122位于第一栅极驱动子电路211A1和第二栅极驱动子电路211A2之间，第一组子像素P1和第二组子像素P2中的另一组 子像素的像素驱动电路122位于第一栅极驱动子电路211A1远离第二栅极驱动子电路211A2的一侧。需要说明的是，图21示意性地示出了第一组子像素P1位于第一栅极驱动子电路211A1和第二栅极驱动子电路211A2之间、第二组子像素P2中的像素驱动电路122位于第一栅极驱动子电路211A1远离第二栅极驱动子电路211A2的一侧的情况。
参见图22A，第一组子像素P1包括被配置为发出第一颜色的光的第一子组子像素P11、被配置为发出第二颜色的光的第二子组子像素P12和被配置为发出第三颜色的光的第三子组子像素P13。在一些实施例中，第一颜色、第二颜色和第三颜色彼此不同。例如，第一颜色为红色，第二颜色为绿色，第三颜色为蓝色。
第一子组子像素P11的像素驱动电路122经由第一组阳极连接线GC1电连接至第一子组子像素P11的发光元件121的阳极P11-1211，第二子组子像素P12的像素驱动电路122经由第二组阳极连接线GC2电连接至第二子组子像素P12的发光元件121的阳极P12-1211，第三子组子像素P13的像素驱动电路122经由第三组阳极连接线GC3电连接至第三子组子像素P13的发光元件121的阳极P13-1211。
第一组阳极连接线GC1、第二组阳极连接线GC2和第三组阳极连接线GC3中的至少一组包括多条第一阳极连接线AC1。例如，第一组阳极连接线GC1、第二组阳极连接线GC2和第三组阳极连接线GC3中的每一组包括多条第一阳极连接线AC1。多条第一阳极连接线AC1包括两条第一阳极连接线AC1，并且，这两条第一阳极连接线AC1中越靠近第一栅极驱动子电路211A1的第一阳极连接线AC1的长度越大。
例如，第一组阳极连接线GC1中的多条第一阳极连接线AC1中的两条第一阳极连接线AC1中越靠近第一栅极驱动子电路211A1的第一阳极连接线AC1的长度越大。又例如，第二组阳极连接线GC2中的多条第一阳极连接线AC1中的两条第一阳极连接线AC1中越靠近第一栅极驱动子电路211A1的第一阳极连接线AC1的长度越大。再例如，第三组阳极连接线GC1中的多条第一阳极连接线AC1中的两条第一阳极连接线AC1中越靠近第一栅极驱动子电路211A1的第一阳极连接线AC1的长度越大。
上述实施例中，第一组阳极连接线GC1、第二组阳极连接线GC2和第三组阳极连接线GC3中的至少一组中的两条第一阳极连接线AC1中越靠近第一栅极驱动子电路211A1的第一阳极连接线AC1的长度越大。这样的结构有助于提高第一组子像素12的显示均一性，从而提高显示面板的显示效果。
在一些实施例中，第一组阳极连接线GC1、第二组阳极连接线GC2和第三组阳 极连接线GC3中的至少一组中的多条第一阳极连接线AC1中越靠近第一栅极驱动子电路211A1的第一阳极连接线AC1的长度越大。换言之，第一组阳极连接线GC1、第二组阳极连接线GC2和第三组阳极连接线GC3中的至少一组中的全部第一阳极连接线AC1中越靠近第一栅极驱动子电路211A1的第一阳极连接线AC1的长度越大。这样的结构有助于进一步提高第一组子像素P1的显示均一性，从而提高显示面板的显示效果。
在一些实施例中，第一组阳极连接线GC1、第二组阳极连接线GC2、第三组阳极连接线GC3中的至少一组与发光元件121的阳极1211位于同一层。这样的结构有助于工艺实现，降低工艺复杂度。在一些实现方式中，第一组阳极连接线GC1与第一子组子像素P11的发光元件121的阳极P11-1211一体设置。在一些实现方式中，第二组阳极连接线GC2与第二子组子像素P12的发光元件121的阳极P12-1211一体设置。在一些实现方式中，第三组阳极连接线GC3与第三子组子像素P13的发光元件121的阳极P13-1211一体设置。
在一些实现方式中，第一组阳极连接线GC1经由第一组过孔VP1电连接至第一子组子像素P11的像素驱动电路122；第二组阳极连接线GC2经由第二组过孔VP2电连接至第二子组子像素P12的像素驱动电路122；第三组阳极连接线GC3经由第三组过孔VP3电连接至第三子组子像素P13的像素驱动电路122。
接下来结合图22B介绍第二组子像素P2的一些实现方式。
参见图22B，第二组子像素P2包括被配置为发出第一颜色的光的第四子组子像素P21、被配置为发出第二颜色的光的第五子组子像素P22和被配置为发出第三颜色的光的第六子组子像素P23。
第四子组子像素P21的像素驱动电路122经由第四组阳极连接线GC4电连接至第四子组子像素P21的发光元件121的阳极P21-1211，第五子组子像素P22的像素驱动电路122经由第五组阳极连接线GC5电连接至第五子组子像素P22的发光元件121的阳极P22-1211，第六子组子像素P23的像素驱动电路122经由第六组阳极连接线GC6电连接至第六子组子像素P23的发光元件121的阳极P23-1211。
第四组阳极连接线GC4、第五组阳极连接线GC5和第六组阳极连接线GC6中的至少一组包括多条第二阳极连接线AC2，多条第二阳极连接线AC2中越靠近第一栅极驱动子电路211A1的第二阳极连接线的长度越大。例如，第四组阳极连接线GC4、第五组阳极连接线GC5和第六组阳极连接线GC6中的每一组均包括多条第二阳极连 接线AC2，多条第二阳极连接线AC2中越靠近第一栅极驱动子电路211A1的第二阳极连接线的长度越大。这样的结构有助于提高第二组子像素P2的显示均一性，从而进一步提高显示面板的显示效果。
在一些实施例中，参见图21，多个子像素12还包括第三组子像素P3和第四组子像素P4。第三组子像素P3和第四组子像素P4中的一组子像素的像素驱动电路122位于第二栅极驱动子电路211A2靠近第一栅极驱动子电路211A1、第一组子像素P1和第二组子像素P2的一侧，另一组子像素的像素驱动电路122位于第二栅极驱动子电路211A2远离第一栅极驱动子电路211A1的一侧。这里，图21示意性地示出了第四组子像素P4的像素驱动电路122位于第二栅极驱动子电路211A2靠近第一栅极驱动子电路211A1、第一组子像素P1和第二组子像素P2的一侧，第三组子像素P3的像素驱动电路122位于第二栅极驱动子电路211A2远离第一栅极驱动子电路211A1的一侧的情况。
下面结合图22C介绍第三组子像素P3的一些实现方式。
参见图22C，第三组子像素P3包括被配置为发出第一颜色的光的第七子组子像素P31、被配置为发出第二颜色的光的第八子组子像素P32和被配置为发出第三颜色的光的第九子组子像素P33。
第七子组子像素P31的像素驱动电路122经由第七组阳极连接线GC7电连接至第七子组子像素P31的发光元件121的阳极P31-1211，第八子组子像素P32的像素驱动电路122经由第八组阳极连接线GC8电连接至第八子组子像素P32的发光元件121的阳极P32-1211，第九子组子像素P33的像素驱动电路122经由第九组阳极连接线GC9电连接至第九子组子像素P33的发光元件121的阳极P33-1211。
第七组阳极连接线GC7、第八组阳极连接线GC8和第九组阳极连接线GC9中的至少一组包括多条第三阳极连接线AC3，多条第三阳极连接线AC3中越靠近第二栅极驱动子电路211A2的阳极连接线的长度越大。例如，第七组阳极连接线GC7、第八组阳极连接线GC8和第九组阳极连接线GC9中的每一组均包括多条第三阳极连接线AC3，多条第三阳极连接线AC3中越靠近第二栅极驱动子电路211A2的阳极连接线的长度越大。这样的结构有助于提高第三组子像素P3的显示均一性，从而进一步提高显示面板的显示效果。
下面结合图22D介绍第四组子像素P4的一些实现方式。
参见图22D，第四组子像素P4包括被配置为发出第一颜色的光的第十子组子像 素P41、被配置为发出第二颜色的光的第十一子组子像素P42和被配置为发出第三颜色的光的第十二子组子像素P43。
第十子组子像素P41的像素驱动电路122经由第十组阳极连接线GC10电连接至第十子组子像素P41的发光元件121的阳极P41-1211，第十一子组子像素P42的像素驱动电路122经由第十一组阳极连接线GC11电连接至第十一子组子像素P42的发光元件121的阳极P42-1211，第十二子组子像素P43的像素驱动电路122经由第十二组阳极连接线GC12电连接至第十二子组子像素P43的发光元件121的阳极P43-1211。
第十组阳极连接线GC10、第十一组阳极连接线GC11和第十二组阳极连接线GC12中的至少一组包括多条第四阳极连接线AC4，多条第四阳极连接线AC4中越靠近第二栅极驱动子电路211A2的阳极连接线的长度越大。例如，第十组阳极连接线GC10、第十一组阳极连接线GC11和第十二组阳极连接线GC12中的每一组均包括多条第四阳极连接线AC4，多条第四阳极连接线AC4中越靠近第二栅极驱动子电路211A2的阳极连接线的长度越大。这样的结构有助于提高第四组子像素P4的显示均一性，从而进一步提高显示面板的显示效果。
在一些实施例中，参见图21，显示面板的多个子像素12还包括第五组子像素P5。第五组子像素P5的像素驱动电路122位于第一组子像素P1的像素驱动电路122和第四组子像素P4的像素驱动电路122之间，第一组子像素P1的像素驱动电路122位于第一栅极驱动子电路211A1和第五组子像素P5的像素驱动电路122之间，第四组子像素P4的像素驱动电路122位于第五组子像素P5的像素驱动电路122和第二栅极驱动子电路211A2之间。
下面结合图22D介绍第五组子像素P5的一些实现方式。
参见图22D，第五组子像素P5包括被配置为发出第一颜色的光的第十三子组子像素P51、被配置为发出第二颜色的光的第十四子组子像素P52和被配置为发出第三颜色的光的第十五子组子像素P53。
第十三子组子像素P51的像素驱动电路122经由第十三组阳极连接线GC13电连接至第十三子组子像素P51的发光元件121的阳极P51-1211，第十四子组子像素P52的像素驱动电路122经由第十四组阳极连接线GC14电连接至第十四子组子像素P52的发光元件121的阳极P52-1211，第十五子组子像素P53的像素驱动电路122经由第十五组阳极连接线GC15电连接至第十五子组子像素P53的发光元件121的阳极P53-1211。
这里，第十三组阳极连接线GC13的长度相同，第十四组阳极连接线GC14的长度相同，第十五组阳极连接线GC15的长度相同。
在显示面板包括上述第一组子像素P1、第二组子像素P2、第三组子像素P3、第四组子像素P4和第五组子像素P5的情况下，第一组子像素P1、第二组子像素P2、第三组子像素P3和第四组子像素P4的像素驱动电路在第一方向上的尺寸被压缩。换言之，第一栅极驱动子电路211A1两侧的子像素在第一方向上的尺寸被压缩，第二栅极驱动子电路211A2两侧的子像素在第一方向上的尺寸被压缩。这样的结构有利于提高显示面板的显示均一性，从而提高显示面板的显示效果。
发明人还注意到，在显示面板利用多路复用电路的情况下，显示面板会存在显示均一性差的问题。发明人经过研究发现，相关技术中，向多路复用电路提供控制信号的控制信号线与显示区的边缘具有类似的形状。例如，显示区具有类似台阶状的边缘，控制信号线同样具有类似台阶状。这样的控制信号线的长度相对较大，导致控制信号线的电阻较大，使得控制信号线上的电压降较大，进而使得子像素不能正常开启或关闭，影响显示面板的显示效果。
有鉴于此，本公开实施例还提供了如下技术方案。
图23A是示出根据本公开又一个实施例的显示面板的结构示意图。图23B是图23A所示圈B的放大示意图。
下面结合图23A、图23B、图3A介绍根据本公开一些实施例的显示面板。
参见图23A，显示面板包括衬底基板11、多个子像素12、多条栅极线13、栅极驱动电路21、多条控制信号线19、多条数据信号输入线20和多路复用电路MX。
衬底基板11包括显示区111和围绕显示区111的周边区112。周边区112包括第一周边区112A，第一周边区112A远离显示区11的边缘具有大于0的第一曲率。例如，第一周边区112A远离显示区11的边缘具有弧度，例如圆弧等。这里，在周边区112远离显示区11的边缘整体均具有大于0的曲率(例如圆环)的情况下，第一周边区112A可以是周边区112的任意一个部分；在周边区112远离显示区11的边缘部分具有大于0的曲率(例如拐角部分)的情况下，第一周边区112A可以是周边区112的拐角部分，例如四个拐角区之一。
多个子像素12位于显示区111。多条栅极线13位于显示区111，并且电连接至多个子像素12。栅极驱动电路21位于显示区111，并且包括级联的多级栅极驱动单元211。多级栅极驱动单元211电连接至多条栅极线13。
参见图3A，多级栅极驱动电路211中的一级或多级栅极驱动单元211包括多个栅极驱动子电路211A。多个栅极驱动子电路211A包括第一栅极驱动子电路211A1和第二栅极驱动子电路211A2。第一栅极驱动子电路211A1和第二栅极驱动子电路211A2由多个子像素12中的第一组子像素P1的像素驱动电路122间隔开。
参见图23B，多条控制信号线19、多条数据信号输入线20和多路复用电路MX至少位于第一周边区112A。多条控制信号线19中的至少一条的至少部分具有大于0的第二曲率。例如，多条控制信号线19的每一条具有大于0的第二曲率。在一些实施例中，第二曲率与第一曲率相同。作为一些实现方式，每条控制信号线19为圆弧形。
多路复用电路MX位于多条控制信号线19和显示区111之间。多路复用电路MX包括多个多路复用单元MX1，多个多路复用单元MX1中的每一个电连接至多条控制信号线19、多条数据信号输入线20中的一条数据信号输入线20和多条数据线15中的至少两条数据线15。
上述实施例中，多条控制信号线19中的至少一条的至少部分具有大于0第二曲率。这样的结构有助于减小控制信号线19的长度，降低控制信号线19的电阻，从而提高显示面板的显示均一性。
在一些实施例中，参见图23B，显示面板还包括电源总线VDD，被配置为向显示区111的电源线16提供电源电压。例如，电源总线VDD位于多条控制信号线19远离显示区111的一侧。
在一些实施例中，参见图23B，多个子像素12包括在第一方向上排布且相邻的第一行子像素C1和第二行子像素C2，第一行子像素C1的数量大于第二行子像素C2的数量。多个多路复用单元MX中的至少一个至少部分地位于第一周边区112A的第一区域112A1。这里，第一区域112A1在第一方向上位于第二行子像素C2远离显示区111的一侧，并且第一区域112A1在与第一方向垂直的第二方向上位于第一行子像素C1远离显示区11的一侧。例如，第一区域112A1在第一方向上位于第二行子像素C2的左侧，第一区域112A1在第二方向上位于第一行子像素C1的下侧。
例如，第一行子像素C1的左边缘所在的第一直线、第一行子像素C1的下边缘所在的第二直线、第二行子像素C2的左边缘所在的第三直线、以及第二行子像素C2的下边缘所在的第四直线所围成的封闭空间可以视为第一区域112A1。应理解，第一周边区112A可以包括多个第一区域112A1。
在一些实施例中，参见图23B，显示面板还包括多条控制信号连接线19A，多条控制信号线19经由多条控制信号连接线19A电连接至多个多路复用单元MX。例如，多条控制信号线19一一对应地电连接至多条控制信号连接线19A，多条控制信号连接线19A一一对应地电连接至多个多路复用单元MX。
在一些实施例中，多条控制信号连接线19A的延伸方向和多条数据线15(参见图23A)的延伸方向相同，即沿着第二方向延伸。这样的方式下，有助于减小控制信号连接线19A的长度，降低控制信号连接线19A的电阻，从而有助于提高显示面板的显示均一性。
图24是示出图23B的局部示意图。下面结合图24介绍多路复用单元MX的结构示意图。
参见图24，多个多路复用单元MX中的每一个包括与多条控制信号线19和至少两条数据线15一一对应的多个开关晶体管SW。作为示例，多个多路复用单元MX中的每一个包括6个开关晶体管，多条控制信号线19的数量为6，至少两条数据线15的数量为6。例如，6个开关晶体管中的3个开关晶体管位于某一个第一区域112A1，另外3个开关晶体管位于另一个第一区域112A1。
多个开关晶体管SW中的每一个的栅极SW0电连接至多条控制信号线19中的一条对应的控制信号线19，多个开关晶体管SW中的每一个的第一电极SW1电连接至多条数据信号输入线20中的一条对应的数据信号输入线20，多个开关晶体管SW中的每一个的第二电极SW2电连接至至少两条数据线15中的一条对应的数据线15。例如，每个开关晶体管SW的栅极SW0经由一条对应的控制信号连接线19电连接至一条对应的控制信号线19。
需要说明的是，本公开不同实施例提供的显示面板的技术方案可以相互组合，以得到多个实施例的显示面板。
本公开实施例还提供了多种显示面板的制造方法。
图25是示出根据本公开一个实施例的显示面板的制造方法的流程示意图。
在步骤252，提供衬底基板，衬底基板包括显示区和围绕显示区的周边区。
在步骤254，在显示区形成多个子像素、多条栅极线、多条发光控制线、栅极驱动电路和发光控制驱动电路。
每个子像素包括发光元件和被配置为驱动发光元件的像素驱动电路。多条栅极线电连接至多个子像素，多条发光控制线电连接至多个子像素。栅极驱动电路包括级联 的多级栅极驱动单元，多级栅极驱动单元电连接至多条栅极线，多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路，第一栅极驱动子电路和第二栅极驱动子电路由多个子像素中的第一组子像素的像素驱动电路间隔开。发光控制驱动电路包括级联的多级发光控制驱动单元，多级发光控制驱动单元电连接至多条发光控制线，多级发光控制驱动单元中的一级或多级发光控制驱动单元包括多个发光控制驱动子电路，多个发光控制驱动子电路包括第一发光控制驱动子电路和第二发光控制驱动子电路，第一发光控制驱动子电路和第二发光控制驱动子电路由多个子像素中的第二组子像素的像素驱动电路间隔开。
上述实施例中，栅极驱动电路和发光控制驱动电路均位于显示区。栅极驱动电路的至少一级栅极驱动单元包括分布在多个子像素的像素驱动电路中的多个栅极驱动子电路，发光控制驱动电路的至少一级发光控制驱动单元包括分布在多个子像素的像素驱动电路中的多个发光控制驱动子电路。这样的结构有利于减小显示面板的边框尺寸。
图26是示出根据本公开另一个实施例的显示面板的制造方法的流程示意图。
在步骤262，提供衬底基板，衬底基板包括显示区和围绕显示区的周边区。
在步骤264，在显示区形成多个子像素、多条栅极线、栅极驱动电路和栅极驱动子电路连接线。
每个子像素包括发光元件和被配置为驱动发光元件的像素驱动电路，多条栅极线电连接至多个子像素，栅极驱动电路包括级联的多级栅极驱动单元。多级栅极驱动单元电连接至多条栅极线，多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路，第一栅极驱动子电路和第二栅极驱动子电路由多个子像素中的第一组子像素的像素驱动电路间隔开。
栅极驱动子电路连接线的一端电连接至第一栅极驱动子电路，栅极驱动子电路连接线的另一端电连接至第二栅极驱动子电路。
第一组子像素中的至少一个子像素的像素驱动电路包括第一像素驱动子电路、第二像素驱动子电路和连接件。第一像素驱动子电路位于栅极驱动子电路连接线的一侧，并且包括驱动晶体管，驱动晶体管包括位于衬底基板一侧的第一有源层。第二像素驱动子电路位于栅极驱动子电路连接线远离第一像素驱动子电路的一侧。连接件的一端 电连接至第一像素驱动子电路，连接件的另一端电连接至第二像素驱动子电路，连接件在衬底基板上的正投影与栅极驱动子电路连接线在衬底基板上的正投影交叠，连接件与第一有源层位于不同层。
上述实施例中，连接件与第一有源层位于不同层，栅极驱动子电路连接线与连接件之间不会形成晶体管。因此，至少减轻了由于栅极驱动子电路连接线与连接件之间形成晶体管导致的显示面板的显示效果下降的问题。
图27是示出根据本公开又一个实施例的显示面板的制造方法的流程示意图。
在步骤272，提供衬底基板，衬底基板包括显示区和围绕显示区的周边区。
在步骤274，在显示区形成多个子像素、多条栅极线和栅极驱动电路。
每个子像素包括发光元件和被配置为驱动发光元件的像素驱动电路，多条栅极线电连接至多个子像素。栅极驱动电路包括级联的多级栅极驱动单元，多级栅极驱动单元电连接至多条栅极线，多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路。
多个子像素包括第一组子像素和第二组子像素，第一组子像素和第二组子像素中的一组子像素的像素驱动电路位于第一栅极驱动子电路和第二栅极驱动子电路之间，第一组子像素和第二组子像素中的另一组子像素的像素驱动电路位于第一栅极驱动子电路远离第二栅极驱动子电路的一侧。
第一组子像素包括：第一子组子像素，被配置为发出第一颜色的光，第一子组子像素的像素驱动电路经由第一组阳极连接线电连接至第一子组子像素的发光元件的阳极；第二子组子像素，被配置为发出第二颜色的光，第二子组子像素的像素驱动电路经由第二组阳极连接线电连接至第二子组子像素的发光元件的阳极；和第三子组子像素，被配置为发出第三颜色的光，第三子组子像素的像素驱动电路经由第三组阳极连接线电连接至第三子组子像素的发光元件的阳极。
第一组阳极连接线、第二组阳极连接线和第三组阳极连接线中的至少一组包括多条第一阳极连接线，多条第一阳极连接线包括两条第一阳极连接线，两条第一阳极连接线中越靠近第一栅极驱动子电路的第一阳极连接线的长度越大。
上述实施例中，第一组阳极连接线、第二组阳极连接线和第三组阳极连接线中的至少一组中的两条第一阳极连接线中越靠近第一栅极驱动子电路的第一阳极连接线的长度越大。这样的结构有助于提高第一组子像素的显示均一性，从而提高显示面板的显示效果。
图28是示出根据本公开再一个实施例的显示面板的制造方法的流程示意图。
在步骤282，提供衬底基板，衬底基板包括显示区和围绕显示区的周边区，周边区包括第一周边区，第一周边区远离显示区的边缘具有大于0的第一曲率。
在步骤284，形成多个子像素、多条数据线、多条栅极线、栅极驱动电路、多条控制信号线、多条数据信号输入线和多路复用电路。
每个子像素包括发光元件和被配置为驱动发光元件的像素驱动电路。多条数据线位于显示区，且电连接至多个子像素。多条栅极线位于显示区，且电连接至多个子像素。栅极驱动电路位于显示区，且包括级联的多级栅极驱动单元。多级栅极驱动单元电连接至多条栅极线，多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路，第一栅极驱动子电路和第二栅极驱动子电路由多个子像素中的第一组子像素的像素驱动电路间隔开。
多条控制信号线至少位于第一周边区，多条控制信号线中的至少一条的至少部分具有大于0的第二曲率。多条数据信号输入线至少位于第一周边区。多路复用电路至少位于第一周边区，且位于多条控制信号线和显示区之间。多路复用电路包括多个多路复用单元，多个多路复用单元中的每一个电连接至多条控制信号线、多条数据信号输入线中的一条数据信号输入线和多条数据线中的至少两条数据线。
上述实施例中，多条控制信号线中的至少一条的至少部分具有大于0第二曲率。这样的结构有助于减小控制信号线的长度，降低控制信号线的电阻，从而提高显示面板的显示均一性。
本公开还提供了一种显示装置，显示装置可以包括上述任意一个实施例的显示面板。在一些实施例中，显示装置例如可以是可穿戴设备(例如手表)、移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进 行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (27)

  1. 一种显示面板，包括：
    衬底基板，包括显示区和围绕所述显示区的周边区，所述周边区包括第一周边区，所述第一周边区远离所述显示区的边缘具有第一曲率，所述第一曲率大于0；
    多个子像素，位于所述显示区，每个子像素包括发光元件和被配置为驱动所述发光元件的像素驱动电路；
    多条数据线，位于所述显示区，且电连接至所述多个子像素；
    多条栅极线，位于所述显示区，且电连接至所述多个子像素；
    栅极驱动电路，位于所述显示区，包括级联的多级栅极驱动单元，所述多级栅极驱动单元电连接至所述多条栅极线，所述多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，所述多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路，所述第一栅极驱动子电路和所述第二栅极驱动子电路由所述多个子像素中的第一组子像素的所述像素驱动电路间隔开；
    多条控制信号线，至少位于所述第一周边区，所述多条控制信号线中的至少一条的至少部分具有第二曲率，所述第二曲率大于0；
    多条数据信号输入线，至少位于所述第一周边区；和
    多路复用电路，至少位于所述第一周边区，且位于所述多条控制信号线和所述显示区之间，所述多路复用电路包括多个多路复用单元，所述多个多路复用单元中的每一个电连接至所述多条控制信号线、所述多条数据信号输入线中的一条数据信号输入线和所述多条数据线中的至少两条数据线。
  2. 根据权利要求1所述的显示面板，其中：
    所述多个子像素包括在第一方向上排布且相邻的第一行子像素和第二行子像素，所述第一行子像素的数量大于所述第二行子像素的数量；
    所述多个多路复用单元中的至少一个至少部分地位于所述第一周边区的第一区域，所述第一区域在第一方向上位于所述第二行子像素的一侧远离所述显示区的一侧，并且在与所述第一方向垂直的第二方向上位于所述第一行子像素远离所述显示区的一侧。
  3. 根据权利要求1所述的显示面板，还包括：
    多条控制信号连接线，所述多条控制信号线经由所述多条控制信号连接线电连接至所述多个多路复用单元。
  4. 根据权利要求3所述的显示面板，其中，所述多条控制信号连接线的延伸方向和所述多条数据线的延伸方向相同。
  5. 根据权利要求1所述的显示面板，其中：
    所述多个多路复用单元中的每一个包括与所述多条控制信号线和所述至少两条数据线一一对应的多个开关晶体管，所述多个开关晶体管中的每一个的栅极电连接至所述多条控制信号线中的一条对应的控制信号线，所述多个开关晶体管中的每一个的第一电极电连接至所述多条数据信号输入线中的一条对应的数据信号输入线，所述多个开关晶体管中的每一个的第二电极电连接至所述至少两条数据线中的一条对应的数据线。
  6. 根据权利要求1所述的显示面板，其中，所述多条控制信号线的每一条具有所述第二曲率。
  7. 根据权利要求1所述的显示面板，其中，所述第二曲率与所述第一曲率相同。
  8. 根据权利要求1所述的显示面板，其中，所述第一组子像素包括：
    第一子组子像素，被配置为发出第一颜色的光，所述第一子组子像素的所述像素驱动电路经由第一组阳极连接线电连接至所述第一子组子像素的所述发光元件的阳极；
    第二子组子像素，被配置为发出第二颜色的光，所述第二子组子像素的所述像素驱动电路经由第二组阳极连接线电连接至所述第二子组子像素的所述发光元件的阳极；和
    第三子组子像素，被配置为发出第三颜色的光，所述第三子组子像素的所述像素驱动电路经由第三组阳极连接线电连接至所述第三子组子像素的所述发光元件的阳极，
    其中，所述第一组阳极连接线、所述第二组阳极连接线和第三组阳极连接线中的至少一组包括多条第一阳极连接线，所述多条第一阳极连接线包括两条第一阳极连接线，所述两条第一阳极连接线中越靠近所述第一栅极驱动子电路的第一阳极连接线的长度越大。
  9. 根据权利要求8所述的显示面板，其中，所述多条第一阳极连接线中越靠近所述第一栅极驱动子电路的第一阳极连接线的长度越大。
  10. 根据权利要求8所述的显示面板，其中，所述第一组阳极连接线、所述第二组阳极连接线、所述第三组阳极连接线中的至少一组与所述发光元件的阳极位于同一层。
  11. 根据权利要求10所述的显示面板，其中：
    所述第一组阳极连接线与所述第一子组子像素的所述发光元件的阳极一体设置；
    所述第二组阳极连接线与所述第二子组子像素的所述发光元件的阳极一体设置；
    所述第三组阳极连接线与所述第三子组子像素的所述发光元件的阳极一体设置。
  12. 根据权利要求11所述的显示面板，其中：
    所述第一组阳极连接线经由第一组过孔电连接至所述第一子组子像素的所述像素驱动电路；
    所述第二组阳极连接线经由第二组过孔电连接至所述第二子组子像素的所述像素驱动电路；
    所述第三组阳极连接线经由第三组过孔电连接至所述第三子组子像素的所述像素驱动电路。
  13. 根据权利要求8所述的显示面板，其中，所述多个子像素还包括第二组子像素，所述第二组子像素的所述像素驱动电路位于所述第一栅极驱动子电路远离所述第二栅极驱动子电路的一侧，所述第二组子像素包括：
    第四子组子像素，被配置为发出所述第一颜色的光，所述第四子组子像素的所述像素驱动电路经由第四组阳极连接线电连接至所述第四子组子像素的所述发光元件 的阳极；
    第五子组子像素，被配置为发出所述第二颜色的光，所述第五子组子像素的所述像素驱动电路经由第五组阳极连接线电连接至所述第五子组子像素的所述发光元件的阳极；和
    第六子组子像素，被配置为发出所述第三颜色的光，所述第六子组子像素的所述像素驱动电路经由第六组阳极连接线电连接至所述第六子组子像素的所述发光元件的阳极，
    其中，所述第四组阳极连接线、所述第五组阳极连接线和所述第六组阳极连接线中的至少一组包括多条第二阳极连接线，所述多条第二阳极连接线中越靠近所述第一栅极驱动子电路的第二阳极连接线的长度越大。
  14. 根据权利要求8-13任意一项所述的显示面板，其中，所述多个子像素还包括第三组子像素和第四组子像素，所述第三组子像素和所述第四组子像素中的一组子像素的所述像素驱动电路位于所述第二栅极驱动子电路靠近所述第一栅极驱动子电路、所述第一组子像素和所述第二组子像素的一侧，另一组子像素的所述像素驱动电路位于所述第二栅极驱动子电路远离所述第一栅极驱动子电路的一侧，所述第三组子像素包括：
    第七子组子像素，被配置为发出所述第一颜色的光，所述第七子组子像素的所述像素驱动电路经由第七组阳极连接线电连接至所述第七子组子像素的所述发光元件的阳极；
    第八子组子像素，被配置为发出所述第二颜色的光，所述第八子组子像素的所述像素驱动电路经由第八组阳极连接线电连接至所述第八子组子像素的所述发光元件的阳极；和
    第九子组子像素，被配置为发出所述第三颜色的光，所述第九子组子像素的所述像素驱动电路经由第九组阳极连接线电连接至所述第九子组子像素的所述发光元件的阳极，
    其中，所述第七组阳极连接线、所述第八组阳极连接线和第九组阳极连接线中的至少一组包括多条第三阳极连接线，所述多条第三阳极连接线中越靠近所述第二栅极驱动子电路的第三阳极连接线的长度越大。
  15. 根据权利要求14所述的显示面板，其中，所述第四组子像素包括：
    第十子组子像素，被配置为发出所述第一颜色的光，所述第十子组子像素的所述像素驱动电路经由第十组阳极连接线电连接至所述第十子组子像素的所述发光元件的阳极；
    第十一子组子像素，被配置为发出所述第二颜色的光，所述第十一子组子像素的所述像素驱动电路经由第十一组阳极连接线电连接至所述第十一子组子像素的所述发光元件的阳极；和
    第十二子组子像素，被配置为发出所述第三颜色的光，所述第十二子组子像素的所述像素驱动电路经由第十二组阳极连接线电连接至所述第十二子组子像素的所述发光元件的阳极，
    其中，所述第十组阳极连接线、所述第十一组阳极连接线和第十二组阳极连接线中的至少一组包括多条第四阳极连接线，所述多条第四阳极连接线中越靠近所述第二栅极驱动子电路的阳极连接线的长度越大。
  16. 根据权利要求15所述的显示面板，其中，所述多个子像素还包括第五组子像素，所述第五组子像素的所述像素驱动电路位于所述第一组子像素的所述像素驱动电路和所述第四组子像素的所述像素驱动电路之间，所述第一组子像素的所述像素驱动电路位于所述第一栅极驱动子电路和所述第五组子像素的所述像素驱动电路之间，所述第四组子像素的所述像素驱动电路位于所述第五组子像素的所述像素驱动电路和所述第二栅极驱动子电路之间，所述第五组子像素包括：
    第十三子组子像素，被配置为发出所述第一颜色的光，所述第十三子组子像素的所述像素驱动电路经由第十三组阳极连接线电连接至所述第十三子组子像素的所述发光元件的阳极；
    第十四子组子像素，被配置为发出所述第二颜色的光，所述第十四子组子像素的所述像素驱动电路经由第十四组阳极连接线电连接至所述第十四子组子像素的所述发光元件的阳极；和
    第十五子组子像素，被配置为发出所述第三颜色的光，所述第十五子组子像素的所述像素驱动电路经由第十五组阳极连接线电连接至所述第十五子组子像素的所述发光元件的阳极，
    其中，所述第十三组阳极连接线的长度相同，所述第十四组阳极连接线的长度相 同，所述第十五组阳极连接线的长度相同。
  17. 根据权利要求8所述的显示面板，还包括：
    第一电路连接线，位于所述显示区，所述第一电路连接线的一端电连接至所述第一栅极驱动子电路，所述第一电路连接线的另一端电连接至所述第二栅极驱动子电路；
    所述第一组子像素位于所述第一栅极驱动子电路和所述第二栅极驱动子电路之间，所述第一组子像素中的至少一个子像素的所述像素驱动电路包括：
    第一像素驱动子电路，位于所述第一电路连接线的一侧，包括驱动晶体管，所述驱动晶体管包括位于所述衬底基板一侧的第一有源层，
    第二像素驱动子电路，位于所述第一电路连接线远离所述第一像素驱动子电路的一侧，和
    连接件，所述连接件的一端电连接至所述第一像素驱动子电路，所述连接件的另一端电连接至所述第二像素驱动子电路，所述连接件在所述衬底基板上的正投影与所述第一电路连接线在所述衬底基板上的正投影交叠，所述连接件与所述驱动有源层位于不同层。
  18. 根据权利要求17所述的显示面板，其中：
    所述驱动晶体管还包括：
    位于所述第一有源层远离所述衬底基板一侧的第一栅极，
    位于所述第一栅极远离所述衬底基板一侧的第一绝缘层，
    位于所述第一绝缘层远离所述衬底基板一侧的第二绝缘层，和
    位于所述第二绝缘层远离所述衬底基板一侧、且电连接至所述第一有源层的第一电极和第二电极；
    所述第一像素驱动子电路还包括存储电容，包括：
    第一电极板，与所述第一栅极位于同一层，和
    第二电极板，位于所述第一绝缘层和所述第二绝缘层之间；
    所述第一电路连接线与所述第一栅极位于同一层，所述第二电极板、所述第一电极和所述第二电极中的至少一个与所述连接件位于同一层。
  19. 根据权利要求18所述的显示面板，其中，所述第一电极、所述第二电极和 所述连接件位于同一层。
  20. 根据权利要求17所述的显示面板，其中，所述一级或多级栅极驱动单元包括级联的前一级栅极驱动单元和后一级栅极驱动单元，其中：
    所述前一级栅极驱动单元的所述第一栅极驱动子电路包括所述前一级栅极驱动单元的第一输入端，所述前一级栅极驱动单元的所述第二栅极驱动子电路包括所述前一级栅极驱动单元的第一输出端；
    所述后一级栅极驱动单元的所述第一栅极驱动子电路包括所述后一级栅极驱动单元的第一输入端，所述后一级栅极驱动单元的所述第二栅极驱动子电路包括所述后一级栅极驱动单元的第一输出端。
  21. 根据权利要求20所述的显示面板，其中：
    所述前一级栅极驱动单元的第一输出端电连接至所述多条栅极线的第一栅极线；
    所述显示面板还包括：
    第一级联连接线，位于所述第一组子像素的所述像素驱动电路远离所述第二栅极驱动子电路的一侧，所述第一级联连接线的一端电连接至所述第一栅极线，所述第一级联连接线的另一端电连接至所述后一级栅极驱动单元的第一输入端。
  22. 根据权利要求21所述的显示面板，还包括：
    多条复位线，位于所述显示区，且电连接至所述多个子像素；
    所述后一级栅极驱动单元的所述第一栅极驱动子电路和所述第二栅极驱动子电路之间的所述第一组子像素的所述像素驱动电路电连接至所述多条复位线中的第一复位线，所述第一复位线经由所述第一级联连接线电连接至所述第一栅极线。
  23. 根据权利要求22所述的显示面板，其中，所述第一级联连接线经由第一过孔电连接至所述第一栅极线，经由第二过孔电连接至所述后一级栅极驱动单元的第一输入端，经由第三过孔电连接至所述第一复位线。
  24. 根据权利要求22所述的显示面板，还包括：
    第二级联连接线，位于所述第一组子像素远离所述第一栅极驱动子电路的一侧， 所述第二级联连接线的一端电连接至所述第一栅极线，所述第二级联连接线的另一端电连接至所述第一复位线。
  25. 根据权利要求1所述的显示面板，还包括：
    多条发光控制线，位于所述显示区，且电连接至所述多个子像素；和
    发光控制驱动电路，位于所述显示区，包括级联的多级发光控制驱动单元，所述多级发光控制驱动单元电连接至所述多条发光控制线，所述多级发光控制驱动单元中的一级或多级发光控制驱动单元包括多个发光控制驱动子电路，所述多个发光控制驱动子电路包括第一发光控制驱动子电路和第二发光控制驱动子电路，所述第一发光控制驱动子电路和所述第二发光控制驱动子电路由所述多个子像素中的第六组子像素的所述像素驱动电路间隔开。
  26. 一种显示装置，包括：如权利要求1-25任意一项所述的显示面板。
  27. 一种显示面板的制造方法，包括：
    提供衬底基板，所述衬底基板包括显示区和围绕所述显示区的周边区，所述周边区包括第一周边区，所述第一周边区远离所述显示区的边缘具有第一曲率，所述第一曲率大于0；和
    形成多个子像素、多条数据线、多条栅极线、栅极驱动电路、多条控制信号线、多条数据信号输入线和多路复用电路，其中：
    每个子像素包括发光元件和被配置为驱动所述发光元件的像素驱动电路，
    所述多条数据线位于所述显示区，且电连接至所述多个子像素，
    所述多条栅极线位于所述显示区，且电连接至所述多个子像素，
    所述栅极驱动电路位于所述显示区，且包括级联的多级栅极驱动单元，所述多级栅极驱动单元电连接至所述多条栅极线，所述多级栅极驱动电路中的一级或多级栅极驱动单元包括多个栅极驱动子电路，所述多个栅极驱动子电路包括第一栅极驱动子电路和第二栅极驱动子电路，所述第一栅极驱动子电路和所述第二栅极驱动子电路由所述多个子像素中的第一组子像素的所述像素驱动电路间隔开，
    所述多条控制信号线至少位于所述第一周边区，所述多条控制信号线中的至少一条的至少部分具有第二曲率，所述第二曲率大于0，
    所述多条数据信号输入线至少位于所述第一周边区，以及
    所述多路复用电路至少位于所述第一周边区，且位于所述多条控制信号线和所述显示区之间，所述多路复用电路包括多个多路复用单元，所述多个多路复用单元中的每一个电连接至所述多条控制信号线、所述多条数据信号输入线中的一条数据信号输入线和所述多条数据线中的至少两条数据线。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN117136641A (zh) * 2022-01-30 2023-11-28 京东方科技集团股份有限公司 显示面板和显示装置
CN117356193A (zh) * 2022-04-29 2024-01-05 京东方科技集团股份有限公司 显示基板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104793417A (zh) * 2015-04-16 2015-07-22 上海中航光电子有限公司 一种tft阵列基板、显示面板及显示装置
CN104978918A (zh) * 2014-04-10 2015-10-14 群创光电股份有限公司 显示面板
CN108803172A (zh) * 2018-06-29 2018-11-13 上海中航光电子有限公司 一种阵列基板、显示面板及显示装置
CN109061972A (zh) * 2018-09-11 2018-12-21 上海天马微电子有限公司 一种显示面板
CN109754753A (zh) * 2019-01-25 2019-05-14 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
US20190347999A1 (en) * 2015-11-30 2019-11-14 Lg Display Co., Ltd. Display device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014142183A1 (ja) * 2013-03-15 2014-09-18 シャープ株式会社 アクティブマトリクス基板、アクティブマトリクス基板の製造方法、及び表示パネル
JP6515090B2 (ja) * 2014-04-28 2019-05-15 シャープ株式会社 表示装置
WO2016080541A1 (ja) * 2014-11-21 2016-05-26 シャープ株式会社 アクティブマトリクス基板及び表示パネル
KR102239481B1 (ko) * 2014-12-31 2021-04-13 엘지디스플레이 주식회사 디스플레이 장치
CN105913791B (zh) * 2016-06-24 2019-09-24 厦门天马微电子有限公司 显示装置、阵列基板及其驱动方法
US10957755B2 (en) 2016-11-15 2021-03-23 Lg Display Co., Ltd. Display panel having a gate driving circuit arranged distributively in a display region of the display panel and organic light-emitting diode display device using the same
WO2019113957A1 (en) * 2017-12-15 2019-06-20 Boe Technology Group Co., Ltd. Display apparatus and gate-driver-on-array circuit
CN108630144A (zh) * 2018-06-19 2018-10-09 武汉天马微电子有限公司 显示面板和显示装置
TWI683292B (zh) * 2018-09-20 2020-01-21 友達光電股份有限公司 畫素陣列基板
CN111261094A (zh) * 2020-03-31 2020-06-09 深圳市华星光电半导体显示技术有限公司 栅极驱动阵列型显示面板
CN111583842A (zh) * 2020-05-29 2020-08-25 京东方科技集团股份有限公司 一种显示面板、显示装置及其断线检测方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104978918A (zh) * 2014-04-10 2015-10-14 群创光电股份有限公司 显示面板
CN104793417A (zh) * 2015-04-16 2015-07-22 上海中航光电子有限公司 一种tft阵列基板、显示面板及显示装置
US20190347999A1 (en) * 2015-11-30 2019-11-14 Lg Display Co., Ltd. Display device
CN108803172A (zh) * 2018-06-29 2018-11-13 上海中航光电子有限公司 一种阵列基板、显示面板及显示装置
CN109061972A (zh) * 2018-09-11 2018-12-21 上海天马微电子有限公司 一种显示面板
CN109754753A (zh) * 2019-01-25 2019-05-14 上海天马有机发光显示技术有限公司 一种显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4033479A4 *

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