WO2021249309A1 - 显示基板、显示装置 - Google Patents

显示基板、显示装置 Download PDF

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Publication number
WO2021249309A1
WO2021249309A1 PCT/CN2021/098417 CN2021098417W WO2021249309A1 WO 2021249309 A1 WO2021249309 A1 WO 2021249309A1 CN 2021098417 W CN2021098417 W CN 2021098417W WO 2021249309 A1 WO2021249309 A1 WO 2021249309A1
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Prior art keywords
base substrate
isolation
electrode
away
display
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PCT/CN2021/098417
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English (en)
French (fr)
Inventor
刘晓云
康亮亮
李晓虎
张娟
黄清雨
闫华杰
焦志强
魏佳奇
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/769,765 priority Critical patent/US20220392968A1/en
Publication of WO2021249309A1 publication Critical patent/WO2021249309A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/18—Carrier blocking layers

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic Light-Emitting Display
  • the micro OLED micro display can provide high-quality video display for mobile information products such as portable computers, wireless Internet browsers, portable DVDs, gaming platforms and wearable computers. It can be said that micro-silicon-based OLED micro-displays provide an excellent solution for near-eye applications (such as helmet displays), whether for civilian consumption, industrial applications, or even military use. It is expected to set off near-eye displays in the military and consumer electronics fields. New wave.
  • Miniature silicon-based OLED display devices have extremely small pixel sizes, high pixel density (Pixels PerInch, PPI), and small spacing between adjacent pixels. The spacing distance is often less than 1 micron, which will cause the horizontal direction between adjacent pixels.
  • PPI Pixel PerInch
  • the problem of current crosstalk causes cross color in the display device. For example, when a pixel has a display signal, part of the display current is transmitted to the adjacent pixel, so that the adjacent pixel cannot display the predetermined pixel gray scale, which greatly affects the display effect of the micro silicon-based OLED display device .
  • embodiments of the present disclosure provide a display substrate, including a base substrate and at least two spaced apart first electrodes arranged on one side of the base substrate, the first electrodes being far away from the substrate
  • a pixel film layer is provided on one side of the substrate, a spacer region is formed between adjacent first electrodes, and an isolation groove is provided on the side of the spacer region away from the base substrate, and the isolation groove is adjacent to the first electrode.
  • the pixel film on the electrode is electrically isolated.
  • a side of the at least two first electrodes away from the base substrate is provided with an isolation column, and the isolation column is located on a side of the first electrode close to the spacer region, and is adjacent to The isolation trench is formed in the spacer region between the isolation pillars of the first electrode.
  • the isolation pillar has a first side wall close to a side of the isolation groove, and an included angle between the first side wall and the base substrate is not less than 80 degrees.
  • the isolation pillar has a second side wall away from the isolation groove, and an inner corner between the second side wall and a surface of the first electrode away from the base substrate Less than 60 degrees.
  • the distance from the surface of the isolation column on the side away from the base substrate to the surface of the first electrode on the side away from the base substrate is 200 to 2000 angstroms.
  • the base substrate includes at least two sub-pixel regions and a non-display area located between adjacent sub-pixel regions, and the orthographic projection of the isolation pillar on the base substrate and the The non-display areas overlap.
  • the pixel film layer includes a charge generation layer disposed on the side of the first electrode away from the base substrate, and the surface of the charge generation layer on the side away from the base substrate is not high. On the surface of the isolation column far away from the base substrate.
  • the pixel film layer further includes a light emitting layer disposed on a side of the charge generation layer away from the base substrate, and a second light emitting layer disposed on a side of the light emitting layer away from the base substrate.
  • the surface of the light-emitting layer on the side away from the base substrate is higher than the surface of the isolation column on the side away from the base substrate.
  • an insulating layer covering the base substrate is provided between the first electrode and the base substrate, and the thickness of the pixel film layer is equal to the thickness of the insulating layer and the first substrate. The sum of the thickness of an electrode.
  • an insulating layer covering the base substrate is provided between the first electrode and the base substrate, and the insulating layer on the spacer between adjacent first electrodes The layer is provided with the isolation groove recessed inward.
  • the isolation groove has a side wall and a bottom wall, and an included angle between the side wall and the bottom wall is not less than 80 degrees.
  • the depth of the isolation groove is not greater than 2000 angstroms.
  • a side of the at least two first electrodes away from the base substrate is provided with an isolation column, and the isolation column is located on a side of the first electrode close to the spacer region, and is adjacent to A first groove is formed in the spacer area between the isolation pillars, and an insulating layer covering the base substrate is provided between the at least two first electrodes and the base substrate, adjacent to the first
  • the insulating layer on the spacer region between the electrodes is provided with a second groove recessed inward, and the first groove and the second groove are combined to form the isolation groove.
  • embodiments of the present disclosure also provide a display device, including any of the foregoing display substrates.
  • FIG. 1 is a first schematic diagram of an embodiment of the disclosure showing that the isolation groove is formed on a substrate;
  • FIG. 2 is a schematic diagram of a display substrate after a pixel film layer is formed on a display substrate according to an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the structure of a pixel film layer in a display substrate according to an embodiment of the disclosure
  • FIG. 4 is a second schematic diagram showing the isolation grooves formed on the substrate according to the embodiment of the present disclosure.
  • FIG. 5 is a third schematic diagram of an embodiment of the disclosure showing that the isolation groove is formed on the substrate.
  • installation should be interpreted broadly unless otherwise clearly defined and defined.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • connection can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • the "about” in the present disclosure refers to a value within the allowable process and measurement error range without strictly limiting the limit.
  • top-emitting electroluminescence structure is widely used in mobile products due to its high aperture ratio and high product brightness.
  • top-emission electroluminescence is the only choice. Due to the limitations of current masks, it is difficult for current RGB structure products to break through 1000ppi.
  • White organic electroluminescent devices (WOLED) + color film substrates (CF) make it possible for products to reach several thousand ppi.
  • Top-emitting devices have a strong microcavity effect. Generally, top-emitting white light devices will give priority to weakening the microcavity effect so that the red, green and blue colors can emit light in a balanced manner, which places higher requirements on the device cathode.
  • the magnesium (Mg):silver (Ag) composite cathode that has been mass-produced in the industry has a transmittance of only about 50%, and the microcavity effect is relatively obvious. In addition, the color film substrate's light selectivity makes it The brightness of the final product is lower.
  • the reflectivity of the mirror P1 is R 1
  • the reflectivity of the half mirror P2 is R2
  • the optical path between the mirror P1 and the half mirror P2 is L
  • the optical path of the light-emitting center distance P1 is Z
  • the light intensity when emitted at the luminous center is I 0 .
  • a hole injection layer (HIL) material with better injection performance is also required.
  • the hole injection layer (HIL) material has high conductivity. Since the cathodes of organic electroluminescent materials are shared, the surrounding pixels often become bright when they are lit. For pixel arrangements such as BV3 or real RGB, it will cause cross-color phenomenon and reduce the color gamut of the product.
  • CMOS Complementary Metal Oxide Semiconductor
  • An embodiment of the present disclosure provides a display substrate, including a base substrate and at least two spaced apart first electrodes arranged on one side of the base substrate, and the first electrode is provided with a side away from the base substrate.
  • a spacer region is formed between adjacent first electrodes, and an isolation groove is provided on the side of the spacer region away from the base substrate, and the isolation groove connects the pixel film adjacent to the first electrode.
  • the substrate forms an isolation groove on the interval between adjacent first electrodes, so that the isolation groove and the first electrode form a step difference, so that in the process of forming the pixel film, the isolation groove can block the adjacent first electrode.
  • the lateral current between the pixel film layers on one electrode, that is, the isolation groove can block the hole injection layer and the charge generation layer in the pixel film layer on the adjacent first electrode, so that the pixel film layer on the adjacent first electrode Electrical isolation prevents crosstalk of pixel film layers on adjacent first electrodes.
  • FIG. 1 is a first schematic diagram of an embodiment of the disclosure showing that the isolation groove is formed on a substrate.
  • the display substrate of the embodiment of the present disclosure is an organic light emitting diode display substrate, which includes a base substrate 10 and at least two first electrodes 11 arranged on one side of the base substrate 10. At least two first electrodes 11 interval settings.
  • the first electrode 11 may be an anode.
  • the adjacent first electrodes 11 are disconnected from each other to form a spacer 12.
  • At least two first electrodes 11 are provided with isolation pillars 13 on the side away from the base substrate 10, and the isolation pillars 13 are located on the side of the first electrode 11 close to the spacer region 12, and the isolation pillars 13 adjacent to the first electrode 11 are in the spacer region.
  • the isolation trench 14 forms the isolation trench 14, that is, the isolation pillars 13 on the adjacent first electrodes 11 enclose the isolation trench 14 in the isolation region 12.
  • At least one first electrode 11 is provided with isolation pillars 13 on opposite sides, and the isolation pillars 13 on opposite sides of one first electrode 11 form a pixel opening, and the pixel opening exposes the first electrode 11.
  • the pixel film (not shown in the figure) is disposed on the pixel opening.
  • the isolation groove 14 and the first electrode 11 form a step difference, which can isolate the pixel film layer on the adjacent first electrode 11 to block the lateral current of the pixel film layer on the adjacent first electrode 11 and prevent adjacent The pixel film layer of the first electrode crosstalks.
  • the isolation pillars 13 may be arranged on both sides of the first electrode 11, or the isolation pillars 13 may be arranged on one side of the first electrode 11, as long as the isolation pillars 13 of the first electrode 11 are adjacent to each other. It suffices that the isolation groove 14 can be formed in the spacer region 12.
  • the present disclosure shows that the substrate may be top-emitting.
  • the first electrode 11 includes a contact electrode 111 provided on a side of the base substrate 10 and a reflective electrode 112 provided on a side of the contact electrode 111 away from the base substrate 10.
  • the contact electrodes 111 of adjacent first electrodes 11 are disconnected from each other, and the reflective electrodes 112 of adjacent first electrodes 11 are disconnected from each other.
  • the first electrode 11 may be a transparent electrode or a semi-transparent electrode.
  • the type and material of the first electrode are not limited.
  • the first electrode may be formed of a transparent conductive material with a high work function, and its electrode material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), oxide Zinc (ZnO), indium oxide (In2O3), aluminum oxide zinc (AZO) and carbon nanotubes.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • GZO gallium zinc oxide
  • ZnO oxide Zinc
  • In2O3 aluminum oxide zinc
  • AZO aluminum oxide zinc
  • a protective layer (not shown in the figure) is provided on the side of the first electrode away from the base substrate 10, and the protective layer is used to protect the first electrode.
  • the protective layer is a PR protective layer.
  • the base substrate 10 includes at least two sub-pixel regions and a non-display region located between adjacent sub-pixel regions.
  • the orthographic projection of the pixel opening on the base substrate 10 overlaps the sub-pixel area.
  • the orthographic projection of the isolation pillar 13 on the base substrate 10 overlaps the non-display area, so as to prevent the isolation pillar 13 from blocking the sub-pixel area and reduce the area of the pixel opening.
  • the design process is simple, efficient and accurate, improves the overall luminous efficiency of the device, and is suitable for the field of ultra-high micro display.
  • the material of the isolation column 13 may be an inorganic material.
  • the material of the isolation pillar 13 may be silicon nitride (SiNx) or silicon oxide (SiOx).
  • the isolation pillar 13 has a first side wall 131 on the side close to the isolation groove 14, and the included angle a between the first side wall 131 and the surface of the base substrate 10 on the side close to the first electrode 11 is not less than 80. Spend.
  • the angle a is 90 degrees. This ensures that during the process of forming the pixel film on the first electrode 11, the pixel film is broken at the first side wall 131, so as to block the lateral current of the pixel film on the adjacent first electrode 11.
  • the isolation pillar 13 has a second side wall 132 away from the isolation groove 14, and the internal angle b between the second side wall 132 and the surface of the first electrode 11 away from the base substrate 10 is less than 60 degrees.
  • the angle b is 45 degrees. This ensures that during the process of forming the pixel film on the first electrode 11, the second electrode (cathode) in the pixel film will not be broken.
  • the cross-section of the isolation column may have various shapes, such as regular trapezoid, inverted trapezoid, rectangle, regular hexagon and other polygons, or other regular or irregular shapes, which will not be omitted here in this embodiment. Go into details.
  • the distance from the surface of the isolation column on the side away from the base substrate to the surface of the first electrode on the side away from the base substrate is 200 to 2000 angstroms to ensure that the isolation groove formed by the isolation column can resist
  • the lateral current of the adjacent pixel film layer is interrupted, and it is ensured that the second electrode (cathode) in the pixel film layer will not be broken.
  • FIG. 2 is a schematic diagram of a display substrate after a pixel film layer is formed on a display substrate according to an embodiment of the disclosure.
  • a pixel film 15 is provided on the side of the first electrode 11 away from the base substrate 10.
  • the pixel film layer 15 is connected to the first electrode 11 exposed by the pixel opening.
  • the pixel film layer 15 at least includes a hole injection layer 151 disposed on the side of the first electrode 11 away from the base substrate 10.
  • the surface of the hole injection layer 151 away from the base substrate 10 is not higher than the surface of the isolation pillar 13 away from the base substrate 10, so as to ensure that the hole injection layer 151 can be separated by the isolation groove.
  • the pixel film layer 15 further includes a charge generation layer 152 disposed on the side of the hole injection layer 151 away from the base substrate 10.
  • the surface of the charge generation layer 152 on the side away from the base substrate 10 is not higher than the spacers. 13
  • the surface of the charge generation layer 152 away from the base substrate 10 is flush with the surface of the isolation column 13 away from the base substrate 10. This ensures that the charge generation layer 152 is separated by the isolation groove.
  • the charge generation layer includes a first generation layer and a second generation layer superimposed, the first generation layer is located on a side close to the base substrate, and the second generation layer is located on a side far from the base substrate.
  • the surface of the second generation layer away from the base substrate is not higher than the surface of the isolation column away from the base substrate.
  • the pixel film layer 15 further includes a light-emitting layer disposed on the side of the charge generation layer 152 away from the base substrate 10 and a second electrode 154 disposed on the side of the light-emitting layer away from the base substrate 10.
  • the second electrode 154 may be a cathode.
  • the surface of the light-emitting layer on the side away from the base substrate 10 is higher than the surface of the spacer 13 on the side away from the base substrate 10. Therefore, it is ensured that the second electrode 154 will not be separated by the isolation groove, and the second electrode 154 will not be broken.
  • an insulating layer 16 covering the base substrate 10 is provided between the first electrode 11 and the base substrate 10.
  • the thickness of the pixel film layer is equal to the sum of the thickness of the insulating layer 16 and the thickness of the first electrode 11. Thereby weakening the microcavity effect.
  • FIG. 3 is a schematic diagram of the structure of a pixel film layer in a display substrate according to an embodiment of the disclosure.
  • the pixel film layer 15 includes a hole injection layer 151 disposed on the side of the first electrode away from the base substrate, and a first hole transport layer 155 disposed on the side of the hole injection layer 151 away from the base substrate.
  • the second light-emitting layer 156 disposed on the side of the first hole transport layer 155 away from the base substrate, the first electron transport layer 157 disposed on the side of the second light-emitting layer 156 away from the base substrate, and the first electron transport layer 157 disposed on the first electron transport layer.
  • the layer 157 is the charge generation layer 152 on the side away from the base substrate, the second hole transport layer 158 disposed on the side of the charge generation layer 152 away from the base substrate, and the second hole transport layer 158 is disposed on the side away from the base substrate.
  • the charge generation layer 152 may include a first generation layer and a second generation layer.
  • the first generation layer may be an N-type charge generation layer
  • the second generation layer may be a P-type charge generation layer.
  • the N-type charge generation layer includes metal materials (for example, Li, Mg, Ca, Cs, Yb).
  • the P-type charge generation layer is made of metal oxides (such as ITO, WO3, MoO3, V2O5, ReO3), or hole transport materials doped with Lewis acids (such as FeCl3:NPB, F4-TCNQ:NPB), or P-type organic Material (such as HATCN) composition.
  • the N-type charge generation layer can improve the injection and migration characteristics of electrons, thereby reducing the driving voltage and improving the efficiency and lifetime of the device.
  • the first hole transport layer 155 and the second hole transport layer 158 can play a role in promoting the transport of holes.
  • the material of the first hole transport layer 155 and the second hole transport layer 158 may include any one selected from the group consisting of: for example, NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine) ( N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-2,2'-dimethylbenzidine), TPD(N,N'-bis-(3-methyl Phenyl)-N,N'-bis-(phenyl)-benzidine), and MTDATA(4,4',4-tris(N-3-methylphenyl-N-phenyl-amino)- Triphenylamine).
  • NPD N,N-dinaphthyl-N,N'-diphenylbenzidine
  • TPD N,N'-bis-(3-methyl Phenyl)-
  • the hole injection layer 151 can promote the injection of holes.
  • the hole injection layer 151 may be made of at least one selected from the group consisting of CuPc (copper phthalocyanine), PEDOT (poly(3,4)-ethylenedioxythiophene), PANI (polyaniline), NPD (N ,N-dinaphthyl-N,N'-diphenylbenzidine) and combinations thereof.
  • this embodiment is not limited to this.
  • the first electron transport layer 157 and the second electron transport layer 159 receive electrons from the second electrode, and can transfer the supplied electrons to the light emitting layer.
  • the first electron transport layer 157 and the second electron transport layer 159 are also used to facilitate the transport of electrons.
  • the materials of the first electron transport layer 157 and the second electron transport layer 159 may include at least one selected from the group consisting of: for example, Alq3 (tris(8-hydroxyquinoline) aluminum), Liq (8-hydroxyquinoline lithium), PBD ( 2-(4-Biphenyl)-5-(4-tert-butylphenyl)-1,3,4-diazole), TAZ(3-(4-Biphenyl)-4-phenyl-5- Tert-butylphenyl-1,2,4-triazole), spiro-PBD, BAlq (bis(2-methyl-8-quinoline)-4-(phenylphenol) aluminum), SAlq, TPBi(2 ,2',2-(1,3,5-benzinetriyl)-tris(1-phenyl-1-H-benzimidazole)(2,2',2-(1,3,5-benzinetriyl) -tris(1-phenyl-1-H-benzimidazole))), diazole,
  • the second electrode 154 may be formed of a material with high conductivity and low work function.
  • the material of the second electrode 154 may include alloys such as magnesium aluminum alloy (MgAl), lithium aluminum alloy (LiAl), or magnesium alloy. , Aluminum, lithium, silver and other single metals.
  • the “patterning process” in this embodiment includes the processes of depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping the photoresist.
  • the "photolithography process” “Process” includes treatments such as film coating, mask exposure, development, etc.
  • the evaporation, deposition, coating, coating, etc. mentioned in this embodiment are all mature preparation processes in related technologies.
  • the preparation process of the display substrate includes:
  • An insulating layer 16 is formed on the base substrate 10, a metal film is deposited on the insulating layer 16, and the metal film is patterned through a patterning process. At least two first layers are formed on the side of the insulating layer 16 away from the base substrate 10. The electrodes 11, at least two first electrodes 11 are arranged at intervals. The adjacent first electrodes 11 are disconnected from each other, and a spacer 12 is formed between the adjacent first electrodes 11. A PR protection film (not shown in the figure) is formed on the side of the first electrode 11 away from the base substrate 10, as shown in FIG. 1.
  • the metal thin film can use a transparent conductive material with a high work function, and the metal thin film material can include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), and zinc oxide. (ZnO), indium oxide (In2O3), aluminum oxide zinc (AZO) and carbon nanotubes.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • GZO gallium zinc oxide
  • ZnO zinc oxide
  • In2O3 aluminum oxide zinc (AZO) and carbon nanotubes.
  • isolation material layer covering the entire base substrate 10 on the side of the first electrode 11 away from the base substrate 10 Coat the isolation material layer through an etching process to remove the isolation material layer on the spacer region 12 ,
  • the isolation material layer on the first electrode 11 is partially removed, and the remaining isolation material layer on the first electrode 11 forms an isolation column 13, which is located on the side of the first electrode 11 close to the spacer region 12, and is adjacent to the isolation column 13
  • An isolation groove 14 is formed in the spacer region 12.
  • At least one first electrode 11 is provided with isolation pillars 13 on opposite sides, and the isolation pillars 13 on opposite sides of a first electrode 11 form a pixel opening, and the pixel opening exposes the first electrode 11, as shown in FIG. 1 .
  • the thickness of the isolation material layer is 200 to 2000 angstroms, and the material of the isolation material layer can be an inorganic material.
  • the width and depth of the isolation groove 14 can be set according to the thickness of the pixel film layer, as long as the isolation groove 14 can block the hole injection layer and the charge generation layer in the adjacent pixel film layer, and will not cause the second electrode to occur. Just break.
  • a pixel film layer 15 is formed on the side of the first electrode 11 away from the base substrate 10.
  • the pixel film layer 15 at least includes a hole injection layer 151 disposed on the side of the first electrode away from the base substrate, a first hole transport layer 155 disposed on the side of the hole injection layer 151 away from the base substrate, and The first hole transport layer 155 is far from the second light-emitting layer 156 on the side of the base substrate, the first electron transport layer 157 is located on the side of the second light-emitting layer 156 far from the base substrate, and the first electron transport layer 157 is located far away.
  • the charge generation layer 152 on the side of the base substrate, the second hole transport layer 158 provided on the side of the charge generation layer 152 away from the base substrate, and the first hole transport layer 158 provided on the side of the second hole transport layer 158 away from the base substrate.
  • the hole injection layer 151 and the charge generation layer 152 are separated by the isolation trench 14.
  • the second electrode 154 in the pixel film layer 15 is not separated by the isolation groove 14, as shown in FIGS. 2 and 3.
  • An encapsulation layer is formed on the pixel film layer to encapsulate the pixel film layer.
  • a low-temperature color film structure layer is formed on the encapsulation layer to achieve a display effect.
  • FIG. 4 is a second schematic diagram of an embodiment of the disclosure showing that the isolation groove is formed on the substrate.
  • FIG. 4 illustrates an exemplary implementation of the display substrate according to the embodiment of the present disclosure.
  • the main structure of the display substrate of the embodiment of the present disclosure is basically the same as that of the display substrate of the previous embodiment. The difference is that an insulating layer covering the base substrate 10 is provided between the first electrode 11 and the base substrate 10. 16.
  • the insulating layer 16 on the spacer area between the adjacent first electrodes 11 is provided with an inwardly recessed isolation groove 14.
  • the isolation groove 14 forms a step with the first electrode 11 to ensure that the lateral current of the pixel film layer on the adjacent first electrode 11 is blocked, and to prevent the pixel film layer on the adjacent first electrode from crosstalk.
  • the isolation groove 14 has a side wall 141 and a bottom wall 142, and the included angle c between the side wall 141 and the bottom wall 142 is not less than 80 degrees.
  • the angle c between the side wall 141 and the bottom wall 142 is 90 degrees.
  • the angle c between the side wall 141 and the bottom wall 142 is not less than 80 degrees to ensure that during the formation of the pixel film layer, the pixel film layer is broken at the isolation groove 14 so as to block the adjacent first electrode 11 The lateral current of the pixel film.
  • the depth of the isolation groove is not greater than 2000 angstroms to ensure that the isolation groove can block the lateral current of the adjacent pixel film layer and ensure that the second electrode (cathode) in the pixel film layer does not Fracture occurred.
  • FIG. 5 is a third schematic diagram of an embodiment of the disclosure showing that the isolation groove is formed on the substrate.
  • FIG. 5 illustrates an exemplary implementation of a display substrate according to an embodiment of the present disclosure.
  • the main structure of the display substrate of the embodiment of the present disclosure is basically the same as that of the display substrate of the previous embodiment. The difference is that the at least two first electrodes 11 are provided on the side away from the base substrate 10
  • the isolation pillar 13 is located on a side of the first electrode 11 close to the spacer region 12, and a first groove 17 is formed on the spacer region between adjacent isolation columns 13.
  • An insulating layer 16 covering the base substrate 10 is provided between the first electrode 11 and the base substrate 10, and the insulating layer 16 on the interval between adjacent first electrodes 11 is provided with a second groove 18 recessed inward.
  • the orthographic projection of the second groove 18 on the base substrate 10 is located in the orthographic projection of the first groove 17 on the base substrate 10.
  • the first groove 17 and the second groove 18 combine to form an isolation groove 14.
  • the shape and size of the isolation column 13 in the embodiment of the present disclosure are the same as the shape and size of the isolation column in the display substrate shown in FIG. 1. This embodiment will not be repeated here.
  • the second groove 18 in the embodiment of the present disclosure has the same shape and size as the isolation groove in the display substrate shown in FIG. 4. This embodiment will not be repeated here.
  • the isolation pillar 13 in the process of forming the isolation trench 14, the isolation pillar 13 is first formed on the first electrode 11, and then the second groove 18 is formed on the insulating layer 16.
  • the second groove 18 is formed on the insulating layer 16 first, and then the isolation pillar 13 is formed on the first electrode 11.
  • This embodiment also provides a method for preparing a display substrate, including:
  • At least two first electrodes are formed on one side of the base substrate, and the at least two first electrodes are arranged at intervals, so that a spacer area is formed between adjacent first electrodes;
  • a pixel film layer is formed on the first electrode, and the pixel film layer on the adjacent first electrode is electrically separated by the isolation groove.
  • step S2 includes:
  • An isolation column is formed on the side of the first electrode away from the base substrate, and the isolation column is located on the side of the first electrode close to the spacer region, so that adjacent isolation columns form the isolation groove in the spacer region.
  • this embodiment shows a method for preparing a substrate, including:
  • At least two first electrodes are formed on the side of the insulating layer away from the base substrate, and the at least two first electrodes are arranged at intervals, so that a spacer area is formed between adjacent first electrodes;
  • this embodiment shows a method for preparing a substrate, including:
  • At least two first electrodes are formed on the side away from the base substrate, and the at least two first electrodes are arranged at intervals, so that a spacer area is formed between adjacent first electrodes;
  • isolation pillars on the side of the at least two first electrodes away from the base substrate, and the isolation pillars are located on the side of the at least two first electrodes close to the spacer area, so that adjacent isolation pillars form first in the spacer area.
  • a second groove recessed inward is formed in the insulating layer on the spacer region between the adjacent at least two first electrodes, and the first groove and the second groove are combined to form the isolation groove.
  • this embodiment shows a method for preparing a substrate, including:
  • At least two first electrodes are formed on the side away from the base substrate, and the at least two first electrodes are arranged at intervals, so that a spacer area is formed between adjacent first electrodes;
  • An embodiment of the present disclosure also provides a display device, including the display substrate of any one of the foregoing embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种显示基板、显示装置。显示基板包括衬底基板以及设置于所述衬底基板一侧的至少两个间隔设置的第一电极，所述第一电极远离所述衬底基板一侧设置有像素膜层，相邻所述第一电极之间形成间隔区，所述间隔区远离所述衬底基板一侧设置有隔离槽，所述隔离槽将相邻所述第一电极上的像素膜层电性隔断。

Description

显示基板、显示装置
本申请要求于2020年6月12日提交中国专利局、申请号为202010536226.9、公开名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引入的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种显示基板、显示装置。
背景技术
现有的微型有机发光显示装置，如硅基微型有机发光显示(Organic Light-Emitting Display，简称：OLED)装置，以单晶硅芯片为基底，像素尺寸为传统显示器件的1/10，精细度远远高于传统器件，可用于形成微型显示器。硅基OLED微显示器具有广阔的市场应用空间，特别适合应用于头盔显示器、立体显示镜以及眼镜式显示器等。如与移动通讯网络、卫星定位等系统联在一起则可在任何地方、任何时间获得精确的图像信息，这在国防、航空、航天乃至单兵作战等军事应用上具有非常重要的军事价值。微型OLED微显示器能够为便携式计算机、无线互联网浏览器、便携式DVD、游戏平台及可戴式计算机等移动信息产品提供高画质的视频显示。可以说，微型硅基OLED微显示无论是对于民用消费领域还是工业应用乃至军事用途都提供了一个极佳的近眼应用(如头盔显示)解决途径，有望在军事以及消费类电子领域掀起近眼显示的新浪潮。
微型硅基OLED显示装置，其像素尺寸特别小，像素密度(Pixels PerInch，简称：PPI)高，相邻像素之间的间隔小，间隔距离往往小于1微米，从而会导致相邻像素之间横向电流串扰的问题，引起显示装置串色。比如，当一个像素有显示信号时，部分显示电流被传输到了与其相邻的像素处，使得相邻的像素不能显示预定的像素灰阶，这使得微型硅基OLED显示装置的显示效 果大受影响。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示基板，包括衬底基板以及设置于所述衬底基板一侧的至少两个间隔设置的第一电极，所述第一电极远离所述衬底基板一侧设置有像素膜层，相邻所述第一电极之间形成间隔区，所述间隔区远离所述衬底基板一侧设置有隔离槽，所述隔离槽将相邻所述第一电极上的像素膜层电性隔断。
在示例性实施方式中，所述至少两个第一电极远离所述衬底基板的一侧设置有隔离柱，所述隔离柱位于所述第一电极靠近所述间隔区的一侧，相邻所述第一电极的隔离柱之间在间隔区形成所述隔离槽。
在示例性实施方式中，所述隔离柱具有靠近所述隔离槽一侧的第一侧壁，所述第一侧壁与所述衬底基板之间的夹角不小于80度。
在示例性实施方式中，所述隔离柱具有远离所述隔离槽一侧的第二侧壁，所述第二侧壁与所述第一电极远离所述衬底基板一侧表面之间的内角小于60度。
在示例性实施方式中，所述隔离柱远离所述衬底基板一侧的表面到所述第一电极远离所述衬底基板一侧的表面的距离为200至2000埃米。
在示例性实施方式中，所述衬底基板包括至少两个子像素区以及位于相邻所述子像素区之间的非显示区，所述隔离柱在所述衬底基板的正投影与所述非显示区交叠。
在示例性实施方式中，所述像素膜层包括设置于所述第一电极远离所述衬底基板一侧的电荷生成层，所述电荷生成层远离所述衬底基板一侧的表面不高于所述隔离柱远离所述衬底基板一侧的表面。
在示例性实施方式中，所述像素膜层还包括设置于所述电荷生成层远离 所述衬底基板一侧的发光层以及设置于所述发光层远离所述衬底基板一侧的第二电极，所述发光层远离所述衬底基板一侧的表面高于所述隔离柱远离所述衬底基板一侧的表面。
在示例性实施方式中，所述第一电极与所述衬底基板之间设置有覆盖所述衬底基板的绝缘层，所述像素膜层的厚度等于所述绝缘层的厚度与所述第一电极的厚度之和。
在示例性实施方式中，所述第一电极与所述衬底基板之间设置有覆盖所述衬底基板的绝缘层，相邻所述第一电极之间所述间隔区上的所述绝缘层设置有向内凹陷的所述隔离槽。
在示例性实施方式中，所述隔离槽具有侧壁和底壁，所述侧壁与所述底壁之间的夹角不小于80度。
在示例性实施方式中，所述隔离槽的深度不大于2000埃米。
在示例性实施方式中，所述至少两个第一电极远离所述衬底基板的一侧设置有隔离柱，所述隔离柱位于所述第一电极靠近所述间隔区的一侧，相邻的所述隔离柱之间在所述间隔区形成第一凹槽，所述至少两个第一电极与所述衬底基板之间设置有覆盖所述衬底基板的绝缘层，相邻第一电极之间间隔区上的绝缘层设置有向内凹陷的第二凹槽，所述第一凹槽与所述第二凹槽组合形成所述隔离槽。
第二方面，本公开实施例还提供了一种显示装置，包括前面任一所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
图1为本公开实施例显示基板形成隔离槽后的示意图一；
图2为本公开实施例显示基板形成像素膜层后的示意图；
图3为本公开实施例显示基板中像素膜层的结构示意图；
图4为本公开实施例显示基板形成隔离槽后的示意图二；
图5为本公开实施例显示基板形成隔离槽后的示意图三。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以至少两个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
顶发射电致发光结构以其高开口率，产品亮度高广泛应用于移动端产品。对于硅基OLED显示产品来说，顶发射电致发光是其唯一的选择。由于当前掩膜版的限制，当前RGB结构产品很难突破1000ppi，白色有机电致发光器 件(WOLED)+彩膜基板(CF)使得产品到达几千ppi成为可能。顶发射器件存在着较强的微腔效应，一般顶发射白光器件会优先考虑弱化微腔效应，以便红绿蓝三色可以均衡出光，这就对器件阴极有着较高的要求。在行业内目前已量产的镁(Mg):银(Ag)复合阴极，该阴极结构透过率只有50％左右，微腔效应比较明显，再加上彩膜基板对光的选择性，使得最终产品的亮度较低。
微腔效应公式如下：
Figure PCTCN2021098417-appb-000001
微腔效应公式中，反射镜P1的反射率为R 1，一半反半透镜P2的反射率为R2，反射镜P1与一半反半透镜P2间光程为L，发光中心距P1的光程为Z，在发光中心发出时的光强为I 0。
微型硅基OLED显示装置中，对于白光单发光层(single)器件，为降低器件启动电压，除了提高阳极注入功函外，还需要注入性能较好的空穴注入层(HIL)材料。空穴注入层(HIL)材料具有较高的导电性。由于有机电致发光材料的阴极是共用的，在点亮时往往出现周边像素发亮的情况，对于BV3或real RGB等像素排布来说就会引起串色现象，导致产品色域降低。
对于多发光层(tandem)器件除了高导电的空穴注入层(HIL)外，又引入了电荷生成层(CGL)。对于像素密度(Pixels Per Inch，简称：PPI)较低的TV等产品来说，解决电荷生成层的串扰往往是通过降低电荷生成层的电性或增加像素膜层之间的间距来实现。由于硅基的产品像素膜层之间的间距限制，以及产品亮度是TV亮度的10倍甚至更高，电荷生成层的电学降低后，其产品工作电压和功耗将会提高，也加剧了互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称：CMOS)的跨压设计难度。
本公开实施例提供一种显示基板，包括衬底基板以及设置于所述衬底基 板一侧的至少两个间隔设置的第一电极，所述第一电极远离所述衬底基板一侧设置有像素膜层，相邻所述第一电极之间形成间隔区，所述间隔区远离所述衬底基板一侧设置有隔离槽，所述隔离槽将相邻所述第一电极上的像素膜层电性隔断。
本公开实施例显示基板通过在相邻第一电极之间的间隔区上形成隔离槽，使隔离槽与第一电极形成段差，从而在形成像素膜层过程中，隔离槽能够阻断相邻第一电极上像素膜层之间的横向电流，即隔离槽能够阻断相邻第一电极上像素膜层中的空穴注入层和电荷生成层，使相邻第一电极上像素膜层之间电性隔断，防止相邻第一电极上像素膜层串扰。
图1为本公开实施例显示基板形成隔离槽后的示意图一。如图1所示，本公开实施例显示基板为有机发光二级管显示基板，包括衬底基板10以及设置于衬底基板10一侧的至少两个第一电极11，至少两个第一电极11间隔设置。第一电极11可以为阳极。相邻第一电极11之间互相断开，形成间隔区12。至少两个第一电极11远离衬底基板10的一侧设置有隔离柱13，隔离柱13位于第一电极11靠近间隔区12的一侧，相邻第一电极11的隔离柱13在间隔区12形成隔离槽14，即相邻第一电极11上的隔离柱13在间隔区12围成隔离槽14。至少一个第一电极11的相对两侧均设置有隔离柱13，一个第一电极11上相对两侧的隔离柱13形成像素开口，该像素开口将该第一电极11暴露。像素膜层(图中未示出)设置于像素开口上。本公开实施例中隔离槽14与第一电极11形成段差，能够将相邻第一电极11上像素膜层隔断，以阻断相邻第一电极11上像素膜层的横向电流，防止相邻第一电极的像素膜层串扰。
在一种示例性实施方式中，隔离柱13可以设置在第一电极11的两侧，或者，隔离柱13可以设置在第一电极11的一侧，只要相邻第一电极11的隔离柱13能够在间隔区12形成隔离槽14即可。
如图1所示，本公开显示基板可以为顶发射。本公开实施例中第一电极11包括设置于衬底基板10一侧的接触电极111以及设置于接触电极111远离衬底基板10一侧的反射电极112。相邻第一电极11的接触电极111互相断开，相邻第一电极11的反射电极112互相断开。在显示基板的发光方式为 顶发射的情况下，第一电极11可以为透明电极或者半透明电极。
在一种示例性实施方式中，第一电极的类型以及材料不作限制。例如，第一电极可由具有高功函数的透明导电材料形成，其电极材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
在一种示例性实施方式中，第一电极远离衬底基板10一侧设置有保护层(图中未示出)，有保护层用于保护第一电极。比如，保护层为PR保护层。
在一种示例性实施方式中，衬底基板10包括至少两个子像素区以及位于相邻子像素区之间的非显示区。像素开口在衬底基板10的正投影与子像素区交叠。隔离柱13在衬底基板10的正投影与非显示区交叠，以避免隔离柱13遮挡子像素区，减小像素开口的面积。该设计工艺简单，高效，精准，提高了器件的整体发光效率，适用于超高微显示领域。
在一种示例性实施方式中，隔离柱13的材料可以采用无机材料。比如，隔离柱13的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)。
如图1所示，隔离柱13具有靠近隔离槽14一侧的第一侧壁131，第一侧壁131与衬底基板10靠近第一电极11一侧表面之间的夹角a不小于80度。比如，夹角a为90度。从而确保在第一电极11上形成像素膜层过程中，像素膜层在第一侧壁131处发生断裂，实现阻断相邻第一电极11上像素膜层的横向电流。
如图1所示，隔离柱13具有远离隔离槽14一侧的第二侧壁132，第二侧壁132与第一电极11远离衬底基板10一侧表面之间的内角b小于60度，比如，夹角b为45度。从而确保在第一电极11上形成像素膜层过程中，像素膜层中的第二电极(阴极)不会发生断裂。
在一种示例性实施方式中，隔离柱的截面可以为多种形状，比如，正梯形、倒梯形、矩形、正六边形等多边形，或者其他规则或不规则形状，本实施例在此不再赘述。
在一种示例性实施方式中，隔离柱远离衬底基板一侧的表面到第一电极远离衬底基板一侧的表面的距离为200至2000埃米，以确保隔离柱形成的隔 离槽能够阻断相邻像素膜层的横向电流，且保证像素膜层中的第二电极(阴极)不会发生断裂。
图2为本公开实施例显示基板形成像素膜层后的示意图。如图2所示，第一电极11远离衬底基板10一侧设置有像素膜层15。像素膜层15与像素开口暴露的第一电极11连接。像素膜层15至少包括设置于第一电极11远离衬底基板10一侧的空穴注入层151。空穴注入层151远离衬底基板10一侧的表面不高于隔离柱13远离衬底基板10一侧的表面，从而确保空穴注入层151能够被隔离槽隔断。
如图2所示，像素膜层15还包括设置于空穴注入层151远离衬底基板10一侧的电荷生成层152，电荷生成层152远离衬底基板10一侧的表面不高于隔离柱13远离衬底基板10一侧的表面。比如，电荷生成层152远离衬底基板10一侧的表面与隔离柱13远离衬底基板10一侧的表面平齐。从而确保电荷生成层152被隔离槽隔断。
在一种示例性实施方式中，电荷生成层包括叠加设置的第一生成层以及第二生成层，第一生成层位于靠近衬底基板的一侧，第二生成层位于远离衬底基板的一侧，第二生成层远离衬底基板一侧的表面不高于隔离柱远离衬底基板一侧的表面。
如图2所示，像素膜层15还包括设置于电荷生成层152远离衬底基板10一侧的发光层以及设置于发光层远离衬底基板10一侧的第二电极154。第二电极154可以为阴极。发光层远离衬底基板10一侧的表面高于隔离柱13远离衬底基板10一侧的表面。从而确保第二电极154不会被隔离槽隔断，保证第二电极154不会发生断裂。
如图1所示，第一电极11与衬底基板10之间设置有覆盖衬底基板10的绝缘层16，像素膜层的厚度等于绝缘层16的厚度与第一电极11的厚度之和，从而弱化微腔效应。
图3为本公开实施例显示基板中像素膜层的结构示意图。如图3所示，像素膜层15包括设置于第一电极远离衬底基板一侧的空穴注入层151、设置于空穴注入层151远离衬底基板一侧的第一空穴传输层155、设置于第一空 穴传输层155远离衬底基板一侧的第二发光层156、设置于第二发光层156远离衬底基板一侧的第一电子传输层157、设置于第一电子传输层157远离衬底基板一侧的电荷生成层152、设置于电荷生成层152远离衬底基板一侧的第二空穴传输层158、设置于第二空穴传输层158远离衬底基板一侧的第一发光层153、设置于第一发光层153远离衬底基板一侧的第二电子传输层159以及设置于第二电子传输层159远离衬底基板一侧的第二电极154。
在上述像素膜层结构中，电荷生成层152可以包括第一生成层和第二生成层。第一生成层可以为N型电荷生成层，第二生成层可以为P型电荷生成层。其中，N型电荷生成层包括金属材料(例如Li、Mg、Ca、Cs、Yb)。P型电荷生成层由金属氧化物(例如ITO、WO3、MoO3、V2O5、ReO3)，或者由空穴传输材料掺杂路易斯酸(例如FeCl3:NPB、F4-TCNQ:NPB)，或者由P型有机材料(例如HATCN)组成。N型电荷生成层可以改善电子的注入和迁移特性，从而降低驱动电压以及改善装置的效率和寿命。
在上述像素膜层结构中，第一空穴传输层155和第二空穴传输层158可以起到促进空穴的传输的作用。第一空穴传输层155和第二空穴传输层158的材料可以包括选自以下的任一者：例如NPD(N,N-二萘基-N,N'-二苯基联苯胺)(N,N'-双(萘-1-基)-N,N'-双(苯基)-2,2'-二甲基联苯胺)、TPD(N,N'-双-(3-甲基苯基)-N,N'-双-(苯基)-联苯胺)、和MTDATA(4,4',4-三(N-3-甲基苯基-N-苯基-氨基)-三苯胺)。然而，本实施例不限于此。
在上述像素膜层结构中，空穴注入层151可以促进空穴的注入。空穴注入层151可以由选自以下的至少一者制成：例如CuPc(铜酞菁)、PEDOT(聚(3,4)-乙烯二氧基噻吩)、PANI(聚苯胺)、NPD(N,N-二萘基-N,N'-二苯基联苯胺)及其组合。然而，本实施例不限于此。
在上述像素膜层结构中，第一电子传输层157和第二电子传输层159接收来自第二电极的电子，并且可以将供给的电子转移至发光层。第一电子传输层157和第二电子传输层159还用于促进电子的传输。第一电子传输层157和第二电子传输层159材料可以包括选自以下的至少一者：例如Alq3(三(8-羟基喹啉)铝)、Liq(8-羟基喹啉锂)、PBD(2-(4-联苯基)-5-(4-叔丁基苯基)-1,3,4-二唑)、TAZ(3-(4-联苯)-4-苯基-5-叔丁基苯基-1,2,4-三唑)、螺-PBD、BAlq(双 (2-甲基-8-喹啉)-4-(苯基苯酚)铝)、SAlq、TPBi(2,2',2-(1,3,5-苯三基)-三(1-苯基-1-H-苯并咪唑)(2,2',2-(1,3,5-benzinetriyl)-tris(1-phenyl-1-H-benzimidazole)))、二唑、三唑、菲咯啉、苯并唑和苯并噻唑。然而，本实施例不限于此。
在上述像素膜层结构中，第二电极154可由高导电性和低功函数的材料形成，比如，第二电极154材料可以包括镁铝合金(MgAl)、锂铝合金(LiAl)等合金或者镁、铝、锂、银等单金属。
下面通过本实施例显示基板的制备过程进一步说明本实施例的技术方案。其中，本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光、显影等处理，本实施例中所说的蒸镀、沉积、涂覆、涂布等均是相关技术中成熟的制备工艺。
显示基板的制备过程包括：
1)在衬底基板10之上形成绝缘层16，在绝缘层16之上沉积金属薄膜，通过构图工艺对金属薄膜进行构图，在绝缘层16远离衬底基板10一侧形成至少两个第一电极11，至少两个第一电极11间隔设置。相邻第一电极11之间互相断开，且相邻第一电极11之间形成间隔区12。在第一电极11远离衬底基板10一侧形成PR保护膜(图中未示出)，如图1所示。其中，金属薄膜可以采用具有高功函数的透明导电材料，金属薄膜材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
2)在第一电极11远离衬底基板10一侧涂覆覆盖整个衬底基板10的隔离材料层，通过刻蚀工艺，对隔离材料层进行干刻，将间隔区12上的隔离材料层去除，将第一电极11上的隔离材料层部分去除，第一电极11上剩余的隔离材料层形成隔离柱13，隔离柱13位于第一电极11靠近间隔区12的一侧，相邻隔离柱13在间隔区12形成隔离槽14。至少一个第一电极11的相对两侧均设置有隔离柱13，一个第一电极11上相对两侧的隔离柱13形成像素开口，该像素开口将该第一电极11暴露，如图1所示。其中，隔离材料层的厚度为200至2000埃米，隔离材料层的材料可以采用无机材料。隔离槽 14的宽度和深度可以根据像素膜层的厚度进行设定，只要保证隔离槽14能够阻断相邻像素膜层中的空穴注入层和电荷生成层，且不会使第二电极发生断裂即可。
3)通过掩膜工艺，在第一电极11远离衬底基板10一侧形成像素膜层15。其中，像素膜层15至少包括设置于第一电极远离衬底基板一侧的空穴注入层151、设置于空穴注入层151远离衬底基板一侧的第一空穴传输层155、设置于第一空穴传输层155远离衬底基板一侧的第二发光层156、设置于第二发光层156远离衬底基板一侧的第一电子传输层157、设置于第一电子传输层157远离衬底基板一侧的电荷生成层152、设置于电荷生成层152远离衬底基板一侧的第二空穴传输层158、设置于第二空穴传输层158远离衬底基板一侧的第一发光层153、设置于第一发光层153远离衬底基板一侧的第二电子传输层159以及设置于第二电子传输层159远离衬底基板一侧的第二电极154，像素膜层15中的空穴注入层151和电荷生成层152被隔离槽14隔断。像素膜层15中的第二电极154没有被隔离槽14隔断，如图2和图3所示。
4)在像素膜层之上形成封装层，以对像素膜层进行封装。
5)在封装层之上形成低温彩膜结构层，实现显示效果。
图4为本公开实施例显示基板形成隔离槽后的示意图二。图4示意了本公开实施例显示基板一种示例性实施方式。如图4所示，本公开实施例显示基板与前述实施例显示基板的主体结构基本相同，所不同的是，第一电极11与衬底基板10之间设置有覆盖衬底基板10的绝缘层16，相邻第一电极11之间间隔区上的绝缘层16设置有向内凹陷的隔离槽14。隔离槽14与第一电极11形成段差，以确保阻断相邻第一电极11上像素膜层的横向电流，防止相邻第一电极上像素膜层串扰。
如图4所示，隔离槽14具有侧壁141和底壁142，侧壁141与底壁142之间的夹角c不小于80度。比如，侧壁141与底壁142之间的夹角c为90度。侧壁141与底壁142之间的夹角c不小于80度，以确保在形成像素膜层过程中，像素膜层在隔离槽14处发生断裂，从而实现阻断相邻第一电极11 上像素膜层的横向电流。
在一种示例性实施方式中，隔离槽的深度不大于2000埃米，以确保隔离槽能够阻断相邻像素膜层的横向电流，且保证像素膜层中的第二电极(阴极)不会发生断裂。
图5为本公开实施例显示基板形成隔离槽后的示意图三。图5示意了本公开实施例显示基板一种示例性实施方式。如图5所示，本公开实施例显示基板与前述实施例显示基板的主体结构基本相同，所不同的是，所述至少两个第一电极11远离所述衬底基板10的一侧设置有隔离柱13，所述隔离柱13位于所述第一电极11靠近所述间隔区12的一侧，相邻的隔离柱13之间在间隔区上形成第一凹槽17。第一电极11与衬底基板10之间设置有覆盖衬底基板10的绝缘层16，相邻第一电极11之间间隔区上的绝缘层16设置有向内凹陷的第二凹槽18。第二凹槽18在衬底基板10的正投影位于第一凹槽17在衬底基板10的正投影中。第一凹槽17和第二凹槽18组合形成隔离槽14。
在一种示例性实施方式中，本公开实施例中的隔离柱13的形状和尺寸与图1所示的显示基板中的隔离柱的形状和尺寸相同。本实施例在此不再赘述。
在一种示例性实施方式中，本公开实施例中的第二凹槽18与图4所示的显示基板中的隔离槽的形状和尺寸相同。本实施例在此不再赘述。
本公开实施例在形成隔离槽14的过程中，先在第一电极11上形成隔离柱13，随后在绝缘层16上形成第二凹槽18。或者，先在绝缘层16上形成第二凹槽18，随后在第一电极11上形成隔离柱13。
本实施例还提供了一种显示基板的制备方法，包括：
S1、在衬底基板的一侧形成至少两个第一电极，至少两个第一电极间隔设置，使相邻所述第一电极之间形成间隔区；
S2、在所述间隔区上形成隔离槽；
S3、在所述第一电极上形成像素膜层，相邻所述第一电极上的像素膜层通过所述隔离槽电性隔断。
在一种示例性实施方式中，步骤S2包括：
在所述第一电极远离衬底基板一侧形成隔离柱，隔离柱位于第一电极靠近所述间隔区的一侧，使相邻隔离柱在间隔区形成所述隔离槽。
在一种示例性实施方式中，本实施例显示基板的制备方法，包括：
S1、在衬底基板的一侧形成覆盖所述衬底基板的绝缘层；
S2、在所述绝缘层远离衬底基板一侧形成至少两个第一电极，至少两个第一电极间隔设置，使相邻所述第一电极之间形成间隔区；
S3、在相邻所述第一电极之间间隔区上的绝缘层16中形成向内凹陷的所述隔离槽。
在一种示例性实施方式中，本实施例显示基板的制备方法，包括：
S1、在衬底基板的一侧形成覆盖所述衬底基板的绝缘层；
S2、远离衬底基板一侧形成至少两个第一电极，至少两个第一电极间隔设置，使相邻所述第一电极之间形成间隔区；
S3、在所述至少两个第一电极远离衬底基板一侧形成隔离柱，隔离柱位于至少两个第一电极靠近所述间隔区的一侧，使相邻隔离柱在间隔区形成第一凹槽；
S4、在相邻所述至少两个第一电极之间间隔区上的绝缘层中形成向内凹陷的第二凹槽，所述第一凹槽与所述第二凹槽组合形成所述隔离槽。
在一种示例性实施方式中，本实施例显示基板的制备方法，包括：
S1、在衬底基板的一侧形成覆盖所述衬底基板的绝缘层；
S2、远离衬底基板一侧形成至少两个第一电极，至少两个第一电极间隔设置，使相邻所述第一电极之间形成间隔区；
S3、在相邻所述第一电极之间间隔区上的绝缘层中形成向内凹陷的第二凹槽；
S4、在所述第一电极远离衬底基板一侧形成隔离柱，隔离柱位于第一电极靠近所述间隔区的一侧，使相邻隔离柱在间隔区形成第一凹槽，所述第一凹槽与所述第二凹槽组合形成所述隔离槽。
本公开实施例还提供了一种显示装置，包括前述任一实施例的显示基板。显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (14)

  1. 一种显示基板，包括衬底基板以及设置于所述衬底基板一侧的至少两个间隔设置的第一电极，所述第一电极远离所述衬底基板一侧设置有像素膜层，相邻所述第一电极之间形成间隔区，所述间隔区远离所述衬底基板一侧设置有隔离槽，所述隔离槽将相邻所述第一电极上的像素膜层电性隔断。
  2. 根据权利要求1所述的显示基板，其中，所述至少两个第一电极远离所述衬底基板的一侧设置有隔离柱，所述隔离柱位于所述第一电极靠近所述间隔区的一侧，相邻所述第一电极的隔离柱之间在间隔区形成所述隔离槽。
  3. 根据权利要求2所述的显示基板，其中，所述隔离柱具有靠近所述隔离槽一侧的第一侧壁，所述第一侧壁与所述衬底基板之间的夹角不小于80度。
  4. 根据权利要求2所述的显示基板，其中，所述隔离柱具有远离所述隔离槽一侧的第二侧壁，所述第二侧壁与所述第一电极远离所述衬底基板一侧表面之间的内角小于60度。
  5. 根据权利要求2所述的显示基板，其中，所述隔离柱远离所述衬底基板一侧的表面到所述第一电极远离所述衬底基板一侧的表面的距离为200至2000埃米。
  6. 根据权利要求2所述的显示基板，其中，所述衬底基板包括至少两个子像素区以及位于相邻所述子像素区之间的非显示区，所述隔离柱在所述衬底基板的正投影与所述非显示区在所述衬底基板的正投影交叠。
  7. 根据权利要求2所述的显示基板，其中，所述像素膜层包括设置于所述第一电极远离所述衬底基板一侧的电荷生成层，所述电荷生成层远离所述衬底基板一侧的表面不高于所述隔离柱远离所述衬底基板一侧的表面。
  8. 根据权利要求7所述的显示基板，其中，所述像素膜层还包括设置于所述电荷生成层远离所述衬底基板一侧的发光层以及设置于所述发光层远离所述衬底基板一侧的第二电极，所述发光层远离所述衬底基板一侧的表面高于所述隔离柱远离所述衬底基板一侧的表面。
  9. 根据权利要求2所述的显示基板，其中，所述第一电极与所述衬底基板之间设置有覆盖所述衬底基板的绝缘层，所述像素膜层的厚度等于所述绝缘层的厚度与所述第一电极的厚度之和。
  10. 根据权利要求1所述的显示基板，其中，所述第一电极与所述衬底基板之间设置有覆盖所述衬底基板的绝缘层，相邻所述第一电极之间所述间隔区上的所述绝缘层设置有向内凹陷的所述隔离槽。
  11. 根据权利要求10所述的显示基板，其中，所述隔离槽具有侧壁和底壁，所述侧壁与所述底壁之间的夹角不小于80度。
  12. 根据权利要求10所述的显示基板，其中，所述隔离槽的深度不大于2000埃米。
  13. 根据权利要求1所述的显示基板，其中，所述至少两个第一电极远离所述衬底基板的一侧设置有隔离柱，所述隔离柱位于所述第一电极靠近所述间隔区的一侧，相邻的所述隔离柱之间在所述间隔区形成第一凹槽，所述至少两个第一电极与所述衬底基板之间设置有覆盖所述衬底基板的绝缘层，相邻第一电极之间间隔区上的绝缘层设置有向内凹陷的第二凹槽，所述第一凹槽与所述第二凹槽组合形成所述隔离槽。
  14. 一种显示装置，包括如权利要求1-13任一所述的显示基板。
PCT/CN2021/098417 2020-06-12 2021-06-04 显示基板、显示装置 WO2021249309A1 (zh)

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CN111668380B (zh) * 2020-06-12 2023-07-14 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030084233A (ko) * 2002-04-25 2003-11-01 엘지.필립스 엘시디 주식회사 유기전계발광 소자 및 그의 제조방법
CN101170856A (zh) * 2007-11-13 2008-04-30 京东方科技集团股份有限公司 有机电致发光显示装置及其制造方法
CN108493228A (zh) * 2018-05-23 2018-09-04 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板
CN208797004U (zh) * 2018-09-25 2019-04-26 合肥视涯显示科技有限公司 一种有机发光显示装置
CN110783481A (zh) * 2019-08-30 2020-02-11 昆山国显光电有限公司 显示面板、显示屏及显示装置
CN111668380A (zh) * 2020-06-12 2020-09-15 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100838090B1 (ko) * 2007-08-09 2008-06-13 삼성에스디아이 주식회사 유기 발광 표시장치 및 이의 제조방법
TW201321871A (zh) * 2011-11-29 2013-06-01 Au Optronics Corp 顯示面板及其製作方法
CN104538423B (zh) * 2014-12-22 2017-10-13 深圳市华星光电技术有限公司 Oled显示器件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030084233A (ko) * 2002-04-25 2003-11-01 엘지.필립스 엘시디 주식회사 유기전계발광 소자 및 그의 제조방법
CN101170856A (zh) * 2007-11-13 2008-04-30 京东方科技集团股份有限公司 有机电致发光显示装置及其制造方法
CN108493228A (zh) * 2018-05-23 2018-09-04 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板
CN208797004U (zh) * 2018-09-25 2019-04-26 合肥视涯显示科技有限公司 一种有机发光显示装置
CN110783481A (zh) * 2019-08-30 2020-02-11 昆山国显光电有限公司 显示面板、显示屏及显示装置
CN111668380A (zh) * 2020-06-12 2020-09-15 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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