WO2018086347A1 - 阵列基板及其制造方法、显示器 - Google Patents

阵列基板及其制造方法、显示器 Download PDF

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Publication number
WO2018086347A1
WO2018086347A1 PCT/CN2017/088078 CN2017088078W WO2018086347A1 WO 2018086347 A1 WO2018086347 A1 WO 2018086347A1 CN 2017088078 W CN2017088078 W CN 2017088078W WO 2018086347 A1 WO2018086347 A1 WO 2018086347A1
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Prior art keywords
light emitting
thin film
emitting units
substrate
film transistors
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PCT/CN2017/088078
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English (en)
French (fr)
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张粲
付杰
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京东方科技集团股份有限公司
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Priority to US15/743,465 priority Critical patent/US10811475B2/en
Publication of WO2018086347A1 publication Critical patent/WO2018086347A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/19—Tandem OLEDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/164—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using vacuum deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • At least one embodiment of the present invention is directed to an array substrate, a method of fabricating the same, and a display.
  • Silicon-based active matrix organic light-emitting diode (AMOLED) microdisplays have broad market applications, and are particularly suitable for use in head-mounted displays, stereoscopic display glasses, and eyeglass-type displays. When combined with systems such as mobile communication networks and satellite positioning, accurate image information can be obtained anywhere and at any time. Silicon-based AMOLED microdisplays provide high-quality video displays for mobile information products such as portable computers, wireless Internet browsers, portable DVDs, gaming platforms and wearable computers. Therefore, silicon-based AMOLED microdisplays provide an excellent near-eye application (such as helmet display) for both consumer and industrial applications as well as military applications.
  • AMOLED active matrix organic light-emitting diode
  • At least one embodiment of the present invention provides an array substrate, a method of manufacturing the same, and a display.
  • the array substrate can achieve the effect of full coloring without using a color filter, and can be converted between a monochrome display and a full color display, and the pixel density can be improved.
  • At least one embodiment of the present invention provides an array substrate including a substrate, wherein a plurality of pixel units arranged in an array are disposed on the substrate, and a plurality of thin film transistors are disposed in each of the pixel units, and each of the pixel units includes a plurality of a plurality of light emitting units arranged in a direction perpendicular to a plane of the substrate, and disposed on a side of the thin film transistor away from the substrate, and each light emitting unit is connected to one of the plurality of thin film transistors, and different light emitting units Connect to different thin film transistors.
  • the method further includes: a retaining wall surrounding each pixel unit to define a region for forming the light emitting unit.
  • the thickness of the retaining wall gradually decreases from a direction close to the substrate to a distance from the substrate.
  • At least one of the plurality of thin film transistors is formed between the barrier wall and the substrate, and at least one of the plurality of light emitting units passes through the through hole provided in the retaining wall.
  • Corresponding thin film transistors are connected.
  • the method further includes: a thin film encapsulation layer, On the side of each of the light-emitting units away from the substrate.
  • each of the light emitting units includes a first electrode, a light emitting layer, and a second electrode, and the first electrode is connected to the corresponding thin film transistor.
  • the plurality of light emitting units respectively emit light of different colors.
  • each pixel unit includes three thin film transistors and three light emitting units, and the three light emitting units respectively emit red light, green light, and blue light.
  • the maximum size of each of the plurality of light emitting units in a direction parallel to the plane of the substrate is less than 10 micrometers.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising forming a plurality of pixel units arranged in an array on a substrate, and forming each pixel unit includes: forming a plurality of thin film transistors on the substrate; A plurality of light emitting units are formed on the transistor, the plurality of light emitting units are sequentially arranged in a direction perpendicular to a plane of the substrate, and each of the light emitting units is connected to one of the plurality of thin film transistors, and the different light emitting units are connected to different thin film transistors.
  • the method further includes: after forming the plurality of thin film transistors, forming a retaining wall to define a region for forming the light emitting unit, wherein forming on the plurality of thin film transistors
  • the plurality of light emitting units include: forming, by the vapor deposition method, at least one of the at least one light emitting unit by using the retaining wall as an evaporation mask.
  • one of the light-emitting units closest to the thin film transistor is formed by an etching method.
  • At least one of the plurality of thin film transistors is formed between the retaining wall and the substrate, and forming the retaining wall includes: forming a through hole in the retaining wall to make At least one of the light emitting cells is connected to a corresponding thin film transistor through a via.
  • the method further includes: forming a thin film encapsulation layer on a side of each of the light emitting units away from the substrate.
  • At least one embodiment of the present invention provides a display comprising any of the above array substrates.
  • FIG. 1a is a schematic diagram of an array substrate according to an embodiment of the invention.
  • Figure 1b is a schematic cross-sectional view of a pixel unit shown in Figure 1a along the AB direction;
  • FIG. 2 is a schematic diagram of a pixel unit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a layer of a light emitting unit in a pixel unit according to an embodiment of the invention
  • FIG. 4 is a schematic flowchart of a method for fabricating each pixel unit in an array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a method for fabricating each pixel unit in an array substrate according to another embodiment of the present invention.
  • a silicon-based active matrix organic light emitting diode (AMOLED) colorization method is prepared by using a white organic light emitting diode (WOLED) and a color filter (CF), but the transmittance of the color filter is low, about For 30-40%, most of the light efficiency will be lost and the power consumption of the display will be increased.
  • the pixel density (PPI) accuracy obtained by directly vapor-depositing red, green and blue pixel units using high-precision metal mask (FMM) technology is not sufficient, and cannot be used in the preparation of micro-OLEDs.
  • Micro OLEDs have smaller pixels, typically a few microns, and high-precision metal reticle technology does not meet the accuracy requirements of micro OLEDs.
  • At least one embodiment of the present invention provides an array substrate including a substrate, wherein a plurality of pixel units arranged in an array are disposed on the substrate, and a plurality of thin film transistors are disposed in each of the pixel units, and each of the pixel units includes a plurality of The plurality of light emitting units are arranged in a direction perpendicular to a plane of the substrate, and are disposed on a side of the thin film transistor away from the substrate, and the plurality of light emitting units are connected in one-to-one correspondence with the plurality of thin film transistors. That is, each of the light emitting units is connected to one of the plurality of thin film transistors, and the different light emitting units are connected to different thin film transistors.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising forming a plurality of pixel units arranged in an array on a substrate, and forming each pixel unit includes: forming a plurality of thin film transistors on the substrate; A plurality of light emitting units are formed on the transistor, the plurality of light emitting units are sequentially arranged in a direction perpendicular to a plane of the substrate, and each of the light emitting units is connected to one of the plurality of thin film transistors, and the different light emitting units are connected to different thin film transistors.
  • the manufacturing method of the array substrate can achieve the effect of achieving full color without using a color filter, and can be converted between a monochrome display and a full color display, and the pixel density can be improved.
  • At least one embodiment of the present invention provides a display comprising any of the above array substrates, which can be switched between a monochrome display and a full color display, and can increase pixel density.
  • the present embodiment provides an array substrate, as shown in FIG. 1a, including a substrate 10 on which a plurality of pixel units 100 arranged in an array are disposed, and a plurality of thin film transistors 140 are disposed in each of the pixel units 100. , 150 and 160.
  • the plurality of thin film transistors 140, 150, and 160 may be arranged in parallel on the substrate 10.
  • the embodiment is not limited thereto, and may be arranged in other arrangements.
  • 1a is an exemplary schematic diagram of the distribution and number of thin film transistors, in which three thin film transistors 140, 150, and 160 are shown in each pixel unit 100, however, embodiments according to the present invention are not limited thereto, for example, a thin film
  • the number of transistors can be two, four or more.
  • Fig. 1b shows a schematic cross-sectional view of a pixel unit 100 of Fig. 1a in the AB direction.
  • each of the pixel units 100 includes a plurality of light emitting units 110, 120, and 130, and the plurality of light emitting units 110, 120, and 130 are sequentially arranged in a direction perpendicular to a plane of the substrate 10, and are disposed in a plurality of thin films.
  • the transistors 140, 150, and 160 are away from the side of the substrate 10, that is, the plurality of light emitting units 110, 120, and 130 are sequentially stacked as shown in FIG. 1b.
  • each of the light emitting units is connected to one of the thin film transistors 140, 150, and 160, and the different light emitting units are connected to different thin film transistors.
  • the number of thin film transistors is consistent with the number of light emitting units, and each thin film transistor is used to individually control one light emitting unit to emit light or not to emit light, thereby achieving the effect of achieving full color without using a color filter, and Convert between monochrome display and full color display.
  • the array substrate further includes a retaining wall 200 surrounding each pixel unit 100 to define regions for forming the light emitting units 110, 120, and 130, that is, adjacent pixel units 100. They are separated by a retaining wall 200.
  • FIG. 1 a shows a schematic diagram of the shape of the pixel unit 100 being a rectangle. The embodiment is not limited thereto, and the shape of the pixel unit 100 may also be a circle or a polygon.
  • the shape and size of the pattern of at least one of the plurality of light emitting units 110, 120, and 130 in the pixel unit 100 are the same as the shape and size of the area defined by the retaining wall 200, that is, the retaining wall 200 and At least one of the plurality of light emitting units 110, 120, and 130 is in close contact to define the shape and size of the light emitting unit.
  • the retaining wall 200 may surround the second and second light emitting units 120 and 130 to define the shapes and sizes of the second and third light emitting units 120 and 130, and the present invention is not limited thereto. It should be noted that the retaining wall 200 may pattern the shape and size of all the light emitting units, or pattern and shape all other light emitting units except the light emitting unit closest to the thin film transistor.
  • the retaining wall 200 can be patterned as a mask to form at least one light emitting unit.
  • the retaining wall 200 is vapor deposited as a vapor deposition mask to form at least one layer of at least one light emitting unit. Therefore, by using the retaining wall 200 as a mask, the high-precision metal mask and color filter required for fabricating the organic light emitting diode are omitted, and the pixel density of the organic light emitting diode can be improved.
  • the retaining wall 200 can be used as a mask to pattern a light emitting unit of a micro organic light emitting diode.
  • the size of each light emitting unit (the largest dimension parallel to the substrate direction) is less than 10 microns.
  • the size of each of the light emitting units includes 2 micrometers to 4 micrometers.
  • the retaining wall 200 can be used as a reticle to pattern a light emitting unit of a general organic light emitting diode.
  • the height of the retaining wall 200 in a direction perpendicular to the plane of the substrate 10 may be higher than the overall height of the plurality of light emitting units 110, 120, and 130, for example, the height exceeds 3 micrometers. -6 microns.
  • the embodiment is not limited thereto, and the height of the retaining wall 200 in a direction perpendicular to the plane of the substrate 10 may also be equal to the height of the plurality of light emitting units 110, 120, and 130 as a whole.
  • the height of the retaining wall 200 is greater than or equal to the height of the plurality of light emitting units 110, 120, and 130 as a whole, which can reduce the pressure on the pixel unit 100 when the package is vacuumed, and reduce the probability of pixel damage.
  • the thickness of the retaining wall 200 gradually decreases from a direction close to the substrate 10 to away from the substrate 10.
  • the thickness of the retaining wall 200 refers to the width of the cross section of the retaining wall 200.
  • the cross section of the retaining wall 200 in the AB direction includes a trapezoid, and the embodiment is not limited thereto, and may be a triangle or a stepped type.
  • the sizes of the plurality of light emitting units 110, 120, and 130 in the direction away from the substrate 10 in the direction away from the substrate 10 do not completely coincide, for example, sequentially increase.
  • the size of the third light emitting unit 130 is larger than the size of the second light emitting unit 120
  • the size of the second light emitting unit 120 is larger than the size of the first light emitting unit 110.
  • the retaining wall 200 includes a first through hole 201 and a second through hole 202.
  • the first thin film transistor 140 is electrically connected to the second light emitting unit 120 through the first through hole 201
  • the third thin film transistor 160 is electrically connected to the third light emitting unit 130 through the second through hole 202.
  • the first through hole 201 and the second through hole 202 may be formed by laser drilling the retaining wall 200.
  • the embodiment is not limited thereto, and the through hole may be formed by etching or the like.
  • the material of the retaining wall 200 may be a photoresist or other organic material, and the embodiment is not limited thereto.
  • FIG. 2 is a schematic diagram of a pixel unit according to an embodiment of the present invention.
  • each pixel unit 100 includes three thin film transistors 140 , 150 , and 160 arranged on a substrate 10 , and a thin film transistor 140 ,
  • the two light emitting units 110, 120, and 130 are sequentially disposed in a direction perpendicular to the plane of the substrate 10, and each of the light emitting units is connected to one of the plurality of thin film transistors 140, 150, and 160.
  • different light emitting units are connected to different thin film crystals Body tube.
  • the first thin film transistor 140 is electrically connected to the third light emitting unit 130
  • the second thin film transistor 150 is electrically connected to the first light emitting unit 110
  • the third thin film transistor 160 is electrically connected to the second light emitting unit 120.
  • the embodiment is not limited thereto, and the first thin film transistor 140 is electrically connected to the second light emitting unit 120, the second thin film transistor 150 is electrically connected to the first light emitting unit 110, and the third thin film transistor 160 is electrically connected to the third light emitting unit 130.
  • the connecting line of each of the thin film transistors and the corresponding light emitting unit in FIG. 2 is an exemplary schematic diagram of an electrical connection relationship.
  • the first electrode material is vapor-deposited through the through holes, so that the light emitting unit is An electrode is connected to the drain of the thin film transistor.
  • the plurality of light emitting units 110, 120, and 130 respectively emit light of different colors.
  • the first light emitting unit 110, the second light emitting unit 120, and the third light emitting unit 130 may be a red light emitting unit, a green light emitting unit, and a blue light emitting unit, respectively, and the embodiment is not limited thereto.
  • different light-emitting units have different decay lifetimes, and the green light-emitting unit generally has a longer decay life than red and blue light-emitting units, and the thin film transistors 140, 150, and 160 can be separately controlled in each pixel unit 100 according to an actual application scenario.
  • the green light emitting unit 120 is separately illuminated, and the other color light emitting units do not emit light, and a green light monochrome display is obtained.
  • each of the pixel units 100 at least one of the light emitting units 110, 120, and 130 is controlled to emit light by the thin film transistors 140, 150, and 160, respectively, and an organic light emitting diode display of a different color can be obtained.
  • the thin film transistors 140, 150, and 160 in each of the pixel units 100 respectively control one of the three different light emitting units 110, 120, and 130 to emit light
  • the thin film transistors 140, 150, and 160 in the three pixel units 100 respectively control the third light emitting unit 130 in the first pixel unit to emit light, the first light emitting unit 110 in the second pixel unit to emit light, and the third pixel.
  • the second light emitting unit 120 in the unit emits light, and a full color display can be realized.
  • the embodiment is not limited thereto.
  • controlling the entire illumination of the illumination units 110, 120, and 130 by the thin film transistors 140, 150, and 160 in the pixel unit 100 can result in a full-color display, and the full-color display has higher performance than a general full-color display.
  • the pixel density that is, the same high-resolution display as the physical pixel size can be obtained.
  • each of the light emitting units includes a first electrode, a light emitting layer, and a second electrode, as shown in FIG. 2,
  • the first light emitting unit 110 includes a first electrode 111, a light emitting layer 112, and a second electrode 113.
  • the second light emitting unit 120 includes a first electrode 121, a light emitting layer 122, and a second electrode 123.
  • the third light emitting unit 130 includes a first electrode 131.
  • the light emitting layer 132 and the second electrode 133 is the first electrode, a light emitting layer, and a second electrode, as shown in FIG. 2
  • the first light emitting unit 110 includes a first electrode 111, a light emitting layer 112, and a second electrode 113.
  • the second light emitting unit 120 includes a first electrode 121, a light emitting layer 122, and a second electrode 123.
  • the third light emitting unit 130 includes a first electrode 131.
  • the first electrode 111 of the first light emitting unit 110, the first electrode 121 of the second light emitting unit 120, and the first electrode 131 of the third light emitting unit 130 are anodes
  • the second electrodes 113 and second of the first light emitting unit 110 are
  • the second electrode 123 of the light emitting unit 120 and the second electrode 133 of the third light emitting unit 130 are cathodes, and the embodiment is not limited thereto.
  • the anode of each light emitting unit is separately connected to the corresponding thin film transistor, and the corresponding thin film transistor controls each light emitting unit to emit light or not.
  • the material of the first electrode and the second electrode is a conductive material.
  • the other first electrode and the second electrode need to adopt a transparent conductive material, so that the light emitted by the light emitting unit can be well emitted.
  • the material of the first electrode 111 of the first light emitting unit 110 may be a transparent conductive material or an opaque conductive material.
  • the materials of the first electrode and the second electrode may also include a metal oxide material or a metal material.
  • the metal oxide material includes indium tin oxide, indium zinc oxide doped, etc., for example, having a thickness of 300 to 500 nm, and the embodiment is not limited thereto.
  • the metal material includes silver, aluminum, or the like, for example, the thickness is 10-20 nm, and the embodiment is not limited thereto, and the metal material can achieve a transparent thickness.
  • FIG. 3 is a schematic diagram of a light emitting unit in a pixel unit according to an embodiment of the invention.
  • FIG. 3 only shows the layer structure of the light-emitting unit.
  • a thin film encapsulation layer disposed on each of the light-emitting units away from the substrate side is included.
  • a first thin film encapsulation layer 310 is disposed between the first light emitting unit 110 and the second light emitting unit 120
  • a second thin film encapsulation layer 320 is disposed between the second light emitting unit 120 and the third light emitting unit 130.
  • the third thin film encapsulation layer 330 is disposed on a side of the unit 130 away from the second light emitting unit 120, and the embodiment is not limited thereto.
  • the thin film encapsulation layers 310, 320, and 330 may separate each of the light emitting units to provide an insulating effect between the respective light emitting units. It should be noted that the materials of the thin film encapsulation layers 310, 320, and 330 are transparent insulating materials, so that the light emitted by the light emitting unit can be well emitted.
  • the embodiment provides a method for fabricating an array substrate, comprising forming a plurality of pixel units arranged in an array on the substrate, and forming each pixel unit comprises: forming a plurality of thin film transistors on the substrate;
  • the substrate may be a silicon substrate, this embodiment Not limited to this.
  • the manufacturing method of the array substrate can achieve the effect of achieving full color without using a color filter, and can be converted between a monochrome display and a full color display, and the pixel density can be improved.
  • the method for fabricating the array substrate provided by the embodiment further includes: after forming the plurality of thin film transistors, forming a retaining wall to define a region for forming the light emitting unit, and using the vapor barrier as the vapor deposition mask The method forms at least one layer of at least one of the plurality of light emitting units.
  • the retaining wall is used as the vapor deposition mask, and at least one light emitting unit is patterned, the high-precision metal mask and the color filter required for fabricating the organic light emitting diode are omitted, and the pixel density of the organic light emitting diode can be improved.
  • the provision of a retaining wall around each pixel unit can reduce the pressure on the pixel unit when vacuuming the package, and reduce the probability of pixel damage.
  • the retaining wall can be used as a reticle to pattern the light-emitting unit of the micro-organic light-emitting diode, or can be patterned to form a light-emitting unit of a general organic light-emitting diode.
  • each pixel unit includes the following steps.
  • S102 forming a retaining wall to define an area for forming a light emitting unit
  • S103 forming a plurality of light emitting units by a vapor deposition method by using a retaining wall as a vapor deposition mask.
  • each pixel unit specifically includes the following steps:
  • Step 1 In the region of the general sub-pixel size on the substrate, three thin film transistors arranged in parallel are formed. Since the semiconductor substrate can be fabricated in the array substrate, the refined thin film transistor is relatively easy to fabricate.
  • step two a retaining wall is formed around the three parallel-arranged thin film transistors to define a region for forming the light-emitting unit.
  • Step 3 the first light-emitting unit is vapor-deposited around the defined area in the retaining wall, that is, the first light-emitting unit is patterned by using the retaining wall as a mask, and the size and shape of the first light-emitting unit are exactly the same as the surrounding area of the retaining wall. .
  • the thickness of the retaining wall gradually decreases from the vicinity of the substrate to the direction away from the substrate.
  • the thickness of the retaining wall here refers to the width of the cross section of the retaining wall.
  • the cross section of the retaining wall includes a trapezoidal shape, and the embodiment is not limited thereto, and may be a triangular shape or a stepped shape, so that the retaining wall surrounds the defined area, and the size of the plurality of light emitting units in the direction away from the substrate toward the substrate is incomplete. Coincident, for example, increases in turn.
  • the material of the retaining wall may be a photoresist or other organic material, and the embodiment is not limited thereto.
  • evaporating the first light emitting unit includes vaporizing the first electrode of the first light emitting unit, the light emitting layer, and
  • the second electrode the embodiment is not limited thereto, and may further include other functional layers, that is, a hole injection layer, a hole transport layer, a hole blocking layer, an electron injection layer, an electron transport layer, an electron blocking layer, and the like.
  • the first electrode is an anode
  • the second electrode is a cathode
  • the anode is electrically connected to a drain in a thin film transistor located in the middle of the three thin film transistors.
  • the material of the first electrode and the second electrode includes a conductive material.
  • the other electrodes are made of a transparent conductive material so that the light emitted from the light-emitting unit can be emitted well.
  • the material of the electrode of the first light-emitting unit closest to the substrate side may be a transparent conductive material or an opaque conductive material.
  • the material of the first electrode and the second electrode may include a metal oxide material or a metal material.
  • the metal oxide material includes indium tin oxide, indium zinc oxide doped, etc., for example, having a thickness of 300 to 500 nm, and the embodiment is not limited thereto.
  • the metal material includes silver, aluminum, or the like, for example, the thickness is 10-20 nm, and the embodiment is not limited thereto, and the metal material can achieve a transparent thickness.
  • At least one of the plurality of thin film transistors is formed between the barrier and the substrate, and the method includes:
  • a through hole is formed in the retaining wall, and at least one of the plurality of light emitting units is connected to the corresponding thin film transistor through the through hole.
  • the laser puncturing method is used to perforate the retaining wall above the thin film transistor, that is, to punch a retaining wall above any one of the three thin film transistors on both sides, and to evaporate the first of the second illuminating unit.
  • the electrode, the first electrode can be electrically connected to the drain of the thin film transistor through the formed via.
  • the subsequent film layer of the second light emitting unit is then patterned by using the retaining wall as a mask.
  • the embodiment is not limited thereto, and a through hole may be formed by etching.
  • Step 5 using a laser drilling method to perforate the retaining wall above the other thin film transistor on both sides, and evaporating the first electrode of the third light emitting unit, the first electrode can pass through the fabricated through hole and the thin film transistor The drain is electrically connected. Then, the subsequent film layer of the third light emitting unit is patterned by using the retaining wall as a mask.
  • a thin film encapsulation layer is formed on the side of each of the light emitting units away from the substrate.
  • the thin film encapsulation layer can be used to separate each of the light emitting units to provide an insulating effect between the respective light emitting units.
  • the material of the thin film encapsulation layer is a transparent insulating material, so that the light emitted by the light emitting unit can be well emitted.
  • This embodiment provides a method for fabricating an array substrate.
  • a method of manufacturing one of the light-emitting units closest to the thin film transistor is different from the manufacturing method provided in the second embodiment.
  • each pixel unit includes the following steps.
  • S202 a light emitting unit closest to the thin film transistor is formed by an etching method
  • S203 forming a retaining wall to define an area for forming the light emitting unit
  • each pixel unit specifically includes the following steps.
  • Step 1 In the region of the general sub-pixel size on the substrate, three thin film transistors arranged in parallel are formed. Since the semiconductor substrate can be fabricated in the array substrate, the refined thin film transistor is relatively easy to fabricate.
  • Step 2 The first light emitting unit closest to the thin film transistor is formed by an etching method, and the first light emitting unit is etched to include the first electrode, the light emitting layer and the second electrode of the first light emitting unit, and the embodiment is not limited thereto.
  • the first electrode is electrically connected to a drain of the thin film transistor located in the middle of the three thin film transistors.
  • etching method means that patterning of respective layers forming the light-emitting unit is performed by an etching process.
  • the step of forming the light-emitting layer includes first depositing a layer of the light-emitting material, and then etching the layer of the light-emitting material through a mask to form a light-emitting layer.
  • the first illuminating unit is affected. Therefore, it is necessary to provide a retaining wall for vapor deposition to form a subsequent illuminating unit, and the retaining wall is used as a reticle. Patterning forms other light emitting units.
  • the shape and size of the first light-emitting unit are not exactly the same as the shape and size of the light-emitting unit area defined by the subsequently formed retaining wall, and may be relatively smaller or larger. When the size of the first light emitting unit is larger than the size of the light emitting unit area defined by the subsequently formed retaining wall, the first light emitting unit does not coincide with the projection of the through hole formed in the retaining wall on the substrate.
  • step three a retaining wall is formed around the three parallel-arranged thin film transistors to define a region for forming the light-emitting unit.
  • the embodiment provides a display comprising any of the above array substrates, which can be switched between a monochrome display and a full color display, and can increase the pixel density.
  • the display includes an organic light emitting diode display, a micro organic light emitting diode display, and the like, and the embodiment is not limited thereto.
  • the display can be applied to a head-mounted display, a stereoscopic display mirror, a glasses-type display, and the like.

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Abstract

一种阵列基板及其制造方法、显示器。该阵列基板包括基板(10)，在基板(10)上设置呈阵列排布的多个像素单元(100)，在每个像素单元(100)中设置有多个薄膜晶体管(140，150，160)，每个像素单元(100)包括多个发光单元(110，120，130)，多个发光单元(110，120，130)依次沿垂直于基板(10)所在平面的方向排列，且设置在薄膜晶体管(140，150，160)远离基板(10)的一侧，其中，每个发光单元与多个薄膜晶体管(140，150，160)之一连接，且不同的发光单元(110，120，130)连接到不同的薄膜晶体管(140，150，160)。采用该阵列基板既可以达到不使用彩色滤光片而实现全彩化的效果，并在单色显示器和全彩化显示器之间转换，又可以提高像素密度。

Description

阵列基板及其制造方法、显示器 技术领域
本发明至少一实施例涉及一种阵列基板及其制造方法、显示器。
背景技术
硅基有源矩阵有机发光二极管(AMOLED)微显示器具有广阔的市场应用空间，特别适合应用于头盔显示器、立体显示镜以及眼镜式显示器等。如与移动通讯网络、卫星定位等系统联在一起则可在任何地方、任何时间获得精确的图像信息。硅基AMOLED微显示器能够为便携式计算机、无线互联网浏览器、便携式DVD、游戏平台及可戴式计算机等移动信息产品提供高画质的视频显示。因此，硅基AMOLED微显示器无论是对于民用消费领域还是工业应用乃至军事用途都提供了一个极佳的近眼应用(如头盔显示)途径。
发明内容
本发明的至少一实施例提供一种阵列基板及其制造方法、显示器。采用该阵列基板既可以达到不使用彩色滤光片而实现全彩化的效果，并在单色显示器和全彩显示器之间转换，又可以提高像素密度。
本发明的至少一实施例提供一种阵列基板，包括基板，在基板上设置呈阵列排布的多个像素单元，在每个像素单元中设置有多个薄膜晶体管，每个像素单元中包括多个发光单元，多个发光单元依次沿垂直于基板所在平面的方向排列，且设置在薄膜晶体管远离基板的一侧，并且，每个发光单元与多个薄膜晶体管之一连接，且不同的发光单元连接到不同的薄膜晶体管。
例如，在本实施例一示例提供的阵列基板中，还包括：挡墙，围绕每个像素单元以限定用于形成发光单元的区域。
例如，在本实施例一示例提供的阵列基板中，从靠近基板到远离基板的方向上，挡墙的厚度逐渐减小。
例如，在本实施例一示例提供的阵列基板中，多个薄膜晶体管中的至少之一形成在挡墙和基板之间，多个发光单元中的至少一个通过设置在挡墙中的通孔与对应的薄膜晶体管连接。
例如，在本实施例一示例提供的阵列基板中，还包括：薄膜封装层，设置 在每个发光单元远离基板的一侧。
例如，在本实施例一示例提供的阵列基板中，每个发光单元包括第一电极、发光层和第二电极，第一电极与对应的薄膜晶体管连接。
例如，在本实施例一示例提供的阵列基板中，多个发光单元分别发射不同颜色的光。
例如，在本实施例一示例提供的阵列基板中，每个像素单元包括三个薄膜晶体管和三个发光单元，三个发光单元分别发射红光、绿光和蓝光。
例如，在本实施例一示例提供的阵列基板中，多个发光单元的每个沿平行于基板所在平面的方向的最大尺寸小于10微米。
本发明的至少一实施例提供一种阵列基板的制造方法，包括在基板上形成阵列排布的多个像素单元，形成每个像素单元包括：在基板上形成多个薄膜晶体管；在多个薄膜晶体管上形成多个发光单元，多个发光单元依次沿垂直于基板所在平面的方向排列，并且，每个发光单元与多个薄膜晶体管之一连接，且不同的发光单元连接到不同的薄膜晶体管。
例如，在本实施例一示例提供的阵列基板的制造方法中，还包括：在形成多个薄膜晶体管之后，形成挡墙以限定用于形成发光单元的区域，其中，在多个薄膜晶体管上形成多个发光单元包括：以挡墙为蒸镀掩模板，采用蒸镀方法形成至少一个发光单元中的至少一层。
例如，在本实施例一示例提供的阵列基板的制造方法中，最靠近薄膜晶体管的一个发光单元采用刻蚀方法形成。
例如，在本实施例一示例提供的阵列基板的制造方法中，多个薄膜晶体管中的至少之一形成在挡墙和基板之间，形成挡墙包括：在挡墙中形成通孔以使多个发光单元中的至少一个通过通孔与对应的薄膜晶体管连接。
例如，在本实施例一示例提供的阵列基板的制造方法中，还包括：在每个发光单元远离基板的一侧形成薄膜封装层。
本发明的至少一实施例提供一种显示器，包括上述任一项阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为本发明一实施例提供的一种阵列基板示意图；
图1b为图1a示出的一个像素单元沿AB方向的截面示意图；
图2为本发明一实施例提供的一个像素单元示意图；
图3为本发明一实施例提供的一个像素单元中的发光单元层示意图；
图4为本发明一实施例提供的一种阵列基板中形成每个像素单元的制造方法的示意性流程图；
图5为本发明另一实施例提供的一种阵列基板中形成每个像素单元的制造方法的示意性流程图。
附图标记：10-基板；100-像素单元；110-第一发光单元；111-第一发光单元的第一电极；112-第一发光单元的发光层；113-第一发光单元的第二电极；120-第二发光单元；121-第二发光单元的第一电极；122-第二发光单元的发光层；123-第二发光单元的第二电极；130-第三发光单元；131-第三发光单元的第一电极；132-第三发光单元的发光层；133-第三发光单元的第二电极；140-第一薄膜晶体管；150-第二薄膜晶体管；160-第三薄膜晶体管；200-挡墙；201-第一通孔；202-第二通孔；310-第一薄膜封装层；320-第二薄膜封装层；330-第三薄膜封装层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相 对位置关系也可能相应地改变。
一种硅基有源矩阵有机发光二极管(AMOLED)彩色化方式均采用白光有机发光二极管(WOLED)配合彩色滤光片(CF)的方式制备，但是彩色滤光片的透过率较低，大约为30～40％，会损失大部分光效，增大显示器的功耗。一般使用高精度金属掩模板(FMM)技术直接蒸镀红绿蓝像素单元的方式得到的像素密度(PPI)精度不够，另外也不能用在微型有机发光二极管(micro-OLED)的制备上，因为微型有机发光二极管的像素较小，一般为几个微米，而高精度金属掩模板技术达不到微型有机发光二极管的精度要求。
本发明的至少一实施例提供一种阵列基板，包括基板，在基板上设置呈阵列排布的多个像素单元，在每个像素单元中设置有多个薄膜晶体管，每个像素单元中包括多个发光单元，多个发光单元依次沿垂直于基板所在平面的方向排列，且设置在薄膜晶体管远离基板的一侧，并且，多个发光单元与多个薄膜晶体管一一对应连接。也就是说，每个发光单元与多个薄膜晶体管之一连接，且不同的发光单元连接到不同的薄膜晶体管。采用该阵列基板，既可以达到不使用彩色滤光片而实现全彩化的效果，并在单色显示器和全彩化显示器之间转换，又可以提高像素密度。
本发明的至少一实施例提供一种阵列基板的制造方法，包括在基板上形成阵列排布的多个像素单元，形成每个像素单元包括：在基板上形成多个薄膜晶体管；在多个薄膜晶体管上形成多个发光单元，多个发光单元依次沿垂直于基板所在平面的方向排列，并且，每个发光单元与多个薄膜晶体管之一连接，且不同的发光单元连接到不同的薄膜晶体管。采用该阵列基板的制造方法，既可以达到不使用彩色滤光片而实现全彩化的效果，并在单色显示器和全彩化显示器之间转换，又可以提高像素密度。
本发明的至少一实施例提供一种显示器，包括上述任一项阵列基板，可以在单色显示器和全彩化显示器之间转换，并且可以提高像素密度。
以下通过几个实施例予以说明。
实施例一
本实施例提供了一种阵列基板，如图1a所示，包括基板10，在基板10上设置呈阵列排布的多个像素单元100，在每个像素单元100中有设置多个薄膜晶体管140、150和160。例如，多个薄膜晶体管140、150和160可以平行排列设置在基板10上，本实施例不限于此，还可以按照其他排列方式排列。 图1a为薄膜晶体管分布及数量的示例性示意图，图中在每个像素单元100中示出了三个薄膜晶体管140、150和160，然而，根据本发明的实施例不限于此，例如，薄膜晶体管的数量可以是两个、四个或者更多。
图1b示出了图1a中一个像素单元100沿AB方向的截面示意图。如图1b所示，每个像素单元100中包括多个发光单元110、120和130，多个发光单元110、120和130依次沿垂直于基板10所在平面的方向排列，且设置在多个薄膜晶体管140、150和160远离基板10的一侧，即多个发光单元110、120和130沿如图1b所示依次叠加排列。并且，每个发光单元与薄膜晶体管140、150和160中的之一连接，且不同的发光单元连接到不同的薄膜晶体管。需要说明的是，薄膜晶体管的数量与发光单元的数量一致，每个薄膜晶体管用于单独控制一个发光单元发光或者不发光，因此达到不使用彩色滤光片而实现全彩化的效果，并在单色显示器和全彩化显示器之间转换。
例如，如图1a和图1b所示，阵列基板还包括挡墙200，围绕每个像素单元100以限定用于形成发光单元110、120和130的区域，也就是说，相邻的像素单元100之间都用挡墙200隔开。需要说明的是，图1a示出了像素单元100的形状为矩形的示意图，本实施例不限于此，像素单元100的形状还可以是圆形或多边形。
例如，如图1b所示，像素单元100中的多个发光单元110、120和130的至少之一的图案的形状以及尺寸与挡墙200限定的区域的形状以及尺寸相同，即挡墙200与多个发光单元110、120和130的至少之一紧密接触以限定该发光单元的形状以及尺寸。例如，挡墙200可以围绕第二发光单元120和第三发光单元130以限定第二发光单元120和第三发光单元130的形状以及尺寸，本发明不限于此。需要说明的是，挡墙200可以图案化全部发光单元的形状和尺寸，或者图案化除与薄膜晶体管最接近的发光单元的其他全部发光单元的形状和尺寸。
例如，挡墙200可以作为掩模板，图案化形成至少一个发光单元。例如，挡墙200作为蒸镀掩模板蒸镀形成至少一个发光单元的至少一层。因此，采用挡墙200作为掩模板，省去了制作有机发光二极管需要的高精度金属掩模板和彩色滤光片，并且能够提高有机发光二极管的像素密度。
例如，挡墙200可以作为掩模板，图案化形成微型有机发光二极管的发光单元。例如，各发光单元的尺寸(平行于基板方向的最大尺寸)小于10微米。 例如，各发光单元的尺寸包括2微米-4微米。
例如，挡墙200可以作为掩模板，图案化形成一般有机发光二极管的发光单元。
在一般的封装过程中，需要抽真空保证盖板玻璃压合状态，但是在抽真空的过程中容易损坏像素。在本实施例中，如图1b所示，挡墙200的沿垂直于基板10所在平面的方向的高度可以高于多个发光单元110、120和130整体的高度，例如，超过高度为3微米-6微米。本实施例不限于此，挡墙200沿垂直于基板10所在平面的方向的高度也可以等于多个发光单元110、120和130整体的高度。挡墙200的设置高度超过或等于多个发光单元110、120和130整体的高度可以减少封装时抽真空对像素单元100的压力，降低像素损坏的几率。
例如，从靠近基板10到远离基板10的方向上，挡墙200的厚度逐渐减小。这里挡墙200的厚度是指挡墙200的横截面的宽度。如图1b所示，挡墙200沿AB方向的截面包括梯形，本实施例不限于此，还可以是三角形或者阶梯型。例如，在挡墙200围绕的像素单元区域中，多个发光单元110、120和130沿靠近基板10向远离基板10的方向上的尺寸不完全重合，例如，依次增大。例如，第三发光单元130的尺寸大于第二发光单元120的尺寸，第二发光单元120的尺寸大于第一发光单元110的尺寸。
例如，多个薄膜晶体管140、150和160中的至少之一形成在挡墙200和基板10之间，多个发光单元110、120和130中的至少一个通过设置在挡墙200中的通孔201和202与对应的薄膜晶体管连接。如图1b所示，挡墙200包括第一通孔201和第二通孔202。第一薄膜晶体管140通过第一通孔201与第二发光单元120电连接，第三薄膜晶体管160通过第二通孔202与第三发光单元130电连接。例如，可以采用激光对挡墙200打孔的方法形成第一通孔201和第二通孔202，本实施例不限于此，也可以采用刻蚀等方法形成通孔。
例如，挡墙200的材料可以是光刻胶或其它有机材料，本实施例不限于此。
图2为本发明一实施例提供的一个像素单元示意图，如图2所示，每个像素单元100包括在基板10上设置三个平行排列的薄膜晶体管140、150和160，在薄膜晶体管140、150和160远离基板10的一侧沿垂直于基板10所在平面的方向依次设置三个发光单元110、120和130，且每个发光单元与多个薄膜晶体管140、150和160中的之一连接，且不同的发光单元连接到不同的薄膜晶 体管。例如，第一薄膜晶体管140与第三发光单元130电连接，第二薄膜晶体管150与第一发光单元110电连接，第三薄膜晶体管160与第二发光单元120电连接。本实施例不限于此，还可以第一薄膜晶体管140与第二发光单元120电连接，第二薄膜晶体管150与第一发光单元110电连接，第三薄膜晶体管160与第三发光单元130电连接，以实现每个薄膜晶体管单独控制一个发光单元。需要说明的是图2中的每个薄膜晶体管与对应的发光单元单独连接的连接线是一种电连接关系的示范性示意图，实际是通过通孔蒸镀第一电极材料，使发光单元的第一电极与薄膜晶体管的漏极相连接。通过不同薄膜晶体管对不同发光单元的单独控制，既可以实现全彩化显示器或者单色显示器效果，又可以提高像素密度。
例如，多个发光单元110、120和130分别发射不同颜色的光。例如，第一发光单元110、第二发光单元120以及第三发光单元130可以分别是红色发光单元、绿色发光单元和蓝色发光单元，本实施例不限于此。例如，不同的发光单元衰减寿命不同，绿色发光单元一般具有比红色和蓝色发光单元更长的衰减寿命，可以根据实际应用场景，在每个像素单元100中分别控制薄膜晶体管140、150和160，使绿色发光单元120单独发光，其他颜色发光单元不发光，得到绿光单色显示器。
例如，在每个像素单元100中通过薄膜晶体管140、150和160分别控制发光单元110、120和130中的至少一个发光单元发光，可以得到不同颜色的有机发光二极管显示器。
例如，在沿同一方向相邻的三个像素单元100中，每个像素单元100中的薄膜晶体管140、150和160分别控制三个不同的发光单元110、120和130中的一个发光单元发光，例如，三个像素单元100中的薄膜晶体管140、150和160分别控制第一个像素单元中的第三发光单元130发光、第二个像素单元中的第一发光单元110发光以及第三个像素单元中的第二发光单元120发光，可以实现全彩化显示器，本实施例不限于此。
例如，在像素单元100中通过薄膜晶体管140、150和160控制发光单元110、120和130全部发光可以得到全彩化显示器，并且该全彩化显示器相比于一般的全彩化显示器具有更高的像素密度，即可以获得与物理像素大小相同的高分辨率的显示效果。
例如，每个发光单元包括第一电极、发光层和第二电极，如图2所示，第 一发光单元110包括第一电极111、发光层112以及第二电极113；第二发光单元120包括第一电极121、发光层122以及第二电极123；第三发光单元130包括第一电极131、发光层132以及第二电极133。例如，第一发光单元110的第一电极111、第二发光单元120的第一电极121以及第三发光单元130的第一电极131为阳极，第一发光单元110的第二电极113、第二发光单元120的第二电极123以及第三发光单元130的第二电极133为阴极，本实施例不限于此。需要说明的是，每个发光单元的阳极与对应的薄膜晶体管单独连接，对应的薄膜晶体管分别控制每个发光单元发光或者不发光。
例如，第一电极以及第二电极的材料为导电材料。具体地，除第一发光单元110的第一电极111外，其他的第一电极以及第二电极均需要采用透明导电材料，以便发光单元发出的光能够很好地出射。需要说明的是，第一发光单元110的第一电极111的材料既可以是透明导电材料，也可以是不透明导电材料。例如，第一电极以及第二电极的材料也可以包括金属氧化物材料或者金属材料。例如，金属氧化物材料包括氧化铟锡、掺铟氧化锌等，例如，厚度为300-500纳米，本实施例不限于此。例如，金属材料包括银、铝等，例如，厚度为10-20纳米，本实施例不限于此，金属材料能够达到透明的厚度即可。
图3为本发明一实施例提供的一个像素单元中的发光单元示意图。为了更清楚地说明，图3仅仅示出了发光单元的层结构。在图3所示的结构中，除了发光层和电极层之外，还包括设置在每个发光单元远离基板侧的薄膜封装层。例如，在第一发光单元110与第二发光单元120之间设置第一薄膜封装层310，在第二发光单元120与第三发光单元130之间设置第二薄膜封装层320，在第三发光单元130远离第二发光单元120的一侧设置第三薄膜封装层330，本实施例不限于此。薄膜封装层310、320和330可以分隔开每个发光单元，在各发光单元之间起到绝缘效果。需要说明的是，薄膜封装层310、320和330的材料为透明绝缘材料，以便发光单元发出的光能够很好地出射。
实施例二
本实施例提供了一种阵列基板的制造方法，包括在基板上形成阵列排布的多个像素单元，形成每个像素单元包括：在基板上形成多个薄膜晶体管；
在多个薄膜晶体管上形成多个发光单元，多个发光单元依次沿垂直于基板所在平面的方向排列，并且，每个发光单元与多个薄膜晶体管之一连接，且不同的发光单元连接到不同的薄膜晶体管。例如，基板可以是硅基板，本实施例 不限于此。采用该阵列基板的制造方法，既可以达到不使用彩色滤光片而实现全彩化的效果，并在单色显示器和全彩化显示器之间转换，又可以提高像素密度。
例如，本实施例提供的阵列基板的制造方法，还包括：在形成多个薄膜晶体管之后，形成挡墙以限定用于形成发光单元的区域，并且，以挡墙为蒸镀掩模板采用蒸镀方法形成多个发光单元中的至少之一的至少一层。
本实施例以挡墙作为蒸镀掩模板，图案化形成至少一个发光单元，省去了制作有机发光二极管需要的高精度金属掩模板和彩色滤光片，并且能够提高有机发光二极管的像素密度。另外，围绕每个像素单元设置挡墙可以减少封装时抽真空对像素单元的压力，降低像素损坏的几率。
例如，挡墙可以作为掩模板，图案化形成微型有机发光二极管的发光单元，也可以图案化形成一般有机发光二极管的发光单元。
例如，如图4所示，形成每个像素单元包括如下步骤。
S101：在基板上形成多个薄膜晶体管；
S102：形成挡墙以限定用于形成发光单元的区域；
S103：以挡墙为蒸镀掩模板，采用蒸镀方法形成多个发光单元。
在一个示例里，形成每个像素单元具体包括如下步骤：
步骤一，在基板上的一般子像素尺寸的区域内，形成三个平行排列的薄膜晶体管，由于可以在阵列基板中采用半导体工艺制备，所以精细化的薄膜晶体管比较容易制作。
步骤二，在三个平行排列的薄膜晶体管周围形成挡墙以限定用于形成发光单元的区域。
步骤三，在挡墙围绕限定的区域蒸镀第一发光单元，即以挡墙作为掩模板，图案化形成第一发光单元，第一发光单元的尺寸和形状与挡墙围绕限定的区域完全相同。
例如，从靠近基板到远离基板的方向上，挡墙的厚度逐渐减小。这里挡墙的厚度是指挡墙的横截面的宽度。例如，挡墙的截面包括梯形，本实施例不限于此，还可以是三角形或者阶梯型，使挡墙围绕限定的区域中，多个发光单元沿靠近基板向远离基板的方向上的尺寸不完全重合，例如，依次增大。
例如，挡墙的材料可以是光刻胶或其它有机材料，本实施例不限于此。
例如，蒸镀第一发光单元包括蒸镀第一发光单元的第一电极、发光层和第 二电极，本实施例不限于此，还可以包括其他功能层，即空穴注入层、空穴传输层、空穴阻挡层、电子注入层、电子传输层和电子阻挡层等。
例如，第一电极为阳极，第二电极为阴极，阳极与三个薄膜晶体管中位于中间的薄膜晶体管中的漏极电连接。
例如，第一电极以及第二电极的材料包括导电材料。例如，除第一发光单元最靠近基板一侧的电极外，其他的电极采用透明导电材料，以便发光单元发出的光能够很好地出射。需要说明的是，第一发光单元最靠近基板一侧的电极的材料既可以是透明导电材料，也可以是不透明导电材料。例如，第一电极以及第二电极的材料可以包括金属氧化物材料或者金属材料。例如，金属氧化物材料包括氧化铟锡、掺铟氧化锌等，例如，厚度为300-500纳米，本实施例不限于此。例如，金属材料包括银、铝等，例如，厚度为10-20纳米，本实施例不限于此，金属材料能够达到透明的厚度即可。
例如，多个薄膜晶体管中的至少之一形成在挡墙和基板之间，方法包括：
步骤四，在挡墙中形成通孔，将多个发光单元中的至少一个通过通孔与对应的薄膜晶体管连接。例如，采用激光打孔的方法对薄膜晶体管上方的挡墙打孔，即，对三个薄膜晶体管中位于两侧的任一个薄膜晶体管上方的挡墙打孔，蒸镀第二发光单元的第一电极，该第一电极可以通过制作出来的通孔与薄膜晶体管的漏极电连接。然后以挡墙作为掩模板，图案化形成第二发光单元的后续膜层。本实施例不限于此，还可以采用刻蚀的方法形成通孔。
步骤五，采用激光打孔的方法对位于两侧的另一个薄膜晶体管上方的挡墙打孔，蒸镀第三发光单元的第一电极，该第一电极可以通过制作出来的通孔与薄膜晶体管的漏极电连接。然后以挡墙作为掩模板，图案化形成第三发光单元的后续膜层。
例如，在每个发光单元远离基板的一侧形成薄膜封装层。薄膜封装层可以用于分隔每个发光单元，在各发光单元之间起到绝缘效果。需要说明的是，薄膜封装层的材料为透明绝缘材料，以便发光单元发出的光能够很好地出射。
需要说明的是，以上步骤是一个示例步骤，本实施例不限于此。
实施例三
本实施例提供了一种阵列基板的制造方法，本实施例中对最靠近薄膜晶体管的一个发光单元的制造方法不同于实施例二提供的制造方法。
例如，如图5所示，形成每个像素单元包括如下步骤。
S201：在基板上形成多个薄膜晶体管；
S202：最靠近薄膜晶体管的一个发光单元采用刻蚀方法形成；
S203：形成挡墙以限定用于形成发光单元的区域；
S204：以挡墙为蒸镀掩模板，采用蒸镀方法形成其他发光单元。
在一个示例里，形成每个像素单元具体包括如下步骤。
步骤一，在基板上的一般子像素尺寸的区域内，形成三个平行排列的薄膜晶体管，由于可以在阵列基板中采用半导体工艺制备，所以精细化的薄膜晶体管比较容易制作。
步骤二，最靠近薄膜晶体管的第一发光单元采用刻蚀方法形成，刻蚀形成第一发光单元包括第一发光单元的第一电极、发光层和第二电极，本实施例不限于此。其中的第一电极与三个薄膜晶体管中位于中间的薄膜晶体管中的漏极电连接。这里“采用刻蚀方法形成”是指形成发光单元的各个层的图案化是通过刻蚀工艺实施。例如，发光层的形成步骤包括：先沉积发光材料层，然后通过掩模对发光材料层进行刻蚀以形成发光层。
例如，由于采用刻蚀工艺形成第一发光单元远离基板方向的其他发光单元，会对第一发光单元造成影响，因此需要设置挡墙来蒸镀形成后续的发光单元，采用该挡墙作为掩模板图案化形成其他发光单元。需要说明的是，第一发光单元的形状和尺寸与后续形成的挡墙限定的发光单元区域的形状和尺寸并不要求完全相同，可以相对更小或者更大。当第一发光单元的尺寸大于后续形成的挡墙限定的发光单元区域的尺寸时，第一发光单元不与挡墙中形成的通孔在基板上的投影重合。
步骤三，在三个平行排列的薄膜晶体管周围形成挡墙以限定用于形成发光单元的区域。
后续形成其他发光单元的步骤与实施例二相同，这里不再赘述。
需要说明的是，以上步骤是一个示例步骤，本实施例不限于此。
实施例四
本实施例提供一种显示器，该显示器包括上述任一项阵列基板，可以在单色显示器和全彩化显示器之间转换，并且可以提高像素密度。
例如，该显示器包括有机发光二极管显示器和微型有机发光二极管显示器等，本实施例不限于此。
例如，该显示器可应用到头盔显示器、立体显示镜以及眼镜式显示器等。
有以下几点需要说明：
(1)除非另作定义，本发明实施例以及附图中，同一标号代表同一含义。
(2)本发明实施例附图中，只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年11月11日递交的中国专利申请第201610994873.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种阵列基板，包括：
    基板；
    呈阵列排布的多个像素单元，设置在所述基板上，
    其中，在每个所述像素单元中设置有多个薄膜晶体管，每个所述像素单元包括多个发光单元，所述多个发光单元依次沿垂直于所述基板所在平面的方向排列，且设置在所述薄膜晶体管远离所述基板的一侧，每个所述发光单元与所述多个薄膜晶体管之一连接，且不同的所述发光单元连接到不同的所述薄膜晶体管。
  2. 根据权利要求1所述的阵列基板，还包括：
    挡墙，围绕每个所述像素单元以限定用于形成所述发光单元的区域。
  3. 根据权利要求2所述的阵列基板，其中，从靠近所述基板到远离所述基板的方向上，所述挡墙的厚度逐渐减小。
  4. 根据权利要求2或3所述的阵列基板，其中，所述多个薄膜晶体管中的至少之一形成在所述挡墙和所述基板之间，所述多个发光单元中的至少一个通过设置在所述挡墙中的通孔与对应的所述薄膜晶体管连接。
  5. 根据权利要求1-4任一项所述的阵列基板，还包括：
    薄膜封装层，设置在每个所述发光单元远离所述基板的一侧。
  6. 根据权利要求1-5任一项所述的阵列基板，其中，每个所述发光单元包括第一电极、发光层和第二电极，所述第一电极与对应的所述薄膜晶体管连接。
  7. 根据权利要求1-6任一项所述的阵列基板，其中，所述多个发光单元分别发射不同颜色的光。
  8. 根据权利要求7所述的阵列基板，其中，每个所述像素单元包括三个所述薄膜晶体管和三个所述发光单元，所述三个发光单元分别发射红光、绿光和蓝光。
  9. 根据权利要求1-8任一项所述的阵列基板，其中，所述多个发光单元的每个沿平行于所述基板所在平面的方向的最大尺寸小于10微米。
  10. 一种阵列基板的制造方法，包括：
    在基板上形成阵列排布的多个像素单元，
    形成每个所述像素单元包括：
    在所述基板上形成多个薄膜晶体管；
    在所述多个薄膜晶体管上形成多个发光单元，所述多个发光单元依次沿垂直于所述基板所在平面的方向排列，
    其中，每个所述发光单元与所述多个薄膜晶体管之一连接，且不同的所述发光单元连接到不同的所述薄膜晶体管。
  11. 根据权利要求10所述的阵列基板的制造方法，还包括：
    在形成所述多个薄膜晶体管之后，形成挡墙以限定用于形成所述发光单元的区域，
    其中，在所述多个薄膜晶体管上形成所述多个发光单元包括：
    以所述挡墙为蒸镀掩模板，采用蒸镀方法形成至少一个所述发光单元中的至少一层。
  12. 根据权利要求10或11所述的阵列基板的制造方法，其中，最靠近所述薄膜晶体管的一个所述发光单元采用刻蚀方法形成。
  13. 根据权利要求11所述的阵列基板的制造方法，其中，所述多个薄膜晶体管中的至少之一形成在所述挡墙和所述基板之间，所述方法还包括：
    在所述挡墙中形成通孔，将所述多个发光单元中的至少一个通过所述通孔与对应的所述薄膜晶体管连接。
  14. 根据权利要求10-13任一项所述的阵列基板的制造方法，还包括：
    在每个所述发光单元远离所述基板的一侧形成薄膜封装层。
  15. 一种显示器，包括如权利要求1-9任一项所述的阵列基板。
PCT/CN2017/088078 2016-11-11 2017-06-13 阵列基板及其制造方法、显示器 WO2018086347A1 (zh)

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