WO2023273519A1 - 显示面板、其制备方法和终端 - Google Patents

显示面板、其制备方法和终端 Download PDF

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Publication number
WO2023273519A1
WO2023273519A1 PCT/CN2022/087163 CN2022087163W WO2023273519A1 WO 2023273519 A1 WO2023273519 A1 WO 2023273519A1 CN 2022087163 W CN2022087163 W CN 2022087163W WO 2023273519 A1 WO2023273519 A1 WO 2023273519A1
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WIPO (PCT)
Prior art keywords
layer
pixel definition
anode
organic light
substrate
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PCT/CN2022/087163
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English (en)
French (fr)
Inventor
安亚斌
贺海明
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荣耀终端有限公司
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Priority to US18/272,289 priority Critical patent/US20240090271A1/en
Publication of WO2023273519A1 publication Critical patent/WO2023273519A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/17—Carrier injection layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a terminal.
  • the hole injection layer, the hole transport layer, etc. are common layers (Common Layer), which cover all the sub-pixel regions and the interval regions between the sub-pixels.
  • Common Layer Common Layer
  • the OELD device since the common layers of each sub-pixel are connected, carriers will conduct laterally in these common layers, causing the common layer to generate lateral leakage, resulting in that when a sub-pixel is lit, its adjacent The sub-pixel is susceptible to the influence of the sub-pixel, resulting in cross-color phenomenon.
  • the first aspect of the present application provides a display panel, which includes:
  • Adjacent first sub-pixels and second sub-pixels are arranged on the substrate, the first sub-pixel includes a first organic light emitting diode, the second sub-pixel includes a second organic light emitting diode, the first organic light emitting diode includes a The first anode on the second organic light emitting diode includes a second anode on the substrate;
  • a pixel definition layer located on the substrate, on the first anode and on the second anode, and the pixel definition layer has a pixel definition hole exposing the first anode and the second anode;
  • the common layer includes a first portion located on the first anode, a second portion located on the second anode, and a blocking portion located on the pixel definition layer and formed due to the pixel definition layer;
  • the first part constitutes a part of the first organic light emitting diode
  • the second part constitutes a part of the second organic light emitting diode
  • the first part and the second part are insulated and separated by the blocking part.
  • the pixel definition layer includes a top surface far away from the substrate and a side surface connected to the top surface; wherein, the side surface includes a recess to form a blocking portion in the common layer. That is to say, the pixel definition layer has a depression that breaks the continuity of the common layer.
  • the recess is obtained by forming an undercut in the pixel definition layer.
  • the pixel definition layer includes a first pixel definition layer and a second pixel definition layer that are sequentially stacked along a direction away from the substrate; wherein, the depression is formed in the first pixel definition layer, and the top surface is formed In the second pixel definition layer.
  • the top surface includes an arc connected to the side surface, and the included angle between the arc and the surface of the substrate ranges from 5 degrees to 30 degrees.
  • the included angle ⁇ ranges from 5 degrees to 30 degrees, on the one hand, the cathode can be slowly overlapped without breaking the line, and on the other hand, the organic light-emitting diode can obtain a larger divergence angle, preventing color shift and The phenomenon of low grayscale color cast occurs.
  • the display panel includes a hole injection layer, a hole transport layer, an organic light-emitting layer, a hole blocking layer, and an electron transport layer that are sequentially stacked along a direction away from the substrate; wherein, the common layer includes a hole One or more layers of hole injection layer, hole transport layer, hole blocking layer and electron transport layer.
  • the hole injection layer is in direct contact with the pixel definition layer, the first anode, and the second anode; defining a gap between the surface of the first pixel definition layer away from the substrate and the surface of the first anode away from the substrate
  • the height is h; define the sum of the height of the hole injection layer and the hole transport layer as h L ; define the sum of the height of the hole injection layer, the hole transport layer, the organic light-emitting layer, the hole blocking layer and the electron transport layer is h H ; where, h L ⁇ h ⁇ h H .
  • the blocking common layer includes at least a hole injection layer and a hole transport layer.
  • the organic light-emitting layer includes a first organic light-emitting layer, an electron-hole pair secondary generation layer, and a second organic light-emitting layer that are sequentially stacked along a direction away from the substrate; The hole pairs the secondary growth layer.
  • the display panel further includes a cathode layer located on the side of the common layer away from the substrate; wherein, the cathode layer is a continuous film layer and will not be blocked by the pixel definition layer.
  • the second aspect of the present application provides a display panel, which includes:
  • a plurality of organic light emitting diodes are arranged at intervals on the substrate, and each organic light emitting diode includes an anode;
  • a pixel definition layer located on the substrate and on the anode, and the pixel definition layer has a plurality of pixel definition holes, and each pixel definition hole exposes an anode;
  • a common layer including a part on the anode and a part on the pixel definition layer;
  • the pixel definition layer includes a first pixel definition layer and a second pixel definition layer sequentially stacked along a direction away from the substrate;
  • a side surface of the first pixel definition layer includes a recess recessed relative to the second pixel definition layer so that a portion of the common layer on the anode is blocked from a portion of the common layer on the pixel definition layer.
  • a second aspect of the present application provides a terminal, which includes the above-mentioned display panel.
  • the terminal since the terminal includes the above-mentioned display panel, it also has the advantage of avoiding cross-color phenomenon.
  • the third aspect of the present application provides a method for preparing a display panel, which includes:
  • a plurality of anodes arranged in an array are formed on a substrate, and the plurality of anodes include adjacent first anodes and second anodes;
  • a pixel definition layer on the substrate and on the plurality of anodes, the pixel definition layer having a pixel definition hole exposing the first anode and the second anode;
  • a common layer is formed on the pixel definition layer and on the plurality of anodes, the common layer includes a first part located on the first anode, a second part located on the second anode, and a layer located on the pixel definition layer and formed due to the pixel definition layer
  • the blocking part, the first part and the second part are insulated and separated by the blocking part;
  • the first part is used to form a part of a first organic light emitting diode
  • the second part is used to form a part of a second organic light emitting diode
  • the first organic light emitting diode includes a first anode
  • the second organic light emitting diode includes a second anode
  • the pixel definition layer includes a top surface away from the substrate and a side surface connected to the top surface; wherein, forming the pixel definition layer includes forming a recess on the side surface.
  • forming the pixel definition layer includes sequentially forming a stacked first pixel definition layer and a second pixel definition layer along a direction away from the substrate; wherein, the concave portion is formed in the first pixel definition layer, and the top A surface is formed in the second pixel definition layer.
  • the preparation method includes sequentially forming a stacked hole injection layer, a hole transport layer, an organic light-emitting layer, a hole blocking layer, and an electron transport layer along a direction away from the substrate; wherein, forming a common layer Including forming one or more layers of hole injection layer, hole transport layer, hole blocking layer and electron transport layer.
  • forming the organic light-emitting layer includes sequentially forming a first organic light-emitting layer, an electron-hole pair secondary generation layer, and a second organic light-emitting layer along a direction away from the substrate; wherein, forming a common layer includes forming an electron-hole pair secondary generation layer; Hole pair secondary generation layer.
  • Fig. 1 is a schematic structural diagram of a terminal provided in some embodiments of the present application.
  • FIG. 2 is a schematic structural diagram of the display panel in FIG. 1 .
  • Fig. 3 is a schematic structural diagram of an OLED provided in some embodiments of the present application.
  • Fig. 4 is a schematic diagram of another structure of an OLED provided in some embodiments of the present application.
  • FIG. 5 is a schematic cross-sectional view of a display panel provided in some embodiments of the present application.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel provided in some embodiments of the present application.
  • FIG. 7 is a schematic cross-sectional view of forming a planarization layer in the method of FIG. 6 .
  • FIG. 8 is a schematic cross-sectional view of forming an anode on the planarization layer shown in FIG. 7 .
  • FIG. 9 is a schematic cross-sectional view of forming a first material layer, a hard mask layer and a patterned photoresist layer on the structure shown in FIG. 8 .
  • FIG. 10 is a schematic cross-sectional view of forming a patterned hard mask layer by using the patterned photoresist layer shown in FIG. 9 as a mask.
  • FIG. 11 is a schematic cross-sectional view of forming a first pixel definition layer by using the patterned hard mask layer shown in FIG. 10 as a mask.
  • FIG. 12 is a schematic cross-sectional view after removing the patterned hard mask layer shown in FIG. 11 .
  • FIG. 13 is a schematic cross-sectional view of forming a second pixel definition layer on the first pixel definition layer shown in FIG. 12 .
  • the first anode 2411 is the first anode 2411
  • the first organic light-emitting layer 2441 is the first organic light-emitting layer 2441
  • the first material layer 52 is the first material layer 52
  • An embodiment of the present application provides a terminal, which can be a product with a display interface such as a mobile phone, a monitor, a tablet computer, and a vehicle-mounted computer, as well as smart display wearable products such as a smart watch and a smart bracelet.
  • a terminal can be a product with a display interface such as a mobile phone, a monitor, a tablet computer, and a vehicle-mounted computer, as well as smart display wearable products such as a smart watch and a smart bracelet.
  • a mobile phone as an example for illustration.
  • the terminal 100 includes a cover 10 , a display panel 20 and a supporting structure 30 .
  • the cover plate 10 defines a display surface of the terminal 100 .
  • the display panel 20 is used for displaying images.
  • the supporting structure 30 is also referred to as a casing or a rear cover or a battery cover.
  • the cover plate 10 and the supporting structure 30 cooperate to form an accommodating space (not shown in the figure), and the display panel 20 is located in the accommodating space between the cover plate 10 and the supporting structure 30 .
  • other functional components/electronic components such as a main board and a battery, can also be installed in the accommodation space.
  • the structure of the display panel 20 will be described below.
  • the display panel 20 includes a plurality of pixels (Pixels) 22 arranged in an array.
  • Each pixel 22 includes at least one sub-pixel 222 for emitting visible light.
  • the first pixel 22 includes three sub-pixels 222 , which are a display sub-pixel R emitting red light, a display sub-pixel G emitting green light, and a display sub-pixel B emitting blue light.
  • the visible lights emitted by the three sub-pixels 222 in the pixel 22 are cyan light, magenta light and yellow light respectively.
  • the pixel 22 includes four sub-pixels 222 , and the visible lights emitted by the four sub-pixels 222 are red light, green light, blue light, and white light respectively.
  • the display panel 20 is a monochromatic display panel, and the sub-pixels 222 included in it all emit visible light of the same color.
  • each sub-pixel in the display panel 20 is a sub-pixel that emits green light. That is, there is no limitation on the number of sub-pixels 222 in the pixel 22 and the combination of light-emitting colors.
  • the display panel 20 further includes a plurality of organic light emitting diodes (Organic Light Emitting Diode, OLED) 24 .
  • OLED Organic Light Emitting Diode
  • Each OLED 24 corresponds to a sub-pixel 222, and each OLED 24 is located in the sub-pixel 222 corresponding to the OLED 24, so that the display panel 20 can realize self-illumination without setting a backlight source.
  • the display panel 20 is an active matrix organic light emitting diode (AMOLED) display panel, which has the advantages of bright colors, high contrast, and fast response.
  • the display panel 20 is a flexible OLED display panel, which is also bendable and deformable, and has great potential in bendable mobile phones and special-shaped displays such as curved surface displays.
  • the arrangement of the OLED 24 in the display panel 20 is described below with an example.
  • each OLED 24 includes an organic light emitting layer 244 and an anode (Anode) 241 and a cathode (Cathode) 247 located on opposite sides of the organic light emitting layer 244.
  • the anode 241 of each OLED 24 is mutually independent, and the cathode 247 of a plurality of OLED 24 is a whole layer.
  • the material of the anode 241 may be a metal material, such as aluminum (Al), magnesium (Mg), silver (Ag), magnesium-silver alloy (Mg/Ag) and the like.
  • the proportion of Mg in the magnesium-silver alloy (Mg/Ag) is, for example, between 8% and 12%.
  • the material of the cathode 247 can be transparent or translucent conductive material, for example, indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO).
  • the cathode 247 is transparent, and the light transmittance of the anode 241 is very small, so the light emitted by the OLED 24 is emitted from the side where the cathode 247 is located.
  • the OLED 24 is a top emission type light emitting device.
  • the material of the anode 241 may be the above-mentioned transparent conductive material; the material of the cathode 247 may be the above-mentioned metal material.
  • the anode 241 transmits light, and the light transmittance of the cathode 247 is very small, so the light emitted by the OLED 24 exits from the side where the anode 241 is located. At this time, the OLED 24 is a bottom emission type light emitting device.
  • the materials of the organic light-emitting layer 244 of the OLEDs 24 in different sub-pixels 222 are different, so that the OLEDs 24 in different sub-pixels 222 emit visible light with different colors, such as red light, green light or blue light.
  • the materials of the organic light-emitting layer 244 of the OLEDs 24 in different sub-pixels 222 are different, so that the OLEDs 24 in different sub-pixels 222 emit visible light with different colors, such as red light, green light or blue light.
  • the organic light-emitting layer 244 of the sub-pixel 222 that emits red light includes a red base layer (R prime, R') and a red light-emitting layer (R-emission layer, R-EML); the sub-pixel 222 that emits green light
  • the organic light-emitting layer 244 of the blue light-emitting sub-pixel 222 includes a green base layer (G prime, G') and a green light emission layer (G-emission layer, G-EML);
  • the organic light-emitting layer 244 of the sub-pixel 222 that emits blue light includes a blue base layer (B prime, B') and blue light emission layer (B-emission layer, B-EML).
  • Each anode 241 corresponds to a sub-pixel 222 .
  • the above-mentioned OLED 24 also includes a hole injection layer (Hole Inject Layer, HIL) 242, hole transport layer (Hole Transfer Layer, HTL) 243, hole blocking layer (Hole Block Layer, HBL) 245, electron transfer layer (Electron Transfer Layer, ETL) 246.
  • HIL hole injection layer
  • HTL hole transport layer
  • HBL hole blocking layer
  • ETL electron transfer layer
  • the hole injection layer 242 and the hole transport layer 243 are located between the organic light emitting layer 244 and the anode 241 .
  • the hole blocking layer 245 and the electron transport layer 246 are located between the organic light emitting layer 244 and the cathode 247 , and are sequentially close to the cathode 247 . That is, in FIG. 3 , the lamination sequence of each film layer in OLED 24 is anode 241 , hole injection layer 242 , hole transport layer 243 , organic light emitting layer 244 , hole blocking layer 245 , electron transport layer 246 and cathode 247 .
  • the above-mentioned OLED 24 also includes a flat layer (Capping Layer, CPL) 248 on the cathode 247 and a lithium fluoride (LiF) layer 249 on the flat layer 248.
  • the flat layer 248 can improve the light extraction efficiency of the OLED 24 microcavity, and the lithium fluoride layer 249 can isolate ions to improve the light extraction efficiency.
  • each OLED 24 in Example 2 includes a first organic light-emitting layer 2441, a second organic light-emitting layer 2442, and electron holes between the first organic light-emitting layer 2441 and the second organic light-emitting layer 2442.
  • the electron-hole pair secondary generation layer 2443 is also called charge generation layer (Charge Generation Layer, CGL).
  • the electron-hole pair secondary generation layer 2443 includes an electron secondary generation layer (N-CGL) and a hole secondary generation layer (P-CGL).
  • N-CGL is generally an organic sensitizer, which may include metal ytterbium (Yb). When ytterbium is used in the electron sensitizer of organic matter, it can promote the release of electrons from the organic matter.
  • the P-type material dopant in P-CGL can be 2,2'-(1,3,4,5,6,8,9,10-octafluoro-2,7- Diylidene pyrene) bismalononitrile, the chemical formula is as follows:
  • the lamination sequence of each film layer in OLED 24 is anode 241, hole injection layer 242, hole transport layer 243, first organic light-emitting layer 2441, electron-hole pair secondary generation layer 2443, second Two organic light emitting layers 2442 , a hole blocking layer 245 , an electron transporting layer 246 and a cathode 247 . Due to the connection of more organic light-emitting layers in series in the OLED 24 of this structure, the light extraction efficiency is improved, and the brightness is also higher at the same current density.
  • the hole injection layer 242, the hole transport layer 243, the hole blocking layer 245, the electron transport layer 246, and the cathode 247 are all common layers, which are simultaneously deposited/covered on each sublayer.
  • a functional layer above the pixels 222 eg, R/G/B.
  • the hole injection layer 242, the hole transport layer 243, the hole blocking layer 245, the electron transport layer 246, the cathode 247, and the electron-hole pair secondary generation layer 2443 are all common layers. , which is a functional layer deposited/covered on each sub-pixel 222 (eg, R/G/B) at the same time. If there is lateral leakage between these common layers, it will lead to cross-color phenomenon.
  • the following specifically introduces how to solve the problem of color crossover caused by the lateral leakage of the common layer in the display panel 20 .
  • the display panel 20 includes a thin film transistor (Thin Film Transistor, TFT) backplane 40
  • the TFT backplane 40 includes a substrate 42, a driving circuit layer 44 disposed on the substrate 42, disposed on the driving circuit layer 44 away from the substrate
  • One side of the 42 is a planarization layer (Planarization, PLN) 46 and a pixel definition layer (Pixel Define Layer, PDL) 48 .
  • the substrate 42 is used as a carrier matrix for carrying the driving circuit layer 44, the pixel definition layer 48 and other layers above it, and its material can be polyethylene terephthalate (PET), polyimide (Polyimide, PI), etc. ) and other flexible materials.
  • the driving circuit layer 44 includes, for example, pixel driving circuits (not shown) arranged in an array.
  • Each pixel driving circuit includes a plurality of driving TFTs, and the anode 241 of each OLED 24 is used to electrically connect with one driving TFT to emit light under the control of the driving TFT.
  • the planarization layer 46 covers a plurality of driving TFTs, so as to flatten, insulate and protect the fluctuations of the driving TFTs on the substrate 42 .
  • the pixel defining layer 48 has a plurality of pixel defining holes 486 (two are exemplarily drawn in FIG. 5 ) exposing the anode 241 of the OLED 24, and each pixel defining hole 486 exposes the anode 241 of one OLED 24.
  • the pixel definition layer 48 is located between two adjacent anodes 241 on the planarization layer 46 and at least partially covers the anodes 241 .
  • Each pixel defining hole 486 corresponds to one sub-pixel 222 .
  • Each OLED 24 corresponds to a pixel defining hole 486 (partial film layers of the OLED 24 are omitted in Fig. 5, only the anode 241 of the OLED 24 is drawn).
  • the anode 241 of the OLED 24 can pass through the through hole (not shown) opened in the planarization layer 46 to realize electrical connection with the driving TFT.
  • the planarization layer 46 can provide a flat reflective surface for the anode 241 .
  • two adjacent sub-pixels 222 located in a pixel 22 are defined as a first sub-pixel 2221 and a second sub-pixel 2222 respectively.
  • the OLED 24 in the first sub-pixel 2221 as the first OLED
  • the OLED 24 in the second sub-pixel 2222 as the second OLED.
  • the anode 241 of the first OLED as the first anode 2411
  • the anode 241 of the second OLED as the second anode 2412 .
  • the first anode 2411 and the second anode 2412 are disposed on the planarization layer 46 at intervals.
  • the blocked common layer 60 is blocked by the pixel definition layer 48 through the structural design of the pixel definition layer 48 .
  • the blocked common layer 60 is at least divided into a first portion 61 located on the first anode 2411, a second portion 62 located on the second anode 2412, and a portion located on the pixel definition layer 48 and formed due to the pixel definition layer 48
  • the blocking part 63 constitutes a part of the first OLED
  • the second part 62 constitutes a part of the second OLED
  • the first part 61 and the second part 62 are insulated and separated by the blocking part 63 .
  • the pixel definition layer 48 includes a top surface 4842 away from the substrate 42 and a side surface 4822 connected to the top surface 4842 .
  • the side surface 4822 includes a concave portion 4824 for forming the blocking portion 63 in the common layer 60 .
  • the recessed portion 4824 is recessed along a direction in which the anode 241 of one OLED 24 points to the anode 241 of the adjacent OLED 24. That is to say, the pixel definition layer 48 has a concave portion 4824 that breaks the continuity of the common layer 60 .
  • the concave portion 4824 is obtained by forming an undercut in the pixel definition layer 48 .
  • pixel definition layer 48 may be composed of multiple layers of materials.
  • the pixel definition layer 48 includes a first pixel definition layer 482 and a second pixel definition layer 484 which are sequentially stacked along a direction away from the substrate 42 .
  • the depressed portion 4824 is formed in the first pixel definition layer 482 .
  • the top surface 4842 of the pixel definition layer 48 is formed in the second pixel definition layer 484 , and the top surface 4842 of the pixel definition layer 48 is the surface of the second pixel definition layer 484 away from the substrate 42 .
  • the angle ⁇ between the arc surface and the upper surface of the substrate 42 ranges from 5 degrees to 30 degrees. In other words, the angle ⁇ between the curved surface and the upper surface of the anode 241 of the OLED 24 away from the substrate 42 ranges from 5 degrees to 30 degrees. In some embodiments, the angle ⁇ between the arc surface and the upper surface of the anode 241 away from the substrate 42 is less than or equal to 15 degrees.
  • the cathode 247 of each OLED 24 will be disconnected in the lapping process; and if the angle ⁇ is too large, it is not conducive to The divergence of the light exiting the OLED 24.
  • the included angle ⁇ ranges from 5 degrees to 30 degrees, on the one hand, the cathode 247 can be slowly overlapped without disconnection, and on the other hand, the OLED 24 can obtain a larger divergence angle to prevent color shift and The phenomenon of low grayscale color cast occurs.
  • support columns (not shown) on the second pixel definition layer 484 may also be formed by one-time patterning through a half-mask process.
  • the support column is used as the support structure 30, which can effectively avoid the evaporation mask used to form the functional layers of the OLED 24 light emitting device from contacting the display panel 20 in the process of forming the OLED 24 by evaporation, so as to improve the display panel 20. product yield.
  • OLED 24 has the structure shown in Figure 3.
  • the common layer includes a hole injection layer 242 , a hole transport layer 243 , a hole blocking layer 245 , an electron transport layer 246 and a cathode 247 .
  • the hole injection layer 242 , the hole transport layer 243 , the organic light emitting layer 244 , the hole blocking layer 245 , and the electron transport layer 246 are sequentially formed on the anode 241 .
  • at least one of the hole injection layer 242 , the hole transport layer 243 , the hole blocking layer 245 and the electron transport layer 246 is blocked, but the cathode 247 is not blocked.
  • the hole injection layer 242 is in direct contact with the pixel definition layer 48 and the anode 241 of the OLED 24 .
  • the anodes 241 of two adjacent OLEDs 24 are basically located in the same plane away from the upper surface of the substrate 42 .
  • the height between the surface of the first pixel definition layer 482 away from the substrate 42 and the surface of the anode 241 of the OLED 24 away from the substrate 42 is defined as h.
  • h L the height sum of hole injection layer 242 and hole transport layer 243 as h L ; define hole injection layer 242, hole transport layer 243, organic light emitting layer 244, hole blocking
  • the sum of the heights of layer 245 and electron transport layer 246 is h H .
  • h L the height from the top of the first pixel definition layer 482 to the upper surface of the anode 241 of the OLED 24 is h, at least the height of the common layers (hole injection layer 242 and hole transport layer 243) below the organic light emitting layer 244 h L is greater than or equal to h, so that at least the hole injection layer 242 and the hole transport layer 243 are blocked.
  • the blocked common layer 60 at least includes a hole injection layer 242 and a hole transport layer 243 .
  • the height of the film layer between the cathode 247 and the anode 241 is h H , where h ⁇ h H , so that the cathode 247 layer formed by the cathode 247 of each OLED 24 is a continuous film layer and will not be blocked by the pixel definition layer 48. broken.
  • OLED 24 has the structure shown in FIG. 4 .
  • the common layers include a hole injection layer 242 , a hole transport layer 243 , a hole blocking layer 245 , an electron transport layer 246 , a cathode 247 and an electron-hole pair secondary generation layer 2443 .
  • the hole injection layer 242 When it is arranged in the pixel defining hole 486, the hole injection layer 242, the hole transport layer 243, the first organic light-emitting layer 2441, the electron-hole pair secondary generation layer 2443, the second organic light-emitting layer 2442, the hole blocking A layer 245 and an electron transport layer 246 are sequentially formed on the anode 241 .
  • at least one layer in the hole injection layer 242, the hole transport layer 243, the hole blocking layer 245, the electron transport layer 246, and the electron-hole pair secondary generation layer 2443 is blocked, but the cathode 247 is not blocked. broken.
  • the hole injection layer 242 is in direct contact with the pixel definition layer 48 and the anode 241 of the OLED 24 .
  • the anodes 241 of two adjacent OLEDs 24 are basically located in the same plane away from the upper surface of the substrate 42 .
  • h the height between the surface away from the substrate 42 of the first pixel definition layer 482 and the surface away from the substrate 42 of the anode 241 of the OLED 24 as h; define the sum of the heights of the hole injection layer 242 and the hole transport layer 243 as h L ; define hole injection layer 242, hole transport layer 243, organic light-emitting layer 244 (comprising first organic light-emitting layer 2441, electron-hole pair secondary generation layer 2443 and second organic light-emitting layer 2442), hole blocking layer
  • the sum of the heights of the electron transport layer 245 and the electron transport layer 246 is h H ; wherein, h L ⁇ h ⁇ h H .
  • the height from the top of the first pixel definition layer 482 to the upper surface of the anode 241 of the OLED 24 is h
  • at least the height of the common layers (hole injection layer 242 and hole transport layer 243) below the organic light emitting layer 244 h L is greater than or equal to h, so that at least the hole injection layer 242 and the hole transport layer 243 are blocked.
  • the blocked common layer 60 at least includes a hole injection layer 242 and a hole transport layer 243 .
  • the height of the film layer between the cathode 247 and the anode 241 is h H , where h ⁇ h H , so that the cathode 247 layer formed by the cathode 247 of each OLED 24 is a continuous film layer and will not be blocked by the pixel definition layer 48. broken.
  • the height h from the top of the first pixel definition layer 482 to the upper surface of the anode 241 of the OLED 24 ranges from 0.3 ⁇ m to 1 ⁇ m.
  • the planarization layer 46 may be an organic material, for example, it may be a PI-based organic material.
  • the material of the first pixel definition layer 482 and the second pixel definition layer 484 can be an organic material or an inorganic material, for example, it can be organosiloxane, silicon oxide (SiOx), silicon nitride (SiNx), metal oxide Wait.
  • the number of pixel definition layers 48 is not limited, and it may also be more than two layers.
  • a method for preparing the above display panel is also provided. According to different needs, the order of steps in the preparation method can be changed, and some steps can be omitted or combined. As shown in Figure 6, the preparation method includes the following steps.
  • Step S11 forming a plurality of anodes on a substrate.
  • Step S12 forming a pixel definition layer on the substrate and the anode.
  • Step S13 forming a blocked common layer on the pixel definition layer and the anode.
  • Step S11 forming a plurality of anodes on a substrate.
  • the anode before forming the anode, it further includes sequentially forming a driving circuit layer and a planarization layer on the substrate.
  • the planarization layer 46 is located on the surface of the driving circuit layer 44 away from the substrate 42 .
  • the driving circuit layer 44 includes, for example, pixel driving circuits arranged in an array. Each pixel driving circuit includes a plurality of driving TFTs.
  • a planarization layer 46 covers a plurality of driving TFTs.
  • the planarization layer 46 is an organic material, for example, a PI-based organic material can be used to form the planarization layer 46 .
  • the anode 241 formed in step S11 is located on the surface of the planarization layer 46 away from the substrate 42 . Specifically, there are multiple anodes 241 formed in step S11 , and the multiple anodes 241 are spaced apart and arranged in an array on the planarization layer 46 (one is illustrated in FIG. 8 ).
  • the planarization layer 46 has a through hole (not shown in the figure), and each anode 241 is electrically connected to a driving TFT through a through hole in the planarization layer 46 .
  • the anode 241 may be formed by In Molding Label (IML).
  • Step S12 forming a pixel definition layer on the substrate and the anode. Step S12 will be described below with reference to FIGS. 9 to 13 .
  • the first material layer 52 may be organosiloxane, which is used for subsequent formation of the first pixel definition layer 482 .
  • the hard mask layer 54 is, for example, ITO.
  • the hard mask layer 54 can also be made of other materials, such as silicon nitride, silicon oxide, aluminum oxide, and the like.
  • the hard mask layer 54 is etched to obtain a patterned hard mask layer 58, and the patterned hard mask layer 58 is exposed part of the first material layer 52.
  • the step of etching the hard mask layer 54 may be wet etching of ITO.
  • the first material layer 52 is processed by using the patterned hard mask layer 58 as a mask.
  • the first material layer 52 is formed with a pixel defining hole 486 exposing the anode 241 , and at the pixel defining hole 486 , an undercut is formed in the first material layer 52 .
  • the first material layer 52 can be ashed with CL 2 /O 2 plasma, and the etching parameters can be adjusted to form the required undercut in the first material layer 52 to obtain the first pixel definition layer 482 .
  • the patterned hard mask layer 58 is removed.
  • the undercut forms the recessed portion 4824 of the first pixel definition layer 482 .
  • a second pixel definition layer 484 is formed on the first pixel definition layer 482 .
  • the pixel defining hole 486 extends through the second pixel defining layer 484 including a top surface 4842 connected to the side surface 4822 of the first pixel defining layer 482 .
  • Top surface 4842 includes an arc.
  • the angle ⁇ (marked in FIG. 5 ) between the arc surface and the upper surface of the anode 241 away from the substrate 42 ranges from 5 degrees to 30 degrees. In some embodiments, the angle ⁇ between the arc surface and the upper surface of the anode 241 away from the substrate 42 is less than or equal to 15 degrees.
  • the formation of the second pixel definition layer 484 can be formed using organosiloxane, and this step also includes ashing the anode 241 with oxidation plasma to remove the photoresist at the undercut position (also called the chamfer position).
  • the first pixel definition layer 482 and the second pixel definition layer 484 constitute the pixel definition layer 48 .
  • Each pixel defines hole 486 exposing one anode 241 .
  • Step S13 forming a blocked common layer on the pixel definition layer and the anode.
  • step S13 includes sequentially forming a hole injection layer, a hole transport layer, an organic light emitting layer, a hole blocking layer, an electron transport layer, and a cathode layer on the pixel definition layer and the plurality of anodes.
  • the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer and the cathode layer are all common layers, which are functional layers that are simultaneously deposited/covered on each sub-pixel (such as R/G/B) .
  • the organic light emitting layers also include an electron-hole pair secondary generation layer located between two adjacent organic light emitting layers.
  • the common layer includes an electron-hole pair secondary generation layer.
  • the blocked common layer includes one or more layers of hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron-hole pair secondary generation layer, but does not include the cathode layer. That is, the cathode layer is a continuous film layer.
  • the blocked common layer includes a portion on each anode 241 forming part of the OLED 24 and a blocking portion on the pixel definition layer 48. The portion of the blocked common layer on the anode 241 and the blocking portion on the pixel definition layer 48 are blocked by the pixel definition layer 48 to be insulated.
  • the adjacent anodes of the blocked common layer The parts on 241 are also insulated and arranged at intervals.
  • two adjacent sub-pixels are defined as a first sub-pixel and a second sub-pixel respectively.
  • the OLED included in the first sub-pixel as the first OLED
  • the OLED included in the second sub-pixel as the second OLED.
  • the anode of the first OLED is defined as the first anode
  • the anode of the second OLED is defined as the second anode.
  • the pixel definition layer 48 exposes the first anode and the second anode.
  • the blocked common layer includes a first portion on the first anode for forming part of a first OLED, a second portion on the second anode for forming part of a second OLED, and on the pixel definition layer 48 and due to The pixel definition layer 48 forms a blocking portion.
  • the first part and the second part are insulated and separated by the blocking part. In this way, at least part of the common layer of the OLEDs in two adjacent sub-pixels is blocked, which reduces the lateral leakage of the common layer between adjacent sub-pixels, improves the problem of crosstalk in the light emission of the display panel, and improves the display performance. quality.

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Abstract

本申请实施例提供一种显示面板、其制备方法及终端。显示面板包括基板、相邻的第一有机发光二极管和第二有机发光二极管、像素定义层以及共通层。第一有机发光二极管和第二有机发光二极管分别包括第一阳极及第二阳极。共通层包括位于第一阳极上的第一部分、位于第二阳极上的第二部分、及位于像素定义层上且由于像素定义层而形成的阻断部分。如此，通过像素定义层的结构设计，使得至少部分共通层之间的横向连接被阻断，可防止串色现象的发生。

Description

显示面板、其制备方法和终端
相关申请的交叉引用
本申请要求在2021-07-02提交中国专利局、申请号为202110750493.0、申请名称为“显示面板、其制备方法和终端”的中国专利的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、其制备方法和终端。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板中，空穴注入层、空穴传输层等均为共通层(Common Layer)，其覆盖所有的子像素区域及子像素之间的间隔区域。当OELD器件工作时，由于各个子像素的共通层是相连的，载流子会在这些共通层中横向传导，使共通层产生侧向漏电，导致当一个子像素点亮时，与其相邻的子像素容易受到该子像素的影响，从而出现串色现象。
发明内容
本申请第一方面提供一种显示面板，其包括：
基板；
相邻的第一子像素及第二子像素，设置于基板上，第一子像素包括一个第一有机发光二极管，第二子像素包括一个第二有机发光二极管，第一有机发光二极管包括位于基板上的第一阳极，第二有机发光二极管包括位于基板上的第二阳极；
像素定义层，位于基板上、第一阳极上及第二阳极上，且像素定义层具有暴露第一阳极及第二阳极的像素限定孔；以及
共通层，共通层包括位于第一阳极上的第一部分、位于第二阳极上的第二部分、及位于像素定义层上且由于像素定义层而形成的阻断部分；
其中，第一部分构成第一有机发光二极管的一部分，第二部分构成第二有机发光二极管的一部分，第一部分与第二部分通过阻断部分得以绝缘间隔。
如此，通过像素定义层的结构设计，使得至少部分共通层之间的横向连接被阻断，可防止串色现象的发生。
在本申请的一些实施例中，像素定义层包括远离基板的顶表面及连接顶表面的侧表面；其中，侧表面包括凹陷部，以使共通层中形成阻断部分。也就是说，像素定义层具有破坏共通层的连续性的凹陷部。
在本申请的一些实施例中，凹陷部为在像素定义层中形成底切(Under Cut)而获得。
在本申请的一些实施例中，像素定义层包括沿远离基板的方向依次层叠设置的第一像素定义层及第二像素定义层；其中，凹陷部形成在第一像素定义层中，顶表面形成在第二像素定义层中。
在本申请的一些实施例中，顶表面包括与侧表面连接的弧面，弧面与基板的表面之间的夹角范围为5度～30度。如此，当该夹角θ范围为5度～30度时，一方面可以实现阴极缓慢搭接而不至于断线，另一方面还可以使有机发光二极管获得更大的发散角，防止色偏及低灰阶色偏的现象发生。
在本申请的一些实施例中，显示面板包括沿远离基板的方向依次层叠设置的空穴注入层、空穴传输层、有机发光层、空穴阻挡层及电子传输层；其中，共通层包括空穴注入层、空穴传输层、空穴阻挡层及电子传输层中的一层或多层。
在本申请的一些实施例中，空穴注入层与像素定义层、第一阳极及第二阳极直接接触；定义第一像素定义层的远离基板的表面到第一阳极的远离基板的表面之间的高度为h；定义空穴注入层和空穴传输层的高度之和为h L；定义空穴注入层、空穴传输层、有机发光层、空穴阻挡层及电子传输层的高度之和为h H；其中，h L≤h≤h H。也就是说，阻断的共通层至少包括空穴注入层和空穴传输层。
在本申请的一些实施例中，有机发光层包括沿远离基板的方向依次层叠设置的第一有机发光层、电子空穴对二次生成层及第二有机发光层；其中，共通层包括电子空穴对二次生成层。
在本申请的一些实施例中，显示面板还包括位于共通层远离基板一侧的阴极层；其中，阴极层为连续的膜层而不会被像素定义层阻断。
本申请第二方面提供一种显示面板，其包括：
基板；
多个有机发光二极管，间隔设置于基板上，每一有机发光二极管包括一个阳极；
像素定义层，位于基板上及阳极上，且像素定义层具有多个像素限定孔，每一像素限定孔暴露一个阳极；以及
共通层，包括位于阳极上的部分及位于像素定义层上的部分；
其中，像素定义层包括沿远离基板的方向依次层叠设置的第一像素定义层及第二像素定义层；
第一像素定义层的侧表面包括相对第二像素定义层凹陷的凹陷部，以使共通层的位于阳极上的部分与共通层的位于像素定义层上的部分被阻断。
本申请第二方面提供一种终端，其包括上述的显示面板。
由于终端包括上述的显示面板，因此，其同样具有可避免串色现象的优点。
本申请第三方面提供一种显示面板的制备方法，其包括：
于一基板上形成阵列排布的多个阳极，多个阳极包括相邻的第一阳极及第二阳极；
于基板上及多个阳极上形成像素定义层，像素定义层具有暴露第一阳极及第二阳极的像素限定孔；以及
于像素定义层上及多个阳极上形成共通层，共通层包括位于第一阳极上的第一部分、位于第二阳极上的第二部分、及位于像素定义层上且由于像素定义层而形成的阻断部分，第一部分与第二部分通过阻断部分得以绝缘间隔；
其中，第一部分用于构成一第一有机发光二极管的一部分，第二部分用于构成一第二有机发光二极管的一部分，第一有机发光二极管包括第一阳极，第二有机发光二极管包括第二阳极。
在本申请的一些实施例中，像素定义层包括远离基板的顶表面及连接顶表面的侧表面； 其中，形成像素定义层包括于侧表面形成一凹陷部。
在本申请的一些实施例中，形成像素定义层包括沿远离基板的方向依次形成层叠设置的第一像素定义层及第二像素定义层；其中，凹陷部形成在第一像素定义层中，顶表面形成在第二像素定义层中。
在本申请的一些实施例中，制备方法包括沿远离基板的方向依次形成层叠设置的空穴注入层、空穴传输层、有机发光层、空穴阻挡层及电子传输层；其中，形成共通层包括形成空穴注入层、空穴传输层、空穴阻挡层及电子传输层中的一层或多层。
在本申请的一些实施例中，形成有机发光层包括沿远离基板的方向依次形成第一有机发光层、电子空穴对二次生成层及第二有机发光层；其中，形成共通层包括形成电子空穴对二次生成层。
附图说明
图1为本申请的一些实施例中，提供的终端的结构示意图。
图2为图1中显示面板的一种结构示意图。
图3为本申请的一些实施例中，提供的OLED的一种结构示意图。
图4为本申请的一些实施例中，提供的OLED的另一种结构示意图。
图5为本申请的一些实施例中，提供的显示面板的剖面示意图。
图6为本申请的一些实施例中，提供的显示面板的制备方法的流程图。
图7为图6的方法中，形成一平坦化层的剖面示意图。
图8为于图7所示的平坦化层上，形成阳极的剖面示意图。
图9为于图8所示的结构上，形成一第一材料层、硬掩膜层及一图案化的光阻层的剖面示意图。
图10为以图9所示的图案化的光阻层为掩膜，形成图案化的硬掩膜层的剖面示意图。
图11为以图10所示的图案化的硬掩膜层为掩膜，形成第一像素定义层的剖面示意图。
图12为去除图11所示的图案化的硬掩膜层后的剖面示意图。
图13为在图12所示的第一像素定义层上，形成第二像素定义层的剖面示意图。
主要元件符号说明
终端                       100
盖板                       10
显示面板                   20
像素                       22
子像素                     222
第一子像素                 2221
第二子像素                 2222
有机发光二极管             24
阳极                       241
第一阳极                   2411
第二阳极                   2412
空穴注入层                 242
空穴传输层                243
有机发光层                244
第一有机发光层            2441
第二有机发光层            2442
电子空穴对二次生成层      2443
空穴阻挡层                245
电子传输层                246
阴极                      247
平坦层                    248
氟化锂层                  249
支撑结构                  30
TFT背板                   40
基板                      42
驱动电路层                44
平坦化层                  46
像素定义层                48
第一像素定义层            482
侧表面                    4822
凹陷部                    4824
第二像素定义层            484
顶表面                    4842
夹角                      θ
像素限定孔                486
第一材料层                52
硬掩膜层                  54
图案化的光阻层            56
图案化的硬掩膜层          58
共通层                    60
第一部分                  61
第二部分                  62
阻断部分                  63
如下具体实施方式将结合上述附图进一步说明本申请。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
本申请实施例提供一种终端，该终端可以为手机、显示器、平板电脑、车载电脑等具有显示界面的产品，以及智能手表、智能手环等智能显示穿戴产品。以下以终端为手机进行举例说明。
如图1所示，终端100包括盖板10、显示面板20及支撑结构30。盖板10界定终端100的显示面。显示面板20用以显示画面。支撑结构30也称壳体或后盖或电池盖。盖板10和支撑结构30配合形成容置空间(图未示)，显示面板20位于盖板10及支撑结构30之间的容置空间内。另，容置空间内还可以装设其他功能部件/电子元器件，如主板、电池等。
以下对显示面板20的结构进行说明。
如图2所示，显示面板20包括阵列排布的多个像素(Pixel)22。每一像素22包括至少一个用于发出的可见光的子像素222。图2中，第一像素22中包括三个子像素222，分别为发红光的显示子像素R、发绿光的显示子像素G以及发蓝光的显示子像素B。
在本申请的一些实施例中，像素22中的三个子像素222发出的可见光分别为青色光、品红色光以及黄光。或者，在本申请的另一些实施例中，像素22中包括四个子像素222，该四个子像素222发出的可见光分别为红光、绿光、蓝光，以及白光。或者，在本申请的再一些实施例中，显示面板20为单色显示面板，其包括的子像素222均为发出相同颜色的可见光。例如，显示面板20中的各个子像素均为发绿光的子像素。即，对像素22中的子像素222的数量及发光颜色的组合不作限定。
在此基础上，为了使得上述子像素222能够发出可见光，在本申请的一些实施例中，显示面板20还包括多个有机发光二极管(Organic Light Emitting Diode,OLED)24。每个OLED 24与一个子像素222相对应，且每个OLED 24位于与该OLED 24对应的子像素222内，从而使得显示面板20能够实现自发光，无需设置背光源。显示面板20有源矩阵有机发光二极管(active matrix organic light emitting diode,AMOLED)显示面板，其具有色彩艳丽、对比度高、响应速度快等优势。在一些实施例中，显示面板20为柔性的OLED显示面板，其还具有可弯曲、可变形的特点，在可弯折手机以及曲面显示等异形显示方面具有巨大潜力。
以下对上述OLED 24在显示面板20中的设置方式进行举例说明。
OLED 24之示例一
图3中示意性地画出了三个OLED 24。如图3所示，每一OLED 24包括有机发光层244及位于有机发光层244的相对两侧的阳极(Anode)241和阴极(Cathode)247。每一OLED 24的阳极241为相互独立的，多个OLED 24的阴极247为一个整层。
在本申请的一些实施例中，阳极241的材料可以为金属材料，例如铝(A1)、镁(Mg)、银(Ag)、镁银合金(Mg/Ag)等。镁银合金(Mg/Ag)中Mg的比例例如在8％～12％之间。阴极247的材料可以为透明或半透明导电材料，例如，氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)。在此情况下，阴极247透光，阳极241的透光率很小，因此OLED 24发出的光线由阴极247所在的一侧出射。此时，OLED 24为顶发射型发光器件。
在本申请的另一些实施例中，阳极241的材料可以为上述透明导电材料；阴极247的材料为上述金属材料。在此情况下，阳极241透光，阴极247的透光率很小，因此OLED24发出的光线由阳极241所在的一侧出射。此时，OLED 24为底发射型发光器件。
基于此，向有机发光层244两侧的阳极241和阴极247施加电压后，从阳极241注入空穴，从阴极247注入电子，阳极241和阴极247中的载流子在有机发光层244中复合发生淬灭，从而使得有机发光层244发出光波辐射。此时，上述OLED 24发光，具有 多个上述OLED 24的显示面板20进行画面显示。其中。同一像素22中，不同子像素222中的OLED 24的有机发光层244的材料不同，使得不同子像素222中的OLED 24发出颜色不同的可见光，例如红光、绿光或蓝光。图3中，发红光的子像素222的有机发光层244包括红色基底层(R prime，R’)及红光发射层(R-emission layer，R-EML)；发绿光的子像素222的有机发光层244包括绿色基底层(G prime，G’)及绿光发射层(G-emission layer，G-EML)；发蓝光的子像素222的有机发光层244包括蓝色基底层(B prime，B’)及蓝光发射层(B-emission layer，B-EML)。每一个阳极241与一个子像素222相对应。
此外，为提高阳极241和阴极247中的载流子在有机发光层244中相遇的几率，以提高OLED 24的发光效率，如图3所示，上述OLED 24还包括空穴注入层(Hole Inject Layer，HIL)242、空穴传输层(Hole Transfer Layer，HTL)243、空穴阻挡层(Hole Block Layer，HBL)245、电子传输层(Electron Transfer Layer，ETL)246。其中，空穴注入层242、空穴传输层243位于有机发光层244与阳极241之间。空穴阻挡层245、电子传输层246位于有机发光层244与阴极247之间，且依次靠近阴极247。即，图3中，OLED24中各膜层的层叠顺序依次为阳极241、空穴注入层242、空穴传输层243、有机发光层244、空穴阻挡层245、电子传输层246及阴极247。
此外，如图3所示，上述OLED 24还包括位于阴极247上的平坦层(Capping Layer，CPL)248及位于平坦层248上的氟化锂(LiF)层249。平坦层248能够提高OLED 24微腔出光效率，氟化锂层249能够隔绝离子，以提高出光效率。
OLED 24之示例二
示例二中的OLED 24，其与示例一的OLED 24的不同在于：示例二中，OLED 24包括多个有机发光层。图4中示出了三个示例二中的OLED 24。如图4所示，示例二中的每一OLED 24包括第一有机发光层2441、第二有机发光层2442、及位于第一有机发光层2441、第二有机发光层2442之间的电子空穴对二次生成层2443。电子空穴对二次生成层2443也称电荷生成层(Charge Generation Layer，CGL)。其中，电子空穴对二次生成层2443包括电子二次生成层(N-CGL)及空穴二次生成层(P-CGL)。N-CGL一般为有机物敏化剂，其可以包括金属镱(Yb)，当镱用于有机物的电子敏化剂中时，可以促进有机物释放电子。P-CGL中的P型材料掺杂剂可以为掺杂重量比例为3％的2,2'-(1,3,4,5,6,8,9,10-八氟-2,7-二亚基芘)双丙二腈，化学式如下：
Figure PCTCN2022087163-appb-000001
即，图4中，OLED 24中各膜层的层叠顺序依次为阳极241、空穴注入层242、空穴传输层243、第一有机发光层2441、电子空穴对二次生成层2443、第二有机发光层2442、 空穴阻挡层245、电子传输层246及阴极247。该种结构的OLED 24由于串联了更多的有机发光层，出光效率提升，在相同的电流密度下，亮度也更高。
对于图3所示的OLED 24中，空穴注入层242、空穴传输层243、空穴阻挡层245、电子传输层246及阴极247等均为共通层，其为同时沉积/覆盖在各个子像素222(如，R/G/B)上面的功能层。对于图4所示的OLED 24中，空穴注入层242、空穴传输层243、空穴阻挡层245、电子传输层246、阴极247、以及电子空穴对二次生成层2443均为共通层，其为同时沉积/覆盖在各个子像素222(如，R/G/B)上面的功能层。如果在这些共通层之间存在侧向漏电，那么会导致出现串色的现象。
以下具体介绍如何解决显示面板20中由于共通层的侧向漏电而导致的串色的问题。
如图5所示，显示面板20包括薄膜晶体管(Thin Film Transistor,TFT)背板40，TFT背板40包括基板42、设置于基板42上的驱动电路层44、设置于驱动电路层44远离基板42的一侧平坦化层(Planarization，PLN)46及像素定义层(Pixel Define Layer，PDL)48。
基板42作为承载位于其上方的驱动电路层44、像素定义层48等各层的承载基体，其材料可以为聚对苯二甲酸类塑料(Polyethylene Terephthalate，PET)、聚酰亚胺(Polyimide，PI)等柔性材料。
驱动电路层44例如包括阵列排布的像素驱动电路(图未示)。每一像素驱动电路包括多个驱动TFT，每一个OLED 24的阳极241用于与一个驱动TFT电性连接，以在驱动TFT的控制下发光。平坦化层46覆盖多个驱动TFT，以对基板42上的驱动TFT的起伏起到平坦、绝缘及保护的作用。
像素定义层48具有暴露OLED 24的阳极241的多个像素限定孔486(图5中示例性地画出了两个)，每一个像素限定孔486暴露一个OLED 24的阳极241。像素定义层48位于平坦化层46上相邻两个阳极241之间，并至少部分覆盖阳极241。每一像素限定孔486与一个子像素222相对应。每一个OLED 24与一个像素限定孔486相对应(图5中省略了OLED 24的部分膜层，仅画图了OLED 24的阳极241)。OLED 24的阳极241可通过平坦化层46开设的通孔(图未示)，以与驱动TFT实现电性连接。平坦化层46可以给阳极241提供一个平坦的反射面。
以下为描述方便，定义位于一像素22中的相邻的两个子像素222分别为第一子像素2221及第二子像素2222。定义第一子像素2221中的OLED 24为第一OLED，第二子像素2222中的OLED 24为第二OLED。定义第一OLED的阳极241为第一阳极2411，第二OLED的阳极241为第二阳极2412。第一阳极2411和第二阳极2412在间隔设置于平坦化层46上。
在本申请的一些实施例中，通过像素定义层48的结构设计，使得上述共通层60中至少一层被像素定义层48阻断。其中，该阻断的共通层60至少被分为位于第一阳极2411上的第一部分61、位于第二阳极2412上的第二部分62以及位于像素定义层48上且由于像素定义层48而形成的阻断部分63。第一部分61构成第一OLED的一部分，第二部分62构成第二OLED的一部分，第一部分61和第二部分62通过阻断部分63得以绝缘间隔。如此，通过像素定义层48的结构设计至少部分共通层60之间的横向连接被阻断，以防止串色现象的发生。
以下详细说明像素定义层48的具体结构。
如图5所示，像素定义层48包括远离基板42的顶表面4842及连接顶表面4842的侧表面4822。侧表面4822包括利于使共通层60中形成阻断部分63的凹陷部4824。凹陷部4824沿着一个OLED 24的阳极241指向与其相邻的OLED 24的阳极241的方向凹陷。也就是说，像素定义层48中具有破坏共通层60的连续性的凹陷部4824。
在本申请的一些实施例中，凹陷部4824为在像素定义层48中形成底切(Under Cut)而获得。为在侧表面4822中形成所需的底切的形状，像素定义层48可由多层材料构成。图5中，像素定义层48包括沿远离基板42的方向依次层叠设置的第一像素定义层482及第二像素定义层484。凹陷部4824形成在第一像素定义层482中。像素定义层48的顶表面4842形成在第二像素定义层484中，像素定义层48的顶表面4842为第二像素定义层484的远离基板42的表面。第一像素定义层482中存在底切形成的倒角，第二像素定义层484的顶表面4842包括与侧表面4822连接的弧面。
在本申请的一些实施例中，弧面与基板42的上表面之间的夹角θ范围为5度～30度。或者说，弧面与OLED 24的阳极241远离基板42的上表面之间的夹角θ范围为5度～30度。在一些实施例中，弧面与阳极241远离基板42的上表面之间的夹角θ小于等于15度。其中，如果弧面与OLED 24的阳极241的上表面之间的夹角θ过小，会导致各个OLED 24的阴极247在搭接过程断线；而如果该夹角θ过大，则不利于OLED 24的出射光的发散。如此，当该夹角θ范围为5度～30度时，一方面可以实现阴极247缓慢搭接而不至于断线，另一方面还可以使OLED 24获得更大的发散角，防止色偏及低灰阶色偏的现象发生。
在本申请的一些实施例中，第二像素定义层484的制备步骤中，还可以通过半掩膜工艺一次构图形成位于第二像素定义层484上的支撑柱(图未示)。支撑柱用作支撑结构30，可以在蒸镀形成OLED 24的过程中，有效的避免用于蒸镀形成OLED 24发光器件的各功能层的蒸镀掩模板接触显示面板20，以提高显示面板20的产品良率。
在本申请的一些实施例中，OLED 24具有图3所示的结构。共通层包括空穴注入层242、空穴传输层243、空穴阻挡层245、电子传输层246及阴极247。当其设置于像素限定孔486内时，空穴注入层242、空穴传输层243、有机发光层244、空穴阻挡层245、电子传输层246依次形成于阳极241上。其中，空穴注入层242、空穴传输层243、空穴阻挡层245及电子传输层246中的至少一层被阻断，但是阴极247不会被阻断。
具体地，空穴注入层242与像素定义层48、OLED 24的阳极241直接接触。相邻的两个OLED 24的阳极241远离基板42的上表面的基本位于同一平面内。如图5所示，定义第一像素定义层482的远离基板42的表面到OLED 24的阳极241的远离基板42的表面之间的高度为h。如图3和图4所示，定义空穴注入层242和空穴传输层243的高度之和为h L；定义空穴注入层242、空穴传输层243、有机发光层244、空穴阻挡层245及电子传输层246的高度之和为h H。其中，h L≤h≤h H。也就是说，第一像素定义层482的顶部到OLED 24的阳极241的上表面的高度为h,至少有机发光层244以下的共通层(空穴注入层242和空穴传输层243)的高度h L大于等于h，使得至少空穴注入层242和空穴传输层243被阻断。即，阻断的共通层60至少包括空穴注入层242和空穴传输层243。另外，阴极247与阳极241之间的膜层的高度为h H，其中h≤h H，使得各OLED 24的阴极247构成的阴极247层为连续的膜层而不会被像素定义层48阻断。
在本申请的另一些实施例中，OLED 24具有图4所示的结构。共通层包括空穴注入层242、空穴传输层243、空穴阻挡层245、电子传输层246、阴极247以及电子空穴对二次生成层2443。当其设置于像素限定孔486内时，空穴注入层242、空穴传输层243、第一有机发光层2441、电子空穴对二次生成层2443、第二有机发光层2442、空穴阻挡层245、电子传输层246依次形成于阳极241上。其中，空穴注入层242、空穴传输层243、空穴阻挡层245、电子传输层246、电子空穴对二次生成层2443中的至少一层被阻断，但是阴极247不会被阻断。
具体地，空穴注入层242与像素定义层48、OLED 24的阳极241直接接触。相邻的两个OLED 24的阳极241远离基板42的上表面的基本位于同一平面内。定义第一像素定义层482的远离基板42的表面到OLED 24的阳极241的远离基板42的表面之间的高度为h；定义空穴注入层242和空穴传输层243的高度之和为h L；定义空穴注入层242、空穴传输层243、有机发光层244(包括第一有机发光层2441、电子空穴对二次生成层2443及第二有机发光层2442)、空穴阻挡层245及电子传输层246的高度之和为h H；其中，h L≤h≤h H。也就是说，第一像素定义层482的顶部到OLED 24的阳极241的上表面的高度为h，至少有机发光层244以下的共通层(空穴注入层242和空穴传输层243)的高度h L大于等于h，使得至少空穴注入层242和空穴传输层243被阻断。即，阻断的共通层60至少包括空穴注入层242和空穴传输层243。另外，阴极247与阳极241之间的膜层的高度为h H，其中h≤h H，使得各OLED 24的阴极247构成的阴极247层为连续的膜层而不会被像素定义层48阻断。
在本申请的一些实施例中，第一像素定义层482的顶部到OLED 24的阳极241的上表面的高度h的范围为0.3μm～1μm。其中，如果h太小，则无法有效实现对共通层60的阻断，而如果h太大，则容易造成阴极247搭接过程中的开路(Open)。
在本申请的一些实施例中，平坦化层46可以为有机材料，例如，其可以为PI系有机材料。第一像素定义层482及第二像素定义层484的材料可以为有机材料或无机材料，例如，其可以为有机硅氧烷、硅氧化物(SiOx)、硅氮化物(SiNx)、金属氧化物等。此外，需要说明的是，像素定义层48的数量不作限定，其也可以为大于两层的多层。
综上，通过像素定义层48的结构设计，使得相邻的两个子像素222中的OLED 24的至少部分共通层60被阻断，以减少相邻的子像素222之间的共通层60的侧向漏电，进而改善显示面板20发光串扰的问题，提升显示品质。
本申请的一些实施例中，还提供上述显示面板的制备方法。根据不同需求，所述制备方法的步骤顺序可以改变，某些步骤可以省略或合并。如图6所示，该制备方法包括以下步骤。
步骤S11：于一基板上形成多个阳极。
步骤S12：于基板及阳极上形成像素定义层。
步骤S13：于像素定义层及阳极上形成阻断的共通层。
以下具体说明各个步骤。
步骤S11：于一基板上形成多个阳极。
在本申请的一些实施例中，形成阳极之前还包括，于所述基板上依次形成驱动电路层及平坦化层。
如图7所示，平坦化层46位于驱动电路层44远离基板42的表面上。驱动电路层44例如包括阵列排布的像素驱动电路。每一像素驱动电路包括多个驱动TFT。平坦化层46覆盖多个驱动TFT。在本申请的一些实施例中，平坦化层46为有机材料，例如，可以使用PI系有机材料形成平坦化层46。
如图8所示，步骤S11中形成的阳极241位于平坦化层46远离基板42的表面上。具体地，步骤S11中形成的阳极241具有多个，且多个阳极241间隔且呈阵列排布于平坦化层46上(图8中示例性地画出了一个)。平坦化层46开设有通孔(图未示)，每一个阳极241通过平坦化层46上的一个通孔与一个驱动TFT实现电性连接。在本申请的一些实施例中，阳极241可通过模内镶件注塑(In Molding Label，IML)形成。
步骤S12：于基板及阳极上形成像素定义层。以下参图9至图13说明步骤S12。
如图9所示，其包括于基板42及阳极241上形成一第一材料层52、一硬掩膜(Hard Mask)层54及一图案化的光阻层56。其中，第一材料层52可以为有机硅氧烷，其用于后续形成第一像素定义层482。硬掩膜层54例如为ITO。硬掩膜层54也可以为其他材料，例如氮化硅、氧化硅、氧化铝等。
如图10所示，以图9中的图案化的光阻层56为掩膜，刻蚀硬掩膜层54，得到一图案化的硬掩膜层58，图案化的硬掩膜层58暴露出部分第一材料层52。在一些实施例中，刻蚀硬掩膜层54的步骤可以为对ITO进行湿蚀刻。
如图11所示，以图案化的硬掩膜层58为掩膜，处理第一材料层52。其中，第一材料层52形成有暴露阳极241的像素限定孔486，且在像素限定孔486处，第一材料层52中形成有底切。具体地，可采用CL 2/O 2等离子体对第一材料层52进行灰化处理，调整刻蚀参数，以在第一材料层52中形成所需的底切，得到第一像素定义层482。
如图12所示，形成第一像素定义层482后，去除图案化的硬掩膜层58。底切形成第一像素定义层482的凹陷部4824。
如图13所示，于第一像素定义层482上形成第二像素定义层484。像素限定孔486延伸贯穿第二像素定义层484，第二像素定义层484包括相与第一像素定义层482的侧表面4822连接的顶表面4842。顶表面4842包括弧面。弧面与阳极241远离基板42的上表面之间的夹角θ(标注在图5中)范围为5度～30度。在一些实施例中，弧面与阳极241远离基板42的上表面之间的夹角θ小于等于15度。其中，形成第二像素定义层484可采用有机硅氧烷形成，该步骤中还包括使用氧化等离子体对阳极241进行灰化处理，以清除底切位置(也称倒角位置)的光阻。第一像素定义层482及第二像素定义层484构成像素定义层48。每一像素限定孔486暴露一个阳极241。
步骤S13：于像素定义层及阳极上形成阻断的共通层。
在形成像素定义层后，步骤S13包括于像素定义层上及多个阳极上依次形成空穴注入层、空穴传输层、有机发光层、空穴阻挡层、电子传输层及阴极层。其中，空穴注入层、空穴传输层、空穴阻挡层、电子传输层及阴极层均为共通层，其为同时沉积/覆盖在各个子像素(如R/G/B)上面的功能层。此外，对于具有多个有机发光层的OLED结构，有机发光层中还包括位于相邻的两个有机发光层之间的电子空穴对二次生成层。共通层包括电子空穴对二次生成层。
在本申请的一些实施例中，由于像素定义层48的结构设置，使得上述共通层中的至少一层被像素定义层48阻断。该阻断的共通层包括空穴注入层、空穴传输层、空穴阻挡 层、电子传输层、电子空穴对二次生成层中的一层或多层，但是不包括阴极层。即，阴极层为连续的膜层。该阻断的共通层包括位于每一阳极241上用于构成OLED 24的一部分的部分及位于像素定义层48上的阻断部分。该阻断的共通层的位于阳极241上的部分与位于像素定义层48上的阻断部分由于像素定义层48而被阻断得以绝缘间隔。
由于该阻断的共通层的位于每一阳极241上的部分与该阻断的共通层的位于像素定义层48上的部分为中断的，因此，该阻断的共通层的位于相邻的阳极241上的部分也是绝缘且间隔设置的。换句话说，定义相邻的两个子像素分别为第一子像素及第二子像素。定义第一子像素包括的OLED为第一OLED，第二子像素包括的OLED为第二OLED。定义第一OLED的阳极为第一阳极，第二OLED的阳极为第二阳极。像素定义层48暴露第一阳极及第二阳极。阻断的共通层包括位于第一阳极上用于构成第一OLED的一部分的第一部分、位于第二阳极上用于构成一第二OLED的一部分的第二部分及位于像素定义层48上且由于像素定义层48而形成的阻断部分。第一部分与第二部分通过阻断部分得以绝缘间隔。如此，相邻的两个子像素中的OLED的至少部分共通层为阻断的，减少了相邻的子像素之间的共通层的侧向漏电，改善了显示面板发光串扰的问题，提升了显示品质。
以上实施例仅用以说明本申请的技术方案而非限制，尽管参照较佳实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解，可以对本申请的技术方案进行修改或等同替换，而不脱离本申请技术方案的精神和实质。

Claims (20)

  1. 一种显示面板，其特征在于，包括：
    基板；
    相邻的第一子像素及第二子像素，设置于所述基板上，所述第一子像素包括一个第一有机发光二极管，所述第二子像素包括一个第二有机发光二极管，所述第一有机发光二极管包括位于所述基板上的第一阳极，所述第二有机发光二极管包括位于所述基板上的第二阳极；
    像素定义层，位于所述基板上、所述第一阳极上及所述第二阳极上，且所述像素定义层具有暴露所述第一阳极及所述第二阳极的像素限定孔；以及
    共通层，所述共通层包括位于所述第一阳极上的第一部分、位于所述第二阳极上的第二部分、及位于所述像素定义层上且由于所述像素定义层而形成的阻断部分；
    其中，所述第一部分构成所述第一有机发光二极管的一部分，所述第二部分构成所述第二有机发光二极管的一部分，所述第一部分与所述第二部分通过所述阻断部分得以绝缘间隔。
  2. 如权利要求1所述的显示面板，其特征在于，所述像素定义层包括远离所述基板的顶表面及连接所述顶表面的侧表面；其中，所述侧表面包括凹陷部，以使所述共通层中形成所述阻断部分。
  3. 如权利要求2所述的显示面板，其特征在于，所述像素定义层包括沿远离所述基板的方向依次层叠设置的第一像素定义层及第二像素定义层；其中，所述凹陷部形成在所述第一像素定义层中，所述顶表面形成在所述第二像素定义层中。
  4. 如权利要求3所述的显示面板，其特征在于，所述顶表面包括与所述侧表面连接的弧面，所述弧面与所述基板的表面之间的夹角范围为5度～30度。
  5. 如权利要求1至4中任意一项所述的显示面板，其特征在于，所述显示面板包括沿远离所述基板的方向依次层叠设置的空穴注入层、空穴传输层、有机发光层、空穴阻挡层及电子传输层；其中，所述共通层包括所述空穴注入层、所述空穴传输层、所述空穴阻挡层及所述电子传输层中的一层或多层。
  6. 如权利要求5所述的显示面板，其特征在于，所述空穴注入层与所述像素定义层、所述第一阳极及所述第二阳极直接接触；
    定义所述第一像素定义层的远离所述基板的表面到所述第一阳极的远离所述基板的表面之间的高度为h；
    定义所述空穴注入层和所述空穴传输层的高度之和为h L；
    定义所述空穴注入层、所述空穴传输层、所述有机发光层、所述空穴阻挡层及所述电子传输层的高度之和为h H；
    其中，h L≤h≤h H。
  7. 如权利要求6所述的显示面板，其特征在于，所述有机发光层包括沿远离所述基板的方向依次层叠设置的第一有机发光层、电子空穴对二次生成层及第二有机发光层；其中，所述共通层包括所述电子空穴对二次生成层。
  8. 如权利要求1至7中任意一项所述的显示面板，其特征在于，所述显示面板还包括位于所述共通层远离所述基板一侧的阴极层；其中，所述阴极层为连续的膜层。
  9. 一种显示面板，其特征在于，包括：
    基板；
    多个有机发光二极管，间隔设置于所述基板上，每一所述有机发光二极管包括一个阳极；
    像素定义层，位于所述基板上及所述阳极上，且所述像素定义层具有多个像素限定孔，每一所述像素限定孔暴露一个所述阳极；以及
    共通层，包括位于所述阳极上的部分及位于所述像素定义层上的部分；
    其中，所述像素定义层包括沿远离所述基板的方向依次层叠设置的第一像素定义层及第二像素定义层；
    所述第一像素定义层的侧表面包括相对所述第二像素定义层凹陷的凹陷部，以使所述共通层的位于所述阳极上的部分与所述共通层的位于所述像素定义层上的部分被阻断。
  10. 如权利要求9所述的显示面板，其特征在于，所述第二像素定义层包括与所述侧表面连接的弧面，所述弧面与所述基板的表面之间的夹角范围为5度～30度。
  11. 如权利要求9或10所述的显示面板，其特征在于，所述显示面板包括沿远离所述基板的方向依次层叠设置的空穴注入层、空穴传输层、有机发光层、空穴阻挡层及电子传输层；其中，所述共通层包括所述空穴注入层、所述空穴传输层、所述空穴阻挡层及所述电子传输层中的一层或多层。
  12. 如权利要求11所述的显示面板，其特征在于，所述空穴注入层与所述像素定义层及所述阳极直接接触；
    定义所述第一像素定义层的远离所述基板的表面到所述阳极的远离所述基板的表面之间的高度为h；
    定义所述空穴注入层和所述空穴传输层的高度之和为h L；
    定义所述空穴注入层、所述空穴传输层、所述有机发光层、所述空穴阻挡层及所述电子传输层的高度之和为h H；
    其中，h L≤h≤h H。
  13. 如权利要求12所述的显示面板，其特征在于，所述有机发光层包括沿远离所述基板的方向依次层叠设置的第一有机发光层、电子空穴对二次生成层及第二有机发光层；其中，所述共通层包括所述电子空穴对二次生成层。
  14. 如权利要求9至13中任意一项所述的显示面板，其特征在于，所述显示面板还包括位于所述共通层远离所述基板一侧的阴极层；其中，所述阴极层为连续的膜层。
  15. 一种终端，其特征在于，包括如权利要求1至14中任意一项所述的显示面板。
  16. 一种显示面板的制备方法，其特征在于，包括：
    于一基板上形成阵列排布的多个阳极，所述多个阳极包括相邻的第一阳极及第二阳极；
    于所述基板上及所述多个阳极上形成像素定义层，所述像素定义层具有暴露所述第一阳极及所述第二阳极的像素限定孔；以及
    于所述像素定义层上及所述多个阳极上形成共通层，所述共通层包括位于所述第一阳极上的第一部分、位于所述第二阳极上的第二部分、及位于所述像素定义层上且由于所述像素定义层而形成的阻断部分，所述第一部分与所述第二部分通过所述阻断部分得以绝缘间隔；
    其中，所述第一部分用于构成一第一有机发光二极管的一部分，所述第二部分用于构成一第二有机发光二极管的一部分，所述第一有机发光二极管包括所述第一阳极，所述第二有机发光二极管包括所述第二阳极。
  17. 如权利要求16所述的显示面板的制备方法，其特征在于，所述像素定义层包括远离所述基板的顶表面及连接所述顶表面的侧表面；其中，形成所述像素定义层包括于所述侧表 面形成一凹陷部。
  18. 如权利要求17所述的显示面板的制备方法，其特征在于，形成所述像素定义层包括沿远离所述基板的方向依次形成层叠设置的第一像素定义层及第二像素定义层；其中，所述凹陷部形成在所述第一像素定义层中，所述顶表面形成在所述第二像素定义层中。
  19. 如权利要求18所述的显示面板的制备方法，其特征在于，所述制备方法包括沿远离所述基板的方向依次形成层叠设置的空穴注入层、空穴传输层、有机发光层、空穴阻挡层及电子传输层；其中，形成所述共通层包括形成所述空穴注入层、所述空穴传输层、所述空穴阻挡层及所述电子传输层中的一层或多层。
  20. 如权利要求19所述的显示面板的制备方法，其特征在于，形成所述有机发光层包括沿远离所述基板的方向依次形成第一有机发光层、电子空穴对二次生成层及第二有机发光层；其中，形成所述共通层包括形成所述电子空穴对二次生成层。
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