WO2021248612A1 - 电路基板制备方法及电路基板 - Google Patents

电路基板制备方法及电路基板 Download PDF

Info

Publication number
WO2021248612A1
WO2021248612A1 PCT/CN2020/101272 CN2020101272W WO2021248612A1 WO 2021248612 A1 WO2021248612 A1 WO 2021248612A1 CN 2020101272 W CN2020101272 W CN 2020101272W WO 2021248612 A1 WO2021248612 A1 WO 2021248612A1
Authority
WO
WIPO (PCT)
Prior art keywords
copper foil
circuit substrate
release film
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/101272
Other languages
English (en)
French (fr)
Inventor
计美阳
陈勇利
韩佳明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AAC Technologies Holdings Shenzhen Co Ltd
AAC Module Technologies Changzhou Co Ltd
Original Assignee
AAC Acoustic Technologies Shenzhen Co Ltd
AAC Module Technologies Changzhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AAC Acoustic Technologies Shenzhen Co Ltd, AAC Module Technologies Changzhou Co Ltd filed Critical AAC Acoustic Technologies Shenzhen Co Ltd
Publication of WO2021248612A1 publication Critical patent/WO2021248612A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement

Definitions

  • the invention relates to the field of circuit substrates, and in particular to a method for preparing a circuit substrate and a circuit substrate.
  • a key process for realizing the layer-to-layer interconnection of circuit substrates of higher density circuit boards is microporation, that is, the processing of micro-holes between layers that connect the circuit substrate.
  • Conductive paste has good processability and conductive effect. It is introduced into the micro-holes of the circuit substrate to form a conductive paste plug micro-hole structure, which can improve the flexibility of the printed circuit board hole interconnection design, and to achieve complex functions. Provide support for manufacturing circuit products.
  • the related art conductive paste plugging micro-hole process is specifically: after the blind hole of the laser circuit substrate, the scum at the bottom of the hole is removed by plasma treatment, and then the hole is filled by printing copper paste, and then the circuit substrate after the hole is filled Pressing to achieve layer-to-layer conduction.
  • the existing technology cannot accurately control the amount of copper paste. Specifically, plug the copper paste in the micro-holes. If the amount of copper paste is too thin, it will be difficult to achieve electrical connection between layers Risk of conduction. In addition, if the copper paste is too thick, there will be more copper paste residues, and it is easy to cause failure of the multi-layer board bonding force of the circuit substrate, which will cause the reliability of the circuit substrate and lead to product quality defects.
  • the technical problem to be solved by the present invention is to provide a method for preparing a circuit substrate and a circuit substrate with a simple process and high reliability.
  • the present invention provides a method for preparing a circuit substrate.
  • the circuit substrate includes a multilayer copper foil substrate.
  • the copper foil substrate includes an insulating dielectric layer and a copper foil covering one side of the insulating dielectric layer.
  • the method includes the following steps: step S1, etching the copper foil layer of the copper foil substrate to obtain a copper foil circuit; step S2, removing the insulating dielectric layer of the copper foil substrate away from the copper One side of the foil layer is bonded and fixed with a release film; step S3, laser the copper foil substrate to form a blind hole that sequentially penetrates the release film and the insulating dielectric layer; the blind hole and the copper foil Layer connection; step S4, fill the blind holes of the copper foil substrate with conductive paste and make the conductive paste level with the release film; step S5, remove the release film; step S6, will pass After the steps S1 to S5, a plurality of the copper foil substrates are sequentially stacked and pressed to obtain the circuit substrate; the respective copper foil lines of the two adjacent copper foil layers are connected to the same The conductive paste in the blind hole or the two overlapping blind holes is electrically connected.
  • the method further includes: step S40, using plasma to treat the release film and the blind holes to clean the copper foil substrate.
  • the thickness of the release film is 25 microns.
  • the release film and the insulating dielectric layer are bonded and fixed by a glue layer with a thickness of 3 microns.
  • the release film and the insulating medium layer are pressed and fixed by a film pressing machine at a temperature of 100° C. and a pressure of 7 kg.
  • the conductive paste is copper paste.
  • step S6 a plurality of the copper foil substrates are laminated to obtain the circuit substrate at a time.
  • the present invention also provides a circuit substrate, which is made by the circuit substrate preparation method.
  • the copper foil layer of the copper foil substrate is etched through step S1 to obtain the copper foil circuit; step S2, the insulating dielectric layer of the copper foil substrate is far away from the copper One side of the foil layer is attached and fixed with a release film; step S3, the laser copper foil substrate is formed to form a blind hole successively penetrating the release film and the insulating dielectric layer; step S4, the blind hole of the copper foil substrate is filled with conductive paste and Make the conductive paste flush with the release film; step S5, remove the release film; step S6, sequentially stack and press a plurality of copper foil substrates processed in steps S1 to S5 to obtain a circuit substrate.
  • the use of conductive paste to fill the blind holes can simplify the production process, the process is simple and the interconnection between any number of layers is realized, the physical space for wiring is increased, and the realization of more complex printed circuit products provides support.
  • the use of release film and conductive paste to fill the holes can effectively control the content of conductive paste, improve product quality, and improve reliability.
  • Fig. 1 is a flow chart of a method for preparing a circuit substrate of the present invention
  • step S3 is a schematic diagram of step S3 of the method for preparing a circuit substrate of the present invention.
  • step S40 of the method for preparing a circuit substrate of the present invention is a schematic diagram of step S40 of the method for preparing a circuit substrate of the present invention.
  • step S4 of the method for preparing a circuit substrate of the present invention
  • FIG. 7 is a schematic diagram of step S5 of the method for preparing a circuit substrate of the present invention.
  • FIG. 8 is a schematic diagram of pressing two of the copper foil substrates in step S6 of the method for preparing a circuit substrate of the present invention.
  • FIG. 9 is a schematic diagram of the circuit substrate in step S6 of the method for preparing a circuit substrate of the present invention.
  • FIG. 10 is a flowchart of step S40 of the method for manufacturing a circuit substrate of the present invention.
  • the present invention provides a method for preparing a circuit substrate. This method is used to prepare the circuit substrate 100.
  • the circuit substrate 100 includes a multilayer copper foil substrate 10.
  • the copper foil substrate 10 is made of liquid crystal polymer.
  • Liquid crystal polymer (English as LIQUID CRYSTAL POLYMER, LCP for short), liquid crystal polymer is a new type of polymer material and can withstand the vapor phase welding and infrared welding used in surface assembly technology. Dimensional stability and heat resistance have high requirements. Specifically applied to printed circuit boards.
  • the copper foil substrate 10 includes a copper foil layer 1 and an insulating dielectric layer 2.
  • the copper foil layer 1 covers one side surface of the insulating dielectric layer 2.
  • the preparation method of the circuit substrate includes the following steps:
  • Step S1 etching the copper foil layer 1 of the copper foil substrate 10 to obtain a copper foil circuit 12 and a copper foil circuit gap 11.
  • Step S2 A layer of release film 3 is attached and fixed to the side of the insulating dielectric layer 2 of the copper foil substrate 10 away from the copper foil layer 1.
  • the release film 3 and the insulating dielectric layer 2 are fixed by a glue layer 6 with a thickness of 3 microns.
  • the thickness of the adhesive layer 6 is small, which can ensure the adhesion while not affecting the thickness of the copper paste plug hole.
  • the release film 3 and the insulating medium layer 2 are pressed and fixed by a film pressing machine at a temperature of 100° C. and a pressure of 7 kg.
  • the film press machine can be a manual film press machine. Through the pressing and fixing of this condition, the release film 3 avoids the generation of air bubbles during the film pressing process, which is beneficial to improve reliability.
  • Step S3 laser the copper foil substrate 10 to form a blind hole 4 that sequentially penetrates the release film 3 and the insulating dielectric layer 2.
  • the blind hole 4 is used to realize the conductivity of the two adjacent layers of the copper foil circuit 12.
  • blind hole 4 is connected to the copper foil layer 1.
  • the method for preparing the circuit substrate further includes: step S40, using plasma to treat the release film 3 and the blind hole 4 to clean the copper foil substrate 10.
  • the laser treatment leaves a small amount of impurities 7 such as glue blocks on the surface of the release film 3 and the blind holes 4. Since the aperture of the blind hole 4 is small, the smaller impurities 7 can be cleaned by plasma treatment, which is beneficial to the subsequent filling of the blind hole 4 with conductive material.
  • Step S4 Fill the blind hole 4 of the copper foil substrate 10 with a conductive paste 5 and make the conductive paste flush with the release film.
  • the conductive paste 5 is a copper paste. Copper paste has good electrical conductivity. Wherein, the conductive paste 5 will be filled into the blind holes 4 by printing copper paste. Using the conductive paste 5 instead of electroplating to fill holes can simplify the manufacturing process, thereby simplifying the process.
  • Step S5 Remove the release film 3.
  • the thickness of the release film 3 is 25 microns.
  • the thickness of the additional layer of the release film 3 makes the surplus of the conductive paste 5 meet the requirement that there will be no disconnection between the layers caused by the compaction of the conductive paste 5 after the pressing, and another The thinner thickness of the release film 3 will not cause the conductive paste 5 to remain thick and cause product quality defects.
  • the use of the release film 3 and the hole filling of the conductive paste 5 can effectively control the content of the conductive paste 5, improve product quality, and thereby improve reliability.
  • step S6 the plurality of copper foil substrates 10 processed in the steps S1 to S5 are sequentially stacked and pressed together to obtain the circuit substrate 100.
  • the respective copper foil circuits 12 of the two adjacent copper foil layers 1 are electrically connected by connecting the conductive paste 5 in the same blind hole 4 or two stacked blind holes 4 respectively.
  • the conductive paste 5 is used to fill the blind holes 4 to simplify the manufacturing process, the process is simple and the interconnection between any number of layers is realized, the physical space for wiring is increased, and more complicated printed circuits are realized. Products provide support.
  • a plurality of the copper foil substrates 10 are laminated to obtain the circuit substrate 100 at a time.
  • the use of a one-time pressing process after lamination is conducive to the mechanical stability of the product, thereby improving reliability.
  • the present invention also provides a circuit board 100, which is made by the circuit board preparation method.
  • the copper foil layer of the copper foil substrate is etched through step S1 to obtain the copper foil circuit; step S2, the insulating dielectric layer of the copper foil substrate is far away from the copper One side of the foil layer is attached and fixed with a release film; step S3, the laser copper foil substrate is formed to form a blind hole successively penetrating the release film and the insulating dielectric layer; step S4, the blind hole of the copper foil substrate is filled with conductive paste and Make the conductive paste flush with the release film; step S5, remove the release film; step S6, sequentially stack and press a plurality of copper foil substrates processed in steps S1 to S5 to obtain a circuit substrate.
  • the use of conductive paste to fill the blind holes can simplify the production process, the process is simple and the interconnection between any number of layers is realized, the physical space for wiring is increased, and the realization of more complex printed circuit products provides support.
  • the use of release film and conductive paste to fill the holes can effectively control the content of conductive paste, improve product quality, and improve reliability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明提供一种电路基板制备方法，该方法包括如下步骤:步骤S1、对铜箔基板的铜箔层进行蚀刻以获得铜箔线路；步骤S2、对铜箔基板的绝缘介质层远离铜箔层一侧贴合固定一层离型膜；步骤S3、镭射铜箔基板以形成依次贯穿离型膜和绝缘介质层的盲孔；步骤S4、对铜箔基板的盲孔填入导电膏并使该导电膏平齐所述离型膜；步骤S5、移除离型膜；步骤S6、将经过步骤S1至S5处理后的多个铜箔基板依次叠设并压合以获得电路基板。本发明提供一种应用电路基板制备方法制造的电路基板。与相关技术相比，本发明电路基板制备方法和电路板基板的工艺简单且可靠性高。

Description

电路基板制备方法及电路基板 技术领域
本发明涉及电路基板领域，尤其涉及一种的电路基板制备方法和电路基板。
 背景技术
随着近年来电子技术飞速发展，电子产品不断朝着小、轻、薄的方向发展，印制电路板也朝着小型轻量化和高密度化发展。而实现更高密度电路板的电路基板的层与层互连的一个关键工艺是微孔化，即连接电路基板的层与层之间的微孔加工。导电膏具有良好的加工性和导电效果，将其引入到电路基板的微孔内，形成导电膏塞微孔结构，可提高印制电路板孔互连设计的灵活性，为实现功能复杂的印制电路产品提供支持。
目前，相关技术的导电膏塞微孔工艺具体为：镭射电路基板的盲孔后，再通过等离子处理将孔底的胶渣去除，再通过印刷铜膏填孔，再将填孔后的电路基板压合来实现层与层之间的导通。
 技术问题
然而，目前由于导电膏技术不成熟，现有技术不能准确控制铜膏量，具体为：在微孔塞铜膏，铜膏量如果太薄，太薄则出现难以实现层与层之间的电气导通的风险。另外铜膏如果过厚，则出现铜膏残留较多，并容易造成电路基板的多层板结合力不合格，从而产生电路基板可靠性的问题、从而使产品出现品质缺陷。
因此，有必要提供一种新的电路基板制备方法和电路基板解决上述问题。
 技术解决方案
本发明需要解决的技术问题是提供一种工艺简单且可靠性高的电路基板制备方法和电路基板。
为解决上述技术问题，本发明提供一种电路基板制备方法，所述电路基板包括多层铜箔基板，所述铜箔基板包括绝缘介质层和覆于所述绝缘介质层一侧表面的铜箔层，该方法包括如下步骤: 步骤S1、对所述铜箔基板的所述铜箔层进行蚀刻以获得铜箔线路；步骤S2、对所述铜箔基板的所述绝缘介质层远离所述铜箔层一侧贴合固定一层离型膜；步骤S3、镭射所述铜箔基板以形成依次贯穿所述离型膜和所述绝缘介质层的盲孔；所述盲孔与所述铜箔层连接；步骤S4、对所述铜箔基板的所述盲孔填入导电膏并使该导电膏平齐所述离型膜；步骤S5、移除所述离型膜；步骤S6、将经过所述步骤S1至S5处理后的多个所述铜箔基板依次叠设并压合以获得所述电路基板；相邻两所述铜箔层的各自的所述铜箔线路通过分别连接同一个所述盲孔或叠置的两个所述盲孔内的所述导电膏电连接。
更优的，所述步骤S4之前还包括：步骤S40、采用等离子处理所述离型膜和所述盲孔以清洁所述铜箔基板。
更优的，所述离型膜的厚度为25微米。
更优的，所述步骤S2中，所述离型膜与所述绝缘介质层通过一层厚度为3微米的胶层贴合固定。
更优的，所述离型膜与所述绝缘介质层通过压膜机在温度为100℃和压力为7kg条件下压合固定。
更优的，所述导电膏为铜膏。
更优的，所述步骤S6中，多个所述铜箔基板通过一次性压合获得所述电路基板。
本发明还提供一种电路基板，所述电路基板由所述电路基板制备方法制成。
 有益效果
与相关技术相比，本发明的电路基板制备方法和电路基板中通过步骤S1、对铜箔基板的铜箔层进行蚀刻以获得铜箔线路；步骤S2、对铜箔基板的绝缘介质层远离铜箔层一侧贴合固定一层离型膜；步骤S3、镭射铜箔基板以形成依次贯穿离型膜和绝缘介质层的盲孔；步骤S4、对铜箔基板的盲孔填入导电膏并使该导电膏平齐所述离型膜；步骤S5、移除离型膜；步骤S6、将经过步骤S1至S5处理后的多个铜箔基板依次叠设并压合以获得电路基板。该过程采用导电膏在盲孔内填孔可以简化制作流程，工艺简单并实现任意层数之间的互连，增加布线物理空间，为实现更多功能复杂的印制电路产品提供支持。另外，采用离型膜配合导电膏的填孔，可以有效的控制导电膏的含量，提升产品品质，从而提高可靠性。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1为本发明电路基板制备方法的流程框图；
图2为本发明电路基板制备方法的步骤S1的示意图；
图3为本发明电路基板制备方法的步骤S2的示意图；
图4为本发明电路基板制备方法的步骤S3的示意图；
图5为本发明电路基板制备方法的步骤S40的示意图；
图6为本发明电路基板制备方法的步骤S4的示意图；
图7为本发明电路基板制备方法的步骤S5的示意图；
图8为本发明电路基板制备方法的步骤S6中两个所述铜箔基板压合的示意图；
[根据细则91更正 16.09.2020]　
图9为本发明电路基板制备方法的步骤S6中所述电路基板的示意图。
图10为本发明电路基板制备方法的步骤S40的流程框图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
[根据细则91更正 16.09.2020]　
请同时参阅图1-10，本发明提供一种电路基板制备方法。该方法用于制备电路基板100。所述电路基板100包括多层铜箔基板10。
本实施方式中，所述铜箔基板10为液晶聚合物制成的。液晶聚合物（英文为LIQUID CRYSTAL POLYMER，简称LCP），液晶聚合物是一种新型的高分子材料并能经受表面装配技术中使用的气相焊接和红外焊接，可以用于电子电气，因为电子电气的表面装配焊接技术对材料的尺寸稳定性和耐热性有很高的要求。具体应用于印刷电路板。
具体的，所述铜箔基板10包括铜箔层1绝缘介质层2。其中，所述铜箔层1覆于所述绝缘介质层2一侧表面。
所述电路基板制备方法包括如下步骤:
步骤S1、对所述铜箔基板10的所述铜箔层1进行蚀刻以获得铜箔线路12及铜箔线路间隙11。
步骤S2、对所述铜箔基板10的所述绝缘介质层2远离所述铜箔层1一侧贴合固定一层离型膜3。
在本步骤S2中，所述离型膜3与所述绝缘介质层2通过一层厚度为3微米的胶层6固定。所述胶层6的厚度较小，可以在保证粘合力的同时不影响铜膏塞孔厚度。
本实施方式中，所述离型膜3与所述绝缘介质层2通过压膜机在温度为100℃和压力为7kg条件下压合固定。其中，所述压膜机可以选择手动压膜机。通过该条件的压合固定，所述离型膜3避免在压膜过程中产生气泡，有利于提高可靠性。
步骤S3、镭射所述铜箔基板10以形成依次贯穿所述离型膜3和所述绝缘介质层2的盲孔4。所述盲孔4用于实现相邻的两层所述铜箔线路12的导电。
其中，所述盲孔4与所述铜箔层1连接。
本实施方式中，为了更好实现后续的工艺，需要对所述铜箔基板10进行清理干净。具体的，所述电路基板制备方法还包括：步骤S40、采用等离子处理所述离型膜3和所述盲孔4以清洁所述铜箔基板10。
在所述步骤S3中，镭射处理在所述离型膜3的表面和所述盲孔4内残留一下胶块等杂质7。由于所述盲孔4的孔径较小，采用等离子处理可以将较小的所述杂质7清除干净，有利于后续所述盲孔4填充导电物质。
步骤S4、对所述铜箔基板10的所述盲孔4填入导电膏5并使该导电膏平齐所述离型膜。
本实施方式中，所述导电膏5为铜膏。铜膏具有良好的导电性能。其中，将采用印刷铜膏方式将所述导电膏5填充入所述盲孔4内。采用所述导电膏5代替电镀进行填孔，可以简化制作流程，从而使工艺简单。
步骤S5、移除所述离型膜3。
本实施方式中，所述离型膜3的厚度为25微米。多一层所述离型膜3的厚度使得所述导电膏5的富余量满足不会出现因压合后所述导电膏5的膏量紧实变少造成的层与层之间断路，另所述离型膜3的厚度较薄不会造成所述导电膏5残留较厚而出现产品的品质缺陷。采用所述离型膜3配合所述导电膏5的填孔，可以有效的控制所述导电膏5的含量，提升产品品质，从而提高可靠性。
步骤S6、将经过所述步骤S1至S5处理后的多个所述铜箔基板10依次叠设并压合以获得所述电路基板100。
相邻两所述铜箔层1的各自的所述铜箔线路12通过分别连接同一个所述盲孔4或叠置的两个所述盲孔4内的所述导电膏5电连接。该过程采用所述导电膏5在所述盲孔4内填孔可以简化制作流程，工艺简单并实现任意层数之间的互连，增加布线物理空间，为实现更多功能复杂的印制电路产品提供支持。
本实施方式中，多个所述铜箔基板10通过一次性压合获得所述电路基板100。采用叠层后一次性压合的加工工艺，有利于产品的机械稳定性，从而提高可靠性。
本发明还提供一种电路基板100，所述电路板基板100由所述电路基板制备方法制成。
与相关技术相比，本发明的电路基板制备方法和电路基板中通过步骤S1、对铜箔基板的铜箔层进行蚀刻以获得铜箔线路；步骤S2、对铜箔基板的绝缘介质层远离铜箔层一侧贴合固定一层离型膜；步骤S3、镭射铜箔基板以形成依次贯穿离型膜和绝缘介质层的盲孔；步骤S4、对铜箔基板的盲孔填入导电膏并使该导电膏平齐所述离型膜；步骤S5、移除离型膜；步骤S6、将经过步骤S1至S5处理后的多个铜箔基板依次叠设并压合以获得电路基板。该过程采用导电膏在盲孔内填孔可以简化制作流程，工艺简单并实现任意层数之间的互连，增加布线物理空间，为实现更多功能复杂的印制电路产品提供支持。另外，采用离型膜配合导电膏的填孔，可以有效的控制导电膏的含量，提升产品品质，从而提高可靠性。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (8)

  1. 一种电路基板制备方法，所述电路基板包括多层铜箔基板，所述铜箔基板包括绝缘介质层和覆于所述绝缘介质层一侧表面的铜箔层，其特征在于，该方法包括如下步骤:
    步骤S1、对所述铜箔基板的所述铜箔层进行蚀刻以获得铜箔线路；
    步骤S2、对所述铜箔基板的所述绝缘介质层远离所述铜箔层一侧贴合固定一层离型膜；
    步骤S3、镭射所述铜箔基板以形成依次贯穿所述离型膜和所述绝缘介质层的盲孔；所述盲孔与所述铜箔层连接；
    步骤S4、对所述铜箔基板的所述盲孔填入导电膏并使该导电膏平齐所述离型膜；
    步骤S5、移除所述离型膜；
    步骤S6、将经过所述步骤S1至S5处理后的多个所述铜箔基板依次叠设并压合以获得所述电路基板；相邻两所述铜箔层的各自的所述铜箔线路通过分别连接同一个所述盲孔或叠置的两个所述盲孔内的所述导电膏电连接。
  2. 根据权利要求1所述的电路基板制备方法，其特征在于，所述步骤S4之前还包括：步骤S40、采用等离子处理所述离型膜和所述盲孔以清洁所述铜箔基板。
  3. 根据权利要求1所述的电路基板制备方法，其特征在于，所述离型膜的厚度为25微米。
  4. 根据权利要求3所述的电路基板制备方法，其特征在于，所述步骤S2中，所述离型膜与所述绝缘介质层通过一层厚度为3微米的胶层贴合固定。
  5. 根据权利要求4所述的电路基板制备方法，其特征在于，所述离型膜与所述绝缘介质层通过压膜机在温度为100℃和压力为7kg条件下压合固定。
  6. 根据权利要求1所述的电路基板制备方法，其特征在于，所述导电膏为铜膏。
  7. 根据权利要求1所述的电路基板制备方法，其特征在于，所述步骤S6中，多个所述铜箔基板通过一次性压合获得所述电路基板。
  8. 一种电路基板，其特征在于，所述电路基板由权利要求1-7中任意一种所述电路基板制备方法制成。
PCT/CN2020/101272 2020-06-08 2020-07-10 电路基板制备方法及电路基板 Ceased WO2021248612A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010514391.4 2020-06-08
CN202010514391.4A CN111836469A (zh) 2020-06-08 2020-06-08 电路基板制备方法及电路基板

Publications (1)

Publication Number Publication Date
WO2021248612A1 true WO2021248612A1 (zh) 2021-12-16

Family

ID=72898574

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/101272 Ceased WO2021248612A1 (zh) 2020-06-08 2020-07-10 电路基板制备方法及电路基板

Country Status (2)

Country Link
CN (1) CN111836469A (zh)
WO (1) WO2021248612A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114554681A (zh) * 2022-03-28 2022-05-27 黄石永兴隆电子有限公司 一种含有阶梯型盲孔的线路板

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115776775A (zh) * 2021-09-07 2023-03-10 深南电路股份有限公司 一种印制电路板及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5979044A (en) * 1997-03-24 1999-11-09 Nec Corporation Fabrication method of multilayer printed wiring board
CN1464767A (zh) * 2002-06-24 2003-12-31 威盛电子股份有限公司 用印刷方式制作电路基板导通孔及线路的方法
CN102595799A (zh) * 2011-12-30 2012-07-18 柏承科技(昆山)股份有限公司 高密度互联印刷电路板的制造方法
CN103281878A (zh) * 2013-06-13 2013-09-04 汕头超声印制板（二厂）有限公司 一种贯穿过孔印制电路板的制作方法
CN103582321A (zh) * 2012-07-19 2014-02-12 富葵精密组件(深圳)有限公司 多层线路板及其制作方法
CN103717013A (zh) * 2012-09-29 2014-04-09 上海美维科技有限公司 一种印制电路板的制造方法
CN103841771A (zh) * 2012-11-26 2014-06-04 北大方正集团有限公司 组合印制电路板和印制电路板的制造方法以及印制电路板
CN104349610A (zh) * 2013-07-24 2015-02-11 北大方正集团有限公司 印制电路板子板及印制电路板的制造方法和印制电路板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101043540B1 (ko) * 2009-10-01 2011-06-21 삼성전기주식회사 인쇄회로기판의 제조방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5979044A (en) * 1997-03-24 1999-11-09 Nec Corporation Fabrication method of multilayer printed wiring board
CN1464767A (zh) * 2002-06-24 2003-12-31 威盛电子股份有限公司 用印刷方式制作电路基板导通孔及线路的方法
CN102595799A (zh) * 2011-12-30 2012-07-18 柏承科技(昆山)股份有限公司 高密度互联印刷电路板的制造方法
CN103582321A (zh) * 2012-07-19 2014-02-12 富葵精密组件(深圳)有限公司 多层线路板及其制作方法
CN103717013A (zh) * 2012-09-29 2014-04-09 上海美维科技有限公司 一种印制电路板的制造方法
CN103841771A (zh) * 2012-11-26 2014-06-04 北大方正集团有限公司 组合印制电路板和印制电路板的制造方法以及印制电路板
CN103281878A (zh) * 2013-06-13 2013-09-04 汕头超声印制板（二厂）有限公司 一种贯穿过孔印制电路板的制作方法
CN104349610A (zh) * 2013-07-24 2015-02-11 北大方正集团有限公司 印制电路板子板及印制电路板的制造方法和印制电路板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114554681A (zh) * 2022-03-28 2022-05-27 黄石永兴隆电子有限公司 一种含有阶梯型盲孔的线路板
CN114554681B (zh) * 2022-03-28 2024-04-12 黄石永兴隆电子有限公司 一种含有阶梯型盲孔的线路板

Also Published As

Publication number Publication date
CN111836469A (zh) 2020-10-27

Similar Documents

Publication Publication Date Title
TWI621388B (zh) Method for manufacturing multilayer printed wiring board and multilayer printed wiring board
WO2017107535A1 (zh) 刚挠结合板及其制备方法
TW201427510A (zh) 具有內埋元件的電路板及其製作方法
US20160135295A1 (en) Multi-layer circuit board
CN113163622B (zh) 一种超薄软硬结合板的热塑聚酰亚胺减法工艺
CN103260350A (zh) 盲埋孔板压合方法及其采用该压合方法制得的盲埋孔板
CN103379751A (zh) 组合印制电路板的制造方法、印制电路板及其制造方法
CN103379750A (zh) 多层电路板及其制作方法
CN115472510A (zh) 嵌埋器件封装基板及其制作方法
CN106340461A (zh) 一种超薄无芯封装基板的加工方法和结构
WO2015141004A1 (ja) 多層回路基板、半導体装置、及びその多層回路基板の製造方法
WO2021248612A1 (zh) 电路基板制备方法及电路基板
CN107484323A (zh) 多层柔性电路板及其制作方法
TW201427524A (zh) 可撓折的電路板及其製作方法
CN115915649A (zh) 多层电路板及其制作方法
TWI519225B (zh) 多層軟性線路結構的製作方法
KR20150083424A (ko) 배선 기판의 제조 방법
CN111629527A (zh) 一种柔性电路板的制作方法及其柔性电路板
CN114007345A (zh) 线路板的制备方法
CN104284530A (zh) 无芯板工艺制作印制电路板或集成电路封装基板的方法
TW201406223A (zh) 多層線路板及其製作方法
CN119155924A (zh) 一种bga区域平整度pcb及其制备方法
CN101022695B (zh) 线路嵌合于介电层的无芯板薄型基板及其制造方法
TW201427505A (zh) 具有內埋元件的電路板及其製作方法
TWI519224B (zh) 多層軟性線路結構的製作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20939967

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20939967

Country of ref document: EP

Kind code of ref document: A1