WO2021248566A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2021248566A1
WO2021248566A1 PCT/CN2020/097937 CN2020097937W WO2021248566A1 WO 2021248566 A1 WO2021248566 A1 WO 2021248566A1 CN 2020097937 W CN2020097937 W CN 2020097937W WO 2021248566 A1 WO2021248566 A1 WO 2021248566A1
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WIPO (PCT)
Prior art keywords
transistor
signal
gate
source
liquid crystal
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PCT/CN2020/097937
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English (en)
French (fr)
Inventor
曹海明
管延庆
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武汉华星光电技术有限公司
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Priority to US16/970,642 priority Critical patent/US11257456B2/en
Publication of WO2021248566A1 publication Critical patent/WO2021248566A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel

Definitions

  • This application relates to the field of display technology, and in particular to a pixel drive circuit and a display panel.
  • the current display technology requirements are applicable to both high frequency and low frequency, so that the display panel not only has the advantages of smooth picture quality brought by high frequency, but also has the advantage of low power consumption brought by low frequency. Therefore, dynamic frame rate technology Came into being, this technology can adjust the refresh frequency of the display panel in real time, thereby satisfying both ultra-low frequency and ultra-high frequency display requirements.
  • the display panel For low-frequency display requirements, since the holding time of each frame of the low-frequency state is extended to several tens of times the original, the display panel is required to have strong image retention capabilities; for high-frequency display requirements, due to the extremely short charging time of each row of pixels, Therefore, the display panel needs to have a strong charging capability, and if a high refresh rate is used to display static or low-speed object images, it will cause the problem of excessive logic power consumption of the display panel.
  • LTPS low-temperature polysilicon
  • IGZO indium gallium zinc oxide
  • FIG. 1 is a diagram of a pixel driving circuit of an existing 1T2C structure.
  • the circuit includes a driving switch T10, a storage capacitor Cst, and a liquid crystal capacitor Clc.
  • the gate input of the driving switch T10 is the current row gate line output signal G (N)
  • the drain is electrically connected to one end of the storage capacitor Cst and the liquid crystal capacitor Clc
  • the source is electrically connected to the data line.
  • the current row gate line output signal G(n) is sent to the signal to control the switch of the drive switch T10.
  • T10 When T10 is turned on, the data line charges the liquid crystal capacitor Clc and the storage capacitor Cst to the required voltage, and then T10 is turned off, and the storage capacitor Cst is discharged.
  • the voltage of the liquid crystal capacitor Clc is maintained until the next update.
  • the 1T2C circuit works, because the drive switch T10 can only be a single type of TFT, and each TFT has its advantages and disadvantages, the 1T2C circuit is not suitable for the needs of dynamic frame rate technology, so it is necessary to design a new pixel driver The circuit is suitable for dynamic frame rate technology.
  • the present application provides a pixel driving circuit and a display panel to solve the problem that the current traditional 1T2C circuit is not suitable for the demand of dynamic frame rate technology.
  • the present application provides a pixel driving circuit, the circuit includes: a first transistor, a second transistor, a liquid crystal capacitor, and a storage capacitor; the first transistor and the second transistor each include a source and a gate. And the drain, the liquid crystal capacitor and the storage capacitor each include a first terminal and a second terminal.
  • the drain of the first transistor is electrically connected to the first end of the liquid crystal capacitor and the first end of the storage capacitor
  • the drain of the second transistor is electrically connected to the first end of the liquid crystal capacitor.
  • Two ends and the second end of the storage capacitor; the gate of the first transistor is connected to a normal signal, the source is connected to a common signal, and the gate of the second transistor is connected to a line scan signal, and the source is connected to Or, the gate of the first transistor is connected to a line scan signal, the source is connected to a data signal, and the gate of the second transistor is connected to a normal signal, and the source is connected to a common signal.
  • the first transistor is a low-temperature polysilicon thin film transistor
  • the second transistor is an oxide semiconductor thin film transistor
  • the gate of the first transistor is connected to a first normal signal, the source is connected to a common signal, and the drain is electrically connected to the first end of the liquid crystal capacitor and the first end of the storage capacitor, and the second The gates of the two transistors are connected to the row scan signal, the source is connected to the data signal, and the drains are respectively electrically connected to the second end of the liquid crystal capacitor and the second end of the storage capacitor.
  • the gate of the first transistor is connected to a row scan signal, the source is connected to a data signal, and the drain is electrically connected to the first end of the liquid crystal capacitor and the first end of the storage capacitor, respectively.
  • the gate of the second transistor is connected to the second normal signal, the source is connected to the common signal, and the drain is electrically connected to the second end of the liquid crystal capacitor and the second end of the storage capacitor, respectively.
  • the first transistor when the pixel driving circuit is working in a low frequency state, the first transistor is turned off and the second transistor is turned on; when the pixel driving circuit is working in a high frequency state, the first transistor Turn on and turn off the second transistor.
  • the first normal signal is a high-level signal; if the first transistor is a P-type thin film transistor, the first normal signal is It is a low-level signal.
  • the second normal signal is a high-level signal; if the second transistor is a P-type thin film transistor, the second normal signal is It is a low-level signal.
  • the row scan signal is generated by the GOA circuit or the gate chip gate IC generation.
  • the data signal is generated by an external clock control chip.
  • the refresh frequency corresponding to the low frequency state includes an ultra low frequency of 1 to 5 Hz
  • the refresh frequency corresponding to the high frequency state includes an ultra high frequency of 120 to 360 Hz.
  • the present application also provides a display panel, including a pixel driving circuit, the pixel driving circuit includes: a first transistor, a second transistor, a liquid crystal capacitor, and a storage capacitor; the first transistor and the second transistor are both Each includes a source, a gate, and a drain.
  • the liquid crystal capacitor and the storage capacitor each include a first terminal and a second terminal.
  • the drain of the first transistor is respectively electrically connected to the first end of the liquid crystal capacitor and the first end of the storage capacitor
  • the drain of the second transistor is respectively electrically connected to the second end of the liquid crystal capacitor And the second end of the storage capacitor.
  • the gate of the first transistor is connected to a normal signal, the source is connected to a common signal, and the gate of the second transistor is connected to a line scan signal, and the source is connected to a data signal; or
  • the gate is connected to a line scan signal, the source is connected to a data signal, the gate of the second transistor is connected to a normal signal, and the source is connected to a common signal.
  • the first transistor is a low temperature polysilicon thin film transistor
  • the second transistor is an oxide semiconductor thin film transistor
  • the gate of the first transistor is connected to a first normal signal, the source is connected to a common signal, and the drain is electrically connected to the first end of the liquid crystal capacitor and the first end of the storage capacitor, respectively.
  • the gate of the second transistor is connected to a row scan signal, the source is connected to a data signal, and the drain is electrically connected to the second end of the liquid crystal capacitor and the second end of the storage capacitor, respectively.
  • the gate of the first transistor is connected to a row scan signal, the source is connected to a data signal, and the drain is electrically connected to the first end of the liquid crystal capacitor and the first end of the storage capacitor, respectively;
  • the gate of the second transistor is connected to a second normal signal, the source is connected to a common signal, and the drain is electrically connected to the second end of the liquid crystal capacitor and the second end of the storage capacitor, respectively.
  • the first transistor when the pixel driving circuit is working in a low frequency state, the first transistor is turned off and the second transistor is turned on; when the pixel driving circuit is working in a high frequency state, the first transistor Turn on and turn off the second transistor.
  • the first normal signal is a high-level signal; if the first transistor is a P-type thin film transistor, the first normal signal is It is a low-level signal.
  • the second normal signal is a high-level signal; if the second transistor is a P-type thin film transistor, the second normal signal is It is a low-level signal.
  • the row scan signal is generated by a GOA circuit or a gate-on-chip film.
  • the data signal is generated by an external clock control chip.
  • the refresh frequency corresponding to the low frequency state includes an ultra low frequency of 1 to 5 Hz
  • the refresh frequency corresponding to the high frequency state includes an ultra high frequency of 120 to 360 Hz.
  • the pixel drive circuit adopts a 2T2C circuit structure, and controls the first transistor T1 or the second transistor T2 to keep normally open through a normal signal, and connect one of the normally open transistors to the common terminal, And another transistor is connected to the row scan signal and the data signal as a drive switch to charge the liquid crystal capacitor and the storage capacitor. Therefore, the first transistor T1 and the second transistor T2 can alternately work when the pixel driving circuit is at a low frequency or a high frequency, so as to meet different working requirements.
  • FIG. 1 is a diagram of a pixel driving circuit with a conventional 1T2C structure.
  • FIG. 2 is a pixel driving circuit with a 2T2C structure according to an embodiment of the present application.
  • FIG. 3 shows the connection relationship of the pixel driving circuit of the 2T2C structure in the embodiment of the present application at low frequency.
  • FIG. 4 shows the connection relationship of the pixel driving circuit of the 2T2C structure in the embodiment of the present application at high frequency.
  • the two electrodes other than the gate of the transistor are distinguished, and one of the electrodes is called the source and the other is called the drain. Since the source and drain of the transistor are symmetrical, the source and drain are interchangeable. According to the form in the figure, it is stipulated that the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the transistors used in all the embodiments of the present application may include P-type and/or N-type transistors. Among them, the P-type transistor is turned on when the gate is at a low potential and turned off when the gate is at a high potential; and the N-type transistor is at the gate. It turns on when the potential is high, and turns off when the gate is low.
  • FIG. 2 is a pixel driving circuit with a 2T2C structure according to an embodiment of the present application.
  • the pixel driving circuit includes: a first transistor T1, a second transistor T2, a liquid crystal capacitor Clc, and a storage capacitor Cst;
  • the transistors T2 each include a source, a gate, and a drain, and the liquid crystal capacitor Clc and the storage capacitor Cst each include a first terminal D1 and a second terminal D2.
  • the drain of the first transistor T1 is electrically connected to the first terminal D1 of the liquid crystal capacitor Clc and the first terminal D1 of the storage capacitor Cst
  • the drain of the second transistor T2 is electrically connected to the second terminal D2 of the liquid crystal capacitor Clc. And the second terminal D2 of the storage capacitor Cst.
  • the gate of the first transistor T1 is connected to the normal signal Gn (not shown in the figure, the following embodiments are represented by the first normal signal Gn1 or the second normal signal Gn2), the source is connected to the common signal Com, and the second The gate of the transistor T2 is connected to the row scan signal Kn, and the source is connected to the data signal Data; or, the gate of the first transistor T1 is connected to the row scan signal Kn, the source is connected to the data signal Data, and the second transistor T2 The gate is connected to the normal signal Gn, and the source is connected to the common signal Com.
  • the pixel driving circuit provided by the embodiment of the present application adopts a 2T2C circuit structure.
  • the first transistor T1 or the second transistor T2 is controlled to be kept normally on through the normal signal Gn, and a transistor whose gate is connected to the normal signal Gn and normally open is connected to Common signal Com, and another transistor is connected to the row scan signal Kn and the data signal Data as a drive switch, so as to charge the liquid crystal capacitor Clc and the storage capacitor Cst, so that the first transistor T1 and the second transistor T2 make the
  • the pixel drive circuit can alternately work at low frequency or high frequency to meet different working requirements.
  • first transistor T1 and the second transistor T2 can be different types of thin film transistors.
  • the embodiment of the present application uses the first transistor T1 A low-temperature polysilicon thin film transistor LTPS is used, and the second transistor T2 is an oxide semiconductor thin film transistor IGZO.
  • the first transistor T1 adopts a low-temperature polysilicon thin film transistor
  • the second transistor T2 adopts an oxide semiconductor thin film transistor. The specific process of applying the pixel driving circuit to a low-frequency working state or a high-frequency working state will be described in detail.
  • FIG. 3 is the connection relationship of the pixel driving circuit of the 2T2C structure in the embodiment of the present application at low frequency.
  • the gate of the first transistor T1 is connected to the first normal signal Gn1
  • the source is connected to the common signal Com
  • the drain is respectively electrically connected to the first terminal D1 of the liquid crystal capacitor Clc and the first terminal D1 of the storage capacitor Cst
  • the gate of the second transistor T2 is connected to the horizontal scanning signal
  • the source is connected to The data signal is input
  • the drain is electrically connected to the second terminal D2 of the liquid crystal capacitor Clc and the second terminal D2 of the storage capacitor Cst, respectively.
  • the first transistor T1 When the pixel driving circuit works in a low frequency state, the first transistor T1 is always on. It can be understood that if the first transistor T1 is an N-type thin film transistor, the first normal signal Gn1 is a high-level signal; if the first transistor T1 is a P-type thin film transistor, the first normal signal Gn1 is a low-level signal . Here, it is taken as an example that the first transistor T1 is an N-type thin film transistor.
  • the second transistor T2 is a drive switch responsible for writing data signals
  • the first transistor T1 is a normally open switch responsible for maintaining the common terminal level of point D1, that is, the gate of the second transistor T2 is connected to the row scan signal, and the source The pole is connected to the data signal, the gate of the first transistor T1 is connected to the first normal signal Gn1, and the source is connected to the common signal Com.
  • the pixel driving circuit charges the storage capacitor Cst and the liquid crystal capacitor Clc to write data through the leakage of the second transistor T2, and since the second transistor T2 adopts the oxide semiconductor thin film transistor IGZO, its leakage current Ioff is relatively small. It solves the problem of insufficient picture retention ability at low frequencies.
  • FIG. 4 shows the connection relationship of the pixel driving circuit of the 2T2C structure of the embodiment of the present application at high frequency.
  • the gate of the first transistor T1 is connected to the row scanning signal Kn
  • the source is connected to the data signal Data
  • the drain is respectively electrically connected to the first terminal D1 of the liquid crystal capacitor Clc and the first terminal D1 of the storage capacitor Cst
  • the gate of the second transistor T2 is connected to the second normal signal Gn2
  • the source The poles are connected to the common signal Com
  • the drains are respectively electrically connected to the second end D2 of the liquid crystal capacitor Clc and the second end D2 of the storage capacitor Cst.
  • the second transistor T2 When the pixel driving circuit works in a high frequency state, the second transistor T2 is normally on. It can also be understood that if the second transistor T2 is an N-type thin film transistor, the second normal signal Gn2 is a high-level signal; if the second transistor T2 is a P-type thin film transistor, the second normal signal Gn2 is a low-level signal. Signal. Here, it is also taken as an example that the second transistor T2 is an N-type thin film transistor.
  • the first transistor T1 is a drive switch responsible for writing the data signal Data
  • the second transistor T2 is a normally open switch responsible for maintaining the common terminal level of point D2, that is, the gate of the first transistor T1 is connected to the row scan signal Kn ,
  • the source is connected to the data signal Data
  • the gate of the second transistor T2 is connected to the second normal signal Gn2, and the source is connected to the common signal Com.
  • the pixel driving circuit charges the storage capacitor Cst and the liquid crystal capacitor Clc to write data through the leakage of the first transistor T1, and the first transistor T1 uses a low-temperature polysilicon thin film transistor LTPS, which has high mobility and strong charging ability , It better solves the problem of insufficient charging capacity at high frequency.
  • the pixel drive circuit adopts the circuit structure of 2T2C, which can switch the connection relationship between the first transistor T1 and the second transistor T2 in the circuit and the external scan line and data line separately for the low frequency state and the high frequency state, so that the connection relationship between the external scan line and the data line can be
  • the second transistor T2 is used to write data in the oxide semiconductor thin film transistor IGZO
  • the first transistor T1 is used to write data in the low temperature polysilicon thin film transistor LTPS, so that the oxide semiconductor thin film can be used in the low frequency state.
  • Transistor IGZO has the advantages of low leakage current and low leakage current loff, so it is more power-saving and has a stronger picture retention ability.
  • low temperature polysilicon thin film transistor LTPS With too high leakage current Ioff and poor picture retention ability, and it is used in high frequency state.
  • the advantages of low-temperature polysilicon thin-film transistor LTPS have higher mobility and stronger charging ability, avoiding the disadvantages of oxide semiconductor thin-film transistor IGZO with lower mobility and weak charging ability.
  • the embodiment of the application can alternately work between low frequency and high frequency states.
  • the low-temperature polysilicon thin film transistor LTPS has a higher mobility as the driving switch
  • the oxide semiconductor thin film transistor IGZO is used for low leakage current.
  • the small Ioff feature is used as a drive switch, thereby solving the problems of insufficient high-frequency charging and serious low-frequency leakage to meet the requirements of dynamic frame rate technology.
  • the line scan signal is generated by the GOA circuit or the gate IC; the data signal is generated by the external clock control chip.
  • the refresh frequency corresponding to the low frequency state includes the ultra-low frequency of 1 to 5 Hz
  • the refresh frequency corresponding to the high frequency state includes the ultra-high frequency of 120 to 360 Hz to meet the requirements of dynamic frame rate technology.
  • An embodiment of the present application also provides a display panel including the pixel driving circuit as described above, and the display panel has the same structure and beneficial effects as the pixel driving circuit provided in the foregoing embodiments. Since the foregoing embodiment has described the structure and beneficial effects of the pixel driving circuit in detail, it will not be repeated here.

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Abstract

像素驱动电路及显示面板，像素驱动电路控制第一晶体管(T1)或第二晶体管(T2)保持常开，常开的一个晶体管连接公共端，另一个晶体管接入行扫描信号(Kn)和数据信号(Data)作为驱动开关，从而对液晶电容(Clc)和存储电容(Cst)进行充电，由此通过第一晶体管(T1)和第二晶体管(T2)可使像素驱动电路在低频或高频时交替工作，以满足不同的工作需求。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路及显示面板。
 背景技术
目前的显示技术要求同时适用于高频和低频的情况，以使显示面板不仅具有高频带来的画质流畅的优点，还具有低频带来的低功耗的优点，因此，动态帧频技术应运而生，该技术可以实时调节显示面板的刷新频率，由此同时满足超低频和超高频的显示需求。对于低频的显示需求，由于低频状态每帧画面的holding时间延长为原先的数十倍，因此要求显示面板的画面保持能力强；对于高频的显示需求，由于每行像素的充电时间极短，因此需要显示面板的充电能力强，并且，如果用高刷新率显示静止或速度较低的物体影像，反而会造成显示面板逻辑功耗过高的问题。
传统的背板技术有A-Si、LTPS、IGZO技术，与a-Si(非晶硅）技术相比，LTPS（低温多晶硅）和IGZO（氧化铟镓锌）两种技术由于迁移率较高而被广泛应用。其中，由于LTPS技术比IGZO技术的迁移率更高、器件所占面积更小，因此充电能力更强，更适合于高频时的应用；而IGZO技术比LTPS技术的均匀性更好、漏电流较小，因此更加省电、画面保持（holding）能力更强，更适合于低频时的应用。可以理解的是，传统的背板技术由于技术的单一性，导致性能优点的单一性，无法满足动态帧频的需求。
参考图1，图1为现有的1T2C结构的像素驱动电路图，该电路包括驱动开关T10、存储电容Cst、液晶电容Clc，其中，驱动开关T10的栅极的输入为当前行栅线输出信号G（n），漏极与存储电容Cst和液晶电容Clc的一端电性连接，源极与数据线电性连接。当前行栅线输出信号G（n）送入信号控制驱动开关T10的开关，当T10打开时数据线将液晶电容Clc和存储电容Cst充电到所需要的的电压后T10关闭，存储电容Cst放电来维持液晶电容Clc的电压保持到下一次更新。该1T2C电路工作时，由于驱动开关T10只能是单一类型的TFT，而每种TFT都有其优点和缺点，因此该1T2C电路不适用于动态帧频技术的需求，故需要设计新的像素驱动电路以适用于动态帧频技术。
 技术问题
本申请提供一种像素驱动电路及显示面板，以解决目前传统的1T2C电路不适用于动态帧频技术的需求的问题。
 技术解决方案
第一方面，本申请提供一种像素驱动电路，该电路包括：第一晶体管、第二晶体管、液晶电容和存储电容；所述第一晶体管和所述第二晶体管均分别包括源极、栅极和漏极，所述液晶电容和所述存储电容均分别包括第一端和第二端。
其中，所述第一晶体管的漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端，所述第二晶体管的漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端；所述第一晶体管的栅极接入常态信号，源极接入公共信号，且所述第二晶体管的栅极接入行扫描信号，源极接入数据信号；或者，所述第一晶体管的栅极接入行扫描信号，源极接入数据信号，且所述第二晶体管的栅极接入常态信号，源极接入公共信号。
在一些实施例中，所述第一晶体管为低温多晶硅薄膜晶体管，所述第二晶体管为氧化物半导体薄膜晶体管；
所述第一晶体管的栅极接入第一常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端，并且所述第二晶体管的栅极接入行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
在一些实施例中，所述第一晶体管的栅极连接行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端，并且所述第二晶体管的栅极接入第二常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
在一些实施例中，当所述像素驱动电路工作于低频状态时，所述第一晶体管关闭，所述第二晶体管打开；当所述像素驱动电路工作于高频状态时，所述第一晶体管打开，所述第二晶体管关闭。
在一些实施例中，若所述第一晶体管为N型薄膜晶体管，则所述第一常态信号为高电平信号；若所述第一晶体管为P型薄膜晶体管，则所述第一常态信号为低电平信号。
在一些实施例中，若所述第二晶体管为N型薄膜晶体管，则所述第二常态信号为高电平信号；若所述第二晶体管为P型薄膜晶体管，则所述第二常态信号为低电平信号。
在一些实施例中，所述行扫描信号由GOA电路或栅极覆晶薄膜gate IC生成。
在一些实施例中，所述数据信号由外部时钟控制芯片生成。
在一些实施例中，所述低频状态对应的刷新频率包括1~5Hz的超低频，所述高频状态对应的刷新频率包括120~360Hz的超高频。
第二方面，本申请还提供一种显示面板，包括像素驱动电路，该像素驱动电路包括：第一晶体管、第二晶体管、液晶电容和存储电容；所述第一晶体管和所述第二晶体管均分别包括源极、栅极和漏极，所述液晶电容和所述存储电容均分别包括第一端和第二端。
所述第一晶体管的漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端，所述第二晶体管的漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
所述第一晶体管的栅极接入常态信号，源极接入公共信号，且所述第二晶体管的栅极接入行扫描信号，源极接入数据信号；或者，所述第一晶体管的栅极接入行扫描信号，源极接入数据信号，且所述第二晶体管的栅极接入常态信号，源极接入公共信号。
在一些实施例中，所述第一晶体管为低温多晶硅薄膜晶体管，所述第二晶体管为氧化物半导体薄膜晶体管。
所述第一晶体管的栅极接入第一常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端。
所述第二晶体管的栅极接入行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
在一些实施例中，所述第一晶体管的栅极连接行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端；所述第二晶体管的栅极接入第二常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
在一些实施例中，当所述像素驱动电路工作于低频状态时，所述第一晶体管关闭，所述第二晶体管打开；当所述像素驱动电路工作于高频状态时，所述第一晶体管打开，所述第二晶体管关闭。
在一些实施例中，若所述第一晶体管为N型薄膜晶体管，则所述第一常态信号为高电平信号；若所述第一晶体管为P型薄膜晶体管，则所述第一常态信号为低电平信号。
在一些实施例中，若所述第二晶体管为N型薄膜晶体管，则所述第二常态信号为高电平信号；若所述第二晶体管为P型薄膜晶体管，则所述第二常态信号为低电平信号。
在一些实施例中，所述行扫描信号由GOA电路或栅极覆晶薄膜生成。
在一些实施例中，所述数据信号由外部时钟控制芯片生成。
在一些实施例中，所述低频状态对应的刷新频率包括1~5Hz的超低频，所述高频状态对应的刷新频率包括120~360Hz的超高频。
 有益效果
在本申请提供像素驱动电路和显示面板中，该像素驱动电路采用2T2C的电路结构，通过常态信号控制第一晶体管T1或第二晶体管T2保持常开，将其中常开的一个晶体管连接公共端，而将另一个晶体管接入行扫描信号和数据信号作为驱动开关，从而对液晶电容和存储电容进行充电。由此第一晶体管T1和第二晶体管T2可在像素驱动电路在低频或高频时交替工作，以满足不同的工作需求。
 附图说明
图1为现有的1T2C结构的像素驱动电路图。
图2是本申请实施例的2T2C结构的像素驱动电路。
图3是本申请实施例的2T2C结构的像素驱动电路在低频时的连接关系。
图4是本申请实施例的2T2C结构的像素驱动电路在高频时的连接关系。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请所有实施例为区分晶体管处栅极之外的两极，将其中一极称为源极，另一极称为漏极。由于晶体管的源极和漏极是对称的，因此其源极和漏极是可以互换的。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本申请所有实施例采用的晶体管可以包括P型和/或N型晶体管两种，其中，P型晶体管在栅极为低电位时打开，在栅极为高电位时关闭；N型晶体管在栅极为高电位时打开，在栅极为低电位时关闭。
参考图2，图2是本申请实施例的2T2C结构的像素驱动电路，该像素驱动电路包括：第一晶体管T1、第二晶体管T2、液晶电容Clc和存储电容Cst；第一晶体管T1和第二晶体管T2均分别包括源极、栅极和漏极，液晶电容Clc和存储电容Cst均分别包括第一端D1和第二端D2。
其中，第一晶体管T1的漏极分别电性连接液晶电容Clc的第一端D1和存储电容Cst的第一端D1，第二晶体管T2的漏极分别电性连接液晶电容Clc的第二端D2和存储电容Cst的第二端D2。并且，第一晶体管T1的栅极接入常态信号Gn（图中未示出，以下实施例以第一常态信号Gn1或第二常态信号Gn2表示），源极接入公共信号Com，且第二晶体管T2的栅极接入行扫描信号Kn，源极接入数据信号Data；或者，第一晶体管T1的栅极接入行扫描信号Kn，源极接入数据信号Data，且第二晶体管T2的栅极接入常态信号Gn，源极接入公共信号Com。
本申请实施例提供的像素驱动电路采用2T2C的电路结构，通过常态信号Gn控制第一晶体管T1或第二晶体管T2保持常开，将其中栅极接入常态信号Gn而常开的一个晶体管接入公共信号Com，而将另一个晶体管接入行扫描信号Kn和数据信号Data作为驱动开关，从而对液晶电容Clc和存储电容进Cst行充电，由此通过第一晶体管T1和第二晶体管T2使该像素驱动电路能在低频或高频交替工作，以满足不同的工作需求。
可以理解的是，第一晶体管T1和第二晶体管T2可为不同类型的薄膜晶体管，为了满足动态帧频技术需要同时适用于低频和高频工作状态的需求，本申请实施例将第一晶体管T1采用低温多晶硅薄膜晶体管LTPS，第二晶体管T2采用氧化物半导体薄膜晶体管IGZO。
下面针对第一晶体管T1采用低温多晶硅薄膜晶体管，第二晶体管T2采用氧化物半导体薄膜晶体管，该像素驱动电路应用于低频工作状态或高频工作状态的具体流程进行详细说明。
参考图3，图3是本申请实施例的2T2C结构的像素驱动电路在低频时的连接关系，当该像素驱动电路处于低频工作状态时，第一晶体管T1的栅极接入第一常态信号Gn1，源极接入公共信号Com，漏极分别电性连接液晶电容Clc的第一端D1和存储电容Cst的第一端D1，并且第二晶体管T2的栅极接入行扫描信号，源极接入数据信号，漏极分别电性连接液晶电容Clc的第二端D2和存储电容Cst的第二端D2。
当该像素驱动电路工作于低频状态时，第一晶体管T1常开。可以理解的是，若第一晶体管T1为N型薄膜晶体管，则第一常态信号Gn1为高电平信号；若第一晶体管T1为P型薄膜晶体管，则第一常态信号Gn1为低电平信号。此处以第一晶体管T1为N型薄膜晶体管为例。
此时，第二晶体管T2为驱动开关负责数据信号的写入，第一晶体管T1为常开开关负责保持D1点的公共端准位，即将第二晶体管T2的栅极接入行扫描信号，源极接入数据信号，第一晶体管T1的栅极接入第一常态信号Gn1，源极接入公共信号Com。
此种驱动方式下，像素驱动电路通过第二晶体管T2漏电向存储电容Cst和液晶电容Clc充电写入数据，且由于第二晶体管T2采用氧化物半导体薄膜晶体管IGZO ，其漏电流Ioff较小，较好地解决了低频时画面保持能力不足的问题。
参考图4，图4是本申请实施例的2T2C结构的像素驱动电路在高频时的连接关系，当该像素驱动电路处于高频工作状态时，第一晶体管T1的栅极连接行扫描信号Kn，源极接入数据信号Data，漏极分别电性连接液晶电容Clc的第一端D1和存储电容Cst的第一端D1，并且第二晶体管T2的栅极接入第二常态信号Gn2，源极接入公共信号Com，漏极分别电性连接液晶电容Clc的第二端D2和存储电容Cst的第二端D2。
当该像素驱动电路工作于高频状态时，第二晶体管T2常开。同样可以理解的是，若第二晶体管T2为N型薄膜晶体管，则第二常态信号Gn2为高电平信号；若第二晶体管T2为P型薄膜晶体管，则第二常态信号Gn2为低电平信号。此处也以第二晶体管T2为N型薄膜晶体管为例。
此时，第一晶体管T1为驱动开关负责数据信号Data的写入，第二晶体管T2为常开开关负责保持D2点的公共端准位，即将第一晶体管T1的栅极接入行扫描信号Kn，源极接入数据信号Data，此时将第二晶体管T2的栅极接入第二常态信号Gn2，源极接入公共信号Com。
此种驱动方式下，像素驱动电路通过第一晶体管T1漏电向存储电容Cst和液晶电容Clc充电写入数据，而第一晶体管T1采用低温多晶硅薄膜晶体管LTPS，其迁移率较高、充电能力较强，较好地解决了高频时充电能力不足的问题。
该像素驱动电路采用2T2C的电路结构，能分别针对低频状态和高频状态自行切换电路内部第一晶体管T1、第二晶体管T2与外部扫描线、数据线之间的连接关系，以使得能在低频状态时利用第二晶体管T2即氧化物半导体薄膜晶体管IGZO写入数据，而在高频状态时利用第一晶体管T1即低温多晶硅薄膜晶体管LTPS写入数据，从而能在低频状态时利用氧化物半导体薄膜晶体管IGZO漏电流低、漏电流loff较小，因此更加省电、画面保持能力更强的优点，避免低温多晶硅薄膜晶体管LTPS漏电流Ioff太高画面保持能力差的缺点，而在高频状态时利用低温多晶硅薄膜晶体管LTPS迁移率更高、充电能力更强的优点，避免氧化物半导体薄膜晶体管IGZO迁移率较低、充电能力较弱的缺点。
本申请实施例能在低频状态和高频状态之间交替工作，高频状态时利用低温多晶硅薄膜晶体管LTPS 迁移率较高的特点做驱动开关，低频状态时利用氧化物半导体薄膜晶体管IGZO低漏电流Ioff小的特点做驱动开关，由此解决高频充电不足，低频漏电严重的问题，以满足动态帧频技术的要求。
可以理解的是，行扫描信号由GOA电路或栅极覆晶薄膜gate IC生成；数据信号由外部时钟控制芯片生成。
需要说明的是，低频状态对应的刷新频率包括1~5Hz的超低频，高频状态对应的刷新频率包括120~360Hz的超高频，以满足动态帧频技术的要求。
本申请实施例还提供一种显示面板，该显示面板包括如上所述的像素驱动电路，该显示面板具有与前述实施例提供的像素驱动电路相同的结构和有益效果。由于前述实施例已经对该像素驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、液晶电容和存储电容；所述第一晶体管和所述第二晶体管均分别包括源极、栅极和漏极，所述液晶电容和所述存储电容均分别包括第一端和第二端；
    所述第一晶体管的漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端，所述第二晶体管的漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端；
    所述第一晶体管的栅极接入常态信号，源极接入公共信号，且所述第二晶体管的栅极接入行扫描信号，源极接入数据信号；或者，所述第一晶体管的栅极接入行扫描信号，源极接入数据信号，且所述第二晶体管的栅极接入常态信号，源极接入公共信号。
  2. 如权利要求1所述的像素驱动电路，其中，所述第一晶体管为低温多晶硅薄膜晶体管，所述第二晶体管为氧化物半导体薄膜晶体管；
    所述第一晶体管的栅极接入第一常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端；
    所述第二晶体管的栅极接入行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
  3. 如权利要求2所述的像素驱动电路，其中，
    所述第一晶体管的栅极连接行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端；
    所述第二晶体管的栅极接入第二常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
  4. 如权利要求3所述的像素驱动电路，其中，
    当所述像素驱动电路工作于低频状态时，所述第一晶体管关闭，所述第二晶体管打开；
    当所述像素驱动电路工作于高频状态时，所述第一晶体管打开，所述第二晶体管关闭。
  5. 如权利要求3所述的像素驱动电路，其中，若所述第一晶体管为N型薄膜晶体管，则所述第一常态信号为高电平信号；若所述第一晶体管为P型薄膜晶体管，则所述第一常态信号为低电平信号。
  6. 如权利要求3所述的像素驱动电路，其中，若所述第二晶体管为N型薄膜晶体管，则所述第二常态信号为高电平信号；若所述第二晶体管为P型薄膜晶体管，则所述第二常态信号为低电平信号。
  7. 如权利要求3所述的像素驱动电路，其中，所述行扫描信号由GOA电路或栅极覆晶薄膜生成。
  8. 如权利要求1所述的像素驱动电路，其中，所述数据信号由外部时钟控制芯片生成。
  9. 如权利要求4所述的像素驱动电路，其中，所述低频状态对应的刷新频率包括1~5Hz的超低频，所述高频状态对应的刷新频率包括120~360Hz的超高频。
  10. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、液晶电容和存储电容；所述第一晶体管和所述第二晶体管均分别包括源极、栅极和漏极，所述液晶电容和所述存储电容均分别包括第一端和第二端；
    所述第一晶体管的漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端，所述第二晶体管的漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端；
    所述第一晶体管的栅极接入常态信号，源极接入公共信号，且所述第二晶体管的栅极接入行扫描信号，源极接入数据信号；或者，所述第一晶体管的栅极接入行扫描信号，源极接入数据信号，且所述第二晶体管的栅极接入常态信号，源极接入公共信号。
  11. 如权利要求10所述的显示面板，其中，所述第一晶体管为低温多晶硅薄膜晶体管，所述第二晶体管为氧化物半导体薄膜晶体管；
    所述第一晶体管的栅极接入第一常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端；
    所述第二晶体管的栅极接入行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
  12. 如权利要求11所述的显示面板，其中，
    所述第一晶体管的栅极连接行扫描信号，源极接入数据信号，漏极分别电性连接所述液晶电容的第一端和所述存储电容的第一端；
    所述第二晶体管的栅极接入第二常态信号，源极接入公共信号，漏极分别电性连接所述液晶电容的第二端和所述存储电容的第二端。
  13. 如权利要求12所述的显示面板，其中，
    当所述像素驱动电路工作于低频状态时，所述第一晶体管关闭，所述第二晶体管打开；
    当所述像素驱动电路工作于高频状态时，所述第一晶体管打开，所述第二晶体管关闭。
  14. 如权利要求12所述的显示面板，其中，
    若所述第一晶体管为N型薄膜晶体管，则所述第一常态信号为高电平信号；若所述第一晶体管为P型薄膜晶体管，则所述第一常态信号为低电平信号。
  15. 如权利要求12所述的显示面板，其中，
    若所述第二晶体管为N型薄膜晶体管，则所述第二常态信号为高电平信号；若所述第二晶体管为P型薄膜晶体管，则所述第二常态信号为低电平信号。
  16. 如权利要求12所述的显示面板，其中，所述行扫描信号由GOA电路或栅极覆晶薄膜生成。
  17. 如权利要求10所述的显示面板，其中，所述数据信号由外部时钟控制芯片生成。
  18. 如权利要求13所述的显示面板，其中，所述低频状态对应的刷新频率包括1~5Hz的超低频，所述高频状态对应的刷新频率包括120~360Hz的超高频。
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