WO2021248501A1 - 静电泄放保护电路及具有静电泄放保护电路的芯片 - Google Patents

静电泄放保护电路及具有静电泄放保护电路的芯片 Download PDF

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Publication number
WO2021248501A1
WO2021248501A1 PCT/CN2020/095976 CN2020095976W WO2021248501A1 WO 2021248501 A1 WO2021248501 A1 WO 2021248501A1 CN 2020095976 W CN2020095976 W CN 2020095976W WO 2021248501 A1 WO2021248501 A1 WO 2021248501A1
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Prior art keywords
voltage
module
inverter
electrostatic
alarm
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PCT/CN2020/095976
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English (en)
French (fr)
Inventor
张均军
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2020/095976 priority Critical patent/WO2021248501A1/zh
Priority to CN202080018787.8A priority patent/CN113678249A/zh
Publication of WO2021248501A1 publication Critical patent/WO2021248501A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/12—Measuring electrostatic fields or voltage-potential
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H05F3/02—Carrying-off electrostatic charges by means of earthing connections

Definitions

  • the embodiments of the present application relate to the field of electronic technology, and in particular to an electrostatic discharge protection circuit and a chip with an electrostatic discharge protection circuit.
  • Electro-Static Discharge (ESD) events of varying degrees will occur during the production, testing, transportation, and use of chips.
  • ESD Electro-Static Discharge
  • a large amount of charge will be poured into the chip from the outside to the inside in an instant.
  • the system of the chip will enter an abnormal state (such as abnormal reset, runaway or deadlock), which will affect the normal operation of the chip.
  • EMC electromagnetic compatibility
  • an electrostatic discharge protection circuit can be set in the chip, and the electrostatic discharge can be carried out through the electrostatic discharge protection circuit to avoid damage to the internal circuit of the chip.
  • an electrostatic discharge protection circuit can be provided at the input and output pads (IO PAD) of the chip, and the electrostatic discharge protection circuit can guide static electricity to be discharged in the input and output power supply loop that can pass a relatively large current when the electrostatic discharge protection circuit performs electrostatic discharge.
  • I PAD input and output pads
  • electrostatic discharge in a complex electromagnetic environment may cause the devices in the chip to be broken down, resulting in abnormal chip current, or complete damage to the chip, etc., making the chip unrecoverable hardware Damage
  • the voltage of each node on the discharge path will change instantaneously, and the chip may experience a series of operating errors (such as abnormal reset, program deadlock, etc.). ).
  • operating errors are non-physical damages that can be recovered by external interventions such as power failure or reset, they may still cause larger errors in the chip at the system level, thereby reducing the stability of the chip’s work and damaging it user experience.
  • one of the technical problems solved by the embodiments of the present application is to provide an electrostatic discharge protection circuit and a chip with the electrostatic discharge protection circuit to overcome some or all of the problems in the prior art.
  • the embodiment of the present application provides an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit includes an RC module, an alarm module, and a discharge module;
  • the alarm module receives the input voltage of the RC module and the output voltage of the RC module. When the input voltage of the RC module increases, the alarm voltage of the alarm module increases, and when the alarm voltage is greater than or equal to the output voltage of the RC module, it outputs an electrostatic alarm signal ;
  • the bleeder module receives the input voltage of the RC module and the output voltage of the RC module.
  • the bleeder voltage of the bleeder module increases, and when the bleeder voltage is greater than or equal to the output voltage of the RC module, Perform electrostatic discharge, and the alarm voltage is greater than the discharge voltage.
  • An embodiment of the application provides a chip with an electrostatic discharge protection circuit, and the chip with an electrostatic discharge protection circuit includes the electrostatic discharge protection circuit provided by the embodiment of the application.
  • the input voltage of the RC module will rise sharply due to the instantaneous impact of electrostatic high voltage.
  • the output voltage of the RC module and the alarm module Both the alarm voltage and the discharge voltage of the bleeder module increase. Since the alarm voltage is greater than the bleed voltage, the time when the alarm voltage is greater than the output voltage of the RC module is earlier than the time when the bleed voltage is greater than the output voltage of the RC module to ensure the alarm
  • the module first outputs an electrostatic alarm signal to warn that the electrostatic discharge is about to be carried out, and then the discharge module performs electrostatic discharge.
  • the electrostatic discharge protection circuit provided by the embodiment of the present application can output an electrostatic alarm signal to warn that an electrostatic discharge event is about to occur before performing electrostatic discharge, so that the chip can take software or hardware preventive measures against the electrostatic discharge event. Or post-remedial measures to reduce the probability of unrecoverable hardware damage or operating errors when the chip is electrostatically discharged, thereby improving the stability of the chip's work and improving the user experience.
  • FIG. 1 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application
  • FIG. 2 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of voltage changes with time according to an embodiment of the application.
  • FIG. 4 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application.
  • FIG. 7 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application.
  • FIG. 8 is a schematic circuit structure diagram of a pulse extension alarm module provided by an embodiment of the application.
  • FIG. 9 is a schematic circuit structure diagram of a pulse extension alarm module provided by an embodiment of the application.
  • FIG. 10 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application.
  • the uncontrolled transfer of electrostatic charge from one object to another is generally called an electrostatic discharge event.
  • an electrostatic discharge event occurs, a large amount of charge will be poured into the chip from the outside to the inside in an instant. If the chip encounters an electrostatic discharge event during operation, or the impact of external electrostatic coupling, it will cause the chip system to enter an abnormal state and affect the chip Normal operation.
  • an electrostatic discharge protection circuit (such as RC clamp electrostatic discharge protection circuit, or transient suppression diode electrostatic discharge protection circuit, etc.) can be set in the chip, and pass The electrostatic discharge protection circuit discharges static electricity to avoid damage to the internal circuit of the chip.
  • electrostatic discharge protection circuit such as RC clamp electrostatic discharge protection circuit, or transient suppression diode electrostatic discharge protection circuit, etc.
  • devices in different voltage domains in the protection chip can be protected, and corresponding electrostatic discharge protection circuits can be provided for the input and output interfaces of each voltage domain.
  • the electrostatic discharge protection circuit includes a resistor R0, a capacitor C0, an inverter P0, and an N-type transistor N0.
  • One end of the resistor R0 is connected to the electrostatic discharge terminal V0, and the other end of the resistor R0 Connect to one end of the capacitor C0, the other end of the capacitor C0 is grounded, the connection between the resistor R0 and the capacitor C0 is connected to the first input terminal of the inverter P0, and the second input terminal of the inverter P0 is connected to the electrostatic discharge terminal V0 ,
  • the inverter P0 has a ground terminal, the drain of the N-type transistor N0 is connected to the electrostatic discharge terminal V0, the gate of the N-type transistor N0 is connected to the output terminal of the inverter P0, and the source of the N-type transistor N0 is grounded.
  • the electrostatic discharge terminal V0 can be connected to the pins or components in the chip that are prone to electrostatic discharge events.
  • the electrostatic discharge terminal V0 can be connected to the chip input interface or the chip output interface, and the electrostatic discharge protection circuit
  • the grounding terminal can be connected to the grounding terminal of the power loop that allows large current to pass through in the chip; for example, the electrostatic discharge terminal V0 can be connected to the power supply pin of the input and output pad (IO PAD), and the grounding of the electrostatic discharge protection circuit
  • the terminal can also be connected to the ground pin of the input and output pads, and when an electrostatic discharge event occurs on the input and output pads, the static electricity is guided to be discharged in the input and output power loop that can pass a larger current.
  • the electrostatic discharge terminal V0 may be connected to the power terminal of the power loop in the chip, and the ground terminal of the electrostatic discharge protection circuit may be connected to the ground terminal of the power loop in the chip.
  • the connection between the resistor R0 and the capacitor C0 is connected to the first input terminal of the inverter P0, and the voltage at the connection between the resistor R0 and the capacitor C0 is the same as the first input of the inverter P0.
  • the voltage at one input terminal is the same.
  • the second input terminal of the inverter P0 is connected to the electrostatic discharge terminal V0 of the electrostatic discharge protection circuit, and the voltage of the second input terminal of the inverter P0 is the same as the voltage of the electrostatic discharge terminal V0 of the electrostatic discharge protection circuit.
  • the transition voltage of the inverter P0 is proportional to the voltage of the second input terminal of the inverter P0.
  • the corner voltage of the inverter P0 is less than the voltage at the first input terminal of the inverter P0, and the output of the inverter P0
  • the terminal is connected to the ground terminal of the inverter P0, and the output terminal of the inverter P0 outputs a low voltage.
  • the turning voltage of the inverter P0 is greater than or equal to the voltage of the first input terminal of the inverter P0
  • the output terminal of the inverter P0 is connected to the second input terminal of the inverter P0, and the output terminal of the inverter P0 Output high voltage.
  • the voltage at the junction of the resistor R0 and the capacitor C0 is the same as the voltage at the electrostatic discharge terminal V0 ,
  • the voltage at the first input terminal of the inverter P0 is the same as the voltage at the second input terminal of the inverter P0, the turning voltage of the inverter P0 is less than the voltage at the first input terminal of the inverter P0, and the output terminal of the inverter P0 Connected with the ground terminal of the inverter P0, the output terminal of the inverter P0 outputs a low voltage, the gate of the N-type transistor N0 receives the low voltage, and the drain of the N-type transistor N0 and the source of the N-type transistor N0 are cut off , Disconnect the electrostatic discharge terminal V0 from the ground to avoid grounding the electrostatic discharge terminal V0 when the chip is working normally.
  • the chip can be equipped with the above-mentioned electrostatic discharge protection circuit to avoid damage to the internal circuit of the chip when an electrostatic discharge event occurs, since it is impossible to know in advance whether the electrostatic discharge protection circuit will perform electrostatic discharge, it is impossible to control the chip's target
  • the electrostatic discharge protection circuit takes any software or hardware precautions for electrostatic discharge.
  • electrostatic discharge in a complex electromagnetic environment may cause the devices in the chip to be broken down, resulting in abnormal chip current, or complete damage to the chip, etc., making the chip unrecoverable hardware Damage
  • the voltage of each node on the discharge path will change instantaneously, and the chip may experience a series of operating errors (such as abnormal reset, program deadlock, etc.). ).
  • operating errors are non-physical damages that can be recovered by external interventions such as power failure or reset, they may still cause larger errors in the chip at the system level, thereby reducing the stability of the chip’s work and damaging it user experience.
  • the embodiments of the present application provide an electrostatic discharge protection circuit and a chip with an electrostatic discharge protection circuit, so as to overcome the technical defect in the prior art that it is impossible to know in advance whether the electrostatic discharge protection circuit will perform electrostatic discharge. .
  • the input voltage of the RC module will rise sharply due to the instantaneous impact of electrostatic high voltage.
  • the output voltage of the RC module and the alarm module Both the alarm voltage and the discharge voltage of the bleeder module increase. Since the alarm voltage is greater than the bleed voltage, the time when the alarm voltage is greater than the output voltage of the RC module is earlier than the time when the bleed voltage is greater than the output voltage of the RC module to ensure the alarm
  • the module first outputs an electrostatic alarm signal to warn that the electrostatic discharge is about to be carried out, and then the discharge module performs electrostatic discharge.
  • the electrostatic discharge protection circuit provided by the embodiment of the present application can output an electrostatic alarm signal to warn that an electrostatic discharge event is about to occur before performing electrostatic discharge, so that the chip can take software or hardware preventive measures against the electrostatic discharge event. Or post-remedial measures to reduce the probability of unrecoverable hardware damage or operating errors when the chip is electrostatically discharged, thereby improving the stability of the chip's work and improving the user experience.
  • FIG. 2 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application
  • FIG. 4 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application, as shown in FIG. 2 and
  • the electrostatic discharge protection circuit includes: an RC module 101, an alarm module 102, and a discharge module 103. Among them, when the input voltage of the RC module 101 increases, its output voltage increases.
  • the alarm module 102 receives the input voltage of the RC module 101 and the output voltage of the RC module 101. When the input voltage of the RC module 101 increases, the alarm voltage of the alarm module 102 increases, and when the alarm voltage is greater than or equal to the output voltage of the RC module 101 When the voltage is applied, an electrostatic alarm signal is output.
  • the bleeder module 103 receives the input voltage of the RC module 101 and the output voltage of the RC module 101. When the input voltage of the RC module 101 increases, the bleeder voltage of the bleeder module 103 increases, and when the bleeder voltage is greater than or equal to RC When the output voltage of the module 101 is used, electrostatic discharge is performed, and the alarm voltage is greater than the discharge voltage.
  • the static alarm signal output by the alarm module 102 is that the signal output by the alarm module 102 is switched from a low voltage to a high voltage.
  • the input terminal of the RC module 101 can be connected to the devices in the chip that may have electrostatic discharge events.
  • the input terminal of the RC module 101 can be connected to the power supply pin VDDIO PAD 110 of the input and output pad (IO PAD). connect.
  • the ground of the electrostatic discharge protection circuit may be connected to the ground VSSIO PAD 120 of the input output pad (IO PAD).
  • An increase in the input voltage of the RC module 101 will cause an electrostatic discharge event at the input of the RC module 101.
  • an electrostatic discharge event of a Human Body Model (HBM) will cause the input voltage of the RC module 101 to rise instantly. high.
  • HBM Human Body Model
  • the output voltage of the RC module 101, the alarm voltage of the alarm module 102, and the discharge voltage of the bleeder module 103 all increase.
  • the input voltage of the RC module will rise sharply due to the instantaneous impact of electrostatic high voltage.
  • the output voltage of the RC module and the alarm module Both the alarm voltage and the discharge voltage of the bleeder module increase. Because the alarm voltage is greater than the bleed voltage, the time when the alarm voltage is greater than or equal to the output voltage of the RC module is earlier than the time when the bleed voltage is greater than the output voltage of the RC module. Make sure that the alarm module first outputs the electrostatic alarm signal to warn that the electrostatic discharge is about to be carried out, and then the discharge module performs electrostatic discharge.
  • the electrostatic discharge protection circuit provided by the embodiment of the present application can output an electrostatic alarm signal to warn that an electrostatic discharge event is about to occur before performing electrostatic discharge, so that the chip can take software or hardware preventive measures against the electrostatic discharge event. Or post-remedial measures to reduce the probability of unrecoverable hardware damage or operating errors when the chip is electrostatically discharged, thereby improving the stability of the chip's work and improving the user experience.
  • the initial value of the alarm voltage of the alarm module and the initial value of the discharge voltage of the discharge module are both smaller than the initial value of the output voltage of the RC module Value
  • the increase rate of the alarm voltage of the alarm module and the increase rate of the discharge voltage of the bleeder module are all greater than the increase rate of the output voltage of the RC module.
  • the initial value of the output voltage of the RC module is the value of the output voltage of the RC module when no electrostatic discharge event occurs at the input end of the RC module (that is, the chip where the electrostatic discharge protection circuit is located is in a normal operating state).
  • the initial value of the alarm voltage of the alarm module can be understood as the value of the alarm voltage of the alarm module when no electrostatic discharge event occurs at the input terminal of the RC module
  • the initial value of the discharge voltage of the discharge module can be understood as The value of the discharge voltage of the discharge module when there is no electrostatic discharge event at the input terminal of the RC module.
  • FIG. 3 is a schematic diagram of voltage changes with time provided by an embodiment of the application.
  • time t0 is the time when an electrostatic discharge event occurs at the input terminal of the RC module.
  • the chip where the bleeder protection circuit is located is in normal operation, the initial value of the output voltage Vc of the RC module is the same as the input voltage VDD of the RC module, and the alarm voltage Vth_inv_det of the alarm module and the bleeder voltage Vth_inv_clamp of the bleeder module are both before t0.
  • the discharge voltage Vth_inv_clamp of the bleeder module is less than the alarm voltage Vth_inv_de of the alarm module.
  • the alarm module will not output an electrostatic alarm signal and the bleeder module will not discharge static electricity before time t0.
  • An electrostatic discharge event occurs at the input terminal of the RC module at t0, and the input voltage VDD of the RC module starts to rise sharply.
  • the output voltage VC of the RC module, the alarm voltage Vth_inv_det of the alarm module and the discharge voltage Vth_inv_clamp of the bleeder module all start rise.
  • the increase rate of the alarm voltage Vth_inv_det of the alarm module and the discharge voltage Vth_inv_clamp of the discharge module are both greater than the increase rate of the output voltage VC of the RC module.
  • the alarm voltage Vth_inv_det of the alarm module Since the alarm voltage Vth_inv_det of the alarm module is always greater than the discharge voltage Vth_inv_clamp of the discharge module, the alarm voltage Vth_inv_det of the alarm module increases to the same as the output voltage VC of the RC module at t1. At t1, the alarm module outputs an electrostatic alarm signal. The discharge voltage Vth_inv_clamp of the discharge module at time t2 after time t1 is also increased to the same as the output voltage VC of the RC module, and the discharge module performs electrostatic discharge at time t1.
  • the RC module 101 may include a first resistor 211 and a first capacitor 221 connected in series, and the connection point of the first resistor 211 and the first capacitor 221 is RC The output voltage terminal of module 101.
  • the alarm module 102 may include a first inverter 212.
  • the first input terminal of the first inverter 212 receives the input voltage of the RC module 101, and the second input terminal of the first inverter 212 receives the output voltage of the RC module 101.
  • the first input terminal of the first inverter 212 is connected to the output terminal of the first inverter 212 to output an electrostatic alarm signal.
  • the bleeding module may include a second inverter 213 and a first switch unit 223.
  • the first input terminal of the second inverter 213 receives the input voltage of the RC module 101, and the second input terminal of the second inverter 213 receives the output voltage of the RC module 101.
  • the output terminal of the second inverter 213 is connected to the first input terminal of the first switch unit 223.
  • the first input terminal of the first switch unit 223 is connected to the output terminal of the second inverter 213.
  • the first switch unit 223 is turned on to realize electrostatic discharge. put.
  • the warning voltage may be the turning voltage of the first inverter 212, and the bleeding voltage may be the turning voltage of the second inverter 213.
  • the turning voltage of the inverter is proportional to the power supply voltage of the inverter, and the turning voltage of the inverter is smaller than the power supply voltage of the inverter.
  • the output terminal of the inverter is connected to the ground terminal of the inverter, and the output terminal of the inverter outputs a low voltage.
  • the turning voltage of the inverter is greater than or equal to the voltage of the input inverter, the output terminal of the inverter is connected to the power supply terminal voltage of the inverter, and the output terminal of the inverter outputs a high voltage, that is, the power supply voltage.
  • the first inverter 212 receives the power supply voltage, that is, the input voltage of the RC module 101, through the first input terminal, and the first inverter 212 receives the input voltage, that is the output of the RC module 101, through the second input terminal.
  • Voltage; the second inverter 213 receives the power supply voltage through the first input terminal, that is, the input voltage of the RC module 101, and the second inverter 213 receives the input voltage through the second input terminal, that is, the output voltage of the RC module 101.
  • the turning voltage Vth_inv_det of the first inverter 212 can be based on Determine, where VDD is the power supply voltage of the first inverter 212, that is, the input voltage of the RC module 101, Vthp is the turn-on voltage of the PMOS tube in the first inverter 212, and Vthn is the NMOS tube in the first inverter 212
  • VDD is the power supply voltage of the first inverter 212
  • Vthp is the turn-on voltage of the PMOS tube in the first inverter 212
  • Vthn is the NMOS tube in the first inverter 212
  • ⁇ p is the transconductance parameter of the PMOS transistor in the first inverter 212
  • ⁇ n is the transconductance parameter of the NMOS transistor in the first inverter 212.
  • the transconductance parameter ⁇ n of the NMOS tube can be adjusted by adjusting the aspect ratio of the NMOS tube, and the transconductance parameter ⁇ p of the PMOS tube can be adjusted by adjusting the aspect ratio of the PMOS tube.
  • the turn-on voltage Vthn of the NMOS tube and the transconductance parameter ⁇ n of the NMOS tube can be adjusted by adjusting the manufacturing process of the NMOS tube.
  • the turn-on voltage Vthp of the PMOS tube and the transconductance parameter ⁇ p of the PMOS tube can be adjusted by adjusting the preparation of the PMOS tube. Process to adjust.
  • the The transition voltage Vth_inv_det is the ratio of the alarm voltage to the input voltage of the RC module 101 to adjust, and the ratio of the increase rate of the alarm voltage to the increase rate of the input voltage of the RC module 101 can also be adjusted.
  • the second inverter 213 is composed of an NMOS tube and a PMOS tube
  • the turn-on voltage Vthn1 of the NMOS tube in the second inverter 212 can adjust the ratio of the turning voltage Vth_inv_clamp (that is, the bleeder voltage) of the second inverter 213 to the input voltage of the RC module 101, and it can also adjust the rate of increase of the bleeder voltage.
  • the ratio of the increase rate of the input voltage to the RC module 101 is adjusted.
  • the initial value of the alarm voltage can be understood as the value of the alarm voltage when no electrostatic discharge event occurs at the input terminal of the RC module 101
  • the initial value of the discharge voltage can be understood as when no electrostatic discharge occurs at the input terminal of the RC module 101.
  • the output voltage of the RC module 101 is equal to the voltage on the first capacitor 221.
  • the voltage on the first capacitor 221 is equal to the input voltage of the RC module 101, that is, the initial value of the output voltage of the RC module 101 is the input voltage of the RC module 101, so according to The above method adjusts the ratio of the alarm voltage to the input voltage of the RC module 101 and the ratio of the discharge voltage to the input voltage of the RC module 101, so that both the alarm voltage and the discharge voltage are less than the input voltage of the RC module 101, which can ensure the initial alarm voltage
  • the initial value and the initial value of the bleeder voltage are smaller than the initial value of the output voltage of the RC module.
  • the output voltage of the RC module 101 is equal to the voltage on the first capacitor 221 in the RC module, the voltage on the first capacitor 221 cannot change suddenly, and the increase rate of the voltage on the first capacitor 221 is less than the increase of the input voltage of the RC module 101. Therefore, the output voltage of the RC module 101 is lower than the increase rate of the input voltage of the RC module 101.
  • the increase rate of the alarm voltage and the discharge voltage can be made
  • the increase rate of is greater than the increase rate of the input voltage of the RC module 101, so as to ensure that the increase rate of the alarm voltage and the increase rate of the discharge voltage are both greater than the increase rate of the output voltage of the RC module.
  • the electrostatic discharge protection circuit can be in the initial state, and the alarm module will not output static electricity. Alarm signal, the discharge module will not discharge static electricity, to ensure that the static discharge protection circuit will not affect the normal operation of other components in the chip.
  • the increase rate of the alarm voltage of the alarm module is greater than the increase rate of the output voltage of the RC module, which can increase the alarm voltage of the alarm module over time to be greater than the output voltage of the RC module, so that the output alarm module can output an electrostatic alarm signal;
  • the increase rate of the bleeder voltage of the bleeder module is greater than the increase rate of the output voltage of the RC module, which can make the bleeder voltage of the bleeder module increase with time to be greater than the output voltage of the RC module, so that the bleeder Discharge the module for electrostatic discharge.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103.
  • the RC module 101 includes a first resistor 211 and a first capacitor 221 connected in series, one end of the first capacitor 221 is grounded, the other end of the first capacitor 221 is connected to the first resistor 211, and the other end of the first resistor 211 is the RC module 101
  • the connection point between the first resistor 211 and the first capacitor 221 is the output voltage terminal of the RC module 101.
  • the first resistor 211 may also be a plurality of resistors connected in series or in parallel, which is not limited in the embodiment of the present application.
  • the first resistor 211 is shown as an example of a resistor.
  • the first capacitor 221 may also be a plurality of capacitors connected in series or in parallel, which is not limited in the embodiment of the present application.
  • the first capacitor 221 is shown as an example in FIG. 4.
  • the first resistor 211 and the first capacitor 221 connected in series form an RC circuit structure.
  • the voltage on the first capacitor 221 also increases.
  • the charging time constant of the RC circuit structure can be adjusted. Because the charging time constant of the RC circuit structure and the voltage on the first capacitor 221 increase at a positive rate Therefore, by adjusting the resistance value of the first resistor 211 and the capacitance value of the first capacitor 221, the increase rate of the voltage on the first capacitor 221, that is, the increase rate of the voltage output by the output voltage terminal of the RC module 101, can be adjusted.
  • the discharge module 103 discharges static electricity when the discharge voltage is greater than or equal to the output voltage of the RC module 101. If the increase rate of the input voltage of the RC module 101 and the increase rate of the discharge voltage are the same, by slowing down the increase rate of the output voltage of the output voltage terminal of the RC module 101, the discharge voltage can be greater than or equal to that of the RC module 101 in advance.
  • the time of output voltage that is, the time when the discharge module 103 performs electrostatic discharge in advance; by accelerating the increase rate of the output voltage from the output voltage terminal of the RC module 101, the time when the discharge voltage is greater than or equal to the output voltage of the RC module 101 can be delayed , That is, delay the time when the discharge module 103 performs electrostatic discharge in advance.
  • the alarm module 102 outputs an electrostatic alarm signal when the alarm voltage is greater than or equal to the output voltage of the RC module 101. If the increase rate of the input voltage of the RC module 101 and the increase rate of the alarm voltage are the same, the output of the RC module 101 is slowed down
  • the increase rate of the voltage output by the voltage terminal can be advanced when the warning voltage is greater than or equal to the output voltage of the RC module 101, that is, the time when the warning module 102 outputs an electrostatic warning signal; by speeding up the output voltage of the RC module 101
  • the speed increase can delay the time when the alarm voltage is greater than or equal to the output voltage of the RC module 101, that is, the time when the alarm module 102 outputs the electrostatic alarm signal.
  • the increase rate of the input voltage of the RC module 101, the increase rate of the bleeder voltage, and the increase rate of the alarm voltage can be unchanged.
  • the time when the discharge module 103 performs electrostatic discharge and the time when the alarm module 102 outputs the electrostatic alarm signal are adjusted.
  • the resistance value of the first resistor 211 may be 1 m ⁇ , and the capacitance value of the first capacitor 221 may be 1 pF.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103.
  • the alarm module 102 includes a first inverter 212.
  • the first inverter 212 is configured to receive the input voltage of the RC module 101 through the first input terminal, and the output voltage of the RC module 101 through the second input terminal of the first inverter 212.
  • the alarm voltage is greater than that of the RC module 101
  • the first input terminal of the first inverter 212 is connected to the output terminal of the first inverter 212, and an electrostatic alarm signal is output.
  • the output terminal of the first inverter 212 can output the input voltage of the RC module 101 to make the electrostatic alarm signal For high voltage.
  • the first inverter 212 may be a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) circuit, or may be composed of at least two field effect transistors, or may be composed of multiple logic gate circuits, etc.
  • CMOS complementary Metal Oxide Semiconductor
  • the embodiments of the present application are described in This does not impose specific restrictions on the specific implementation of the first inverter 212.
  • the warning voltage may be the turning voltage of the second inverter 213.
  • the turning voltage of the inverter is proportional to the power supply voltage of the inverter, and the turning voltage of the inverter is smaller than the power supply voltage of the inverter.
  • the output terminal of the inverter is grounded, and the output terminal of the inverter outputs a low voltage.
  • the turning voltage of the inverter is greater than or equal to the voltage of the input inverter, the output terminal of the inverter is connected to the power supply terminal voltage of the inverter, and the output terminal of the inverter outputs a high voltage, that is, the power supply voltage.
  • the first inverter 212 receives the power supply voltage, that is, the input voltage of the RC module 101, through the first input terminal, and the first inverter 212 receives the input voltage, that is the output voltage of the RC module 101, through the second input terminal.
  • the alarm voltage may be the turning voltage Vth_inv_det of the first inverter 212.
  • the turning voltage Vth_inv_det of the first inverter 212 can be based on Determine, where VDD is the power supply voltage of the first inverter 212, that is, the input voltage of the RC module 101, Vthp is the turn-on voltage of the PMOS tube in the first inverter 212, and Vthn is the NMOS tube in the first inverter 212
  • VDD is the power supply voltage of the first inverter 212
  • Vthp is the turn-on voltage of the PMOS tube in the first inverter 212
  • Vthn is the NMOS tube in the first inverter 212
  • the turn-on voltage, ⁇ p is the transconductance parameter of the PMOS transistor in the first inverter 212
  • ⁇ n is the transconductance parameter of the NMOS transistor in the first inverter 212.
  • the transconductance parameter ⁇ n of the NMOS tube can be adjusted by adjusting the aspect ratio of the NMOS tube, and the transconductance parameter ⁇ p of the PMOS tube can be adjusted by adjusting the aspect ratio of the PMOS tube.
  • the turn-on voltage Vthn of the NMOS tube and the transconductance parameter ⁇ n of the NMOS tube can be adjusted by adjusting the manufacturing process of the NMOS tube.
  • the turn-on voltage Vthp of the PMOS tube and the transconductance parameter ⁇ p of the PMOS tube can be adjusted by adjusting the manufacturing process of the PMOS tube. To make adjustments.
  • the The transition voltage Vth_inv_det is the ratio of the alarm voltage to the input voltage of the RC module 101 to adjust, and the ratio of the increase rate of the alarm voltage to the increase rate of the input voltage of the RC module 101 can also be adjusted.
  • the alarm voltage of the first inverter 212 when the alarm voltage of the first inverter 212 is less than the output voltage of the RC module 101, the ground terminal of the first inverter 212 and the output terminal of the first inverter 212 Conduction.
  • the alarm voltage is less than the output voltage of the RC module 101
  • the first inverter 212 The ground terminal is connected to the output terminal of the first inverter 212, and the output voltage of the output terminal of the first inverter 212 is 0.
  • the output voltage of the output terminal of the first inverter 212 is 0, it can be regarded as the first inverter.
  • the output terminal of the phaser 212 does not output an electrostatic alarm signal, so that no alarm is issued after the electrostatic discharge event ends, which prevents the chip from performing unnecessary processing operations after the electrostatic discharge event has ended, and saves processing resources of the chip.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103.
  • the bleeder module includes a second inverter 213 and a first switch unit 223.
  • the first input terminal of the second inverter 213 receives the input voltage of the RC module 101, and the second input terminal of the second inverter 213 receives the output voltage of the RC module 101.
  • the output terminal of the second inverter 213 is connected to the first input terminal of the first switch unit 223.
  • the first input terminal of the first switch unit 223 is connected to the output terminal of the second inverter 213.
  • the first switch unit 223 is turned on to realize electrostatic discharge. put.
  • the second input terminal of the first switch unit 223 is connected to the input terminal of the RC module 101, and the output terminal of the first switch unit 223 is grounded.
  • the first The second input terminal of a switch unit 223 is connected to the output terminal of the first switch unit 223 to guide the static electricity at the input terminal of the RC module 101 to the ground, so as to discharge static electricity.
  • the bleeding voltage may be the turning voltage of the second inverter 213.
  • the turning voltage of the inverter is proportional to the power supply voltage of the inverter, and the turning voltage of the inverter is smaller than the power supply voltage of the inverter.
  • the output terminal of the inverter is grounded, and the output terminal of the inverter outputs a low voltage.
  • the turning voltage of the inverter is greater than or equal to the voltage of the input inverter, the output terminal of the inverter is connected to the power supply terminal voltage of the inverter, and the output terminal of the inverter outputs a high voltage, that is, the power supply voltage.
  • the second inverter 213 receives the power supply voltage, that is, the input voltage of the RC module 101, through the first input terminal, and the second inverter 213 receives the input voltage, that is the output voltage of the RC module 101, through the second input terminal.
  • the turning voltage Vth_inv_clamp of the second inverter 213 can be based on Determine, where VDD is the power supply voltage of the second inverter 213, that is, the input voltage of the RC module 101, Vthp1 is the turn-on voltage of the PMOS transistor in the second inverter 213, and Vthn1 is the NMOS transistor in the second inverter 213 Turn-on voltage, ⁇ p1 is the transconductance parameter of the PMOS transistor in the second inverter 213, and ⁇ n1 is the transconductance parameter of the NMOS transistor in the second inverter 213.
  • the transconductance parameter ⁇ n1 of the NMOS tube can be adjusted by adjusting the aspect ratio of the NMOS tube
  • the transconductance parameter ⁇ p1 of the PMOS tube can be adjusted by adjusting the aspect ratio of the PMOS tube.
  • the turn-on voltage Vthn1 of the NMOS tube and the transconductance parameter ⁇ n1 of the NMOS tube can be adjusted by adjusting the manufacturing process of the NMOS tube.
  • the turn-on voltage Vthp1 of the PMOS tube and the transconductance parameter ⁇ p1 of the PMOS tube can be adjusted by adjusting the preparation of the PMOS tube. Process to adjust.
  • the The transition voltage Vth_inv_clamp is the ratio of the discharge voltage to the input voltage of the RC module 101 to adjust, and at the same time, the ratio of the increase rate of the alarm voltage to the increase rate of the input voltage of the RC module 101 can be adjusted.
  • the first switching unit 223 may be composed of one or more transistors.
  • the plurality of transistors may respectively respond when the output voltage of the second inverter 213 is greater than the first switching voltage.
  • the switching action of, turns on the first switch unit 223.
  • the embodiment of the present application does not specifically limit the composition of the first switch unit 223.
  • the first switch unit 223 includes a single N-type transistor as an example for description, where the gate of the N-type transistor receives the output voltage of the second inverter 213, and the drain of the N-type transistor is connected to the RC module 101.
  • the input terminal is connected, and the source of the N-type transistor is grounded.
  • the drain of the N-type transistor is connected to the source of the N-type transistor.
  • the static electricity at the input end of the RC module 101 is guided to the ground to discharge static electricity.
  • FIG. 7 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of this application.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103.
  • the electrostatic discharge protection circuit further includes a pulse expansion alarm module 104, which delays the electrostatic alarm signal and outputs a delayed electrostatic alarm signal whose duration is greater than the duration of the electrostatic alarm signal.
  • the duration of an electrostatic discharge event is often short (for example, the electrostatic discharge event gradually disappears after about 100nS).
  • the chip may take hardware preventive measures quickly, but software processing The speed may not be able to respond to the alarm signal in time.
  • the pulse extension alarm module 104 delays the electrostatic alarm signal, and the output duration is longer than the delayed electrostatic alarm signal, which can facilitate the micro-control unit MCU or electrostatic discharge protection
  • the circuit module in the chip where the circuit is used to handle the electrostatic discharge event does not respond to the alarm signal in time, it responds to the delayed electrostatic alarm signal whose duration is greater than the electrostatic alarm signal, such as subsequent error correction, etc. Improve the stability of chip work and improve user experience.
  • FIG. 8 is a schematic circuit structure diagram of a pulse expansion alarm module provided by an embodiment of the application.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and a pulse extension alarm module 104.
  • the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, and a second capacitor. 134.
  • the third inverter 144 includes a third switch unit 114, a third switch unit 124, and a second capacitor. 134.
  • the second switch unit 114 is turned on when the first input terminal of the second switch unit 114 receives the electrostatic alarm signal, and is turned off when the first input terminal of the second switch unit 114 does not receive the electrostatic alarm signal.
  • the third switch unit 124 is turned off when the first input terminal of the third switch unit 124 receives the electrostatic alarm signal, and turned on when the first input terminal of the third switch unit 124 does not receive the electrostatic alarm signal.
  • the second capacitor 134 is used to charge when the second switch unit 114 is turned off and the third switch unit 134 is turned on, and to discharge when the second switch unit 114 is turned on and the third switch unit 134 is turned off.
  • the first input terminal of the third inverter 144 receives the voltage of the second capacitor 134, and when the voltage of the second capacitor 134 is less than the pulse expansion voltage, it outputs a delayed electrostatic alarm signal.
  • the first input terminal of the second switch unit 114 is connected to the output terminal of the alarm module 102, the second input terminal of the second switch unit 114 is connected to the first terminal of the second capacitor 134, and the output of the second switch unit 114 is The terminal is grounded.
  • the first input terminal of the third switch unit 124 is connected to the output terminal of the alarm module 102, the second input terminal of the third switch unit 124 receives the input voltage of the RC module 101, and the output terminal of the third switch unit 124 is connected to the second capacitor 134
  • the first terminal is connected, and the second terminal of the second capacitor 134 is grounded.
  • the second input terminal of the third inverter 144 receives the input voltage of the RC module 101, and the third inverter 144 has a ground terminal.
  • the first input terminal of the second switch unit 114 receives the electrostatic alarm signal output from the output terminal of the alarm module 102, and the second input terminal of the second switch unit 114 and the second switch The output terminal of the unit 114 is turned on, and the first terminal of the second capacitor 134 is grounded.
  • the first input terminal of the third switch unit 124 receives the electrostatic alarm signal output by the output terminal of the alarm module 102, and the first terminal of the third switch unit 124
  • the second input terminal is disconnected from the output terminal of the third switch unit 124, the output terminal of the third switch unit 124 does not output any voltage to the first terminal of the second capacitor 134, and the first terminal of the second capacitor 134 discharges to make the first terminal
  • the voltage of the second capacitor 134 is less than the pulse expansion voltage.
  • the first input terminal of the third inverter 144 receives the voltage of the second capacitor 134, and the output terminal of the third inverter 144 outputs a delayed electrostatic alarm signal.
  • the first input terminal of the second switch unit 114 does not receive the electrostatic alarm signal output from the output terminal of the alarm module 102, and the second input terminal of the second switch unit 114 is connected to the first input terminal of the second switch unit 114.
  • the output terminal of the second switch unit 114 When the output terminal of the second switch unit 114 is disconnected, the first terminal of the second capacitor 134 is disconnected from the ground, and the first input terminal of the third switch unit 124 does not receive the electrostatic alarm signal output by the output terminal of the alarm module 102,
  • the second input terminal of the three switch unit 124 is connected to the output terminal of the third switch unit 124, and the input voltage of the RC module 101 is output to the first terminal of the second capacitor 134 through the output terminal of the third switch unit 124.
  • Charge 134 increases the voltage of the second capacitor 134.
  • the first input terminal of the third inverter 144 receives the voltage of the second capacitor 134.
  • the third inverter 144 When the voltage of the second capacitor 134 does not increase to be greater than or equal to the pulse extension voltage, the third inverter 144 still outputs a delay electrostatic alarm Signal; when the voltage of the second capacitor 134 increases to greater than or equal to the pulse extension voltage, the third inverter 144 stops outputting the delayed electrostatic alarm signal, which starts from the time when the output terminal of the alarm module 102 does not output the electrostatic alarm signal ,
  • the length of time until the voltage of the second capacitor 134 increases to be greater than or equal to the pulse extension voltage can be understood as the time difference between the duration of the delayed electrostatic alarm signal and the duration of the electrostatic alarm signal.
  • the time when the third inverter 144 outputs the delayed electrostatic alarm signal is later than the time when the alarm module 102 outputs the electrostatic alarm signal, but the time difference between the two times is very short and can be ignored.
  • the second switch unit 114 may be composed of one or more transistors. When the second switch unit 114 includes a plurality of transistors, the plurality of transistors may respond respectively when the first input terminal of the second switch unit 114 receives an electrostatic alarm signal. The second switch unit 114 is turned on by the switching action of, or when the first input terminal of the second switch unit 114 does not receive the electrostatic alarm signal, a corresponding switch action can be made to turn off the second switch unit 114.
  • the embodiment of the present application does not specifically limit the composition of the second switch unit 114.
  • the third switch unit 124 may be composed of one or more transistors. When the third switch unit 124 includes a plurality of transistors, the plurality of transistors may respectively respond when the first input terminal of the third switch unit 124 receives an electrostatic alarm signal. The third switch unit 124 is turned on by the switching action of, or when the first input terminal of the third switch unit 124 does not receive the electrostatic alarm signal, corresponding switching actions are made to turn off the third switch unit 124.
  • the embodiment of the present application does not specifically limit the composition of the third switch unit 124.
  • the second capacitor 134 may also include a plurality of capacitors connected in series or in parallel, which is not limited in the embodiment of the present application.
  • the third inverter 144 may be a complementary metal oxide semiconductor circuit, or may be composed of at least two field effect transistors, or may be composed of multiple logic gate circuits, etc.
  • the embodiment of the present application does not apply to the third inverter 144 here. Make specific restrictions on the specific implementation method.
  • the pulse extension voltage may be the turning voltage of the third inverter 144.
  • the turning voltage of the inverter is proportional to the power supply voltage of the inverter, and the turning voltage of the inverter is smaller than the power supply voltage of the inverter.
  • the output terminal of the inverter is grounded, and the output terminal of the inverter outputs a low voltage.
  • the turning voltage of the inverter is greater than or equal to the voltage of the input inverter, the output terminal of the inverter is connected to the power supply terminal voltage of the inverter, and the output terminal of the inverter outputs a high voltage, that is, the power supply voltage.
  • the third inverter 144 receives the power supply voltage, that is, the input voltage of the RC module 101, through the second input terminal, and the third inverter 144 receives the input voltage, that is, the voltage of the second capacitor 134 through the first input terminal.
  • the pulse extension voltage may be the turning voltage Vth_inv_pulse of the third inverter 144.
  • the corner voltage Vth_inv_pulse of the third inverter 144 can be based on Determine, where VDD is the power supply voltage of the third inverter 144, that is, the input voltage of the RC module 101, Vthp2 is the turn-on voltage of the PMOS transistor in the third inverter 144, and Vthn2 is the NMOS transistor in the third inverter 144 Turn-on voltage, ⁇ p2 is the transconductance parameter of the PMOS transistor in the third inverter 144, and ⁇ n2 is the transconductance parameter of the NMOS transistor in the third inverter 144.
  • the transconductance parameter ⁇ n2 of the NMOS tube can be adjusted by adjusting the aspect ratio of the NMOS tube
  • the transconductance parameter ⁇ p2 of the PMOS tube can be adjusted by adjusting the aspect ratio of the PMOS tube.
  • the turn-on voltage Vthn2 of the NMOS tube and the transconductance parameter ⁇ n2 of the NMOS tube can be adjusted by adjusting the manufacturing process of the NMOS tube.
  • the turn-on voltage Vthp2 of the PMOS tube and the transconductance parameter ⁇ p2 of the PMOS tube can be adjusted by adjusting the preparation of the PMOS tube. Process to adjust.
  • the The transition voltage Vth_inv_pulse is the ratio of the pulse extension voltage to the input voltage of the RC module 101 to adjust, and at the same time, the ratio of the increase rate of the pulse extension voltage to the increase rate of the input voltage of the RC module 101 can be adjusted.
  • the input voltage of the third inverter 144 when the voltage of the second capacitor 134 is charged to be greater than or equal to the pulse extension voltage (that is, when the voltage of the second capacitor 134 increases to be greater than or equal to the pulse extension voltage), the input voltage of the third inverter 144 The voltage at the first input terminal is greater than or equal to the pulse extension voltage, and the third inverter 144 stops outputting the delayed electrostatic alarm signal. Therefore, by adjusting the charging speed of the voltage of the second capacitor 134, the duration of the delayed electrostatic alarm signal can be adjusted.
  • the difference between the third switch unit 124 and the second capacitor 134 can be adjusted.
  • the RC time constant between the time and the charging speed of the second capacitor 134 can be adjusted.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and The pulse extension alarm module 104, wherein the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144.
  • the second input terminal of the third inverter 114 is connected to the input voltage terminal of the RC module 101.
  • the second input terminal of the third inverter 144 is connected to the third inverter.
  • the output terminal of the phaser 144 is turned on.
  • the second input terminal of the third inverter 144 receives the input voltage of the RC module 101, and when the voltage of the second capacitor 134 received at the first input terminal of the third inverter 144 is less than the pulse extension voltage, the third inverter 144
  • the second input terminal of the phaser 144 is connected to the output terminal of the third inverter 144, and the output terminal of the third inverter 144 outputs the input voltage signal of the RC module 101, so that the delayed electrostatic alarm signal is a high voltage to ensure The voltage value of the delayed electrostatic alarm signal can meet the demand.
  • the ground terminal of the third inverter 144 and the output terminal of the third inverter 144 When it is turned on, the delayed electrostatic alarm signal is a high voltage, and the output terminal of the third inverter 144 stops outputting the delayed electrostatic alarm signal.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and The pulse extension alarm module 104, wherein the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144.
  • the third switch unit 124 includes a P-type transistor, the gate of the P-type transistor receives the electrostatic alarm signal, the drain of the P-type transistor receives the input voltage of the RC module 11, and the source of the P-type transistor is connected to the second capacitor 134 , The P-type transistor is turned on when the electrostatic alarm signal is greater than or equal to the first switching threshold.
  • the third switch unit 144 includes a P-type transistor, which can enable the third switch unit 144 to realize that the electrostatic alarm signal is greater than or equal to the first under the premise of low manufacturing cost. The function of turning on at the switching threshold.
  • the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and The pulse extension alarm module 104, wherein the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144.
  • the third switch unit 124 includes n P-type transistors, n ⁇ 2, where n is a natural number, the gates of the n P-type transistors receive electrostatic alarm signals, and the drains of the first-stage P-type transistors among the n P-type transistors Receiving the input voltage of the RC module 11, the source of the previous P-type transistor among the n P-type transistors is connected to the drain of the adjacent next-stage P-type transistor, and the n-th P-type transistor among the n P-type transistors The source is connected to the second capacitor 134, and the n P-type transistors are turned on when the electrostatic alarm signal is greater than or equal to the first switching threshold.
  • the third switch unit 144 including n P-type transistors, n ⁇ 2, compared with the third switch unit 144 including only one transistor, the third switch unit 144 can be turned on when the electrostatic alarm signal is greater than or equal to the first switch threshold.
  • the resistance of the third switch unit 144 is increased, the charging time of the second capacitor 134 is prolonged, thereby prolonging the duration of the delayed electrostatic alarm signal, and the structure of the second capacitor 134 or in the third switch unit 144 Compared with the scheme of setting the resistance to extend the duration of the delayed electrostatic alarm signal, the cost of this scheme is lower.
  • FIG. 10 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided by an embodiment of the application. As shown in FIG. 10, on the basis of the first embodiment, the electrostatic discharge protection circuit provided by the eleventh embodiment of the present application , The electrostatic discharge protection circuit further includes a processing module 200.
  • the processing module 200 receives the electrostatic alarm signal, and executes at least one of an electrostatic discharge prevention method and an electrostatic discharge remedial method in response to the electrostatic alarm signal.
  • the electrostatic discharge prevention method includes suspending the program currently executed by the processing module 200.
  • the electrostatic discharge remedial method includes resending the data sent by the processing module 200 in the electrostatic discharge time interval after the electrostatic warning signal ends.
  • the electrostatic discharge time interval is the time when the processing module 200 receives the electrostatic warning signal and the processing module 200 stops. The time interval between when the static warning signal is received.
  • the processing module 200 may be a Micro Controller Unit (MCU), or may be a circuit module used to process an electrostatic discharge event in a chip where the electrostatic discharge protection circuit is located.
  • MCU Micro Controller Unit
  • the processing module 200 receives the electrostatic alarm signal, and executes at least one of the electrostatic discharge prevention method and the electrostatic discharge remedial method in response to the electrostatic alarm signal.
  • the electrostatic discharge prevention method includes suspending the program currently executed by the processing module 200. By executing the electrostatic discharge prevention method, an error in the program currently executed by the processing module 200 can be avoided due to the occurrence of an electrostatic discharge event.
  • the data sent by the processing module 200 during the electrostatic discharge time interval may be affected by the electrostatic discharge event and cause errors. By resending this part of the data after the electrostatic alarm signal ends, the module that receives the data sent by the processing module 200 The data without error sent by the processing module 200 can be obtained.
  • a chip with an electrostatic discharge protection circuit is provided, and the chip includes any one of the first to twelfth embodiments The electrostatic discharge protection circuit provided by the embodiment.
  • the chip provided by the embodiment of the present application includes an electrostatic discharge protection circuit.
  • the electrostatic discharge protection circuit when an electrostatic discharge event occurs, the input voltage of the RC module will rise sharply due to the instantaneous impact of electrostatic high voltage.
  • the output voltage of the RC module, the alarm voltage of the alarm module, and the discharge voltage of the bleeder module increase, the alarm voltage is greater than or equal to the output voltage of the RC module earlier than the bleeder because the alarm voltage is greater than the discharge voltage.
  • the voltage is greater than or equal to the output voltage of the RC module, make sure that the alarm module outputs an electrostatic alarm signal first to warn that the electrostatic discharge is about to be carried out, and then the discharge module performs electrostatic discharge.
  • the electrostatic discharge protection circuit provided by the embodiment of the present application can output an electrostatic alarm signal to warn that an electrostatic discharge event is about to occur before performing electrostatic discharge, so that the chip can take software or hardware preventive measures against the electrostatic discharge event. Or post-remedial measures to reduce the probability of unrecoverable hardware damage or operating errors when the chip is electrostatically discharged, thereby improving the stability of the chip's work and improving the user experience.

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Abstract

一种静电泄放保护电路及具有静电泄放保护电路的芯片，静电泄放保护电路包括RC模块(101)、告警模块(102)以及泄放模块(103)；RC模块(101)的输入电压增大时其输出电压增大；告警模块(102)接收RC模块(101)的输入电压以及RC模块(101)的输出电压，当RC模块(101)的输入电压增大时告警模块(102)的告警电压增大，并在告警电压大于或等于RC模块(101)的输出电压时，输出静电告警信号；泄放模块(103)接收RC模块(101)的输入电压以及RC模块(101)的输出电压，在RC模块(101)的输入电压增大时泄放模块(103)的泄放电压增大，并在泄放电压大于或等于RC模块(101)的输出电压时，进行静电泄放，告警电压大于泄放电压。该保护电路能够根据提前获知进行静电泄放，提高了芯片工作的稳定性，改善了用户体验。

Description

静电泄放保护电路及具有静电泄放保护电路的芯片 技术领域
本申请实施例涉及电子技术领域，尤其涉及静电泄放保护电路及具有静电泄放保护电路的芯片。
背景技术
在芯片的生产、测试、运输、使用等过程中，都会出现不同程度的静电泄放(Electro-Static Discharge，ESD)事件。静电泄放事件发生时，大量的电荷会在瞬间从外向内灌入芯片。若芯片在运行时遭遇静电泄放事件，或者外部静电耦合的冲击，会导致芯片的系统进入异常状态(例如异常复位，跑飞或死锁)，影响芯片的正常运行。芯片是否能够经受住静电泄放事件，是芯片电磁兼容(Electromagnetic Compatibility，EMC)测试的重要检测标准。
通过对芯片封装，可防止部分静电直接释放到芯片内部电路，但芯片裸露在外部的引脚(例如电源引脚，时钟引脚，通讯引脚等)，仍然会暴露在静电环境中，为了避免静电通过这部分引脚释放到芯片内部电路，可以在芯片中设置静电泄放保护电路，并通过静电泄放保护电路进行静电泄放，避免损伤芯片内部电路。例如，可以在芯片的输入输出焊盘(IO PAD)处设置静电泄放保护电路，静电泄放保护电路在进行静电泄放时可以引导静电在能够通过较大电流的输入输出电源环中释放。
虽然为芯片配备静电泄放保护电路能够避免在发生静电泄放事件时对芯片内部电路造成损坏，但由于无法提前获知静电泄放保护电路是否将要进行静电泄放，也就无法控制芯片针对静电泄放保护电路进行静电泄放采取任何软件或硬件上的防范措施。若缺少这类防范措施，一方面在复杂电磁环境下发生的静电泄放，可能会使芯片中的器件被击穿，导致芯片电流异常，或使芯片彻底损坏等，使芯片出现无法恢复的硬件损伤，另一方面，在静电泄放保护电路进行静电泄放的过程中，放电通路上各节点的电压会发生瞬间变化，芯片可能因此发生一系列的运行错误(例如异常复位，程序死锁等)，虽然这些运行错误是可通过断电或复位等外部干预来恢复的非物理性的损伤，但仍可能导致芯片在系统层面出现更大的错误，从而降低了芯片工作的稳定性，损害了用户体验。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种静电泄放保护电路及具有静电泄放保护电路的芯片，用以克服现有技术中部分或全部问题。
本申请实施例提供了一种静电泄放保护电路，静电泄放保护电路包括RC模块、告警模块以及泄放模块；
RC模块的输入电压增大时其输出电压增大；
告警模块接收RC模块的输入电压以及RC模块的输出电压，当RC模块的输入电压增大时告警模块的告警电压增大，并在告警电压大于或等于RC模块的输出电压时，输出静电告警信号；
泄放模块接收RC模块的输入电压以及RC模块的输出电压，在RC模块的输入电压增大时泄放模块的泄放电压增大，并在泄放电压大于或等于RC模块的输出电压时，进行静电泄放，告警电压大于泄放电压。
本申请实施例提供了一种具有静电泄放保护电路的芯片，具有静电泄放保护电路的芯片包括本申请实施例提供的静电泄放保护电路。
本申请实施例所提供的静电泄放保护电路中，在发生静电泄放事件时，由于在瞬间受到静电高压冲击，RC模块的输入电压会急剧上升，此时RC模块的输出电压、告警模块的告警电压以及泄放模块的泄放电压均增大，其中由于告警电压大于泄放电压，因此告警电压大于RC模块的输出电压的时刻早于泄放电压大于RC模块的输出电压的时刻，确保告警模块先输出静电告警信号，以警示将要进行静电泄放，之后泄放模块才进行静电泄放。因此本申请实施例所提供的静电泄放保护电路能够在进行静电泄放前，输出静电告警信号以警示静电泄放事件即将发生，使芯片能够针对静电泄放事件采取软件或硬件上的防范措施或事后补救措施，降低芯片在静电泄放时出现无法恢复的硬件损伤或运行错误的几率，从而提高了芯片工作的稳定性，改善了用户体验。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图；
图2为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图；
图3为本申请实施例提供的一种电压随时间变化的示意图；
图4为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图；
图5为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图；
图6为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图；
图7为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图；
图8为本申请实施例提供的一种脉冲扩展告警模块的示意性电路结构图；
图9为本申请实施例提供的一种脉冲扩展告警模块的示意性电路结构图；
图10为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图。
具体实施方式
实施本申请实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本申请实施例中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请实施例一部分实施例，而不是全部的实施例。基于本申请实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本申请实施例保护的范围。
静电荷从一个物体向另一个物体未经控制地转移的事件一般被称为静电泄放事件。在发生静电泄放事件时，大量的电荷会在瞬间从外向内灌入芯片，若芯片在运行时遭遇静电泄放事件，或者外部静电耦合的冲击，会导致芯片的系统进入异常状态，影响芯片的正常运行。
为了避免静电通过这部分引脚释放到芯片内部电路，可以在芯片中设置静电泄放保护电路(例如RC钳位静电泄放保护电路，或瞬态抑制二极管静电泄放保护电路等)，并通过静电泄放保护电路进行静电泄放，避免损伤芯片内部电路。其中，可以为保护芯片中处于不同电压域的器件，可以为每个电压域的输入输出接口分别设置对应的静电泄放保护电路。
具体的，如图1所示，静电泄放保护电路包括：电阻R0、电容C0、反相器P0以及N型晶体管N0，其中电阻R0的一端与静电泄放端V0连接，电阻R0的另一端与电容C0的一端连接，电容C0的另一端接地，电阻R0与电 容C0的连接处与反相器P0的第一输入端连接，反相器P0的第二输入端与静电泄放端V0连接，反相器P0具有接地端，N型晶体管N0的漏极与静电泄放端V0连接，N型晶体管N0的栅极与反相器P0的输出端连接，N型晶体管N0的源极接地。其中，静电泄放端V0可以与芯片中容易发生静电释放事件的引脚或元器件导通，例如，静电泄放端V0可以与芯片输入接口或芯片输出接口导通，静电泄放保护电路的接地端可以与芯片中允许通过大电流的电源环的接地端导通；又例如，静电泄放端V0可以与输入输出焊盘(IO PAD)的电源引脚连接，静电泄放保护电路的接地端也可以与输入输出焊盘的接地引脚连接，在输入输出焊盘发生静电泄放事件时引导静电在能够通过较大电流的输入输出电源环中进行释放。又例如，静电泄放端V0可以与芯片中电源环的电源端连接，静电泄放保护电路的接地端可以与芯片中电源环的接地端连接。
在图1所示的静电泄放保护电路中，电阻R0与电容C0的连接处与反相器P0的第一输入端连接，电阻R0与电容C0的连接处的电压与反相器P0的第一输入端的电压相同。反相器P0的第二输入端与静电泄放保护电路的静电泄放端V0连接，反相器P0的第二输入端的电压与静电泄放保护电路的静电泄放端V0的电压相同。反相器P0的转折电压与反相器P0的第二输入端的电压成正比。当反相器P0的第一输入端的电压与反相器P0的第二输入端的电压相同时，反相器P0的转折电压小于反相器P0的第一输入端的电压，反相器P0的输出端与反相器P0的接地端导通，反相器P0的输出端输出低电压。当反相器P0的转折电压大于或等于反相器P0的第一输入端的电压时，反相器P0的输出端与反相器P0的第二输入端导通，反相器P0的输出端输出高电压。
在芯片正常工作(即芯片中与静电泄放端V0导通的引脚或器件未发生静电泄放事件时)时，电阻R0与电容C0的连接处的电压与静电泄放端V0的电压相同，反相器P0的第一输入端的电压与反相器P0的第二输入端的电压相同，反相器P0的转折电压小于反相器P0的第一输入端的电压，反相器P0的输出端与反相器P0的接地端导通，反相器P0的输出端输出低电压，N型晶体管N0的栅极接收该低电压，N型晶体管N0的漏极与N型晶体管N0的源极截止，将静电泄放端V0与地断开，避免在芯片正常工作时将静电泄放端V0接地。
在芯片中与静电泄放端V0导通的引脚或器件发生静电泄放事件时，静电泄放端V0的电压上升，反相器P0的转折电压、电阻R0与电容C0的连接处的电压也随之上升，其中反相器P0的转折电压上升速度比电阻R0与电容 C0的连接处的电压上升的速度快，当反相器P0的转折电压大于或等于电阻R0与电容C0的连接处的电压(即反相器P0的转折电压大于或等于反相器P0的第一输入端的电压)时，反相器P0的输出端与反相器P0的第二输入端导通，反相器P0的输出端输出高电压，N型晶体管N0的栅极接收该高电压信号，N型晶体管N0的漏极与N型晶体管N0的源极导通，将静电泄放端V0与地导通，将静电泄放端V0处的静电导入地。
虽然通过为芯片配备上述静电泄放保护电路能够避免在发生静电泄放事件时对芯片内部电路造成损坏，但由于无法提前获知静电泄放保护电路是否将要进行静电泄放，也就无法控制芯片针对静电泄放保护电路进行静电泄放采取任何软件或硬件上的防范措施。若缺少这类防范措施，一方面在复杂电磁环境下发生的静电泄放，可能会使芯片中的器件被击穿，导致芯片电流异常，或使芯片彻底损坏等，使芯片出现无法恢复的硬件损伤，另一方面，在静电泄放保护电路进行静电泄放的过程中，放电通路上各节点的电压会发生瞬间变化，芯片可能因此发生一系列的运行错误(例如异常复位，程序死锁等)，虽然这些运行错误是可通过断电或复位等外部干预来恢复的非物理性的损伤，但仍可能导致芯片在系统层面出现更大的错误，从而降低了芯片工作的稳定性，损害了用户体验。
有鉴于此，本申请实施例提供一种静电泄放保护电路及具有静电泄放保护电路的芯片，用以克服现有技术中无法提前获知静电泄放保护电路是否将要进行静电泄放的技术缺陷。
本申请实施例所提供的静电泄放保护电路中，在发生静电泄放事件时，由于在瞬间受到静电高压冲击，RC模块的输入电压会急剧上升，此时RC模块的输出电压、告警模块的告警电压以及泄放模块的泄放电压均增大，其中由于告警电压大于泄放电压，因此告警电压大于RC模块的输出电压的时刻早于泄放电压大于RC模块的输出电压的时刻，确保告警模块先输出静电告警信号，以警示将要进行静电泄放，之后泄放模块才进行静电泄放。因此本申请实施例所提供的静电泄放保护电路能够在进行静电泄放前，输出静电告警信号以警示静电泄放事件即将发生，使芯片能够针对静电泄放事件采取软件或硬件上的防范措施或事后补救措施，降低芯片在静电泄放时出现无法恢复的硬件损伤或运行错误的几率，从而提高了芯片工作的稳定性，改善了用户体验。
下面结合本申请实施例附图进一步说明本申请实施例具体实现。
实施例一
图2为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图，图4为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图，如图2以及图4所示，在本申请实施例一提供的静电泄放保护电路中，静电泄放保护电路包括：RC模块101、告警模块102以及泄放模块103。其中，RC模块101的输入电压增大时其输出电压增大。
告警模块102，接收RC模块101的输入电压以及RC模块101的输出电压，当RC模块101的输入电压增大时告警模块102的告警电压增大，并在告警电压大于或等于RC模块101的输出电压时，输出静电告警信号。
泄放模块103，接收RC模块101的输入电压以及RC模块101的输出电压，在RC模块101的输入电压增大时泄放模块103的泄放电压增大，并在泄放电压大于或等于RC模块101的输出电压时，进行静电泄放，告警电压大于泄放电压。
示例性地，告警模块102输出静电告警信号为告警模块102输出的信号从低电压翻转为高电压。RC模块101的输入端可以与芯片中可能发生静电泄放事件的器件连接，例如，图5所示，RC模块101的输入端可以与输入输出焊盘(IO PAD)的电源引脚VDDIO PAD 110连接。又例如，图6所示，静电泄放保护电路的接地可以与输入输出焊盘(IO PAD)的接地VSSIO PAD 120连接。
RC模块101的输入电压的增大，会引发RC模块101的输入端发生静电泄放事件，例如发生人体模型(Human Body Model，HBM)的静电泄放事件，RC模块101的输入电压会瞬间升高。另外，在RC模块101的输入电压的增大时，RC模块101的输出电压、告警模块102的告警电压以及泄放模块103的泄放电压均增大。
本申请实施例所提供的静电泄放保护电路中，在发生静电泄放事件时，由于在瞬间受到静电高压冲击，RC模块的输入电压会急剧上升，此时RC模块的输出电压、告警模块的告警电压以及泄放模块的泄放电压均增大，其中由于告警电压大于泄放电压，因此告警电压大于或等于RC模块的输出电压的时刻早于泄放电压大于RC模块的输出电压的时刻，确保告警模块先输出静电告警信号，以警示将要进行静电泄放，之后泄放模块才进行静电泄放。因此本申请实施例所提供的静电泄放保护电路能够在进行静电泄放前，输出静电告警信号 以警示静电泄放事件即将发生，使芯片能够针对静电泄放事件采取软件或硬件上的防范措施或事后补救措施，降低芯片在静电泄放时出现无法恢复的硬件损伤或运行错误的几率，从而提高了芯片工作的稳定性，改善了用户体验。
实施例二
在实施例一的基础上，本申请实施例二提供的静电泄放保护电路中，告警模块的告警电压的初始值以及泄放模块的泄放电压的初始值均小于RC模块的输出电压的初始值，告警模块的告警电压的增速以及泄放模块的泄放电压的增速均大于RC模块的输出电压的增速。
示例性地，RC模块的输出电压的初始值为当RC模块的输入端未发生静电泄放事件(即静电泄放保护电路所在芯片处于正常运行状态)时，RC模块的输出电压的值。同样的，告警模块的告警电压的初始值可以被理解为当RC模块的输入端未发生静电泄放事件时告警模块的告警电压的值，泄放模块的泄放电压的初始值可以被理解为当RC模块的输入端未发生静电泄放事件时泄放模块的泄放电压的值。
示例性的，图3为本申请实施例提供的一种电压随时间变化的示意图，如图3所示，t0时刻为RC模块的输入端发生静电泄放事件的时刻，在t0时刻之前，静电泄放保护电路所在芯片处于正常运行状态，RC模块的输出电压Vc的初始值与RC模块的输入电压VDD相同，并且在t0时刻之前告警模块的告警电压Vth_inv_det以及泄放模块的泄放电压Vth_inv_clamp均小于RC模块的输出电压Vc，泄放模块的泄放电压Vth_inv_clamp小于告警模块的告警电压Vth_inv_de，在t0时刻前告警模块不会输出静电告警信号且泄放模块也不会进行静电泄放。
在t0时刻RC模块的输入端发生静电泄放事件，RC模块的输入电压VDD开始急剧上升，此时RC模块的输出电压VC、告警模块的告警电压Vth_inv_det以及泄放模块的泄放电压Vth_inv_clamp均开始上升。其中告警模块的告警电压Vth_inv_det以及泄放模块的泄放电压Vth_inv_clamp的增速均大于RC模块的输出电压VC的增速。
由于告警模块的告警电压Vth_inv_det始终大于泄放模块的泄放电压Vth_inv_clamp，在t1时刻告警模块的告警电压Vth_inv_det增大到与RC模块的输出电压VC相同，在t1时刻告警模块输出静电告警信号，在t1时刻后的t2时刻泄放模块的泄放电压Vth_inv_clamp也增大到与RC模块的输出电压VC相 同，在t1时刻泄放模块进行静电泄放。
示例性的，在本申请的一个实施例中，如图4所示，RC模块101可以包括串联的第一电阻211与第一电容221，第一电阻211与第一电容221的连接点为RC模块101的输出电压端。告警模块102可以包括第一反相器212。第一反相器212的第一输入端接收RC模块101的输入电压，第一反相器212的第二输入端接收RC模块101的输出电压，在告警电压大于RC模块101的输出电压时，第一反相器212的第一输入端与第一反相器212的输出端导通，输出静电告警信号。泄放模块可以包括第二反相器213以及第一开关单元223。第二反相器213的第一输入端接收RC模块101的输入电压，第二反相器213的第二输入端接收RC模块101的输出电压，在告警电压大于或等于RC模块的输出电压时，第二反相器213的输出端连接第一开关单元223的第一输入端。第一开关单元223的第一输入端连接第二反相器213的输出端，在第二反相器213的输出电压大于第一开关电压时，第一开关单元223导通，以实现静电泄放。
告警电压可以为第一反相器212的转折电压，泄放电压可以为第二反相器213的转折电压。
需要说明的是，反相器的转折电压与反相器的电源电压成正比，且反相器的转折电压小于反相器的电源电压。当反相器的转折电压小于输入反相器的电压时，反相器的输出端与反相器的接地端导通，反相器的输出端输出低电压。当反相器的转折电压大于或等于输入反相器的电压时，反相器的输出端与反相器的电源端电压导通，反相器的输出端输出高电压即电源电压。在本申请的实施例中，第一反相器212通过第一输入端接收电源电压即RC模块101的输入电压，第一反相器212通过第二输入端接收输入电压即RC模块101的输出电压；第二反相器213通过第一输入端接收电源电压即RC模块101的输入电压，第二反相器213通过第二输入端接收输入电压即RC模块101的输出电压。
当第一反向器212由NMOS管与PMOS管组成时，第一反相器212的转折电压Vth_inv_det可以根据
Figure PCTCN2020095976-appb-000001
确定，其中VDD为第一反相器212的电源电压即RC模块101的输入电压，Vthp为第一反相器212中PMOS管的导通电压，Vthn为第一反相器212中NMOS管的导通电压，βp为第一反相器212中PMOS管的跨导参数，βn为第一反相器212 中NMOS管的跨导参数。通过调整NMOS管的宽长比可以调整NMOS管的跨导参数βn，通过调整PMOS管的宽长比可以调整PMOS管的跨导参数βp。而NMOS管的导通电压Vthn以及NMOS管的跨导参数βn可以通过调整NMOS管的制备工艺来进行调整，PMOS管的导通电压Vthp以及PMOS管的跨导参数βp可以通过调整PMOS管的制备工艺来进行调整。通过调整第一反相器212中NMOS管的导通电压Vthn、NMOS管的跨导参数βn、PMOS管的导通电压Vthp以及PMOS管的跨导参数βp，可以对第一反相器212的转折电压Vth_inv_det即告警电压与RC模块101的输入电压的比值进行调整，同时还可以对告警电压的增速与RC模块101的输入电压的增速的比值进行调整。
同样的，当第二反相器213由NMOS管与PMOS管组成时，通过调整第二反相器212中NMOS管的导通电压Vthn1、NMOS管的跨导参数βn1、PMOS管的导通电压Vthp1以及PMOS管的跨导参数βp1，可以对第二反相器213的转折电压Vth_inv_clamp(即泄放电压)与RC模块101的输入电压的比值进行调整，同时还可以对泄放电压的增速与RC模块101的输入电压的增速的比值进行调整。
由于告警电压的初始值可以被理解为当RC模块101的输入端未发生静电泄放事件时告警电压的值，泄放电压的初始值可以被理解为当RC模块101的输入端未发生静电泄放事件时泄放电压的值。而RC模块101的输出电压等于第一电容221上的电压。当RC模块101的输入端未发生静电泄放事件时，第一电容221上的电压等于RC模块101的输入电压，即RC模块101的输出电压的初始值为RC模块101的输入电压，因此根据上述方法调整告警电压与RC模块101的输入电压的比值以及泄放电压与RC模块101的输入电压的比值，使告警电压以及泄放电压均小于RC模块101的输入电压，可以确保告警电压的初始值以及泄放电压的初始值均小于RC模块的输出电压的初始值。
另外，由于RC模块101的输出电压等于RC模块中第一电容221上的电压，第一电容221上的电压不能突变，第一电容221上的电压的增速小于RC模块101的输入电压的增速，从而使RC模块101的输出电压小于RC模块101的输入电压的增速。通过调整告警电压的增速与RC模块101的输入电压的增速的比值、泄放电压的增速与RC模块101的输入电压的增速的比值，可以使告警电压的增速以及泄放电压的增速均大于RC模块101的输入电压的增速，从而确保告警电压的增速以及泄放电压的增速均大于RC模块的输出电压的增 速。
通过使告警模块的告警电压的初始值以及泄放模块的泄放电压的初始值均小于RC模块的输出电压的初始值，可以使静电泄放保护电路在初始状态下，告警模块不会输出静电告警信号，泄放模块也不会进行静电泄放，确保静电泄放保护电路不会影响芯片中其他组件的正常工作。而告警模块的告警电压的增速大于RC模块的输出电压的增速，能够使告警模块的告警电压随着时间的增长，增加至大于RC模块的输出电压，使输出告警模块输出静电告警信号；同样的，泄放模块的泄放电压的增速均大于RC模块的输出电压的增速，能够使泄放模块的泄放电压随着时间的增长，增加至大于RC模块的输出电压，使泄放模块进行静电泄放。
实施例三
在实施例一的基础上，如图4所示，本申请实施例三提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102以及泄放模块103。其中，RC模块101包括串联的第一电阻211与第一电容221，第一电容221一端接地，第一电容221的另一端与第一电阻211连接，第一电阻211的另一端为RC模块101的输入电压端，第一电阻211与第一电容221的连接点为RC模块101的输出电压端。
具体的，第一电阻211也可以为多个串联或并联的电阻，本申请的实施例对此不做限制，图4中以第一电阻211为一个电阻为例进行展示。第一电容221也可以为多个串联或并联的电容，本申请的实施例对此不做限制，图4中以第一电容221为一个电容为例进行展示。
串联的第一电阻211与第一电容221形成RC电路结构，当从RC模块101的输入电压端输入的电压增大时，第一电容221上的电压也增大。通过调整第一电阻211的电阻值以及第一电容221的电容值，可以对RC电路结构的充电时间常数进行调整，由于RC电路结构的充电时间常数与第一电容221上的电压的增速正相关，因此通过调整第一电阻211的电阻值以及第一电容221的电容值，可以对第一电容221上的电压的增速即RC模块101的输出电压端所输出电压的增速进行调整。
泄放模块103在泄放电压大于或等于RC模块101的输出电压时进行静电泄放。若RC模块101的输入电压的增速以及泄放电压的增速均不变，通过减慢RC模块101的输出电压端所输出电压的增速，可以提前泄放电压大于或 等于RC模块101的输出电压的时刻，即提前泄放模块103进行静电泄放的时刻；通过加快RC模块101的输出电压端所输出电压的增速，可以延迟泄放电压大于或等于RC模块101的输出电压的时刻，即延迟提前泄放模块103进行静电泄放的时刻。
告警模块102在告警电压大于或等于RC模块101的输出电压时输出静电告警信号，若RC模块101的输入电压的增速以及告警电压的增速均不变时，通过减慢RC模块101的输出电压端所输出电压的增速，可以提前告警电压大于或等于RC模块101的输出电压的时刻，即提前告警模块102输出静电告警信号的时刻；通过加快RC模块101的输出电压端所输出电压的增速，可以延迟告警电压大于或等于RC模块101的输出电压的时刻，即延迟告警模块102输出静电告警信号的时刻。
综上所述，通过调整第一电阻211的电阻值以及第一电容221的电容值，可以在RC模块101的输入电压的增速、泄放电压的增速以及告警电压的增速均不变的前提下，对泄放模块103进行静电泄放的时刻以及告警模块102输出静电告警信号的时刻进行调整。
优选的，第一电阻211的电阻值可以为1mΩ，第一电容221的电容值可以为1pF。
实施例四
在实施例一的基础上，如图4所示，本申请实施例四提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102以及泄放模块103。其中，告警模块102包括第一反相器212。第一反相器212，用于通过第一输入端接收RC模块101的输入电压，通过第一反相器212的第二输入端接收RC模块101的输出电压，在告警电压大于RC模块101的输出电压时，第一反相器212的第一输入端与第一反相器212的输出端导通，输出静电告警信号。
具体的，第一反相器212的第一输入端与第一反相器212的输出端导通时，第一反相器212的输出端可以输出RC模块101的输入电压，使静电告警信号为高电压。
第一反相器212可以为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)电路，也可以由至少两个场效应管组成，或由多个逻辑门电路组成等，本申请的实施例在此不对第一反相器212的具体 实现方式做出具体限制。
告警电压可以为第二反相器213的转折电压。需要说明的是，反相器的转折电压与反相器的电源电压成正比，且反相器的转折电压小于反相器的电源电压。当反相器的转折电压小于反相器的输入电压时，反相器的输出端接地，反相器的输出端输出低电压。当反相器的转折电压大于或等于输入反相器的电压时，反相器的输出端与反相器的电源端电压导通，反相器的输出端输出高电压即电源电压。在本实施例中，第一反相器212通过第一输入端接收电源电压即RC模块101的输入电压，第一反相器212通过第二输入端接收输入电压即RC模块101的输出电压。
示例性的，当第一反相器212由NMOS管与PMOS管组成时，告警电压可以为第一反相器212的转折电压Vth_inv_det。第一反相器212的转折电压Vth_inv_det可以根据
Figure PCTCN2020095976-appb-000002
确定，其中VDD为第一反相器212的电源电压即RC模块101的输入电压，Vthp为第一反相器212中PMOS管的导通电压，Vthn为第一反相器212中NMOS管的导通电压，βp为第一反相器212中PMOS管的跨导参数，βn为第一反相器212中NMOS管的跨导参数。通过调整NMOS管的宽长比可以调整NMOS管的跨导参数βn，通过调整PMOS管的宽长比可以调整PMOS管的跨导参数βp。NMOS管的导通电压Vthn以及NMOS管的跨导参数βn可以通过调整NMOS管的制备工艺来进行调整，PMOS管的导通电压Vthp以及PMOS管的跨导参数βp可以通过调整PMOS管的制备工艺来进行调整。通过调整第一反相器212中NMOS管的导通电压Vthn、NMOS管的跨导参数βn、PMOS管的导通电压Vthp以及PMOS管的跨导参数βp，可以对第一反相器212的转折电压Vth_inv_det即告警电压与RC模块101的输入电压的比值进行调整，同时还可以对告警电压的增速与RC模块101的输入电压的增速的比值进行调整。
可选地，在本申请的一个实施例中，第一反相器212在告警电压小于RC模块101的输出电压时，第一反相器212的接地端与第一反相器212的输出端导通。
具体的，由于告警电压小于RC模块101的输出电压时，可以理解为静电泄放事件已经结束，第一反相器212在告警电压小于RC模块101的输出电压时，第一反相器212的接地端与第一反相器212的输出端导通，第一反相器 212的输出端的输出电压为0，当第一反相器212的输出端的输出电压为0时，可以认为第一反相器212的输出端未输出静电告警信号，从而在静电泄放事件结束后不再报警，避免芯片在静电泄放事件已经结束后执行不需要的处理操作，节省了芯片的处理资源。
实施例五
在实施例一的基础上，如图4所示，本申请实施例五提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102以及泄放模块103。其中，泄放模块包括第二反相器213以及第一开关单元223。
第二反相器213的第一输入端接收RC模块101的输入电压，第二反相器213的第二输入端接收RC模块101的输出电压，在告警电压大于或等于RC模块的输出电压时，第二反相器213的输出端连接第一开关单元223的第一输入端。
第一开关单元223的第一输入端连接第二反相器213的输出端，在第二反相器213的输出电压大于第一开关电压时，第一开关单元223导通，以实现静电泄放。
具体的，第一开关单元223的第二输入端与RC模块101的输入端连接，第一开关单元223的输出端接地，当第二反相器213的输出电压大于第一开关电压时，第一开关单元223的第二输入端与第一开关单元223的输出端导通，将RC模块101的输入端处的静电导向地，以实现静电泄放。
泄放电压可以为第二反相器213的转折电压。需要说明的是，反相器的转折电压与反相器的电源电压成正比，且反相器的转折电压小于反相器的电源电压。当反相器的转折电压小于反相器的输入电压时，反相器的输出端接地，反相器的输出端输出低电压。当反相器的转折电压大于或等于输入反相器的电压时，反相器的输出端与反相器的电源端电压导通，反相器的输出端输出高电压即电源电压。在本实施例中，第二反相器213通过第一输入端接收电源电压即RC模块101的输入电压，第二反相器213通过第二输入端接收输入电压即RC模块101的输出电压。
示例性的，当第二反向器213由NMOS管与PMOS管组成时，第二反相器213的转折电压Vth_inv_clamp可以根据
Figure PCTCN2020095976-appb-000003
确定，其中VDD为第二反向器213的电 源电压即RC模块101的输入电压，Vthp1为第二反向器213中PMOS管的导通电压，Vthn1为第二反向器213中NMOS管的导通电压，βp1为第二反向器213中PMOS管的跨导参数，βn1为第二反向器213中NMOS管的跨导参数。通过调整NMOS管的宽长比可以调整NMOS管的跨导参数βn1，通过调整PMOS管的宽长比可以调整PMOS管的跨导参数βp1。而NMOS管的导通电压Vthn1以及NMOS管的跨导参数βn1可以通过调整NMOS管的制备工艺来进行调整，PMOS管的导通电压Vthp1以及PMOS管的跨导参数βp1可以通过调整PMOS管的制备工艺来进行调整。通过调整第二反向器213中NMOS管的导通电压Vthn1、NMOS管的跨导参数βn1、PMOS管的导通电压Vthp1以及PMOS管的跨导参数βp1，可以对第二反向器213的转折电压Vth_inv_clamp即泄放电压与RC模块101的输入电压的比值进行调整，同时还可以对告警电压的增速与RC模块101的输入电压的增速的比值进行调整。
第一开关单元223可以由一个或多个晶体管组成，在第一开关单元223包括多个晶体管时，多个晶体管可以在第二反相器213的输出电压大于第一开关电压时分别做出相应的开关动作，使第一开关单元223导通。本申请的实施例不对第一开关单元223的组成做出具体限定。在图4中，以第一开关单元223包括单个N型晶体管为例进行说明，其中N型晶体管的栅极接收第二反相器213的输出电压，N型晶体管的漏极与RC模块101的输入端连接，N型晶体管的源极接地，当N型晶体管的栅极处的电压大于第一开关电压时，N型晶体管的漏极与N型晶体管的源极导通，通过N型晶体管将RC模块101的输入端处的静电导向地，以实现静电泄放。
实施例六
在实施例一至五中任一个实施例的基础上，图7为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图，如图7所示，本申请实施例六提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102以及泄放模块103。其中，静电泄放保护电路还包括脉冲扩展告警模块104，脉冲扩展告警模块104对静电告警信号延时，输出持续时间大于静电告警信号的持续时间的延时静电告警信号。
具体的，静电泄放事件的持续时间往往较短(例如，静电泄放事件在持续约100nS后逐渐消失)，告警信号发生时，芯片采取硬件上的防范措施的速度可能很快，但软件处理的速度可能无法及时针对告警信号做出响应，通过脉 冲扩展告警模块104对静电告警信号延时，输出持续时间大于静电告警信号的延时静电告警信号，可以方便微控制单元MCU或静电泄放保护电路所在芯片中用于处理静电泄放事件的电路模块在未及时针对告警信号做出响应时，针对持续时间大于静电告警信号的延时静电告警信号做出响应，例如进行后续纠错等，从而提高了芯片工作的稳定性，改善了用户体验。
实施例七
在实施例六的基础上，图8为本申请实施例提供的一种脉冲扩展告警模块的示意性电路结构图，如图7以及图8所示，本申请实施例七提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102、泄放模块103以及脉冲扩展告警模块104，其中脉冲扩展告警模块104包括第二开关单元114、第三开关单元124、第二电容134、第三反相器144。
第二开关单元114，在第二开关单元114的第一输入端接收静电告警信号时导通，在第二开关单元114的第一输入端未接收静电告警信号时断开。
第三开关单元124，在第三开关单元124的第一输入端接收静电告警信号时断开，在第三开关单元124的第一输入端未接收静电告警信号时导通。
第二电容134，用于在第二开关单元114断开且第三开关单元134导通时充电，在第二开关单元114导通且第三开关单元134断开时放电。
第三反相器144的第一输入端接收第二电容134的电压，在第二电容134的电压小于脉冲扩展电压时，输出延时静电告警信号。
具体的，第二开关单元114的第一输入端与告警模块102的输出端连接，第二开关单元114的第二输入端与第二电容134的第一端连接，第二开关单元114的输出端接地。第三开关单元124的第一输入端与告警模块102的输出端连接，第三开关单元124的第二输入端接收RC模块101的输入电压，第三开关单元124的输出端与第二电容134第一端连接，第二电容134第二端接地。第三反相器144的第二输入端接收RC模块101的输入电压，第三反相器144具有接地端。
当告警模块102的输出端输出静电告警信号时，第二开关单元114的第一输入端接收告警模块102的输出端输出的静电告警信号，第二开关单元114的第二输入端与第二开关单元114的输出端导通，将第二电容134的第一端接地，同时第三开关单元124的第一输入端接收告警模块102的输出端输出的静电告警信号，第三开关单元124的第二输入端与第三开关单元124的输出端断 开，第三开关单元124的输出端未向第二电容134的第一端输出任何电压，第二电容134的第一端进行放电，使第二电容134的电压处于小于脉冲扩展电压的状态，第三反相器144的第一输入端接收第二电容134的电压，通过第三反相器144的输出端输出延时静电告警信号。
当告警模块102的输出端未输出静电告警信号时，第二开关单元114的第一输入端未接收告警模块102的输出端输出的静电告警信号，第二开关单元114的第二输入端与第二开关单元114的输出端断开，使第二电容134第一端与地断开，同时第三开关单元124的第一输入端未接收告警模块102的输出端输出的静电告警信号时，第三开关单元124的第二输入端与第三开关单元124的输出端导通，通过第三开关单元124的输出端向第二电容134第一端输出RC模块101的输入电压，对第二电容134进行充电使第二电容134的电压增大。第三反相器144的第一输入端接收第二电容134的电压，当第二电容134的电压未增大至大于或等于脉冲扩展电压时，第三反相器144仍输出延时静电告警信号；当第二电容134的电压增大至大于或等于脉冲扩展电压时，第三反相器144停止输出延时静电告警信号，其中从告警模块102的输出端未输出静电告警信号的时刻开始，到第二电容134的电压增大至大于或等于脉冲扩展电压的时刻为止的时间长度，可以理解为延时静电告警信号的持续时间与静电告警信号的持续时间之间的时间差。
需要说明的是，第三反相器144输出延时静电告警信号的时刻晚于告警模块102输出静电告警信号的时刻，但两个时刻之间的时间差非常短，可以被忽略。
第二开关单元114可以由一个或多个晶体管组成，在第二开关单元114包括多个晶体管时，多个晶体管可以在第二开关单元114的第一输入端接收静电告警信号时分别做出相应的开关动作使第二开关单元114导通，也可以在第二开关单元114的第一输入端未接收静电告警信号时分别做出相应的开关动作使第二开关单元114断开。本申请的实施例不对第二开关单元114的组成做出具体限定。
第三开关单元124可以由一个或多个晶体管组成，在第三开关单元124包括多个晶体管时，多个晶体管可以在第三开关单元124的第一输入端接收静电告警信号时分别做出相应的开关动作使第三开关单元124导通，也可以在第三开关单元124的第一输入端未接收静电告警信号时分别做出相应的开关动作 使第三开关单元124断开。本申请的实施例不对第三开关单元124的组成做出具体限定。第二电容134也可以包括多个串联或并联的电容，本申请的实施例对此不做限制。
第三反相器144可以为互补金属氧化物半导体电路，也可以由至少两个场效应管组成，或由多个逻辑门电路组成等，本申请的实施例在此不对第三反相器144的具体实现方式做出具体限制。
其中，脉冲扩展电压可以为第三反相器144的转折电压。需要说明的是，反相器的转折电压与反相器的电源电压成正比，且反相器的转折电压小于反相器的电源电压。当反相器的转折电压小于反相器的输入电压时，反相器的输出端接地，反相器的输出端输出低电压。当反相器的转折电压大于或等于输入反相器的电压时，反相器的输出端与反相器的电源端电压导通，反相器的输出端输出高电压即电源电压。在本实施例中，第三反相器144通过第二输入端接收电源电压即RC模块101的输入电压，第三反相器144通过第一输入端接收输入电压即第二电容134的电压。
示例性的，当第三反相器144由NMOS管与PMOS管组成时，脉冲扩展电压可以为第三反相器144的转折电压Vth_inv_pulse。第三反相器144的转折电压Vth_inv_pulse可以根据
Figure PCTCN2020095976-appb-000004
确定，其中VDD为第三反相器144的电源电压即RC模块101的输入电压，Vthp2为第三反相器144中PMOS管的导通电压，Vthn2为第三反相器144中NMOS管的导通电压，βp2为第三反相器144中PMOS管的跨导参数，βn2为第三反相器144中NMOS管的跨导参数。通过调整NMOS管的宽长比可以调整NMOS管的跨导参数βn2，通过调整PMOS管的宽长比可以调整PMOS管的跨导参数βp2。而NMOS管的导通电压Vthn2以及NMOS管的跨导参数βn2可以通过调整NMOS管的制备工艺来进行调整，PMOS管的导通电压Vthp2以及PMOS管的跨导参数βp2可以通过调整PMOS管的制备工艺来进行调整。通过调整第三反相器144中NMOS管的导通电压Vthn2、NMOS管的跨导参数βn2、PMOS管的导通电压Vthp2以及PMOS管的跨导参数βp2，可以对第三反相器144的转折电压Vth_inv_pulse即脉冲扩展电压与RC模块101的输入电压的比值进行调整，同时还可以对脉冲扩展电压的增速与RC模块101的输入电压的增速的比值进行调整。
需要说明的是，由于在第二电容134的电压充电到大于或等于脉冲扩展电压时(即第二电容134的电压增大至大于或等于脉冲扩展电压时)，输入第三反相器144的第一输入端的电压大于或等于脉冲扩展电压，第三反相器144停止输出延时静电告警信号，因此通过调整第二电容134的电压的充电速度，可以调整延时静电告警信号的持续时间。其中，通过调整第三开关单元124的第一输入端与第三开关单元124的输出端之间的电阻值以及第二电容134的电容值，可以调整第三开关单元124与第二电容134之间的RC时间常数，从而对第二电容134的充电速度进行调整。
实施例八
在实施例七的基础上，如图7以及图8所示，本申请实施例八提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102、泄放模块103以及脉冲扩展告警模块104，其中脉冲扩展告警模块104包括第二开关单元114、第三开关单元124、第二电容134、第三反相器144。其中第三反相器114的第二输入端与RC模块101的输入电压端连接，在第二电容134的电压小于脉冲扩展电压时，第三反相器144的第二输入端与第三反相器144的输出端导通。
其中，第三反相器144的第二输入端接收RC模块101的输入电压，在第三反相器144的第一输入端接收的第二电容134的电压小于脉冲扩展电压时，第三反相器144的第二输入端与第三反相器144的输出端导通，第三反相器144的输出端输出RC模块101的输入电压信号，使延时静电告警信号为高电压，确保延时静电告警信号的电压值能够满足需求。
进一步的，在第三反相器144的第一输入端接收的第二电容134的电压大于或等于脉冲扩展电压时，第三反相器144的接地端与第三反相器144的输出端导通，延时静电告警信号为高电压，第三反相器144的输出端停止输出延时静电告警信号。
实施例九
在实施例八的基础上，如图7以及图8所示，本申请实施例九提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102、泄放模块103以及脉冲扩展告警模块104，其中脉冲扩展告警模块104包括第二开关单元114、第三开关单元124、第二电容134、第三反相器144。
其中第三开关单元124包括P型晶体管，P型晶体管的栅极接收所述静 电告警信号，P型晶体管的漏极接收RC模块11的输入电压，P型晶体管的源极与第二电容134连接，P型晶体管在静电告警信号大于或等于第一开关阈值时导通。
由于在芯片中设置晶体管的工艺较为成熟，成本较低，第三开关单元144包括P型晶体管，可以在制造成本较低的前提下使第三开关单元144实现在静电告警信号大于或等于第一开关阈值时导通的功能。
实施例十
在实施例八的基础上，如图7以及图9所示，本申请实施例十提供的静电泄放保护电路中，静电泄放保护电路包括RC模块101、告警模块102、泄放模块103以及脉冲扩展告警模块104，其中脉冲扩展告警模块104包括第二开关单元114、第三开关单元124、第二电容134、第三反相器144。
其中第三开关单元124包括n个P型晶体管，n≥2，其中n为自然数，n个P型晶体管的栅极接收静电告警信号，n个P型晶体管中第一级P型晶体管的漏极接收RC模块11的输入电压，n个P型晶体管中前一级P型晶体管的源极与相邻后一级P型晶体管的漏极连接，n个P型晶体管中第n级P型晶体管的源极与第二电容134连接，n个P型晶体管在静电告警信号大于或等于第一开关阈值时导通。
通过第三开关单元144包括n个P型晶体管，n≥2，与第三开关单元144仅包括一个晶体管相比，可以使第三开关单元144在静电告警信号大于或等于第一开关阈值时导通的同时，提高第三开关单元144的电阻，延长第二电容134的充电时间，从而延长延时静电告警信号的持续时间，与通过调整第二电容134的结构或在第三开关单元144中设置电阻，以延长延时静电告警信号持续时间的方案相比较，该方案成本较低。
实施例十一
图10为本申请实施例提供的一种静电泄放保护电路的示意性电路结构图，如图10所示，在实施例一的基础上，本申请实施例十一提供的静电泄放保护电路中，静电泄放保护电路还包括处理模块200。
处理模块200接收静电告警信号，并响应于静电告警信号执行静电泄放防范方法以及静电泄放补救方法中至少一种。
静电泄放防范方法包括暂停处理模块200当前执行的程序。
静电泄放补救方法包括在静电告警信号结束后重新发送处理模块200在 静电泄放时间区间内所发送的数据，静电泄放时间区间为处理模块200收到静电告警信号的时刻与处理模块200停止收到静电告警信号的时刻之间的时间区间。
具体的，处理模块200可以为微控制单元(Micro Controller Unit，MCU)，也可以为静电泄放保护电路所在芯片中用于处理静电泄放事件的电路模块。
本申请实施例所提供的静电泄放保护电路中，处理模块200接收静电告警信号，并响应于静电告警信号执行静电泄放防范方法以及静电泄放补救方法中至少一种。其中静电泄放防范方法包括暂停处理模块200当前执行的程序，通过执行静电泄放防范方法，可以避免因发生静电泄放事件而导致处理模块200当前执行的程序出错。而处理模块200在静电泄放时间区间内所发送的数据可能因受静电泄放事件影响而出错，通过在静电告警信号结束后重新发送这部分数据，可以使接收处理模块200所发送数据的模块能够获取处理模块200发送的未出错的数据。
实施例十二
在实施例一至十一中任意一个实施例的基础上，如本申请实施例十二提供一种具有静电泄放保护电路的芯片，该芯片包括实施例一至十二中任意一个实施例中任意一个实施例所提供的静电泄放保护电路。
本申请实施例所提供的芯片包括静电泄放保护电路，在该静电泄放保护电路中，在发生静电泄放事件时，由于在瞬间受到静电高压冲击，RC模块的输入电压会急剧上升，此时RC模块的输出电压、告警模块的告警电压以及泄放模块的泄放电压均增大，其中由于告警电压大于泄放电压，因此告警电压大于或等于RC模块的输出电压的时刻早于泄放电压大于或等于RC模块的输出电压的时刻，确保告警模块先输出静电告警信号，以警示将要进行静电泄放，之后泄放模块才进行静电泄放。因此本申请实施例所提供的静电泄放保护电路能够在进行静电泄放前，输出静电告警信号以警示静电泄放事件即将发生，使芯片能够针对静电泄放事件采取软件或硬件上的防范措施或事后补救措施，降低芯片在静电泄放时出现无法恢复的硬件损伤或运行错误的几率，从而提高了芯片工作的稳定性，改善了用户体验。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然，在实施本申请时可以把各单元的功能在同一个或多个硬件中实现。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非 排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (14)

  1. 一种静电泄放保护电路，其特征在于，所述静电泄放保护电路包括RC模块、告警模块以及泄放模块；
    所述RC模块的输入电压增大时其输出电压增大；
    所述告警模块接收所述RC模块的输入电压以及所述RC模块的输出电压，当所述RC模块的输入电压增大时所述告警模块的告警电压增大，并在所述告警电压大于或等于所述RC模块的输出电压时，输出静电告警信号；
    所述泄放模块接收所述RC模块的输入电压以及所述RC模块的输出电压，在所述RC模块的输入电压增大时所述泄放模块的泄放电压增大，并在所述泄放电压大于或等于所述RC模块的输出电压时，进行静电泄放，所述告警电压大于所述泄放电压。
  2. 根据权利要求1所述的静电泄放保护电路，其特征在于，所述告警模块的告警电压的初始值以及所述泄放模块的泄放电压的初始值均小于所述RC模块的输出电压的初始值，所述告警模块的告警电压的增速以及所述泄放模块的泄放电压的增速均大于所述RC模块的输出电压的增速。
  3. 根据权利要求1所述的静电泄放保护电路，其特征在于，所述RC模块包括串联的第一电阻与第一电容，所述第一电容一端接地，所述第一电容的另一端与所述第一电阻连接，所述第一电阻的另一端为所述RC模块的输入电压端，所述第一电阻与所述第一电容的连接点为所述RC模块的输出电压端。
  4. 根据权利要求1所述的静电泄放保护电路，其特征在于，所述告警模块包括第一反相器；
    所述第一反相器的第一输入端接收所述RC模块的输入电压，其第二输入端接收所述RC模块的输出电压，在所述告警电压大于或等于所述RC模块的输出电压时，所述第一反相器的第二输入端与所述第一反相器的输出端导通，输出所述静电告警信号。
  5. 根据权利要求4所述的静电泄放保护电路，其特征在于，所述第一反相器在所述告警电压小于所述RC模块的输出电压时，所述第一反相器的接地端与所述第一反相器的输出端导通。
  6. 根据权利要求1所述的静电泄放保护电路，其特征在于，所述泄放模块包括第二反相器以及第一开关单元；
    所述第二反相器的第一输入端接收所述RC模块的输入电压，第二输入端接收所述RC模块的输出电压，在所述告警电压大于或等于所述RC模块的输 出电压时，所述第二反相器的第一输入端与所述第二反相器的输出端导通；
    所述第一开关单元的第一输入端连接所述第二反相器的输出端，在所述第二反相器的输出电压大于第一开关电压时，所述第一开关单元导通，以实现静电泄放。
  7. 根据权利要求1-6中任一项所述的静电泄放保护电路，其特征在于，所述静电泄放保护电路还包括脉冲扩展告警模块，所述脉冲扩展告警模块对所述静电告警信号延时，输出持续时间大于所述静电告警信号的持续时间的延时静电告警信号。
  8. 根据权利要求7所述的静电泄放保护电路，其特征在于，所述脉冲扩展告警模块包括第二开关单元、第三开关单元、第二电容、第三反相器；
    所述第二开关单元，在所述第二开关单元的第一输入端接收所述静电告警信号时导通，在所述第二开关单元的第一输入端未接受所述静电告警信号时断开；
    所述第三开关单元，在所述第三开关单元的第一输入端接收所述静电告警信号时断开，在所述第三开关单元的第一输入端未接受所述静电告警信号时导通；
    所述第二电容，在所述第二开关单元断开且所述第三开关单元导通时充电，在所述第二开关单元导通且所述第三开关单元断开时放电；
    所述第三反相器的第一输入端接收所述第二电容的电压，在所述第二电容的电压小于脉冲扩展电压时，输出所述延时静电告警信号。
  9. 根据权利要求8所述的静电泄放保护电路，其特征在于，所述第三反相器的第二输入端与所述RC模块的输入电压端连接，在所述第二电容的电压小于所述脉冲扩展电压时，所述第二反相器的第二输入端与所述第二反相器的输出端导通。
  10. 根据权利要求9所述的静电泄放保护电路，其特征在于，所述第三反相器在所述第二电容的电压大于或等于所述脉冲扩展电压时，所述第三反相器的接地端与所述第三反相器的输出端导通。
  11. 根据权利要求8所述的静电泄放保护电路，其特征在于，所述第三开关单元包括n个P型晶体管，n≥2；
    所述n个P型晶体管的栅极接收所述静电告警信号，所述n个P型晶体管中第一级P型晶体管的漏极接收所述RC模块的输入电压，所述n个P型晶体 管中前一级P型晶体管的源极与相邻后一级P型晶体管的漏极连接，所述n个P型晶体管中第n级P型晶体管的源极与所述第二电容连接，所述n个P型晶体管在所述静电告警信号大于或等于所述第一开关阈值时导通。
  12. 根据权利要求8所述的静电泄放保护电路，其特征在于，所述第三开关单元包括P型晶体管；
    所述P型晶体管的栅极接收所述静电告警信号，所述P型晶体管的漏极接收所述RC模块的输入电压，所述P型晶体管的源极与所述第二电容连接，所述P型晶体管在所述静电告警信号大于或等于所述第一开关阈值时导通。
  13. 根据权利要求1所述的静电泄放保护电路，其特征在于，所述静电泄放保护电路还包括处理模块：
    所述处理模块接收所述静电告警信号，并响应于所述静电告警信号执行静电泄放防范方法以及静电泄放补救方法中至少一种；
    所述静电泄放防范方法包括暂停所述处理模块当前执行的程序；
    所述静电泄放补救方法包括在所述告警模块停止输出所述静电告警信号后重新发送所述处理模块在静电泄放时间区间内所发送的数据，所述静电泄放时间区间为所述处理模块收到所述静电告警信号的时刻与所述处理模块停止收到所述静电告警信号的时刻之间的时间区间。
  14. 一种具有静电泄放保护电路的芯片，其特征在于，包括如权利要求1至13中任意一项所述的静电泄放保护电路。
PCT/CN2020/095976 2020-06-12 2020-06-12 静电泄放保护电路及具有静电泄放保护电路的芯片 WO2021248501A1 (zh)

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