WO2023102697A1 - 静电防护电路、芯片和终端 - Google Patents

静电防护电路、芯片和终端 Download PDF

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Publication number
WO2023102697A1
WO2023102697A1 PCT/CN2021/135828 CN2021135828W WO2023102697A1 WO 2023102697 A1 WO2023102697 A1 WO 2023102697A1 CN 2021135828 W CN2021135828 W CN 2021135828W WO 2023102697 A1 WO2023102697 A1 WO 2023102697A1
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Prior art keywords
transistor
voltage
voltage terminal
circuit
switch
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PCT/CN2021/135828
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English (en)
French (fr)
Inventor
高鑫
王黎晖
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180043997.7A priority Critical patent/CN116670957A/zh
Priority to PCT/CN2021/135828 priority patent/WO2023102697A1/zh
Publication of WO2023102697A1 publication Critical patent/WO2023102697A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Definitions

  • the present application relates to the field of chip technology, in particular to an electrostatic protection circuit, a chip and a terminal.
  • ESD electrostatic discharge
  • this application provides an electrostatic protection circuit, chip and terminal.
  • the present application provides an electrostatic protection circuit, which includes a control circuit, a first switch, a first voltage terminal, a second voltage terminal and a ground terminal; the second voltage terminal is used to provide the first voltage terminal with Operating Voltage.
  • the first switch and the protected device are coupled in parallel between the first voltage terminal and the ground terminal.
  • the control circuit is used to send a control signal to the first switch when it detects that the first voltage terminal sends an electrostatic signal to the second voltage terminal; the first switch is used to conduct under the control of the control signal.
  • the first switch by coupling the first switch between the first voltage terminal and the ground terminal, the first switch is turned on under the control of the control signal, so that the first voltage terminal, the first switch, and the ground terminal form a path.
  • the electrostatic voltage on the first voltage terminal can be discharged through the first switch, so as to prevent the electrostatic voltage on the first voltage terminal from being too high, thereby preventing the high electrostatic voltage from forming a larger peak value when it is discharged instantaneously The current will cause impact on the protected device and damage the protected device.
  • the first switch and the protected device are coupled in parallel between the first voltage end and the ground end.
  • the static electricity on the first voltage terminal can be discharged through the path of the first voltage terminal, the first switch, and the ground terminal.
  • the present application does not need to pass through the second voltage terminal when discharging static electricity, which can shorten the static discharge path and reduce the parasitic resistance on the static discharge path.
  • the present application can also control that no other devices other than the first switch are integrated on the path of the first voltage terminal, the first switch, and the ground terminal. In this way, compared with the related art, the total voltage on the path from the first voltage terminal to the ground terminal of the present application is no longer affected by the impedance of other devices.
  • the total voltage on the path from the first voltage terminal to the ground terminal can be greatly reduced, preventing the total voltage on the path from the first voltage terminal to the ground terminal from being greater than Breakdown voltage threshold, causing the protected device to be damaged.
  • the electrostatic protection circuit further includes a second switch; the second switch is coupled between the second voltage terminal and the ground terminal; When sending an electrostatic signal, send a control signal to the second switch; the second switch is used to conduct under the control of the control signal.
  • the first voltage terminal discharges at least part of the electrostatic voltage through the second switch, reduces the voltage value of the first voltage terminal, and prevents the voltage of the first voltage terminal from being too large, and the power supply provides an operating voltage to the first voltage terminal through the second voltage terminal.
  • the first switch is mistakenly turned on, thereby preventing the working voltage from leaking through the first switch.
  • control circuit includes a detection circuit, and the detection circuit is connected in series between the second voltage terminal and the ground terminal; when it is detected that the first voltage terminal sends an electrostatic signal to the second voltage terminal, output a detection circuit Signal.
  • the detection signal can be used as a control signal; the detection circuit is also used to send the detection signal to the first switch and the second switch.
  • the detection circuit can be used to detect that when the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and it is directly input to the second switch The signal is detected, and the first switch and the second switch are controlled to conduct, so as to realize electrostatic discharge through the first switch and the second switch.
  • the control circuit further includes a first inverter; a detection circuit, configured to send a detection signal to the first inverter when detecting that the first voltage terminal sends an electrostatic signal to the second voltage terminal;
  • the first inverter is used to invert the detection signal to obtain a control signal and output the control signal; the detection signal and the control signal are at high and low levels.
  • the detection circuit can be used to detect that when the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and a detection signal is output. After that, the detection signal is sent to the first inverter, and the first inverter inverts the detection signal, and then outputs the inverted control signal.
  • the first inverter can send a control signal to the second switch, so as to control the second switch to be turned on, so as to realize electrostatic discharge through the second switch.
  • a control signal may also be sent to the first switch to control the conduction of the first switch, so as to realize electrostatic discharge through the first switch.
  • the solution in which the control circuit includes the first inverter can be applied in a scenario where the path from the detection circuit to the first switch and the second switch is too long. It is avoided that the signal output by the detection circuit is consumed on the path due to an overly long path from the detection circuit to the first switch and the second switch, so that the first switch and the second switch cannot be fully turned on.
  • control circuit further includes a second inverter and a detection circuit, further configured to send a detection signal to the second inverter when it detects that the first voltage terminal sends an electrostatic signal to the second voltage terminal.
  • the second inverter is used to invert the detection signal to obtain a control signal, and send the control signal to the first switch; the detection signal and the control signal are at high and low levels to control the conduction of the first switch, so as to realize passing through the first switch.
  • a switch for electrostatic discharge However, the first inverter still sends the control signal to the second switch to control the conduction of the second switch to realize electrostatic discharge through the second switch.
  • the detection circuit of this solution can directly send the detection signal to the second inverter.
  • the second inverter also has channel impedance, the coupling path between the second inverter and the first switch is short, and the second inverter After the device transmits the voltage of the first voltage terminal to the first switch, the first switch can be fully turned on. It can also be said that the first switch is strongly turned on, which will not affect the electrostatic discharge efficiency of the first voltage terminal through the first switch. Therefore, compared with the above scheme in which the control circuit includes the first inverter but does not include the second inverter, this scheme can improve the electrostatic discharge efficiency of the first voltage terminal through the first switch.
  • the above-mentioned first switch may include a first transistor
  • the second switch may include a second transistor
  • the above-mentioned first inverter includes a first P-type transistor and a first N-type transistor.
  • the gate of the second transistor is coupled to the first inverter, the first pole is coupled to the second voltage terminal, and the second pole is coupled to the ground terminal.
  • the gate of the first P-type transistor is coupled to the output terminal of the detection circuit, the first pole is coupled to the second voltage terminal, and the second pole is coupled to the gates of the first transistor and the gate of the second transistor.
  • the gate of the first N-type transistor is coupled to the output terminal of the detection circuit, the first pole is coupled to the ground terminal, and the second pole is coupled to the gates of the first transistor and the second transistor.
  • the above-mentioned first switch may include a first transistor
  • the second switch may include a second transistor
  • the above-mentioned first inverter includes a first P-type transistor and a first N-type transistor
  • the above-mentioned second inverter includes a second a P-type transistor and a second N-type transistor.
  • the first pole of the second transistor is coupled to the second voltage terminal, and the second pole is coupled to the ground terminal.
  • the gate of the first P-type transistor is coupled to the output terminal of the detection circuit, the first pole is coupled to the second voltage terminal, and the second pole is coupled to the gate of the second transistor.
  • the gate of the first N-type transistor is coupled to the output terminal of the detection circuit, the first pole is coupled to the ground terminal, and the second pole is coupled to the gate of the second transistor.
  • the gate of the second P-type transistor is coupled to the output terminal of the detection circuit, the first pole is coupled to the first voltage terminal, and the second pole is coupled to the gate of the first transistor.
  • the gate of the second N-type transistor is coupled to the output terminal of the detection circuit, the first pole is coupled to the ground terminal, and the second pole is coupled to the gate of the first transistor.
  • the above-mentioned first switch may include a first transistor, and the second switch may include a second transistor.
  • the control circuit does not include the first inverter and the second inverter, the gate of the first transistor and the second inverter The gates of the two transistors may be coupled to the output of the detection circuit.
  • the first transistor and the second transistor may be N-type transistors or P-type transistors.
  • the detection circuit is a resistor-capacitor circuit, and the resistor-capacitor circuit includes a resistor, a capacitor, and an output coupled between the resistor and the capacitor.
  • the first switch and the second switch receive the first inverter
  • the resistance R has a certain effect on the high level of the second voltage terminal VDD
  • the delay acts, therefore, the detection signal output from the RC circuit is low.
  • the inverted control signal is a high level opposite to the low level, and under the control of the high level, the N-type first transistor and the second transistor are turned on.
  • the resistor R has a delay effect on the high level of the second voltage terminal VDD, so the detection signal output from the RC circuit is low level, and the P-type The first transistor and the second transistor are turned on at low level.
  • the first switch and the second switch receive the first inverter When the control signal is sent, or the first switch receives the control signal sent by the second inverter, and when the second switch receives the control signal sent by the first inverter, since the capacitor C is coupled to the second voltage terminal VDD and the RC circuit Between the output terminals of the RC circuit, the capacitor C has no delay effect on the high level of the second voltage terminal VDD, and the high level of the second voltage terminal VDD can pull up the output terminal of the RC circuit through the capacitor C.
  • the output detection signal is also at high level.
  • the inverted control signal is a low level opposite to the high level, and under the control of the low level, the P-type first transistor and the second transistor are turned on.
  • the capacitor C since the capacitor C is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the capacitor C has no effect on the high level of the second voltage terminal VDD. Delay effect, and the high level of the second voltage terminal VDD can pull up the output terminal of the RC circuit through the capacitor C, therefore, the detection signal output from the RC circuit is also high level, under the control of the high level, N type of the first transistor and the second transistor are turned on.
  • the electrostatic protection circuit further includes a third transistor; the third transistor is coupled between the first voltage terminal and the second voltage terminal; when the second voltage terminal provides an operating voltage to the first voltage terminal, the third transistor The three transistors are used as triodes; when the first voltage terminal sends an electrostatic signal to the second aunt terminal, the gate of the third transistor can be suspended and multiplexed as a diode.
  • a chip in a second aspect, includes the electrostatic protection circuit described in the first aspect.
  • the implementation manner of the second aspect corresponds to the first aspect and any implementation manner of the first aspect.
  • technical effects corresponding to the implementation of the second aspect reference may be made to the above-mentioned first aspect and the technical effects corresponding to any one of the implementations of the first aspect, which will not be repeated here.
  • a terminal in a third aspect, includes the chip described in the second aspect.
  • the implementation manner of the third aspect corresponds to the first aspect and any implementation manner of the first aspect.
  • technical effects corresponding to the implementation of the third aspect reference may be made to the above-mentioned first aspect and the technical effects corresponding to any one of the implementations of the first aspect, which will not be repeated here.
  • FIG. 1 is a circuit diagram of the protected circuit integrated in the chip provided by the embodiment of the present application.
  • FIG. 2 is a connection diagram between an electrostatic clamp circuit and a protected circuit in the related art
  • FIG. 3 is a connection diagram between an electrostatic clamp circuit and a protected circuit in the related art
  • FIG. 4a is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • FIG. 4b is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • FIG. 5a is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • FIG. 5b is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • FIG. 6a is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • Fig. 6b is a circuit diagram of an electrostatic protection circuit provided by an embodiment of the present application.
  • FIG. 7a is a circuit diagram of an electrostatic protection circuit provided by an embodiment of the present application.
  • FIG. 7b is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • FIG. 8a is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • Fig. 8b is a circuit diagram of an electrostatic protection circuit provided by an embodiment of the present application.
  • Fig. 9a is a circuit diagram of an electrostatic protection circuit provided by an embodiment of the present application.
  • FIG. 9b is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • FIG. 10a is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • FIG. 10b is a circuit diagram of an electrostatic protection circuit provided in an embodiment of the present application.
  • Fig. 11a is a circuit diagram of an electrostatic protection circuit provided by an embodiment of the present application.
  • Fig. 11b is a circuit diagram of an electrostatic protection circuit provided by an embodiment of the present application.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.
  • first target object, the second target object, etc. are used to distinguish different target objects, rather than describing a specific order of the target objects.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • An embodiment of the present application provides a terminal, which may be a mobile phone, a computer, a tablet computer, a TV, a vehicle display, a smart watch, a server, a memory, a radar, a base station, a car, and other devices containing chips.
  • the terminal may also be other devices, and this embodiment of the present application does not limit the specific form of the terminal.
  • the following uses a mobile phone as an example for description.
  • the mobile phone may include multiple chips, and the chip includes one or more protected circuits, and each protected circuit includes one or more protected devices. As shown in FIG. 1 , the chip generates charges during manufacturing, transportation, packaging or testing. If the chip touches the ground, electrostatic discharge will occur, which will damage the protected devices in the protected circuit 200 .
  • the protected circuit 200 may be stored in any circuit in scenarios such as manufacturing, transportation, packaging or testing, and the circuit includes a second voltage terminal VDD and a ground terminal VSS.
  • the protected circuit 200 includes a first voltage terminal TVDD, and a protected device 50 coupled between the first voltage terminal TVDD and a ground terminal VSS.
  • the second voltage terminal VDD is taken as an example in FIG. 1 where the protection device is an inverter including a P-type transistor and an N-type transistor.
  • the power supply can provide the working voltage to the first voltage terminal TVDD through the second voltage terminal VDD; further, the first voltage terminal TVDD can provide the working voltage to the protected device 50 .
  • the static electricity in the chip may cause the electrostatic voltage on the protected circuit 200 to become high.
  • the static electricity cannot be effectively released, it cannot be released from the protected circuit 200, but stored in the P-type transistor and the N-type transistor of the protected device 50.
  • the transistor is a P-type transistor, the electrostatic voltage is stored in the N-hydrazine of the P-type transistor; if the transistor is an N-type transistor, the 2kV electrostatic voltage is stored in the P-type substrate of the N-type transistor. Regardless of whether it is the N-hydrazine of the P-type transistor or the P-type substrate of the N-type transistor, the area occupied by the transistor is relatively large.
  • N-type and P-type substrates The larger the area of N-type and P-type substrates, the more electrostatic charges can be stored. When the higher electrostatic voltage is discharged instantaneously, a larger peak current will be formed. For N-type transistors and P-type Transistors cause shocks, and in extreme cases, N-type transistors and P-type transistors will be damaged.
  • the protected circuit 200 of the present application may be any circuit integrated in a chip.
  • the protected device 50 is a P-type transistor and an N-type transistor.
  • the protected circuit 200 may be, for example, a low power consumption circuit.
  • the protected device 50 in the protected circuit 200 may be a multi-threshold complementary metal oxide semiconductor (MTCMOS), a low dropout regulator (LDO) or a power gate control device (power gating) etc.
  • MTCMOS multi-threshold complementary metal oxide semiconductor
  • LDO low dropout regulator
  • power gating power gate control device
  • Circuit 200 In order to prevent the electrostatic discharge from damaging the protected device in the chip, as shown in FIG. Circuit 200 is always in a safe state.
  • the electrostatic discharge clamping circuit 100 is coupled between the second voltage terminal VDD and the ground terminal VSS, as long as the second voltage terminal VDD is at a high level, under the control of the high level, The electrostatic discharge clamping circuit 100 is then turned on.
  • the first voltage terminal TVDD is coupled to the second voltage terminal TVDD. Therefore, when the first voltage terminal TVDD is at a high level, the first voltage terminal VDD may indirectly control the conduction of the electrostatic discharge clamping circuit 100 .
  • the protected device 50 when the protected device 50 is working normally and the power supply supplies the working voltage to the first voltage terminal TVDD through the second voltage terminal VDD, if the power-on of the first voltage terminal TVDD is too fast (for example, ns-us level), it may be Under the indirect control of a voltage terminal TVDD, the electrostatic discharge clamping circuit 100 is mistakenly turned on, and then the first voltage terminal TVDD, the electrostatic discharge clamping circuit 100, and the ground terminal VSS form a path, and the operating voltage on the first voltage terminal TVDD is directly Through the branch where the electrostatic discharge clamping circuit 100 is located, it flows to the ground terminal VSS. It can also be said that the operating voltage on the first voltage terminal TVDD leaks through the branch where the electrostatic discharge clamping circuit 100 is located. As a result, the voltage on the first voltage terminal TVDD is always small and cannot reach an ideal voltage value, which affects the normal operation of the transistor.
  • the electrostatic discharge clamping circuit 100 is integrated between the second voltage terminal VDD and the ground terminal VSS. Ensure that the resistance between the first voltage terminal TVDD and the second voltage terminal VDD is extremely low, so that the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS through the second voltage terminal VDD is less than the breakdown voltage threshold. It should be noted here that the breakdown voltage threshold refers to the maximum withstand voltage of the protected device 50 . If the clamping voltage of the electrostatic clamping circuit 100 exceeds the breakdown voltage threshold, the protected device 50 will be permanently damaged.
  • the electrostatic discharge clamping circuit 100 when static electricity is discharged through the path of the first voltage terminal TVDD, the electrostatic discharge clamping circuit 100, and the ground terminal VSS, since multiple devices may be integrated between the first voltage terminal TVDD and the second voltage terminal VDD , and cannot control the impedance of multiple devices.
  • the impedance of multiple devices When the impedance of multiple devices is large, the impedance of multiple devices between the first voltage terminal TVDD and the second voltage terminal VDD, the clamping voltage of the electrostatic clamp circuit 100, and the voltage between the first voltage terminal TVDD and the second voltage Under the action of the parasitic resistance on the path from the terminal VDD, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS may be greater than the breakdown voltage threshold, and the protected device 50 will still be damaged.
  • the device between the first voltage terminal TVDD and the second voltage terminal VDD may include a diode, and the charge on the first voltage terminal TVDD may flow to the second voltage terminal VDD through the diode when static electricity is discharged.
  • the size of the diode is small, and the impedance when it is turned on is large, thereby greatly increasing the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS.
  • the electrostatic protection circuit may include a control circuit 10, a first switch 20, and a ground terminal VSS.
  • the first switch 20 and the protected device 50 are coupled in parallel between the first voltage terminal TVDD and the ground terminal.
  • the control circuit 10 is configured to send a control signal to the first switch 20 when detecting that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD.
  • the first switch 20 is configured to be turned on under the control of the control signal. After the first switch 20 is turned on, the first voltage terminal TVDD, the first switch 20 and the ground terminal VSS form a path.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged through the first switch 20, so as to prevent the electrostatic voltage on the first voltage terminal TVDD from being too high, thereby avoiding the formation of relatively high electrostatic voltage when the high electrostatic voltage is discharged instantaneously.
  • the large peak current impacts the protected device 50 and damages the protected device 50 .
  • the first switch 20 and the protected device 50 are coupled in parallel between the first voltage terminal TVDD and the ground terminal VSS.
  • the static electricity on the first voltage terminal TVDD can be discharged through the path of the first voltage terminal TVDD, the first switch 20, and the ground terminal VSS.
  • the electrostatic discharge path can be shortened and the parasitic resistance on the electrostatic discharge path can be reduced.
  • the present application can also control that no other devices except the first switch 20 are integrated on the path of the first voltage terminal TVDD, the first switch 20 , and the ground terminal VSS.
  • the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS of the present application is no longer affected by the impedance of other devices.
  • the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can be greatly reduced, preventing the path from the first voltage terminal TVDD to the ground terminal VSS
  • the total voltage of is greater than the breakdown voltage threshold, causing the protected device 50 to be damaged.
  • the electrostatic protection circuit may further include a second switch 30 coupled between the second voltage terminal VDD and the ground terminal VSS.
  • the control circuit 10 is further configured to send a control signal to the second switch 30 when detecting that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD.
  • the second switch 30 is configured to be turned on under the control of the control signal. After the second switch 30 is turned on, the first voltage terminal TVDD, the second voltage terminal VDD, the second switch 30 and the ground terminal VSS can form a path, and the electrostatic voltage on the first voltage terminal TVDD can be discharged through the first switch 20 , can also be released through the second switch 30 .
  • the first voltage terminal TVDD discharges at least part of the electrostatic voltage through the second switch 30, reduces the voltage value of the first voltage terminal TVDD, prevents the voltage of the first voltage terminal TVDD from being too large, and the power supply supplies the first voltage to the first voltage terminal VDD through the second voltage terminal VDD.
  • the terminal TVDD provides an operating voltage, and when the first voltage terminal TVDD is powered on too quickly, the first switch 20 is mistakenly turned on, thereby preventing the operating voltage from leaking through the first switch 20 .
  • the above-mentioned first switch 20 includes a first transistor T1
  • the second switch 30 includes a second transistor T2.
  • the control circuit 10 includes a detection circuit 11 and a first inverter 12 .
  • both the first transistor T1 and the second transistor T2 are N-type transistors.
  • the first pole of the first transistor T1 is coupled to the first voltage terminal TVDD, and the second pole is coupled to the ground terminal VSS.
  • the first pole of the second transistor T2 is coupled to the second voltage terminal VDD, and the second pole is coupled to the ground terminal VSS.
  • first pole of the first transistor T1 may be a source, and the second pole may be a drain.
  • the first poles of the second transistor T2 and the third transistor T3 hereinafter, the first P-type transistor P1, the first N-type transistor N1, the second P-type transistor P2 and the second N-type transistor N2 may also be sources, The second pole may also be a drain. I won't go into details below.
  • the detection circuit 11 may be a resistor-capacitor (RC) circuit, and the detection circuit 11 includes a resistor R and a capacitor C, and an output terminal coupled between the resistor R and the capacitor C.
  • the resistor R is coupled between the second voltage terminal VDD and the output terminal of the RC circuit
  • the capacitor C is coupled between the ground terminal VSS and the output terminal of the RC circuit.
  • the control terminal of the first inverter 12 is coupled to the output terminal of the RC circuit, the input terminal of the first inverter 12 is respectively coupled to the second voltage terminal VDD and the ground terminal VSS, and the output terminal of the first inverter 12 is coupled to the second voltage terminal VSS.
  • a transistor T1 is coupled to a gate of a second transistor T2.
  • the first inverter 12 may include a first P-type transistor P1 and a first N-type transistor N1.
  • the gate of the first P-type transistor P1 is coupled to the output terminal of the RC circuit, the first pole of the first P-type transistor P1 is coupled to the second voltage terminal VDD, and the second pole of the first P-type transistor P1 is coupled to the first transistor T1 Coupled with the gate of the second transistor T2.
  • the gate of the first N-type transistor N1 is coupled to the output terminal of the RC circuit, the first pole of the first N-type transistor N1 is coupled to the ground terminal VSS, the second pole of the first N-type transistor N1 is coupled to the gate of the first transistor T1 The pole is coupled to the gate of the second transistor T2.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging, or testing. If the chip touches the ground, it will form an electrostatic discharge.
  • the charge on the first voltage terminal TVDD passes through the second The voltage terminal VDD flows to the low potential ground terminal VSS.
  • the charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the third transistor T3 may be a P-type transistor.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event (ESD event), and the RC circuit The output end outputs a detection signal. Since the resistor R is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the resistor R has a delay effect on the high level of the second voltage terminal VDD, and the detection signal output from the RC circuit is low which is opposite to the high level. level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the low level output by the RC circuit can be transmitted to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 as the enable signal of the first P-type transistor P1 and the first N-type transistor N1 .
  • the first P-type transistor P1 Under the control of the low level, the first P-type transistor P1 is turned on, and the first N-type transistor N1 is turned off.
  • a control signal can be sent to the first transistor T1 and the second transistor T2. That is, the first pole of the first P-type transistor P1 transmits the high level of the second voltage terminal VDD to the gate of the first transistor T1 and the gate of the second transistor T2 through the second pole of the first P-type transistor P1. pole.
  • the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 are turned on under the control of the high level.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can normally work at the first voltage terminal Between TVDD and ground terminal VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the RC circuit can also output a low level to the first inverter 12 to turn on the first P-type transistor P1.
  • the first P-type transistor P1 sends the high level of the second voltage terminal VDD to the gate of the first transistor T1 to turn on the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and the first inverter 12, and the connection between the RC circuit and the first inverter 12 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.
  • the control circuit 10 when the control circuit 10 does not include the first inverter 12 (or the control circuit does not include the first inverter and the second inverter hereinafter), this
  • the first transistor T1 and the second transistor T2 in the embodiment of the application may be P-type transistors, and the gates of the first transistor T1 and the second transistor T2 may be coupled to the output terminal of the RC circuit.
  • other circuit structures in the solution shown in Fig. 5a and Fig. 5b are the same as those in the solution shown in Fig. 4a and Fig. 4b.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging or testing. If the chip touches the ground, electrostatic discharge will be formed, and the charge on the first voltage terminal TVDD passes through the second The voltage terminal VDD flows to the low potential ground terminal VSS. The charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the third transistor T3 may be a P-type transistor.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event (ESD event), and the RC circuit The output end outputs a detection signal. Since the resistor R is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the resistor R has a delay effect on the high level of the second voltage terminal VDD, and the detection signal output from the RC circuit is low which is opposite to the high level. level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal that can be used as a control signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the low level output by the RC circuit can be transmitted to the gates of the first transistor T1 and the second transistor T2. Since the first transistor T1 and the second transistor T2 are P-type transistors, the first transistor T1 and the second transistor T2 is turned on under the control of low level.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the embodiment of the present application can reduce the layout area of the electrostatic protection circuit.
  • the foregoing scheme in which the control circuit 10 includes the first inverter 12 can be applied in the scenario where the path from the RC circuit to the gate of the first transistor T1 and the gate of the second transistor T2 is too long. Avoiding that the path from the RC circuit to the gate of the first transistor T1 and the gate of the second transistor T2 is too long, causing the signal output by the RC circuit to be consumed on the path, so that the first transistor T1 and the second transistor T2 cannot fully conduction.
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can normally work at the first voltage terminal Between TVDD and ground terminal VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the electrostatic voltage is transmitted to the second voltage terminal VDD and the first voltage terminal TVDD through the power supply, once the charge is determined by the RC circuit
  • the RC circuit can also output a low level to the first transistor T1, so that the first transistor T1 is turned on.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and the first inverter 12, and the connection between the RC circuit and the first inverter 12 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.
  • the above-mentioned first switch 20 includes a first transistor T1
  • the second switch 30 includes a second transistor T2.
  • the control circuit 10 includes a detection circuit 11 and a first inverter 12 .
  • both the first transistor T1 and the second transistor T2 are P-type transistors.
  • the first pole of the first transistor T1 is coupled to the first voltage terminal TVDD, and the second pole is coupled to the ground terminal VSS.
  • the first pole of the second transistor T2 is coupled to the second voltage terminal VDD, and the second pole is coupled to the ground terminal VSS.
  • the detection circuit 11 may be an RC circuit, and the detection circuit 11 includes a resistor R, a capacitor C, and an output terminal coupled between the resistor R and the capacitor C.
  • the capacitor C is coupled between the second voltage terminal VDD and the output terminal of the RC circuit
  • the resistor R is coupled between the ground terminal VSS and the output terminal of the RC circuit.
  • the control terminal of the first inverter 12 is coupled to the output terminal of the RC circuit, the input terminal of the first inverter 12 is respectively coupled to the second voltage terminal VDD and the ground terminal VSS, and the output terminal of the first inverter 12 is coupled to the second voltage terminal VSS.
  • the gates of the two transistors T2 are coupled.
  • the first inverter 12 may include a first P-type transistor P1 and a first N-type transistor N1.
  • the gate of the first P-type transistor P1 is coupled to the output terminal of the RC circuit, the first pole of the first P-type transistor P1 is coupled to the second voltage terminal VDD, and the second pole of the first P-type transistor P1 is coupled to the first transistor T1 Coupled with the gate of the second transistor T2.
  • the gate of the first N-type transistor N1 is coupled to the output terminal of the RC circuit, the first pole of the first N-type transistor N1 is coupled to the ground terminal VSS, the second pole of the first N-type transistor N1 is coupled to the gate of the first transistor T1 The pole is coupled to the gate of the second transistor T2.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging or testing. If the chip touches the ground, electrostatic discharge will be formed, and the charge on the first voltage terminal TVDD will go to a low potential. flow. The charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and the output terminal of the RC circuit outputs a detection Signal. Since the capacitor C is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the capacitor C has no delay effect on the high level of the second voltage terminal VDD, and the high level of the second voltage terminal VDD can be controlled by the capacitor C. The output end of the RC circuit is pulled high, therefore, the detection signal output from the RC circuit is also high level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the high level output by the RC circuit can be transmitted to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 as the enable signal of the first P-type transistor P1 and the first N-type transistor N1 .
  • the first N-type transistor N1 is turned on, and the first P-type transistor P1 is turned off.
  • a control signal can be sent to the first transistor T1 and the second transistor T2. That is, the first pole of the first N-type transistor N1 transmits the low level of the ground terminal VSS to the gate of the first transistor T1 and the gate of the second transistor T2 through the second pole of the first N-type transistor N1 .
  • the first transistor T1 and the second transistor T2 are P-type transistors, the first transistor T1 and the second transistor T2 are turned on under the control of the low level.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can normally work at the first voltage terminal Between TVDD and ground terminal VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the RC circuit can also output a high level to the first inverter, so that the first N-type transistor 1 is turned on.
  • the first N-type transistor N1 sends the low level of the ground terminal VSS to the gate of the first transistor T1 to turn on the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and the first inverter 12, and the connection between the RC circuit and the first inverter 12 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.
  • the present application when the control circuit does not include the first inverter 12 (or the control circuit does not include the first inverter and the second inverter hereinafter), the present application
  • the first transistor T1 and the second transistor T2 in this embodiment may be N-type transistors, and the gates of the first transistor T1 and the second transistor T2 may be coupled to the output terminal of the RC circuit.
  • other circuit structures in the solution shown in Fig. 7a and Fig. 7b are the same as those in the solution shown in Fig. 6a and Fig. 6b.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging or testing. If the chip touches the ground, electrostatic discharge will be formed, and the charge on the first voltage terminal TVDD will go to a low potential. flow. The charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and the output terminal of the RC circuit outputs a detection Signal. Since the capacitor C is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the capacitor C has no delay effect on the high level of the second voltage terminal VDD, and the high level of the second voltage terminal VDD can be controlled by the capacitor C. The output end of the RC circuit is pulled high, therefore, the detection signal output from the RC circuit is also high level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal that can be used as a control signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the high level output by the RC circuit can be transmitted to the gates of the first transistor T1 and the second transistor T2. Since the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 is turned on under the control of high level.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the embodiment of the present application can reduce the layout area of the electrostatic protection circuit.
  • the foregoing scheme in which the control circuit 10 includes the first inverter 12 can be applied in the scenario where the path from the RC circuit to the gate of the first transistor T1 and the gate of the second transistor T2 is too long. Avoiding that the path from the RC circuit to the gate of the first transistor T1 and the gate of the second transistor T2 is too long, causing the signal output by the RC circuit to be consumed on the path, so that the first transistor T1 and the second transistor T2 cannot fully conduction.
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can normally work at the first voltage terminal Between TVDD and ground terminal VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1. .
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and the first inverter 12, and the connection between the RC circuit and the first inverter 12 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.
  • the above-mentioned first switch 20 includes a first transistor T1
  • the second switch 30 includes a second transistor T2.
  • the control circuit 10 includes a detection circuit 11 , a first inverter 12 and a second inverter 13 .
  • both the first transistor T1 and the second transistor T2 are N-type transistors.
  • the first pole of the first transistor T1 is coupled to the first voltage terminal TVDD, and the second pole is coupled to the ground terminal VSS.
  • the first pole of the second transistor T2 is coupled to the second voltage terminal VDD, and the second pole is coupled to the ground terminal VSS.
  • the detection circuit 11 may be an RC circuit, the detection circuit 11 includes a resistor R and a capacitor C, the resistor R is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, and the capacitor C is coupled between the ground terminal VSS and the output terminal of the RC circuit between.
  • the control terminal of the first inverter 12 is coupled to the output terminal of the RC circuit, the input terminal of the first inverter 12 is respectively coupled to the second voltage terminal VDD and the ground terminal VSS, and the output terminal of the first inverter 12 is coupled to the second voltage terminal VSS.
  • the gates of the two transistors T2 are coupled.
  • the first inverter 12 may include a first P-type transistor P1 and a first N-type transistor N1.
  • the gate of the first P-type transistor P1 is coupled to the output terminal of the RC circuit, the first pole of the first P-type transistor P1 is coupled to the second voltage terminal VDD, and the second pole of the first P-type transistor P1 is coupled to the second transistor T2 the gate coupling.
  • the gate of the first N-type transistor N1 is coupled to the output terminal of the RC circuit, the first pole of the first N-type transistor N1 is coupled to the ground terminal VSS, the second pole of the first N-type transistor N1 is coupled to the gate of the second transistor T2 pole coupling.
  • the control terminal of the second inverter 13 is coupled to the output terminal of the RC circuit, the input terminals of the second inverter 13 are respectively coupled to the first voltage terminal TVDD and the ground terminal VSS, and the output terminal of the second inverter 13 is coupled to the first voltage terminal VSS.
  • the gate of a transistor T1 is coupled.
  • the second inverter 13 may include a second P-type transistor P2 and a second N-type transistor N2.
  • the gate of the second P-type transistor P2 is coupled to the output terminal of the RC circuit, the first pole of the second P-type transistor P2 is coupled to the first voltage terminal TVDD, and the second pole of the second P-type transistor P2 is coupled to the first transistor T1 the gate coupling.
  • the gate of the second N-type transistor N2 is coupled to the output terminal of the RC circuit, the first pole of the second N-type transistor N2 is coupled to the ground terminal VSS, the second pole of the second N-type transistor N2 is coupled to the gate of the first transistor T1 pole coupling.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging or testing. If the chip touches the ground, electrostatic discharge will be formed, and the charge on the first voltage terminal TVDD passes through the second The voltage terminal VDD flows toward a low potential. The charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the third transistor T3 may be a P-type transistor.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and the output terminal of the RC circuit outputs a detection Signal. Since the resistor R is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the resistor R has a delay effect on the high level of the second voltage terminal VDD, and the detection signal output from the RC circuit is low which is opposite to the high level. level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the low level output by the RC circuit can be transmitted to the gate of the first P-type transistor P1, the gate of the first N-type transistor N1, the gate of the second P-type transistor P2, the gate of the second N-type transistor N2 pole, as an enable signal for the first P-type transistor P1, the first N-type transistor N1, the second P-type transistor P2, and the second N-type transistor N2.
  • the first P-type transistor P1 and the second P-type transistor P2 are turned on, and the first N-type transistor N1 and the second N-type transistor N2 are turned off.
  • a control signal can be sent to the first transistor T1 and the second transistor T2.
  • the first pole of the first P-type transistor P1 transmits the high level of the second voltage terminal VDD to the gate of the second transistor T2 through the second pole of the first P-type transistor P1 .
  • the second P-type transistor P2 After the second P-type transistor P2 is turned on, it can send a control signal to the first transistor T1 and the second transistor T2. That is, the first pole of the second P-type transistor P2 sends the high level of the first voltage terminal TVDD to the gate of the first transistor T1 through the second pole of the second P-type transistor P2 .
  • the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 are turned on under the control of the high level.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the first P-type transistor P1 of the first inverter 12 and the second P-type transistor P2 of the second inverter 13 have a channel impedance when they are turned on.
  • the first P-type transistor P1 is coupled with the gate of the first transistor T1 through a relatively long path, resulting in The channel resistance increases further.
  • the first P-type transistor P1 transmits the voltage of the second voltage terminal VDD to the first transistor T1
  • a part of the voltage needs to be divided by the gate of the first transistor T1, so that the voltage is transmitted to the gate of the first transistor T1 for turning on the first transistor T1.
  • the voltage of the first transistor T1 decreases, and the conduction of the first transistor T1 is insufficient.
  • the first transistor T1 is weakly turned on, resulting in low efficiency of static electricity discharge through the first voltage terminal TVDD through the first transistor T1.
  • the RC circuit can directly send a low level to the gate of the second P-type transistor P2, although the second P-type transistor P2 also has a channel Impedance, but the coupling path between the second P-type transistor P2 and the gate of the first transistor T1 is relatively short.
  • the second P-type transistor P2 transmits the voltage of the first voltage terminal TVDD to the first transistor T1, it is transferred by the first transistor T1
  • the voltage divided by the gate is small, and the first transistor T1 can be fully turned on. It can also be said that the first transistor T1 is strongly turned on, which will not affect the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1. Therefore, compared with the solution in which the control circuit 10 does not include the second inverter 13 , this embodiment can improve the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1 .
  • the solution shown in FIG. 4 a can reduce the layout area of the ESD protection circuit because the control circuit 10 does not include the second inverter 13 .
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can normally work at the first voltage terminal Between TVDD and ground VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and a second inverter 13, and the connection between the RC circuit and the second inverter 13 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.
  • the first transistor T1 of the embodiment of the present application can be N type transistor
  • the second transistor T2 can be a P-type transistor
  • the gate of the first transistor T1 can be coupled to the second inverter 13
  • the gate of the second transistor T2 can be coupled to the output terminal of the RC circuit.
  • other circuit structures in the solution shown in Fig. 9a and Fig. 9b are the same as those in the solution shown in Fig. 8a and Fig. 8b.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging or testing. If the chip touches the ground, electrostatic discharge will be formed, and the charge on the first voltage terminal TVDD passes through the second The voltage terminal VDD flows toward a low potential. The charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the third transistor T3 may be a P-type transistor.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and the output terminal of the RC circuit outputs a detection Signal. Since the resistor R is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the resistor R has a delay effect on the high level of the second voltage terminal VDD, and the detection signal output from the RC circuit is low which is opposite to the high level. level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the low level output by the RC circuit can be transmitted to the gate of the second P-type transistor P2, the gate of the second N-type transistor N2, and the gate of the second transistor T2, as the second P-type transistor P2, the second transistor T2 Two N-type transistors N2 and an enable signal of the second transistor T2.
  • the second P-type transistor P2 and the second transistor T2 are turned on, and the second N-type transistor N2 is turned off. After the second P-type transistor P2 is turned on, it can send a control signal to the first transistor T1.
  • the first pole of the second P-type transistor P2 sends the high level of the first voltage terminal TVDD to the gate of the first transistor T1 through the second pole of the second P-type transistor P2 . Since the first transistor T1 is an N-type transistor, the first transistor T1 is turned on under the control of the high level. The electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the RC circuit can directly send a low level to the gate of the second P-type transistor P2, although the second P-type transistor P2 also has a channel impedance , but the coupling path between the second P-type transistor P2 and the gate of the first transistor T1 is relatively short.
  • the second P-type transistor P2 transmits the voltage of the first voltage terminal TVDD to the first transistor T1, it is transferred
  • the voltage divided by the gate is small, and the first transistor T1 can be fully turned on. It can also be said that the first transistor T1 is strongly turned on, which will not affect the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1. Therefore, compared with the solution in which the control circuit 10 does not include the second inverter 13 , this embodiment can improve the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1 .
  • the solution shown in FIG. 5 a can reduce the layout area of the electrostatic protection circuit because the control circuit 10 does not include the second inverter 13 .
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can normally work at the first voltage terminal Between TVDD and ground VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and a second inverter 13, and the connection between the RC circuit and the second inverter 13 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.
  • the first switch 20 includes a first transistor T1
  • the second switch 30 includes a second transistor T2
  • the control circuit 10 includes a detection circuit 11 , a first inverter 12 and a second inverter 13 .
  • both the first transistor T1 and the second transistor T2 are P-type transistors.
  • the first pole of the first transistor T1 is coupled to the first voltage terminal TVDD, and the second pole is coupled to the ground terminal VSS.
  • the first pole of the second transistor T2 is coupled to the second voltage terminal VDD, and the second pole is coupled to the ground terminal VSS.
  • the detection circuit 11 may be an RC circuit, and the detection circuit 11 includes a resistor R and a capacitor C, and an output terminal coupled between the resistor R and the capacitor C.
  • the capacitor C is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, and the resistor R is coupled between the ground terminal VSS and the output terminal of the RC circuit.
  • the control terminal of the first inverter 12 is coupled to the output terminal of the RC circuit, the input terminal of the first inverter 12 is respectively coupled to the second voltage terminal VDD and the ground terminal VSS, and the output terminal of the first inverter 12 is coupled to the second voltage terminal VSS.
  • the gates of the two transistors T2 are coupled.
  • the first inverter 12 may include a first P-type transistor P1 and a first N-type transistor N1.
  • the gate of the first P-type transistor P1 is coupled to the output terminal of the RC circuit, the first pole of the first P-type transistor P1 is coupled to the second voltage terminal VDD, and the second pole of the first P-type transistor P1 is coupled to the second transistor T2 the gate coupling.
  • the gate of the first N-type transistor N1 is coupled to the output terminal of the RC circuit, the first pole of the first N-type transistor N1 is coupled to the ground terminal VSS, the second pole of the first N-type transistor N1 is coupled to the gate of the second transistor T2 pole coupling.
  • the control terminal of the second inverter 13 is coupled to the output terminal of the RC circuit, the input terminals of the second inverter 13 are respectively coupled to the first voltage terminal TVDD and the ground terminal VSS, and the output terminal of the second inverter 13 is coupled to the first voltage terminal VSS.
  • the gate of a transistor T1 is coupled.
  • the second inverter 13 may include a second P-type transistor P2 and a second N-type transistor N2.
  • the gate of the second P-type transistor P2 is coupled to the output terminal of the RC circuit, the first pole of the second P-type transistor P2 is coupled to the first voltage terminal TVDD, and the second pole of the second P-type transistor P2 is coupled to the first transistor T1 the gate coupling.
  • the gate of the second N-type transistor N2 is coupled to the output terminal of the RC circuit, the first pole of the second N-type transistor N2 is coupled to the ground terminal VSS, the second pole of the second N-type transistor N2 is coupled to the gate of the first transistor T1 pole coupling.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging or testing. If the chip touches the ground, it will form electrostatic discharge.
  • the charge on the first voltage terminal TVDD passes through the second The voltage terminal VDD flows toward a low potential.
  • the charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the third transistor T3 may be a P-type transistor.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and the output terminal of the RC circuit outputs a detection Signal. Since the capacitor C is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the capacitor C has no delay effect on the high level of the second voltage terminal VDD, and the high level of the second voltage terminal VDD can be controlled by the capacitor C. The output end of the RC circuit is pulled high, therefore, the detection signal output from the RC circuit is also high level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the high level output by the RC circuit can be transmitted to the gate of the first P-type transistor P1, the gate of the first N-type transistor N1, the gate of the second P-type transistor P2, the gate of the second N-type transistor N2 pole, as an enable signal for the first P-type transistor P1, the first N-type transistor N1, the second P-type transistor P2, and the second N-type transistor N2.
  • the first N-type transistor N1 and the second N-type transistor N2 are turned on, and the first P-type transistor P1 and the second P-type transistor P2 are turned off.
  • a control signal can be sent to the first transistor T1 and the second transistor T2.
  • the first pole of the first N-type transistor N1 transmits the low level of the ground terminal VSS to the gate of the second transistor T2 through the second pole of the first N-type transistor N1 .
  • the second N-type transistor N2 can send a control signal to the first transistor T1 and the second transistor T2. That is, the first pole of the second N-type transistor N2 sends the low level of the ground terminal VSS to the gate of the first transistor T1 through the second pole of the second N-type transistor N2 .
  • the first transistor T1 and the second transistor T2 are P-type transistors, the first transistor T1 and the second transistor T2 are turned on under the control of the low level.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the first N-type transistor N1 of the first inverter 12 and the second N-type transistor N2 of the second inverter 13 have a channel impedance when they are turned on.
  • the first N-type transistor N1 is coupled with the gate of the first transistor T1 through a relatively long path, resulting in The channel resistance increases further.
  • the first N-type transistor N1 transmits the voltage of the ground terminal VSS to the first transistor T1
  • a part of the voltage needs to be divided by the gate of the first transistor T, resulting in transmission to the gate of the first transistor T1 for turning on the first transistor
  • the voltage of T1 decreases, and the conduction of the first transistor T1 is insufficient.
  • the first transistor T1 is weakly turned on, so that the static electricity discharge efficiency of the first voltage terminal TVDD through the first transistor T1 is low.
  • the RC circuit can directly send a high level to the gate of the second N-type transistor N2, although the second N-type transistor N2 also has a channel Impedance, but the coupling path between the second N-type transistor N2 and the gate of the first transistor T1 is relatively short.
  • the second N-type transistor N2 transmits the voltage of the first voltage terminal TVDD to the first transistor T1, it is transferred by the first transistor T1
  • the voltage divided by the gate is small, and the first transistor T1 can be fully turned on. It can also be said that the first transistor T1 is strongly turned on, which will not affect the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1. Therefore, compared with the solution in which the control circuit 10 does not include the second inverter 13 , this embodiment can improve the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1 .
  • the solution shown in FIG. 5 a can reduce the layout area of the electrostatic protection circuit because the control circuit 10 does not include the second inverter 13 .
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can work normally at the first voltage terminal Between TVDD and ground terminal VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the RC circuit can also output a high level to the first inverter 12 and the second inverter 13, so as to turn on the second N-type transistor N2.
  • the second N-type transistor N2 sends the low level of the ground terminal VSS to the gate of the first transistor T1 to turn on the first transistor T1 .
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and a second inverter 13, and the connection between the RC circuit and the second inverter 13 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.
  • the first transistor T1 of the embodiment of the present application can be P type transistor
  • the second transistor T2 can be an N-type transistor
  • the gate of the first transistor T1 can be coupled to the second inverter 13
  • the gate of the second transistor T2 can be coupled to the output terminal of the RC circuit.
  • other circuit structures in the solutions shown in Fig. 11a and Fig. 11b are the same as other circuit structures in the solutions shown in Fig. 10a and Fig. 10b.
  • the electrostatic protection circuit can work in the electrostatic discharge stage and the normal working stage.
  • the chip in the electrostatic discharge stage: the chip generates charges due to reasons such as manufacturing, transportation, packaging or testing. If the chip touches the ground, electrostatic discharge will be formed, and the charge on the first voltage terminal TVDD passes through the second The voltage terminal VDD flows toward a low potential. The charges flow to the second voltage terminal VDD, and the voltage of the second voltage terminal VDD is rapidly pulled up. It should be noted here that, compared with the voltage on the ground terminal VSS, the voltage on the second voltage terminal VDD and the voltage on the first voltage terminal TVDD are at a high level.
  • the electrostatic protection circuit may further include a third transistor T3.
  • a third transistor T3 In the electrostatic discharge stage, by suspending the gate of the third transistor T3 (that is, no voltage is applied to the gate of the third transistor T3, It can also be said that no high level and low level are input to the third transistor T3, so that the source, body and drain of the third transistor T3 can form a diode. Charges on the first voltage terminal TVDD can flow to a low potential through the diode.
  • the third transistor T3 may be a P-type transistor.
  • the RC circuit When the RC circuit detects that the first voltage terminal TVDD sends an electrostatic signal to the second voltage terminal VDD, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event, and the output terminal of the RC circuit outputs a detection Signal. Since the capacitor C is coupled between the second voltage terminal VDD and the output terminal of the RC circuit, the capacitor C has no delay effect on the high level of the second voltage terminal VDD, and the high level of the second voltage terminal VDD can be controlled by the capacitor C. The output end of the RC circuit is pulled high, therefore, the detection signal output from the RC circuit is also high level.
  • the RC circuit can be used to identify the pulse rising edge of the second voltage terminal VDD, and when it matches the pulse rising edge of the electrostatic voltage, it is determined that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as electrostatic discharge. event, and output a detection signal. For example, if the rising edge of the electrostatic voltage pulse occurs between ns and ⁇ s, the RC circuit determines that the charge on the first voltage terminal TVDD flows to the second voltage terminal VDD as an electrostatic discharge event.
  • the rising edge of the electrostatic voltage pulse in other scenarios may also occur in other time ranges, which is not limited in this embodiment of the present application, as long as the way for the RC circuit to identify the electrostatic voltage is preset. It can also be said that when the first voltage terminal TVDD of the RC circuit sends an electrostatic signal to the second voltage terminal VDD, the level of the second voltage terminal VDD rises rapidly, and the voltage on the RC circuit increases.
  • the high level output by the RC circuit can be transmitted to the gate of the second P-type transistor P2, the gate of the second N-type transistor N2, and the gate of the second transistor T2, as the second P-type transistor P2,
  • the second N-type transistor N2 and the second transistor T2 are turned on, and the second P-type transistor P2 is turned off.
  • the second N-type transistor N2 After the second N-type transistor N2 is turned on, it can send a control signal to the first transistor T1. That is, the first pole of the second N-type transistor N2 sends the low level of the ground terminal VSS to the gate of the first transistor T1 through the second pole of the second N-type transistor N2 .
  • the first transistor T1 is a P-type transistor, the first transistor T1 is turned on under the control of the low level.
  • the electrostatic voltage on the first voltage terminal TVDD can be discharged to the ground terminal VSS through the first transistor T1 and the second transistor T2 respectively.
  • the static electricity discharge effect of the second transistor T2 is not good due to the large impedance between the first voltage terminal TVDD and the second voltage terminal VDD, it will not affect the static electricity on the first voltage terminal TVDD.
  • the voltage is discharged to the ground terminal VSS through the first transistor T1.
  • the first voltage terminal TVDD can also indirectly control the conduction of the first transistor T1, at least part of the electrostatic voltage can be discharged through the second transistor T2. Therefore, even if the first voltage terminal TVDD is powered on too quickly, the first switch 20 will not be turned on by mistake, so as to prevent the operating voltage on the first voltage terminal TVDD from leaking through the first switch 20 .
  • the RC circuit can directly send a high level to the gate of the second N-type transistor N2, although the second N-type transistor N2 also has a channel impedance , but the coupling path between the second N-type transistor N2 and the gate of the first transistor T1 is relatively short.
  • the voltage divided by the gate is small, and the first transistor T1 can be fully turned on. It can also be said that the first transistor T1 is strongly turned on, which will not affect the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1. Therefore, compared with the solution in which the control circuit 10 does not include the second inverter 13 , this embodiment can improve the electrostatic discharge efficiency of the first voltage terminal TVDD through the first transistor T1 .
  • the solution shown in FIG. 7 a can reduce the layout area of the electrostatic protection circuit because the control circuit 10 does not include the second inverter 13 .
  • the second voltage terminal VDD can be coupled with the power supply, and the power supply inputs the operating voltage to the first voltage terminal TVDD through the second voltage terminal VDD, so that the protected device 50 can work normally at the first voltage terminal Between TVDD and ground VSS.
  • the electrostatic protection circuit may further include a driving circuit 60, and in a normal working phase, the driving circuit 60 may provide a low level for the gate of the third transistor T3 to turn on the third transistor T3. Further, the second voltage terminal VDD can send the working voltage to the first voltage terminal TVDD through the third transistor T3.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD is discharged to the ground terminal VSS through the first transistor T1.
  • the electrostatic voltage transmitted from the power supply to the first voltage terminal TVDD will not affect the normal operation of the protected circuit 200 while being discharged through the first transistor T1. Work. Moreover, since the first voltage terminal TVDD discharges the electrostatic voltage through the first transistor T1, the total voltage on the path from the first voltage terminal TVDD to the ground terminal VSS can also be avoided from being relatively large. The clamping voltage between the ground terminals VSS is relatively large, causing the protected device 50 to be damaged.
  • this embodiment takes the static electricity protection circuit including the first switch 20 and the second switch 30 as an example to illustrate the working principle of the static electricity protection circuit.
  • the control circuit 10 may include an RC circuit and a second inverter 13, and the connection between the RC circuit and the second inverter 13 The connection relationship and working principle are the same as those in this embodiment, and will not be repeated here.

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Abstract

本申请实施例提供了一种静电防护电路、芯片和终端，涉及芯片技术领域，通过将第一开关耦合于第一电压端与接地端之间，不但可以静电泄放，还可以防止第一电压端到接地端路径的总电压大于击穿电压阈值，导致被保护器件被损坏。该静电防护电路包括控制电路、第一开关、第一电压端、第二电压端和接地端；第二电压端用于向第一电压端提供工作电压；第一开关和被保护器件并联耦合于第一电压端与接地端之间。控制电路，用于在检测到第一电压端向第二电压端发送静电信号时，向第一开关发送控制信号；第一开关，用于在控制信号的控制下导通。

Description

静电防护电路、芯片和终端 技术领域
本申请涉及芯片技术领域，尤其涉及一种静电防护电路、芯片和终端。
背景技术
芯片因制造、运输、封装或测试等原因产生电荷后，若芯片的管脚连接到接地端，则会形成静电泄放(electrostatic discharge，ESD)。静电泄放过程中，容易损坏芯片中的器件，进而影响芯片的功能。
因此，如何防止因静电泄放损坏器件，是目前亟待解决的问题。
发明内容
为了解决上述技术问题，本申请提供一种静电防护电路、芯片和终端，通过将第一开关耦合于第一电压端与接地端之间，不但可以静电泄放，还可以防止第一电压端到接地端路径上的总电压大于击穿电压阈值，导致被保护器件被损坏。
第一方面，本申请提供一种静电防护电路，该静电防护电路包括控制电路、第一开关、第一电压端、第二电压端和接地端；第二电压端用于向第一电压端提供工作电压。第一开关和被保护器件并联耦合于第一电压端与接地端之间。控制电路，用于在检测到第一电压端向第二电压端发送静电信号时，向第一开关发送控制信号；第一开关，用于在控制信号的控制下导通。
本申请中，通过将第一开关耦合在第一电压端与接地端之间，使得第一开关在控制信号的控制下导通，使第一电压端、第一开关、以及接地端形成通路。这样一来，第一电压端上的静电电压可以通过第一开关泄放，避免造成第一电压端上的静电电压过高，进而避免较高的静电电压在瞬间放电时，形成较大的峰值电流，对被保护器件造成冲击，损坏被保护器件。
并且，本申请通过使第一开关与被保护器件并联耦合于第一电压端与接地端之间。在静电泄放时，第一电压端上的静电可以通过第一电压端、第一开关、以及接地端这一通路泄放。相较于相关技术，本申请在静电泄放时无需经过第二电压端，可以减短静电泄放路径，减小静电泄放路径上的寄生电阻。并且，本申请还可以控制在第一电压端、第一开关、以及接地端这一通路上，不再集成除第一开关以外的其他器件。这样一来，相较于相关技术，本申请第一电压端到接地端路径上的总电压不再受其他器件的阻抗的影响。通过减小静电泄放路径上的寄生电阻，以及排除其他器件的阻抗影响，第一电压端到接地端路径上的总电压可以大大降低，防止第一电压端到接地端路径上的总电压大于击穿电压阈值，导致被保护器件被损坏。
在一些可能实现的方式中，静电防护电路还包括第二开关；第二开关耦合于第二电压端与接地端之间；控制电路，还用于在检测到第一电压端向第二电压端发送静电信号 时，向第二开关发送控制信号；第二开关，用于在控制信号的控制下导通。第二开关导通后，第一电压端、第二电压端、第二开关、接地端可以形成通路，第一电压端上的静电电压除了通过第一开关泄放以外，还可以通过第二开关泄放。第一电压端通过第二开关泄放至少部分静电电压，降低第一电压端的电压值，防止第一电压端的电压过大，且电源通过第二电压端向第一电压端提供工作电压，第一电压端的上电过快时，导致第一开关误开启，从而避免工作电压通过第一开关漏电。
在一些可能实现的方式中，控制电路包括检测电路，检测电路串接于第二电压端与接地端之间；用于在检测到第一电压端向第二电压端发送静电信号时，输出检测信号。该检测信号可以用作控制信号；检测电路，还用于将检测信号发送至第一开关和第二开关。可以利用检测电路检测第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并直接向第二开关输入检测信号，控制第一开关和第二开关导通，实现通过第一开关和第二开关进行静电泄放。
在一些可能实现的方式中，控制电路还包括第一反相器；检测电路，用于在检测到第一电压端向第二电压端发送静电信号时，向第一反相器发送检测信号；第一反相器，用于对检测信号取反，得到控制信号，并输出控制信号；检测信号与控制信号互为高低电平。可以利用检测电路检测第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号。之后，将检测信号发送至第一反相器，第一反相器对检测信号取反后，将取反后的控制信号输出。
第一反向器可以将控制信号发送至第二开关，以控制第二开关导通，实现通过第二开关进行静电泄放。还可以将控制信号发送至第一开关，以控制第一开关导通，实现通过第一开关进行静电泄放。相较于下文控制电路包括第二反相器的方案，本方案因控制电路不包括第二反相器，可以减小静电防护电路的版图面积。
相较于前述控制电路不包括第一反相器的方案，控制电路包括第一反相器的方案可以应用在检测电路到第一开关和第二开关的路径过长的场景中。避免因检测电路到第一开关和第二开关的路径过长，导致检测电路输出的信号消耗在所述路径上，使得第一开关和第二开关不能充分导通。
或者，控制电路还包括第二反相器，检测电路，还用于在检测到第一电压端向第二电压端发送静电信号时，向第而反相器发送检测信号。第二反相器，用于对检测信号取反，得到控制信号，并将控制信号发送至第一开关；检测信号与控制信号互为高低电平，以控制第一开关导通，实现通过第一开关进行静电泄放。而第一反相器仍然将控制信号发送至第二开关，以控制第二开关导通，实现通过第二开关进行静电泄放。
本方案的检测电路可以直接将检测信号发送至第二反相器，虽然第二反相器也具有沟道阻抗，但第二反相器与第一开关耦合的路径较短，第二反相器将第一电压端的电压传输至第一开关后，第一开关可以充分导通，也可以说，第一开关强开启，不会影响第一电压端通过第一开关的静电泄放效率。因此，相较于上文控制电路包括第一反相器，不包括第二反相器的方案，本方案可以提高第一电压端通过第一开关的静电泄放效率。
对于上述第一开关、第二开关、第一反相器和第二反相器。例如，上述第一开关可以包括第一晶体管，第二开关可以包括第二晶体管，上述第一反相器包括第一P型晶体管和第一N型晶体管。第二晶体管的栅极与第一反相器耦合，第一极与第二电压端耦合，第二极与接地端耦合。第一P型晶体管的栅极与检测电路的输出端耦合，第一极与第二电压端耦合，第二极与第一晶体管的栅极和第二晶体管的栅极耦合。第一N型晶体管的栅极与检测电路的输出端耦合，第一极与接地端耦合，第二极与第一晶体管的栅极和第二晶体管的栅极耦合。
又例如，上述第一开关可以包括第一晶体管，第二开关可以包括第二晶体管，上述第一反相器包括第一P型晶体管和第一N型晶体管，上述第二反相器包括第二P型晶体管和第二N型晶体管。第二晶体管的的第一极与第二电压端耦合，第二极与接地端耦合。第一P型晶体管的栅极与检测电路的输出端耦合，第一极与第二电压端耦合，第二极与第二晶体管的栅极耦合。第一N型晶体管的栅极与检测电路的输出端耦合，第一极与接地端耦合，第二极与第二晶体管的栅极耦合。第二P型晶体管的栅极与检测电路的输出端耦合，第一极与第一电压端耦合，第二极与第一晶体管的栅极耦合。第二N型晶体管的栅极与检测电路的输出端耦合，第一极与接地端耦合，第二极与第一晶体管的栅极耦合。
又例如，上述第一开关可以包括第一晶体管，第二开关可以包括第二晶体管，在控制电路不包括第一反相器和第二反相器的情况下，第一晶体管的栅极和第二晶体管的栅极可以与检测电路的输出端耦合。
在一些可能实现的方式中，第一晶体管和第二晶体管可以是N型晶体管，也可以是P型晶体管。检测电路为电阻-电容电路，电阻-电容电路包括电阻、电容、以及耦合于电阻与电容之间的输出端。
以电阻耦合于第二电压端与电容-电阻电路的输出端之间，电容耦合于电容-电阻电路的输出端与接地端之间为例，第一开关和第二开关接收第一反相器发送的控制信号时，或者，第一开关接收第二反相器发送的控制信号，第二开关接收第一反相器发送的控制信号时，电阻R对第二电压端VDD的高电平具有延迟作用，因此，从RC电路输出的检测信号为低电平。取反后的控制信号为与低电平相反的高电平，在高电平的控制下，N型的第一晶体管和第二晶体管导通。或者，第一开关和第二开关接收检测电路发送的控制信号时，电阻R对第二电压端VDD的高电平具有延迟作用，因此，从RC电路输出的检测信号为低电平，P型的第一晶体管和第二晶体管在低电平下导通。
以电容耦合于第二电压端与电容-电阻电路的输出端之间，电阻耦合于电容-电阻电路的输出端与接地端之间为例，第一开关和第二开关接收第一反相器发送的控制信号时，或者，第一开关接收第二反相器发送的控制信号，第二开关接收第一反相器发送的控制信号时，由于电容C耦合于第二电压端VDD与RC电路的输出端之间，电容C对第二电压端VDD的高电平没有延迟作用，且第二电压端VDD的高电平可以通过电容C将RC电路的输出端拉高，因此，从RC电路输出的检测信号也为高电平。取反后的控制信号为与高电平相反的低电平，在低电平的控制下，P型的第一晶体管和第二晶体管导通。或者，第一开关和第二开关接收检测电路发送的控制信号时，由于电容C耦合于第二电 压端VDD与RC电路的输出端之间，电容C对第二电压端VDD的高电平没有延迟作用，且第二电压端VDD的高电平可以通过电容C将RC电路的输出端拉高，因此，从RC电路输出的检测信号也为高电平，在高电平的控制下，N型的第一晶体管和第二晶体管导通。
在一些可能实现的方式中，静电防护电路还包括第三晶体管；第三晶体管耦合于第一电压端与第二电压端之间；当第二电压端向第一电压端提供工作电压时，第三晶体管用作三极管；当第一电压端向第二点阿姨端发送静电信号时，第三晶体管的栅极可以悬空，并复用作二极管。
第二方面，提供一种芯片，该芯片包括第一方面所述的静电防护电路。
第二方面的实现方式与第一方面以及第一方面的任意一种实现方式相对应。第二方面的实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
第三方面，提供一种终端，该终端包括第二方面所述的芯片。
第三方面的实现方式与第一方面以及第一方面的任意一种实现方式相对应。第三方面的实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
附图说明
图1为本申请实施例提供的被保护电路集成在芯片中的电路图；
图2为相关技术的静电钳制电路与被保护电路的连接关系图；
图3为相关技术的静电钳制电路与被保护电路的连接关系图；
图4a为本申请实施例提供的一种静电防护电路的电路图；
图4b为本申请实施例提供的一种静电防护电路的电路图；
图5a为本申请实施例提供的一种静电防护电路的电路图；
图5b为本申请实施例提供的一种静电防护电路的电路图；
图6a为本申请实施例提供的一种静电防护电路的电路图；
图6b为本申请实施例提供的一种静电防护电路的电路图；
图7a为本申请实施例提供的一种静电防护电路的电路图；
图7b为本申请实施例提供的一种静电防护电路的电路图；
图8a为本申请实施例提供的一种静电防护电路的电路图；
图8b为本申请实施例提供的一种静电防护电路的电路图；
图9a为本申请实施例提供的一种静电防护电路的电路图；
图9b为本申请实施例提供的一种静电防护电路的电路图；
图10a为本申请实施例提供的一种静电防护电路的电路图；
图10b为本申请实施例提供的一种静电防护电路的电路图；
图11a为本申请实施例提供的一种静电防护电路的电路图；
图11b为本申请实施例提供的一种静电防护电路的电路图。
附图标记：
10-控制电路；11-检测电路；12-第一反相器；13-第二反相器；20-第一开关；30-第二开关；50-被保护器件；60-驱动电路；100-静电钳制电路；200-被保护电路。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。
本申请实施例提供一种终端，终端可以是手机、电脑、平板电脑、电视、车载显示器、智能手表、服务器、存储器、雷达、基站、汽车等包含芯片的设备。当然，终端还可以是其他设备，本申请实施例不对终端的具体形式进行限定。为了方便说明，下文以终端为手机进行举例说明。
手机可以包括多个芯片，芯片中包括一个或多个被保护电路，每个被保护电路包括一个或多个被保护器件。如图1所示，芯片在制造、运输、封装或测试等场景下产生电荷，如果芯片碰触到地，则会形成静电泄放，损坏被保护电路200中的被保护器件。
例如，如图1所示，被保护电路200在制造、运输、封装或测试等场景下可以寄存在任意电路中，该电路包括第二电压端VDD和接地端VSS。被保护电路200包括第一电压端TVDD、以及耦合于第一电压端TVDD与接地端VSS之间的被保护器件50。第二电压端VDD图1以保护器件为包含P型晶体管和N型晶体管的反相器为例。被保护器件50处于工作状态时，电源可以通过第二电压端VDD向第一电压端TVDD提供工作电压；进一步的，第一电压端TVDD可以将工作电压提供给被保护器件50。
芯片中的静电可能导致被保护电路200上的静电电压变高，静电无法有效释放时，不能从被保护电路200释放出去，而是存储在被保护器件50的P型晶体管和N型晶体管中，逐渐使得第一电压端TVDD的电压进一步变高。若晶体管为P型晶体管，则静电电压存储在P型晶体管的N肼中；若晶体管为N型晶体管，则2kV静电电压存储在N 型晶体管的P型衬底中。而不论是P型晶体管的N肼，还是N型晶体管的P型衬底，其在晶体管中所占的面积都比较大。N肼和P型衬底的面积越大，所能存储的静电电荷越多，较高的静电电压在瞬间放电时，将形成较大的峰值电流(peak current)，对N型晶体管和P型晶体管造成冲击，极限情况下，将损坏N型晶体管和P型晶体管。
此处需要说明的是，本申请的被保护电路200可以是集成于芯片中的任意电路，前述示例中，被保护器件50为P型晶体管和N型晶体管仅为示例。可选的，被保护电路200例如可以是低功耗电路。此情况下，被保护电路200中的被保护器件50可以是多阈值器件(multi-threshold complementary metal oxide semiconductor，MTCMOS)、低压差稳压器(low dropout regulator，LDO)或电源栅控器件(power gating)等。
为了防止静电泄放损坏芯片中的被保护器件，如图2所示，相关技术提出在芯片中集成静电泄放钳制电路100，静电电压可以通过静电泄放钳制电路100泄放，从而使被保护电路200始终处于安全状态。
然而，如图3所示，若将静电泄放钳制电路100耦合在第二电压端VDD与接地端VSS之间，则只要第二电压端VDD为高电平，在高电平的控制下，静电泄放钳制电路100即可导通。而第一电压端TVDD又与第二电压端TVDD耦合，因此，在第一电压端TVDD为高电平时，第一电压端VDD可能间接控制静电泄放钳制电路100导通。因此，在被保护器件50正常工作，电源通过第二电压端VDD向第一电压端TVDD提供工作电压时，如果第一电压端TVDD的上电过快(例如ns～us级)，可能在第一电压端TVDD的间接控制下，导致静电泄放钳制电路100误开启，进而第一电压端TVDD、静电泄放钳制电路100、以及接地端VSS形成通路，第一电压端TVDD上的工作电压直接通过静电泄放钳制电路100所在支路流向接地端VSS，也可以说，第一电压端TVDD上的工作电压通过静电泄放钳制电路100所在支路漏电。从而导致第一电压端TVDD上的电压始终较小，达不到理想的电压值，影响晶体管正常工作。
此外，如图3所示，将静电泄放钳制电路100集成在第二电压端VDD与接地端VSS之间，在第二电压端VDD到接地端VSS通路上的电流基本不变时，还需要保证第一电压端TVDD到第二电压端VDD之间的电阻极低，以使得第一电压端TVDD经过第二电压端VDD到接地端VSS路径上的总电压，小于击穿电压阈值。此处需要说明的是，击穿电压阈值，是指：被保护器件50处于可承受的最大的耐压电压。若静电钳制电路100的钳位电压超过此击穿电压阈值，被保护器件50则会形成永久性击穿损毁。
然而，相关技术通过第一电压端TVDD、静电泄放钳制电路100、以及接地端VSS这一通路静电泄放时，由于第一电压端TVDD到第二电压端VDD之间可能集成有多个器件，且无法控制多个器件的阻抗。在多个器件的阻抗较大时，在第一电压端TVDD到第二电压端VDD之间的多个器件的阻抗、静电钳制电路100的钳位电压、以及第一电压端TVDD到第二电压端VDD路径上的寄生电阻的作用下，可能使得第一电压端TVDD到接地端VSS路径上的总电压大于击穿电压阈值，仍然会损坏被保护器件50。其中，第一电压端TVDD与第二电压端VDD之间的器件可以包括二极管，静电泄放时，第一电压端TVDD上的电荷可以通过二极管流向第二电压端VDD。而二极管的尺寸较小，导通时的阻抗较大，从而大大增加第一电压端TVDD到接地端VSS路径上的总电压。
基于上述问题，本申请实施例提供一种静电防护电路，如图4a-图5b所示，静电防护电路可以包括控制电路10、第一开关20、接地端VSS。第一开关20与被保护器件50并联耦合于第一电压端TVDD与接地端之间。控制电路10，用于在检测到第一电压端TVDD向第二电压端VDD发送静电信号时，向第一开关20发送控制信号。第一开关20，用于在所述控制信号的控制下导通。第一开关20导通后，第一电压端TVDD、第一开关20、以及接地端VSS形成通路。这样一来，第一电压端TVDD上的静电电压可以通过第一开关20泄放，避免造成第一电压端TVDD上的静电电压过高，进而避免较高的静电电压在瞬间放电时，形成较大的峰值电流，对被保护器件50造成冲击，损坏被保护器件50。
并且，本申请通过使第一开关20与被保护器件50并联耦合于第一电压端TVDD与接地端VSS之间。静电泄放时，第一电压端TVDD上的静电可以通过第一电压端TVDD、第一开关20、以及接地端VSS这一通路泄放，相较于相关技术，本申请在静电泄放时无需经过第二电压端VDD，可以减短静电泄放路径，减小静电泄放路径上的寄生电阻。并且，本申请还可以控制在第一电压端TVDD、第一开关20、以及接地端VSS这一通路上，不再集成除第一开关20以外的其他器件。这样一来，相较于相关技术，本申请第一电压端TVDD到接地端VSS路径上的总电压不再受其他器件的阻抗的影响。通过减小静电泄放路径上的寄生电阻，以及排除其他器件的阻抗影响，第一电压端TVDD到接地端VSS路径上的总电压可以大大降低，防止第一电压端TVDD到接地端VSS路径上的总电压大于击穿电压阈值，导致被保护器件50被损坏。
在上述电路基础上，如图4a-图5b所示，静电防护电路还可以包括第二开关30，第二开关30耦合于第二电压端VDD与接地端VSS之间。控制电路10，还用于在检测到第一电压端TVDD向第二电压端VDD发送静电信号时，向第二开关30发送控制信号。第二开关30，用于在所述控制信号的控制下导通。第二开关30导通后，第一电压端TVDD、第二电压端VDD、第二开关30、接地端VSS可以形成通路，第一电压端TVDD上的静电电压除了通过第一开关20泄放以外，还可以通过第二开关30泄放。第一电压端TVDD通过第二开关30泄放至少部分静电电压，降低第一电压端TVDD的电压值，防止第一电压端TVDD的电压过大，且电源通过第二电压端VDD向第一电压端TVDD提供工作电压，第一电压端TVDD的上电过快时，导致第一开关20误开启，从而避免工作电压通过第一开关20漏电。
下面结合附图和具体实施例，对静电防护的电路结构及工作原理进行详细说明。
一个实施例中，如图4a和图4b所示，上述第一开关20包括第一晶体管T1，第二开关30包括第二晶体管T2。控制电路10包括检测电路11和第一反相器12。其中，第一晶体管T1和第二晶体管T2均为N型晶体管。第一晶体管T1的第一极与第一电压端TVDD耦合，第二极与接地端VSS耦合。第二晶体管T2的第一极与第二电压端VDD耦合，第二极与接地端VSS耦合。
此处需要说明的是，第一晶体管T1第一极可以是源极，第二极可以是漏极。第二晶体管T2以及下文中的第三晶体管T3、第一P型晶体管P1、第一N型晶体管N1、第二 P型晶体管P2和第二N型晶体管N2的第一极也可以是源极，第二极也可以是漏极。下文不再赘述。
检测电路11可以是电阻-电容(RC)电路，检测电路11包括电阻R电容C、以及耦合于电阻R与电容C之间的输出端。电阻R耦合于第二电压端VDD与RC电路的输出端之间，电容C耦合于接地端VSS与RC电路的输出端之间。
第一反相器12的控制端与RC电路的输出端耦合，第一反相器12的输入端分别与第二电压端VDD和接地端VSS耦合，第一反相器12的输出端与第一晶体管T1和第二晶体管T2的栅极耦合。具体的，第一反相器12可以包括第一P型晶体管P1和第一N型晶体管N1。第一P型晶体管P1的栅极与RC电路的输出端耦合，第一P型晶体管P1的第一极与第二电压端VDD耦合，第一P型晶体管P1的第二极与第一晶体管T1和第二晶体管T2的栅极耦合。第一N型晶体管N1的栅极与RC电路的输出端耦合，第一N型晶体管N1的第一极与接地端VSS耦合，第一N型晶体管N1的第二极与第一晶体管T1的栅极和第二晶体管T2的栅极耦合。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图4a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷经过第二电压端VDD向低电势接地端VSS流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。其中，第三晶体管T3可以是P型晶体管。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件(ESD event)，RC电路的输出端输出检测信号。由于电阻R耦合于第二电压端VDD与RC电路的输出端之间，电阻R对第二电压端VDD的高电平有延迟作用，从RC电路输出的检测信号为与高电平相反的低电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路确定判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的低电平可以传输至第一P型晶体管P1的栅极和第一N型晶体 管N1的栅极，作为第一P型晶体管P1和第一N型晶体管N1的使能信号。在低电平的控制下，第一P型晶体管P1导通，第一N型晶体管N1截止。第一P型晶体管P1导通后，可以向第一晶体管T1和第二晶体管T2发送控制信号。即，第一P型晶体管P1的第一极通过第一P型晶体管P1的第二极，将第二电压端VDD的高电平发送至第一晶体管T1的栅极和第二晶体管T2的栅极。
由于第一晶体管T1和第二晶体管T2为N型晶体管，因此，第一晶体管T1和第二晶体管T2在高电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
如图4b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第一反相器12输出低电平，以使第一P型晶体管P1导通。第一P型晶体管P1将第二电压端VDD的高电平发送至第一晶体管T1的栅极，使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括第二开关30的情况下，控制电路10可以包括RC电路和第一反相器12，且RC电路与第一反相器12之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
另一个实施例中，如图5a和图5b所示，在控制电路10不包括第一反相器12(或者控制电路不包括第一反相器以及下文的第二反相器)时，本申请实施例的第一晶体管T1 和第二晶体管T2可以为P型晶体管，第一晶体管T1和第二晶体管T2的栅极可以与RC电路的输出端耦合。此外，图5a和图5b所示的方案中的其他电路结构，与图4a和图4b所示的方案中的其他电路结构相同。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图5a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷经过第二电压端VDD向低电势接地端VSS流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。其中，第三晶体管T3可以是P型晶体管。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件(ESD event)，RC电路的输出端输出检测信号。由于电阻R耦合于第二电压端VDD与RC电路的输出端之间，电阻R对第二电压端VDD的高电平有延迟作用，从RC电路输出的检测信号为与高电平相反的低电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号，该检测信号可以用作控制信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路确定判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的低电平可以传输至第一晶体管T1和第二晶体管T2的栅极，由于第一晶体管T1和第二晶体管T2为P型晶体管，因此，第一晶体管T1和第二晶体管T2在低电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
并且，相较于前述图4a所示的控制电路10包括第一反相器12的方案，本申请实施 例可以减小静电防护电路的版图面积。但是，前述控制电路10包括第一反相器12的方案，可以应用在RC电路到第一晶体管T1的栅极和第二晶体管T2的栅极的路径过长的场景中。避免因RC电路到第一晶体管T1的栅极和第二晶体管T2的栅极的路径过长，导致RC电路输出的信号消耗在所述路径上，使得第一晶体管T1和第二晶体管T2不能充分导通。
如图5b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第一晶体管T1输出低电平，以使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括第二开关30的情况下，控制电路10可以包括RC电路和第一反相器12，且RC电路与第一反相器12之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
又一个实施例中，如图6a和图6b所示，上述第一开关20包括第一晶体管T1，第二开关30包括第二晶体管T2。控制电路10包括检测电路11和第一反相器12。其中，第一晶体管T1和第二晶体管T2均为P型晶体管。第一晶体管T1的第一极与第一电压端TVDD耦合，第二极与接地端VSS耦合。第二晶体管T2的第一极与第二电压端VDD耦合，第二极与接地端VSS耦合。
检测电路11可以是RC电路，检测电路11包括电阻R、电容C、以及耦合于电阻R与电容C之间的输出端。电容C耦合于第二电压端VDD与RC电路的输出端之间，电阻R耦合于接地端VSS与RC电路的输出端之间。
第一反相器12的控制端与RC电路的输出端耦合，第一反相器12的输入端分别与第二电压端VDD和接地端VSS耦合，第一反相器12的输出端与第二晶体管T2的栅极耦合。具体的，第一反相器12可以包括第一P型晶体管P1和第一N型晶体管N1。第一P型晶体管P1的栅极与RC电路的输出端耦合，第一P型晶体管P1的第一极与第二 电压端VDD耦合，第一P型晶体管P1的第二极与第一晶体管T1和第二晶体管T2的栅极耦合。第一N型晶体管N1的栅极与RC电路的输出端耦合，第一N型晶体管N1的第一极与接地端VSS耦合，第一N型晶体管N1的第二极与第一晶体管T1的栅极和第二晶体管T2的栅极耦合。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图6a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷向低电势流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，RC电路的输出端输出检测信号。由于电容C耦合于第二电压端VDD与RC电路的输出端之间，电容C对第二电压端VDD的高电平没有延迟作用，且第二电压端VDD的高电平可以通过电容C将RC电路的输出端拉高，因此，从RC电路输出的检测信号也为高电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的高电平可以传输至第一P型晶体管P1的栅极和第一N型晶体管N1的栅极，作为第一P型晶体管P1和第一N型晶体管N1的使能信号。在高电平的控制下，第一N型晶体管N1导通，第一P型晶体管P1截止。第一N型晶体管N1导通后，可以向第一晶体管T1和第二晶体管T2发送控制信号。即，第一N型晶体管N1的第一极通过第一N型晶体管N1的第二极，将接地端VSS的低电平发送至第一晶体管T1的栅极和第二晶体管T2的栅极。
由于第一晶体管T1和第二晶体管T2为P型晶体管，因此，第一晶体管T1和第二晶体管T2在低电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通 过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
如图6b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第一反相器输出高电平，以使第一N型晶体管1导通。第一N型晶体管N1将接地端VSS的低电平发送至第一晶体管T1的栅极，使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括第二开关30的情况下，控制电路10可以包括RC电路和第一反相器12，且RC电路与第一反相器12之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
又一个实施例中，如图7a和图7b所示，在控制电路不包括第一反相器12(或者控制电路不包括第一反相器以及下文的第二反相器)时，本申请实施例的第一晶体管T1和第二晶体管T2可以为N型晶体管，第一晶体管T1和第二晶体管T2的栅极可以与RC电路的输出端耦合。此外，图7a和图7b所示的方案中的其他电路结构，与图6a和图6b所示的方案中的其他电路结构相同。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图7a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷向低电势流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶 段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，RC电路的输出端输出检测信号。由于电容C耦合于第二电压端VDD与RC电路的输出端之间，电容C对第二电压端VDD的高电平没有延迟作用，且第二电压端VDD的高电平可以通过电容C将RC电路的输出端拉高，因此，从RC电路输出的检测信号也为高电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号，该检测信号可以用作控制信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的高电平可以传输至第一晶体管T1和第二晶体管T2的栅极，由于第一晶体管T1和第二晶体管T2为N型晶体管，因此，第一晶体管T1和第二晶体管T2在高电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
并且，相较于前述图6a所示的控制电路10包括第一反相器12的方案，本申请实施例可以减小静电防护电路的版图面积。但是，前述控制电路10包括第一反相器12的方案，可以应用在RC电路到第一晶体管T1的栅极和第二晶体管T2的栅极的路径过长的场景中。避免因RC电路到第一晶体管T1的栅极和第二晶体管T2的栅极的路径过长，导致RC电路输出的信号消耗在所述路径上，使得第一晶体管T1和第二晶体管T2不能充分导通。
如图7b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第一晶体管T1输出低电平，以使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括第二开关30的情况下，控制电路10可以包括RC电路和第一反相器12，且RC电路与第一反相器12之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
又一个实施例中，如图8a和图8b所示，上述第一开关20包括第一晶体管T1，第二开关30包括第二晶体管T2。控制电路10包括检测电路11、第一反相器12和第二反相器13。其中，第一晶体管T1和第二晶体管T2均为N型晶体管。第一晶体管T1的第一极与第一电压端TVDD耦合，第二极与接地端VSS耦合。第二晶体管T2的第一极与第二电压端VDD耦合，第二极与接地端VSS耦合。
检测电路11可以是RC电路，检测电路11包括电阻R和电容C，电阻R耦合于第二电压端VDD与RC电路的输出端之间，电容C耦合于接地端VSS与RC电路的输出端之间。
第一反相器12的控制端与RC电路的输出端耦合，第一反相器12的输入端分别与第二电压端VDD和接地端VSS耦合，第一反相器12的输出端与第二晶体管T2的栅极耦合。具体的，第一反相器12可以包括第一P型晶体管P1和第一N型晶体管N1。第一P型晶体管P1的栅极与RC电路的输出端耦合，第一P型晶体管P1的第一极与第二电压端VDD耦合，第一P型晶体管P1的第二极与第二晶体管T2的栅极耦合。第一N型晶体管N1的栅极与RC电路的输出端耦合，第一N型晶体管N1的第一极与接地端VSS耦合，第一N型晶体管N1的第二极与第二晶体管T2的栅极耦合。
第二反相器13的控制端与RC电路的输出端耦合，第二反相器13的输入端分别与第一电压端TVDD和接地端VSS耦合，第二反相器13的输出端与第一晶体管T1的栅极耦合。具体的，第二反相器13可以包括第二P型晶体管P2和第二N型晶体管N2。第二P型晶体管P2的栅极与RC电路的输出端耦合，第二P型晶体管P2的第一极与第一电压端TVDD耦合，第二P型晶体管P2的第二极与第一晶体管T1的栅极耦合。第二N型晶体管N2的栅极与RC电路的输出端耦合，第二N型晶体管N2的第一极与接地端VSS耦合，第二N型晶体管N2的第二极与第一晶体管T1的栅极耦合。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图8a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷经过第二电压端VDD向低电势流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。其中，第三晶体管T3可以是P型晶体管。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，RC电路的输出端输出检测信号。由于电阻R耦合于第二电压端VDD与RC电路的输出端之间，电阻R对第二电压端VDD的高电平有延迟作用，从RC电路输出的检测信号为与高电平相反的低电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路确定判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的低电平可以传输至第一P型晶体管P1的栅极、第一N型晶体管N1的栅极、第二P型晶体管P2的栅极、第二N型晶体管N2的栅极，作为第一P型晶体管P1、第一N型晶体管N1、第二P型晶体管P2、以及第二N型晶体管N2的使能信号。在低电平的控制下，第一P型晶体管P1和第二P型晶体管P2导通，第一N型晶体管N1和第二N型晶体管N2截止。第一P型晶体管P1导通后，可以向第一晶体管T1和第二晶体管T2发送控制信号。即，第一P型晶体管P1的第一极通过第一P型晶体管P1的第二极，将第二电压端VDD的高电平发送至第二晶体管T2的栅极。第二P型晶体管P2导通后，可以向第一晶体管T1和第二晶体管T2发送控制信号。即，第二P型晶体管P2的第一极通过第二P型晶体管P2的第二极，将第一电压端TVDD的高电平发送至第一晶体管T1的栅极。
由于第一晶体管T1和第二晶体管T2为N型晶体管，因此，第一晶体管T1和第二晶体管T2在高电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通 过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
此外，第一反相器12的第一P型晶体管P1和第二反相器13的第二P型晶体管P2在导通时，具有沟道阻抗。对于图4a所示的控制电路10不包括第二反相器13的方案，第一P型晶体管P1通过较长路径与第一晶体管T1的栅极耦合，导致到达第一晶体管T1的栅极的沟道阻抗进一步增大。第一P型晶体管P1将第二电压端VDD的电压传输至第一晶体管T1后，需被第一晶体管T1的栅极分一部分电压，导致传输至第一晶体管T1的栅极、用于开启第一晶体管T1的电压减小，第一晶体管T1导通不充分，也可以说，第一晶体管T1弱开启，从而导致第一电压端TVDD通过第一晶体管T1的静电泄放效率低。
而对于本实施例的控制电路10包括第二反相器13的方案，RC电路可以直接将低电平发送至第二P型晶体管P2的栅极，虽然第二P型晶体管P2也具有沟道阻抗，但第二P型晶体管P2与第一晶体管T1的栅极耦合的路径较短，第二P型晶体管P2将第一电压端TVDD的电压传输至第一晶体管T1后，被第一晶体管T1的栅极分去的电压较小，第一晶体管T1可以充分导通，也可以说，第一晶体管T1强开启，不会影响第一电压端TVDD通过第一晶体管T1的静电泄放效率。因此，相较于控制电路10不包括第二反相器13的方案，本实施例可以提高第一电压端TVDD通过第一晶体管T1的静电泄放效率。
当然，相较于本实施例控制电路10包括第二反相器13的方案，图4a所示的方案因控制电路10不包括第二反相器13，可以减小静电防护电路的版图面积。
如图8b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第一反相器12和第二反相器13输出低电平，以使第二P型晶体管P2导通。第二P型晶体管P2将第一电压端TVDD的高电平发送至第一晶体管T1的栅极，使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括第二开关30的情况下，控制电路10可以包括RC电路和第二反相器13，且RC电路与第二反相器13之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
又一个实施例中，如图9a和图9b所示，在控制电路10不包括第一反相器12，但包括第二反相器13时，本申请实施例的第一晶体管T1可以为N型晶体管，第二晶体管T2可以为P型晶体管，第一晶体管T1的栅极可以与第二反相器13耦合，第二晶体管T2的栅极可以与RC电路的输出端耦合。此外，图9a和图9b所示的方案中的其他电路结构，与图8a和图8b所示的方案中的其他电路结构相同。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图9a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷经过第二电压端VDD向低电势流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。其中，第三晶体管T3可以是P型晶体管。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，RC电路的输出端输出检测信号。由于电阻R耦合于第二电压端VDD与RC电路的输出端之间，电阻R对第二电压端VDD的高电平有延迟作用，从RC电路输出的检测信号为与高电平相反的低电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路确定判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的低电平可以传输至第二P型晶体管P2的栅极、第二N型晶体管N2的栅极、以及第二晶体管T2的栅极，作为第二P型晶体管P2、第二N型晶体管N2、以及第二晶体管T2的使能信号。在低电平的控制下，第二P型晶体管P2和第二晶体管T2导通，第二N型晶体管N2截止。第二P型晶体管P2导通后，可以向第一晶体 管T1发送控制信号。即，第二P型晶体管P2的第一极通过第二P型晶体管P2的第二极，将第一电压端TVDD的高电平发送至第一晶体管T1的栅极。由于第一晶体管T1为N型晶体管，因此，第一晶体管T1在高电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
对于本实施例的控制电路10包括第二反相器13的方案，RC电路可以直接将低电平发送至第二P型晶体管P2的栅极，虽然第二P型晶体管P2也具有沟道阻抗，但第二P型晶体管P2与第一晶体管T1的栅极耦合的路径较短，第二P型晶体管P2将第一电压端TVDD的电压传输至第一晶体管T1后，被第一晶体管T1的栅极分去的电压较小，第一晶体管T1可以充分导通，也可以说，第一晶体管T1强开启，不会影响第一电压端TVDD通过第一晶体管T1的静电泄放效率。因此，相较于控制电路10不包括第二反相器13的方案，本实施例可以提高第一电压端TVDD通过第一晶体管T1的静电泄放效率。
当然，相较于本实施例控制电路10包括第二反相器13的方案，图5a所示的方案因控制电路10不包括第二反相器13，可以减小静电防护电路的版图面积。
如图9b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第二反相器13输出低电平，经第二反相器13取反后，将取反后的高电平输入至第一晶体管T1，以使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括 第二开关30的情况下，控制电路10可以包括RC电路和第二反相器13，且RC电路与第二反相器13之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
又一个实施例中，如图10a和图10b所示，上述第一开关20包括第一晶体管T1，第二开关30包括第二晶体管T2。控制电路10包括检测电路11、第一反相器12和第二反相器13。其中，第一晶体管T1和第二晶体管T2均为P型晶体管。第一晶体管T1的第一极与第一电压端TVDD耦合，第二极与接地端VSS耦合。第二晶体管T2的第一极与第二电压端VDD耦合，第二极与接地端VSS耦合。
检测电路11可以是RC电路，检测电路11包括电阻R和电容C、以及耦合于电阻R与电容C之间的输出端。电容C耦合于第二电压端VDD与RC电路的输出端之间，电阻R耦合于接地端VSS与RC电路的输出端之间。
第一反相器12的控制端与RC电路的输出端耦合，第一反相器12的输入端分别与第二电压端VDD和接地端VSS耦合，第一反相器12的输出端与第二晶体管T2的栅极耦合。具体的，第一反相器12可以包括第一P型晶体管P1和第一N型晶体管N1。第一P型晶体管P1的栅极与RC电路的输出端耦合，第一P型晶体管P1的第一极与第二电压端VDD耦合，第一P型晶体管P1的第二极与第二晶体管T2的栅极耦合。第一N型晶体管N1的栅极与RC电路的输出端耦合，第一N型晶体管N1的第一极与接地端VSS耦合，第一N型晶体管N1的第二极与第二晶体管T2的栅极耦合。
第二反相器13的控制端与RC电路的输出端耦合，第二反相器13的输入端分别与第一电压端TVDD和接地端VSS耦合，第二反相器13的输出端与第一晶体管T1的栅极耦合。具体的，第二反相器13可以包括第二P型晶体管P2和第二N型晶体管N2。第二P型晶体管P2的栅极与RC电路的输出端耦合，第二P型晶体管P2的第一极与第一电压端TVDD耦合，第二P型晶体管P2的第二极与第一晶体管T1的栅极耦合。第二N型晶体管N2的栅极与RC电路的输出端耦合，第二N型晶体管N2的第一极与接地端VSS耦合，第二N型晶体管N2的第二极与第一晶体管T1的栅极耦合。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图10a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷经过第二电压端VDD向低电势流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。其中，第三晶体管T3可以是P型晶体管。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，RC电路的输出端输出 检测信号。由于电容C耦合于第二电压端VDD与RC电路的输出端之间，电容C对第二电压端VDD的高电平没有延迟作用，且第二电压端VDD的高电平可以通过电容C将RC电路的输出端拉高，因此，从RC电路输出的检测信号也为高电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路确定判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的高电平可以传输至第一P型晶体管P1的栅极、第一N型晶体管N1的栅极、第二P型晶体管P2的栅极、第二N型晶体管N2的栅极，作为第一P型晶体管P1、第一N型晶体管N1、第二P型晶体管P2、以及第二N型晶体管N2的使能信号。在高电平的控制下，第一N型晶体管N1和第二N型晶体管N2导通，第一P型晶体管P1和第二P型晶体管P2截止。第一N型晶体管N1导通后，可以向第一晶体管T1和第二晶体管T2发送控制信号。即，第一N型晶体管N1的第一极通过第一N型晶体管N1的第二极，将接地端VSS的低电平发送至第二晶体管T2的栅极。第二N型晶体管N2导通后，可以向第一晶体管T1和第二晶体管T2发送控制信号。即，第二N型晶体管N2的第一极通过第二N型晶体管N2的第二极，将接地端VSS的低电平发送至第一晶体管T1的栅极。
由于第一晶体管T1和第二晶体管T2为P型晶体管，因此，第一晶体管T1和第二晶体管T2在低电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
此外，第一反相器12的第一N型晶体管N1和第二反相器13的第二N型晶体管N2在导通时，具有沟道阻抗。对于图5a所示的控制电路10不包括第二反相器13的方案，第一N型晶体管N1通过较长路径与第一晶体管T1的栅极耦合，导致到达第一晶体管T1的栅极的沟道阻抗进一步增大。第一N型晶体管N1将接地端VSS的电压传输至第一晶体管T1后，需被第一晶体管T的栅极分一部分电压，导致传输至第一晶体管T1的栅极、用于开启第一晶体管T1的电压减小，第一晶体管T1导通不充分，也可以说，第一晶体管T1弱开启，从而导致第一电压端TVDD通过第一晶体管T1的静电泄放效率低。
而对于本实施例的控制电路10包括第二反相器13的方案，RC电路可以直接将高电 平发送至第二N型晶体管N2的栅极，虽然第二N型晶体管N2也具有沟道阻抗，但第二N型晶体管N2与第一晶体管T1的栅极耦合的路径较短，第二N型晶体管N2将第一电压端TVDD的电压传输至第一晶体管T1后，被第一晶体管T1的栅极分去的电压较小，第一晶体管T1可以充分导通，也可以说，第一晶体管T1强开启，不会影响第一电压端TVDD通过第一晶体管T1的静电泄放效率。因此，相较于控制电路10不包括第二反相器13的方案，本实施例可以提高第一电压端TVDD通过第一晶体管T1的静电泄放效率。
当然，相较于本实施例控制电路10包括第二反相器13的方案，图5a所示的方案因控制电路10不包括第二反相器13，可以减小静电防护电路的版图面积。
如图10b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第一反相器12和第二反相器13输出高电平，以使第二N型晶体管N2导通。第二N型晶体管N2将接地端VSS的低电平发送至第一晶体管T1的栅极，使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括第二开关30的情况下，控制电路10可以包括RC电路和第二反相器13，且RC电路与第二反相器13之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
又一个实施例中，如图11a和图11b所示，在控制电路10不包括第一反相器12，但包括第二反相器13时，本申请实施例的第一晶体管T1可以为P型晶体管，第二晶体管T2可以为N型晶体管，第一晶体管T1的栅极可以与第二反相器13耦合，第二晶体管T2的栅极可以与RC电路的输出端耦合。此外，图11a和图11b所示的方案中的其他电路结构，与图10a和图10b所示的方案中的其他电路结构相同。
基于本实施例的电路结构，静电防护电路可以工作在静电泄放阶段和正常工作阶段。
如图11a所示，在静电泄放阶段：芯片因制造、运输、封装或测试等原因产生电荷，如果芯片接触到地，则会形成静电泄放，第一电压端TVDD上的电荷经过第二电压端 VDD向低电势流动。电荷流至第二电压端VDD，第二电压端VDD的电压被迅速拉高。此处需要说明的是，相较于接地端VSS上的电压，第二电压端VDD上的电压和第一电压端TVDD上的电压为高电平。
在一些可能实现的方式中，静电防护电路还可以包括第三晶体管T3，在静电泄放阶段，通过将第三晶体管T3的栅极悬空(即，第三晶体管T3的栅极不加任何电压，也可以说，不向第三晶体管T3输入高电平和低电平)，使第三晶体管T3的源极、体端、以及漏极可以构成二极管。第一电压端TVDD上的电荷可以通过二极管向低电势流动。其中，第三晶体管T3可以是P型晶体管。
当RC电路检测到第一电压端TVDD向第二电压端VDD发送静电信号时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，RC电路的输出端输出检测信号。由于电容C耦合于第二电压端VDD与RC电路的输出端之间，电容C对第二电压端VDD的高电平没有延迟作用，且第二电压端VDD的高电平可以通过电容C将RC电路的输出端拉高，因此，从RC电路输出的检测信号也为高电平。
本申请实施例可以利用RC电路识别到第二电压端VDD的脉冲上升沿，与静电电压的脉冲上升沿匹配时，判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件，并输出检测信号。例如，若静电电压的脉冲上升沿发生在ns级到μs之间，则RC电路确定判定第一电压端TVDD上的电荷流至第二电压端VDD为静电泄放事件。当然，其他场景下的静电电压的脉冲上升沿还可能发生在其他时间范围内，本申请实施例对此不作限定，只要预先设定RC电路识别静电电压的方式即可。也可以说，当RC电路第一电压端TVDD向第二电压端VDD发送静电信号时，第二电压端VDD的电平快速上升，RC电路上的电压增大。
接着，RC电路输出的高电平可以传输至第二P型晶体管P2的栅极、第二N型晶体管N2的栅极、以及及第二晶体管T2的栅极，作为第二P型晶体管P2、第二N型晶体管N2、以及第二晶体管T2的使能信号。在高电平的控制下，第二N型晶体管N2和第二晶体管T2导通，第二P型晶体管P2截止。第二N型晶体管N2导通后，可以向第一晶体管T1发送控制信号。即，第二N型晶体管N2的第一极通过第二N型晶体管N2的第二极，将接地端VSS的低电平发送至第一晶体管T1的栅极。由于第一晶体管T1为P型晶体管，因此，第一晶体管T1在低电平的控制下导通。第一电压端TVDD上的静电电压可以分别通过第一晶体管T1和第二晶体管T2泄放至接地端VSS。
此处需要说明的是，即使因第一电压端TVDD与第二电压端VDD间的阻抗较大，导致第二晶体管T2的静电泄放效果不好，也不影响第一电压端TVDD上的静电电压通过第一晶体管T1泄放至接地端VSS。并且，虽然第一电压端TVDD也可以间接控制第一晶体管T1导通，但由于至少部分静电电压可以通过第二晶体管T2泄放。因此，即使第一电压端TVDD的上电过快，也不会第一开关20误开启，从而避免第一电压端TVDD上的工作电压通过第一开关20漏电。
对于本实施例的控制电路10包括第二反相器13的方案，RC电路可以直接将高电平发送至第二N型晶体管N2的栅极，虽然第二N型晶体管N2也具有沟道阻抗，但第二N型晶体管N2与第一晶体管T1的栅极耦合的路径较短，第二N型晶体管N2将第一电压 端TVDD的电压传输至第一晶体管T1后，被第一晶体管T1的栅极分去的电压较小，第一晶体管T1可以充分导通，也可以说，第一晶体管T1强开启，不会影响第一电压端TVDD通过第一晶体管T1的静电泄放效率。因此，相较于控制电路10不包括第二反相器13的方案，本实施例可以提高第一电压端TVDD通过第一晶体管T1的静电泄放效率。
当然，相较于本实施例控制电路10包括第二反相器13的方案，图7a所示的方案因控制电路10不包括第二反相器13，可以减小静电防护电路的版图面积。
如图11b所示，在正常工作阶段：第二电压端VDD可以与电源耦合，电源通过第二电压端VDD向第一电压端TVDD输入工作电压，使被保护器件50正常工作在第一电压端TVDD与接地端VSS之间。
在一些可能实现的方式中，静电防护电路还可以包括驱动电路60，在正常工作阶段，驱动电路60可以为第三晶体管T3的栅极提供低电平，使第三晶体管T3导通。进一步的，第二电压端VDD可以通过第三晶体管T3将工作电压发送至第一电压端TVDD。
此外，在正常工作阶段，若芯片中除被保护电路200以外的其他电路存在静电电压，且该静电电压通过电源传输至第二电压端VDD和第一电压端TVDD，则一旦被RC电路判定电荷通过电源流至第二电压端VDD为静电泄放事件，RC电路也可以向第二反相器13输出高电平，经第二反相器13取反后，将取反后的低电平输入至第一晶体管T1，以使第一晶体管T1导通。进而使从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放至接地端VSS。
此情况下，由于第一晶体管T1与被保护器件50并联，因此，从电源传输至第一电压端TVDD的静电电压，通过第一晶体管T1泄放的同时，不会影响被保护电路200的正常工作。并且，由于第一电压端TVDD通过第一晶体管T1泄放了静电电压，还可以避免第一电压端TVDD到接地端VSS路径上的总电压较大，也可以说，避免第一电压端TVDD与接地端VSS之间的钳位电压较大，导致被保护器件50被损坏。
此外，需要说明的是，本实施例是以静电防护电路包括第一开关20和第二开关30举例，说明静电防护电路的工作原理。但是，在静电防护电路包括第一开关20、不包括第二开关30的情况下，控制电路10可以包括RC电路和第二反相器13，且RC电路与第二反相器13之间的连接关系以及工作原理，与本实施例相同，在此不再赘述。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (18)

  1. 一种静电防护电路，其特征在于，包括控制电路、第一钳制电路、第一电压端、第二电压端和接地端；所述第一开关和被保护器件并联耦合于所述第一电压端与所述接地端之间；
    所述第二电压端用于向所述第一电压端提供工作电压；
    所述控制电路，用于在检测到所述第一电压端向所述第二电压端发送静电信号时，向所述第一开关发送控制信号；
    所述第一开关，用于在所述控制信号的控制下导通。
  2. 根据权利要求1所述的静电防护电路，其特征在于，所述静电防护电路还包括第二开关；所述第二开关耦合于所述第二电压端与所述接地端之间；
    所述控制电路，还用于在检测到所述第一电压端向所述第二电压端发送静电信号时，向所述第二开关发送控制信号；
    所述第二开关，用于在所述控制信号的控制下导通。
  3. 根据权利要求2所述的静电防护电路，其特征在于，所述控制电路包括检测电路，所述检测电路串接于所述第二电压端与所述接地端之间；
    所述检测电路，用于在检测到所述第一电压端向所述第二电压端发送静电信号时，输出检测信号。
  4. 根据权利要求3所述的静电防护电路，其特征在于，所述检测信号用作所述控制信号；所述检测电路，还用于将所述检测信号发送至所述第二开关。
  5. 根据权利要求3所述的静电防护电路，其特征在于，所述控制电路还包括第一反相器，所述第一反相器耦合于所述第二电压端与所述接地端之间，且所述第一反相器的控制端与所述检测电路的输出端耦合；
    所述第一反相器，用于对所述检测信号取反，得到所述控制信号，并输出控制信号；所述检测信号与所述控制信号互为高低电平。
  6. 根据权利要求5所述的静电防护电路，其特征在于，所述第一反相器，还用于将所述控制信号发送至所述第二开关。
  7. 根据权利要求4或6所述的静电防护电路，其特征在于，所述第二开关包括第二晶体管；所述第二晶体管的第一极与所述第二电压端耦合，所述第二晶体管的第二极与所 述接地端耦合；
    在所述检测电路向所述第二开关发送所述控制信号的情况下，所述第二晶体管的栅极与所述检测电路耦合；
    在所述第一反相器向所述第二开关发送所述控制信号的情况下，所述第二晶体管的栅极与所述第一反相器耦合。
  8. 根据权利要求3-4、7任一项所述的静电防护电路，其特征在于，所述检测电路，还用于在所述检测信号用作所述控制信号时，将所述检测信号发送至所述第一开关。
  9. 根据权利要求5-7任一项所述的静电防护电路，其特征在于，第一反相器，还用于将所述控制信号发送至第一开关。
  10. 根据权利要求8或9所述的静电防护电路，其特征在于，所述第一开关还包括第一晶体管；所述第一晶体管的第一极与所述第一电压端耦合，所述第一晶体管的第二极与所述接地端耦合；
    在所述检测电路向所述第一开关发送所述控制信号的情况下，所述第一晶体管的栅极与所述检测电路耦合；
    在所述第一反相器向所述第一开关发送所述控制信号的情况下，所述第一晶体管的栅极与所述第一反相器耦合。
  11. 根据权利要求3-7任一项所述的静电防护电路，其特征在于，所述控制电路还包括第二反相器；
    所述检测电路，还用于在检测到所述第二电压端向所述第二电压端发送静电信号时，向所述第二反相器发送检测信号；
    所述第二反相器，用于对所述检测信号取反，得到所述控制信号，并将所述控制信号发送至所述第一开关。
  12. 根据权利要求11所述的静电防护电路，其特征在于，所述第一开关还包括第一晶体管；
    所述第一晶体管的栅极与所述第二反相器耦合，第一极与所述第一电压端耦合，第二极与所述接地端耦合。
  13. 根据权利要求3-10任一项所述的静电防护电路，其特征在于，所述检测电路为电阻-电容电路；
    所述电阻-电容电路包括电阻、电容、以及耦合于所述电阻与所述电容之间的输出端。
  14. 根据权利要求13所述的静电防护电路，其特征在于，所述电阻耦合于所述第二电压端与所述电容-电阻电路的输出端之间，所述电容耦合于所述电容-电阻电路的输出端与所述接地端之间；
    所述第一开关和所述第二开关接收所述第一反相器发送的所述控制信号时，或者，所述第一开关接收所述第二反相器发送的所述控制信号，所述第二开关接收所述第一反相器发送的所述控制信号时，所述第一开关的第一晶体管和所述第二开关的第二晶体管为N型晶体管；或者，
    所述第一开关和所述第二开关接收所述检测电路发送的所述控制信号时，所述第一开关的第一晶体管和所述第二开关的第二晶体管为P型晶体管。
  15. 根据权利要求13所述的静电防护电路，其特征在于，所述电容耦合于所述第二电压端与所述电容-电阻电路的输出端之间，所述电阻耦合于所述电容-电阻电路的输出端与所述接地端之间；
    所述第一开关和所述第二开关接收所述第一反相器发送的所述控制信号时，或者，所述第一开关接收所述第二反相器发送的所述控制信号，所述第二开关接收所述第一反相器发送的所述控制信号时，所述第一开关的第一晶体管和所述第二开关的第二晶体管为P型晶体管；或者，
    所述第一开关和所述第二开关接收所述检测电路发送的所述控制信号时，所述第一开关的第一晶体管和所述第二开关的第二晶体管为N型晶体管。
  16. 根据权利要求1-15任一项所述的静电防护电路，其特征在于，所述静电防护电路还包括第三晶体管；所述第三晶体管耦合于所述第一电压端与所述第二电压端之间；
    当所述第二电压端向所述第一电压端提供工作电压时，所述第三晶体管用作三极管；
    当所述第一电压端向所述第二点阿姨端发送静电信号时，所述第三晶体管用作二极管。
  17. 一种芯片，其特征在于，包括权利要求1-16任一项所述的静电防护电路。
  18. 一种终端，其特征在于，包括权利要求17所述的芯片。
PCT/CN2021/135828 2021-12-06 2021-12-06 静电防护电路、芯片和终端 WO2023102697A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116914714A (zh) * 2023-09-13 2023-10-20 上海韬润半导体有限公司 一种静电保护电路及其实现方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120236448A1 (en) * 2011-03-16 2012-09-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US20120307405A1 (en) * 2011-06-02 2012-12-06 Globalfoundries Inc. Integrated circuit having electrostatic discharge protection
CN103683235A (zh) * 2012-09-24 2014-03-26 上海华虹宏力半导体制造有限公司 静电放电自保护电路
CN104104071A (zh) * 2013-04-01 2014-10-15 索尼公司 保护电路、电子装置及驱动保护电路的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120236448A1 (en) * 2011-03-16 2012-09-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US20120307405A1 (en) * 2011-06-02 2012-12-06 Globalfoundries Inc. Integrated circuit having electrostatic discharge protection
CN103683235A (zh) * 2012-09-24 2014-03-26 上海华虹宏力半导体制造有限公司 静电放电自保护电路
CN104104071A (zh) * 2013-04-01 2014-10-15 索尼公司 保护电路、电子装置及驱动保护电路的方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116914714A (zh) * 2023-09-13 2023-10-20 上海韬润半导体有限公司 一种静电保护电路及其实现方法
CN116914714B (zh) * 2023-09-13 2023-12-01 上海韬润半导体有限公司 一种静电保护电路及其实现方法

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