WO2021244271A1 - 片上终端电路及存储器设备 - Google Patents

片上终端电路及存储器设备 Download PDF

Info

Publication number
WO2021244271A1
WO2021244271A1 PCT/CN2021/094076 CN2021094076W WO2021244271A1 WO 2021244271 A1 WO2021244271 A1 WO 2021244271A1 CN 2021094076 W CN2021094076 W CN 2021094076W WO 2021244271 A1 WO2021244271 A1 WO 2021244271A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
transistor
electrically connected
signal input
resistance
Prior art date
Application number
PCT/CN2021/094076
Other languages
English (en)
French (fr)
Inventor
刘志拯
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/385,439 priority Critical patent/US11888474B2/en
Publication of WO2021244271A1 publication Critical patent/WO2021244271A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Definitions

  • This application relates to the field of memory, and in particular to an on-chip terminal circuit and a memory device.
  • Memory devices degrade signal integrity due to the increase in their capacity and operating speed. For example, as the operating speed of the memory device increases, the bandwidth of the data transmitted by the channel of the memory controller connected to the memory device may increase, which may reduce signal quality. Therefore, on-chip termination (ODT, On Die Termination) circuits are used to reduce signal noise and prevent signal reflections on the circuit.
  • ODT On Die Termination
  • the embodiments of the present application provide an on-chip terminal circuit and a memory device, which can keep the resistance of the on-chip terminal circuit stable, so as to improve the signal integrity of the memory device.
  • the embodiment of the present application provides an on-chip terminal circuit, including: a signal input terminal; a ground terminal; a first transistor, including a control terminal, a first terminal, and a second terminal.
  • the control terminal, the first terminal, and the The signal input terminal is electrically connected, and the second terminal is electrically connected to the ground terminal;
  • the second transistor includes a control terminal, a first terminal, and a second terminal.
  • the first terminal is electrically connected to the signal input terminal, so
  • the second terminal is electrically connected to the ground terminal, and when the voltage of the signal input terminal changes, the change trend of the resistance of the first transistor is opposite to the change trend of the resistance of the second transistor.
  • the first transistor works in the saturation region, and the resistance of the first transistor changes at least one of the following: decreases as the voltage at the signal input terminal increases, and decreases as the signal input The terminal voltage decreases and increases.
  • the second transistor works in the linear region, and the resistance of the second transistor changes at least one of the following: increases with the increase of the voltage at the signal input terminal, and increases with the increase of the signal input terminal voltage. The voltage decreases and decreases.
  • control terminal of the second transistor is electrically connected to the power supply voltage.
  • control terminal of the second transistor is electrically connected to the power supply voltage through a transmission gate.
  • the on-chip terminal circuit further includes: an inverter having an input end and an output end, the input end is electrically connected to the signal input end; a third transistor has a control end, a first end, and The second terminal is electrically connected to the output terminal of the inverter, the first terminal is electrically connected to the control terminal of the second transistor, and the second terminal is electrically connected to the ground terminal. connect.
  • the second terminal of the first transistor and the second terminal of the second transistor are electrically connected to the ground terminal through an enabling unit, and the enabling unit is turned on or off according to a control signal. Open to control the connection and disconnection of the second terminal and the ground terminal.
  • the enabling unit is an N-Metal-Oxide-Semiconductor (NMOS) transistor.
  • NMOS N-Metal-Oxide-Semiconductor
  • An embodiment of the application provides a memory device, including an on-chip terminal circuit
  • the on-chip terminal circuit includes: a signal input terminal; a ground terminal; a first transistor, including a control terminal, a first terminal and a second terminal, the control terminal and The first terminal is electrically connected to the signal input terminal, the second terminal is electrically connected to the ground terminal; the second transistor includes a control terminal, a first terminal, and a second terminal, and the first terminal is electrically connected to the ground terminal.
  • the signal input terminal is electrically connected, and the second terminal is electrically connected to the ground terminal.
  • the first transistor works in the saturation region, and the resistance of the first transistor changes at least one of the following: decreases as the voltage at the signal input terminal increases, and decreases as the signal input The terminal voltage decreases and increases.
  • the second transistor works in the linear region, and the resistance of the second transistor changes at least one of the following: increases with the increase of the voltage at the signal input terminal, and increases with the increase of the signal input terminal voltage. The voltage decreases and decreases.
  • control terminal of the second transistor is electrically connected to the power supply voltage.
  • control terminal of the second transistor is electrically connected to the power supply voltage through a transmission gate.
  • the on-chip terminal circuit further includes: an inverter having an input end and an output end, the input end is electrically connected to the signal input end; a third transistor has a control end, a first end, and The second terminal is electrically connected to the output terminal of the inverter, the first terminal is electrically connected to the control terminal of the second transistor, and the second terminal is electrically connected to the ground terminal. connect.
  • the second terminal of the first transistor and the second terminal of the second transistor are electrically connected to the ground terminal through an enabling unit, and the enabling unit is turned on or off according to a control signal. Open to control the connection and disconnection of the second terminal and the ground terminal.
  • the enabling unit is an NMOS transistor.
  • the changing trend of the resistance of the first transistor is opposite to the changing trend of the resistance of the second transistor, regardless of the voltage at the signal input terminal.
  • the resistance changes of the first transistor and the second transistor are complementary, so that the resistance of the on-chip terminal circuit can always be within a preset value range, and the resistance of the on-chip terminal circuit is stable High performance, thereby improving the signal integrity of the memory device.
  • FIG. 1 is a schematic diagram of the composition structure of an on-chip terminal circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the composition structure of an on-chip terminal circuit provided by an embodiment of the present application.
  • the on-chip terminal resistance value at the interface is required to fluctuate within a small range.
  • the resistance of the on-chip termination circuit when the data (DQ) pad voltage is required to be between 10% and 50% of the power supply voltage (VDDQ), the resistance of the on-chip termination circuit must be located in a specific area, that is, when the DQ pad voltage is at the voltage of VDDQ When the change is between 10% and 50%, the resistance of the on-chip termination circuit needs to be maintained stable, so as to improve the signal integrity of the memory device.
  • the embodiments of the present application provide an on-chip termination circuit.
  • the DQ pad voltage changes for example, in some embodiments, the DQ pad voltage changes between 10% and 50% of VDDQ
  • the on-chip termination circuit The resistance remains stable, thereby improving the signal integrity of the memory device.
  • FIG. 1 is a schematic diagram of the composition structure of an on-chip terminal circuit provided by an embodiment of the present application.
  • the on-chip terminal circuit provided by the embodiment of the present application includes a signal input terminal 10, a ground terminal 11, a first transistor M1 and a second transistor M2.
  • the signal input terminal 10 is used to receive an input signal, such as a voltage signal on a DQ pad.
  • the first transistor M1 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal and the first terminal are electrically connected to the signal input terminal 10, and the second terminal is electrically connected to the ground terminal 11. connect.
  • the first transistor M1 is an NMOS transistor, the first terminal is the drain terminal, and the second terminal is the source terminal.
  • the first transistor M1 may also be a PMOS (N-Metal-Oxide-Semiconductor) transistor, the first terminal of which is a drain terminal and the second terminal is a source terminal.
  • the second transistor M2 includes a control terminal, a first terminal, and a second terminal.
  • the first terminal is electrically connected to the signal input terminal 10, and the second terminal is electrically connected to the ground terminal 11.
  • the second transistor M2 is an NMOS transistor, the first terminal of which is a drain terminal, and the second terminal is a source terminal.
  • the second transistor M2 may also be a PMOS transistor, the first terminal of which is a drain terminal, and the second terminal is a source terminal.
  • the transistor type of the first transistor M1 and the second transistor M2 are the same, for example, both are NMOS transistors, or both are PMOS transistors.
  • the change trend of the resistance of the first transistor M1 is opposite to the change trend of the resistance of the second transistor M2.
  • the resistance of the second transistor M2 shows an increasing trend; And/or if the resistance of the first transistor M1 shows an increasing trend, the resistance of the second transistor M2 shows a decreasing trend.
  • the control terminal and the first terminal of the first transistor M1 are electrically connected to the signal input terminal 10, that is, the control terminal of the first transistor M1 is short-circuited with the first terminal, then the The first transistor M1 works in the saturation region.
  • the change trend of the resistance of the first transistor M1 is opposite to the change trend of the voltage of the signal input terminal 10. That is, the resistance of the first transistor M1 decreases as the voltage of the signal input terminal 10 increases, or the resistance of the first transistor M1 increases as the voltage of the signal input terminal 10 decreases.
  • the second transistor M2 operates in a linear region.
  • the changing trend of the resistance of the second transistor M2 is the same as the changing trend of the voltage of the signal input terminal 10. That is, the resistance of the second transistor M2 increases as the voltage of the signal input terminal 10 increases, and/or the resistance of the second transistor M2 decreases as the voltage of the signal input terminal 10 decreases.
  • control terminal of the second transistor M2 is electrically connected to a power supply voltage VDDQ, and the power supply voltage VDDQ drives the second transistor M2 to turn on. Since the power supply voltage VDDQ is basically maintained stable, the change trend of the resistance of the second transistor M2 is only related to the change trend of the voltage of the signal input terminal 10.
  • control terminal of the second transistor M2 is electrically connected to the power supply voltage VDDQ through a transmission gate TG.
  • the on-off of the transmission gate TG controls whether the control terminal of the second transistor M2 is electrically connected to the power supply voltage VDDQ, and improves the stability of the electrical connection.
  • control terminal of the second transistor M2 may also be electrically connected to the power supply voltage VDDQ through other switching units, such as an NMOS transistor or a PMOS transistor.
  • switching units such as an NMOS transistor or a PMOS transistor.
  • the change trend of the resistance of the first transistor M1 is opposite to the change trend of the voltage of the signal input terminal 10 and the change trend of the resistance of the second transistor M2 is the same as that of the signal input terminal 10.
  • the change trend of the voltage is the same, and it can be understood that in some embodiments of the present application, the change trend of the resistance of the first transistor M1 may be the same as the change trend of the voltage of the signal input terminal 10.
  • the change trend of the resistance of the second transistor M2 is opposite to the change trend of the voltage of the signal input terminal 10, so as to satisfy the change of the resistance of the first transistor M1 as the voltage of the signal input terminal 10 changes.
  • the trend is opposite to the requirement of the change trend of the resistance of the second transistor M2.
  • the second terminal of the first transistor M1 and the second terminal of the second transistor M2 are not directly electrically connected to the ground terminal 11, but are connected to the ground terminal 11 through the enabling unit M4. Terminal 11 is electrically connected.
  • the enabling unit M4 is turned on or off according to a control signal to control the turning on and off of the second terminal of the first transistor M1 and the second terminal of the second transistor M2 and the ground terminal 11.
  • the enabling unit M4 is an NMOS transistor, the control terminal of the NMOS transistor is electrically connected to the control module, and the drain terminal of the NMOS transistor is connected to the second terminal and the second terminal of the first transistor M1.
  • the second terminal of the transistor M2 is electrically connected, and the source terminal of the NMOS transistor is electrically connected to the ground terminal 11.
  • the control terminal of the NMOS transistor drives the NMOS transistor to be turned on or off according to the control signal EN issued by the control module, thereby controlling the second terminal of the first transistor M1 and the second terminal of the second transistor M2 and The grounding terminal 11 is connected and disconnected.
  • the enabling unit M4 may also be a PMOS transistor, and the control terminal of the PMOS transistor drives the PMOS transistor to be turned on or off according to the control signal EN issued by the control module.
  • the second terminal of the first transistor M1 and the second terminal of the second transistor M2 are further controlled to be turned on and off with the ground terminal 11.
  • the change trend of the resistance of the first transistor M1 is opposite to the change trend of the resistance of the second transistor M2, regardless of the signal
  • the voltage at the input terminal 10 becomes larger or smaller, and the resistance changes of the first transistor M1 and the second transistor M2 are complementary, so that the resistance changes of the first transistor M1 and the second transistor M2 can be approximated Cancellation, the resistance of the on-chip terminal circuit is always maintained within a preset value range, and the resistance of the on-chip terminal circuit has high stability, thereby improving the signal integrity of the memory device.
  • the inventor found that the resistance of the on-chip terminal circuit may not fall within the preset value range in some cases.
  • the reason for this situation is that as the voltage of the signal input terminal 10 changes, the resistance change amplitude of the second transistor M2 is greater than the resistance change amplitude of the first transistor M1, which makes The change in the resistance of the first transistor M1 cannot offset the change in the resistance of the second transistor M2, so that the resistance of the on-chip terminal circuit increases or decreases, which is not maintained within the preset value range.
  • FIG. 2 is a schematic diagram of the composition structure of an on-chip terminal circuit provided by an embodiment of the present application.
  • the control terminal of the second transistor M2 is not only connected to the power supply voltage VDDQ, but also connected to the signal output terminal 10 through the inverter 12 and the third transistor M3.
  • the signal output terminal 10 and the power supply voltage VDDQ jointly control the control terminal of the second transistor M2.
  • the on-chip terminal circuit includes an inverter 12 and a third transistor M3.
  • the inverter 12 has an input terminal and an output terminal. The input terminal is electrically connected to the signal input terminal 10, and the output terminal is electrically connected to the control terminal of the third transistor M3.
  • the third transistor M3 has a control terminal, a first terminal and a second terminal.
  • the control terminal is electrically connected to the output terminal of the inverter 12, the first terminal is electrically connected to the control terminal of the second transistor M2, and the second terminal is electrically connected to the ground terminal 11 .
  • the change trend of the voltage of the signal input terminal 10 is transmitted to the control terminal of the second transistor M2 through the inverter 12 and the third transistor M3. Therefore, the voltage of the control terminal of the second transistor M2 is With the change of the voltage of the signal input terminal 10, the same change trend is presented.
  • the changing trend of the resistance of the second transistor M2 is opposite to the changing trend of the voltage at the control terminal of the second transistor M2, and is the same as the changing trend of the voltage at the signal input terminal 10, so it can slow down
  • the change trend of the resistance of the second transistor M2 reduces the change amplitude of the resistance of the second transistor M2, so that the resistance change of the second transistor M2 and the resistance change of the first transistor M1 tend to be equal to each other.
  • the change in the resistance of the first transistor M1 can approximately offset the change in the resistance of the second transistor M2, so that the resistance of the on-chip terminal circuit is maintained within a preset value range.
  • the change trend of the voltage of the signal input terminal 10 is decreasing, the voltage of the signal input terminal 10 is transferred to the second transistor through the inverter 12 and the third transistor M3.
  • the changing trend of the voltage at the control terminal of the second transistor M2 is decreasing, and the changing trend of the resistance of the second transistor M2 is increasing. Since the signal transmission terminal 10 is electrically connected to the first terminal of the second transistor M2, the voltage at the first terminal of the second transistor M2 and the voltage at the signal input terminal 10 have the same changing trend, that is, The changing trend of the voltage at the first terminal of the second transistor M2 is also decreasing.
  • the change trend of the resistance of the second transistor M2 is the same as the change trend of the voltage of the signal input terminal 10.
  • the magnitude of change is reduced, so that the resistance change of the second transistor M2 and the resistance change of the first transistor M1 tend to be equal to each other.
  • the change in the resistance of the first transistor M1 can approximately offset the change in the resistance of the second transistor M2, so that the resistance of the on-chip terminal circuit is maintained within a preset value range.
  • the change trend of the voltage of the signal input terminal 10 is increasing, the voltage of the signal input terminal 10 is transferred to the second transistor through the inverter 12 and the third transistor M3.
  • the changing trend of the voltage at the control terminal of the second transistor M2 is increasing, and the changing trend of the resistance of the second transistor M2 is decreasing. Since the signal transmission terminal 10 is electrically connected to the first terminal of the second transistor M2, the voltage at the first terminal of the second transistor M2 and the voltage at the signal input terminal 10 have the same changing trend, that is, The changing trend of the voltage at the first terminal of the second transistor M2 is also increasing.
  • the voltage change trend of the control terminal of the second transistor M2 and the first terminal work together, so that the change trend of the resistance of the second transistor M2 is the same as the change trend of the voltage of the signal input terminal 10.
  • the amplitude is reduced.
  • the resistance change of the second transistor M2 and the resistance change amplitude of the first transistor M1 tend to be equal, so that all The change in the resistance of the first transistor M1 can approximately offset the change in the resistance of the second transistor M2, so that the resistance of the on-chip terminal circuit is maintained within a preset value range.
  • the third transistor M3 is an NMOS transistor, and in other embodiments of the present application, the third transistor M3 may also be a PMOS transistor. It can be understood that, in some embodiments of the present application, the third transistor M3 and the second transistor M2 are transistors of the same type, for example, both are NMOS transistors, or both are PMOS transistors.
  • the embodiment of the present application also provides a memory device.
  • the memory device includes the on-chip terminal circuit described in any of the foregoing embodiments.
  • the resistance of the on-chip terminal circuit is maintained within a preset value range as the voltage of the signal input terminal changes, and the resistance of the on-chip terminal circuit is highly stable, so that the memory device provided by the embodiment of the present application has high signal integrity , which greatly improves the storage performance of the memory device.
  • the embodiments of the present application provide an on-chip terminal circuit and a memory device, wherein the on-chip terminal circuit includes: a signal input terminal; a ground terminal; a first transistor including a control terminal, a first terminal, and a second terminal. The control terminal And the first end is electrically connected to the signal input end, the second end is electrically connected to the ground end; the second transistor includes a control end, a first end and a second end, the first end is The signal input terminal is electrically connected, and the second terminal is electrically connected to the ground terminal.
  • the change trend of the resistance of the first transistor is the same as that of the second transistor.
  • the change trend of the resistance is opposite.
  • the on-chip terminal circuit provided in the embodiments of the present application is applied to a memory device.
  • the resistance of the on-chip terminal circuit always maintains a value Within the range, the resistance stability of the on-chip terminal circuit is high, which can improve the signal integrity of the memory device, and thus can improve the storage performance of the memory device.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

一种片上终端电路及存储器设备，其中该片上终端电路包括：信号输入端（10）；接地端（11）；第一晶体管（M1），包括控制端、第一端及第二端，所述控制端及所述第一端与所述信号输入端（10）电连接，所述第二端与所述接地端（11）电连接；第二晶体管（M2），包括控制端、第一端及第二端，所述第一端与所述信号输入端（10）电连接，所述第二端与所述接地端（11）电连接，在所述信号输入端（10）的电压发生变化的情况下，所述第一晶体管（M1）的电阻的变化趋势与所述第二晶体管（M2）的电阻的变化趋势相反。在所述信号输入端（10）的电压发生变化的情况下，所述片上终端电路的电阻始终维持在一数值范围内，所述片上终端电路的电阻稳定性高，进而提高存储器设备的信号完整性。

Description

片上终端电路及存储器设备
相关申请的交叉引用
本申请基于申请号为202010493235.4、申请日为2020年06月03日、申请名称为“片上终端电路及存储器设备”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及存储器领域，尤其涉及一种片上终端电路及存储器设备。
背景技术
存储器设备由于其容量和操作速度的增大而使信号完整性劣化。例如，随着存储器设备的操作速度的增大，存储器控制器连接到存储器设备的通道所传输数据的带宽可能增大，这会降低信号质量。因此，使用片上终端(ODT，On Die Termination)电路来降低信号噪声，防止信号在电路上形成反射。
对于存储器来说，信号完整性至关重要。因此，随着存储器运行速度的提升，对片上终端电路的要求变得非常严格。例如，根据第四代低功耗双重数据比率(LPDDR4，Low Power Double Data Rate 4)规范，当焊盘电压在电源电压VDDQ的10％到50％之间时，片上终端电路的电阻必须位于特定区域内。
然而，现有的片上终端电路的电阻不稳定，不能满足需求。
发明内容
本申请实施例提供一种片上终端电路及存储器设备，能够使片上终端电路的电阻维持稳定，以提高存储器设备信号完整性。
本申请实施例的技术方案是这样实现的：
本申请实施例提供了一种片上终端电路，包括：信号输入端；接地端；第一晶体管，包括控制端、第一端及第二端，所述控制端及所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接；第二晶体管，包括控制端、第一端及第二端，所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接，在所述信号输入端的电压发生变化的情况下，所述第一晶体管的电阻的变化趋势与所述第二晶体管的电阻的变化趋势相反。
在一些实施例中，所述第一晶体管工作在饱和区，所述第一晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而减小，随所述信号输入端的电压的减小而增加。
在一些实施例中，所述第二晶体管工作在线性区，所述第二晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而增加，随所述信号输入端的电压的减小而减小。
在一些实施例中，所述第二晶体管的控制端与电源电压电连接。
在一些实施例中，所述第二晶体管的控制端通过传输门与所述电源电压电连接。
在一些实施例中，所述片上终端电路还包括：反相器，具有输入端及输出端，所述输入端与所述信号输入端电连接；第三晶体管，具有控制端、第一端及第二端，所述控制端与所述反相器的所述输出端电连接，所述第一端与所述第二晶体管的控制端电连接，所述第二端与所述接地端电连接。
在一些实施例中，所述第一晶体管的第二端及所述第二晶体管的第二端通过使能单元与所述接地端电连接，所述使能单元根据控制信号而接通或断开，以控制所述第二端与所述接地端的接通及断开。
在一些实施例中，所述使能单元为N型金属氧化物半导体(NMOS，N-Metal-Oxide-Semiconductor)晶体管。
本申请实施例提供一种存储器设备，包括片上终端电路，所述片上终端电路包括：信号输入端；接地端；第一晶体管，包括控制端、第一端及第二端，所述控制端及所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接；第二晶体管，包括控制端、第一端及第二端，所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接，在所述信号输入端的电压发生变化的情况下，所述第一晶体管的电阻的变化趋势与所述第二晶体管的电阻的变化趋势相反。
在一些实施例中，所述第一晶体管工作在饱和区，所述第一晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而减小，随所述信号输入端的电压的减小而增加。
在一些实施例中，所述第二晶体管工作在线性区，所述第二晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而增加，随所述信号输入端的电压的减小而减小。
在一些实施例中，所述第二晶体管的控制端与电源电压电连接。
在一些实施例中，所述第二晶体管的控制端通过传输门与所述电源电压电连接。
在一些实施例中，所述片上终端电路还包括：反相器，具有输入端及输出端，所述输入端与所述信号输入端电连接；第三晶体管，具有控制端、第一端及第二端，所述控制端与所述反相器的所述输出端电连接，所述第一端与所述第二晶体管的控制端电连接，所述第二端与所述接地端电连接。
在一些实施例中，所述第一晶体管的第二端及所述第二晶体管的第二端通过使能单元与所述接地端电连接，所述使能单元根据控制信号而接通或断开，以控制所述第二端与所述接地端的接通及断开。
在一些实施例中，所述使能单元为NMOS晶体管。
本申请实施例中，在所述信号输入端的电压发生变化的情况下，所述第一晶体管的电阻的变化趋势与所述第二晶体管的电阻的变化趋势相反，则不论所述信号输入端的电压变大或者变小，所述第一晶体管与所述第二晶体管的电阻变化均互补，从而能够使所述片上终端电路的电阻始终在一预设数值范围内，所述片上终端电路的电阻稳定性高，进而提高存储器设备的信号完整性。
附图说明
图1是本申请实施例提供的一种片上终端电路的组成结构示意图；
图2是本申请实施例提供的一种片上终端电路的组成结构示意图。
具体实施方式
下面结合附图对本申请提供的片上终端电路及存储器设备的具体实施例做详细说明。
通常对于高速芯片来说，为了保证信号传输完整性，会要求接口处片上终端电阻值在一较小范围内波动。例如，根据LPDDR4规范，要求数据(DQ)焊盘电压在电源电压(VDDQ)的10％到50％之间时，片上终端电路的电阻必须位于特定区域内，即当DQ焊盘电压在VDDQ的10％到50％之间变化时，片上终端电路的电阻需要维持稳定，从而能够提高存储器设备的信号完整性。对于如双重数据比率(DDR5，Double Data Rate 5)、第五代低功耗双重数据比率(LPDDR5，Low Power Double Data Rate 5)等速度更快或带宽更大的芯片来说，可能对片上终端电路的要求更高。然而对于相关技术中的片上终端电路，片上终端电路的电阻受外界因素影响较大(如受焊盘电压的影响)，稳定性不够，不能满足需求。
因此，本申请实施例提供一种片上终端电路，当DQ焊盘电压变化时(例如在一些实施例中，DQ焊盘电压在VDDQ的10％到50％之间变化时)，片上终端电路的电阻维持稳定，从而提高存储器设备的信号完整性。
图1是本申请实施例提供的一种片上终端电路的组成结构示意图。请参阅图1，本申请实施例提供的片上终端电路包括信号输入端10、接地端11、第一晶体管M1及第二晶体管M2。
所述信号输入端10用于接收输入信号，例如DQ焊盘上的电压信号。
所述第一晶体管M1包括控制端、第一端及第二端，所述控制端及所述第一端与所述信号输入端10电连接，所述第二端与所述接地端11电连接。在一些实施例中，所述第一晶体管M1为NMOS晶体管，其第一端为漏极端，第二端为源极端。在一些实施例中，所述第一晶体管M1也可为P型金属氧化物半导体(PMOS，N-Metal-Oxide-Semiconductor)晶体管，其第一端为漏极端，第二端为源极端。
所述第二晶体管M2包括控制端、第一端及第二端，所述第一端与所述信号输入端10电连接，所述第二端与所述接地端11电连接。在一些实施例中，所述第二晶体管M2为NMOS晶体管，其第一端为漏极端，第二端为源极端。在一些实施例中，所述第二晶体管M2也可为PMOS晶体管，其第一端为漏极端，第二端为源极端。
可以理解的是，在本申请的一些实施例中，所述第一晶体管M1与所述第二晶体管M2的晶体管类型相同，例如，两者均为NMOS晶体管，或者两者均为PMOS晶体管。
其中，随着所述信号输入端10的电压的变化，所述第一晶体管M1的电阻的变化趋势与所述第二晶体管M2的电阻的变化趋势相反。在一些实施例中，在所述信号输入端10的电压的相同的变化趋势下，若所述第一晶体管M1的电阻呈减小趋势，则所述第二晶体管M2的电阻呈增大趋势；和/或若所述第一晶体管M1的电阻呈增大趋势，则 所述第二晶体管M2的电阻呈减小趋势。
在一些实施例中，所述第一晶体管M1的控制端、第一端均与所述信号输入端10电连接，即所述第一晶体管M1的控制端与第一端短接，则所述第一晶体管M1工作在饱和区。所述第一晶体管M1的电阻的变化趋势与所述信号输入端10的电压的变化趋势相反。即所述第一晶体管M1的电阻随所述信号输入端10的电压的增加而减小，或所述第一晶体管M1的电阻随所述信号输入端10的电压的减小而增加。
在一些实施例中，所述第二晶体管M2工作在线性区。所述第二晶体管M2的电阻的变化趋势与所述信号输入端10的电压的变化趋势相同。即所述第二晶体管M2的电阻随所述信号输入端10的电压的增加而增加，和/或所述第二晶体管M2的电阻随所述信号输入端10的电压的减小而减小。
在一些实施例中，所述第二晶体管M2的控制端与电源电压VDDQ电连接，所述电源电压VDDQ驱动所述第二晶体管M2的开启。由于所述电源电压VDDQ基本维持稳定，因此，所述第二晶体管M2的电阻的变化趋势仅与所述信号输入端10的电压的变化趋势相关。
在一些实施例中，所述第二晶体管M2的控制端通过传输门TG与所述电源电压VDDQ电连接。所述传输门TG的通断控制所述第二晶体管M2的控制端与所述电源电压VDDQ是否电连接，并提高电连接的稳定性。
在本申请的一些实施例中，所述第二晶体管M2的控制端也可通过其他开关单元，例如NMOS晶体管或者PMOS晶体管，与所述电源电压VDDQ电连接。所述开关单元导通，则所述第二晶体管M2的控制端与所述电源电压VDDQ电连接，所述开关单元断开，则所述第二晶体管M2的控制端与所述电源电压VDDQ断开连接。
在一些实施例中，所述第一晶体管M1的电阻的变化趋势与所述信号输入端10的电压的变化趋势相反，所述第二晶体管M2的电阻的变化趋势与所述信号输入端10的电压的变化趋势相同，而可以理解的是，在本申请的一些实施例中，也可以为，所述第一晶体管M1的电阻的变化趋势与所述信号输入端10的电压的变化趋势相同，所述第二晶体管M2的电阻的变化趋势与所述信号输入端10的电压的变化趋势相反，以满足随着所述信号输入端10的电压的变化，所述第一晶体管M1的电阻的变化趋势与所述第二晶体管M2的电阻的变化趋势相反的要求。
在一些实施例中，所述第一晶体管M1的第二端及所述第二晶体管M2的第二端并非是直接与所述接地端11电连接，而是通过使能单元M4与所述接地端11电连接。所述使能单元M4根据控制信号而接通或断开，以控制所述第一晶体管M1的第二端及第二晶体管M2的第二端与所述接地端11的接通及断开。
在一些实施例中，所述使能单元M4为NMOS晶体管，所述NMOS晶体管的控制端与控制模块电连接，所述NMOS晶体管的漏极端与所述第一晶体管M1的第二端及第二晶体管M2的第二端电连接，所述NMOS晶体管的源极端与所述接地端11电连接。所述NMOS晶体管的控制端根据控制模块发出的控制信号EN而驱动所述NMOS晶体管的接通或断开，进而控制所述第一晶体管M1的第二端及第二晶体管M2的第二端与所述接地端11的接通及断开。在本申请的另一些实施例中，所述使能单元M4也可为 PMOS晶体管，所述PMOS晶体管的控制端根据控制模块发出的控制信号EN而驱动所述PMOS晶体管的接通或断开，进而控制所述第一晶体管M1的第二端及第二晶体管M2的第二端与所述接地端11的接通及断开。
在本申请实施例中，随着所述信号输入端10的电压的变化，所述第一晶体管M1的电阻的变化趋势与所述第二晶体管M2的电阻的变化趋势相反，则不论所述信号输入端10的电压变大或者变小，所述第一晶体管M1与所述第二晶体管M2的电阻变化均互补，从而能够使所述第一晶体管M1与所述第二晶体管M2的电阻变化近似抵消，所述片上终端电路的电阻始终维持在一预设数值范围内，所述片上终端电路的电阻稳定性高，进而提高存储器设备的信号完整性。
在实施本申请实施例时，发明人发现，所述片上终端电路的电阻在一些情况下会出现不在预设数值范围内的情况。经研究，发明人发现，出现该种状况的原因在于，随着所述信号输入端10的电压的变化，所述第二晶体管M2的电阻变化幅度大于第一晶体管M1的电阻变化幅度，这使得第一晶体管M1的电阻的变化不能抵消第二晶体管M2的电阻的变化，从而使得片上终端电路的电阻增大或者减小，并未维持在预设数值范围内。
有鉴于此，本申请实施例提供一种片上终端电路，能够减缓所述第二晶体管M2的电阻的变化趋势，所述第二晶体管M2的电阻变化幅度减小，以使所述片上终端电路的电阻维持在预设数值范围内。图2是本申请实施例提供的一种片上终端电路的组成结构示意图。请参阅图2，在本申请实施例中，所述第二晶体管M2的控制端不仅与电源电压VDDQ连接，还通过反相器12及第三晶体管M3与信号输出端10连接。所述信号输出端10及所述电源电压VDDQ共同控制所述第二晶体管M2的控制端。具体说明如下：
所述片上终端电路包括反相器12及第三晶体管M3。
所述反相器12具有输入端及输出端。所述输入端与所述信号输入端10电连接，所述输出端与所述第三晶体管M3的控制端电连接。
所述第三晶体管M3具有控制端、第一端及第二端。所述控制端与所述反相器12的所述输出端电连接，所述第一端与所述第二晶体管M2的控制端电连接，所述第二端与所述接地端11电连接。所述信号输入端10的电压的变化趋势经所述反相器12及所述第三晶体管M3而传递至所述第二晶体管M2的控制端，因此，所述第二晶体管M2的控制端的电压随所述信号输入端10的电压的变化而呈相同的变化趋势。
在本申请实施例中，所述第二晶体管M2的电阻的变化趋势与所述第二晶体管M2的控制端的电压的变化趋势相反，与信号输入端10的电压的变化趋势相同，因此，能够减缓所述第二晶体管M2的电阻的变化趋势，减小所述第二晶体管M2的电阻的变化幅度，使所述第二晶体管M2的电阻变化与第一晶体管M1的电阻变化幅度趋于相等，以使所述第一晶体管M1的电阻的变化能够近似抵消所述第二晶体管M2的电阻的变化，从而使得片上终端电路的电阻维持在预设数值范围内。
举例说明，若所述信号输入端10的电压的变化趋势为减小，则所述信号输入端10的电压经所述反相器12及所述第三晶体管M3而传递至所述第二晶体管M2的控制端后，所述第二晶体管M2的控制端的电压的变化趋势为减小，所述第二晶体管M2的电 阻的变化趋势为增大。而由于所述信号传输端10与所述第二晶体管M2的第一端电连接，所述第二晶体管M2的第一端的电压与所述信号输入端10的电压的变化趋势相同，即所述第二晶体管M2的第一端的电压的变化趋势也为减小。在所述第二晶体管M2的控制端与第一端的电压变化趋势的协同作用下，所述第二晶体管M2的电阻的变化趋势既与所述信号输入端10的电压的变化趋势相同，其变化幅度又相较于第二晶体管M2的控制端仅与电源电压VDDQ连接的情况下有减小，这样所述第二晶体管M2的电阻变化与第一晶体管M1的电阻变化幅度趋于相等，以使所述第一晶体管M1的电阻的变化能够近似抵消所述第二晶体管M2的电阻的变化，从而使得片上终端电路的电阻维持在预设数值范围内。
举例说明，若所述信号输入端10的电压的变化趋势为增大，则所述信号输入端10的电压经所述反相器12及所述第三晶体管M3而传递至所述第二晶体管M2的控制端后，所述第二晶体管M2的控制端的电压的变化趋势为增大，所述第二晶体管M2的电阻的变化趋势为减小。而由于所述信号传输端10与所述第二晶体管M2的第一端电连接，所述第二晶体管M2的第一端的电压与所述信号输入端10的电压的变化趋势相同，即所述第二晶体管M2的第一端的电压的变化趋势也为增大。则所述第二晶体管M2的控制端与第一端的电压变化趋势协同作用，使得所述第二晶体管M2的电阻的变化趋势既与所述信号输入端10的电压的变化趋势相同，其变化幅度又相较于第二晶体管M2的控制端仅与电源电压VDDQ连接的情况下有减小，所述第二晶体管M2的电阻变化与第一晶体管M1的电阻变化幅度趋于相等，以使所述第一晶体管M1的电阻的变化能够近似抵消所述第二晶体管M2的电阻的变化，从而使得片上终端电路的电阻维持在预设数值范围内。
在一些实施例中，所述第三晶体管M3为NMOS管，而在本申请的另一些实施例中，所述第三晶体管M3也可为PMOS管。可以理解的是，在本申请的一些实施例中，所述第三晶体管M3与所述第二晶体管M2为同种类型晶体管，例如，两者均为NMOS晶体管，或者两者均为PMOS晶体管。
上述仅为本申请实施例列举的一种减缓所述第二晶体管M2的电阻的变化趋势的示例性实施例。可以理解的是，能够实现该效果的其他方法也可行，本申请实施例对此并不进行限定。
本申请实施例还提供一种存储器设备。所述存储器设备包括上述任一实施例所述的片上终端电路。所述片上终端电路的电阻随信号输入端的电压的变化而维持在预设数值范围内，所述片上终端电路的电阻稳定性高，使得本申请实施例提供的存储器设备具有较高的信号完整性，大大提高了所述存储器设备的存储性能。
以上所述仅是本申请的示例性实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。
工业实用性
本申请实施例提供了一种片上终端电路及存储器设备，其中，该片上终端电路包括：信号输入端；接地端；第一晶体管，包括控制端、第一端及第二端，所述控制端及所述 第一端与所述信号输入端电连接，所述第二端与所述接地端电连接；第二晶体管，包括控制端、第一端及第二端，所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接，在所述信号输入端的电压发生变化的情况下，所述第一晶体管的电阻的变化趋势与所述第二晶体管的电阻的变化趋势相反。本申请实施例提供的片上终端电路应用于存储器设备中，对该存储器设备进行操作的过程中，在所述信号输入端的电压发生变化的情况下，所述片上终端电路的电阻始终维持在一数值范围内，所述片上终端电路的电阻稳定性高，能够提高存储器设备的信号完整性，进而能够提高所述存储器设备的存储性能。

Claims (16)

  1. 一种片上终端电路，包括：
    信号输入端；
    接地端；
    第一晶体管，包括控制端、第一端及第二端，所述控制端及所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接；
    第二晶体管，包括控制端、第一端及第二端，所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接，在所述信号输入端的电压发生变化的情况下，所述第一晶体管的电阻的变化趋势与所述第二晶体管的电阻的变化趋势相反。
  2. 根据权利要求1所述的片上终端电路，其中，所述第一晶体管工作在饱和区，所述第一晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而减小，随所述信号输入端的电压的减小而增加。
  3. 根据权利要求1所述的片上终端电路，其中，所述第二晶体管工作在线性区，所述第二晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而增加，随所述信号输入端的电压的减小而减小。
  4. 根据权利要求3所述的片上终端电路，其中，所述第二晶体管的控制端与电源电压电连接。
  5. 根据权利要求4所述的片上终端电路，其中，所述第二晶体管的控制端通过传输门与所述电源电压电连接。
  6. 根据权利要求4所述的片上终端电路，其中，所述片上终端电路还包括：
    反相器，具有输入端及输出端，所述输入端与所述信号输入端电连接；
    第三晶体管，具有控制端、第一端及第二端，所述控制端与所述反相器的所述输出端电连接，所述第一端与所述第二晶体管的控制端电连接，所述第二端与所述接地端电连接。
  7. 根据权利要求1所述的片上终端电路，其中，所述第一晶体管的第二端及所述第二晶体管的第二端通过使能单元与所述接地端电连接，所述使能单元根据控制信号而接通或断开，以控制所述第二端与所述接地端的接通及断开。
  8. 根据权利要求7所述的片上终端电路，其中，所述使能单元为NMOS晶体管。
  9. 一种存储器设备，包括片上终端电路，所述片上终端电路包括：
    信号输入端；
    接地端；
    第一晶体管，包括控制端、第一端及第二端，所述控制端及所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接；
    第二晶体管，包括控制端、第一端及第二端，所述第一端与所述信号输入端电连接，所述第二端与所述接地端电连接，在所述信号输入端的电压发生变化的情况下，所述第一晶体管的电阻的变化趋势与所述第二晶体管的电阻的变化趋势相反。
  10. 根据权利要求9所述的存储器设备，其中，所述第一晶体管工作在饱和区， 所述第一晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而减小，随所述信号输入端的电压的减小而增加。
  11. 根据权利要求9所述的存储器设备，其中，所述第二晶体管工作在线性区，所述第二晶体管的电阻的变化趋势为以下至少之一：随所述信号输入端的电压的增加而增加，随所述信号输入端的电压的减小而减小。
  12. 根据权利要求11所述的存储器设备，其中，所述第二晶体管的控制端与电源电压电连接。
  13. 根据权利要求12所述的存储器设备，其中，所述第二晶体管的控制端通过传输门与所述电源电压电连接。
  14. 根据权利要求12所述的存储器设备，其中，所述片上终端电路还包括：
    反相器，具有输入端及输出端，所述输入端与所述信号输入端电连接；
    第三晶体管，具有控制端、第一端及第二端，所述控制端与所述反相器的所述输出端电连接，所述第一端与所述第二晶体管的控制端电连接，所述第二端与所述接地端电连接。
  15. 根据权利要求9所述的存储器设备，其中，所述第一晶体管的第二端及所述第二晶体管的第二端通过使能单元与所述接地端电连接，所述使能单元根据控制信号而接通或断开，以控制所述第二端与所述接地端的接通及断开。
  16. 根据权利要求15所述的存储器设备，其中，所述使能单元为NMOS晶体管。
PCT/CN2021/094076 2020-06-03 2021-05-17 片上终端电路及存储器设备 WO2021244271A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/385,439 US11888474B2 (en) 2020-06-03 2021-07-26 On die termination circuit and memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010493235.4A CN113760802B (zh) 2020-06-03 2020-06-03 片上终端电路及存储器设备
CN202010493235.4 2020-06-03

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/385,439 Continuation US11888474B2 (en) 2020-06-03 2021-07-26 On die termination circuit and memory device

Publications (1)

Publication Number Publication Date
WO2021244271A1 true WO2021244271A1 (zh) 2021-12-09

Family

ID=78783038

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/094076 WO2021244271A1 (zh) 2020-06-03 2021-05-17 片上终端电路及存储器设备

Country Status (2)

Country Link
CN (1) CN113760802B (zh)
WO (1) WO2021244271A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655086A (zh) * 2005-02-25 2005-08-17 清华大学 调整负载中晶体管跨导变化范围用的偏置补偿电路
CN1996025A (zh) * 2006-09-01 2007-07-11 威盛电子股份有限公司 电源电平检测器
CN101119100A (zh) * 2006-07-31 2008-02-06 中国科学院微电子研究所 一种具有温度补偿的高增益宽带放大器电路
CN101820277A (zh) * 2009-02-27 2010-09-01 台湾积体电路制造股份有限公司 用于可编程加电序列的装置和方法
US9325318B1 (en) * 2014-11-26 2016-04-26 Taiwan Semiconductor Manufacturing Company Ltd. Post driver

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101458537B (zh) * 2007-12-11 2011-11-02 上海华虹Nec电子有限公司 电压调整器电路及电阻偏差补偿方法
KR102511901B1 (ko) * 2016-04-11 2023-03-20 에스케이하이닉스 주식회사 넓은 동작 영역을 갖는 불휘발성 메모리 소자
CN208433950U (zh) * 2018-07-10 2019-01-25 上海艾为电子技术股份有限公司 一种具有恒定导通电阻的模拟开关

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655086A (zh) * 2005-02-25 2005-08-17 清华大学 调整负载中晶体管跨导变化范围用的偏置补偿电路
CN101119100A (zh) * 2006-07-31 2008-02-06 中国科学院微电子研究所 一种具有温度补偿的高增益宽带放大器电路
CN1996025A (zh) * 2006-09-01 2007-07-11 威盛电子股份有限公司 电源电平检测器
CN101820277A (zh) * 2009-02-27 2010-09-01 台湾积体电路制造股份有限公司 用于可编程加电序列的装置和方法
US9325318B1 (en) * 2014-11-26 2016-04-26 Taiwan Semiconductor Manufacturing Company Ltd. Post driver

Also Published As

Publication number Publication date
CN113760802B (zh) 2024-05-14
CN113760802A (zh) 2021-12-07

Similar Documents

Publication Publication Date Title
US5546033A (en) Output driver circuits with enhanced supply-line bounce control and improved VOH characteristic
US5726589A (en) Off-chip driver circuit with reduced hot-electron degradation
KR100744004B1 (ko) 온 다이 터미네이션 회로를 구비하는 반도체메모리소자 및그의 구동방법
CN107710620B (zh) 输入/输出(i/o)驱动器
TWI694460B (zh) 第四代雙倍資料率記憶體的輸入輸出驅動器
KR20060038745A (ko) 온 다이 터미네이션 회로를 갖는 반도체메모리소자
US6842058B2 (en) Method and apparatus for slew control of an output signal
US9143133B2 (en) Output apparatus, output driver, and level shifting system
US6236237B1 (en) Output buffer predriver with edge compensation
US7863933B2 (en) Tri-state I/O port
KR100937996B1 (ko) 온다이 터미네이션 장치
WO2021244271A1 (zh) 片上终端电路及存储器设备
US8004314B2 (en) Semiconductor device
KR100930414B1 (ko) 데이터 출력 장치
EP0139904A2 (en) Improved tristate control circuitry for a driver circuit
US11888474B2 (en) On die termination circuit and memory device
US20180277196A1 (en) Double data rate synchronous dynamic random access memory and output driving circuit thereof
US7902882B2 (en) Apparatus including a follower output buffer having an output impedance that adapts to a transmission line impedance
US8004310B1 (en) Power supply regulation
US6236235B1 (en) Output circuit
KR940003399B1 (ko) 저잡음 데이타 출력 버퍼
KR20020018018A (ko) 출력 인터페이스 회로
US20220416792A1 (en) Integrated circuit with output driver that compensates for supply voltage variations
US20230170013A1 (en) Apparatuses including output drivers and methods for providing output data signals
US20230064147A1 (en) Buffer circuit capable of adjusting a gain, receiving circuit and semiconductor apparatus including the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21817066

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21817066

Country of ref document: EP

Kind code of ref document: A1