WO2021244231A1 - 晶圆布局的设计方法及光刻机曝光系统 - Google Patents

晶圆布局的设计方法及光刻机曝光系统 Download PDF

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WO2021244231A1
WO2021244231A1 PCT/CN2021/092903 CN2021092903W WO2021244231A1 WO 2021244231 A1 WO2021244231 A1 WO 2021244231A1 CN 2021092903 W CN2021092903 W CN 2021092903W WO 2021244231 A1 WO2021244231 A1 WO 2021244231A1
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wafer
yield
layout
die
wafer layout
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PCT/CN2021/092903
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English (en)
French (fr)
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许威
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长鑫存储技术有限公司
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Priority to EP21817512.3A priority Critical patent/EP3985715A4/en
Priority to US17/395,637 priority patent/US11657204B2/en
Publication of WO2021244231A1 publication Critical patent/WO2021244231A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for designing a wafer layout and an exposure system of a photolithography machine.
  • Semiconductor wafers such as silicon, germanium and III-V material wafers are used in the manufacture of integrated circuits.
  • Various semiconductor processes can be used on the wafers, such as photolithography (such as patterning, etching, deposition, etc.), Epitaxial growth, doping, polishing and other such processes form crystal grains.
  • photolithography such as patterning, etching, deposition, etc.
  • Epitaxial growth, doping, polishing and other such processes form crystal grains.
  • several identical dies are formed on a single wafer, ranging from tens per wafer to hundreds per wafer or even thousands of dies per wafer, depending on the size of the bare chip of the device.
  • the wafer layout can be calculated according to the size of the die, the arrangement of the die in a single shot, and the edge rinsing position of the wafer, so that the maximum number of complete dies can be obtained in the edge rinsing position of the wafer.
  • the inventor found that since in actual production, the yield rate of the die in the radial distribution of the wafer is not 100%, the qualified die on a single wafer is produced according to the wafer layout in the prior art. The number of is often smaller than the number of complete dies calculated, resulting in a low single wafer yield.
  • the purpose of some embodiments of this application is to provide a wafer layout design method and a photolithography machine exposure system.
  • the wafer layout obtained according to this wafer layout design method has a larger number of qualified dies during production. .
  • an embodiment of the present application provides a method for designing a wafer layout, including: providing a yield distribution map of the wafer under the initial wafer layout; determining the wafer according to the yield distribution map The edge position of the yield rate; the new wafer layout is calculated according to the die size and the edge position of the yield rate.
  • An embodiment of the present application also provides an exposure system for a lithography machine, including: at least one processor; and a memory and an exposure device communicatively connected to the at least one processor; wherein the memory stores the Instructions executed by at least one processor, the instructions are executed by the at least one processor, so that the at least one processor can execute the above-mentioned wafer layout design method to obtain a new wafer layout; the processor is used for The obtained new wafer layout is sent to the exposure device, and the exposure device is used for wafer exposure according to the new wafer layout.
  • the embodiment of the present application provides a method for designing a wafer layout.
  • the initial wafer layout (that is, the wafer layout in the prior art) is based on the die size and the wafer edge washing position. Certainly, but due to the difference in process control ability during the production process, the yield rate of the die near the wafer edge washing position is often low or even zero. Therefore, the wafer is processed according to the initial wafer layout in the prior art.
  • the number of qualified dies obtained is often less than the number of complete dies in the initial wafer layout; however, in this embodiment, the actual wafer yield is determined according to the yield distribution map of the wafer under the initial wafer layout Edge position, when determining the new wafer layout, consider the damage of the die near the wafer edge washing position during the production process, and determine the new wafer according to the actual yield edge position and die size Layout.
  • the number of qualified dies obtained is approximately the same as the number of complete dies in the new wafer layout, thereby improving the production quality of qualified dies on the wafer. Rate.
  • the yield of the die at the edge position of the yield rate is a preset yield value, and the preset yield value is smaller than that of the die at a position close to the center of the wafer at the edge of the yield rate.
  • the yield rate is greater than or equal to the yield rate of the crystal grain at a position far from the center of the circle at the edge of the yield rate.
  • the preset yield value is zero.
  • the edge position of the yield is a closed line surrounding the center of the circle, and the closed line is a closed curve or a closed polyline.
  • the closed curve and the edge line of the wafer are concentric circles.
  • the calculation of the new wafer layout according to the die size and the edge position of the yield includes: determining the die where the center of the wafer is located in the initial wafer layout; The die at the center of the circle is moved by a fixed step to shift the initial wafer layout.
  • the fixed step includes a horizontal fixed step and a vertical fixed step. In the transverse direction, the longitudinal fixed step is along the longitudinal direction; the number of complete dies in the edge position of the yield rate is calculated; and the die at the position of the center of the wafer is repeatedly moved until the complete The number of dies is the largest; and the wafer layout corresponding to the maximum number of the obtained complete dies is determined as the new wafer layout.
  • the crystal grain has a horizontal side and a vertical side, the horizontal side has a horizontal size, the vertical side has a vertical size, the horizontal fixed step does not exceed half of the horizontal size, and the vertical fixed step Not more than half of the longitudinal dimension.
  • center point of the die at the center of the wafer in the initial wafer layout coincides with the center of the circle; or, the center point of the die at the center of the wafer in the initial wafer layout is Any vertex coincides with the center of the circle.
  • the providing the yield distribution map of the wafer under the initial wafer layout includes: determining the initial wafer layout according to the wafer edge washing position and the die size; and comparing all the wafers according to the initial wafer layout The wafer is exposed; the exposed wafer is inspected to obtain the yield distribution map under the initial wafer layout.
  • the determining the initial wafer layout according to the wafer edge washing position and the die size includes: according to the size of the dicing lane, the layout of the die in a single shot, the die size, and the wafer The edge washing position is calculated to obtain the initial wafer layout.
  • the determining the yield edge position of the wafer according to the yield distribution map includes: determining that the distance between the center of the wafer and the qualified die farthest from the center is the first size ; Taking the center of the wafer as the origin and the first size as the radius to obtain a closed pattern, and use the position of the closed pattern as the edge position of the yield.
  • the method further includes: performing wafer exposure according to the new wafer layout.
  • the calculation of the new wafer layout according to the die size and the yield edge position includes: according to the size of the dicing lane, the layout of the die in a single shot, the die size and the yield edge The position calculation obtains the new wafer layout.
  • the method further includes:
  • FIG. 1 is a schematic flowchart of a method for designing a wafer layout according to a first embodiment of the present application
  • FIG. 2 is a schematic diagram of the initial wafer layout in the first embodiment of the present application.
  • FIG. 3 is a graph showing the gradual change of the yield of the die on a wafer with a radius of 150 mm with the radius according to the first embodiment of the present application;
  • FIG. 4 is a schematic flowchart of a method for designing a wafer layout according to a second embodiment of the present application
  • FIG. 5 is a schematic diagram of a new wafer layout according to the second embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of an exposure system of a lithography machine according to a third embodiment of the present application.
  • the first embodiment of the present application relates to a method for designing a wafer layout.
  • the core of this embodiment is to include: providing a yield distribution map of wafers under an initial wafer layout; The yield edge position of the wafer; a new wafer layout is calculated according to the die size and the yield edge position.
  • the initial wafer layout (that is, the wafer layout in the prior art) is determined according to the die size and the wafer edge washing position, but due to the difference in process control capabilities during the production process, it will often lead to near the wafer edge washing position The die yield is low or even zero.
  • the number of qualified dies obtained is often less than the number of complete dies in the initial wafer layout;
  • the actual yield edge position of the wafer is determined according to the yield distribution map of the wafer under the initial wafer layout.
  • the new wafer layout is determined according to the actual yield edge position and die size. After the wafer is exposed according to the new wafer layout, the number of qualified dies obtained is compared with the The number of complete dies in the new wafer layout is roughly the same, thereby improving the production yield of qualified dies on the wafer.
  • FIG. 1 The schematic flow diagram of the wafer layout design method in this embodiment is shown in FIG. 1, which will be described in detail below with reference to FIG. 2 and FIG. 3.
  • Step 101 Provide a yield distribution map 401 of wafers under the initial wafer layout 51.
  • the yield distribution map 401 of the wafer under the initial wafer layout 51 is provided, including: determining the initial wafer layout 51 according to the wafer edge washing position 2 and the die size; Exposure; the exposed wafer is inspected to obtain a yield distribution map 401 under the initial wafer layout 51.
  • photoresist needs to be spin-coated on the surface of the wafer.
  • the excess glue will be pushed to the edge of the wafer by centrifugal force. Some are thrown off the wafer, and some remain on the edge 1 of the wafer. Because the relative velocity of the airflow at the edge 1 of the wafer is very high, the remaining glue will quickly solidify to form a raised edge. Therefore, after the photoresist is spin-coated, the edge 1 of the wafer is soft baked, and the photoresist at the edge 1 of the wafer is removed by chemical or optical methods. This is called photoresist edge repair, or photolithography. Glue the edges.
  • the wafer edge washing position 2 is the position obtained after the photoresist edge repair is performed on the wafer. Specifically, EBR (Edge Bevel Remove) or WEE (Wafer Edge Exposure) methods can be used for photoresist edge removal.
  • the wafer edge washing position 2 is shown by a dashed line. It is located on the side of the wafer edge 1 close to the center O of the wafer. Since the wafer edge washing position 2 is on the side far from the center O In actual production, a complete die cannot be obtained. Therefore, when determining the initial wafer layout 51, the initial wafer layout 51 is determined according to the wafer edge washing position 2 and the die size, and the wafers are processed according to the initial wafer layout 51 Exposure and inspection of the exposed wafer can obtain a yield distribution map 401 of the wafer under the initial wafer layout 51, where the yield distribution map 401 is a position distribution map of the qualified die 41 on the wafer.
  • the size of the dicing lane and the layout of the die in a single shot are also obtained, so that according to the size of the dicing lane, the die in a single shot
  • the initial wafer layout 51 is calculated by calculating the die layout, die size, and wafer edge washing position 2.
  • the size of the scribe lane is the distance between two adjacent dies on the wafer
  • shot is the area shot by one exposure when the wafer is exposed.
  • the single exposure area of the photomask corresponds to In the area on the wafer
  • the layout of the die in a single shot is the arrangement of the die exposed by the photomask during exposure. That is to say, when determining the initial wafer layout 51, it is jointly determined according to the size of the scribe lane, the layout of the die in a single shot, the die size, and the wafer edge washing position 2.
  • Step 102 Determine the yield edge position 3 of the wafer according to the yield distribution map 401.
  • the yield distribution map 401 is detected to determine the yield edge position 3 of the wafer.
  • the distribution of the qualified die 41 and the unqualified die 42 on the wafer can be seen.
  • the specific change trends are shown in Table 1 below:
  • the complete die in this embodiment is the complete die calculated in the initial wafer layout 51; and the qualified die 41 is the conformity obtained after the wafer is exposed according to the initial wafer layout 51. Use the required grains. In actual production, the complete dies on the wafer close to the edge 1 of the wafer may be damaged and do not meet the usage requirements. Therefore, the number of qualified dies 41 and the number of complete dies are generally different.
  • the yield edge position 3 is defined, the die yield at the yield edge position 3 is a preset yield value, and the preset yield value is smaller than the yield edge position 3 near the center of the wafer.
  • the grain yield at the position on the O side is greater than or equal to the grain yield at the position on the side of the edge position 3 away from the center O.
  • the preset yield value is 30%, that is to say, if there are 100 dies at the edge position 3 of the yield, 30 dies are qualified dies 41, and the remaining 70 are unqualified dies 42; and The yield of the die at the edge position 3 near the center O of the wafer is greater than 30%, and the yield of the die at the edge position 3 far from the center O is less than or equal to 30%.
  • the preset yield value is 0, that is, the yield of the die at the edge position 3 of the yield on the wafer is 0.
  • the preset yield value can also be 20%, 30%, or 50%, of course, it can also be set according to actual needs.
  • the preset yield value at the yield edge position 3 can be set to 50%.
  • the grains at the low-grain yield position where the yield edge position 3 is far away from the center of the circle are not taken into consideration, so that according to the grain size And in the new wafer layout calculated by the edge position 3 of the yield rate, it is easier to obtain the closely-arranged qualified die.
  • the preset yield value of the yield edge position 3 can be set to 0, so that according to the die size and the yield edge position 3 In the new wafer layout calculated, the total number of qualified dies obtained is the largest.
  • the yield edge position 3 is a closed line surrounding the center O, and the closed line is a closed curve or a closed polyline.
  • the closed curve and the edge 1 line of the wafer are concentric circles, thereby facilitating the determination of the yield edge position 3 on the wafer.
  • determining the yield edge position 3 of the wafer according to the yield distribution map 401 includes: determining the distance between the center O of the wafer and the qualified die 41 furthest from the center O as the first size; The center O of the wafer is the origin and the first dimension is the radius to obtain the closed pattern, and the position of the closed pattern is taken as the yield edge position 3.
  • the yield edge position 3 is a closed curve concentric with the edge 1 of the wafer, and the die yield of the yield edge position 3 is 0 for description
  • the yield distribution map 401 it is determined in the yield distribution map 401 that The qualified die 41 with the farthest distance from the center O of the wafer, the distance between the center O of the wafer and the qualified die 41 with the farthest from the center O is determined as the first dimension R1, so that the center O of the wafer is taken as the origin ,
  • the first dimension R1 is the radius to obtain a closed pattern concentric with the edge 1 of the wafer, and the position of the closed pattern is regarded as the yield edge position 3.
  • Step 103 Calculate a new wafer layout according to the die size and the edge position 3 of the yield rate. Specifically, the new wafer layout is calculated based on the size of the dicing lane, the layout of the die in a single shot, the die size, and the position of the edge of the yield.
  • Step 104 Perform wafer exposure according to the new wafer layout.
  • the damage of the die near the wafer edge washing position 2 during the production process is taken into consideration, and according to the actual quality Determine the new wafer layout based on the edge position 3 and the die size.
  • the wafer exposure is performed according to the new wafer layout, the number of qualified dies 41 obtained and the number of complete dies in the new wafer layout It is substantially the same, thereby improving the production yield of qualified dies 41 on the wafer.
  • the new wafer layout is calculated according to the die size and yield edge position 3, it also includes: when the yield distribution map of the wafer under the new wafer layout changes, it needs to be re-determined The new yield edge position and the corrected new wafer layout are recalculated according to the new yield edge position. In this way, the wafer layout can be corrected in time according to the changed wafer yield distribution map, and the production yield of qualified dies 41 on the wafer is further ensured.
  • the embodiment of the present application provides a method for designing a wafer layout.
  • the initial wafer layout 51 (that is, the wafer layout in the prior art) is based on the die size and the wafer edge washing position 2
  • the yield of the die near the wafer edge washing position 2 is often low or even zero. Therefore, according to the initial wafer layout in the prior art 51.
  • the number of qualified dies 41 obtained is often less than the number of complete dies in the initial wafer layout 51; and in this embodiment, the yield distribution map 401 of wafers under the initial wafer layout 51 is To determine the actual yield edge position 3 of the wafer, consider the damage of the die near the wafer edge washing position 2 during the production process when determining the new wafer layout, according to the actual yield edge position 3 and die size to determine the new wafer layout. After wafer exposure is performed according to the new wafer layout, the number of qualified dies 41 obtained is approximately the same as the number of complete dies in the new wafer layout. Thus, the production yield of qualified die 41 on the wafer is improved.
  • the second embodiment of the present application relates to a method for designing a wafer layout.
  • the second embodiment is an improvement of the first embodiment, and the main improvement lies in that this embodiment provides an implementation method of how to specifically determine a new wafer layout.
  • FIG. 4 The schematic flow chart of the wafer layout design method in this embodiment is shown in FIG. 4, which will be described in detail below with reference to FIGS. 2 and 5:
  • Step 201 Provide a yield distribution map 401 of wafers under the initial wafer layout 51.
  • Step 202 Determine the yield edge position 3 of the wafer according to the yield distribution map 401.
  • steps 201 and 202 are substantially the same as the steps 101 and 102 in the first embodiment. To avoid repetition, they will not be repeated in this embodiment.
  • Step 203 Determine the die 411 at the position of the center O of the wafer in the initial wafer layout 51.
  • the center point of the die 411 at the location of the center O of the wafer may be overlapped with the center O of the wafer, or the die at the location of the center O of the wafer may be overlapped. Any vertex of 411 coincides with the circle center O.
  • the initial wafer layout 51 is as shown in FIG. 2, taking any vertex of the die 411 at the position of the center O of the wafer overlapping with the center O as an example for description. Of course, in practical applications, any point on the die 411 at the position of the center O of the wafer in the initial wafer layout 51 may coincide with the center O.
  • Step 204 Move the die 411 at the position of the circle center O at a fixed step relative to the circle center O, so that the initial wafer layout 51 is shifted.
  • the die 411 at the position of the center O is moved at a fixed step relative to the center O of the wafer, so that the initial wafer layout 51 is shifted, so that the die layout on the entire wafer is changed.
  • the crystal grain has horizontal and vertical sides, the horizontal side has a horizontal size, the vertical side has a vertical size, the horizontal fixed step does not exceed half of the horizontal size, and the vertical fixed step does not exceed half of the vertical size.
  • the moving direction and moving step distance can also be set by oneself, for example, the horizontal fixed step and the vertical fixed step are both less than 1 mm.
  • Step 205 Calculate the number of complete dies in the edge position 3 of the yield rate.
  • Step 206 Repeatedly moving the die 411 at the position of the center O of the wafer until the maximum number of complete dies is obtained.
  • each time the initial wafer layout 51 is moved the shifted wafer layout is obtained, and the shifted wafer layout is used to compare the test wafer (the test wafer and the wafer in this application).
  • the same circle size) is exposed to obtain a new yield distribution map 402 under the shifted wafer layout, and the shifted wafer layout is calculated to have a complete wafer within the yield edge position 3 in the new yield distribution diagram 402.
  • the above steps 204 and 205 are repeated until the number of complete dies in the edge position 3 of the calculated yield is the largest.
  • Step 207 Determine the wafer layout corresponding to the maximum number of complete dies in the obtained yield edge position 3 as the new wafer layout 52.
  • Step 208 Perform wafer exposure according to the new wafer layout 52.
  • the wafer layout corresponding to the maximum number of complete dies in the yield edge position 3 obtained in the above steps is determined as the new wafer layout 52. In this way, the new wafer layout is used.
  • the circle layout 52 has the largest number of qualified dies 41 after wafer exposure.
  • exposing the wafer according to the new wafer layout 52 includes: determining the initial exposure position of the die 411 at the position of the center O of the wafer in the new wafer layout 52, taking the initial exposure position as a reference According to the layout of the die in a single shot, the wafers are sequentially exposed in the single shot.
  • the embodiment of the present application provides a method for designing a wafer layout, and provides a specific method for calculating a new wafer layout 52 based on the die size and the yield edge position 3 Method to realize.
  • This embodiment can be implemented in cooperation with the first embodiment.
  • the related technical details mentioned in the first embodiment are still valid in this embodiment, and the related technical details mentioned in this embodiment can also be applied in the first embodiment.
  • the technical effect that can be achieved in the first embodiment can also be achieved in this embodiment, and in order to reduce repetition, it will not be repeated here.
  • the third embodiment of the present application relates to an exposure system of a lithography machine. As shown in FIG. 6, it includes at least one processor 501; Stored with instructions that can be executed by at least one processor 501, the instructions are executed by at least one processor 501, so that at least one processor 501 can execute the wafer layout design method in any of the above embodiments to obtain a new wafer layout 52; The processor 501 is used to send the obtained new wafer layout 52 to the exposure device 503, and the exposure device 503 is used to perform wafer exposure according to the new wafer layout 52.
  • the memory 502 and the processor 501 are connected in a bus manner.
  • the bus may include any number of interconnected buses and bridges, and the bus connects one or more various circuits of the processor 501 and the memory 502 together.
  • the bus can also connect various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are all known in the art, and therefore, will not be further described herein.
  • the bus interface provides an interface between the bus and the transceiver.
  • the transceiver may be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on the transmission medium.
  • the data processed by the processor 501 is transmitted on the wireless medium through the antenna, and further, the antenna also receives the data and transmits the data to the processor 501.
  • the processor 501 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions.
  • the memory 502 may be used to store data used by the processor 501 when performing operations.
  • the fourth embodiment of the present application also provides a computer-readable storage medium that stores a computer program that, when executed by a processor, implements the wafer layout design method in any of the foregoing embodiments.
  • the program is stored in a storage medium and includes several instructions to enable a device ( It may be a single-chip microcomputer, a chip, etc.) or a processor (processor) that executes all or part of the steps of the methods described in the embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

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Abstract

一种晶圆布局（52）的设计方法，包括：提供初始晶圆布局（51）下的晶圆的良率分布图（401）；根据良率分布图（401）确定晶圆的良率边缘位置（3）；根据晶粒尺寸以及良率边缘位置（3）计算得到新的晶圆布局（52），根据这种晶圆布局（52）的设计方法得到的晶圆布局（52）在生产时得到的合格晶粒的数目较多。还公开了一种光刻机曝光系统。

Description

晶圆布局的设计方法及光刻机曝光系统
交叉引用
本申请引用于2020年06月01日递交的名称为“晶圆布局的设计方法及光刻机曝光系统”的第2020104867270号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种晶圆布局的设计方法及光刻机曝光系统。
背景技术
半导体晶圆(诸如硅、锗和III-V材料晶圆)被用在集成电路的制造中，在晶圆上可使用各种半导体工艺，诸如光刻(例如图案形成、蚀刻、沉积等)、外延生长、掺杂、抛光和其它此类工艺形成晶粒。通常，在单个晶圆上形成若干相同的晶粒，范围从每个晶圆数十到每个晶圆数百甚至到每个晶圆数千个晶粒，取决于装置裸芯片的尺寸。
现有技术中可根据晶粒的尺寸，单个shot中晶粒的排布方式以及晶圆洗边位置来计算晶圆布局，从而使得在晶圆洗边位置内得到的完整晶粒的数目最多。
然而，发明人发现由于在实际生产中，晶粒在晶圆径向分布上的良率不是全部为100％，在根据现有技术中的晶圆布局生产时单片晶圆上的合格晶粒的数目往往小于计算得到完整晶粒的数目，使得单片晶圆良率较低。
发明内容
本申请部分实施例的目的在于提供一种晶圆布局的设计方法及光刻机曝光系统，根据此种晶圆布局的设计方法得到的晶圆布局在生产时得到的合格晶粒的数目较多。
为解决上述技术问题，本申请实施例提供了一种晶圆布局的设计方法，包括：提供初始晶圆布局下的晶圆的良率分布图；根据所述良率分布图确定所述晶圆的良率边缘位置；根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局。
本申请实施例还提供了一种光刻机曝光系统，包括：至少一个处理器；以及，与所 述至少一个处理器通信连接的存储器和曝光装置；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行上述的晶圆布局的设计方法得到新的晶圆布局；所述处理器用于将得到的所述新的晶圆布局发送至所述曝光装置，所述曝光装置用于根据所述新的晶圆布局进行晶圆曝光。
本申请实施例相对于现有技术而言，提供了一种晶圆布局的设计方法，初始晶圆布局(即现有技术中的晶圆布局)是根据晶粒尺寸以及晶圆洗边位置来确定的，但由于生产过程中工艺控制能力的差异往往会导致靠近晶圆洗边位置处的晶粒良率较低甚至为零，因此，在根据现有技术中的初始晶圆布局进行晶圆曝光后，得到的合格晶粒的数目往往小于初始晶圆布局中完整晶粒的数目；而本实施例中根据初始晶圆布局下的晶圆的良率分布图来确定晶圆实际的良率边缘位置，在确定新的晶圆布局时将在生产过程中靠近晶圆洗边位置处的晶粒的损坏情况考虑在内，根据实际的良率边缘位置以及晶粒尺寸来确定新的晶圆布局，根据新的晶圆布局进行晶圆曝光后，得到的合格晶粒的数目与该新的晶圆布局中的完整晶粒的数目大致相同，从而提高了晶圆上合格晶粒的生产良率。
另外，所述良率边缘位置处的晶粒良率为预设良率值，所述预设良率值小于所述良率边缘位置靠近所述晶圆的圆心一侧位置处的晶粒良率、且大于或等于所述良率边缘位置远离所述圆心一侧位置处的晶粒良率。
另外，所述预设良率值为0。
另外，所述良率边缘位置呈包围所述圆心的封闭线条，且所述封闭线条为封闭曲线或封闭折线。
另外，所述封闭曲线与所述晶圆的边缘线为同心圆。
另外，所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局，包括：确定所述初始晶圆布局中所述晶圆的圆心所在位置的晶粒；相对所述圆心以固定步进移动所述圆心所在位置的晶粒，以使所述初始晶圆布局发生偏移，其中，所述固定步进包括横向固定步进和纵向固定步进，所述横向固定步进沿所述横向方向，所纵向固定步进沿所述纵向方向；计算所述良率边缘位置内完整晶粒的数目；重复移动所述晶圆的圆心所在位置的晶粒，直至得到的所述完整晶粒的数目最多；将得到的所述完整晶粒的数目最多时对应的晶圆布局，确定为所述新的晶圆布局。
另外，所述晶粒具有横边和纵边，所述横边具有横向尺寸，所述纵边具有纵向尺寸，所述横向固定步进不超过所述横向尺寸的一半，所述纵向固定步进不超过所述纵向尺寸的一半。
另外，所述初始晶圆布局中所述晶圆的圆心所在位置的晶粒的中心点与所述圆心重 合；或者，所述初始晶圆布局中所述晶圆的圆心所在位置的晶粒的任一顶点与所述圆心重合。
另外，所述提供初始晶圆布局下的晶圆的良率分布图，包括：根据晶圆洗边位置和所述晶粒尺寸确定所述初始晶圆布局；根据所述初始晶圆布局对所述晶圆进行曝光；对曝光后的所述晶圆进行检测得到所述初始晶圆布局下的所述良率分布图。
另外，所述根据晶圆洗边位置和所述晶粒尺寸确定所述初始晶圆布局，包括：根据切割道的尺寸、单个shot中晶粒的布局、所述晶粒尺寸以及所述晶圆洗边位置计算得到所述初始晶圆布局。
另外，所述根据所述良率分布图确定所述晶圆的良率边缘位置，包括：确定所述晶圆的圆心与距离所述圆心最远的合格晶粒之间的距离为第一尺寸；以所述晶圆的圆心为原点、所述第一尺寸为半径得到封闭图形，将所述封闭图形所在位置作为所述良率边缘位置。
另外，所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局之后，还包括：根据所述新的晶圆布局进行晶圆曝光。
另外，所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局，包括：根据切割道的尺寸、单个shot中晶粒的布局、所述晶粒尺寸以及所述良率边缘位置计算得到所述新的晶圆布局。
另外，在所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局之后，还包括：
当所述新的晶圆布局下所述晶圆的良率分布图发生变化时，重新确定新的良率边缘位置并根据所述新的良率边缘位置重新计算得到更正后的新的晶圆布局。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例的晶圆布局的设计方法的流程示意图；
图2是根据本申请第一实施例中初始晶圆布局的示意图；
图3是根据本申请第一实施例的半径为150毫米的晶圆上的晶粒良率随着半径逐渐变化的曲线图；
图4是根据本申请第二实施例的晶圆布局的设计方法的流程示意图；
图5是根据本申请第二实施例中新的晶圆布局的示意图；
图6是根据本申请第三实施例的光刻机曝光系统的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请的第一实施例涉及一种晶圆布局的设计方法，本实施例的核心在于包括：提供初始晶圆布局下的晶圆的良率分布图；根据所述良率分布图确定所述晶圆的良率边缘位置；根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局。初始晶圆布局(即现有技术中的晶圆布局)是根据晶粒尺寸以及晶圆洗边位置来确定的，但由于生产过程中工艺控制能力的差异往往会导致靠近晶圆洗边位置处的晶粒良率较低甚至为零，因此，在根据现有技术中的初始晶圆布局进行晶圆曝光后，得到的合格晶粒的数目往往小于初始晶圆布局中完整晶粒的数目；而本实施例中根据初始晶圆布局下的晶圆的良率分布图来确定晶圆实际的良率边缘位置，在确定新的晶圆布局时将在生产过程中靠近晶圆洗边位置处的晶粒的损坏情况考虑在内，根据实际的良率边缘位置以及晶粒尺寸来确定新的晶圆布局，根据新的晶圆布局进行晶圆曝光后，得到的合格晶粒的数目与该新的晶圆布局中的完整晶粒的数目大致相同，从而提高了晶圆上合格晶粒的生产良率。
下面对本实施例的晶圆布局的设计方法的实现细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本方案的必须。
本实施例中的晶圆布局的设计方法的流程示意图如图1所示，下面结合附图2和图3进行详细说明：
步骤101：提供初始晶圆布局51下的晶圆的良率分布图401。
本实施例中提供初始晶圆布局51下晶圆的良率分布图401，包括：根据晶圆洗边位置2和晶粒尺寸确定初始晶圆布局51；根据初始晶圆布局51对晶圆进行曝光；对曝光后的晶圆进行检测得到初始晶圆布局51下的良率分布图401。
具体地说，在对晶圆进行曝光形成晶粒之前，需在晶圆表面旋涂光刻胶，光刻胶旋涂的过程中，多余的胶会被离心力推到晶圆的边缘1，大部分被甩离晶圆，有一部分残留在晶圆的边缘1。由于晶圆的边缘1气流相对速度很大，导致残留的胶很快固化，形成隆起的 边缘。因此，在光刻胶旋涂之后，对晶圆的边缘1软烘后，利用化学或光学的方法去除晶圆的边缘1处的光刻胶，称为光刻胶边缘修复，也叫光刻胶去边。晶圆洗边位置2是在对晶圆进行光刻胶边缘修复后得到的位置。具体的，可采用EBR(Edge Bevel Remove)或WEE(Wafer Edge Exposure)方式进行光刻胶去边。
如图2所示，晶圆洗边位置2以虚线示出，位于晶圆的边缘1靠近晶圆的圆心O一侧，由于晶圆上自晶圆洗边位置2远离圆心O的一侧在实际制作中无法得到完整的晶粒，因此，在确定初始晶圆布局51时根据晶圆洗边位置2和晶粒尺寸来确定初始晶圆布局51，并根据初始晶圆布局51对晶圆进行曝光，对曝光后的晶圆进行检测便能够得到初始晶圆布局51下晶圆的良率分布图401，其中，良率分布图401为合格晶粒41在晶圆上的位置分布图。
在实际应用中，根据晶圆洗边位置2和晶粒尺寸确定初始晶圆布局51时，还获取切割道的尺寸以及单个shot中晶粒的布局，从而根据切割道的尺寸、单个shot中晶粒的布局、晶粒尺寸以及晶圆洗边位置2计算得到初始晶圆布局51。其中，切割道尺寸为晶圆上相邻两个晶粒之间的间隔距离，shot为在对晶圆进行曝光时一次曝光所拍摄的区域，也可以理解为光掩膜单次曝光区域对应到晶圆上的区域，单个shot中晶粒的布局即为光掩膜在曝光时所曝光晶粒的排布方式。也就是说，在确定初始晶圆布局51时，根据切割道的尺寸、单个shot中晶粒的布局、晶粒尺寸以及晶圆洗边位置2来共同确定。
步骤102：根据良率分布图401确定晶圆的良率边缘位置3。
具体地说，在得到初始晶圆布局51下的晶圆的良率分布图401后，对良率分布图401进行检测确定出晶圆的良率边缘位置3。在良率分布图401中可以看到合格晶粒41和不合格晶粒42在晶圆上的分布情况。图3所示为半径为150毫米的晶圆上的晶粒良率(晶粒良率＝合格晶粒41的数目/总晶粒的数目*100％)随着半径逐渐变化的曲线图，其具体变化趋势如下表1所示：
半径(毫米) 晶粒良率(％)
～ ～
145 25
145.5 5
146 1
146.5 0.5
147 0
147.5 0
148 0
148.5 0
149 0
149.5 0
150 0
从图3及表1中可以看出，越靠近晶圆的圆心O位置处的晶圆径向上的晶粒良率越高，越靠近晶圆的边缘1位置处的晶圆径向上的晶粒良率越低。假设晶圆洗边位置2距离圆心O的距离为147.5毫米，从上表中可以看出，在晶圆洗边位置2处的晶粒良率为0，但实际检测得到的晶粒良率自距离圆心O147毫米位置处便为0，因此，在实际生产后得到的合格晶粒41的数目小于初始晶圆布局51中完整晶粒的数目。需要说明的是，本实施例中完整晶粒为初始晶圆布局51中所计算得到的完整晶粒；而合格晶粒41则是依据初始晶圆布局51对晶圆进行曝光后所得到的符合使用要求的晶粒。由于在实际生产中，晶圆上靠近晶圆的边缘1的完整晶粒可能损坏而不符合使用要求，因此，合格晶粒41的数目与完整晶粒的数目一般并不相同。
针对于此，本实施例中定义出良率边缘位置3，良率边缘位置3处的晶粒良率为预设良率值，预设良率值小于良率边缘位置3靠近晶圆的圆心O一侧位置处的晶粒良率、且大于或等于良率边缘位置3远离圆心O一侧位置处的晶粒良率。假设预设良率值为30％，也就是说，良率边缘位置3处若有100颗晶粒，则有30个晶粒为合格晶粒41，其余70个为不合格晶粒42；而良率边缘位置3靠近晶圆的圆心O一侧位置处的晶粒良率大于30％，且良率边缘位置3远离圆心O一侧位置处的晶粒良率小于或等于30％。
本实施例中预设良率值为0，即就是说在晶圆上良率边缘位置3处的晶粒良率为0。例如图2中所示的良率边缘位置3。预设良率值还可以为20％、30％或50％，当然也可根据实际需求自行设置。可将良率边缘位置3处的预设良率值设置为50％，此时不将良率边缘位置3远离圆心的低晶粒良率位置处的晶粒考虑在内，从而根据晶粒尺寸以及良率边缘位置3计算得到新的晶圆布局中，较容易得到紧密排布的合格晶粒。若仅考虑合格晶粒41的总数目而不考虑合格晶粒41的排布位置，则可将良率边缘位置3的预设良率值设置为0，使得根据晶粒尺寸以及良率边缘位置3计算得到新的晶圆布局中，所得到的合格晶粒的总数目最多。
可选地，良率边缘位置3呈包围圆心O的封闭线条，且封闭线条为封闭曲线或封闭折线。可选地，封闭曲线与晶圆的边缘1线为同心圆，从而方便在晶圆上确定出良率边缘位置3。
值得说明的是，根据良率分布图401确定晶圆的良率边缘位置3，包括：确定晶圆的圆心O与距离圆心O最远的合格晶粒41之间的距离为第一尺寸；以晶圆的圆心O为原点、第一尺寸为半径得到封闭图形，将封闭图形所在位置作为良率边缘位置3。
具体地说，以良率边缘位置3为与晶圆的边缘1线为同心圆的封闭曲线、且良率边缘位置3的晶粒良率为0进行说明，在良率分布图401中确定与晶圆的圆心O距离最远的合 格晶粒41，确定晶圆的圆心O与距离圆心O最远的合格晶粒41之间的距离为第一尺寸R1，从而以晶圆的圆心O为原点、第一尺寸R1为半径得到与晶圆的边缘1为同心圆的封闭图形，将该封闭图形所在位置作为良率边缘位置3。
步骤103：根据晶粒尺寸以及良率边缘位置3计算得到新的晶圆布局。具体包括：根据切割道的尺寸、单个shot中晶粒的布局、晶粒尺寸以及良率边缘位置3计算得到新的晶圆布局。
步骤104：根据新的晶圆布局进行晶圆曝光。
针对上述步骤103和步骤104具体地说，本实施例中在确定新的晶圆布局时将在生产过程中靠近晶圆洗边位置2处的晶粒的损坏情况考虑在内，根据实际的良率边缘位置3以及晶粒尺寸来确定新的晶圆布局，根据新的晶圆布局进行晶圆曝光后，得到的合格晶粒41的数目与该新的晶圆布局中的完整晶粒的数目大致相同，从而提高了晶圆上合格晶粒41的生产良率。
值得说明的是，在根据晶粒尺寸以及良率边缘位置3计算得到新的晶圆布局之后，还包括：当新的晶圆布局下的晶圆的良率分布图发生变化时，需要重新确定新的良率边缘位置以及根据新的良率边缘位置重新计算得到更正后的新的晶圆布局。从而实现根据变化后的晶圆的良率分布图及时更正晶圆布局，进一步保证了晶圆上合格晶粒41的生产良率。
与现有技术相比，本申请实施例提供了一种晶圆布局的设计方法，初始晶圆布局51(即现有技术中的晶圆布局)是根据晶粒尺寸以及晶圆洗边位置2来确定的，但由于生产过程中的工艺控制能力的差异往往会导致靠近晶圆洗边位置2处的晶粒良率较低甚至为零，因此，在根据现有技术中的初始晶圆布局51进行晶圆曝光后，得到的合格晶粒41的数目往往小于初始晶圆布局51中完整晶粒的数目；而本实施例中根据初始晶圆布局51下的晶圆的良率分布图401来确定晶圆实际的良率边缘位置3，在确定新的晶圆布局时将在生产过程中靠近晶圆洗边位置2处的晶粒的损坏情况考虑在内，根据实际的良率边缘位置3以及晶粒尺寸来确定新的晶圆布局，根据新的晶圆布局进行晶圆曝光后，得到的合格晶粒41的数目与该新的晶圆布局中的完整晶粒的数目大致相同，从而提高了晶圆上合格晶粒41的生产良率。
本申请的第二实施例涉及一种晶圆布局的设计方法。第二实施例是对第一实施例的改进，主要改进之处在于，本实施例提供了一种具体如何确定新的晶圆布局的实现方式。
本实施例中的晶圆布局的设计方法的流程示意图如图4所示，下面结合附图2和5进行详细说明：
步骤201：提供初始晶圆布局51下的晶圆的良率分布图401。
步骤202：根据良率分布图401确定晶圆的良率边缘位置3。
上述步骤201、202与第一实施例中的步骤101和102大致相同，为避免重复，本实施例中不再赘述。
步骤203：确定初始晶圆布局51中晶圆的圆心O所在位置的晶粒411。
具体地说，在确定初始晶圆布局51时，可将晶圆的圆心O所在位置的晶粒411的中心点与晶圆的圆心O重合，或者，将晶圆的圆心O所在位置的晶粒411的任一顶点与圆心O重合。本实施例中初始晶圆布局51如图2所示，以晶圆的圆心O所在位置的晶粒411的任一顶点与圆心O重合为例进行说明。当然，在实际应用中，初始晶圆布局51中晶圆的圆心O所在位置的晶粒411上任意一点可与圆心O重合。
步骤204：相对圆心O以固定步进移动圆心O所在位置的晶粒411，以使初始晶圆布局51发生偏移。
具体地说，相对晶圆的圆心O以固定步进移动圆心O所在位置的晶粒411，以使初始晶圆布局51发生偏移，从而使得整个晶圆上的晶粒布局发生变化。其中，晶粒具有横边和纵边，横边具有横向尺寸，纵边具有纵向尺寸，横向固定步进不超过横向尺寸的一半，纵向固定步进不超过纵向尺寸的一半。也就是说，在相对圆心O移动圆心O所在位置的晶粒411时，可以在横向以小于晶粒横向尺寸的一半为固定步进移动；或者，在纵向以小于晶粒纵向尺寸的一半为固定步进移动。当然，在实际应用中，也可自行设置移动方向和移动的步进距离，例如，横向固定步进和纵向固定步进均小于1毫米。
步骤205：计算良率边缘位置3内完整晶粒的数目。
步骤206：重复移动晶圆的圆心O所在位置的晶粒411，直至得到的完整晶粒的数目最多。
针对上述步骤205和206具体地说，每一次移动初始晶圆布局51后得到偏移后的晶圆布局，以偏移后的晶圆布局对测试晶圆(测试晶圆与本申请中的晶圆尺寸相同)进行曝光，从而得到偏移后的晶圆布局下新的良率分布图402，计算偏移后的晶圆布局在新的良率分布图402中良率边缘位置3内完整晶粒的数目。重复执行上述步骤204和步骤205，直至计算得到的良率边缘位置3内完整晶粒的数目最多。
步骤207：将得到的良率边缘位置3内完整晶粒的数目最多时对应的晶圆布局，确定为新的晶圆布局52。
步骤208：根据新的晶圆布局52进行晶圆曝光。
针对上述步骤207和208具体地说，将上述步骤中得到的良率边缘位置3内完整晶粒的数目最多时对应的晶圆布局，确定为新的晶圆布局52，如此，利用新的晶圆布局52进行晶圆曝光后得到的合格晶粒41的数目最多。
本实施例中根据新的晶圆布局52对晶圆进行曝光，包括：确定晶圆的圆心O所在位置的晶粒411在新的晶圆布局52中的初始曝光位置，以初始曝光位置为参照，根据单个shot中晶粒的布局以该单个shot依次对晶圆进行曝光。
与现有技术相比，本申请实施例中提供了一种晶圆布局的设计方法，给出了一种根据晶粒尺寸以及所述良率边缘位置3计算得到新的晶圆布局52的具体实现方式。
上面各种方法的步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对算法中或者流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其算法和流程的核心设计都在该专利的保护范围内。
本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，本实施例中提到的相关技术细节也可应用在第一实施例中。在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。
本申请第三实施例涉及一种光刻机曝光系统，如图6所示，包括至少一个处理器501；以及，与至少一个处理器501通信连接的存储器502和曝光装置503；其中，存储器502存储有可被至少一个处理器501执行的指令，指令被至少一个处理器501执行，以使至少一个处理器501能够执行上述任一实施例中的晶圆布局的设计方法得到新的晶圆布局52；处理器501用于将得到的新的晶圆布局52发送至曝光装置503，曝光装置503用于根据新的晶圆布局52进行晶圆曝光。
其中，存储器502和处理器501采用总线方式连接，总线可以包括任意数量的互联的总线和桥，总线将一个或多个处理器501和存储器502的各种电路连接在一起。总线还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路连接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口在总线和收发机之间提供接口。收发机可以是一个元件，也可以是多个元件，比如多个接收器和发送器，提供用于在传输介质上与各种其他装置通信的单元。经处理器501处理的数据通过天线在无线介质上进行传输，进一步，天线还接收数据并将数据传送给处理器501。
处理器501负责管理总线和通常的处理，还可以提供各种功能，包括定时、外围接口、电压调节、电源管理以及其他控制功能。而存储器502可以被用于存储处理器501在执行操作时所使用的数据。
本申请的第四实施例还提供了一种计算机可读存储介质，存储有计算机程序，所述计算机程序被处理器执行时实现上述任一实施例中的晶圆布局的设计方法。
即，本领域技术人员可以理解，实现上述实施例方法中的全部或部分步骤是可以通 过程序来指令相关的硬件来完成，该程序存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种晶圆布局的设计方法，其中，包括：
    提供初始晶圆布局下的晶圆的良率分布图；
    根据所述良率分布图确定所述晶圆的良率边缘位置；
    根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局。
  2. 根据权利要求1所述的设计方法，其中：
    所述良率边缘位置处的晶粒良率为预设良率值，所述预设良率值小于所述良率边缘位置靠近所述晶圆的圆心一侧位置处的晶粒良率、且大于或等于所述良率边缘位置远离所述圆心一侧位置处的晶粒良率。
  3. 根据权利要求2所述的设计方法，其中：
    所述预设良率值为0。
  4. 根据权利要求2所述的设计方法，其中：
    所述良率边缘位置呈包围所述圆心的封闭线条，且所述封闭线条为封闭曲线或封闭折线。
  5. 根据权利要求4所述的设计方法，其中：
    所述封闭曲线与所述晶圆的边缘线为同心圆。
  6. 根据权利要求1所述的设计方法，其中，所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局，包括：
    确定所述初始晶圆布局中所述晶圆的圆心所在位置的晶粒；
    相对所述圆心以固定步进移动所述圆心所在位置的晶粒，以使所述初始晶圆布局发生偏移，其中，所述固定步进包括横向固定步进和纵向固定步进，所述横向固定步进沿所述横向方向，所纵向固定步进沿所述纵向方向；
    计算所述良率边缘位置内完整晶粒的数目；
    重复移动所述晶圆的圆心所在位置的晶粒，直至得到的所述完整晶粒的数目最多；
    将得到的所述完整晶粒的数目最多时对应的晶圆布局，确定为所述新的晶圆布局。
  7. 根据权利要求6所述的设计方法，其中，所述晶粒具有横边和纵边，所述横边具有横向尺寸，所述纵边具有纵向尺寸，所述横向固定步进不超过所述横向尺寸的一半，所述纵向固定步进不超过所述纵向尺寸的一半。
  8. 根据权利要求6所述的设计方法，其中：
    所述初始晶圆布局中所述晶圆的圆心所在位置的晶粒的中心点与所述圆心重合；
    或者，
    所述初始晶圆布局中所述晶圆的圆心所在位置的晶粒的任一顶点与所述圆心重合。
  9. 根据权利要求1所述的设计方法，其中，所述提供初始晶圆布局下的晶圆的良率分布图，包括：
    根据晶圆洗边位置和所述晶粒尺寸确定所述初始晶圆布局；
    根据所述初始晶圆布局对所述晶圆进行曝光；
    对曝光后的所述晶圆进行检测得到所述初始晶圆布局下的所述良率分布图。
  10. 根据权利要求9所述的设计方法，所述根据晶圆洗边位置和所述晶粒尺寸确定所述初始晶圆布局，包括：
    根据切割道的尺寸、单个shot中晶粒的布局、所述晶粒尺寸以及所述晶圆洗边位置计算得到所述初始晶圆布局。
  11. 根据权利要求1所述的设计方法，其中，所述根据所述良率分布图确定所述晶圆的良率边缘位置，包括：
    确定所述晶圆的圆心与距离所述圆心最远的合格晶粒之间的距离为第一尺寸；
    以所述晶圆的圆心为原点、所述第一尺寸为半径得到封闭图形，将所述封闭图形所在位置作为所述良率边缘位置。
  12. 根据权利要求1所述的设计方法，其中，所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局之后，还包括：
    根据所述新的晶圆布局进行晶圆曝光。
  13. 根据权利要求1所述的设计方法，其中，所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局，包括：
    根据切割道的尺寸、单个shot中晶粒的布局、所述晶粒尺寸以及所述良率边缘位置计算得到所述新的晶圆布局。
  14. 根据权利要求1所述的设计方法，其中，在所述根据晶粒尺寸以及所述良率边缘位置计算得到新的晶圆布局之后，还包括：
    当所述新的晶圆布局下所述晶圆的良率分布图发生变化时，重新确定新的良率边缘位置并根据所述新的良率边缘位置重新计算得到更正后的新的晶圆布局。
  15. 一种光刻机曝光系统，其中，包括：
    至少一个处理器；以及，
    与所述至少一个处理器通信连接的存储器和曝光装置；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理 器执行，以使所述至少一个处理器能够执行如权利要求1所述的晶圆布局的设计方法得到新的晶圆布局；
    所述处理器用于将得到的所述新的晶圆布局发送至所述曝光装置，所述曝光装置用于根据所述新的晶圆布局进行晶圆曝光。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114997097A (zh) * 2022-08-03 2022-09-02 成都复锦功率半导体技术发展有限公司 基于比例布图的多型号芯片版图设计方法、芯片及终端
CN116859680A (zh) * 2023-07-14 2023-10-10 江苏影速集成电路装备股份有限公司 一种针对晶圆的曝光方法及曝光装置
CN117115143A (zh) * 2023-10-16 2023-11-24 深圳市壹倍科技有限公司 一种检测晶圆芯粒的方法、装置、计算机设备及存储介质
US11988612B2 (en) 2021-01-26 2024-05-21 Changxin Memory Technologies, Inc. Methods for determining focus spot window and judging whether wafer needs to be reworked

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW466657B (en) * 2000-06-23 2001-12-01 Promos Technologies Inc Method for calculating the yield loss
US20020170022A1 (en) * 2001-04-25 2002-11-14 Fujitsu Limited Data analysis apparatus, data analysis method, and computer products
JP2008251811A (ja) * 2007-03-30 2008-10-16 Fujitsu Microelectronics Ltd ウェハレイアウト方法及びウェハレイアウト装置
CN101311737A (zh) * 2007-05-23 2008-11-26 中芯国际集成电路制造(上海)有限公司 晶圆质量控制方法
US20130110272A1 (en) * 2011-11-01 2013-05-02 Hsin-Ming Hou Experiments Method for Predicting Wafer Fabrication Outcome
CN103187329A (zh) * 2011-12-28 2013-07-03 无锡华润上华科技有限公司 一种晶圆良率分析方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6980917B2 (en) * 2002-12-30 2005-12-27 Lsi Logic Corporation Optimization of die yield in a silicon wafer “sweet spot”

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW466657B (en) * 2000-06-23 2001-12-01 Promos Technologies Inc Method for calculating the yield loss
US20020170022A1 (en) * 2001-04-25 2002-11-14 Fujitsu Limited Data analysis apparatus, data analysis method, and computer products
JP2008251811A (ja) * 2007-03-30 2008-10-16 Fujitsu Microelectronics Ltd ウェハレイアウト方法及びウェハレイアウト装置
CN101311737A (zh) * 2007-05-23 2008-11-26 中芯国际集成电路制造(上海)有限公司 晶圆质量控制方法
US20130110272A1 (en) * 2011-11-01 2013-05-02 Hsin-Ming Hou Experiments Method for Predicting Wafer Fabrication Outcome
CN103187329A (zh) * 2011-12-28 2013-07-03 无锡华润上华科技有限公司 一种晶圆良率分析方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11988612B2 (en) 2021-01-26 2024-05-21 Changxin Memory Technologies, Inc. Methods for determining focus spot window and judging whether wafer needs to be reworked
CN114997097A (zh) * 2022-08-03 2022-09-02 成都复锦功率半导体技术发展有限公司 基于比例布图的多型号芯片版图设计方法、芯片及终端
CN114997097B (zh) * 2022-08-03 2022-10-25 成都复锦功率半导体技术发展有限公司 基于比例布图的多型号芯片版图设计方法、芯片及终端
CN116859680A (zh) * 2023-07-14 2023-10-10 江苏影速集成电路装备股份有限公司 一种针对晶圆的曝光方法及曝光装置
CN116859680B (zh) * 2023-07-14 2024-04-30 江苏影速集成电路装备股份有限公司 一种针对晶圆的曝光方法及曝光装置
CN117115143A (zh) * 2023-10-16 2023-11-24 深圳市壹倍科技有限公司 一种检测晶圆芯粒的方法、装置、计算机设备及存储介质
CN117115143B (zh) * 2023-10-16 2024-01-02 深圳市壹倍科技有限公司 一种检测晶圆芯粒的方法、装置、计算机设备及存储介质

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