WO2021233437A1 - 一种显示装置 - Google Patents

一种显示装置 Download PDF

Info

Publication number
WO2021233437A1
WO2021233437A1 PCT/CN2021/095253 CN2021095253W WO2021233437A1 WO 2021233437 A1 WO2021233437 A1 WO 2021233437A1 CN 2021095253 W CN2021095253 W CN 2021095253W WO 2021233437 A1 WO2021233437 A1 WO 2021233437A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate
display device
light
drain
Prior art date
Application number
PCT/CN2021/095253
Other languages
English (en)
French (fr)
Inventor
刘晓伟
李潇
李富琳
高上
孙明晓
Original Assignee
海信视像科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202010440865.5A external-priority patent/CN113707669A/zh
Priority claimed from CN202011187049.4A external-priority patent/CN114446186A/zh
Priority claimed from CN202011291216.XA external-priority patent/CN114519962B/zh
Application filed by 海信视像科技股份有限公司 filed Critical 海信视像科技股份有限公司
Publication of WO2021233437A1 publication Critical patent/WO2021233437A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

  • This application relates to the field of display technology, and in particular to a display device.
  • Micro-Light Emitting Diode (Micro-LED) technology, that is, light-emitting diode (Light Emitting Diode, LED) miniaturization and matrix technology.
  • micro-light-emitting diode display technology has higher luminous efficiency, higher luminous brightness and lower luminous efficiency than organic light-emitting diode (OLED) display technology. Power consumption.
  • OLED organic light-emitting diode
  • a display device includes a plurality of pixel units.
  • the pixel units include a display area and a light-transmitting area. Small-sized and high-brightness micro light-emitting diodes are arranged in the display area, and a large number of areas Set as a light-transmitting area; set an electrochromic device in the light-transmitting area, wherein the electrochromic device appears transparent when the transparent display device is switched to the transparent display mode, and appears black and opaque when the transparent display device is switched to the normal display mode Light state.
  • the electrochromic device becomes transparent, so that most of the area in each pixel unit can transmit ambient light, which improves the transmittance of ambient light; in the conventional display mode, the electrochromic device becomes pure Black can greatly increase the contrast of the display, thereby improving the display quality.
  • the display device includes: a base substrate, a solar cell device layer, a first insulating layer, a driving circuit layer, and a light emitting device.
  • the solar cell device layer is arranged between the base substrate and the driving circuit layer, wherein the orthographic projection of the solar cell device layer on the base substrate at least covers the orthographic projection of the metal layer on the side of the driving circuit layer closest to the base substrate on the base substrate.
  • a display device is provided.
  • the driving circuit layer in the display device includes a metal connection electrode.
  • the metal connection electrode is used to connect the micro light emitting diode.
  • the metal connection electrode is a part of the metal layer in the driving circuit layer. When the metal layer is formed, the metal connection electrode can be patterned directly, and it is no longer necessary to pattern again to form the connection electrode. Therefore, the process steps are reduced, which is beneficial to improve the product yield.
  • FIG. 1 is a schematic diagram of a top view structure of a pixel unit of a display device in the related art
  • FIG. 2 is a schematic diagram of a top view structure of a pixel unit of a transparent display device in the related art
  • FIG. 3 is a top view of a pixel unit of a transparent display device provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of a pixel unit of a transparent display device provided by an embodiment of the application;
  • FIG. 5 is a schematic diagram of a cross-sectional structure of an electrochromic device provided by an embodiment of the application.
  • FIG. 6 is a schematic flowchart of a method for driving a transparent display device according to an embodiment of the application
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of a transparent display device provided by an embodiment of the application.
  • FIG. 8 is one of the top views of a pixel unit of a transparent display device according to an embodiment of the application.
  • FIG. 9 is the second top view of a pixel unit of a transparent display device provided by an embodiment of the application.
  • FIG. 10 is a schematic diagram of a cross-sectional structure of a solar cell device layer provided by an embodiment of the application.
  • FIG. 11 is a second schematic diagram of a partial cross-sectional structure of a transparent display device provided by an embodiment of the application.
  • FIG. 12 is the third schematic diagram of a partial cross-sectional structure of a transparent display device provided by an embodiment of the application.
  • FIG. 13 is a schematic diagram of a cross-sectional structure of a display device provided by an embodiment of the application.
  • FIG. 14 is a schematic diagram of a cross-sectional structure of a driving circuit layer provided by an embodiment of the application.
  • 15 is the second schematic diagram of the cross-sectional structure of the display device provided by the embodiment of the application.
  • FIG. 16 is a flowchart of a manufacturing method of a display device according to an embodiment of the application.
  • transparent display devices have gradually stepped into people's lives, such as transparent shop windows, transparent traffic signs, transparent watches, transparent car displays, etc., with broad application prospects.
  • LCD transparent display devices are generally liquid crystal display (Liquid Crystal Display, LCD for short) or Organic Light-Emitting Diode (OLED) display, adding a part of the light-transmitting area in the pixel unit to serve as a transparent environment Light, realize transparent display.
  • LCD transparent display devices need backlights to provide brightness, so they need a higher aperture ratio, while OLEDs have lower light-emitting brightness. Therefore, the pixel units of these two display modes need to have as large an aperture area as possible, so the area of the light-transmitting area will be compressed.
  • the transmittance of the display screen is very low; and because part of the display screen is used for light transmission and the other is used for display, the display picture of the display screen has the problems of low contrast and poor picture quality.
  • FIG. 1 is a schematic top view of the structure of a pixel unit of a display device in the related art.
  • the gate lines L of the display device extend along the first direction x and are arranged along the second direction y, and the data lines N extend along the second direction y and along the first direction x.
  • the gate line L and the data line N cross each other to divide a plurality of pixel units.
  • each pixel unit needs to be equipped with a color film, and the light emitted by the backlight module passes through the color film as sub-pixels of the corresponding color. Therefore, each pixel unit needs to have as high an aperture ratio as possible, and the aperture area is 10 Need as large an area as possible.
  • organic light emitting diode display devices there is no need to configure a backlight module, and organic light emitting diodes are used as sub-pixels to emit light.
  • the light emitting brightness of organic light emitting diodes is low, so each pixel unit also needs as large an opening area 10 as possible.
  • FIG. 2 is a schematic top view of the structure of a pixel unit of a transparent display device in the related art.
  • the pixel unit needs to have the aperture ratio as large as possible, which makes the transparent display device's transmittance of ambient light low, and the transparent display effect is not good; when the pixel unit is After the aperture ratio is compressed, the display picture has the problems of low contrast and poor picture quality clarity.
  • FIG. 3 is a top view of a pixel unit of the transparent display device provided by an embodiment of the present application.
  • the transparent display device includes a plurality of gate lines L and a plurality of first data lines N1.
  • the gate lines L extend along the first direction x and along the second direction.
  • y is arranged, the first data line N1 extends along the second direction y, and is arranged along the first direction x.
  • the first direction x and the second direction y cross each other, so that the gate line L and the first data line N1 cross each other to divide a plurality of pixel units.
  • the first direction x and the second direction y are in a mutually perpendicular relationship, and the first direction x is the direction of the pixel unit row, and the second direction y is the direction of the pixel unit column.
  • the pixel unit of the transparent display device includes: a display area E and a light-transmitting area F.
  • Micro-Light Emitting Diode (Micro-LED) 11 is set in the display area E.
  • Micro-LED is different from ordinary light-emitting diodes.
  • the size of Micro-LED 11 is very small and the brightness is high. Therefore, the application of Micro-LED When used in a transparent display device, a large number of areas can be set as light-transmitting areas to increase the transmittance of the transparent display device.
  • the size of the Micro-LED can be set below 100 ⁇ m, but in practical applications, the specific size of the Micro-LED can also be adjusted according to the overall size of the display device, which is not limited here. For example, when the display device is applied to a 12-inch vehicle-mounted display screen, the size of a pixel unit is about 140 ⁇ m, and the size of the Micro-LED in the pixel unit is 20 ⁇ m-30 ⁇ m.
  • the micro light emitting diode 11 in the transparent display device has multiple colors, including: red micro light emitting diode, green micro light emitting diode and blue micro light emitting diode, adjacent one red micro light emitting diode, one green micro light emitting diode and one blue micro light emitting diode.
  • Miniature light-emitting diodes constitute a pixel.
  • the light-transmitting area F is the area of the pixel unit other than the display area E.
  • the electrochromic device 12 is arranged in the light-transmitting area F.
  • the electrochromic device 12 presents a transparent state when the transparent display device is switched to the transparent display mode. When the device is switched to the normal display mode, it appears black and opaque. In the transparent display mode, the electrochromic device 12 becomes transparent, so that most of the area in each pixel unit can transmit ambient light, which improves the transmittance of the ambient light; in the normal display mode, the electrochromic device 12 becomes pure black, which can greatly increase the contrast of the display, thereby improving the display quality.
  • the transparent display device provided by the embodiment of the present application is further provided with a plurality of second data lines N2.
  • the second data lines N2 extend along the second direction y, are arranged along the first direction x, and are aligned with the first
  • the data lines N1 are alternately arranged, and the second data line N2 is used to provide a signal for the electrochromic device 12, so that the electrochromic device 12 can switch between a transparent state and a black opaque state according to different requirements of the display mode.
  • the pixel unit of the transparent display device provided by the embodiment of the present application further includes: a first thin film transistor 13 and a second thin film transistor 14.
  • the first thin film transistor 13 includes a first gate G1, a first source S1, and a first drain D1.
  • the first gate G1 of the first thin film transistor 13 is connected to the gate line L, the first source S1 is connected to the first data line N1, and the first drain D1 is connected to the micro light emitting diode 11; Under control, the signal voltage of the first data line N1 can be applied to the micro light emitting diode 11, so as to realize the control of the brightness of the micro light emitting diode 11.
  • the second thin film transistor 14 includes a second gate G2, a second source S2, and a second drain D2.
  • the second gate G2 of the second thin film transistor 14 is connected to the gate line L, the second source S2 is connected to the second data line N2, and the second drain D2 is connected to the electrochromic device 12; when the display device is switched to the transparent display mode, The second thin film transistor 14 transmits the first signal loaded by the second data line to the electrochromic device 12 under the control of the signal of the gate line L, so that the electrochromic device 12 is in a transparent state under the control of the first signal; When the display device is switched to the normal display mode, the second thin film transistor 14 transmits the second signal loaded by the second data line to the electrochromic device 12 under the control of the signal of the gate line L, so that the electrochromic device 12 is in Under the control of the second signal, it is in a black opaque state.
  • the electrochromic device 12 becomes transparent, so that most of the area in each pixel unit can transmit ambient light, which improves the transmittance of the ambient light; in the normal display mode, the electrochromic device 12 becomes pure black, which can greatly increase the contrast of the display, thereby improving the display quality.
  • the light-transmitting area F of the transparent display device is located between the first data line N1 and the second data line N2 in the pixel unit, and the electrochromic device 12 covers the entire area of the light-transmitting area F, making it transparent
  • the display device is in the transparent display mode, all the light-transmitting areas F covered by the electrochromic device 12 are in a transparent state, which can increase the transmittance of ambient light; in the normal display mode, the light-transmitting areas covered by the electrochromic device 12 F are all black and opaque, which can increase the contrast of the display to the greatest extent, thereby making the display quality the best.
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of a pixel unit of a transparent display device provided by an embodiment of the application.
  • the pixel unit includes: a base substrate 21 and a driving circuit layer 22.
  • the base substrate 21 is located at the bottom of the display device and has a bearing function.
  • the shape of the base substrate 21 is rectangular or square, including the sky side, the ground side, the left side, and the right side.
  • the sky side is opposite to the ground side
  • the left side is opposite to the right side
  • the sky side is connected to the left side and the right side respectively
  • the ground side is connected to the left side and the right side respectively.
  • the size of the base substrate 21 is adapted to the size of the display device. Generally, the size of the base substrate is slightly smaller than the size of the display device.
  • the base substrate 21 is made of glass and other materials, and the glass needs to be cleaned and dried before being manufactured.
  • the driving circuit layer 22 is located on the base substrate 21, and the driving circuit layer 22 includes driving elements and signal lines for driving the micro light emitting diode to emit light.
  • a thin film transistor (Thin Film Transistor, TFT for short) manufacturing process is used to prepare the driving circuit layer 22.
  • the driving circuit layer 22 is composed of a plurality of metal layers and insulating layers. By patterning the metal layers and insulating layers, a circuit composed of driving elements such as first and second thin film transistors, capacitors, resistors, etc. having a specific connection relationship is formed. After the driving circuit layer 22 is electrically connected to the micro light emitting diode 11 and the electrochromic device 12, the driving circuit layer 22 can provide a driving signal to the micro light emitting diode 11, control the micro light emitting diode 11 to emit light, and provide the electrochromic device 12 The driving signal controls the display state of the electrochromic device 12.
  • the driving circuit layer 22 in the embodiment of the present application includes an exposed first electrode e1 and a second electrode e2.
  • the first electrode e1 is used for electrically connecting the micro light emitting diode 11, and the second electrode e2 is used for electrical Connect the electrochromic device 12.
  • the first electrode e1 is an exposed pad on the array substrate, and the micro light emitting diode 11 is usually welded on the first electrode e1, thereby achieving electrical connection between the two.
  • the first electrode e1 and the second electrode e2 in the embodiment of the present application are made of transparent conductive material indium tin oxide, and there is no contact between the two first electrodes e1 connected to the same micro light emitting diode 11.
  • the patterns of the first electrode e1 and the second electrode e2 are formed by one patterning process.
  • the driving circuit layer 22 includes: a gate metal layer 221, a gate insulating layer 222, an active layer 223, a source-drain metal layer 224 and a flat layer 225.
  • the gate metal layer 221 is located on the base substrate 21.
  • the gate metal layer has a pattern including a first gate G1, a second gate G2 and a gate line.
  • the gate metal layer 221 may be a single layer of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), aluminum (Al), molybdenum (Mo) or chromium (Cr) or Multi-layer metal, or aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy metal layer can also be used.
  • the pattern of the gate metal layer 221 can be formed by a single patterning process.
  • the gate insulating layer 222 is located on the surface of the gate metal layer 221 facing away from the base substrate 21.
  • the gate insulating layer 222 is used to insulate the gate metal layer 221 so that other metal layers can be formed on the gate insulating layer 222.
  • the gate insulating layer 222 may be an inorganic layer of silicon oxide, silicon nitride, or metal oxide, and may include a single layer or multiple layers.
  • the active layer 223 is located on the surface of the gate insulating layer 222 away from the gate metal layer 221.
  • the active layer 223 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions.
  • the region between the source region and the drain region is a channel region a that is not doped.
  • the active layer 223 may be made of materials such as amorphous silicon or polysilicon, and polysilicon may be formed by the crystallization of amorphous silicon.
  • the source-drain metal layer 224 is located on the surface of the active layer 223 facing away from the gate insulating layer 222.
  • the source-drain metal layer 224 has a pattern including a first source S1, a second source S2, a first drain D1, a second drain D2, a first data line, a second data line, and a fixed potential signal line P.
  • the source and drain metal layer 224 may be a single-layer or multi-layer metal of gold (Au), silver (Ag), copper (Cu), or aluminum (Al), or may also be a metal of aluminum (Al): copper (Cu) alloy. Floor.
  • the patterns of the active layer 223 and the source-drain metal layer 224 may be formed by a single patterning process; alternatively, the patterns of the active layer 223 and the source-drain metal layer 224 may also be formed by patterning separately.
  • first gate G1, active layer 223, first source S1 and first drain D1 constitute a first thin film transistor
  • second gate G2, active layer 223, second source S2 and second drain D2 constitutes the second thin film transistor
  • the flat layer 225 is located on the surface of the active layer 223 and the source/drain metal layer 224 away from the gate insulating layer 222.
  • the flat layer 225 is used to insulate the active layer 223 and the source/drain metal layer 224, and at the same time flatten the surface of the film layer, which is beneficial to the formation of other devices on the flat layer 225.
  • the flat layer 225 can be made of SiN X /SiO X and other materials.
  • the flat layer 225 is used to expose the first drain D1, the second drain D2 and the fixed potential signal line P in the source and drain metal layer. Formed by a patterning process, the first electrode e1 is electrically connected to the first drain electrode D1 and the fixed potential signal line P through the via hole of the flat layer 225, and the second electrode e2 is electrically connected to the second drain electrode D2 through the via hole of the flat layer 225. Connected, the fixed potential signal line P can provide potential for the micro light emitting diode 11.
  • FIG. 5 is a schematic diagram of a cross-sectional structure of an electrochromic device provided by an embodiment of the application.
  • the electrochromic device 12 is located on the surface of the driving circuit layer 22 away from the base substrate 21.
  • the electrochromic device 12 specifically includes: a first transparent conductive layer 121; located on the side of the first conductive layer 121 The ion storage layer 122; the ion conductive layer 123 on the side of the ion storage layer 122 away from the first transparent conductive layer 121; the color changing layer 124 on the side of the ion conductive layer 123 away from the ion storage layer 122; and the color changing layer 124 away from the ions
  • the second transparent conductive layer 125 on the side of the conductive layer 123.
  • the material of the color changing layer 124 can be one of viologen compounds, metal phthalocyanine compounds, conductive polymer materials, and electro-acid-base responsive materials, which are not limited herein.
  • the color-changing layer 124 adopts an electro-acid-base responsive material
  • the first transparent conductive layer 121 and the second transparent conductive layer 125 form an electric field after applying an electrical signal, so that the ions in the ion storage layer 122 can be conducted through ions.
  • the layer 123 reaches the color-changing layer 124, so that the acid-base characteristics of the color-changing layer 124 are changed.
  • the color development changes accordingly, so that the electrochromic device 12 is converted from a transparent color. Is black. If a reverse voltage is applied to the electrochromic device 12, the electrochromic device 12 can be converted from black to transparent.
  • the first transparent conductive layer 121 may be disposed on the side close to the driving circuit layer 22; the second transparent conductive layer 125 may also be disposed on the side close to the driving circuit layer 22, where Not limited.
  • the electrochromic device 12 can be formed by a single patterning process.
  • FIG. 6 is a schematic flowchart of a method for driving a transparent display device according to an embodiment of the application.
  • the driving method of the display device includes:
  • the electrochromic device presents a transparent state when the transparent display device is switched to the transparent display mode, and presents a black opaque state when the transparent display device is switched to the normal display mode.
  • the transparent display device when the transparent display device is switched to the transparent display mode, the first signal loaded by the second data line is transmitted to the electrochromic device, so that the electrochromic device is in a transparent state under the control of the first signal; when the display device is switched In the normal display mode, the second signal loaded by the second data line is transmitted to the electrochromic device, so that the electrochromic device is in a black opaque state under the control of the second signal.
  • the electrochromic device becomes transparent, so that most of the area in each pixel unit can transmit ambient light, which improves the transmittance of the ambient light; in the normal display mode, the electrochromic device changes It is pure black, which can greatly increase the contrast of the display, thereby improving the display quality.
  • Micro-LEDs have high transmittance when applied to transparent display devices, and the display image of the transparent display device can be viewed on both sides of the screen.
  • the ambient light can directly illuminate the metal wires included in the display device.
  • the metal wires have a high reflectivity, which will cause glare and other problems, resulting in poor display effects.
  • this application provides the following solutions.
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of a transparent display device provided by an embodiment of the application.
  • the transparent display device includes: a base substrate 11a, a driving circuit layer 12a, a light emitting device 13a, a solar cell device layer 14a, a first insulating layer 15a, and a second insulating gate 16a.
  • the base substrate 11a is located at the bottom of the display device and has a bearing function.
  • the shape of the base substrate 11a is rectangular or square, including the sky side, the ground side, the left side, and the right side.
  • the sky side is opposite to the ground side
  • the left side is opposite to the right side
  • the sky side is connected to the left side and the right side respectively
  • the ground side is connected to the left side and the right side respectively.
  • the size of the base substrate 11a is adapted to the size of the display device. Generally, the size of the base substrate is slightly smaller than the size of the display device.
  • the base substrate 11a is made of glass and other materials, and the glass needs to be cleaned and dried before being manufactured.
  • the driving circuit layer 12a is located on the base substrate 11a, and the driving circuit layer 12a includes driving elements and signal lines for driving the micro light emitting diode to emit light.
  • a thin film transistor (Thin Film Transistor, TFT for short) manufacturing process is used to prepare the driving circuit layer 12a.
  • the driving circuit layer 12a is composed of a plurality of metal layers and insulating layers, and a circuit composed of driving elements such as thin film transistors, capacitors, and resistors having a specific connection relationship is formed by patterning the metal layers and insulating layers. After the driving circuit layer 12a is electrically connected to the light emitting device 13a, the driving circuit layer 12a can provide a driving signal to the light emitting device 13a to control the light emitting device 13a to emit light.
  • the driving circuit layer 12a in the embodiment of the present application includes an exposed connecting electrode e, and the connecting electrode e is used to electrically connect the light emitting device 13a.
  • the connection electrode e is an exposed pad on the array substrate, and the light emitting device 13a is usually soldered to the connection electrode e, thereby achieving electrical connection between the two.
  • the connecting electrode e in the embodiment of the present application is made of indium tin oxide, a transparent conductive material, and there is no contact between the two connecting electrodes e connected to the same light-emitting device 13a.
  • connection electrode e The pattern of the connection electrode e is formed by one patterning process.
  • the light emitting device 13a is located on the driving circuit layer 12a, is electrically connected to the connection electrode e, and serves as a sub-pixel.
  • the light emitting device 13a provided in the embodiment of the present application may be a micro light emitting diode.
  • the micro light emitting diode is different from ordinary light emitting diodes.
  • the size of the micro light emitting diode is very small and the brightness is high. Therefore, the micro light emitting diode is applied to a transparent display device. At this time, a large number of areas can be set as light-transmitting areas to increase the transmittance of the transparent display device.
  • the miniature light-emitting diodes in the transparent display device have a variety of colors, including: red miniature light-emitting diodes, green miniature light-emitting diodes and blue miniature light-emitting diodes, adjacent one red miniature light-emitting diode, one green miniature light-emitting diode and one blue miniature light-emitting diode
  • the light-emitting diode constitutes a pixel.
  • the solar cell device layer 14a is first fabricated, and the solar cell device layer 14a is located above the base substrate.
  • the reflectivity of the solar cell device layer 14a is lower than that of the metal wire.
  • the ambient light is irradiated from the base substrate side to the display device, it first irradiates the solar cell device layer 14a.
  • the solar cell device layer 14a is adjacent to the driving circuit layer.
  • the metal layer of the base substrate has a shielding effect, which can prevent direct ambient light from irradiating the metal wires in the transparent display screen, avoid glare and other problems, thereby improving the display effect of the display device.
  • the driving circuit layer 12a is located on the solar cell device layer 14a.
  • the first insulating layer 15a is arranged between the solar cell device layer 14a and the driving circuit layer 12a to insulate the solar cell device layer 14a.
  • the first insulating layer 15a can be It is an inorganic layer of silicon oxide, silicon nitride, or metal oxide, and has the same size as the base substrate 11a.
  • the second insulating layer 16a is located on the driving circuit layer 12a for protecting the driving circuit layer 12a, and the second insulating layer 16a includes an opening exposing the connection electrode e.
  • the second insulating layer 16a may be made of materials such as resin, and the opening position of the connecting electrode e in the second insulating layer 16a is exposed for welding the light emitting device 13a.
  • the pattern of the opening in the second insulating layer 16a for exposing the position where the connection electrode e of the welding light emitting device 13a is located is formed by one patterning process.
  • the driving circuit layer 12a includes: a gate metal layer 121a, a gate insulating layer 122a, an active layer 123a, a source and drain metal layer 124a, a flat layer 125a, and a connection electrode e.
  • the gate metal layer 121a is located on the base substrate 11a.
  • the gate metal layer has a pattern including a gate G and a gate line.
  • the gate metal layer 121a may be a single layer of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), aluminum (Al), molybdenum (Mo) or chromium (Cr) or Multi-layer metal, or aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy metal layer can also be used.
  • the pattern of the gate metal layer 121a can be formed by a single patterning process.
  • the gate insulating layer 122a is located on the surface of the gate metal layer 121a away from the base substrate 11a.
  • the gate insulating layer 122a is used to insulate the gate metal layer 121a, so that another metal layer can be formed on the gate insulating layer 122a.
  • the gate insulating layer 122a may be an inorganic layer of silicon oxide, silicon nitride, or metal oxide, and may include a single layer or multiple layers.
  • the active layer 123a is located on the surface of the gate insulating layer 122a away from the gate metal layer 121a.
  • the active layer 123a includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions.
  • the region between the source region and the drain region is a channel region a-1 that is not doped.
  • the active layer 123a may be made of materials such as amorphous silicon or polysilicon, and polysilicon may be formed by crystallization of amorphous silicon.
  • the source-drain metal layer 124a is located on the surface of the active layer 123a facing away from the gate insulating layer 122a.
  • the source-drain metal layer 124a has a pattern including a source electrode S, a drain electrode D, a data line, and a fixed potential signal line P-1.
  • the source and drain metal layer 124a may be a single-layer or multi-layer metal of gold (Au), silver (Ag), copper (Cu), or aluminum (Al), or may also be a metal of aluminum (Al): copper (Cu) alloy Floor.
  • the patterns of the active layer 123a and the source-drain metal layer 124a can be formed by a single patterning process; alternatively, the patterns of the active layer 123a and the source-drain metal layer 124a can also be formed by patterning separately.
  • the aforementioned gate G, active layer 123a, source S and drain D constitute a thin film transistor.
  • the flat layer 125a is located on the surface of the active layer 123a and the source/drain metal layer 124a away from the gate insulating layer 122a.
  • the flat layer 125a is used to insulate the active layer 123a and the source/drain metal layer 124a, and at the same time flatten the surface of the film layer, which facilitates the formation of other devices on the flat layer 125a.
  • the planarization layer 125a can be made of SiN X /SiO X and other materials, and the pattern of the via hole in the planarization layer 125a for exposing the drain D in the source/drain metal layer and the fixed potential signal line P-1 is formed by a single patterning process.
  • the connection electrode e is electrically connected to the drain D and the fixed-potential signal line P-1 through the via hole of the flat layer 125a, and the fixed-potential signal line P-1 can provide a potential for the light-emitting unit.
  • the orthographic projection of the solar cell device layer 14a on the base substrate 11a completely covers the orthographic projection of the gate metal layer 121a on the base substrate.
  • the solar cell device layer 14a has a shielding effect on the gate metal layer 121a, which can prevent direct ambient light from irradiating the gate metal layer 121a in the transparent display screen, avoid glare and other problems, thereby improving the display device The display effect.
  • the gate lines S1-1 extend along the direction of the pixel row and are arranged along the direction of the pixel column
  • the data line S2-1 extends along the direction of the pixel column, and the gate line S1-1 and the data line S2-1 cross each other to divide a plurality of pixel units.
  • the pixel unit provided by the embodiment of the present application includes a micro light emitting diode E-1 and a light-transmitting area F-1.
  • the light-transmitting area F-1 is the area of the pixel unit excluding the micro light-emitting diode E-1. Since the pixel unit includes the light-transmitting area F-1, the display device can be a transparent display device. Since the display device is a transparent display device, Therefore, the displayed image can be viewed on both sides of the display device.
  • the solar cell device layer 14a covers the gate line S1-1, because the gate line S1-1 in the metal line of the transparent display device is compared with other metal lines.
  • the width is the largest, and the main cause of glare is the reflection of the grid line S1-1 on the ambient light. Therefore, the solar cell device layer 14a at least covers the grid line S1-1, which can achieve the anti-reflection effect, thereby reducing the grid line S1-1 Problems such as glare caused by reflected ambient light can improve the display effect of the transparent display device.
  • FIG. 9 is the second top view of a pixel unit of a transparent display device provided by an embodiment of the application.
  • the solar cell device layer 14a completely covers the gate line S1-1 and the data line S2-1, and the solar cell device layer 14a completely covers the gate line S1-1 and the data line S2. -1 can achieve the effect of anti-reflection to the greatest extent, thereby avoiding the glare caused by the metal wire reflecting the ambient light to the greatest extent, and improving the display effect of the transparent display device.
  • FIG. 10 is a schematic diagram of a cross-sectional structure of a solar cell device layer provided by an embodiment of this application
  • FIG. 11 is a second schematic diagram of a partial cross-sectional structure of a transparent display device provided by an embodiment of this application.
  • the solar cell device layer 14a is made of a P-I-N type amorphous silicon film. 10 and 11, the solar cell device layer 14a includes a conductive layer 141a, an N-type semiconductor layer 142a, an intrinsic semiconductor layer 143a, and a P-type semiconductor layer 144a.
  • the conductive layer 141a is located on the base substrate 11a, and the material used is transparent conductive material indium tin oxide, and the shape and size are the same as the solar cell device layer 14a.
  • the N-type semiconductor layer 142a is located on the conductive layer 141a, and has the same shape and size as the conductive layer 141a.
  • the reflectivity of the N-type semiconductor layer 142a is lower than that of metal.
  • the N-type semiconductor layer 142a covers the metal line, it can avoid ambient light exposure Metal wires to avoid problems such as glare.
  • the intrinsic semiconductor layer 143a is located on the N-type semiconductor layer 142a, and has the same shape and size as the N-type semiconductor layer 142a.
  • the P-type semiconductor layer 144a is located on the intrinsic semiconductor layer 143a, and has the same shape and size as the intrinsic semiconductor layer 143a.
  • the solar cell device layer 14a can be formed by a single patterning process.
  • FIG. 12 is a third schematic diagram of a partial cross-sectional structure of a transparent display device provided by an embodiment of the application.
  • the transparent display device provided by the embodiment of the present application includes a power module 17a and a terminal 18a.
  • the power module 17a provides power for the transparent display device, and the terminal 18a is used to electrically connect the power module 17a and the conductive layer 141a of the solar cell device layer 14a, so as to realize the electrical connection between the power module 17a of the transparent display device and the solar cell device.
  • the electric energy converted by the solar cell device is applied to the display device.
  • the driving mode of miniature light-emitting diodes can be divided into two types: active and passive.
  • the active driving mode has the advantages of low power consumption, anti-crosstalk, and low driving cost.
  • the current micro light emitting diode drive substrate and the micro light emitting diode are manufactured separately.
  • the driving substrate includes driving elements such as thin film transistors, and the electrodes on the driving substrate for connecting the micro light-emitting diodes are transparent electrodes.
  • the micro light emitting diode has two electrodes, and the electrode of the micro light emitting diode and the transparent electrode are electrically connected by welding. This causes the light emitted by the micro light emitting diode to enter the drive substrate through the transparent electrode, and illuminate the channel region of the thin film transistor through reflection, which affects the performance of the thin film transistor.
  • the active micro light emitting diode panel needs to be fabricated by 5-6 patterning processes. The more patterning times, not only will the cost increase, but also the yield rate will decrease.
  • transparent electrodes are often used as connecting electrodes in the last patterning of liquid crystal panels and OLED panels at this stage. Micro light-emitting diodes are connected to the transparent electrodes, and the emitted light will enter the interior of the panel through the transparent electrodes, which affects the performance of the device.
  • an embodiment of the present application provides a display device to overcome the above-mentioned problems.
  • the following driving schemes are not limited to microLEDs, but can also be applied to miniLEDs.
  • FIG. 13 is a schematic diagram of a cross-sectional structure of a display device provided by an embodiment of the application.
  • the display device provided by the embodiment of the present application includes: a base substrate 11b, a driving circuit layer 12b, a reflective layer 13b, and a micro light emitting diode 14b.
  • the base substrate 11b is located at the bottom of the display device and has a bearing function.
  • the shape of the base substrate 11b is rectangular or square, including the sky side, the ground side, the left side, and the right side.
  • the sky side is opposite to the ground side
  • the left side is opposite to the right side
  • the sky side is connected to the left side and the right side respectively
  • the ground side is connected to the left side and the right side respectively.
  • the size of the base substrate 11b is adapted to the size of the display device. Generally, the size of the base substrate is slightly smaller than the size of the display device.
  • the base substrate 11b is made of glass and other materials, and the glass needs to be cleaned and dried before being manufactured.
  • the driving circuit layer 12b is located on the base substrate 11b, and the driving circuit layer 12b includes driving elements and signal lines for driving the display device to emit light.
  • a thin film transistor (Thin Film Transistor, TFT for short) manufacturing process is used to prepare the driving circuit layer 12b.
  • the driving circuit layer 12b is composed of a plurality of metal layers and insulating layers, and a circuit composed of driving elements such as thin film transistors, capacitors, and resistors having a specific connection relationship is formed by patterning the metal layers and the insulating layers. After the driving circuit layer is electrically connected to the micro light emitting diode, the driving circuit layer can provide a driving signal to the micro light emitting diode to control the micro light emitting diode to emit light.
  • FIG. 14 is a schematic diagram of a cross-sectional structure of a driving circuit layer provided by an embodiment of the application.
  • the driving circuit layer includes a gate metal layer 121b, a gate insulating layer 122b, an active layer 123b, and a source-drain metal layer 124b.
  • the gate metal layer 121b is located on the base substrate 11b.
  • the gate metal layer 121b has a pattern including a gate G-2 and a gate line.
  • the gate metal layer 121b may be a single layer of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), aluminum (Al), molybdenum (Mo) or chromium (Cr) or Multi-layer metal, or aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy metal layer can also be used.
  • the pattern of the gate metal layer 121b can be formed by a single patterning process. Specifically, a metal layer used for the gate is formed on the base substrate 11b; a photoresist layer is formed on the metal layer; a mask is set above the photoresist layer, and the mask is on the gate Areas other than the poles, gate lines and other signal lines have patterns; the photoresist layer is exposed and developed to expose the metal layer other than the required pattern; the exposed metal layer is etched; the remaining photoresist layer is stripped, A pattern of the gate metal layer 121b is formed.
  • the gate insulating layer 122b is located on the surface of the gate metal layer away from the base substrate.
  • the gate insulating layer 122b is used to insulate the gate metal layer 121b, so that other metal layers can be formed on the gate insulating layer.
  • the gate insulating layer 122b may be an inorganic layer of silicon oxide, silicon nitride, or metal oxide, and may include a single layer or multiple layers.
  • the gate insulating layer 122b has a via hole that exposes the signal line in the gate metal layer, so that when another metal layer is formed on the gate insulating layer, the signal lines of the two metal layers can be electrically connected.
  • the pattern of the gate insulating layer 122b can be formed by a single patterning process. Specifically, an insulating layer is formed on the gate metal layer 121b; a photoresist layer is formed on the insulating layer; a mask is set above the photoresist layer, and the mask includes a pattern in the area where the via hole is located. Expose and develop the photoresist layer to expose the insulating layer in the area where the via is located; etch the exposed insulating layer; peel off the remaining photoresist layer to form a pattern of the gate insulating layer 122b.
  • the active layer 123b is located on the surface of the gate insulating layer 122b away from the gate metal layer.
  • the active layer 123b includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions.
  • the region between the source region and the drain region is a channel region a that is not doped.
  • the active layer 123b may be made of materials such as amorphous silicon or polycrystalline silicon, and polycrystalline silicon may be formed by crystallization of amorphous silicon.
  • the source-drain metal layer 124b is located on the surface of the active layer 123b away from the gate insulating layer 122b.
  • the source-drain metal layer 124b has a pattern including a source electrode S-2, a drain electrode D-2, and a data line.
  • the source and drain metal layer 124b may be a single-layer or multi-layer metal of gold (Au), silver (Ag), copper (Cu), or aluminum (Al), or may also be a metal of aluminum (Al): copper (Cu) alloy Floor.
  • the patterns of the active layer 123b and the source-drain metal layer 124b can be formed by a single patterning process. Specifically, a semiconductor layer used for the active layer is formed on the gate insulating layer 122b, a metal layer used for the source and drain is formed on the semiconductor layer; a photoresist layer is formed on the metal layer ; A halftone mask is set above the photoresist layer, the halftone mask includes a completely transparent area, a semi-transmissive area and a light-shielding area, wherein the fully transparent area corresponds to the active layer 123b and the source-drain metal layer 124b There is no patterned area, the semi-transmissive area corresponds to the channel area a-2 of the active layer 123b, and the light-shielded area corresponds to the patterned area of the active layer 123b and the source/drain metal layer 124b; the photoresist layer is exposed to form Fully exposed area, partially exposed area and unexposed area; after the fully exposed area is developed
  • Adhesive layer etch the exposed metal layer and semiconductor layer; ash the photoresist in the partially exposed area, remove the photoresist layer in this area, and etch the metal layer in this area; stripping The remaining photoresist layer forms the pattern of the active layer 123b and the source-drain metal layer 124b.
  • the aforementioned gate G-2, active layer, source S-2 and drain D-2 constitute a thin film transistor.
  • the embodiment of the present application only takes a bottom-gate thin film transistor as an example for specific description.
  • the thin film transistor can also be fabricated as a top-gate structure, and the active layer 123b of the top-gate structure is located on the bottom side of the gate metal layer 121b.
  • the performance of thin film transistors will be affected by light.
  • the active layer exposed between the source S-2 and drain D-2 of the thin film transistor is the channel region of the thin film transistor a-2.
  • the channel region a-2 is sensitive to light. In order to avoid affecting the performance of the thin film transistor, it is necessary to prevent the channel region from being exposed to light.
  • the light-reflecting layer 13b is located on the surface of the driving circuit layer 12b away from the base substrate 11b.
  • the light-reflecting layer 13b is located on the surface of the driving circuit layer 12b, has a protective effect on the driving circuit layer 12b, and also insulates the driving circuit layer 12b.
  • the light-reflecting layer 13b also has the function of reflecting incident light, so when the light emitted by the micro light emitting diode is incident on the surface of the light-reflecting layer 13b, it can be reflected from the light-reflecting layer 13b to the light-emitting side, thereby improving the utilization efficiency of the emitted light.
  • the driving circuit layer further includes a metal connection electrode e-2.
  • the metal connection electrode is used to connect the miniature light-emitting diode, the metal connection electrode e-2 is a part of the metal layer in the driving circuit layer, so that the metal connection electrode e-2 can be directly patterned when the metal layer is formed, and it is no longer necessary to form the connection electrode Frame the picture again. Therefore, the process steps are reduced, which is beneficial to improve the product yield.
  • the light-reflecting layer 13b has a pattern exposing the metal connecting electrode e-2, the pattern of the light-reflecting layer 13b is complementary to the metal connecting electrode e-2, and the metal connecting electrode e-2 is an opaque metal material. Neither the light incident on the metal connecting electrode e-2 nor the light reflecting layer 13b will have the emitted light incident on the driving circuit layer 12b, thereby ensuring that the thin film transistors in the driving circuit layer have stable performance.
  • the reflective layer 13b is made of metal oxide.
  • metal oxides with higher reflectivity such as aluminum oxide or titanium dioxide, can be used. Under normal circumstances, the reflectivity of the reflective layer 13b can reach more than 90%.
  • materials that increase the reflectivity can also be doped to fully reflect the light emitted by the micro LED to the reflective layer 13b.
  • the light-reflecting layer 13b is formed in a region other than the metal connection electrode e-2.
  • a metal layer is formed in the area other than the metal connecting electrode e-2, and the metal layer can be made of metal aluminum or titanium; and then the metal layer is formed by means of oxygen-rich ions such as O 3 , N 2 O, or thermal oxidation. Oxidation forms aluminum oxide or titanium dioxide, thereby forming a light-reflecting layer 13b having a high reflectivity.
  • the micro light emitting diode 14b is welded to the metal connecting electrode e-2.
  • the micro light emitting diode 14b is different from the ordinary light emitting diode, and specifically refers to a micro light emitting diode chip.
  • the size of the micro light emitting diode 14b is generally less than 500 ⁇ m.
  • the micro light emitting diode 14b can be directly used as a display device, and the micro light emitting diode 14b can realize sub-pixel display.
  • the miniature light-emitting diodes can include multiple colors for realizing full-color display.
  • FIG. 15 is the second schematic diagram of the cross-sectional structure of the display device provided by the embodiment of the application.
  • the micro light emitting diode 14b can also be used as a backlight source to provide backlight.
  • a display panel 200 is also provided on the light-emitting side of the micro LED light board.
  • the micro light-emitting diode is beneficial to control the dynamic light emission of the backlight to a smaller subarea, and is beneficial to improve the contrast of the picture.
  • the micro light emitting diode light board may include only one color of micro light emitting diodes, or may include multiple colors of micro light emitting diodes, which is not limited here.
  • the source-drain metal layer 124b further includes: contact pins p, which are connected to signal lines (not shown in the figure) in the source-drain metal layer, and belong to source-drain metal A part of the layer pattern can be formed by the same patterning process as the source electrode S-2, the drain electrode D-2, the data line and the signal line in the source-drain metal layer 124b.
  • the light-reflecting layer 13b is directly formed on the surface of the source-drain metal layer 124b and the active layer 123b away from the gate insulating layer 122b, and the light-reflecting layer 13b has a pattern that exposes a portion of the drain D-2 and the contact pin p, which The drain D-2 and the contact pin p serve as the metal connecting electrode e-2 for connecting the two electrodes of the micro light emitting diode 14b.
  • an insulating layer and a transparent connecting electrode are usually fabricated on the source and drain metal layer 124b.
  • the transparent connecting electrode usually uses indium tin oxide (ITO). Therefore, the ITO and metal overlap structure is often used as the lead in the panel. This will increase the contact resistance, affect the transmission of current, and the overlap will easily affect the yield.
  • ITO indium tin oxide
  • part of the pattern in the source and drain metal layer 124b is directly used as the metal connecting electrode e-2, and there is no need to pattern the subsequent insulating layer and transparent electrode, and the leads are made of metal materials, and there is no ITO and The problem of metal overlap, thereby avoiding the problem of contact resistance and improving yield.
  • the gate metal layer 121b further includes a first signal line s1-2
  • the source and drain metal layer 124b further includes a second signal line s2-2
  • the first signal line s1-2 and the second signal line s2-2 pass
  • the via holes of the gate insulating layer 122b are electrically connected. Arranging the signal lines on different metal layers and electrically connecting them together through vias can improve the conductivity of the signal lines, avoid components in the circuit, and shorten the length of the signal lines.
  • FIG. 16 is a flowchart of a manufacturing method of a display device according to an embodiment of the application.
  • the manufacturing method of the display device includes:
  • the source-drain metal layer includes metal connecting electrodes
  • S50b Weld the miniature light-emitting diode on the metal connecting electrode.
  • the display device can be manufactured after four patterning. Compared with the manufacturing method in the related art, the number of patterning is reduced, which is beneficial to reduce cost and improve product yield.
  • the patterns in the source and drain metal layers are directly used as metal connection electrodes, which can save the process steps of separately forming transparent connection electrodes, simplify the process, and reduce the cost.
  • the problem of high contact resistance formed by the overlapping of the transparent connecting electrode and the metal can be avoided, and the product yield can be improved.
  • the light-reflecting layer is directly formed on the source and drain metal layers, and has a complementary pattern to the metal connecting electrode, and the metal connecting electrode is a opaque metal material, so that after connecting the micro light emitting diode, the light emitted by the micro light emitting diode can be avoided Entering into the driving circuit layer and irradiating the channel of the thin film transistor causes the problem of device performance degradation.
  • a metal layer is formed on the base substrate; a photoresist layer is formed on the metal layer; a mask is set above the photoresist layer Plate, the mask has patterns in areas other than the gate, gate line and other signal lines; Exposes and develops the photoresist layer to expose the metal layer except for the required pattern; etches the exposed metal layer; The remaining photoresist layer is stripped to form a pattern of the gate metal layer.
  • the gate metal layer can be a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), aluminum (Al), molybdenum (Mo) or chromium (Cr) Layer metal, or a metal layer of aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy can also be used.
  • an insulating layer is formed on the gate metal layer; a photoresist layer is formed on the insulating layer; A mask is set on the upper side, and the mask has a pattern in the area where the via hole is located; the photoresist layer is exposed and developed to expose the insulating layer in the area where the via hole is located; the exposed insulating layer is etched; the remaining light is stripped.
  • the resist layer forms the pattern of the gate insulating layer.
  • the gate insulating layer may be an inorganic layer of silicon oxide, silicon nitride, or metal oxide, and may include a single layer or multiple layers.
  • the halftone mask includes a completely transparent area, a semi-transmissive area, and a light-shielding area.
  • the fully transparent area corresponds to The source layer and the source-drain metal layer do not have patterned areas
  • the semi-transmissive area corresponds to the channel area of the active layer
  • the light-shielding area corresponds to the patterned area of the active layer and the source-drain metal layer
  • the photoresist layer is exposed, A fully exposed area, a partially exposed area and an unexposed area are formed; after the fully exposed area is developed, the photoresist is completely removed. After the partially exposed area is developed, there is a thinner photoresist layer. After the unexposed area is developed, there is a thicker photoresist layer.
  • Resist layer etch the exposed metal layer and semiconductor layer; ash the photoresist in the partially exposed area, remove the photoresist layer in this area, and etch the metal layer in this area, The channel region is exposed; the remaining photoresist layer is stripped to form patterns of the active layer and the source and drain metal layers.
  • the active layer can be made of materials such as amorphous silicon or polysilicon, and the source and drain metal layers can be a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu) or aluminum (Al), or can also be used Aluminum (Al): A metal layer of copper (Cu) alloy.
  • the pattern of the reflective layer is formed on the side of the active layer and the source/drain metal layer away from the gate insulating layer, it is formed on the surface of the active layer and the source/drain metal layer away from the gate insulating layer except for the metal connecting electrode.
  • a metal layer; the metal layer is oxidized to form a reflective layer.
  • the above-mentioned metal layer may be aluminum or titanium, and then the metal layer is oxidized to form aluminum oxide or titanium dioxide by means of oxygen-rich ions such as O 3 , N 2 O, or thermal oxidation, thereby forming a light-reflecting layer.
  • the light-reflecting layer replaces the white oil on the surface of the micro-light-emitting diode panel, and has a higher reflectivity.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本申请公开了一种显示装置，包括多个像素单元，像素单元包括：显示区和透光区；在显示区内设置尺寸小、亮度高的微型发光二极管，可以将大量区域设置为透光区；在透光区内设置电致变色器件，其中电致变色器件在透明显示装置切换至透明显示模式时呈现透明状态，在透明显示装置切换为常规显示模式时呈现黑色不透光状态。在透明显示模式下，电致变色器件变为透明，使得每个像素单元中有大部分面积可以透射环境光，提高环境光的透过率；在常规显示模式下，电致变色器件变为纯黑色，可以极大提高显示的对比度，进而改善显示画质。

Description

一种显示装置
相关申请交叉引用
本申请要求于2020年05月22日提交中国专利局、申请号为202010440865.5、申请名称为“一种显示装置及其制作方法”、2020年11月18日提交中国专利局、申请号为202011291216.X、申请名称为“一种透明显示装置”以及2020年10月30日提交中国专利局、申请号为202011187049.4、申请名称为“一种透明显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示装置。
背景技术
微型发光二极管(Micro Light Emitting Diode，简称Micro-LED)技术，即发光二极管(Light Emitting Diode，简称LED)微缩化和矩阵化技术。微型发光二极管显示技术作为新一代显示技术，相比于有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示技术，微型发光二极管显示技术具有更高的发光效率，更高的发光亮度以及更低的功耗。Micro-LED的应用以及相应的驱动方式是行业内的热点问题。
发明内容
本申请一些实施例中提供了一种显示装置，显示装置包括多个像素单元，像素单元包括显示区和透光区，在显示区内设置尺寸小、亮度高的微型发光二极管，可以将大量区域设置为透光区；在透光区内设置电致变色器件，其中电致变色器件在透明显示装置切换至透明显示模式时呈现透明状态，在透明显示装置切换为常规显示模式时呈现黑色不透光状态。在透明显示模式下，电致变色器件变为透明，使得每个像素单元中有大部分面积可以透射环境光，提高环境光的透过率；在常规显示模式下，电致变色器件变为纯黑色，可以极大提高显示的对比度，进而改善显示画质。
本申请一些实施例中提供了一种显示装置，显示装置包括：衬底基板、太阳能电池器件层、第一绝缘层、驱动线路层、发光器件。太阳能电池器件层设置在衬底基板与驱动线路层之间，其中太阳能电池器件层在衬底基板的正投影至少覆盖驱动线路层最靠近衬底基板一侧的金属层在衬底基板的正投影，当设置了太阳能电池器件层之后，环境光从衬底基板一侧照射到透明显示装置时首先照射到太阳能器件层上，太阳能器件层对驱动线路层紧邻着衬底基板的金属层具有遮挡作用，因此避免了环境光照射到金属线而引起的眩光等问题，提高了透明显示装置的显示效果。
本申请一些实施例中提供了一种显示装置，显示装置中的驱动线路层包括金属连接电极，金属连接电极用于连接微型发光二极管，金属连接电极为驱动线路层中金属层的一部分，这样在形成金属层时可以直接构图出金属连接电极，不再需要为了形成连接电极再进行一次构图。由此减少工艺步骤，有利于提高产品良率。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，显而易见地，下面所介绍的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中显示装置的像素单元的俯视结构示意图；
图2为相关技术中透明显示装置的像素单元的俯视结构示意图；
图3为本申请实施例提供的透明显示装置的像素单元的俯视图；
图4为本申请实施例提供的透明显示装置像素单元的局部截面结构示意图；
图5为本申请实施例提供的电致变色器件的截面结构示意图；
图6为本申请实施例提供的透明显示装置驱动方法的流程示意图；
图7为本申请实施例提供的透明显示装置的局部截面结构示意图之一；
图8为本申请实施例提供的透明显示装置像素单元的俯视图之一；
图9为本申请实施例提供的透明显示装置像素单元的俯视图之二；
图10为本申请实施例提供的太阳能电池器件层截面结构示意图；
图11为本申请实施例提供的透明显示装置的局部截面结构示意图之二；
图12为本申请实施例提供的透明显示装置的局部截面结构示意图之三；
图13为本申请实施例提供的显示装置的截面结构示意图之一；
图14为本申请实施例提供的驱动线路层的截面结构示意图；
图15为本申请实施例提供的显示装置的截面结构示意图之二；
图16为本申请实施例提供的显示装置的制作方法的流程图。
具体实施方式
为使本申请的上述目的、特征和优点能够更为明显易懂，下面将结合附图和实施例对本申请做进一步说明。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
随着显示技术的发展，透明显示装置逐渐步入人们的生活，例如透明橱窗、透明交通指示牌、透明手表、透明车载显示等，应用前景广阔。
目前采用的透明显示装置一般是液晶显示(Liquid Crystal Display，简称LCD)或有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示，在像素单元中增加一部分透光区域，以用作透过环境光，实现透明显示。LCD透明显示装置需要背光提供亮度，因此需要较高的开口率，而OLED的发光亮度较低，因此这两种显示方式的像素单元需要尽量大的开口面积，因此会压缩透光区域的面积，使得显示屏透过率很低；且由于显示屏一部分用于透光一部分用于显示，所以显示屏的显示画面存在对比度低，画质清晰度差的问题。
图1为相关技术中显示装置的像素单元的俯视结构示意图。
如图1所示，相关技术中显示装置的栅线L沿着第一方向x延伸，沿着第二方向y进行排列，数据线N沿着第二方向y进行延伸，沿着第一方向x进行排列，栅线L和数据线N相互交叉划分出多个像素单元。
对于液晶显示装置而言，每个像素单元均需要配置彩膜，背光模组出射的光线经过彩膜之后作为相应颜色的子像素，因此每个像素单元均需要尽量高的开口率，开口区域10需要尽量大的面积。
对于有机发光二极管显示装置而言，不需要配置背光模组，采用有机发光二极管作为子像素进行发光，然而有机发光二极管的发光亮度较低，因此每个像素单元同样需要尽量大的开口区域10。
图2为相关技术中透明显示装置的像素单元的俯视结构示意图。
如图2所示，液晶显示装置和有机发光二极管显示装置要实现透明状态，需要在每个像素单元中分割出一部分区域作为透光区F，用于透射环境光。然而在液晶显示装置和有机发光二极管显示装置中，为了驱动像素单元进行发光，像素单元中一半以上区域需要设置驱动电路，本身无法用于透光。因此只能压缩开口区的面积用于透射环境光，而像素单元又需要开口率尽量大，这就使得透明显示装置对环境光的透过率较低，透明显示效果欠佳；当像素单元的开口率被压缩之后显示画面存在对比度低，画质清晰度差的问题。
有鉴于此，本申请实施例提供一种透明显示装置，图3为本申请实施例提供的透明显示装置的像素单元的俯视图。
如图3所示，从透明显示装置的俯视结构上看，透明显示装置包括多条栅线L和多条第一数据线N1，栅线L沿着第一方向x延伸，沿着第二方向y进行排列，第一数据线N1沿着第二方向y进行延伸，沿着第一方向x进行排列。其中，第一方向x和第二方向y相互交叉，从而使得栅线L和第一数据线N1相互交叉划分出多个像素单元。在具体实施时，第一方向x和第二方向y为相互垂直的关系，且第一方向x为像素单元行的方向，第二方向y为像素单元列的方向。
参照图3，本申请实施例提供的透明显示装置的像素单元包括：显示区E和透光区F。
显示区E内设置微型发光二极管(Micro-Light Emitting Diode，简称Micro-LED)11，Micro-LED不同于普通的发光二极管，Micro-LED11的尺寸非常小且亮度较高，因此将Micro-LED应用于透明显示装置中时，可以将大量区域设置为透光区域，提高透明显示装置的透过率。
通常情况下，Micro-LED的尺寸可以设置在100μm以下，但是在实际应用中，也可以根据显示装置的整体尺寸来调整Micro-LED的具体尺寸，在此不做限定。举例来说，当显示装置应用于12寸车载显示屏时，一个像素单元的尺寸大约为140μm左右，像素单元中的Micro-LED的尺寸为20μm-30μm。
透明显示装置中的微型发光二极管11有多种颜色，包括：红色微型发光二极管、绿色微型发光二极管和蓝色微型发光二极管，相邻的一个红色微型发光二极管、一个绿色微型发光二极管和一个蓝色微型发光二极管构成一个像素。
透光区F为像素单元除显示区E以外的区域，在透光区F内设置电致变色器件12，电致变色器件12在透明显示装置切换至透明显示模式时呈现透明状态，在透明显示装置切换为常规显示模式时呈现黑色不透光状态。在透明显示模式的时候，电致变色器件12变为透明，使得每个像素单元中有大部分面积可以透射环境光，提高环境光的透过率；在常 规显示模式的时候，电致变色器件12变为纯黑色，可以极大提高显示的对比度，进而改善显示画质。
参照图3，本申请实施例提供的透明显示装置还设置有多条第二数据线N2，第二数据线N2沿着第二方向y延伸，沿着第一方向x进行排列，并且与第一数据线N1交替排列，第二数据线N2用于为电致变色器件12提供信号，使电致变色器件12根据显示模式的不同需求，在透明状态和黑色不透光状态转换。
如图3所示，本申请实施例提供的透明显示装置的像素单元还包括：第一薄膜晶体管13和第二薄膜晶体管14。
第一薄膜晶体管13包括：第一栅极G1、第一源极S1和第一漏极D1。
第一薄膜晶体管13的第一栅极G1连接栅线L，第一源极S1连接第一数据线N1，第一漏极D1连接微型发光二极管11；第一薄膜晶体管13在栅线L信号的控制下，可以将第一数据线N1的信号电压加载到微型发光二极管11上，从而实现对微型发光二极管11亮度的控制。
第二薄膜晶体管14包括：第二栅极G2、第二源极S2和第二漏极D2。
第二薄膜晶体管14的第二栅极G2连接栅线L，第二源极S2连接第二数据线N2，第二漏极D2连接电致变色器件12；当显示装置切换为透明显示模式时，第二薄膜晶体管14在栅线L的信号的控制下，将第二数据线加载的第一信号传输至电致变色器件12，使电致变色器件12在第一信号的控制下呈透明状态；当显示装置切换为常规显示模式时，第二薄膜晶体管14在栅线L的信号的控制下，将第二数据线加载的第二信号传输至电致变色器件12，使电致变色器件12在第二信号的控制下呈黑色不透光状态。在透明显示模式的时候，电致变色器件12变为透明，使得每个像素单元中有大部分面积可以透射环境光，提高环境光的透过率；在常规显示模式的时候，电致变色器件12变为纯黑色，可以极大提高显示的对比度，进而改善显示画质。
本申请实施例提供的透明显示装置的透光区F位于像素单元中的第一数据线N1和第二数据线N2之间，且电致变色器件12覆盖透光区F的全部区域，使得透明显示装置在透明显示模式时，电致变色器件12覆盖的透光区F全部呈现透明状态，可以提高环境光的透过率；在常规显式模式时，电致变色器件12覆盖的透光区F全部呈黑色不透光状态，可以最大程度的提高显示的对比度，进而使显示画质最优。
图4为本申请实施例提供的透明显示装置像素单元的局部截面结构示意图。
参照图4，从透明显示装置的截面结构来看，像素单元包括：衬底基板21和驱动线路层22。
衬底基板21位于显示装置的底部，具有承载作用。衬底基板21的形状为矩形或方形，包括天侧、地侧、左侧和右侧。其中天侧和地侧相对，左侧和右侧相对，天侧分别与左侧的一端和右侧的一侧相连，地侧分别与左侧的另一端和右侧的另一端相连。
衬底基板21的尺寸与显示装置的尺寸相适应，通常情况下，衬底基板的尺寸略小于显示装置的尺寸。
衬底基板21采用玻璃等材料，在进行制作之前，需要对玻璃进行清洗、烘干等操作。
驱动线路层22位于衬底基板21上，驱动线路层22包括用于驱动微型发光二极管进行发光的驱动元件以及信号线。本申请实施例中，采用薄膜晶体管(Thin Film Transistor，简称TFT)制作工艺来制备驱动线路层22。
驱动线路层22由多个金属层以及绝缘层组成，通过对金属层以及绝缘层进行构图形成具有特定连接关系的第一薄膜晶体管和第二薄膜晶体管、电容以及电阻等驱动元件组成的电路。将驱动线路层22与微型发光二极管11和电致变色器件12电连接之后，可以由驱动线路层22向微型发光二极管11提供驱动信号，控制微型发光二极管11进行发光，向电致变色器件12提供驱动信号，控制电致变色器件12的显示状态。
如图4所示，本申请实施例中的驱动线路层22包括暴露出的第一电极e1和第二电极e2，第一电极e1用于电连接微型发光二极管11，第二电极e2用于电连接电致变色器件12。第一电极e1为阵列基板上暴露的焊盘，微型发光二极管11通常焊接于第一电极e1上，由此实现两者之间的电连接。
具体地，本申请实施例中的第一电极e1和第二电极e2采用透明导电材料氧化铟锡进行制作，且连接同一微型发光二极管11的两个第一电极e1之间不接触。
第一电极e1和第二电极e2的图形采用一次构图工艺形成。
具体地，如图4所示，在本申请实施例中，驱动线路层22包括：栅极金属层221、栅极绝缘层222、有源层223、源漏金属层224和平坦层225。
栅极金属层221位于衬底基板21之上。栅极金属层具有包括第一栅极G1、第二栅极G2和栅线的图形。
栅极金属层221可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、铝(Al)、钼(Mo)或铬(Cr)的单层或多层金属，或者还可以采用铝(Al):钕(Nd)合金、钼(Mo):钨(W)合金的金属层。
栅极金属层221的图形可以采用一次构图工艺形成。
栅极绝缘层222位于栅极金属层221背离衬底基板21一侧的表面。栅极绝缘层222用于对栅极金属层221进行绝缘，从而可以在栅极绝缘层222之上再形成其它金属层。
栅极绝缘层222可以为氧化硅、氮化硅或金属氧化物的无机层，并且可以包括单层或多层。
有源层223位于栅极绝缘层222背离栅极金属层221一侧的表面。有源层223包括通过掺杂N型杂质离子或P型杂质离子而形成的源极区域和漏极区域。在源极区域和漏极区域之间的区域是不进行掺杂的沟道区a。
有源层223可以采用非晶硅或多晶硅等材料进行制作，多晶硅可以通过非晶硅的结晶而形成。
源漏金属层224位于有源层223背离栅极绝缘层222一侧的表面。源漏金属层224具有包括第一源极S1、第二源极S2、第一漏极D1、第二漏极D2、第一数据线、第二数据线和固定电位信号线P的图形。
源漏金属层224可以采用金(Au)、银(Ag)、铜(Cu)或铝(Al)的单层或多层金属，或者还可以采用铝(Al):铜(Cu)合金的金属层。
有源层223和源漏金属层224的图形可以采用一次构图工艺形成；或者，有源层223和源漏金属层224的图形也可以分别进行构图形成。
上述第一栅极G1、有源层223、第一源极S1和第一漏极D1构成第一薄膜晶体管，第二栅极G2、有源层223、第二源极S2和第二漏极D2构成第二薄膜晶体管。
平坦层225位于有源层223和源漏金属层224背离栅极绝缘层222一侧的表面。平坦层225用于对有源层223和源漏金属层224进行绝缘，同时将膜层表面平整化，有利于在 平坦层225之上再形成其它器件。
平坦层225可以采用SiN X/SiO X等材料进行制作，平坦层225中用于暴露源漏金属层中的第一漏极D1、第二漏极D2和固定电位信号线P的过孔的图形采用一次构图工艺形成，第一电极e1通过平坦层225的过孔与第一漏极D1和固定电位信号线P电连接，第二电极e2通过平坦层225的过孔与第二漏极D2电连接，固定电位信号线P可以为微型发光二极管11提供电位。
图5为本申请实施例提供的电致变色器件的截面结构示意图。
参照图4和图5，电致变色器件12位于驱动线路层22背离衬底基板21一侧的表面，电致变色器件12具体包括：第一透明导电层121；位于第一导电层121一侧的离子储存层122；位于离子储存层122背离第一透明导电层121一侧的离子导电层123；位于离子导电层123背离离子储存层122一侧的变色层124；以及位于变色层124远离离子导电层123一侧的第二透明导电层125。
其中，变色层124的材料可以采用紫罗精类化合物、金属酞菁类化合物、导电高分子材料和电致酸碱响应材料中的一种，在此不做限定。
举例来说，当变色层124采用电致酸碱响应材料时，第一透明导电层121和第二透明导电层125在施加电信号之后形成电场，使得离子存储层122中的离子可以通过离子导电层123到达变色层124，从而使变色层124的酸碱特性发生改变，变色层124中的染料在酸碱特性发生变化时显色随之变化，由此使电致变色器件12由透明色转化为黑色。而如果对电致变色器件12施加反向电压，可以使电致变色器件12由黑色再转化为透明。
本申请实施例提供的电致变色器件12可以将第一透明导电层121靠近驱动线路层22的一侧设置；也可以将第二透明导电层125靠近驱动线路层22的一侧设置，在此不做限定。
电致变色器件12可以采用一次构图工艺形成。
本申请实施例的另一方面，提供了一种基于上述透明显示装置的驱动方法。图6为本申请实施例提供的透明显示装置驱动方法的流程示意图。
参照图6，本申请实施例提供的显示装置的驱动方法，包括：
S10、确定透明显示装置的显示模式；
S20、在透明显示装置切换为透明显示模式时，控制电致变色器件切换为透明状态；
S30、在透明显示装置切换为常规显示模式时，控制电致变色器件切换为黑色不透光状态。
电致变色器件在透明显示装置切换至透明显示模式时呈现透明状态，在透明显示装置切换为常规显示模式时呈现黑色不透光状态。
具体地，当透明显示装置切换为透明显示模式时，第二数据线加载的第一信号传输至电致变色器件，使电致变色器件在第一信号的控制下呈透明状态；当显示装置切换为常规显示模式时，将第二数据线加载的第二信号传输至电致变色器件，使电致变色器件在第二信号的控制下呈黑色不透光状态。在透明显示模式的时候，电致变色器件变为透明，使得每个像素单元中有大部分面积可以透射环境光，提高环境光的透过率；在常规显示模式的时候，电致变色器件变为纯黑色，可以极大提高显示的对比度，进而改善显示画质。
Micro-LED应用于透明显示装置的透过率高，在屏幕两侧均可以观看透明显示装置的显示图像。然而在实际显示的时候，环境光可以直接照射显示装置中包含的金属线，金属 线的反射率较高，会造成眩光等问题，从而造成显示效果较差的问题。为了解决上述问题，本申请提供了以下解决方案。
图7为本申请实施例提供的透明显示装置的局部截面结构示意图之一。
参照图7，透明显示装置包括：衬底基板11a、驱动线路层12a、发光器件13a、太阳能电池器件层14a、第一绝缘层15a和第二绝缘栅16a。
衬底基板11a位于显示装置的底部，具有承载作用。衬底基板11a的形状为矩形或方形，包括天侧、地侧、左侧和右侧。其中天侧和地侧相对，左侧和右侧相对，天侧分别与左侧的一端和右侧的一侧相连，地侧分别与左侧的另一端和右侧的另一端相连。
衬底基板11a的尺寸与显示装置的尺寸相适应，通常情况下，衬底基板的尺寸略小于显示装置的尺寸。
衬底基板11a采用玻璃等材料，在进行制作之前，需要对玻璃进行清洗、烘干等操作。
驱动线路层12a位于衬底基板11a上，驱动线路层12a包括用于驱动微型发光二极管进行发光的驱动元件以及信号线。本申请实施例中，采用薄膜晶体管(Thin Film Transistor，简称TFT)制作工艺来制备驱动线路层12a。
驱动线路层12a由多个金属层以及绝缘层组成，通过对金属层以及绝缘层进行构图形成具有特定连接关系的薄膜晶体管、电容以及电阻等驱动元件组成的电路。将驱动线路层12a与发光器件13a电连接之后，可以由驱动线路层12a向发光器件13a提供驱动信号，控制发光器件13a进行发光。
参照图7，本申请实施例中的驱动线路层12a包括暴露出的连接电极e，连接电极e用于电连接发光器件13a。连接电极e为阵列基板上暴露的焊盘，发光器件13a通常焊接于连接电极e上，由此实现两者之间的电连接。
具体地，本申请实施例中的连接电极e采用透明导电材料氧化铟锡进行制作，且连接同一发光器件13a的两个连接电极e之间不接触。
连接电极e的图形采用一次构图工艺形成。
发光器件13a位于驱动线路层12a之上，与连接电极e电连接，作为子像素。
具体地，本申请实施例提供的发光器件13a可以为微型发光二极管，微型发光二极管不同于普通的发光二极管，微型发光二极管尺寸非常小且亮度较高，因此将微型发光二极管应用于透明显示装置中时，可以将大量区域设置为透光区域，提高透明显示装置的透过率。
透明显示装置中的微型发光二极管有多种颜色，包括：红色微型发光二极管、绿色微型发光二极管和蓝色微型发光二极管，相邻的一个红色微型发光二极管、一个绿色微型发光二极管和一个蓝色微型发光二极管构成一个像素。
对于透明显示装置，可以在透明显示装置的两侧进行观看，当在衬底基板一侧观看透明显示装置时，由于金属线紧连着衬底基板，环境光可以直接照射到显示屏的金属线上，由于金属线的反射率较高，会造成眩光等问题，从而造成显示效果较差。
有鉴于此，本申请实施例提供的透明显示装置中，在制作微型发光二极管透明显示装置的驱动线路层前，先制作太阳能电池器件层14a，太阳能电池器件层14a位于衬底基板的上方，由于太阳能电池器件层14a的反射率较金属线的反射率低，环境光从衬底基板一侧照射到显示装置时首先照射到太阳能电池器件层14a上，太阳能电池器件层14a对驱动线路层紧邻着衬底基板的金属层具有遮挡作用，可以避免环境直接光照射到透明显示屏中 的金属线，避免出现眩光等问题，从而提高显示装置的显示效果。
驱动线路层12a位于太阳能电池器件层14a之上，第一绝缘层15a设置在太阳能电池器件层14a与驱动线路层12a之间，用于对太阳能电池器件层14a进行绝缘，第一绝缘层15a可以为氧化硅、氮化硅或金属氧化物的无机层，尺寸大小与衬底基板11a一致。
第二绝缘层16a位于驱动线路层12a之上，用于保护驱动线路层12a，第二绝缘层16a包括暴露连接电极e的开口。在本申请实施例中，第二绝缘层16a可以采用树脂等材料进行制作，第二绝缘层16a中暴露连接电极e的开口位置，用于焊接发光器件13a。
第二绝缘层16a中用于暴露焊接发光器件13a的连接电极e所在的位置的开口的图形采用一次构图工艺形成。
参照图7，在本申请实施例中，驱动线路层12a包括：栅极金属层121a、栅极绝缘层122a、有源层123a、源漏金属层124a、平坦层125a和连接电极e。
栅极金属层121a位于衬底基板11a之上。栅极金属层具有包括栅极G和栅线的图形。
栅极金属层121a可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、铝(Al)、钼(Mo)或铬(Cr)的单层或多层金属，或者还可以采用铝(Al):钕(Nd)合金、钼(Mo):钨(W)合金的金属层。
栅极金属层121a的图形可以采用一次构图工艺形成。
栅极绝缘层122a位于栅极金属层121a背离衬底基板11a一侧的表面。栅极绝缘层122a用于对栅极金属层121a进行绝缘，从而可以在栅极绝缘层122a之上再形成其它金属层。
栅极绝缘层122a可以为氧化硅、氮化硅或金属氧化物的无机层，并且可以包括单层或多层。
有源层123a位于栅极绝缘层122a背离栅极金属层121a一侧的表面。有源层123a包括通过掺杂N型杂质离子或P型杂质离子而形成的源极区域和漏极区域。在源极区域和漏极区域之间的区域是不进行掺杂的沟道区a-1。
有源层123a可以采用非晶硅或多晶硅等材料进行制作，多晶硅可以通过非晶硅的结晶而形成。
源漏金属层124a位于有源层123a背离栅极绝缘层122a一侧的表面。源漏金属层124a具有包括源极S、漏极D、数据线和固定电位信号线P-1的图形。
源漏金属层124a可以采用金(Au)、银(Ag)、铜(Cu)或铝(Al)的单层或多层金属，或者还可以采用铝(Al):铜(Cu)合金的金属层。
有源层123a和源漏金属层124a的图形可以采用一次构图工艺形成；或者，有源层123a和源漏金属层124a的图形也可以分别进行构图形成。
上述栅极G、有源层123a、源极S和漏极D构成薄膜晶体管。
平坦层125a位于有源层123a和源漏金属层124a背离栅极绝缘层122a一侧的表面。平坦层125a用于对有源层123a和源漏金属层124a进行绝缘，同时将膜层表面平整化，有利于在平坦层125a之上再形成其它器件。
平坦层125a可以采用SiN X/SiO X等材料进行制作，平坦层125a中用于暴露源漏金属层中的漏极D和固定电位信号线P-1的过孔的图形采用一次构图工艺形成，连接电极e通过平坦层125a的过孔与漏极D和固定电位信号线P-1电连接，固定电位信号线P-1可以为发光单元提供电位。
如图7所示，太阳能电池器件层14a在衬底基板11a的正投影完全覆盖栅极金属层121a 在衬底基板的正投影，环境光从衬底基板一侧照射到显示装置时首先照射到太阳能电池器件层14a上，太阳能电池器件层14a对栅极金属层121a具有遮挡作用，可以避免环境直接光照射到透明显示屏中的栅极金属层121a，避免出现眩光等问题，从而提高显示装置的显示效果。
图8为本申请实施例提供的透明显示装置像素单元的俯视图之一，从透明显示装置的俯视结构上看，栅线S1-1沿着像素行的方向延伸，沿着像素列的方向进行排列，数据线S2-1沿着像素列的方向进行延伸，栅线S1-1和数据线S2-1相互交叉划分出多个像素单元。
参照图8，本申请实施例提供的像素单元包括微型发光二极管E-1和透光区F-1。
透光区F-1为像素单元除微型发光二极管E-1以外的区域，由于像素单元包括透光区F-1，因此该显示装置可以为透明显示装置，由于该显示装置为透明显示装置，因此在显示装置的两侧均可以观看到显示图像。
如图8所示，本申请实施例提供的透明显示装置中，太阳能电池器件层14a遮盖栅线S1-1，由于透明显示装置的金属线中栅线S1-1相较于其他金属线来说宽度最大，造成的眩光的主要原因是栅线S1-1对环境光的反射，因此太阳能电池器件层14a至少遮盖栅线S1-1，可以达到抗反射的作用，从而减小栅线S1-1反射环境光带来的眩光等问题，提高透明显示装置的显示效果。
图9为本申请实施例提供的透明显示装置像素单元的俯视图之二。
参照图9，在本申请提供的另一实施例中，太阳能电池器件层14a完全遮盖栅线S1-1和数据线S2-1，太阳能电池器件层14a完全遮盖栅线S1-1和数据线S2-1可以最大程度的达到抗反射的作用，进而最大程度避免金属线反射环境光带来的眩光等问题，提高透明显示装置的显示效果。
图10为本申请实施例提供的太阳能电池器件层截面结构示意图；图11为本申请实施例提供的透明显示装置的局部截面结构示意图之二。
太阳能电池器件层14a采用P-I-N型非晶硅薄膜制成。参照图10和图11，太阳能电池器件层14a包括：导电层141a、N型半导体层142a、本征半导体层143a和P型半导体层144a。
导电层141a位于衬底基板11a之上，采用的材料为透明导电材料氧化铟锡，形状大小与太阳能电池器件层14a一致。
N型半导体层142a位于导电层141a之上，形状大小与导电层141a一致，N型半导体层142a的反射率较金属较低，当N型半导体层142a覆盖金属线时，可以避免环境光照射到金属线，从而避免眩光等问题。
本征半导体层143a位于N型半导体层142a之上，形状大小与N型半导体层142a一致。
P型半导体层144a位于本征半导体层143a之上，形状大小与本征半导体层143a一致。
P-I-N型非晶硅薄膜太阳能电池器件的基础工艺在面板产线都可以兼容，因此采用P-I-N型非晶硅薄膜制作太阳能电池器件层，可以在不大幅增加产品成本的基础上，提升产品的功能。
太阳能电池器件层14a可以采用一次构图工艺形成。
图12为本申请实施例提供的透明显示装置的局部截面结构示意图之三。
参照图12，本申请实施例提供的透明显示装置包括电源模块17a和端子18a。
电源模块17a为透明显示装置提供电源，端子18a用于电连接电源模块17a和太阳能电池器件层14a的导电层141a，从而实现透明显示装置的电源模块17a与太阳能电池器件的电连接，这样就可以将太阳能电池器件转化的电能应用于显示装置。
微型发光二极管的驱动方式可以分为有源和无源两种，其中有源驱动模式具有低功耗、抗串扰、驱动成本低等优势。
目前的微型发光二极管驱动基板与微型发光二极管分别制作。驱动基板内包括薄膜晶体管等驱动元件，驱动基板之上用于连接微型发光二极管的电极为透明电极。微型发光二极管具有两个电极，采用焊接的方式将微型发光二极管的电极与透明电极电连接。这就导致微型发光二极管的出射光线会通过透明电极入射到驱动基板内部，通过反射会照射到薄膜晶体管的沟道区，影响薄膜晶体管的性能。
然而现阶段有源微型发光二极管面板需要采用5-6次构图工艺进行制作，构图的次数越多，不仅会造成成本的上升，还会导致良率下降。并且现阶段液晶面板以及OLED面板制程中最后一次构图常采用透明电极作为连接电极，微型发光二极管连接到透明电极上，出射的光线会通过透明电极入射到面板内部，影响器件性能。
有鉴于此，本申请实施例提供一种显示装置，用于克服上述问题。以下驱动方案不限于microLED，也可应用于miniLED。
图13为本申请实施例提供的显示装置的截面结构示意图之一。
参照图13，本申请实施例提供的显示装置包括：衬底基板11b、驱动线路层12b、反光层13b以及微型发光二极管14b。
衬底基板11b位于显示装置的底部，具有承载作用。衬底基板11b的形状为矩形或方形，包括天侧、地侧、左侧和右侧。其中天侧和地侧相对，左侧和右侧相对，天侧分别与左侧的一端和右侧的一侧相连，地侧分别与左侧的另一端和右侧的另一端相连。
衬底基板11b的尺寸与显示装置的尺寸相适应，通常情况下，衬底基板的尺寸略小于显示装置的尺寸。
衬底基板11b采用玻璃等材料，在进行制作之前，需要对玻璃进行清洗、烘干等操作。
驱动线路层12b位于衬底基板11b上，驱动线路层12b包括用于驱动显示器件进行发光的驱动元件以及信号线。本申请实施例中，采用薄膜晶体管(Thin Film Transistor，简称TFT)制作工艺来制备驱动线路层12b。
驱动线路层12b由多个金属层以及绝缘层组成，通过对金属层以及绝缘层进行构图形成具有特定连接关系的薄膜晶体管、电容以及电阻等驱动元件组成的电路。将驱动线路层与微型发光二极管电连接之后，可以由驱动线路层向微型发光二极管提供驱动信号，控制微型发光二极管进行发光。
图14为本申请实施例提供的驱动线路层的截面结构示意图。
参照图14，驱动线路层包括：栅极金属层121b、栅极绝缘层122b、有源层123b和源漏金属层124b。
栅极金属层121b位于衬底基板11b上。栅极金属层121b具有包括栅极G-2以及栅线的图形。
栅极金属层121b可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、铝(Al)、钼(Mo)或铬(Cr)的单层或多层金属，或者还可以采用铝(Al):钕(Nd)合金、钼(Mo):钨(W)合金的金属层。
栅极金属层121b的图形可以采用一次构图工艺形成。具体地，在衬底基板11b上形成一层栅极所采用的金属层；在金属层上形成一层光刻胶层；在光刻胶层的上方设置掩膜板，掩膜板在除栅极、栅线以及其它信号线之外区域具有图形；对光刻胶层进行曝光显影，暴露出除需要图形以外的金属层；对暴露的金属层进行刻蚀；剥离保留的光刻胶层，形成栅极金属层121b的图形。
栅极绝缘层122b位于栅极金属层背离衬底基板一侧的表面。栅极绝缘层122b用于对栅极金属层121b进行绝缘，从而可以在栅极绝缘层之上再形成其它金属层。
栅极绝缘层122b可以为氧化硅、氮化硅或金属氧化物的无机层，并且可以包括单层或多层。
栅极绝缘层122b具有包括暴露栅极金属层中信号线的过孔，从而在栅极绝缘层之上再形成其它金属层时，可以使两个金属层的信号线电连接。
栅极绝缘层122b的图形可以采用一次构图工艺形成。具体地，在栅极金属层121b上形成一层绝缘层；在绝缘层上形成一层光刻胶层；在光刻胶层的上方设置掩膜板，掩膜板包括过孔所在区域具有图形；对光刻胶层进行曝光显影，暴露出过孔所在区域的绝缘层；对暴露的绝缘层进行刻蚀；剥离保留的光刻胶层，形成栅极绝缘层122b的图形。
有源层123b位于栅极绝缘层122b背离栅极金属层一侧的表面。有源层123b包括通过掺杂N型杂质离子或P型杂质离子而形成的源极区域和漏极区域。在源极区域和漏极区域之间的区域是不进行掺杂的沟道区a。
有源层123b可以采用非晶硅或多晶硅等材料进行制作，多晶硅可以通过非晶硅的结晶而形成。
源漏金属层124b位于有源层123b背离栅极绝缘层122b一侧的表面。源漏金属层124b具有包括源极S-2、漏极D-2和数据线的图形。
源漏金属层124b可以采用金(Au)、银(Ag)、铜(Cu)或铝(Al)的单层或多层金属，或者还可以采用铝(Al):铜(Cu)合金的金属层。
有源层123b和源漏金属层124b的图形可以采用一次构图工艺形成。具体地，在栅极绝缘层122b上形成一层有源层采用的半导体层，在半导体层上形成一层源极和漏极所采用的金属层；在金属层上形成一层光刻胶层；在光刻胶层的上方设置半色调掩膜板，半色调掩膜板包括完全透光区、半透光区以及遮光区，其中完全透光区对应有源层123b和源漏金属层124b不存在图形的区域，半透光区对应有源层123b的沟道区a-2，遮光区对应有源层123b和源漏金属层124b具有图形的区域；对光刻胶层进行曝光，形成完全曝光区、部分曝光区和未曝光区；完全曝光区显影之后光刻胶全部去除，部分曝光区显影之后存在厚度较薄的光刻胶层，未曝光区显影之后存在厚度较厚的光刻胶层；对暴露的金属层和半导体层进行刻蚀；对部分曝光区内的光刻胶进行灰化处理，去除此区域的光刻胶层，并将此区域的金属层进刻蚀；剥离保留的光刻胶层，形成有源层123b和源漏金属层124b的图形。
其中，上述栅极G-2、有源层、源极S-2和漏极D-2构成薄膜晶体管。本申请实施例仅以底栅型薄膜晶体管为例进行具体说明，在具体应用时，薄膜晶体管还可以制作为顶栅结构，顶栅结构的有源层123b位于栅极金属层121b的底侧。
薄膜晶体管作为驱动线路层中重要的驱动元件，其性能将受到光照的影响，其中，薄膜晶体管的源极S-2和漏极D-2之间暴露的有源层为薄膜晶体管的沟道区a-2。沟道区a-2 对光照敏感，为了避免影响薄膜晶体管的性能，需要避免沟道区受到光照。
反光层13b位于驱动线路层12b背离衬底基板11b一侧的表面。反光层13b位于驱动线路层12b的表面，对驱动线路层12b具有保护作用，同时还对驱动线路层12b进行绝缘。反光层13b还具有对入射光线进行反射的作用，那么微型发光二极管的出射光入射到反光层13b的表面时，可以由反光层13b向出光一侧反射，由此提高出射光的利用效率。
参照图14，在本申请实施例中，驱动线路层还包括金属连接电极e-2。金属连接电极用于连接微型发光二极管，金属连接电极e-2为驱动线路层中金属层的一部分，这样在形成金属层时可以直接构图出金属连接电极e-2，不再需要为了形成连接电极再进行一次构图。由此减少工艺步骤，有利于提高产品良率。
反光层13b具有暴露金属连接电极e-2的图形，反光层13b的图形与金属连接电极e-2互补，而金属连接电极e-2为不透光的金属材料，那么无论微型发光二极管出射的光线入射到金属连接电极e-2还是反光层13b都不会有出射光入射到驱动线路层12b中，由此可以保证驱动线路层中的薄膜晶体管具有稳定的性能。
反光层13b采用金属氧化物进行制作。在本申请实施例中，可以采用氧化铝或二氧化钛等具有较高反射率的金属氧化物。通常情况下反光层13b的反射率可以达到90％以上，为了提高反光层13b的反射率，还可以掺杂增加反射率的材料，由此充分反射微型发光二极管出射到反光层13b的光线。
反光层13b形成在除金属连接电极e-2以外的区域。具体地，在除金属连接电极e-2以外的区域形成一层金属层，该金属层可以采用金属铝或钛；再通过O 3、N 2O等富氧离子或者热氧化的方式将金属层氧化形成氧化铝或二氧化钛，由此形成具有高反射率的反光层13b。
微型发光二极管14b焊接于金属连接电极e-2上。微型发光二极管14b不同于普通的发光二极管，其具体指的是微型发光二极管芯片。微型发光二极管14b的尺寸一般小于500μm。
由于微型发光二极管14b的尺寸很小，在本申请实施例中，可以直接利用微型发光二极管14b作为显示器件，由微型发光二极管14b实现子像素的显示。微型发光二极管可以包括多种颜色，用于实现全彩显示。
图15为本申请实施例提供的显示装置的截面结构示意图之二。
参照图15，本申请另一实施例中，还可以利用微型发光二极管14b作为背光源，用于提供背光。此时，在微型发光二极管灯板的出光侧还设置有显示面板200。
微型发光二极管作为背光源，有利于将背光的动态发光控制到更小的分区，有利于提高画面的对比度。微型发光二极管灯板可以只包括一种颜色的微型发光二极管，也可以包括多种颜色的微型发光二极管，在此不做限定。
在本申请实施例中，参照图14，源漏金属层124b还包括：接触引脚p，接触引脚与源漏金属层中的信号线(图中未示出)连接，且属于源漏金属层构图的一部分，可以与源漏金属层124b中的源极S-2、漏极D-2、数据线以及信号线采用同一次构图工艺形成。
反光层13b直接形成在源漏金属层124b和有源层123b背离栅极绝缘层122b一侧的表面，且反光层13b具有暴露部分漏极D-2和接触引脚p的图形，暴露出的漏极D-2以及接触引脚p即作为金属连接电极e-2，用于连接微型发光二极管14b的两个电极。
在相关技术中，通常会在源漏金属层124b之上再制作绝缘层以及透明连接电极，透 明连接电极通常采用氧化铟锡(ITO)，因此面板中常采用ITO与金属搭接的结构作为引线，这将会增大接触电阻，影响电流的传输，且搭接还容易影响良率。
而在本申请实施例中，直接采用源漏金属层124b中的部分图形作为金属连接电极e-2，不需要进行后续绝缘层以及透明电极的构图，且引线均采用金属材料，不存在ITO与金属进行搭接的问题，由此避免了接触电阻的问题，提高良率。
参照图14，栅极金属层121b还包括第一信号线s1-2，源漏金属层124b还包括第二信号线s2-2，第一信号线s1-2和第二信号线s2-2通过栅极绝缘层122b的过孔电连接。将信号线设置在不同的金属层，并通过过孔将其电连接在一起，可以提高信号线的导电性，可以对电路中元件进行避让，缩短信号线的长度。
图16为本申请实施例提供的显示装置的制作方法的流程图。
参照图16，显示装置的制作方法包括：
S10b、在衬底基板上形成栅极金属层的图形；
S20b、在栅极金属层背离衬底基板的一侧形成栅极绝缘层的图形；
S30b、在栅极绝缘层背离栅极金属层的一侧形成有源层和源漏金属层的图形；源漏金属层包括金属连接电极；
S40b、在有源层和源漏金属层背离栅极绝缘层的一侧形成反光层的图形；
S50b、在金属连接电极上焊接微型发光二极管。
采用本申请实施例提供的上述制作方法，经过四次构图可以制备完成显示装置，相比于相关技术中的制作方法，减少了构图次数，有利于降低成本，提高产品良率。
采用源漏金属层中的图形直接作为金属连接电极，可以省去单独形成透明连接电极的工艺步骤，简化流程，降低成本。并且还可以避免透明连接电极与金属搭接形成的接触电阻高等问题，提升产品良率。
反光层直接形成在源漏金属层之上，与金属连接电极具有互补的图形，而金属连接电极为不透光的金属材料，由此在连接微型发光二极管之后，可以避免微型发光二极管出射的光线进入到驱动线路层中，照射到薄膜晶体管的沟道造成器件性能下降的问题。
具体地，在衬底基板上形成栅极金属层的图形时，在衬底基板上形成一层金属层；在金属层上形成一层光刻胶层；在光刻胶层的上方设置掩膜板，掩膜板在除栅极、栅线以及其它信号线之外区域具有图形；对光刻胶层进行曝光显影，暴露出除需要图形以外的金属层；对暴露的金属层进行刻蚀；剥离保留的光刻胶层，形成栅极金属层的图形。
栅极金属层可以采用金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、铝(Al)、钼(Mo)或铬(Cr)的单层或多层金属，或者还可以采用铝(Al):钕(Nd)合金、钼(Mo):钨(W)合金的金属层。
在栅极金属层背离衬底基板的一侧形成栅极绝缘层的图形时，在栅极金属层上形成一层绝缘层；在绝缘层上形成一层光刻胶层；在光刻胶层的上方设置掩膜板，掩膜板在过孔所在区域具有图形；对光刻胶层进行曝光显影，暴露出过孔所在区域的绝缘层；对暴露的绝缘层进行刻蚀；剥离保留的光刻胶层，形成栅极绝缘层的图形。
栅极绝缘层可以为氧化硅、氮化硅或金属氧化物的无机层，并且可以包括单层或多层。
在栅极绝缘层背离栅极金属层的一侧形成有源层和源漏金属层的图形时，在栅极绝缘层上形成一层半导体层，在半导体层上形成一层金属层；在金属层上形成一层光刻胶层；在光刻胶层的上方设置半色调掩膜板，半色调掩膜板包括完全透光区、半透光区以及遮光区，其中完全透光区对应有源层和源漏金属层不存在图形的区域，半透光区对应有源层的 沟道区，遮光区对应有源层和源漏金属层具有图形的区域；对光刻胶层进行曝光，形成完全曝光区、部分曝光区和未曝光区；完全曝光区显影之后光刻胶全部去除，部分曝光区显影之后存在厚度较薄的光刻胶层，未曝光区显影之后存在厚度较厚的光刻胶层；对暴露的金属层和半导体层进行刻蚀；对部分曝光区内的光刻胶进行灰化处理，去除此区域的光刻胶层，并将此区域的金属层进刻蚀，暴露沟道区；剥离保留的光刻胶层，形成有源层和源漏金属层的图形。
有源层可以采用非晶硅或多晶硅等材料，源漏金属层可以采用金(Au)、银(Ag)、铜(Cu)或铝(Al)的单层或多层金属，或者还可以采用铝(Al):铜(Cu)合金的金属层。
在有源层和源漏金属层背离栅极绝缘层的一侧形成反光层的图形时，在有源层和源漏金属层背离栅极绝缘层一侧的表面除金属连接电极以外的区域形成一层金属层；对金属层进行氧化处理，形成反光层。
上述金属层可以采用铝或钛，再通过O 3、N 2O等富氧离子或者热氧化的方式将金属层氧化形成氧化铝或二氧化钛，由此形成反光层。该反光层代替微型发光二极管面板表面的白油，具有较高的反射率。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

  1. 一种显示装置，其特征在于，包括：
    多个像素单元，所述像素单元包括显示区和透光区；
    所述显示区内设置有微型发光二极管，所述透光区内设置有电致变色器件；所述电致变色器件在所述透明显示装置切换至透明显示模式时呈现透明状态，在所述透明显示装置切换为常规显示模式时呈现黑色不透光状态。
  2. 如权利要求1所述的显示装置，其特征在于，还包括多条栅线和多条第一数据线；所述栅线沿第一方向延伸，沿第二方向排列；所述第一数据线沿第二方向延伸，沿第一方向排列；所述第一方向和所述第二方向交叉；所述栅线和所述第一数据线划分出所述像素单元；
    所述像素单元还包括：
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接所述栅线，所述第一薄膜晶体管的源极连接所述第一数据线，所述第一薄膜晶体管的漏极连接所述微型发光二极管；所述第一薄膜晶体管在所述栅线的信号的控制下，将所述第一数据线的信号传输至所述微型发光二极管。
  3. 如权利要求2所述的显示装置，其特征在于，还包括多条第二数据线；所述第二数据线沿所述第二方向延伸，沿所述第一方向排列；所述第一数据线和所述第二数据线沿所述第一方向交替排列；
    所述像素单元还包括：
    第二薄膜晶体管，所述第二薄膜晶体管的栅极连接所述栅线接，所述第二薄膜晶体管的源极连接所述第二数据线，所述第二薄膜晶体管的漏极连接所述电致变色器件；所述第二薄膜晶体管在所述栅线的信号的控制下，将所述第二数据线的信号传输至所述电致变色器件。
  4. 如权利要求3所述的显示装置，其特征在于，所述透光区位于所述像素单元中的所述第一数据线和所述第二数据线之间，所述电致变色器件覆盖所述透光区的全部区域。
  5. 如权利要求1所述的显示装置，其特征在于，所述像素单元包括：
    衬底基板，具有支撑和承载作用；
    驱动线路层，位于所述衬底基板的一侧，用于提供驱动信号；所述驱动线路层包括所述第一薄膜晶体管、所述第二薄膜晶体管、暴露出的多个第一电极和第二电极；所述微型发光二极管连接所述第一电极，所述电致变色器件连接所述第二电极。
  6. 如权利要求5所述的显示装置，其特征在于，所述驱动线路层包括：
    栅极金属层，位于所述衬底基板的一侧的表面；所述栅极金属层包括第一栅极、第二栅极和栅线；
    栅极绝缘层，位于所述栅极金属层背离所述衬底基板一侧的表面；
    有源层，位于所述栅极绝缘层背离所述栅极金属层一侧的表面；
    源漏金属层，位于所述有源层背离所述栅极绝缘层一侧的表面；所述源漏金属层包括第一源极、第一漏极、第二源极、第二漏极、第一数据线和第二数据线；
    平坦层，位于所述有源层和所述源漏金属层背离所述栅极绝缘层一侧的表面；所述平坦层包括用于暴露所述第一漏极和所述第二漏极的过孔，所述第一电极通过所述平坦层的 过孔与所述第一漏极电连接，所述第二电极通过所述平坦层的过孔与所述第二漏极电连接；
    所述第一栅极、所述有源层、所述第一源极和所述第一漏极构成所述第一薄膜晶体管；所述第二栅极、所述有源层、所述第二源极和所述第二漏极构成所述第二薄膜晶体管。
  7. 如权利要求5所述的显示装置，其特征在于，所述电致变色器件包括：
    第一透明导电层；
    离子储存层，位于所述第一导电层的一侧；
    离子导电层，位于所述离子储存层背离所述第一透明导电层的一侧；
    变色层，位于所述离子导电层背离所述离子储存层的一侧；
    第二透明导电层，位于所述变色层远离所述离子导电层的一侧；
    所述第一透明导电层靠近所述驱动线路层一侧设置；或者，所述第二透明导电层靠近所述驱动线路层一侧设置。
  8. 如权利要求7所述的显示装置，其特征在于，所述变色层的材料采用紫罗精类化合物、金属酞菁类化合物、导电高分子材料和电致酸碱响应材料中的一种。
  9. 一种显示装置，其特征在于，包括：
    衬底基板，具有支撑和承载作用；
    太阳能电池器件层，位于所述衬底基板的一侧；
    第一绝缘层，位于所述太阳能电池器件层远离所述衬底基板的一侧；
    驱动线路层，位于所述第一绝缘层远离所述衬底基板的一侧；所述驱动线路层包括多个连接电极；
    发光器件，位于所述驱动线路层背离所述第一绝缘层的一侧，所述发光器件与所述连接电极电连接；
    所述太阳能电池器件层在所述衬底基板的正投影至少覆盖所述驱动线路层最靠近所述衬底基板一侧的金属层在所述衬底基板的正投影。
  10. 一种显示装置，其特征在于，包括：
    衬底基板，具有承载作用；
    驱动线路层，位于所述衬底基板上，用于提供驱动信号；所述驱动线路层包括金属连接电极；
    反光层，位于所述驱动线路层背离所述衬底基板一侧的表面；所述反光层具有暴露所述金属连接电极的图形；
    微型发光二极管，焊接于所述金属连接电极上。
PCT/CN2021/095253 2020-05-22 2021-05-21 一种显示装置 WO2021233437A1 (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN202010440865.5 2020-05-22
CN202010440865.5A CN113707669A (zh) 2020-05-22 2020-05-22 一种显示装置及其制作方法
CN202011187049.4A CN114446186A (zh) 2020-10-30 2020-10-30 一种透明显示装置
CN202011187049.4 2020-10-30
CN202011291216.XA CN114519962B (zh) 2020-11-18 2020-11-18 一种透明显示装置
CN202011291216.X 2020-11-18

Publications (1)

Publication Number Publication Date
WO2021233437A1 true WO2021233437A1 (zh) 2021-11-25

Family

ID=78707720

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/095253 WO2021233437A1 (zh) 2020-05-22 2021-05-21 一种显示装置

Country Status (1)

Country Link
WO (1) WO2021233437A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114740667A (zh) * 2022-04-22 2022-07-12 湖北长江新型显示产业创新中心有限公司 一种显示模组和显示装置
CN114882851A (zh) * 2022-05-16 2022-08-09 京东方科技集团股份有限公司 一种透明显示面板、其驱动方法及显示装置
CN114975537A (zh) * 2022-04-25 2022-08-30 上海天马微电子有限公司 一种显示面板、显示装置及显示面板的控制方法
CN115167020A (zh) * 2022-07-27 2022-10-11 京东方科技集团股份有限公司 一种显示面板及显示装置
WO2023216145A1 (zh) * 2022-05-11 2023-11-16 北京奕斯伟计算技术股份有限公司 显示面板及其显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107680989A (zh) * 2017-07-26 2018-02-09 友达光电股份有限公司 双面显示器及其制造方法
CN110112140A (zh) * 2019-04-22 2019-08-09 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法
CN111063693A (zh) * 2019-12-05 2020-04-24 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107680989A (zh) * 2017-07-26 2018-02-09 友达光电股份有限公司 双面显示器及其制造方法
CN110112140A (zh) * 2019-04-22 2019-08-09 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法
CN111063693A (zh) * 2019-12-05 2020-04-24 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114740667A (zh) * 2022-04-22 2022-07-12 湖北长江新型显示产业创新中心有限公司 一种显示模组和显示装置
CN114740667B (zh) * 2022-04-22 2023-11-07 湖北长江新型显示产业创新中心有限公司 一种显示模组和显示装置
CN114975537A (zh) * 2022-04-25 2022-08-30 上海天马微电子有限公司 一种显示面板、显示装置及显示面板的控制方法
WO2023216145A1 (zh) * 2022-05-11 2023-11-16 北京奕斯伟计算技术股份有限公司 显示面板及其显示装置
CN114882851A (zh) * 2022-05-16 2022-08-09 京东方科技集团股份有限公司 一种透明显示面板、其驱动方法及显示装置
CN115167020A (zh) * 2022-07-27 2022-10-11 京东方科技集团股份有限公司 一种显示面板及显示装置
CN115167020B (zh) * 2022-07-27 2023-10-20 京东方科技集团股份有限公司 一种显示面板及显示装置

Similar Documents

Publication Publication Date Title
WO2021233437A1 (zh) 一种显示装置
US10338443B2 (en) Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same
US6515428B1 (en) Pixel structure an organic light-emitting diode display device and its manufacturing method
US7164230B2 (en) Dual panel-type organic electroluminescent display device and method for fabricating the same
JP5220918B2 (ja) 表示装置
US20060208275A1 (en) Transflective liquid crystal display panel and manufacturing method thereof
CN101226948B (zh) 显示器及其制造方法
US7499120B2 (en) Liquid crystal display pixel structure and method for manufacturing the same
KR20090050765A (ko) 유기 발광 표시 장치 및 그 제조 방법
JP2005528641A (ja) 液晶表示装置用薄膜トランジスタアレイ基板
US20240168328A1 (en) Hybrid display device and spliced display device
US11482592B2 (en) Substrate and manufacturing method thereof and electronic device
CN113097269B (zh) 一种显示面板及显示装置
CN114519962B (zh) 一种透明显示装置
KR100567272B1 (ko) 듀얼패널타입 유기전계발광 소자 및 그 제조방법
CN113707669A (zh) 一种显示装置及其制作方法
CN215340637U (zh) 显示基板、彩膜基板、显示面板和显示装置
US11281046B2 (en) Backlight module, manufacturing method thereof, and display device
US20220392990A1 (en) Display device
CN114913782A (zh) 一种显示装置
CN115911052A (zh) 一种显示装置及其显示方法
CN114594632A (zh) 液晶显示装置及其制作方法
CN114446186A (zh) 一种透明显示装置
CN115248516A (zh) 显示基板、彩膜基板、显示面板和显示装置
KR20210113511A (ko) 표시 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21808943

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21808943

Country of ref document: EP

Kind code of ref document: A1