WO2021232579A1 - 一种可控压摆率n型mos高边驱动电路 - Google Patents

一种可控压摆率n型mos高边驱动电路 Download PDF

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Publication number
WO2021232579A1
WO2021232579A1 PCT/CN2020/103960 CN2020103960W WO2021232579A1 WO 2021232579 A1 WO2021232579 A1 WO 2021232579A1 CN 2020103960 W CN2020103960 W CN 2020103960W WO 2021232579 A1 WO2021232579 A1 WO 2021232579A1
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field effect
effect transistor
electrically connected
gate
drain
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PCT/CN2020/103960
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English (en)
French (fr)
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王飞
王云
郑鲲鲲
郝炳贤
任广辉
薛静
王桂磊
阿达姆松·亨利·H
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广东省大湾区集成电路与系统应用研究院
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Publication of WO2021232579A1 publication Critical patent/WO2021232579A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

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  • the invention relates to a drive circuit, in particular to a controllable slew rate N-type MOS high-side drive circuit, which belongs to the technical field of drive circuits.
  • the N-type MOS high-side load is an inductive load
  • the source of the MOS switch will be pulled to a voltage lower than ground by the load due to the freewheeling of the inductance.
  • it is as low as -20V
  • the drive circuit in order to prevent the PN junction of the MOS switch's drive circuit from conducting to the substrate, the drive circuit must use an isolation structure device.
  • N-type MOS isolation devices are provided for negative pressure applications. For this reason, a controllable slew rate full N-type MOS high-side drive circuit is designed to solve the above-mentioned problems.
  • the main purpose of the present invention is to provide a controllable slew rate N-type MOS high-side drive circuit, which uses a controllable current to charge and discharge the gate of the switch. When the charge and discharge are completed, the gate is strongly opened or closed.
  • all MNx are NMOS devices isolated from the substrate, M0 is a high-side N-type MOS switch that needs to be driven, M1 is an ordinary high-voltage N-type MOS, without substrate isolation, and VHIGH is the power supply for the drive.
  • the leftmost MN0-MN3 provides a bias circuit, M1 is a source follower structure, which limits the charging voltage of the M0 grid, and realizes the functions of high-side driving and controllable slew rate.
  • a controllable slew rate N-type MOS high-side drive circuit includes four groups of first field effect transistor components in which drains and sources are connected in series and connected with their own drains and gates.
  • the first field effect transistor components It includes field effect transistors MN3, MN2, MN1, and MN0.
  • the drain of the field effect transistor MN3 is connected to the bias current, and the source of the field effect transistor MN0 is connected to the source of MN4 and connected to OFF.
  • the gate of the field effect transistor MN0 is connected to the gate of the field effect transistor MN4, the drain of the field effect transistor MN4 is connected to the OFF Control circuit component, and the OFF Control circuit component is connected
  • the ON Control circuit component is connected to the gate of the field effect transistor MO, the source of the field effect transistor MO is connected to the output terminal DRAIN, the drain of the field effect transistor MO is connected to the external output terminal SOURCE, the ON Control circuit component
  • the power supply is connected, the ON Control circuit component is also connected to the source of the field effect transistor M1, and the drain of the field effect transistor M1 is connected to the power supply.
  • the drain of the field effect transistor MN3 in the first field effect transistor component is connected to the source of the field effect transistor MN2
  • the drain of the field effect transistor MN2 is connected to the source of the field effect transistor MN1
  • the drain of the field effect transistor MN1 The electrode is connected to the source of the field effect transistor MN0.
  • the OFF The Control circuit assembly includes seven groups of field effect transistors, which are field effect transistors MN10, MN11, MN12, MN13, MN14, MN15, and MN16.
  • the sources of the field effect transistors MN10, MN11, MN12, and MN16 are connected to each other.
  • the transistors MN10, MN13, and MN14 are connected to the bias current, and the field effect transistor MN10 is connected to the gate of the field effect transistor MN11.
  • the drain of the field effect transistor MN11 is connected to the gate of the field effect transistor MN12
  • the source of the field effect transistor MN13 is connected to the drain of the field effect transistor MN12
  • the field effect transistor The gate of MN13 is connected to the gate of the field effect transistor MN14 and to the drain of the field effect transistor MN4 and the gates of the field effect transistors MN16 and MN15.
  • the ON The Control circuit component includes field effect transistors MN4, MN5, MN6, MN9, MN8, and MN7, the sources of the field effect transistors MN4, MN5, MN6, and MN9 are connected to each other, and the drains of the field effect transistors MN4, MN7, and MN9 Connect the bias current.
  • the gate of the field effect transistor MN4 is connected to the gate of the field effect transistor MN5, and the drain of the field effect transistor MN4 is connected to the gate of the field effect transistor MN4, and the gate of the field effect transistor MN6
  • the electrode is connected to the source of the field effect transistor MN5, the source of the field effect transistor MN7 is electrically connected to the drain of the field effect transistor MN6, and the gate of the field effect transistor MN7 is connected to the field effect transistor MN8. Grid connection.
  • the drain of the field effect transistor MN8 is connected to the source of the field effect transistor M1, and the gate of the MN3 is connected to the gate of the field effect transistor M1.
  • the drain of the field effect transistor MN9 is connected to the gate of the field effect transistor MO.
  • the present invention provides a controllable slew rate N-type MOS high-side driving circuit, which uses a controllable current to charge and discharge the gate of the switch. When the charge and discharge are completed, the gate is forced to be opened or closed to prevent the gate from being damaged. Voltage disturbance, all MNx are NMOS devices isolated from the substrate, M0 is the high-side N-type MOS switch that needs to be driven, and VHIGH is the power supply for the drive. The leftmost MN0-MN3 provides a bias circuit, M1 is a source follower structure, which limits the charging voltage of the M0 grid, and realizes the functions of high-side driving and controllable slew rate.
  • Fig. 1 is an overall circuit diagram of a preferred embodiment of a controllable slew rate N-type MOS high-side drive circuit according to the present invention
  • FIG. 2 is a circuit diagram of an ON Control circuit component of a preferred embodiment of a controllable slew rate N-type MOS high-side drive circuit according to the present invention
  • FIG. 3 is a waveform diagram of the current value comparison between Iin1 and Iin2 of a preferred embodiment of a controllable slew rate N-type MOS high-side drive circuit according to the present invention
  • FIG. 4 is a preferred embodiment of a controllable slew rate N-type MOS high-side drive circuit according to the present invention, in which M1 is a source follower structure that limits the control waveform of the charging voltage of the M0 gate.
  • this embodiment provides a controllable slew rate N-type MOS high-side drive circuit, which includes four sets of drains and sources connected in series with each other and electrically connected with their drains and gates.
  • the first field effect transistor component includes field effect transistors MN3, MN2, MN1, and MN0, and the drain of the field effect transistor MN3 Connect the bias current, the source of the field effect transistor MN0 is electrically connected to the source of MN4 and is connected to the OFF Control circuit component and the output terminal SOURCE, and the gate of the field effect transistor MN0 is connected to the gate of the field effect transistor MN4 ,
  • the drain of the field effect transistor MN4 is connected to the OFF Control circuit component, the OFF Control circuit component is connected to the ON Control circuit component and connected to the gate of the field effect transistor MO, and the source of the field effect transistor MO is externally connected
  • the output terminal DRAIN the drain of the field effect transistor MO is connected to the external output terminal SOURCE, the ON Control circuit
  • the preset Iin1 circuit is greater than the current of Iin2.
  • the ratio of all current mirrors is 1:1.
  • MN5 mirrors the Iin1 current of MN4, which is greater than the Iin2 current flowing into MN7.
  • MN5 works in the linear region, and MN9 is forced to work in the linear region to match the on-resistance of MN5.
  • MN5, MN6, MN8, MN9 constitute a current mirror, and Iout is the mirror current of Iin2;
  • the current flowing through MN7 finally flows through the self-biased MN6 tube.
  • the gate voltage of MN9 is raised to VGS_MN7+VGS_MN6, and the output current is only the same as the aspect ratio of MN8 and MN9.
  • the current is not limited by any input circuit
  • a controllable current is used to charge and discharge the gate of the switch.
  • the gate is opened to prevent voltage disturbance of the gate.
  • the OFF Control circuit components are used to achieve a working mode similar to that of ON Control.
  • a controllable current is used to charge and discharge the gate of the switch. When the discharge is completed, the gate is strongly turned off to prevent voltage disturbance of the gate.
  • the function of MN14 tube is to turn ON in OFF mode The charging current of Control; the function of the MN4 tube is to turn off the discharging current of OFF Control in the ON mode.
  • All MNx are NMOS devices isolated from the substrate, M0 is a high-side N-type MOS switch that needs to be driven, M1 is an ordinary high-voltage N-type MOS, without substrate isolation, and VHIGH is the power supply for the drive.
  • the leftmost MN0-MN3 provides a bias circuit, and M1 is a source follower structure to limit the charging voltage of the M0 grid.
  • the drain of the field effect transistor MN3 in the first field effect transistor component is electrically connected to the source of the field effect transistor MN2, and the drain of the field effect transistor MN2 is electrically connected to the source of the field effect transistor MN1 ,
  • the drain of the field effect transistor MN1 is electrically connected to the source of the field effect transistor MN0
  • the OFF Control circuit assembly includes seven groups of field effect transistors, which are field effect transistors MN10, MN11, MN12, MN13, MN14, MN15 and MN16,
  • the sources of the field effect transistors MN10, MN11, MN12, and MN16 are electrically connected to each other, the field effect transistors MN10, MN13, and MN14 are electrically connected to a power supply for bias current, and the field effect transistor MN10 is electrically connected to the field effect transistor.
  • the gate of the transistor MN11 is electrically connected, the drain of the field effect transistor MN11 is electrically connected to the gate of the field effect transistor MN12, and the source of the field effect transistor MN13 is electrically connected to the drain of the field effect transistor MN12. Electrically connected, the gate of the field effect transistor MN13 is electrically connected to the gate of the field effect transistor MN14 and is electrically connected to the drain of the field effect transistor MN4 and the gates of the field effect transistors MN16 and MN15.
  • the ON The Control circuit component includes field effect transistors MN4, MN5, MN6, MN9, MN8, and MN7.
  • the sources of the field effect transistors MN4, MN5, MN6, and MN9 are electrically connected to each other.
  • the drain is connected to the power bias current
  • the gate of the field effect transistor MN4 is electrically connected to the gate of the field effect transistor MN5
  • the drain of the field effect transistor MN4 is electrically connected to the gate of the field effect transistor MN4
  • the gate of the field effect transistor MN6 is electrically connected to the source of the field effect transistor MN5
  • the source of the field effect transistor MN7 is electrically connected to the drain of the field effect transistor MN6, and the field effect transistor MN7
  • the gate of is electrically connected to the gate of the field effect transistor MN8,
  • the drain of the field effect transistor MN8 is electrically connected to the source of the field effect transistor M1
  • the gate of MN3 is electrically connected to the field effect transistor M1
  • the gate of the field effect transistor MN9 is electrically connected to the gate of the field effect transistor MO.

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Abstract

本发明公开了一种可控压摆率N型MOS高边驱动电路，属于驱动电路技术领域，用可控电流对开关的栅极充放电，在充放电完成时，强开或者强关栅极以防止栅极的电压扰动，所有MNx为与衬底隔离的NMOS器件，M0为需驱动的高边N型MOS开关，VHIGH为驱动的电源。最左侧MN0-MN3提供了偏置电路，M1为源级跟随器结构，限制M0栅极的充电电压，实现高边驱动以及可控压摆率的功能。

Description

一种可控压摆率N型MOS高边驱动电路 技术领域
本发明涉及一种驱动电路，特别是涉及一种可控压摆率N型MOS高边驱动电路，属于驱动电路技术领域。
 背景技术
N型MOS高边的负载为感性负载时，当高边开关关闭，由于电感的续流，MOS开关的源级会被负载拉到低于地的电压，在某些应用中，以至于低至-20V，为防止MOS开关的驱动电路到衬底生PN结导通，驱动电路必须采用隔离结构的器件，在某些高压工艺中，只提供N型MOS的隔离器件用于负压的应用，为此设计一种可控压摆率全N型MOS高边驱动电路来解决上述问题。
 技术解决方案
本发明的主要目的是为了提供一种可控压摆率N型MOS高边驱动电路，用一段可控电流对开关的栅极充放电，在充放电完成时，强开或者强关栅极以防止栅极的电压扰动，所有MNx为与衬底隔离的NMOS器件，M0为需驱动的高边N型MOS开关，M1为普通高压N型MOS，无需衬底隔离，VHIGH为驱动的电源。最左侧MN0-MN3提供了偏置电路，M1为源级跟随器结构，限制M0栅极的充电电压，实现高边驱动以及可控压摆率的功能。
本发明的目的可以通过采用如下技术方案达到：
一种可控压摆率N型MOS高边驱动电路，包括四组漏极与源极相互串联并以自身漏极与栅极连接的第一场效应晶体管组件，所述第一场效应晶体管组件包括场效应晶体管MN3、MN2、MN1和MN0，所述场效应晶体管MN3的漏极接偏置电流，所述场效应晶体管MN0的源极连接MN4的源极并连接OFF Control电路组件以及输出端SOURCE，所述场效应晶体管MN0的栅极连接场效应晶体管MN4的栅极，所述场效应晶体管MN4的漏极连接所述OFF Control电路组件，所述OFF Control电路组件连接ON Control电路组件组件并连接场效应晶体管MO的栅极，所述场效应晶体管MO的源极外接输出端DRAIN，所述场效应晶体管MO的漏极连接外接输出端SOURCE，所述ON Control电路组件连接电源，所述ON Control电路组件还连接场效应晶体管M1的源极，且场效应晶体管M1的漏极连接电源。
优选的，所述第一场效应晶体管组件中场效应晶体管MN3的漏极连接场效应晶体管MN2的源极，场效应晶体管MN2的漏极连接场效应晶体管MN1的源极，场效应晶体管MN1的漏极连接场效应晶体管MN0的源极。
优选的，所述OFF Control电路组件包括七组场效应晶体管分别为场效应晶体管MN10、MN11、MN12、MN13、MN14、MN15和MN16，所述场效应晶体管MN10、MN11、MN12和MN16的源极互相连接，所述场效应晶体管MN10、MN13和MN14与偏置电流连接，所述场效应晶体管MN10与所述场效应晶体管MN11栅极连接。
优选的，所述场效应晶体管MN11的漏极与所述场效应晶体管MN12的栅极连接，所述场效应晶体管MN13的源极与所述场效应晶体管MN12的漏极连接，所述场效应晶体管MN13的栅极与所述场效应晶体管MN14的栅极连接且与场效应晶体管MN4的漏极以及场效应晶体管MN16和MN15的栅极连接。
优选的，所述ON Control电路组件包括场效应晶体管MN4、MN5、MN6、MN9、MN8和MN7，所述场效应晶体管MN4、MN5、MN6和MN9的源极互相连接，所述场效应晶体管MN4、MN7和MN9的漏极连接偏置电流。
优选的，所述场效应晶体管MN4的栅极与所述场效应晶体管MN5的栅极连接，且场效应晶体管MN4的漏极与场效应晶体管MN4的栅极连接，所述场效应晶体管MN6的栅极与所述场效应晶体管MN5的源极连接，所述场效应晶体管MN7的源极电性连接场效应晶体管MN6的漏极，所述场效应晶体管MN7的栅极与所述场效应晶体管MN8的栅极连接。
优选的，所述场效应晶体管MN8的漏极连接场效应晶体管M1的源极，所述MN3的栅极连接场效应晶体管M1的栅极。
优选的，所述场效应晶体管MN9的漏极连接场效应晶体管MO的栅极。
 有益效果
本发明的有益技术效果：
本发明提供的一种可控压摆率N型MOS高边驱动电路，用一段可控电流对开关的栅极充放电，在充放电完成时，强开或者强关栅极以防止栅极的电压扰动，所有MNx为与衬底隔离的NMOS器件，M0为需驱动的高边N型MOS开关，VHIGH为驱动的电源。最左侧MN0-MN3提供了偏置电路，M1为源级跟随器结构，限制M0栅极的充电电压，实现高边驱动以及可控压摆率的功能。
 附图说明
图1为按照本发明的一种可控压摆率N型MOS高边驱动电路的一优选实施例的整体电路图；
图2为按照本发明的一种可控压摆率N型MOS高边驱动电路的一优选实施例的ON Control电路组件电路图；
图3为按照本发明的一种可控压摆率N型MOS高边驱动电路的一优选实施例的Iin1与Iin2之间电流值对比波形图；
图4为按照本发明的一种可控压摆率N型MOS高边驱动电路的一优选实施例的M1为源级跟随器结构，限制M0栅极的充电电压控制波形图。
 本发明的实施方式
为使本领域技术人员更加清楚和明确本发明的技术方案，下面结合实施例及附图对本发明作进一步详细的描述，但本发明的实施方式不限于此。
如图1-图4所示，本实施例提供的一种可控压摆率N型MOS高边驱动电路，包括四组漏极与源极相互串联并以自身漏极与栅极电性连接的第一场效应晶体管组件，所述第一场效应晶体管组件包括场效应晶体管MN3、MN2、MN1和MN0，所述场效应晶体管MN3的漏极 连接偏置电流，所述场效应晶体管MN0的源极电性连接MN4的源极和连接有OFF Control电路组件以及输出端SOURCE，所述场效应晶体管MN0的栅极连接场效应晶体管MN4的栅极，所述场效应晶体管MN4的漏极连接所述OFF Control电路组件，所述OFF Control电路组件连接ON Control电路组件组件并连接场效应晶体管MO的栅极，所述场效应晶体管MO的源极外接输出端DRAIN，所述场效应晶体管MO的漏极连接外接输出端SOURCE，所述ON Control电路组件连接电源，所述ON Control电路组件还连接场效应晶体管M1的源极，且场效应晶体管M1的漏极连接电源。
状态一：
当Iin1与Iin2同时流入时，预设Iin1电路大于Iin2电流，为方便说明，假设所有电流镜的比例为1：1。MN5镜像MN4的Iin1电流，大于MN7流入的Iin2电流，MN5工作在线性区，MN9被强制工作在线性区以于MN5的导通电阻匹配。MN5，MN6，MN8，MN9构成电流镜，Iout即为Iin2的镜像电流；
状态二：
当Iin2维持而Iin1消失时，流过MN7的电流最终流过自偏的MN6管，对于MN8，MN9的栅极电压被抬高到VGS_MN7+VGS_MN6， 输出电流只同MN8，MN9本身的宽长比相关，电流没有被任何输入电路限制；
利用Iout的特性，用一段可控电流对开关的栅极充放电，在充电完成时，强开栅极以防止栅极的电压扰动。
当需要关闭M0时，采用OFF Control电路组件实现同ON Control相似的工作模式，用一段可控电流对开关的栅极充放电，在放电完成时，强关栅极以防止栅极的电压扰动。MN14管的作用是在OFF模式下关闭ON Control的充电电流；MN4管的作用是在ON模式下关闭OFF Control的放电电流。
所有MNx为与衬底隔离的NMOS器件，M0为需驱动的高边N型MOS开关，M1为普通高压N型MOS，无需衬底隔离，VHIGH为驱动的电源。最左侧MN0-MN3提供了偏置电路，M1为源级跟随器结构，限制M0栅极的充电电压。
在本实施例中，所述第一场效应晶体管组件中场效应晶体管MN3的漏极电性连接场效应晶体管MN2的源极，场效应晶体管MN2的漏极电性连接场效应晶体管MN1的源极，场效应晶体管MN1的漏极电性连接场效应晶体管MN0的源极，所述OFF Control电路组件包括七组场效应晶体管分别为场效应晶体管MN10、MN11、MN12、MN13、MN14、MN15和MN16，所述场效应晶体管MN10、MN11、MN12和MN16的源极互相电性连接，所述场效应晶体管MN10、MN13和MN14与电源电性连接偏置电流，所述场效应晶体管MN10与所述场效应晶体管MN11栅极电性连接，所述场效应晶体管MN11的漏极与所述场效应晶体管MN12的栅极电性连接，所述场效应晶体管MN13的源极与所述场效应晶体管MN12的漏极电性连接，所述场效应晶体管MN13的栅极与所述场效应晶体管MN14的栅极电性连接且与场效应晶体管MN4的漏极以及场效应晶体管MN16和MN15的栅极电性连接。
在本实施例中，所述ON Control电路组件包括场效应晶体管MN4、MN5、MN6、MN9、MN8和MN7，所述场效应晶体管MN4、MN5、MN6和MN9的源极互相电性连接，所述场效应晶体管MN4、MN7和MN9的漏极连接电源偏置电流，所述场效应晶体管MN4的栅极与所述场效应晶体管MN5的栅极电性连接，且场效应晶体管MN4的漏极与场效应晶体管MN4的栅极电性连接，所述场效应晶体管MN6的栅极与所述场效应晶体管MN5的源极电性连接，所述场效应晶体管MN7的源极电性连接场效应晶体管MN6的漏极，所述场效应晶体管MN7的栅极与所述场效应晶体管MN8的栅极电性连接，所述场效应晶体管MN8的漏极电性连接场效应晶体管M1的源极，所述MN3的栅极电性连接场效应晶体管M1的栅极，所述场效应晶体管MN9的漏极电性连接场效应晶体管MO的栅极。
以上所述，仅为本发明进一步的实施例，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明所公开的范围内，根据本发明的技术方案及其构思加以等同替换或改变，都属于本发明的保护范围。

Claims (8)

  1. 一种可控压摆率N型MOS高边驱动电路，其特征在于：包括四组漏极与源极相互串联并以自身漏极与栅极电性连接的第一场效应晶体管组件，所述第一场效应晶体管组件包括场效应晶体管MN3、MN2、MN1和MN0，所述场效应晶体管MN3的漏极连接偏置电流，所述场效应晶体管MN0的源极电性连接有场效应晶体管MN4的源极和电性连接有OFF Control（关闭控制）电路组件以及输出端SOURCE，所述场效应晶体管MN0的栅极电性连接场效应晶体管MN4的栅极，所述场效应晶体管MN4的漏极电性连接所述OFF Control电路组件，所述OFF Control电路组件电性连接ON Control（开启控制）电路组件组件并电性连接场效应晶体管MO的栅极，所述场效应晶体管MO的源极外接输出端DRAIN，所述场效应晶体管MO的漏极电性连接外接输出端SOURCE，所述ON Control电路组件电性连接电源，所述ON Control电路组件还通过电性连接场效应晶体管M1的源极，且场效应晶体管M1的漏极连接电源。
  2. 根据权利要求1所述的一种可控压摆率N型MOS高边驱动电路，其特征在于：所述第一场效应晶体管组件中场效应晶体管MN3的漏极电性连接场效应晶体管MN2的源极，场效应晶体管MN2的漏极电性连接场效应晶体管MN1的源极，场效应晶体管MN1的漏极电性连接场效应晶体管MN0的源极。
  3. 根据权利要求1所述的一种可控压摆率N型MOS高边驱动电路，其特征在于：所述OFF Control电路组件包括七组场效应晶体管分别为场效应晶体管MN10、MN11、MN12、MN13、MN14、MN15和MN16，所述场效应晶体管MN10、MN11、MN12和MN16的源极互相电性连接，所述场效应晶体管MN10、MN13和MN14与电源电性连接，所述场效应晶体管MN10与所述场效应晶体管MN11栅极电性连接。
  4. 根据权利要求3所述的一种可控压摆率N型MOS高边驱动电路，其特征在于：所述场效应晶体管MN11的漏极与所述场效应晶体管MN12的栅极电性连接，所述场效应晶体管MN13的源极与所述场效应晶体管MN12的漏极电性连接，所述场效应晶体管MN13的栅极与所述场效应晶体管MN14的栅极电性连接且与场效应晶体管MN4的漏极以及场效应晶体管MN16和MN15的栅极电性连接。
  5. 根据权利要求1所述的一种可控压摆率N型MOS高边驱动电路，其特征在于：所述ON Control电路组件包括场效应晶体管MN4、MN5、MN6、MN9、MN8和MN7，所述场效应晶体管MN4、MN5、MN6和MN9的源极互相电性连接，所述场效应晶体管MN4、MN7和MN9的漏极连接电源。
  6. 根据权利要求5所述的一种可控压摆率N型MOS高边驱动电路，其特征在于：所述场效应晶体管MN4的栅极与所述场效应晶体管MN5的栅极电性连接，且场效应晶体管MN4的漏极与场效应晶体管MN4的栅极电性连接，所述场效应晶体管MN6的栅极与所述场效应晶体管MN5的源极电性连接，所述场效应晶体管MN7的源极电性连接场效应晶体管MN6的漏极，所述场效应晶体管MN7的栅极与所述场效应晶体管MN8的栅极电性连接。
  7. 根据权利要求6所述的一种可控压摆率N型MOS高边驱动电路，其特征在于：所述场效应晶体管MN8的漏极电性连接场效应晶体管M1的源极，所述MN3的栅极电性连接场效应晶体管M1的栅极。
  8. 根据权利要求6所述的一种可控压摆率N型MOS高边驱动电路，其特征在于：所述场效应晶体管MN9的漏极电性连接场效应晶体管MO的栅极。
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