WO2021224982A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021224982A1
WO2021224982A1 PCT/JP2020/018638 JP2020018638W WO2021224982A1 WO 2021224982 A1 WO2021224982 A1 WO 2021224982A1 JP 2020018638 W JP2020018638 W JP 2020018638W WO 2021224982 A1 WO2021224982 A1 WO 2021224982A1
Authority
WO
WIPO (PCT)
Prior art keywords
coil
substrate
transmission
side substrate
receiving
Prior art date
Application number
PCT/JP2020/018638
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English (en)
French (fr)
Japanese (ja)
Inventor
雅俊 長谷川
Original Assignee
ウルトラメモリ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウルトラメモリ株式会社 filed Critical ウルトラメモリ株式会社
Priority to JP2022519874A priority Critical patent/JP7278016B2/ja
Priority to PCT/JP2020/018638 priority patent/WO2021224982A1/ja
Publication of WO2021224982A1 publication Critical patent/WO2021224982A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Definitions

  • the present invention relates to a semiconductor device.
  • RAM volatile memory
  • DRAM Dynamic Random Access Memory
  • logic chips arithmetic units
  • the capacity has been increased by miniaturizing the memory (memory cell array, memory chip) and increasing the number of cells in a plane.
  • this kind of large capacity has reached its limit due to the weakness to noise due to miniaturization and the increase in area.
  • Patent Document 1 when power is supplied from the primary coil to the secondary coil, the power supply loss is reduced by arranging the relay coil.
  • the relay coil of Patent Document 1 employs a mechanism for adjusting the resonance frequency in order to supply electric power by resonance. Therefore, the technique described in Patent Document 1 is not suitable for non-contact communication for transmitting signals of various frequencies.
  • Patent Document 2 discloses an electronic circuit in which three pairs of transmitting coils and receiving coils arranged on concentric circles are arranged coaxially in order. Then, in Patent Document 2, when a signal is transmitted from one transmitting coil to the other two receiving coils, one end of the other two transmitting coils is released, so that the other two transmitting coils interfere with communication. It suppresses doing. However, in Patent Document 2, it is not possible to increase the strength of the received signal.
  • An object of the present invention is to provide a semiconductor device capable of increasing the strength of a received signal.
  • the present invention is a semiconductor device including a plurality of semiconductor substrates to be laminated, wherein a transmission coil arranged on the transmission side substrate, which is one of the semiconductor substrates, and the semiconductor substrate different from the transmission side substrate are used.
  • An intermediate substrate which is at least one semiconductor substrate between a receiving coil arranged on a receiving side substrate and overlapping with the transmitting coil in a stacking direction and the transmitting side substrate and the receiving side substrate.
  • the present invention relates to a semiconductor device including an intermediate coil arranged at a position where the transmitting coil and the receiving coil overlap in a stacking direction, and both ends of which are electrically open.
  • the intermediate coil is a semiconductor substrate between the receiving side substrate and the transmitting side substrate, which is closer to the receiving side substrate than the intermediate point between the receiving side substrate and the transmitting side substrate. It is preferably placed in either.
  • a plurality of the intermediate coils are arranged on one intermediate substrate.
  • FIG. 1 It is a top view of the semiconductor substrate laminated on the semiconductor device which concerns on one Embodiment of this invention.
  • a cross-sectional view of the semiconductor device of one embodiment is shown.
  • a first embodiment of the semiconductor device of one embodiment is shown.
  • a second embodiment of the semiconductor device of one embodiment is shown.
  • the semiconductor device 1 is, for example, a member including a plurality of semiconductor substrates 10 to be laminated.
  • the semiconductor device 1 is, for example, a memory member having a memory chip (DRAM chip).
  • the semiconductor device 1 realizes non-contact communication between the laminated semiconductor substrates 10.
  • the semiconductor device 1 can improve the ease of manufacture and the degree of integration by, for example, performing communication using a magnetic field.
  • the semiconductor device 1 according to the following embodiment is intended to improve the communication strength in non-contact communication.
  • the semiconductor device 1 includes a plurality of semiconductor substrates 10, a transmission circuit 20, a transmission coil 30, a reception circuit 40, a reception coil 50, and an intermediate coil 60. Be prepared.
  • the semiconductor substrate 10 is, for example, a silicon substrate.
  • the semiconductor substrate 10 includes a wiring layer arranged on one surface.
  • five semiconductor substrates 10 are provided: a first substrate 11, a second substrate 12, a third substrate 13, a fourth substrate 14, and a fifth substrate 15.
  • the second substrate 12 and the third substrate 13 are adhered with the wiring layers 112 and 113 facing each other.
  • the fourth substrate 14 and the fifth substrate 15 are adhered with the wiring layers 114 and 115 facing each other.
  • the third substrate 13 and the fourth substrate 14 are adhered so that the surfaces opposite to the wiring layers 113 and 114 face each other.
  • the first substrate 11 and the second substrate 12 are adhered so that the surfaces opposite to the wiring layers 111 and 112 face each other.
  • the transmission coil 30 is a signal transmission coil arranged on the semiconductor substrate 10.
  • the transmission coil 30 is arranged on a transmission-side substrate, which is one semiconductor substrate 10.
  • the transmission coil 30 is arranged in the wiring layers 111 and 115 of the first substrate 11 and the fifth substrate 15. That is, the transmission coils 30a, 30c, and 30e of the first substrate 11 are arranged on the wiring layer 111 of the first substrate 11 which is the transmission side substrate. Further, the transmission coils 30b, 30d, and 30f of the fifth substrate 15 are arranged on the wiring layer 115 of the fifth substrate 15 which is the transmission side substrate.
  • the transmission coils 30a, 30c, 30e of the first substrate 11 and the transmission coils 30b, 30d, 30f of the fifth substrate 15 are arranged at positions where they do not overlap in the stacking direction D.
  • the transmission circuit 20 is, for example, an electronic circuit.
  • the transmission circuit 20 applies a transmission signal as an electric signal to the transmission coil.
  • the transmission circuit 20 generates a magnetic flux corresponding to the transmission signal in the transmission coil 30.
  • the receiving coil 50 is a signal receiving coil arranged on the semiconductor substrate 10.
  • the receiving coil 50 is arranged on a receiving side substrate, which is a semiconductor substrate 10 different from the transmitting side substrate. Further, the receiving coil 50 is arranged at a position where it overlaps with the transmitting coil 30 in the stacking direction D.
  • the receiving coil 50 is arranged in the wiring layers 111 and 115 of the first substrate 11 and the fifth substrate 15. That is, the receiving coils 50b, 50d, and 50f of the first substrate 11 are arranged on the wiring layer 111 of the first substrate 11 which is the receiving side substrate. Further, the receiving coils 50a, 50c, 50e of the fifth substrate 15 are arranged on the wiring layer 115 of the fifth substrate 15 which is the receiving side substrate.
  • the receiving coils 50a, 50c, 50e of the fifth substrate 15 are arranged at positions where they overlap with the transmitting coils 30a, 30c, 30e of the first substrate 11 in the stacking direction D.
  • the receiving coils 50b, 50d, 50f of the first substrate 11 are arranged at positions where they overlap with the transmitting coils 30b, 30d, 30f of the fifth substrate 15 in the stacking direction D.
  • the receiving circuit 40 is, for example, an electronic circuit.
  • the reception circuit 40 acquires a transmission signal received by the reception coil 50 as a reception signal.
  • the intermediate coil 60 is a coil in which both ends are electrically released.
  • the intermediate coil 60 is arranged on an intermediate substrate, which is at least one semiconductor substrate 10 between the transmitting side substrate and the receiving side substrate.
  • the intermediate coil 60 is arranged in the wiring layer of the intermediate substrate.
  • the intermediate coil 60 is arranged at least in the wiring layer 112 of the second substrate 12.
  • the intermediate coil 60 is arranged, for example, in the wiring layers 112 and 113 of the second substrate 12 and the third substrate 13.
  • the intermediate coil 60 is arranged at a position where it overlaps the transmitting coil 30 and the receiving coil 50 in the stacking direction D.
  • the intermediate coil 60c is arranged at a position where the transmission coil 30c of the first substrate 11 and the reception coil 50c of the fifth substrate 15 overlap in the stacking direction D.
  • the intermediate coil 60d is arranged at a position where the transmission coil 30d of the fifth substrate 15 and the reception coil 50d of the first substrate 11 overlap in the stacking direction D.
  • the intermediate coil 60e is arranged at a position where the transmission coil 30e of the first substrate 11 and the reception coil 50e of the fifth substrate 15 overlap in the stacking direction D.
  • the intermediate coil 60f is arranged at a position where the transmission coil 30f of the fifth substrate 15 and the reception coil 50f of the first substrate 11 overlap in the stacking direction D.
  • a plurality of intermediate coils 60 are arranged on one intermediate substrate.
  • the four intermediate coils 60c, 60d, 60e, 60f are arranged on the second substrate 12, for example.
  • the transmission circuit 20 applies an electric signal for transmission to the transmission coil 30 of the fifth substrate 15.
  • the transmission coil 30 converts an electric signal into a magnetic field.
  • the receiving coil 50 of the first substrate 11 generates an electric signal based on the magnetic field converted by the transmitting coil 30 of the fifth substrate 15.
  • the receiving circuit 40 receives the signal by acquiring the electric signal generated by the receiving coil 50 of the first substrate 11. As a result, one communication channel is formed.
  • the intermediate coil 60 in the intermediate coil 60 arranged on the second substrate 12 (and the third substrate 13), a transient minute current sufficient to charge its own parasitic capacitance flows with the start of transmission of the transmission signal. .. As a result, a reception voltage corresponding to the distance from the transmission coil 30 is generated at both ends of the intermediate coil 60. Subsequently, the current flowing due to the generated reception voltage changes in the opposite direction to the case of the closed loop (coil whose ends are not released). Therefore, the intermediate coil 60 generates a magnetic field in a direction that strengthens the change in the magnetic field of the transmission coil 30. As a result, the change in the magnetic field at the position of the receiving coil 50 is larger than that without the intermediate coil 60. That is, the voltage value of the received signal received by the receiving coil 50 can be made larger than that in the case where the intermediate coil 60 is not provided.
  • Example 1 Next, the first embodiment of the semiconductor device 1 in the present embodiment will be described with reference to FIGS. 2 and 3.
  • the signal transmitted from the transmission coil 30 arranged on the fifth substrate was received by the reception coil 50 arranged on the first substrate.
  • the transmission coil 30 and the reception coil 50 were set as follows.
  • Transmission coil 30 15 turns, diameter 70 ⁇ m, line width 1.4 ⁇ m, line spacing 0.3 ⁇ m
  • Receiving coil 50 30 turns, diameter 70 ⁇ m, line width 0.3 ⁇ m, line spacing 0.3 ⁇ m
  • the distance between the transmitting coil 30 and the receiving coil 50 was set to 40 ⁇ m.
  • the received signal is received in three modes: no intermediate coil 60, the intermediate coil 60 is arranged on the second substrate 12 (1), and the intermediate coil 60 is arranged on the 2nd substrate 12 and the 3rd substrate 13 (2).
  • the intermediate coil 60 was set as follows. Intermediate coils 60c, 60d (second substrate only): 25 turns, diameter 70 ⁇ m, line width 1.0 ⁇ m, line spacing 0.3 ⁇ m Intermediate coils 60e, 60f (second substrate and third substrate): 20 turns, diameter 56 ⁇ m, line width 1.0 ⁇ m, line spacing 0.3 ⁇ m
  • the voltage amplitude of the receiving coil 50 was increased by arranging the intermediate coil 60 regardless of whether the current of the transmitting coil 30 was 360 ⁇ A, 500 ⁇ A, 640 ⁇ A, or 730 ⁇ A. rice field. Further, it was found that the voltage amplitude of the receiving coil 50 can be made larger by arranging a plurality of intermediate coils 60.
  • the numerical value shown together with the voltage waveform of the receiving coil 50 is the amplitude on the high side / the amplitude on the low side, and the unit is mV.
  • Example 2 a second embodiment of the semiconductor device 1 in the present embodiment will be described with reference to FIGS. 2 and 4.
  • the signal transmitted from the transmission coil 30 arranged on the first substrate was received by the reception coil 50 arranged on the fifth substrate 15.
  • the transmission coil 30 and the reception coil 50 were set in the same manner as in the first embodiment.
  • the distance between the transmission coil 30 and the reception coil 50 was also set in the same manner as in the first embodiment.
  • the intermediate coil 60 was also set in the same manner as in the first embodiment.
  • the voltage amplitude of the receiving coil 50 was increased by arranging the intermediate coil 60 regardless of whether the current of the transmitting coil 30 was 360 ⁇ A, 500 ⁇ A, 640 ⁇ A, or 730 ⁇ A. rice field. Further, it was found that the voltage amplitude of the receiving coil 50 can be made larger by arranging a plurality of intermediate coils 60. That is, it was found that the voltage amplitude of the receiving coil 50 can be increased in the second embodiment as in the first embodiment.
  • the numerical value shown together with the voltage waveform of the receiving coil 50 is the amplitude on the high side / the amplitude on the low side, and the unit is mV.
  • a semiconductor device 1 including a plurality of semiconductor substrates 10 to be laminated, wherein a transmission coil 30 arranged on a transmission side substrate, which is one semiconductor substrate 10, and a semiconductor substrate 10 different from the transmission side substrate 10
  • the substrate includes an intermediate coil 60 arranged at a position where the transmitting coil 30 and the receiving coil 50 overlap in the stacking direction D, and the intermediate coils 60 having both ends electrically released.
  • the magnetic field generated by the transmission coil 30 generates a magnetic field in the direction of strengthening the signal by the intermediate coil 60. Therefore, the receiving coil can receive the magnetic field strengthened by the intermediate coil 60 and can increase the strength of the received signal as compared with the case where the intermediate coil 60 is not provided.
  • a plurality of intermediate coils 60 are arranged on one intermediate substrate. Thereby, on one intermediate substrate, the intermediate coil 60 can be arranged for each communication channel formed by one transmission coil 30 and one reception coil 50. Therefore, the range of design can be widened, and the variation of the semiconductor substrate 10 can be widened.
  • the intermediate coil 60 is a semiconductor substrate 10 of the semiconductor substrate 10 between the receiving side substrate and the transmitting side substrate, which is closer to the receiving side substrate than the intermediate point between the receiving side substrate and the transmitting side substrate. It may be placed in either.
  • the value of the transient current that charges the parasitic capacitance of the intermediate coil 60 is smaller than that of arranging the intermediate coil 60 on the semiconductor substrate 10 close to the transmitting side substrate, so that the ringing noise generated by this change in current is eliminated. It can be relatively suppressed. Therefore, improvement in communication quality can be expected.
  • the number of intermediate substrates in the stacking direction D is not limited to three.
  • the number of intermediate substrates is not limited as long as communication is possible between the transmission coil 30 and the reception coil 50.
  • the number of intermediate coils 60 in the stacking direction D is set to 1 or 2, but the number is not limited to this. Three or more intermediate coils 60 may be arranged. Further, a plurality of intermediate coils 60 may be arranged at overlapping positions in the stacking direction D in the same intermediate substrate.
  • a communication channel in which the intermediate coil 60 is not provided, a communication channel in which one is provided, and a communication channel in which a plurality of intermediate coils 60 are provided may be arranged so as to coexist.
  • the semiconductor device 1 can be flexibly configured according to the communication distance and cost of the transmission coil 30 and the reception coil 50, the diameter or the number of turns of the transmission coil 30 and the reception coil 50 that can be arranged. ..

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Near-Field Transmission Systems (AREA)
PCT/JP2020/018638 2020-05-08 2020-05-08 半導体装置 WO2021224982A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2022519874A JP7278016B2 (ja) 2020-05-08 2020-05-08 半導体装置
PCT/JP2020/018638 WO2021224982A1 (ja) 2020-05-08 2020-05-08 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/018638 WO2021224982A1 (ja) 2020-05-08 2020-05-08 半導体装置

Publications (1)

Publication Number Publication Date
WO2021224982A1 true WO2021224982A1 (ja) 2021-11-11

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PCT/JP2020/018638 WO2021224982A1 (ja) 2020-05-08 2020-05-08 半導体装置

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JP (1) JP7278016B2 (zh)
WO (1) WO2021224982A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109112A (ja) * 2008-10-30 2010-05-13 Hitachi Ltd 半導体集積回路
JP2012169513A (ja) * 2011-02-16 2012-09-06 Keio Gijuku 電子回路
WO2017010012A1 (ja) * 2015-07-16 2017-01-19 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ 半導体装置
WO2017126018A1 (ja) * 2016-01-18 2017-07-27 ウルトラメモリ株式会社 半導体装置
WO2017138106A1 (ja) * 2016-02-10 2017-08-17 ウルトラメモリ株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109112A (ja) * 2008-10-30 2010-05-13 Hitachi Ltd 半導体集積回路
JP2012169513A (ja) * 2011-02-16 2012-09-06 Keio Gijuku 電子回路
WO2017010012A1 (ja) * 2015-07-16 2017-01-19 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ 半導体装置
WO2017126018A1 (ja) * 2016-01-18 2017-07-27 ウルトラメモリ株式会社 半導体装置
WO2017138106A1 (ja) * 2016-02-10 2017-08-17 ウルトラメモリ株式会社 半導体装置

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JP7278016B2 (ja) 2023-05-19

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